amend! [RISCV] GPR Pairs for Inline Asm using Pr

lenary · lenary · commit a7dd51989e0c · 2024-11-14T04:55:48.000-08:00
[RISCV] GPR Pairs for Inline Asm using `R` This patch adds support for getting even-odd general purpose register pairs into and out of inline assembly using the `R` constraint as proposed in riscv-non-isa/riscv-c-api-doc#92 There are a few different pieces to this patch, each of which need their own explanation. - Renames the Register Class used for f64 values on rv32i_zdinx from `GPRPair*` to `GPRF64Pair*`. These register classes are kept broadly unmodified, as their primary value type is used for type inference over selection patterns. This rename affects quite a lot of files. - Adds new `GPRPair*` register classes which will be used for `R` constraints and for instructions that need an even-odd GPR pair. This new type is used for `amocas.d.*`(rv32) and `amocas.q.*`(rv64) in Zacas, instead of the `GPRF64Pair` class being used before. - Marks the new `GPRPair` class legal as for holding a `MVT::Untyped`. Two new RISCVISD node types are added for creating and destructing a pair - `BuildGPRPair` and `SplitGPRPair`, and are introduced when bitcasting to/from the pair type and `untyped`. - Adds functionality to `splitValueIntoRegisterParts` and `joinRegisterPartsIntoValue` to handle changing `i<2*xlen>` MVTs into `untyped` pairs. - Adds an override for `getNumRegisters` to ensure that `i<2*xlen>` values, when going to/from inline assembly, only allocate one (pair) register (they would otherwise allocate two). This is due to a bug in SelectionDAGBuilder.cpp which other backends also work around. - Ensures that Clang understands that `R` is a valid inline assembly constraint. - Adds Conditions to the GPRF64Pair-related changes to `LowerOperation` and `ReplaceNodeResults` which match when BITCAST for the relevant types should be handled in a custom manner. - This also allows `R` to be used for `f64` types on `rv32_zdinx` architectures, where doubles are stored in a GPR pair.
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
@@ -108,14 +108,10 @@ bool RISCVTargetInfo::validateAsmConstraint(
       return true;
     }
     return false;
-  case 'P':
-    // An even-odd register pair - GPR
-    if (Name[1] == 'r') {
-      Info.setAllowsRegister();
-      Name += 1;
-      return true;
-    }
-    return false;
+  case 'R':
+    // An even-odd GPR pair
+    Info.setAllowsRegister();
+    return true;
   case 'v':
     // A vector register.
     if (Name[1] == 'r' || Name[1] == 'd' || Name[1] == 'm') {
@@ -130,9 +126,8 @@ bool RISCVTargetInfo::validateAsmConstraint(
 std::string RISCVTargetInfo::convertConstraint(const char *&Constraint) const {
   std::string R;
   switch (*Constraint) {
-  // c*, P*, and v* are all two-letter constraints on RISC-V.
+  // c* and v* are two-letter constraints on RISC-V.
   case 'c':
-  case 'P':
   case 'v':
     R = std::string("^") + std::string(Constraint, 2);
     Constraint += 1;
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm.c b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
@@ -38,11 +38,11 @@ typedef long long double_xlen_t;
 #elif __riscv_xlen == 64
 typedef __int128_t double_xlen_t;
 #endif
-double_xlen_t test_Pr_wide_scalar(double_xlen_t p) {
-// CHECK-LABEL: define{{.*}} {{i128|i64}} @test_Pr_wide_scalar(
-// CHECK: call {{i128|i64}} asm sideeffect "", "=^Pr,^Pr"({{i128|i64}} %{{.*}})
+double_xlen_t test_R_wide_scalar(double_xlen_t p) {
+// CHECK-LABEL: define{{.*}} {{i128|i64}} @test_R_wide_scalar(
+// CHECK: call {{i128|i64}} asm sideeffect "", "=R,R"({{i128|i64}} %{{.*}})
   double_xlen_t ret;
-  asm volatile("" : "=Pr"(ret) : "Pr"(p));
+  asm volatile("" : "=R"(ret) : "R"(p));
   return ret;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20458,6 +20458,7 @@ RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
     default:
       break;
     case 'f':
+    case 'R':
       return C_RegisterClass;
     case 'I':
     case 'J':
@@ -20474,8 +20475,6 @@ RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
       return C_RegisterClass;
     if (Constraint == "cr" || Constraint == "cf")
       return C_RegisterClass;
-    if (Constraint == "Pr")
-      return C_RegisterClass;
   }
   return TargetLowering::getConstraintType(Constraint);
 }
@@ -20519,6 +20518,10 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
           return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
       }
       break;
+    case 'R':
+      if (VT == MVT::f64 && !Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())
+        return std::make_pair(0U, &RISCV::GPRF64PairCRegClass);
+      return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
     default:
       break;
     }
@@ -20578,10 +20581,6 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       if (Subtarget.hasStdExtZdinx() && Subtarget.is64Bit())
         return std::make_pair(0U, &RISCV::GPRCRegClass);
     }
-  } else if (Constraint == "Pr") {
-    if (VT == MVT::f64 && !Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())
-      return std::make_pair(0U, &RISCV::GPRF64PairCRegClass);
-    return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
   }
 
   // Clang will correctly decode the usage of register name aliases into their
diff --git a/llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll b/llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll
@@ -12,7 +12,7 @@ define i64 @test_Pr_wide_scalar_simple(i64 noundef %0) nounwind {
 ; CHECK-NEXT:    mv a1, a3
 ; CHECK-NEXT:    ret
 entry:
-  %1 = call i64 asm sideeffect "/* $0 <- $1 */", "=&^Pr,^Pr"(i64 %0)
+  %1 = call i64 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i64 %0)
   ret i64 %1
 }
 
@@ -29,7 +29,7 @@ entry:
   %1 = zext i32 %0 to i64
   %2 = shl i64 %1, 32
   %3 = or i64 %1, %2
-  %4 = call i64 asm sideeffect "/* $0 <- $1 */", "=&^Pr,^Pr"(i64 %3)
+  %4 = call i64 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i64 %3)
   %5 = trunc i64 %4 to i32
   %6 = lshr i64 %4, 32
   %7 = trunc i64 %6 to i32
@@ -63,7 +63,7 @@ entry:
   store i64 %1, ptr %3, align 8
   %4 = load ptr, ptr %2, align 4
   %5 = load i64, ptr %3, align 8
-  %6 = call { ptr, i64 } asm sideeffect "/* $0; $1 */", "=r,=^Pr,0,1"(ptr %4, i64 %5)
+  %6 = call { ptr, i64 } asm sideeffect "/* $0; $1 */", "=r,=R,0,1"(ptr %4, i64 %5)
   %7 = extractvalue { ptr, i64} %6, 0
   %8 = extractvalue { ptr, i64 } %6, 1
   store ptr %7, ptr %2, align 4
diff --git a/llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll b/llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll
@@ -2,8 +2,8 @@
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
-define i128 @test_Pr_wide_scalar_simple(i128 noundef %0) nounwind {
-; CHECK-LABEL: test_Pr_wide_scalar_simple:
+define i128 @test_R_wide_scalar_simple(i128 noundef %0) nounwind {
+; CHECK-LABEL: test_R_wide_scalar_simple:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    # a2 <- a0
@@ -12,12 +12,12 @@ define i128 @test_Pr_wide_scalar_simple(i128 noundef %0) nounwind {
 ; CHECK-NEXT:    mv a1, a3
 ; CHECK-NEXT:    ret
 entry:
-  %1 = call i128 asm sideeffect "/* $0 <- $1 */", "=&^Pr,^Pr"(i128 %0)
+  %1 = call i128 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i128 %0)
   ret i128 %1
 }
 
-define i64 @test_Pr_wide_scalar_with_ops(i64 noundef %0) nounwind {
-; CHECK-LABEL: test_Pr_wide_scalar_with_ops:
+define i64 @test_R_wide_scalar_with_ops(i64 noundef %0) nounwind {
+; CHECK-LABEL: test_R_wide_scalar_with_ops:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a1, a0
 ; CHECK-NEXT:    #APP
@@ -29,16 +29,16 @@ entry:
   %1 = zext i64 %0 to i128
   %2 = shl i128 %1, 64
   %3 = or i128 %1, %2
-  %4 = call i128 asm sideeffect "/* $0 <- $1 */", "=&^Pr,^Pr"(i128 %3)
+  %4 = call i128 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i128 %3)
   %5 = trunc i128 %4 to i64
   %6 = lshr i128 %4, 64
   %7 = trunc i128 %6 to i64
   %8 = or i64 %5, %7
   ret i64 %8
 }
 
-define i128 @test_Pr_wide_scalar_inout(ptr %0, i128 noundef %1) nounwind {
-; CHECK-LABEL: test_Pr_wide_scalar_inout:
+define i128 @test_R_wide_scalar_inout(ptr %0, i128 noundef %1) nounwind {
+; CHECK-LABEL: test_R_wide_scalar_inout:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi sp, sp, -32
 ; CHECK-NEXT:    mv a3, a2
@@ -63,7 +63,7 @@ entry:
   store i128 %1, ptr %3, align 16
   %4 = load ptr, ptr %2, align 8
   %5 = load i128, ptr %3, align 16
-  %6 = call { ptr, i128 } asm sideeffect "/* $0; $1 */", "=r,=^Pr,0,1"(ptr %4, i128 %5)
+  %6 = call { ptr, i128 } asm sideeffect "/* $0; $1 */", "=r,=R,0,1"(ptr %4, i128 %5)
   %7 = extractvalue { ptr, i128} %6, 0
   %8 = extractvalue { ptr, i128 } %6, 1
   store ptr %7, ptr %2, align 8
diff --git a/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32 -mattr=+zhinx | FileCheck %s
 
-;; These tests cover the use of `r` and `cr` constraints for floating point values on rv32.
+;; These tests cover the use of `r`, `R`, and `cr` constraints for floating point values on rv32.
 ;;
 ;; In particular, there is significant complexity around using paired GPRs for double values on rv32.
 
@@ -26,8 +26,8 @@ entry:
   ret void
 }
 
-define dso_local void @zdinx_asm_Pr(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
-; CHECK-LABEL: zdinx_asm_Pr:
+define dso_local void @zdinx_asm_R(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
+; CHECK-LABEL: zdinx_asm_R:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
@@ -47,7 +47,7 @@ define dso_local void @zdinx_asm_Pr(ptr nocapture noundef writeonly %a, double n
 ; CHECK-NEXT:    ret
 entry:
   %arrayidx = getelementptr inbounds double, ptr %a, i32 1
-  %0 = tail call double asm "fsgnjx.d $0, $1, $2", "=^Pr,^Pr,^Pr"(double %b, double %c)
+  %0 = tail call double asm "fsgnjx.d $0, $1, $2", "=R,R,R"(double %b, double %c)
   store double %0, ptr %arrayidx, align 8
   ret void
 }
