Commit bb9500f
[RISCV] TableGen RISC-V ISD Nodes
This commit moves RISC-V to auto-generate its target-specific SDNode
types. The biggest change is that SDNodes can now be validated against
their expected type profiles, and that we don't need to edit several
different files when declaring a new one.
This takes Sergei's work in llvm#119709 and "finishes" it - by moving the
final five RISCVISD opcodes into tablegen (including defining their
types), and by ensuring the tablegen has expected closing scope
comments.
Only one opcode is not currently verifying on the in-tree tests:
PROBED_ALLOCA, which I cannot make head or tail of what it should be
doing, so I have just ensured it skips verification for the moment (as
in Sergei's patch).
Co-authored-by: Sergei Barannikov <[email protected]>1 parent 692f832 commit bb9500f
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lines changed- llvm/lib/Target/RISCV
23 files changed
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