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| 1 | +#include "stm32.h" |
| 2 | +#include "codal_target_hal.h" |
| 3 | +#include "CodalDmesg.h" |
| 4 | + |
| 5 | +void target_init(); |
| 6 | + |
| 7 | +extern "C" void cpu_init() |
| 8 | +{ |
| 9 | + SystemCoreClockUpdate(); |
| 10 | + |
| 11 | + target_init(); |
| 12 | + |
| 13 | + RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| 14 | + RCC_OscInitTypeDef RCC_OscInitStruct; |
| 15 | + |
| 16 | + /* Enable Power Control clock */ |
| 17 | + __HAL_RCC_PWR_CLK_ENABLE(); |
| 18 | + |
| 19 | + /* The voltage scaling allows optimizing the power consumption when the device is |
| 20 | + clocked below the maximum system frequency, to update the voltage scaling value |
| 21 | + regarding system frequency refer to product datasheet. */ |
| 22 | + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); |
| 23 | + |
| 24 | + /* Enable HSE Oscillator and activate PLL with HSE as source */ |
| 25 | + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| 26 | + RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
| 27 | + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| 28 | + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| 29 | + |
| 30 | + uint32_t pllm = HSE_VALUE / 1000000; |
| 31 | + |
| 32 | + CODAL_ASSERT(pllm >= 4); |
| 33 | + CODAL_ASSERT(pllm <= 25); |
| 34 | + CODAL_ASSERT(pllm * 1000000 == HSE_VALUE); |
| 35 | + |
| 36 | + RCC_OscInitStruct.PLL.PLLM = pllm; |
| 37 | + RCC_OscInitStruct.PLL.PLLN = 336; |
| 38 | + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; |
| 39 | + RCC_OscInitStruct.PLL.PLLQ = 7; |
| 40 | + HAL_RCC_OscConfig(&RCC_OscInitStruct); |
| 41 | + |
| 42 | + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 |
| 43 | + clocks dividers */ |
| 44 | + RCC_ClkInitStruct.ClockType = |
| 45 | + (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| 46 | + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| 47 | + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| 48 | + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; |
| 49 | + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; |
| 50 | + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); |
| 51 | + |
| 52 | + SystemCoreClockUpdate(); |
| 53 | + |
| 54 | + __HAL_RCC_TIM5_CLK_ENABLE(); |
| 55 | + |
| 56 | + // enable backup registers (for reboot into bootloader or into app) |
| 57 | + PWR->CR |= PWR_CR_DBP; |
| 58 | + RCC->BDCR |= RCC_BDCR_RTCEN; |
| 59 | +} |
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