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OmerMajNitionOmerMajNition
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gradually moving towards unified wiring function call that dumps the ports in case the width don't match
1 parent 4ea3411 commit 5058c3c

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7 files changed

+128
-213
lines changed

7 files changed

+128
-213
lines changed

‎include/reactor-sdk/OutputPort.hh‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,11 @@ class Output : public reactor::Output<T> {
6060
origin.connect(std::move(other_bank_ports));
6161
}
6262

63+
template <typename OtherReactorType>
64+
void operator>>(ReactorBankInputPortOffset<OtherReactorType, T> &&other_bank_ports) {
65+
origin.connect_fanout(std::move(other_bank_ports));
66+
}
67+
6368
private:
6469
Output& origin;
6570
};
@@ -78,6 +83,9 @@ class Output : public reactor::Output<T> {
7883
template <typename ReactorType>
7984
void connect(ReactorBankInputPortOffset<ReactorType, T> &&other_bank_ports);
8085

86+
template <typename ReactorType>
87+
void connect_fanout(ReactorBankInputPortOffset<ReactorType, T> &&other_bank_ports);
88+
8189
public:
8290
using value_type = T;
8391
Output(const std::string& name, reactor::Reactor* container)

‎include/reactor-sdk/impl/Connection.hh‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -93,13 +93,13 @@ void connect_fanout_(std::set<reactor::Port<T>*> &left_ports, std::set<reactor::
9393
if (left_ports.size() < right_ports.size()) {
9494
reactor::log::Warn() << "There are more right ports (" << right_ports.size() << ") than left ports (" << left_ports.size() << ")";
9595
display_ (left_ports, right_ports);
96+
reactor::log::Warn() << "Fanning out left port to all right ports";
9697
} else if (left_ports.size() > right_ports.size()) {
9798
reactor::log::Warn() << "There are more left ports (" << left_ports.size() << ") than right ports (" << right_ports.size() << ")";
9899
display_ (left_ports, right_ports);
100+
reactor::log::Warn() << "Fanning out left port to all right ports";
99101
}
100102

101-
reactor::log::Warn() << "Fanning out left port to all right ports";
102-
103103
auto left_port_itr = left_ports.begin();
104104
for (auto *right_port : right_ports) {
105105
(*left_port_itr)->environment()->draw_connection((*left_port_itr), right_port, reactor::ConnectionProperties{});

‎include/reactor-sdk/impl/InputMultiport_wiring_impl.hh‎

Lines changed: 20 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,38 @@
11
#pragma once
22

3+
#include "Connection.hh"
4+
35
namespace sdk
46
{
57
template <typename T>
68
void MultiportInput<T>::connect(Input<T>& input) {
7-
if (n_inputs > 1) {
8-
reactor::log::Warn() << "There are more left ports than right ports. "
9-
<< "Not all ports will be connected!";
10-
}
9+
std::set<reactor::Port<T>*> left_ports;
10+
std::set<reactor::Port<T>*> right_ports;
11+
bool result = false;
1112
for (auto& output_port : *this) {
12-
output_port.environment()->draw_connection(output_port, input, reactor::ConnectionProperties{});
13-
break;
13+
result = left_ports.insert(&output_port).second;
14+
reactor_assert(result);
1415
}
16+
result = right_ports.insert(&input).second;
17+
reactor_assert(result);
18+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
1519
}
1620

1721
template <typename T>
1822
void MultiportInput<T>::connect(MultiportInput<T>& input) {
19-
auto input_itr = input.begin();
20-
21-
if (n_inputs < input.get_nports()) {
22-
reactor::log::Warn() << "There are more right ports than left ports. "
23-
<< "Not all ports will be connected!";
24-
} else if (n_inputs > input.get_nports()) {
25-
reactor::log::Warn() << "There are more left ports than right ports. "
26-
<< "Not all ports will be connected!";
23+
std::set<reactor::Port<T>*> left_ports;
24+
std::set<reactor::Port<T>*> right_ports;
25+
bool result = false;
26+
for (auto& left_port : *this) {
27+
result = left_ports.insert(&left_port).second;
28+
reactor_assert(result);
2729
}
2830

29-
for (auto& output_port : *this) {
30-
output_port.environment()->draw_connection(output_port, *input_itr, reactor::ConnectionProperties{});
31-
++input_itr;
32-
if (input_itr == input.end())
33-
{
34-
break;
35-
}
31+
for (auto& right_port : input) {
32+
result = right_ports.insert(&right_port).second;
33+
reactor_assert(result);
3634
}
35+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
3736
}
3837

3938
} // namespace sdk

‎include/reactor-sdk/impl/InputPort_wiring_impl.hh‎

Lines changed: 8 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -18,32 +18,20 @@ void Input<T>::connect(Input<T>& input) {
1818

1919
template <typename T>
2020
void Input<T>::connect(MultiportInput<T>& input) {
21-
auto input_itr = input.begin();
22-
23-
if (1 < input.get_nports()) {
24-
reactor::log::Warn() << "There are more right ports than left ports, not all ports would be connected";
25-
}
21+
std::set<reactor::Port<T>*> left_ports;
22+
std::set<reactor::Port<T>*> right_ports;
23+
bool result = left_ports.insert(this).second;
24+
reactor_assert(result);
2625

27-
if (input_itr != input.end())
28-
{
29-
this->environment()->draw_connection(*this, *input_itr, reactor::ConnectionProperties{});
26+
for (auto& right_port : input) {
27+
result = right_ports.insert(&right_port).second;
28+
reactor_assert(result);
3029
}
30+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
3131
}
3232

3333
template <typename T>
3434
void Input<T>::connect_fanout(MultiportInput<T>& input) {
35-
// auto input_itr = input.begin();
36-
37-
// if (1 < input.get_nports()) {
38-
// reactor::log::Warn() << "Fanning out input to all right output ports";
39-
// }
40-
41-
// while (input_itr != input.end())
42-
// {
43-
// this->environment()->draw_connection(*this, *input_itr, reactor::ConnectionProperties{});
44-
// ++input_itr;
45-
// }
46-
4735
std::set<reactor::Port<T>*> left_ports;
4836
std::set<reactor::Port<T>*> right_ports;
4937
bool result = left_ports.insert(this).second;

‎include/reactor-sdk/impl/OutputMultiport_wiring_impl.hh‎

Lines changed: 20 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -29,46 +29,36 @@ void MultiportOutput<T>::connect(Output<T>& input) {
2929

3030
template <typename T>
3131
void MultiportOutput<T>::connect(MultiportInput<T>& input) {
32-
auto input_itr = input.begin();
33-
34-
if (n_inputs < input.get_nports()) {
35-
reactor::log::Warn() << "There are more right ports than left ports. "
36-
<< "Not all ports will be connected!";
37-
} else if (n_inputs > input.get_nports()) {
38-
reactor::log::Warn() << "There are more left ports than right ports. "
39-
<< "Not all ports will be connected!";
32+
std::set<reactor::Port<T>*> left_ports;
33+
std::set<reactor::Port<T>*> right_ports;
34+
bool result = false;
35+
for (auto& left_port : *this) {
36+
result = left_ports.insert(&left_port).second;
37+
reactor_assert(result);
4038
}
4139

42-
for (auto& output_port : *this) {
43-
output_port.environment()->draw_connection(output_port, *input_itr, reactor::ConnectionProperties{});
44-
++input_itr;
45-
if (input_itr == input.end())
46-
{
47-
break;
48-
}
40+
for (auto& right_port : input) {
41+
result = right_ports.insert(&right_port).second;
42+
reactor_assert(result);
4943
}
44+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
5045
}
5146

5247
template <typename T>
5348
void MultiportOutput<T>::connect(MultiportOutput<T>& input) {
54-
auto input_itr = input.begin();
55-
56-
if (n_inputs < input.get_nports()) {
57-
reactor::log::Warn() << "There are more right ports than left ports. "
58-
<< "Not all ports will be connected!";
59-
} else if (n_inputs > input.get_nports()) {
60-
reactor::log::Warn() << "There are more left ports than right ports. "
61-
<< "Not all ports will be connected!";
49+
std::set<reactor::Port<T>*> left_ports;
50+
std::set<reactor::Port<T>*> right_ports;
51+
bool result = false;
52+
for (auto& left_port : *this) {
53+
result = left_ports.insert(&left_port).second;
54+
reactor_assert(result);
6255
}
6356

64-
for (auto& output_port : *this) {
65-
output_port.environment()->draw_connection(output_port, *input_itr, reactor::ConnectionProperties{});
66-
++input_itr;
67-
if (input_itr == input.end())
68-
{
69-
break;
70-
}
57+
for (auto& right_port : input) {
58+
result = right_ports.insert(&right_port).second;
59+
reactor_assert(result);
7160
}
61+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
7262
}
7363

7464
template <typename T>
@@ -120,27 +110,6 @@ void MultiportOutput<T>::connect(ReactorBankInputPort<OtherReactorType, T> &&oth
120110
template <typename T>
121111
template <typename OtherReactorType>
122112
void MultiportOutput<T>::connect(ReactorBankInputPortOffset<OtherReactorType, T> &&other_bank_ports) {
123-
// auto reactor_itr = other_bank_ports.begin();
124-
125-
// if (n_inputs < other_bank_ports.size()) {
126-
// reactor::log::Warn() << "There are more right ports than left ports. "
127-
// << "Not all ports will be connected!";
128-
// } else if (n_inputs > other_bank_ports.size()) {
129-
// reactor::log::Warn() << "There are more left ports than right ports. "
130-
// << "Not all ports will be connected!";
131-
// }
132-
// for (auto& output_port : *this) {
133-
// auto *reactor = (*reactor_itr).get();
134-
// char* reactor_base = reinterpret_cast<char*>(reactor);
135-
// Input<T>* port = reinterpret_cast<Input<T>*>(reactor_base + other_bank_ports.get_offset());
136-
// output_port.environment()->draw_connection(output_port, *port, reactor::ConnectionProperties{});
137-
// ++reactor_itr;
138-
// if (reactor_itr == other_bank_ports.end())
139-
// {
140-
// break;
141-
// }
142-
// }
143-
144113
std::set<reactor::Port<T>*> left_ports;
145114
std::set<reactor::Port<T>*> right_ports;
146115
bool result;

‎include/reactor-sdk/impl/OutputPort_wiring_impl.hh‎

Lines changed: 48 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -18,40 +18,24 @@ void Output<T>::connect(Output<T>& input) {
1818
template <typename T>
1919
void Output<T>::connect(MultiportInput<T>& input) {
2020
if (is_accumulated) {
21-
auto input_itr = input.begin();
22-
23-
if (accumulated.size() < input.get_nports()) {
24-
reactor::log::Warn() << "There are more right ports than left ports. "
25-
<< "Not all ports will be connected!";
26-
} else if (accumulated.size() > input.get_nports()) {
27-
reactor::log::Warn() << "There are more left ports than right ports. "
28-
<< "Not all ports will be connected!";
21+
std::set<reactor::Port<T>*> left_ports;
22+
std::set<reactor::Port<T>*> right_ports;
23+
bool result = false;
24+
result = left_ports.insert(this).second;
25+
reactor_assert(result);
26+
for (auto *l_port : accumulated) {
27+
result = left_ports.insert(l_port).second;
28+
reactor_assert(result);
2929
}
3030

31-
this->environment()->draw_connection(*this, *input_itr, reactor::ConnectionProperties{});
32-
++input_itr;
33-
34-
for (auto *l_port : accumulated) {
35-
if (input_itr != input.end()) {
36-
break;
37-
}
38-
this->environment()->draw_connection(*l_port, *input_itr, reactor::ConnectionProperties{});
39-
++input_itr;
31+
for (auto& right_port : input) {
32+
result = right_ports.insert(&right_port).second;
33+
reactor_assert(result);
4034
}
35+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
4136
is_accumulated = false;
4237
accumulated.clear();
4338
} else {
44-
// auto input_itr = input.begin();
45-
46-
// if (1 < input.get_nports()) {
47-
// reactor::log::Warn() << "There are more right ports than left ports. "
48-
// << "Not all ports will be connected!";
49-
// }
50-
51-
// if (input_itr != input.end())
52-
// {
53-
// this->environment()->draw_connection(*this, *input_itr, reactor::ConnectionProperties{});
54-
// }
5539
std::set<reactor::Port<T>*> left_ports;
5640
std::set<reactor::Port<T>*> right_ports;
5741
bool result = left_ports.insert(this).second;
@@ -67,41 +51,24 @@ void Output<T>::connect(MultiportInput<T>& input) {
6751
template <typename T>
6852
void Output<T>::connect_fanout(MultiportInput<T>& input) {
6953
if (is_accumulated) {
70-
auto input_itr = input.begin();
71-
72-
if (accumulated.size() < input.get_nports()) {
73-
reactor::log::Warn() << "There are more right ports than left ports. "
74-
<< "Not all ports will be connected!";
75-
} else if (accumulated.size() > input.get_nports()) {
76-
reactor::log::Warn() << "There are more left ports than right ports. "
77-
<< "Not all ports will be connected!";
54+
std::set<reactor::Port<T>*> left_ports;
55+
std::set<reactor::Port<T>*> right_ports;
56+
bool result = false;
57+
result = left_ports.insert(this).second;
58+
reactor_assert(result);
59+
for (auto *l_port : accumulated) {
60+
result = left_ports.insert(l_port).second;
61+
reactor_assert(result);
7862
}
7963

80-
this->environment()->draw_connection(*this, *input_itr, reactor::ConnectionProperties{});
81-
++input_itr;
82-
83-
for (auto *l_port : accumulated) {
84-
if (input_itr != input.end()) {
85-
break;
86-
}
87-
this->environment()->draw_connection(*l_port, *input_itr, reactor::ConnectionProperties{});
88-
++input_itr;
64+
for (auto& right_port : input) {
65+
result = right_ports.insert(&right_port).second;
66+
reactor_assert(result);
8967
}
68+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
9069
is_accumulated = false;
9170
accumulated.clear();
9271
} else {
93-
// auto input_itr = input.begin();
94-
95-
// if (1 < input.get_nports()) {
96-
// reactor::log::Warn() << "Fanning out input to all right output ports";
97-
// }
98-
99-
// while (input_itr != input.end())
100-
// {
101-
// this->environment()->draw_connection(*this, *input_itr, reactor::ConnectionProperties{});
102-
// ++input_itr;
103-
// }
104-
10572
std::set<reactor::Port<T>*> left_ports;
10673
std::set<reactor::Port<T>*> right_ports;
10774
bool result = left_ports.insert(this).second;
@@ -139,23 +106,42 @@ void Output<T>::connect(ReactorBankInputPort<ReactorType, T> &&other_bank_ports)
139106
for (auto &p_reactor : other_bank_ports) {
140107
auto *reactor = p_reactor.get();
141108
this->environment()->draw_connection(*this, reactor->*(other_bank_ports.get_member()), reactor::ConnectionProperties{});
109+
break;
142110
}
143111
}
144112

145113
template <typename T>
146114
template <typename ReactorType>
147115
void Output<T>::connect(ReactorBankInputPortOffset<ReactorType, T> &&other_bank_ports) {
148-
149-
if (1 < other_bank_ports.size()) {
150-
reactor::log::Warn() << "There are more right ports than left ports. "
151-
<< "Not all ports will be connected!";
116+
std::set<reactor::Port<T>*> left_ports;
117+
std::set<reactor::Port<T>*> right_ports;
118+
bool result = left_ports.insert(this).second;
119+
reactor_assert(result);
120+
for (auto &p_reactor : other_bank_ports) {
121+
auto *reactor = p_reactor.get();
122+
char* reactor_base = reinterpret_cast<char*>(reactor);
123+
Input<T>* port = reinterpret_cast<Input<T>*>(reactor_base + other_bank_ports.get_offset());
124+
result = right_ports.insert(port).second;
125+
reactor_assert(result);
152126
}
127+
connect_ (left_ports, right_ports, reactor::ConnectionProperties{});
128+
}
129+
130+
template <typename T>
131+
template <typename ReactorType>
132+
void Output<T>::connect_fanout(ReactorBankInputPortOffset<ReactorType, T> &&other_bank_ports) {
133+
std::set<reactor::Port<T>*> left_ports;
134+
std::set<reactor::Port<T>*> right_ports;
135+
bool result = left_ports.insert(this).second;
136+
reactor_assert(result);
153137
for (auto &p_reactor : other_bank_ports) {
154138
auto *reactor = p_reactor.get();
155139
char* reactor_base = reinterpret_cast<char*>(reactor);
156140
Input<T>* port = reinterpret_cast<Input<T>*>(reactor_base + other_bank_ports.get_offset());
157-
this->environment()->draw_connection(*this, *port, reactor::ConnectionProperties{});
141+
result = right_ports.insert(port).second;
142+
reactor_assert(result);
158143
}
144+
connect_fanout_ (left_ports, right_ports, reactor::ConnectionProperties{});
159145
}
160146

161147
} // namespace sdk

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