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[beken-72xx] Add draft SPI TX support
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‎cores/beken-72xx/arduino/libraries/SPI/SPI.cpp‎

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/* Copyright (c) Kuba Szczodrzyński 2024-03-15. */
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#include "SPIPrivate.h"
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#define SPI_PERI_CLK_26M (26 * 1000 * 1000)
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#define SPI_PERI_CLK_DCO (80 * 1000 * 1000)
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bool SPIClass::beginPrivate() {
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if (!this->data)
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return false;
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uint32_t param;
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REG_SPI0->ctrl = 0;
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intc_service_change_handler(IRQ_SPI, (FUNCPTR)SPIClass::isrHandlerStatic);
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// bk_spi_configure()
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REG_SPI0->BIT_WIDTH = 0;
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REG_SPI0->MSTEN = true;
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// disable hardware CS - issues with per-byte data transfer otherwise
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#if LT_BK7231N
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REG_SPI0->WIRE3_EN = true;
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#else
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REG_SPI0->NSSMD = 3;
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#endif
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// spi_init_msten(0)
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REG_SPI0->TX_FIFO_INT_LEVEL = 0;
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REG_SPI0->TX_FIFO_INT_LEVEL = 0;
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REG_SPI0->TX_UDF_INT_EN = true;
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REG_SPI0->RX_OVF_INT_EN = true;
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// spi_active(1)
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REG_SPI0->SPIEN = true;
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// spi_icu_configuration(1)
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param = PWD_SPI_CLK_BIT;
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icu_ctrl(CMD_CLK_PWR_UP, &param);
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param = IRQ_SPI_BIT;
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icu_ctrl(CMD_ICU_INT_ENABLE, &param);
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// spi_gpio_configuration()
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param = GFUNC_MODE_SPI;
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gpio_ctrl(CMD_GPIO_ENABLE_SECOND, &param);
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return true;
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}
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bool SPIClass::endPrivate() {
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if (!this->data)
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return true;
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uint32_t param;
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param = IRQ_SPI_BIT;
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icu_ctrl(CMD_ICU_INT_DISABLE, &param);
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param = PWD_SPI_CLK_BIT;
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icu_ctrl(CMD_CLK_PWR_DOWN, &param);
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REG_SPI0->ctrl = 0;
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return true;
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}
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void SPIClass::setFrequency(uint32_t frequency) {
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if (!this->data)
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return;
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uint32_t param;
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uint32_t maxFrequency = 30000000;
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uint32_t sourceClk;
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uint32_t clockDiv;
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REG_SPI0->SPIEN = false;
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this->settings._clock = frequency;
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if (frequency == 26000000 || frequency == 13000000 || frequency == 6500000 || frequency <= 4333000) {
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#if CFG_XTAL_FREQUENCE
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sourceClk = CFG_XTAL_FREQUENCE;
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#else
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sourceClk = SPI_PERI_CLK_26M;
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#endif
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param = PCLK_POSI_SPI;
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icu_ctrl(CMD_CONF_PCLK_26M, &param);
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} else {
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if (frequency > maxFrequency) {
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LT_WM(SPI, "Clock freq too high! %lu > %lu", frequency, maxFrequency);
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frequency = maxFrequency;
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}
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sourceClk = SPI_PERI_CLK_DCO;
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param = PWD_SPI_CLK_BIT;
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icu_ctrl(CMD_CLK_PWR_DOWN, &param);
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param = PCLK_POSI_SPI;
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icu_ctrl(CMD_CONF_PCLK_DCO, &param);
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param = PWD_SPI_CLK_BIT;
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icu_ctrl(CMD_CLK_PWR_UP, &param);
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}
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if (frequency == 26000000 || frequency == 13000000 || frequency == 6500000) {
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clockDiv = sourceClk / frequency - 1;
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} else {
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clockDiv = ((sourceClk >> 1) / frequency);
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if (clockDiv < 2)
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clockDiv = 2;
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else if (clockDiv >= 255)
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clockDiv = 255;
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}
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REG_SPI0->SPI_CKR = clockDiv;
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REG_SPI0->SPIEN = true;
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}
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void SPIClass::setBitOrder(uint8_t bitOrder) {
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if (!this->data)
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return;
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this->settings._bitOrder = bitOrder;
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#if LT_BK7231N
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REG_SPI0->LSB_FIRST = bitOrder == SPI_LSBFIRST;
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#endif
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}
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void SPIClass::setDataMode(uint8_t dataMode) {
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if (!this->data)
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return;
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this->settings._dataMode = dataMode;
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REG_SPI0->CKPOL = (dataMode >> 1) & 0b1;
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REG_SPI0->CKPHA = (dataMode >> 0) & 0b1;
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}
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void SPIClass::commitTransaction() {
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if (this->txLen != 0) {
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REG_SPI0->TX_FIFO_CLR = true;
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REG_SPI0->TX_TRANS_LEN = this->txLen * 8;
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REG_SPI0->TX_FIFO_INT_EN = false;
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REG_SPI0->TX_EN = true;
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while (this->txLen--) {
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while (REG_SPI0->TX_FIFO_WR_READY == false) {}
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uint32_t data = *this->txBuf++;
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// LT_I("<- TX: %02x", data);
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REG_SPI0->SPI_DAT = data;
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}
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REG_SPI0->TX_FIFO_INT_EN = false;
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REG_SPI0->TX_EN = false;
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}
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if (this->rxLen != 0) {
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// REG_SPI0->RX_FIFO_CLR = true;
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// REG_SPI0->RX_TRANS_LEN = this->rxLen * 8;
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// REG_SPI0->RX_FIFO_INT_EN = false;
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// REG_SPI0->RX_FINISH_INT_EN = false;
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// REG_SPI0->RX_EN = true;
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// while (this->rxLen--) {
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// while (REG_SPI0->RX_FIFO_RD_READY == false) {}
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// uint32_t data = REG_SPI0->SPI_DAT;
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// // LT_I("-> RX: %02x", data);
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// *this->rxBuf++ = data;
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// }
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// REG_SPI0->RX_EN = false;
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// REG_SPI0->TX_FIFO_INT_EN = false;
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// REG_SPI0->RX_FIFO_INT_EN = false;
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}
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}
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void SPIClass::isrHandlerStatic(void *param) {
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SPI.isrHandler(param);
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}
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void SPIClass::isrHandler(void *param) {
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if (REG_SPI0->RX_FIFO_INT) {
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LT_I("RX_FIFO_INT, rxLen=%d", this->rxLen);
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while (this->rxLen != 0 && REG_SPI0->RX_FIFO_RD_READY == true) {
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uint8_t data = REG_SPI0->SPI_DAT;
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LT_I("RX data in ISR #1 %02x", data);
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*this->rxBuf++ = data;
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this->rxLen--;
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}
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if (this->rxLen == 0) {
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REG_SPI0->RX_EN = false;
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REG_SPI0->TX_FIFO_INT_EN = false;
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REG_SPI0->RX_FIFO_INT_EN = false;
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}
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REG_SPI0->RX_FIFO_INT = true;
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}
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if (REG_SPI0->RX_FINISH_INT) {
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LT_I("RX_FINISH_INT, rxLen=%d", this->rxLen);
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while (this->rxLen != 0 && REG_SPI0->RX_FIFO_RD_READY == true) {
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uint8_t data = REG_SPI0->SPI_DAT;
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LT_I("RX data in ISR #2 %02x", data);
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*this->rxBuf++ = data;
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this->rxLen--;
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}
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REG_SPI0->RX_EN = false;
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REG_SPI0->TX_FIFO_INT_EN = false;
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REG_SPI0->RX_FIFO_INT_EN = false;
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REG_SPI0->RX_FINISH_INT = true;
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}
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if (REG_SPI0->TX_UDF_INT) {
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LT_W("TX underflow");
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REG_SPI0->TX_UDF_INT = true;
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}
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if (REG_SPI0->RX_OVF_INT) {
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LT_W("RX overflow");
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REG_SPI0->RX_OVF_INT = true;
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}
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}

‎cores/beken-72xx/arduino/libraries/SPI/SPIPrivate.h‎

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/* Copyright (c) Kuba Szczodrzyński 2024-03-15. */
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#pragma once
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#include <ArduinoPrivate.h>
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#include <SPI.h>
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struct SPIData {};
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// Register structures based on:
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// - https://github.com/bekencorp/armino/blob/main/middleware/soc/bk7231n/soc/spi_struct.h
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// - https://wiki.bekencorp.com/pages/viewpage.action?pageId=23692278
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// - BDK beken378/driver/spi/*.h
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typedef volatile struct {
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union {
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struct {
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uint32_t TX_FIFO_INT_LEVEL : 2; //!< TX FIFO interrupt generation condition (1/16/32/48) [RW] (0x0[0:1])
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uint32_t RX_FIFO_INT_LEVEL : 2; //!< RX FIFO interrupt generation condition (1/16/32/48) [RW] (0x0[2:3])
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uint32_t TX_UDF_INT_EN : 1; //!< TX FIFO underflow interrupt enable [RW] (0x0[4])
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uint32_t RX_OVF_INT_EN : 1; //!< RX FIFO overflow interrupt enable [RW] (0x0[5])
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uint32_t TX_FIFO_INT_EN : 1; //!< TX FIFO interrupt enable [RW] (0x0[6])
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uint32_t RX_FIFO_INT_EN : 1; //!< RX FIFO interrupt enable [RW] (0x0[7])
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uint32_t SPI_CKR : 8; //!< Prescaler factor [RW] (0x0[8:15])
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#if LT_BK7231N || LT_BK7271
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uint32_t SLV_RELEASE_INT_EN : 1; //!< Slave release interrupt enable (four-wire slave mode) [RW] (0x0[16])
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uint32_t WIRE3_EN : 1; //!< Three-wire mode (no CSN signal) [RW] (0x0[17])
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#else
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uint32_t NSSMD : 2; //!< (0x0[16:17])
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#endif
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uint32_t BIT_WIDTH : 1; //!< Data bit width (0: 8-bit, 1: 16-bit) [RW] (0x0[18])
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#if LT_BK7231N || LT_BK7271
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uint32_t LSB_FIRST : 1; //!< Data frame format (0: MSB-first, 1: LSB-first) [RW] (0x0[19])
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#else
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uint32_t _reserved0 : 1; //!< (0x0[19])
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#endif
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uint32_t CKPOL : 1; //!< SPI clock polarity [RW] (0x0[20])
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uint32_t CKPHA : 1; //!< SPI clock phase [RW] (0x0[21])
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uint32_t MSTEN : 1; //!< Master mode enable [RW] (0x0[22])
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uint32_t SPIEN : 1; //!< SPI enable [RW] (0x0[23])
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#if LT_BK7231N || LT_BK7271
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uint32_t BYTE_INTLVAL : 8; //!< SCK interval between data units (master) [RW] (0x0[24:31])
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#else
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uint32_t _reserved1 : 8; //!< (0x0[24:31])
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#endif
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};
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uint32_t ctrl;
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};
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#if LT_BK7231N || LT_BK7271
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union {
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struct {
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uint32_t TX_EN : 1; //!< TX enable [RW] (0x1[0])
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uint32_t RX_EN : 1; //!< RX enable [RW] (0x1[1])
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uint32_t TX_FINISH_INT_EN : 1; //!< TX_TRANS_LEN completed interrupt enabled [RW] (0x1[2])
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uint32_t RX_FINISH_INT_EN : 1; //!< RX_TRANS_LEN completed interrupt enable [RW] (0x1[3])
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uint32_t _reserved2 : 4; //!< (0x1[4:7])
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uint32_t TX_TRANS_LEN : 12; //!< TX data length (bits), 0: unlimited [RW] (0x1[8:19])
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uint32_t RX_TRANS_LEN : 12; //!< RX data length (bits), 0: unlimited [RW] (0x1[20:31])
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};
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uint32_t config;
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};
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#endif
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#if LT_BK7231N || LT_BK7271
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union {
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struct {
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uint32_t _reserved3 : 1; //!< (0x2[0])
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uint32_t TX_FIFO_WR_READY : 1; //!< TX FIFO write allowed [R] (0x2[1])
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uint32_t RX_FIFO_RD_READY : 1; //!< RX FIFO read allowed [R] (0x2[2])
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uint32_t _reserved4 : 1; //!< (0x2[3])
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uint32_t _reserved5 : 4; //!< (0x2[4:7])
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uint32_t TX_FIFO_INT : 1; //!< TX FIFO interrupt (1: clear) [RW] (0x2[8])
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uint32_t RX_FIFO_INT : 1; //!< RX FIFO interrupt (1: clear) [RW] (0x2[9])
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uint32_t SLV_RELEASE_INT : 1; //!< Slave release interrupt (1: clear) [RW] (0x2[10])
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uint32_t TX_UDF_INT : 1; //!< TX FIFO underflow interrupt (1: clear) [RW] (0x2[11])
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uint32_t RX_OVF_INT : 1; //!< RX FIFO overflow interrupt (1: clear) [RW] (0x2[12])
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uint32_t TX_FINISH_INT : 1; //!< TX_TRANS_LEN completed interrupt [R] (0x2[13])
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uint32_t RX_FINISH_INT : 1; //!< RX_TRANS_LEN completed interrupt [R] (0x2[14])
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uint32_t _reserved6 : 1; //!< (0x2[15])
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uint32_t TX_FIFO_CLR : 1; //!< TX FIFO clear enable [W] (0x2[16])
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uint32_t RX_FIFO_CLR : 1; //!< RX FIFO clear enable [W] (0x2[17])
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uint32_t _reserved7 : 14; //!< (0x2[18:31])
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};
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uint32_t status;
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};
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#else
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union {
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struct {
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uint32_t TX_FIFO_EMPTY : 1; //!< (0x1[0])
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uint32_t TX_FIFO_FULL : 1; //!< (0x1[1])
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uint32_t RX_FIFO_EMPTY : 1; //!< (0x1[2])
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uint32_t RX_FIFO_FULL : 1; //!< (0x1[3])
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uint32_t _reserved8 : 4; //!< (0x2[4:7])
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uint32_t TX_FIFO_INT : 1; //!< TX FIFO interrupt (1: clear) [RW] (0x2[8])
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uint32_t RX_FIFO_INT : 1; //!< RX FIFO interrupt (1: clear) [RW] (0x2[9])
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uint32_t MODF : 1; //!< (0x1[10])
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uint32_t TX_UDF_INT : 1; //!< TX FIFO underflow interrupt (1: clear) [RW] (0x2[11])
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uint32_t RX_OVF_INT : 1; //!< RX FIFO overflow interrupt (1: clear) [RW] (0x2[12])
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uint32_t _reserved9 : 1; //!< (0x1[13])
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uint32_t SLVSEL : 1; //!< (0x1[14])
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uint32_t SPIBUSY : 1; //!< (0x1[15])
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uint32_t _reserved10 : 16; //!< (0x1[16:31])
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};
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uint32_t status;
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};
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#endif
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union {
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struct {
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uint32_t SPI_DAT : 16; //!< FIFO read/write operation [RW] (0x2[0:15])
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uint32_t _reserved11 : 16; //!< (0x2[16:31])
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};
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uint32_t data;
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};
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#if !(LT_BK7231N || LT_BK7271)
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union {
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struct {
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uint32_t _reserved12 : 1; //!< (0x3[0])
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uint32_t S_CS_UP_INT_EN : 1; //!< (0x3[1])
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uint32_t _reserved13 : 2; //!< (0x3[2:3])
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uint32_t S_CS_UP_INT_STATUS : 1; //!< (0x3[4])
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uint32_t _reserved14 : 27; //!< (0x3[5:31])
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};
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uint32_t slave_ctrl;
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};
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#endif
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} spi_hw_t;
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#if LT_BK7271
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#define REG_SPI0 ((spi_hw_t *)0x00802500)
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#define REG_SPI1 ((spi_hw_t *)0x00802540)
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#define REG_SPI2 ((spi_hw_t *)0x00802580)
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#else
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#define REG_SPI0 ((spi_hw_t *)0x00802700)
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#endif

‎cores/beken-72xx/arduino/src/lt_defs.h‎

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#define LT_ARD_HAS_WIFI 1
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#define LT_ARD_HAS_SERIAL 1
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#define LT_ARD_HAS_SPI 1
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#define LT_ARD_HAS_WIRE 1
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#define LT_ARD_MD5_HOSTAPD 1

‎cores/beken-72xx/base/sdk_private.h‎

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#include <pwm_pub.h>
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#include <rtos_pub.h>
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#include <saradc_pub.h>
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#include <spi_pub.h>
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#include <start_type_pub.h>
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#include <sys_ctrl.h>
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#include <sys_rtos.h>

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