Paddles: Delay mismatch between PDET2 and pot_cnt_n?

[daglem]

If PDET2 is delayed by one cycle, and pot_cnt_n are not, I cannot see how the paddle circuit can work.

• If the POT register is loaded with the counter value one cycle after detection of FF, the counter will have wrapped around to 100, and 00 will be loaded into the register instead of the correct FF.
• The RS flip flop in the schematic below will both be set and reset on the same cycle (set one cycle after detection of FF, and reset on the same cycle since the counter has wrapped around to 100, i.e. bit 8 is set).

Are by any chance all pot_cnt_n also delayed by one cycle? Or is there something I didn't understand correctly?