diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml index a986067d5f871..969fa8b4bdc94 100644 --- a/.github/workflows/assigner.yml +++ b/.github/workflows/assigner.yml @@ -29,7 +29,7 @@ jobs: steps: - name: Check out source code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml index 29ec478524686..897b9027c1f04 100644 --- a/.github/workflows/backport_issue_check.yml +++ b/.github/workflows/backport_issue_check.yml @@ -26,7 +26,7 @@ jobs: steps: - name: Check out source code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 9bfb923e397ef..17f94c9c75582 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -42,7 +42,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.4.20250818 options: '--entrypoint /bin/bash' env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr @@ -74,7 +74,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml index 3959b5fccc8f7..e1ae01a09aeb1 100644 --- a/.github/workflows/bug_snapshot.yaml +++ b/.github/workflows/bug_snapshot.yaml @@ -24,7 +24,7 @@ jobs: steps: - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 @@ -52,7 +52,7 @@ jobs: echo "BUGS_PICKLE_PATH=${BUGS_PICKLE_PATH}" >> ${GITHUB_ENV} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 + uses: aws-actions/configure-aws-credentials@7474bc4690e29a8392af63c5b98e7449536d5c3a # v4.3.1 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index d61f52bbce403..21974f618c6e8 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -18,7 +18,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.4.20250818 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -53,7 +53,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 persist-credentials: false @@ -136,13 +136,13 @@ jobs: if: (success() || failure()) steps: - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 persist-credentials: false - name: Download Artifacts - uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 + uses: actions/download-artifact@634f93cb2916e3fdff6788551b99b062d0335ce0 # v5.0.0 with: path: artifacts @@ -159,7 +159,7 @@ jobs: - name: Merge Test Results run: | - junitparser merge artifacts/*/twister.xml junit.xml + junitparser merge --glob artifacts/**/twister.xml junit.xml junit2html junit.xml junit-clang.html - name: Upload Unit Test Results in HTML diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index bc5dd7e758d60..c15c7ab9b8386 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -17,7 +17,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.4.20250818 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -64,7 +64,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 @@ -140,7 +140,7 @@ jobs: steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 @@ -156,7 +156,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 + uses: actions/download-artifact@634f93cb2916e3fdff6788551b99b062d0335ce0 # v5.0.0 with: path: coverage/reports @@ -232,10 +232,11 @@ jobs: - name: Upload coverage to Codecov if: always() - uses: codecov/codecov-action@18283e04ce6e62d37312384ff67231eb8fd56d24 # v5.4.3 + uses: codecov/codecov-action@fdcc8476540edceab3de004e990f80d881c6cc00 # v5.5.0 with: env_vars: OS,PYTHON fail_ci_if_error: false verbose: true token: ${{ secrets.CODECOV_TOKEN }} files: coverage/reports/merged.xml + flags: unittests-coverage diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index ac0d73c8d600d..03d8dc7bcdd70 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -36,10 +36,10 @@ jobs: config: ./.github/codeql/codeql-js-config.yml steps: - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Initialize CodeQL - uses: github/codeql-action/init@181d5eefc20863364f96762470ba6f862bdef56b # v3.29.2 + uses: github/codeql-action/init@2d92b76c45b91eb80fc44c74ce3fce0ee94e8f9d # v3.30.0 with: languages: ${{ matrix.language }} build-mode: ${{ matrix.build-mode }} @@ -53,6 +53,6 @@ jobs: exit 0 - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@181d5eefc20863364f96762470ba6f862bdef56b # v3.29.2 + uses: github/codeql-action/analyze@2d92b76c45b91eb80fc44c74ce3fce0ee94e8f9d # v3.30.0 with: category: "/language:${{matrix.language}}" diff --git a/.github/workflows/coding_guidelines.yml b/.github/workflows/coding_guidelines.yml index b574199cff166..2b8839799a3d2 100644 --- a/.github/workflows/coding_guidelines.yml +++ b/.github/workflows/coding_guidelines.yml @@ -11,7 +11,7 @@ jobs: name: Run coding guidelines checks on patch series (PR) steps: - name: Checkout the code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 9d1621cc4d3a9..01d83587152f9 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -21,7 +21,7 @@ jobs: echo "$HOME/.local/bin" >> $GITHUB_PATH - name: Checkout the code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml index 2b6018699649e..58d4fd3210de7 100644 --- a/.github/workflows/daily_test_version.yml +++ b/.github/workflows/daily_test_version.yml @@ -20,14 +20,14 @@ jobs: steps: - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 + uses: aws-actions/configure-aws-credentials@7474bc4690e29a8392af63c5b98e7449536d5c3a # v4.3.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} aws-region: us-east-1 - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index bf61725c26009..caef0b0ced8e8 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -33,7 +33,7 @@ jobs: os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python ${{ matrix.python-version }} uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 29dc9913d9a3e..3c8d65f7761b8 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -27,7 +27,7 @@ jobs: file_check: ${{ steps.check-doc-files.outputs.any_modified }} steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -78,7 +78,7 @@ jobs: echo "${HOME}/.local/bin" >> $GITHUB_PATH - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -164,6 +164,19 @@ jobs: name: api-coverage path: zephyr/api-coverage.tar.xz + - name: Upload Doxygen coverage to Codecov + if: github.event_name == 'schedule' + uses: codecov/codecov-action@fdcc8476540edceab3de004e990f80d881c6cc00 # v5.5.0 + with: + env_vars: OS,PYTHON + fail_ci_if_error: false + verbose: true + token: ${{ secrets.CODECOV_TOKEN }} + working-directory: zephyr + files: new.info + disable_search: true + flags: doxygen-coverage + - name: process-pr if: github.event_name == 'pull_request' run: | @@ -198,7 +211,7 @@ jobs: steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: path: zephyr diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index 710d9ec1cebc0..d19cb60527355 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -66,7 +66,7 @@ jobs: - name: Configure AWS Credentials if: steps.download-artifacts.outputs.found_artifact == 'true' - uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 + uses: aws-actions/configure-aws-credentials@7474bc4690e29a8392af63c5b98e7449536d5c3a # v4.3.1 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_PR_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml index a435f7ef5d03b..ed692a1a564c6 100644 --- a/.github/workflows/doc-publish.yml +++ b/.github/workflows/doc-publish.yml @@ -40,7 +40,7 @@ jobs: fi - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 + uses: aws-actions/configure-aws-credentials@7474bc4690e29a8392af63c5b98e7449536d5c3a # v4.3.1 with: aws-access-key-id: ${{ vars.AWS_DOCS_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_DOCS_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index ddbc5f33d2cc9..37873ac3ae57c 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -14,7 +14,7 @@ jobs: check-errno: runs-on: ubuntu-24.04 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.28.2 + image: ghcr.io/zephyrproject-rtos/ci:v0.28.4 steps: - name: Apply container owner mismatch workaround @@ -26,7 +26,7 @@ jobs: git config --global --add safe.directory ${GITHUB_WORKSPACE} - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Environment Setup run: | diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index c10dea7101f95..d0c9fe1c2a153 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -28,7 +28,7 @@ jobs: group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.4.20250818 options: '--entrypoint /bin/bash' defaults: run: @@ -62,7 +62,7 @@ jobs: sudo apt-get install -y python3-venv - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -89,7 +89,7 @@ jobs: west update 2>&1 1> west.update.log || west update 2>&1 1> west.update2.log - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 + uses: aws-actions/configure-aws-credentials@7474bc4690e29a8392af63c5b98e7449536d5c3a # v4.3.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/greet_first_time_contributor.yml b/.github/workflows/greet_first_time_contributor.yml index ae69fd5cc012a..20a315e132197 100644 --- a/.github/workflows/greet_first_time_contributor.yml +++ b/.github/workflows/greet_first_time_contributor.yml @@ -18,7 +18,7 @@ jobs: issues: write # to comment on issues steps: - - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - uses: zephyrproject-rtos/action-first-interaction@58853996b1ac504b8e0f6964301f369d2bb22e5c # v1.1.1+zephyr.6 with: repo-token: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index 77612ecd7adb9..a1f2d69a4ce97 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -32,7 +32,7 @@ jobs: runs-on: ${{ matrix.os }} steps: - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: path: zephyr fetch-depth: 0 diff --git a/.github/workflows/issue_count.yml b/.github/workflows/issue_count.yml index 2e5b11f11e904..01356e62d3379 100644 --- a/.github/workflows/issue_count.yml +++ b/.github/workflows/issue_count.yml @@ -45,7 +45,7 @@ jobs: path: ${{ env.OUTPUT_FILE_NAME }} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 + uses: aws-actions/configure-aws-credentials@7474bc4690e29a8392af63c5b98e7449536d5c3a # v4.3.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/license_check.yml b/.github/workflows/license_check.yml index 212c76366598d..f0593a79f0e7b 100644 --- a/.github/workflows/license_check.yml +++ b/.github/workflows/license_check.yml @@ -11,7 +11,7 @@ jobs: name: Scan code for licenses steps: - name: Checkout the code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 - name: Scan the code diff --git a/.github/workflows/maintainer_check.yml b/.github/workflows/maintainer_check.yml index dee115e8ced61..096fede5e3e12 100644 --- a/.github/workflows/maintainer_check.yml +++ b/.github/workflows/maintainer_check.yml @@ -17,7 +17,7 @@ jobs: steps: - name: Check out source code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 @@ -30,14 +30,14 @@ jobs: run: | pip install -r scripts/requirements-actions.txt --require-hashes - - name: Fetch MAINTAINERS.yml from mainline + - name: Fetch MAINTAINERS.yml from pull request run: | - git fetch origin main - git show origin/main:MAINTAINERS.yml > mainline_MAINTAINERS.yml + git fetch origin pull/${{ github.event.pull_request.number }}/head + git show FETCH_HEAD:MAINTAINERS.yml > pr_MAINTAINERS.yml - name: Check maintainer file changes env: GITHUB_TOKEN: ${{ secrets.ZB_PR_ASSIGNER_GITHUB_TOKEN }} run: | python ./scripts/ci/check_maintainer_changes.py \ - --repo zephyrproject-rtos/zephyr mainline_MAINTAINERS.yml MAINTAINERS.yml + --repo zephyrproject-rtos/zephyr MAINTAINERS.yml pr_MAINTAINERS.yml diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index c0ab05502fd63..3d71fe1af0476 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -13,36 +13,24 @@ jobs: name: Manifest steps: - name: Checkout the code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: path: zephyrproject/zephyr - ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 persist-credentials: false - - name: Set up Python - uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 - with: - python-version: 3.12 - cache: pip - cache-dependency-path: scripts/requirements-actions.txt - - - name: Install Python packages - run: | - cd zephyrproject/zephyr - pip install -r scripts/requirements-actions.txt --require-hashes - - name: west setup env: BASE_REF: ${{ github.base_ref }} working-directory: zephyrproject/zephyr run: | + pip install west==1.4.0 git config --global user.email "you@example.com" git config --global user.name "Your Name" west init -l . || true - name: Manifest - uses: zephyrproject-rtos/action-manifest@1729cded3fc798cf0de4a789c596dcb9c40eb14c # v1.9.1 + uses: zephyrproject-rtos/action-manifest@09983f53d3d878791aa37a7755ae44d695f4c1e5 # v2.0.0 with: github-token: ${{ secrets.GITHUB_TOKEN }} manifest-path: 'west.yml' diff --git a/.github/workflows/pinned-gh-actions.yml b/.github/workflows/pinned-gh-actions.yml index e7f51a3316ef1..2038ea874e4ed 100644 --- a/.github/workflows/pinned-gh-actions.yml +++ b/.github/workflows/pinned-gh-actions.yml @@ -14,6 +14,6 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Ensure SHA pinned actions uses: zgosalvez/github-actions-ensure-sha-pinned-actions@fc87bb5b5a97953d987372e74478de634726b3e5 # v3.0.25 diff --git a/.github/workflows/pr_metadata_check.yml b/.github/workflows/pr_metadata_check.yml index 3e862321e9691..b24c5c29136c5 100644 --- a/.github/workflows/pr_metadata_check.yml +++ b/.github/workflows/pr_metadata_check.yml @@ -19,7 +19,7 @@ jobs: runs-on: ubuntu-24.04 steps: - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 @@ -36,4 +36,7 @@ jobs: env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | - python -u scripts/ci/do_not_merge.py -p "${{ github.event.pull_request.number }}" + python -u scripts/ci/do_not_merge.py \ + -p "${{ github.event.pull_request.number }}" \ + -o "${{ github.event.repository.owner.login }}" \ + -r "${{ github.event.repository.name }}" diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml index edf38bad2b9c7..4264c7f214b77 100644 --- a/.github/workflows/pylib_tests.yml +++ b/.github/workflows/pylib_tests.yml @@ -32,7 +32,7 @@ jobs: os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python ${{ matrix.python-version }} uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml index 91f4037a2e2cc..e1e0b8d002705 100644 --- a/.github/workflows/release.yml +++ b/.github/workflows/release.yml @@ -15,7 +15,7 @@ jobs: permissions: contents: write # to create GitHub release entry steps: - - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + - uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml index b7527d0b50c11..dca774f65b2d6 100644 --- a/.github/workflows/scorecards.yml +++ b/.github/workflows/scorecards.yml @@ -29,7 +29,7 @@ jobs: steps: - name: "Checkout code" - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: persist-credentials: false @@ -56,6 +56,6 @@ jobs: # Upload the results to GitHub's code scanning dashboard (optional). # Commenting out will disable upload of results to your repo's Code Scanning dashboard - name: "Upload to code-scanning" - uses: github/codeql-action/upload-sarif@181d5eefc20863364f96762470ba6f862bdef56b # v3.29.2 + uses: github/codeql-action/upload-sarif@2d92b76c45b91eb80fc44c74ce3fce0ee94e8f9d # v3.30.0 with: sarif_file: results.sarif diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml index 4140dacbd63dd..dc6ba26a07053 100644 --- a/.github/workflows/scripts_tests.yml +++ b/.github/workflows/scripts_tests.yml @@ -32,7 +32,7 @@ jobs: os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 diff --git a/.github/workflows/stats_merged_prs.yml b/.github/workflows/stats_merged_prs.yml index 5ca8eb9aa9d54..99dce0c4ee107 100644 --- a/.github/workflows/stats_merged_prs.yml +++ b/.github/workflows/stats_merged_prs.yml @@ -16,7 +16,7 @@ jobs: runs-on: ubuntu-24.04 steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml index d080409645b1d..54e9ab8888e72 100644 --- a/.github/workflows/twister-publish.yaml +++ b/.github/workflows/twister-publish.yaml @@ -23,7 +23,7 @@ jobs: steps: # Needed for elasticearch and upload script - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: fetch-depth: 0 persist-credentials: false diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index d5f214be9fb36..44a4ecdf4d70c 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -42,7 +42,7 @@ jobs: steps: - name: Checkout if: github.event_name == 'pull_request' - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -127,7 +127,7 @@ jobs: needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.4.20250818 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -171,7 +171,7 @@ jobs: git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -323,7 +323,7 @@ jobs: steps: - name: Check out source code - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 @@ -341,13 +341,13 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 + uses: actions/download-artifact@634f93cb2916e3fdff6788551b99b062d0335ce0 # v5.0.0 with: path: artifacts - name: Merge Test Results run: | - junitparser merge artifacts/*/*/twister.xml junit.xml + junitparser merge --glob artifacts/**/twister.xml junit.xml junit2html junit.xml junit.html - name: Upload Unit Test Results @@ -360,6 +360,12 @@ jobs: junit.html junit.xml + - name: Upload test results to Codecov + if: ${{ !cancelled() && (github.event_name == 'push') }} + uses: codecov/test-results-action@47f89e9acb64b76debcd5ea40642d25a4adced9f # v1.1.1 + with: + token: ${{ secrets.CODECOV_TOKEN }} + - name: Publish Unit Test Results uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0 with: diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index bb95812b7be67..6d14e634ea816 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -39,7 +39,7 @@ jobs: os: [ubuntu-24.04] steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python ${{ matrix.python-version }} uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 5590016e922ec..510fb856b7d4d 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -32,7 +32,7 @@ jobs: runs-on: ${{ matrix.os }} steps: - name: Checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 with: path: zephyr fetch-depth: 0 @@ -51,7 +51,7 @@ jobs: toolchains: all - name: Run Pytest For Twister Black Box Tests - if: ${{ startsWith(runner.os, 'ubuntu') }} + if: ${{ runner.os == 'Linux' }} working-directory: zephyr shell: bash env: @@ -59,6 +59,7 @@ jobs: ZEPHYR_TOOLCHAIN_VARIANT: zephyr run: | export ZEPHYR_SDK_INSTALL_DIR=${{ github.workspace }}/zephyr-sdk + sudo apt-get install -y lcov echo "Run twister tests" source zephyr-env.sh PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox/ diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index c391148b5812d..21ddf53390116 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -36,7 +36,7 @@ jobs: os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0 - name: Set up Python ${{ matrix.python-version }} uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 diff --git a/.gitignore b/.gitignore index b57bdc8537266..3c5deca2ccc69 100644 --- a/.gitignore +++ b/.gitignore @@ -55,6 +55,7 @@ doc/doc.warnings hide-defaults-note venv .venv +.envrc .DS_Store .clangd new.info diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index 2af90ce1fdd7c..b5841d18bfac3 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -529,10 +529,6 @@ "UP032", # https://docs.astral.sh/ruff/rules/f-string "UP038", # https://docs.astral.sh/ruff/rules/non-pep604-isinstance ] -"./scripts/kconfig/hardenconfig.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] "./scripts/kconfig/kconfigfunctions.py" = [ "B011", # https://docs.astral.sh/ruff/rules/assert-false "SIM114", # https://docs.astral.sh/ruff/rules/if-with-same-arms diff --git a/CMakeLists.txt b/CMakeLists.txt index 7fb0f6d9870d0..abe74033e623a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1872,26 +1872,39 @@ endif() if(CONFIG_BUILD_OUTPUT_BIN AND CONFIG_BUILD_OUTPUT_UF2) if(CONFIG_BUILD_OUTPUT_UF2_USE_FLASH_BASE) - set(flash_addr "${CONFIG_FLASH_BASE_ADDRESS}") + set(code_address "${CONFIG_FLASH_BASE_ADDRESS}") else() - set(flash_addr "${CONFIG_FLASH_LOAD_OFFSET}") + set(code_address "${CONFIG_FLASH_LOAD_OFFSET}") endif() if(CONFIG_BUILD_OUTPUT_UF2_USE_FLASH_OFFSET) # Note, the `+ 0` in formula below avoids errors in cases where a Kconfig # variable is undefined and thus expands to nothing. - math(EXPR flash_addr - "${flash_addr} + ${CONFIG_FLASH_LOAD_OFFSET} + 0" + math(EXPR code_address + "${code_address} + ${CONFIG_FLASH_LOAD_OFFSET} + 0" OUTPUT_FORMAT HEXADECIMAL ) endif() + # No-XIP images (such as ones for RP2350 with CONFIG_XIP=n) + # are typically loaded to RAM + if(NOT CONFIG_XIP) + if(CONFIG_BUILD_OUTPUT_ADJUST_LMA) + math(EXPR code_address + "${CONFIG_SRAM_BASE_ADDRESS} + ${CONFIG_BUILD_OUTPUT_ADJUST_LMA} + 0" + OUTPUT_FORMAT HEXADECIMAL + ) + else() + set(code_address "${CONFIG_SRAM_BASE_ADDRESS}") + endif() + endif() + list(APPEND post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/uf2conv.py -c -f ${CONFIG_BUILD_OUTPUT_UF2_FAMILY_ID} - -b ${flash_addr} + -b ${code_address} -o ${KERNEL_UF2_NAME} ${KERNEL_BIN_NAME} ) @@ -2163,6 +2176,16 @@ if (CONFIG_BUILD_OUTPUT_VIF) include(${CMAKE_CURRENT_LIST_DIR}/cmake/vif.cmake) endif() +get_property(post_build_patch_elf_commands + GLOBAL PROPERTY + post_build_patch_elf_commands + ) + +list(PREPEND + post_build_commands + ${post_build_patch_elf_commands} + ) + get_property(extra_post_build_commands GLOBAL PROPERTY extra_post_build_commands diff --git a/Kconfig.zephyr b/Kconfig.zephyr index dd26888e75772..d8df86add4d39 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -6,6 +6,7 @@ # SPDX-License-Identifier: Apache-2.0 source "Kconfig.constants" +source "$(KCONFIG_ENV_FILE)" osource "$(APPLICATION_SOURCE_DIR)/VERSION" @@ -1029,7 +1030,7 @@ config WARN_EXPERIMENTAL config NOT_SECURE bool help - Symbol to be selected by a feature to inidicate that feature is + Symbol to be selected by a feature to indicate that feature is not secure. config TAINT diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 1f40198d499b3..0160330ac59ff 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -221,9 +221,6 @@ ARM arch: maintainers: - wearyzen collaborators: - - microbuilder - - carlocaione - - galak - MaureenHelm - stephanosio - bbolen @@ -241,9 +238,7 @@ ARM arch: - arch.arm ARM64 arch: - status: maintained - maintainers: - - carlocaione + status: odd fixes collaborators: - npitre - povergoing @@ -674,7 +669,6 @@ Board/SoC configuration: maintainers: - tejlmand collaborators: - - galak - nashif - nordicjm - "57300" @@ -803,7 +797,6 @@ CMSIS-DSP integration: maintainers: - stephanosio collaborators: - - galak - XenuIsWatching files: - modules/cmsis-dsp/ @@ -830,11 +823,20 @@ CMSIS-NN integration: tests: - libraries.cmsis_nn +CRC: + status: maintained + maintainers: + - thenguyenyf + files: + - include/zephyr/sys/crc.h + - subsys/crc/ + - tests/subsys/crc/ + labels: + - "area: CRC" + Cache: status: maintained maintainers: - - carlocaione - collaborators: - nashif files: - include/zephyr/drivers/cache.h @@ -1049,7 +1051,6 @@ Devicetree: - mbolivar collaborators: - decsny - - galak - rruuaanng files-regex: - ^dts/bindings/.*zephyr.* @@ -1269,6 +1270,19 @@ Documentation Infrastructure: - drivers.can - canbus +"Drivers: CRC": + status: maintained + maintainers: + - thenguyenyf + files: + - drivers/crc/ + - dts/bindings/crc/ + - include/zephyr/drivers/crc.h + - samples/drivers/crc/ + - tests/drivers/crc/ + labels: + - "area: CRC" + "Drivers: Charger": status: maintained maintainers: @@ -1583,6 +1597,18 @@ Documentation Infrastructure: tests: - drivers.fpga +"Drivers: Firmware": + status: maintained + maintainers: + - LaurentiuM1234 + files: + - drivers/firmware/ + - include/zephyr/drivers/firmware/ + - dts/bindings/firmware/ + - doc/hardware/arch/arm-scmi.rst + labels: + - "area: Firmware" + "Drivers: Flash": status: maintained maintainers: @@ -1643,7 +1669,6 @@ Documentation Infrastructure: - include/zephyr/drivers/gnss/ - include/zephyr/gnss/ - dts/bindings/gnss/ - - include/zephyr/dt-bindings/gnss/ - tests/drivers/build_all/gnss/ - tests/drivers/gnss/ - tests/subsys/gnss/ @@ -1908,7 +1933,6 @@ Documentation Infrastructure: status: odd fixes files: - drivers/mipi_dsi/ - - doc/hardware/peripherals/mipi_dsi.rst - include/zephyr/drivers/mipi_dsi.h - include/zephyr/drivers/mipi_dsi/ - tests/drivers/mipi_dsi/ @@ -1940,9 +1964,7 @@ Documentation Infrastructure: - drivers.mspi "Drivers: Mbox": - status: maintained - maintainers: - - carlocaione + status: odd fixes collaborators: - wearyzen - ithinuel @@ -2021,9 +2043,7 @@ Documentation Infrastructure: - samples.drivers.peci "Drivers: PM CPU ops": - status: maintained - maintainers: - - carlocaione + status: odd fixes collaborators: - gdengi - nbalabak @@ -2328,9 +2348,7 @@ Documentation Infrastructure: - drivers.stepper "Drivers: Syscon": - status: maintained - maintainers: - - carlocaione + status: odd fixes files: - include/zephyr/drivers/syscon.h - drivers/syscon/ @@ -2744,7 +2762,6 @@ IPC: maintainers: - doki-nordic collaborators: - - carlocaione - arnopo files: - include/zephyr/ipc/ @@ -3168,7 +3185,6 @@ MIPS arch: Memory Management: status: maintained maintainers: - - carlocaione - dcpleung files: - subsys/mem_mgmt/ @@ -3248,7 +3264,7 @@ Modbus: - include/zephyr/modbus/ - tests/subsys/modbus/ - subsys/modbus/ - - doc/services/modbus/ + - doc/connectivity/modbus/ labels: - "area: modbus" tests: @@ -3894,7 +3910,6 @@ Octavo Systems Platforms: Open AMP: status: maintained maintainers: - - carlocaione - iuliana-prodan collaborators: - uLipe @@ -4030,7 +4045,6 @@ RISCV arch: - mgielda - katsuster - edersondisouza - - carlocaione - npitre - ycsin - VynDragon @@ -4191,6 +4205,7 @@ Renesas RA Platforms: - duynguyenxa - thaoluonguw - thenguyenyf + - khoa-nguyen-18 files: - boards/arduino/uno_r4/ - boards/renesas/*ra*/ @@ -4202,6 +4217,7 @@ Renesas RA Platforms: - samples/boards/renesas/ - tests/boards/renesas/ - include/zephyr/drivers/misc/renesas_ra_external_interrupt/ + - include/zephyr/drivers/misc/interconn/renesas_elc/ labels: - "platform: Renesas RA" description: >- @@ -4611,11 +4627,11 @@ TDK Sensors: TI K3 Platforms: status: maintained maintainers: - - vaishnavachath + - glneo collaborators: - gramsay0 - dnltz - - glneo + - vaishnavachath files: - boards/ti/*am62*/ - drivers/*/*davinci* @@ -4919,7 +4935,6 @@ Utilities: - dcpleung - peter-mitsis files: - - lib/crc/ - lib/utils/ - tests/unit/timeutil/ - tests/unit/time_units/ @@ -5120,7 +5135,6 @@ West: maintainers: - stephanosio collaborators: - - microbuilder - povergoing files: - modules/cmsis/ @@ -5336,13 +5350,13 @@ West: - nika-nordic - masz-nordic collaborators: - - hubertmis - nordic-krch - kl-cruz - magp-nordic - jaz1-nordic - mif1-nordic - adamkondraciuk + - lstnl files: - modules/hal_nordic/ labels: @@ -5568,7 +5582,6 @@ West: "West project: libmetal": status: odd fixes collaborators: - - carlocaione - arnopo files: - modules/Kconfig.libmetal @@ -5591,6 +5604,15 @@ West: labels: - "area: Storage" +"West project: lora-basics-modem": + status: maintained + maintainers: + - JordanYates + files: + - modules/lora-basics-modem/ + labels: + - "area: LoRa" + "West project: loramac-node": status: maintained maintainers: @@ -5717,7 +5739,6 @@ West: "West project: open-amp": status: odd fixes collaborators: - - carlocaione - uLipe - iuliana-prodan files: @@ -5841,7 +5862,6 @@ West: - povergoing - sgrrzhf collaborators: - - carlocaione - wearyzen - ithinuel files: @@ -6031,6 +6051,7 @@ nRF Platforms: - kl-cruz - magp-nordic - nika-nordic + - lstnl files: - boards/nordic/ - drivers/*/*nrf*.c diff --git a/SDK_VERSION b/SDK_VERSION index c3d16c1646bdb..44e33a4117fca 100644 --- a/SDK_VERSION +++ b/SDK_VERSION @@ -1 +1 @@ -0.17.2 +0.17.4 diff --git a/arch/Kconfig b/arch/Kconfig index a179cc63b084c..52e15ac4bae9c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -135,6 +135,7 @@ config XTENSA select ARCH_HAS_DIRECTED_IPIS select THREAD_STACK_INFO select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE + select ARCH_SUPPORTS_COREDUMP_STACK_PTR if !SMP help Xtensa architecture @@ -230,6 +231,16 @@ config SRAM_BASE_ADDRESS /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. +config XIP + bool "Execute in place" + help + This option allows zephyr to operate with its text and read-only + sections residing in ROM (or similar read-only memory). Not all boards + support this option so it must be used with care; you must also + supply a linker command file when building your image. Enabling this + option increases both the code and data footprint of the image. + + if ARC || ARM || ARM64 || X86 || RISCV || RX # Workaround for not being able to have commas in macro arguments @@ -780,6 +791,9 @@ config ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET help Select when the architecture implements arch_thread_priv_stack_space_get(). +config ARCH_HAS_HW_SHADOW_STACK + bool + # # Other architecture related options # @@ -1092,9 +1106,12 @@ config CACHE_MANAGEMENT This option enables the cache management functions backed by arch or driver code. +if CACHE_MANAGEMENT + +if DCACHE + config DCACHE_LINE_SIZE_DETECT bool "Detect d-cache line size at runtime" - depends on CACHE_MANAGEMENT && DCACHE help This option enables querying some architecture-specific hardware for finding the d-cache line size at the expense of taking more memory and @@ -1106,18 +1123,21 @@ config DCACHE_LINE_SIZE_DETECT config DCACHE_LINE_SIZE int "d-cache line size" - depends on CACHE_MANAGEMENT && DCACHE && !DCACHE_LINE_SIZE_DETECT + depends on !DCACHE_LINE_SIZE_DETECT + default $(dt_node_int_prop_int,/cpus/cpu@0,d-cache-line-size) \ + if $(dt_node_has_prop,/cpus/cpu@0,d-cache-line-size) default 0 help - Size in bytes of a CPU d-cache line. If this is set to 0 the value is - obtained from the 'd-cache-line-size' DT property instead if present. - + Size in bytes of a CPU d-cache line. Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT. +endif # DCACHE + +if ICACHE + config ICACHE_LINE_SIZE_DETECT bool "Detect i-cache line size at runtime" - depends on CACHE_MANAGEMENT && ICACHE help This option enables querying some architecture-specific hardware for finding the i-cache line size at the expense of taking more memory and @@ -1129,17 +1149,19 @@ config ICACHE_LINE_SIZE_DETECT config ICACHE_LINE_SIZE int "i-cache line size" - depends on CACHE_MANAGEMENT && ICACHE && !ICACHE_LINE_SIZE_DETECT + depends on !ICACHE_LINE_SIZE_DETECT + default $(dt_node_int_prop_int,/cpus/cpu@0,i-cache-line-size) \ + if $(dt_node_has_prop,/cpus/cpu@0,i-cache-line-size) default 0 help - Size in bytes of a CPU i-cache line. If this is set to 0 the value is - obtained from the 'i-cache-line-size' DT property instead if present. + Size in bytes of a CPU i-cache line. Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT. +endif # ICACHE + choice CACHE_TYPE prompt "Cache type" - depends on CACHE_MANAGEMENT default ARCH_CACHE config ARCH_CACHE @@ -1154,6 +1176,8 @@ config EXTERNAL_CACHE endchoice +endif # CACHE_MANAGEMENT + endmenu config ARCH diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index 113ac5029736c..6e8e51e050010 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -22,7 +22,8 @@ #include #include #include -#include +#include +#include #include #include @@ -67,7 +68,7 @@ extern char __device_states_end[]; */ static void dev_state_zero(void) { - z_early_memset(__device_states_start, 0, __device_states_end - __device_states_start); + arch_early_memset(__device_states_start, 0, __device_states_end - __device_states_start); } #endif @@ -81,7 +82,7 @@ extern void arc_secureshield_init(void); * This routine prepares for the execution of and runs C code. */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); @@ -91,11 +92,11 @@ void z_prep_c(void) arc_cluster_scm_enable(); #endif - z_bss_zero(); + arch_bss_zero(); #ifdef __CCAC__ dev_state_zero(); #endif - z_data_copy(); + arch_data_copy(); #if CONFIG_ARCH_CACHE arch_cache_init(); #endif diff --git a/arch/arc/core/smp.c b/arch/arc/core/smp.c index 9da905ca5d291..bd317d2d99773 100644 --- a/arch/arc/core/smp.c +++ b/arch/arc/core/smp.c @@ -11,13 +11,13 @@ */ #include #include +#include #include -#include #include #include -#include #include #include +#include volatile struct { arch_cpustart_t fn; diff --git a/arch/arm/core/cortex_a_r/prep_c.c b/arch/arm/core/cortex_a_r/prep_c.c index a10588a49275f..d2cd695fb134c 100644 --- a/arch/arm/core/cortex_a_r/prep_c.c +++ b/arch/arm/core/cortex_a_r/prep_c.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) #include @@ -96,7 +98,7 @@ extern FUNC_NORETURN void z_cstart(void); * This routine prepares for the execution of and runs C code. * */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); @@ -107,8 +109,8 @@ void z_prep_c(void) #if defined(CONFIG_CPU_HAS_FPU) z_arm_floating_point_init(); #endif - z_bss_zero(); - z_data_copy(); + arch_bss_zero(); + arch_data_copy(); #if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS)) z_arm_init_stacks(); #endif diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index 170a5943f39b6..d0e31acb1ed83 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/core/cortex_a_r/thread.c b/arch/arm/core/cortex_a_r/thread.c index 96d32b8f58d62..c7134dac7afb2 100644 --- a/arch/arm/core/cortex_a_r/thread.c +++ b/arch/arm/core/cortex_a_r/thread.c @@ -14,8 +14,8 @@ */ #include +#include #include -#include #include #include #include diff --git a/arch/arm/core/cortex_m/CMakeLists.txt b/arch/arm/core/cortex_m/CMakeLists.txt index 3de8e544bc121..de4c99f4b67b8 100644 --- a/arch/arm/core/cortex_m/CMakeLists.txt +++ b/arch/arm/core/cortex_m/CMakeLists.txt @@ -2,20 +2,20 @@ zephyr_library() -if(CONFIG_ARMV8_1_M_PACBTI_STANDARD) +if(CONFIG_ARM_PACBTI_STANDARD) zephyr_compile_options(-mbranch-protection=standard) -elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET) +elseif(CONFIG_ARM_PACBTI_PACRET) zephyr_compile_options(-mbranch-protection=pac-ret) -elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF) +elseif(CONFIG_ARM_PACBTI_PACRET_LEAF) zephyr_compile_options(-mbranch-protection=pac-ret+leaf) -elseif(CONFIG_ARMV8_1_M_PACBTI_BTI) +elseif(CONFIG_ARM_PACBTI_BTI) zephyr_compile_options(-mbranch-protection=bti) -elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_BTI) +elseif(CONFIG_ARM_PACBTI_PACRET_BTI) zephyr_compile_options(-mbranch-protection=pac-ret+bti) -elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF_BTI) +elseif(CONFIG_ARM_PACBTI_PACRET_LEAF_BTI) zephyr_compile_options(-mbranch-protection=pac-ret+leaf+bti) -elseif(CONFIG_ARMV8_1_M_PACBTI_NONE) - #TODO: Enable this after Zephyr SDK updates to GCC version >=14.2 +elseif(CONFIG_ARM_PACBTI_NONE) + #TODO: Enable this after Zephyr SDK updates to the latest GCC version # zephyr_compile_options(-mbranch-protection=none) endif() diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index cb7f134598f3a..9a94b69b71786 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -310,60 +310,6 @@ config ARMV8_1_M_PMU This option is enabled when the CPU implements ARMv8-M Performance Monitoring Unit (PMU). -choice ARMV8_1_M_PACBTI - prompt "Pointer Authentication and Branch Target Identification" - default ARMV8_1_M_PACBTI_NONE - depends on ARMV8_1_M_MAINLINE - -config ARMV8_1_M_PACBTI_STANDARD - bool "Standard (PACRET + LEAF + BTI)" - help - This option instructs the compiler to generate code with all branch protection features - enabled at their standard level. - -config ARMV8_1_M_PACBTI_PACRET - bool "PACRET only" - help - This option instructs the compiler to generate code with return address signing for - all functions that save the return address to memory. - -config ARMV8_1_M_PACBTI_PACRET_LEAF - bool "PACRET + Leaf" - help - This option instructs the compiler to generate code with return address signing for - all functions that save the return address to memory and, - also sign leaf functions even if they do not write the return address to memory. - -config ARMV8_1_M_PACBTI_BTI - bool "BTI only" - help - This option enables Branch Target Identification (BTI), which inserts special landing - pad instructions at valid indirect branch targets. This option does not enable Pointer - Authentication (PAC). - -config ARMV8_1_M_PACBTI_PACRET_BTI - bool "PACRET + BTI" - help - This option instructs the compiler to generate code with return address signing for - all functions that save the return address to memory and, - add landing-pad instructions at the permitted targets of indirect branch instructions - -config ARMV8_1_M_PACBTI_PACRET_LEAF_BTI - bool "PACRET + Leaf + BTI" - help - This option instructs the compiler to generate code with return address signing for - all functions that save the return address to memory and, - also sign leaf functions even if they do not write the return address to memory and, - add landing-pad instructions at the permitted targets of indirect branch instructions - -config ARMV8_1_M_PACBTI_NONE - bool "None" - help - This option instructs the compiler to generate code without branch protection or return - address signing - -endchoice - config ARMV8_M_PMU_EVENTCNT int "Number of event counters in the Performance Monitoring Unit" depends on ARMV8_1_M_PMU diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index bc317f8ddec07..2ead97a1e6dff 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include /* * GCC can detect if memcpy is passed a NULL argument, however one of @@ -59,7 +61,7 @@ void __weak relocate_vector_table(void) /* Copy vector table to its location in SRAM */ size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; - z_early_memcpy(_sram_vector_start, _vector_start, vector_size); + arch_early_memcpy(_sram_vector_start, _vector_start, vector_size); #endif SCB->VTOR = VECTOR_ADDRESS & VTOR_MASK; barrier_dsync_fence_full(); @@ -193,7 +195,7 @@ extern FUNC_NORETURN void z_cstart(void); * This routine prepares for the execution of and runs C code. * */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); @@ -203,8 +205,8 @@ void z_prep_c(void) #if defined(CONFIG_CPU_HAS_FPU) z_arm_floating_point_init(); #endif - z_bss_zero(); - z_data_copy(); + arch_bss_zero(); + arch_data_copy(); #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) /* Invoke SoC-specific interrupt controller initialization */ z_soc_irq_init(); diff --git a/arch/arm/core/cortex_m/reset.S b/arch/arm/core/cortex_m/reset.S index c3f9362eca85d..b09391aaf0b59 100644 --- a/arch/arm/core/cortex_m/reset.S +++ b/arch/arm/core/cortex_m/reset.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,7 +20,7 @@ _ASM_FILE_PROLOGUE GTEXT(z_arm_reset) -GTEXT(z_early_memset) +GTEXT(arch_early_memset) GDATA(z_interrupt_stacks) GDATA(z_main_stack) #if defined(CONFIG_DEBUG_THREAD_INFO) @@ -35,6 +36,23 @@ GTEXT(z_arm_init_arch_hw_at_boot) GTEXT(arch_pm_s2ram_resume) #endif +/* + * PACBTI Mask for CONTROL register: + * bit 4 - BTI_EN, bit 5 - UBTI_EN, + * bit 6 - PAC_EN, bit 7 - UPAC_EN + */ +#ifdef CONFIG_ARM_PAC +#define CONTROL_ARM_PAC_MASK (1<<6)|(1<<7) +#else +#define CONTROL_ARM_PAC_MASK 0 +#endif + +#ifdef CONFIG_ARM_BTI +#define CONTROL_ARM_BTI_MASK (1<<4)|(1<<5) +#else +#define CONTROL_ARM_BTI_MASK 0 +#endif + /** * * @brief Reset vector @@ -177,7 +195,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) ldr r0, =z_interrupt_stacks ldr r1, =0xaa ldr r2, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE - bl z_early_memset + bl arch_early_memset #endif /* @@ -189,7 +207,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) adds r0, r0, r1 msr PSP, r0 mrs r0, CONTROL - movs r1, #2 + movs r1, #(2 | CONTROL_ARM_PAC_MASK | CONTROL_ARM_BTI_MASK) orrs r0, r1 /* CONTROL_SPSEL_Msk */ msr CONTROL, r0 /* diff --git a/arch/arm/core/cortex_m/swap_helper.S b/arch/arm/core/cortex_m/swap_helper.S index 40f00fc005629..70a175d080dad 100644 --- a/arch/arm/core/cortex_m/swap_helper.S +++ b/arch/arm/core/cortex_m/swap_helper.S @@ -2,6 +2,7 @@ * Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2017-2019 Nordic Semiconductor ASA. * Copyright (c) 2020 Stephanos Ioannidis + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -313,6 +314,24 @@ SECTION_FUNC(TEXT, z_arm_pendsv) #endif +#ifdef CONFIG_ARM_PAC_PER_THREAD + /* Read thread's dedicated PAC key and write them in the privileged PAC key registers. + * Note: There is no way to know the _current thread mode after the thread creation since + * `_current->arch.mode` for the userspace thread is set in z_arm_userspace_enter() which + * runs after z_arm_pendsv is done. So for now, while switching to an unprivileged thread + * the same PAC keys are set in both privileged and unprivileged PAC key registers. + * TODO: find a way to not set privileged PAC keys if the thread being switched into is an + * unprivileged thread. + */ + add r0, r2, #_thread_offset_to_pac_keys + ldmia r0!, {r3-r6} + msr PAC_KEY_P_0, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} +#endif /* CONFIG_ARM_PAC_PER_THREAD */ + /* load callee-saved + psp from thread */ add r0, r2, #_thread_offset_to_callee_saved ldmia r0, {r4-r11, ip} diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c index a1e281af4d5a5..80db710b157b2 100644 --- a/arch/arm/core/cortex_m/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2021 Lexmark International, Inc. - * Copyright (c) 2023 Arm Limited + * Copyright (c) 2023, 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,11 +15,12 @@ */ #include +#include #include -#include #include #include #include +#include #if (MPU_GUARD_ALIGN_AND_SIZE_FLOAT > MPU_GUARD_ALIGN_AND_SIZE) #define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - MPU_GUARD_ALIGN_AND_SIZE) @@ -121,6 +122,12 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta #if defined(CONFIG_USERSPACE) thread->arch.priv_stack_start = 0; #endif +#endif +#ifdef CONFIG_ARM_PAC_PER_THREAD + /* Generate PAC key and save it in thread context to be set later + * when the thread is actually switched in + */ + sys_csrand_get(&thread->arch.pac_keys, sizeof(struct pac_keys)); #endif /* * initial values in all other registers/thread entries are @@ -541,6 +548,9 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, #endif #endif /* CONFIG_BUILTIN_STACK_GUARD */ +#ifdef CONFIG_ARM_PAC_PER_THREAD + __set_PAC_KEY_P((uint32_t *)&main_thread->arch.pac_keys); +#endif /* * Set PSP to the highest address of the main stack * before enabling interrupts and jumping to main. diff --git a/arch/arm/core/cortex_m/thread_abort.c b/arch/arm/core/cortex_m/thread_abort.c index 99af867110705..30562bbc7a4e4 100644 --- a/arch/arm/core/cortex_m/thread_abort.c +++ b/arch/arm/core/cortex_m/thread_abort.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/core/irq_offload.c b/arch/arm/core/irq_offload.c index 65349de331b0c..ff457f74946bf 100644 --- a/arch/arm/core/irq_offload.c +++ b/arch/arm/core/irq_offload.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015 Intel corporation + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,7 +35,8 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) offload_routine = routine; offload_param = parameter; - __asm__ volatile ("svc %[id]" + __asm__ volatile ("svc %[id]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti")) : : [id] "i" (_SVC_CALL_IRQ_OFFLOAD) : "memory"); diff --git a/arch/arm/core/offsets/offsets_aarch32.c b/arch/arm/core/offsets/offsets_aarch32.c index 693546630b05e..e8236d8459f76 100644 --- a/arch/arm/core/offsets/offsets_aarch32.c +++ b/arch/arm/core/offsets/offsets_aarch32.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,6 +33,10 @@ GEN_OFFSET_SYM(_thread_arch_t, basepri); GEN_OFFSET_SYM(_thread_arch_t, swap_return_value); +#if defined(CONFIG_ARM_PAC_PER_THREAD) +GEN_OFFSET_SYM(_thread_arch_t, pac_keys); +#endif + #if defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R) GEN_OFFSET_SYM(_thread_arch_t, exception_depth); GEN_OFFSET_SYM(_cpu_arch_t, exc_depth); diff --git a/arch/arm/core/userspace.S b/arch/arm/core/userspace.S index 3594940078da3..2cd42f3210773 100644 --- a/arch/arm/core/userspace.S +++ b/arch/arm/core/userspace.S @@ -273,10 +273,24 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) orrs ip, ip, #1 /* Store (unprivileged) mode in thread's mode state variable */ str r1, [r0, #_thread_offset_to_mode] + +#ifdef CONFIG_ARM_PAC_PER_THREAD + /* Read thread's dedicated PAC key and since we are in unprivileged mode write them in the + * unprivileged PAC key registers. + * This needs to be done before we switch to unprivileged mode. + */ + add r1, r0, #_thread_offset_to_pac_keys + ldmia r1!, {r3-r6} + msr PAC_KEY_U_0, r3 + msr PAC_KEY_U_1, r4 + msr PAC_KEY_U_2, r5 + msr PAC_KEY_U_3, r6 + clrm {r3-r6} +#endif #endif dsb msr CONTROL, ip -#endif +#endif /* CONFIG_CPU_AARCH32_CORTEX_R */ /* ISB is not strictly necessary here (stack pointer is not being * touched), but it's recommended to avoid executing pre-fetched diff --git a/arch/arm/include/offsets_short_arch.h b/arch/arm/include/offsets_short_arch.h index ea6af4db92df3..d9c3c5e4d0398 100644 --- a/arch/arm/include/offsets_short_arch.h +++ b/arch/arm/include/offsets_short_arch.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Carlo Caione + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -59,6 +60,10 @@ (___thread_stack_info_t_start_OFFSET + ___thread_t_stack_info_OFFSET) #endif +#if defined(CONFIG_ARM_PAC_PER_THREAD) +#define _thread_offset_to_pac_keys \ + (___thread_t_arch_OFFSET + ___thread_arch_t_pac_keys_OFFSET) +#endif /* end - threads */ diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index 57d87e016f16c..a2368adc81240 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -72,6 +72,13 @@ config CPU_CORTEX_A76_A55 help This option signifies the use of a Cortex-A76 and A55 big little CPU cluster +config CPU_CORTEX_A78 + bool + select CPU_CORTEX_A + select ARMV8_A + help + This option signifies the use of a Cortex-A78 CPU + config CPU_CORTEX_R82 bool select CPU_AARCH64_CORTEX_R diff --git a/arch/arm64/core/early_mem_funcs.S b/arch/arm64/core/early_mem_funcs.S index 383cdec790195..51c7a450633a8 100644 --- a/arch/arm64/core/early_mem_funcs.S +++ b/arch/arm64/core/early_mem_funcs.S @@ -18,9 +18,9 @@ _ASM_FILE_PROLOGUE * to memset or memcpy on its own. */ -/* void z_early_memset(void *dst, int c, size_t n) */ -GTEXT(z_early_memset) -SECTION_FUNC(TEXT, z_early_memset) +/* void arch_early_memset(void *dst, int c, size_t n) */ +GTEXT(arch_early_memset) +SECTION_FUNC(TEXT, arch_early_memset) /* is dst pointer 8-bytes aligned? */ tst x0, #0x7 @@ -51,9 +51,9 @@ SECTION_FUNC(TEXT, z_early_memset) 4: ret -/* void z_early_memcpy(void *dst, const void *src, size_t n) */ -GTEXT(z_early_memcpy) -SECTION_FUNC(TEXT, z_early_memcpy) +/* void arch_early_memcpy(void *dst, const void *src, size_t n) */ +GTEXT(arch_early_memcpy) +SECTION_FUNC(TEXT, arch_early_memcpy) /* are dst and src pointers 8-bytes aligned? */ orr x8, x1, x0 diff --git a/arch/arm64/core/prep_c.c b/arch/arm64/core/prep_c.c index 11c7d2b112bab..19787e844e616 100644 --- a/arch/arm64/core/prep_c.c +++ b/arch/arm64/core/prep_c.c @@ -14,10 +14,11 @@ * initialization is performed. */ -#include #include #include #include +#include +#include extern void z_arm64_mm_init(bool is_primary_core); @@ -30,7 +31,7 @@ __weak void z_arm64_mm_init(bool is_primary_core) { } * This routine prepares for the execution of and runs C code. * */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); @@ -39,8 +40,8 @@ void z_prep_c(void) /* Initialize tpidrro_el0 with our struct _cpu instance address */ write_tpidrro_el0((uintptr_t)&_kernel.cpus[0]); - z_bss_zero(); - z_data_copy(); + arch_bss_zero(); + arch_data_copy(); #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK /* After bss clean, _kernel.cpus is in bss section */ z_arm64_safe_exception_stack_init(); diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index c09ddd336168a..a52223643091b 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/core/thread.c b/arch/arm64/core/thread.c index 3d93eb4b824d8..53cf707b584e1 100644 --- a/arch/arm64/core/thread.c +++ b/arch/arm64/core/thread.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include /* diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt index 6f1042b0050ff..d817afa3d7fe0 100644 --- a/arch/common/CMakeLists.txt +++ b/arch/common/CMakeLists.txt @@ -17,6 +17,9 @@ if(CONFIG_GEN_ISR_TABLES) ) endif() +zephyr_library_sources(init.c) +zephyr_library_sources_ifdef(CONFIG_XIP xip.c) + zephyr_library_sources_ifdef( CONFIG_ISR_TABLE_SHELL isr_tables_shell.c diff --git a/arch/common/Kconfig b/arch/common/Kconfig index 1684b9f16fdec..54f52da620253 100644 --- a/arch/common/Kconfig +++ b/arch/common/Kconfig @@ -1,6 +1,7 @@ # Common architecture configuration options # Copyright (c) 2022, CSIRO. +# Copyright 2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 config SEMIHOST @@ -74,3 +75,96 @@ config ARM_MPU Since this does not compromise User Mode, we make the skipping of full partitioning the default behavior for the ARMv8-M and ARMv8-R MPU driver. + +config ARM_PAC_PER_THREAD + bool "Set cryptographically secure PAC key per thread" + depends on ARM_PAC + depends on ENTROPY_DEVICE_RANDOM_GENERATOR || TIMER_RANDOM_GENERATOR + help + Select this option to generate and use unique keys per thread to generate Pointer + Authentication Code. + Internally, sys_csrand_get() is used as part of arch_new_thread() to generate + cryptographically secure random keys, which are saved in the thread's + architecture-specific context. These keys are then loaded into the PAC key registers + before switching to the thread during context switches. + Applications can chose to have hardware based random keys generator by selecting the right + generator from RNG_GENERATOR_CHOICE or by selecting TIMER_RANDOM_GENERATOR for testing + with pseudo random keys. + Note: GCC version 14.3 or higher is needed to support this option. + +config ARM_PAC + bool + help + This option signifies that Pointer Authentication Code is enabled. + +config ARM_BTI + bool + help + This option signifies that Branch Target Identification is enabled. + +choice ARM_PACBTI + prompt "Pointer Authentication and Branch Target Identification (PACBTI)" + default ARM_PACBTI_NONE + depends on ARMV8_1_M_MAINLINE + help + Select a PACBTI configuration to enable the compiler to insert the required + Pointer Authentication and Branch Target Identification (PACBTI) instructions. + This also sets the necessary configuration options to enable PACBTI bits + in hardware. + +config ARM_PACBTI_STANDARD + bool "Standard (PACRET + LEAF + BTI)" + select ARM_PAC + select ARM_BTI + help + This option instructs the compiler to generate code with all branch protection features + enabled at their standard level. + +config ARM_PACBTI_PACRET + bool "PACRET only" + select ARM_PAC + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory. + +config ARM_PACBTI_PACRET_LEAF + bool "PACRET + Leaf" + select ARM_PAC + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + also sign leaf functions even if they do not write the return address to memory. + +config ARM_PACBTI_BTI + bool "BTI only" + select ARM_BTI + help + This option enables Branch Target Identification (BTI), which inserts special landing + pad instructions at valid indirect branch targets. This option does not enable Pointer + Authentication (PAC). + +config ARM_PACBTI_PACRET_BTI + bool "PACRET + BTI" + select ARM_PAC + select ARM_BTI + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + add landing-pad instructions at the permitted targets of indirect branch instructions + +config ARM_PACBTI_PACRET_LEAF_BTI + bool "PACRET + Leaf + BTI" + select ARM_PAC + select ARM_BTI + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + also sign leaf functions even if they do not write the return address to memory and, + add landing-pad instructions at the permitted targets of indirect branch instructions + +config ARM_PACBTI_NONE + bool "None" + help + This option instructs the compiler to generate code without branch protection or return + address signing +endchoice diff --git a/arch/common/init.c b/arch/common/init.c new file mode 100644 index 0000000000000..b5e83a0b8dc19 --- /dev/null +++ b/arch/common/init.c @@ -0,0 +1,128 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright The Zephyr Project Contributors + */ + +#include +#include +#include +#include +#include + +/* LCOV_EXCL_START + * + * This code is called so early in the boot process that code coverage + * doesn't work properly. In addition, not all arches call this code, + * some like x86 do this with optimized assembly + */ + +/** + * @brief equivalent of memset() for early boot usage + * + * Architectures that can't safely use the regular (optimized) memset very + * early during boot because e.g. hardware isn't yet sufficiently initialized + * may override this with their own safe implementation. + */ +__boot_func +void __weak arch_early_memset(void *dst, int c, size_t n) +{ + (void) memset(dst, c, n); +} + +/** + * @brief equivalent of memcpy() for early boot usage + * + * Architectures that can't safely use the regular (optimized) memcpy very + * early during boot because e.g. hardware isn't yet sufficiently initialized + * may override this with their own safe implementation. + */ +__boot_func +void __weak arch_early_memcpy(void *dst, const void *src, size_t n) +{ + (void) memcpy(dst, src, n); +} + +/** + * @brief Clear BSS + * + * This routine clears the BSS region, so all bytes are 0. + */ +__boot_func +void arch_bss_zero(void) +{ + if (IS_ENABLED(CONFIG_SKIP_BSS_CLEAR)) { + return; + } + + arch_early_memset(__bss_start, 0, __bss_end - __bss_start); +#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm)) + arch_early_memset(&__ccm_bss_start, 0, + (uintptr_t) &__ccm_bss_end + - (uintptr_t) &__ccm_bss_start); +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) + arch_early_memset(&__dtcm_bss_start, 0, + (uintptr_t) &__dtcm_bss_end + - (uintptr_t) &__dtcm_bss_start); +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ocm)) + arch_early_memset(&__ocm_bss_start, 0, + (uintptr_t) &__ocm_bss_end + - (uintptr_t) &__ocm_bss_start); +#endif +#ifdef CONFIG_CODE_DATA_RELOCATION + extern void bss_zeroing_relocation(void); + + bss_zeroing_relocation(); +#endif /* CONFIG_CODE_DATA_RELOCATION */ +#ifdef CONFIG_COVERAGE_GCOV + arch_early_memset(&__gcov_bss_start, 0, + ((uintptr_t) &__gcov_bss_end - (uintptr_t) &__gcov_bss_start)); +#endif /* CONFIG_COVERAGE_GCOV */ +#ifdef CONFIG_NOCACHE_MEMORY + arch_early_memset(&_nocache_ram_start, 0, + (uintptr_t) &_nocache_ram_end - (uintptr_t) &_nocache_ram_start); +#endif +} + +#ifdef CONFIG_LINKER_USE_BOOT_SECTION +/** + * @brief Clear BSS within the boot region + * + * This routine clears the BSS within the boot region. + * This is separate from arch_bss_zero() as boot region may + * contain symbols required for the boot process before + * paging is initialized. + */ +__boot_func +void arch_bss_zero_boot(void) +{ + arch_early_memset(&lnkr_boot_bss_start, 0, + (uintptr_t)&lnkr_boot_bss_end + - (uintptr_t)&lnkr_boot_bss_start); +} +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ + +#ifdef CONFIG_LINKER_USE_PINNED_SECTION +/** + * @brief Clear BSS within the pinned region + * + * This routine clears the BSS within the pinned region. + * This is separate from arch_bss_zero() as pinned region may + * contain symbols required for the boot process before + * paging is initialized. + */ +#ifdef CONFIG_LINKER_USE_BOOT_SECTION +__boot_func +#else +__pinned_func +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ +void arch_bss_zero_pinned(void) +{ + arch_early_memset(&lnkr_pinned_bss_start, 0, + (uintptr_t)&lnkr_pinned_bss_end + - (uintptr_t)&lnkr_pinned_bss_start); +} +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ + +/* LCOV_EXCL_STOP */ diff --git a/arch/common/nocache.ld b/arch/common/nocache.ld index 749e88c9aed6d..b51192f97ad05 100644 --- a/arch/common/nocache.ld +++ b/arch/common/nocache.ld @@ -1,6 +1,7 @@ /* * Copyright (c) 2019 Nordic Semiconductor ASA * Copyright (c) 2019 Intel Corporation + * Copyright (c) 2025 Basalte bv * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,14 +9,15 @@ /* Copied from linker.ld */ /* Non-cached region of RAM */ -SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,,) +SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) { #if defined(CONFIG_MMU) MMU_ALIGN; #else - MPU_ALIGN(_nocache_ram_size); + MPU_ALIGN(_nocache_noload_ram_size); #endif _nocache_ram_start = .; + _nocache_noload_ram_start = .; *(.nocache) *(".nocache.*") @@ -24,9 +26,32 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,,) #if defined(CONFIG_MMU) MMU_ALIGN; #else - MPU_ALIGN(_nocache_ram_size); + MPU_ALIGN(_nocache_noload_ram_size); #endif + _nocache_noload_ram_end = .; +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +_nocache_noload_ram_size = _nocache_noload_ram_end - _nocache_noload_ram_start; + +/* Non-cached loadable region of RAM and ROM */ +SECTION_DATA_PROLOGUE(_NOCACHE_LOAD_SECTION_NAME,,) +{ +#if defined(CONFIG_MMU) + MMU_ALIGN; +#else + MPU_ALIGN(_nocache_load_ram_size); +#endif + _nocache_load_ram_start = .; + *(.nocache_load) + *(".nocache_load.*") + +#if defined(CONFIG_MMU) + MMU_ALIGN; +#else + MPU_ALIGN(_nocache_load_ram_size); +#endif + _nocache_load_ram_end = .; _nocache_ram_end = .; } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +_nocache_load_ram_size = _nocache_load_ram_end - _nocache_load_ram_start; +_nocache_load_rom_start = LOADADDR(_NOCACHE_LOAD_SECTION_NAME); _nocache_ram_size = _nocache_ram_end - _nocache_ram_start; -_nocache_load_start = LOADADDR(_NOCACHE_SECTION_NAME); diff --git a/kernel/xip.c b/arch/common/xip.c similarity index 79% rename from kernel/xip.c rename to arch/common/xip.c index 9973b6ef595ec..234d323118b54 100644 --- a/kernel/xip.c +++ b/arch/common/xip.c @@ -9,6 +9,7 @@ #include #include #include +#include #ifdef CONFIG_REQUIRES_STACK_CANARIES #ifdef CONFIG_STACK_CANARIES_TLS @@ -23,30 +24,30 @@ extern volatile uintptr_t __stack_chk_guard; * * This routine copies the data section from ROM to RAM. */ -void z_data_copy(void) +void arch_data_copy(void) { - z_early_memcpy(&__data_region_start, &__data_region_load_start, + arch_early_memcpy(&__data_region_start, &__data_region_load_start, __data_region_end - __data_region_start); #ifdef CONFIG_ARCH_HAS_RAMFUNC_SUPPORT - z_early_memcpy(&__ramfunc_region_start, &__ramfunc_load_start, + arch_early_memcpy(&__ramfunc_region_start, &__ramfunc_load_start, __ramfunc_end - __ramfunc_region_start); #endif /* CONFIG_ARCH_HAS_RAMFUNC_SUPPORT */ #ifdef CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT #if CONFIG_NOCACHE_MEMORY - z_early_memcpy(&_nocache_ram_start, &_nocache_load_start, - (uintptr_t) &_nocache_ram_size); + arch_early_memcpy(&_nocache_load_ram_start, &_nocache_load_rom_start, + (uintptr_t) &_nocache_load_ram_size); #endif /* CONFIG_NOCACHE_MEMORY */ #endif /* CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT */ #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm)) - z_early_memcpy(&__ccm_data_start, &__ccm_data_load_start, + arch_early_memcpy(&__ccm_data_start, &__ccm_data_load_start, __ccm_data_end - __ccm_data_start); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm)) - z_early_memcpy(&__itcm_start, &__itcm_load_start, + arch_early_memcpy(&__itcm_start, &__itcm_load_start, (uintptr_t) &__itcm_size); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) - z_early_memcpy(&__dtcm_data_start, &__dtcm_data_load_start, + arch_early_memcpy(&__dtcm_data_start, &__dtcm_data_load_start, __dtcm_data_end - __dtcm_data_start); #endif #ifdef CONFIG_CODE_DATA_RELOCATION @@ -74,7 +75,7 @@ void z_data_copy(void) } __stack_chk_guard = guard_copy; #else - z_early_memcpy(&_app_smem_start, &_app_smem_rom_start, + arch_early_memcpy(&_app_smem_start, &_app_smem_rom_start, _app_smem_end - _app_smem_start); #endif /* CONFIG_REQUIRES_STACK_CANARIES */ #endif /* CONFIG_USERSPACE */ diff --git a/arch/mips/core/prep_c.c b/arch/mips/core/prep_c.c index 0247f90df6249..823ea58b6dee7 100644 --- a/arch/mips/core/prep_c.c +++ b/arch/mips/core/prep_c.c @@ -9,10 +9,11 @@ * @brief Full C support initialization */ -#include #include #include #include +#include +#include static void interrupt_init(void) { @@ -44,12 +45,12 @@ static void interrupt_init(void) * @return N/A */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); #endif - z_bss_zero(); + arch_bss_zero(); interrupt_init(); #if CONFIG_ARCH_CACHE diff --git a/arch/riscv/core/ipi_clint.c b/arch/riscv/core/ipi_clint.c index e5f1256665337..f2f70a8434a48 100644 --- a/arch/riscv/core/ipi_clint.c +++ b/arch/riscv/core/ipi_clint.c @@ -4,10 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include - #include +#include +#include #define CLINT_NODE DT_NODELABEL(clint) #if !DT_NODE_EXISTS(CLINT_NODE) diff --git a/arch/riscv/core/prep_c.c b/arch/riscv/core/prep_c.c index e74a570cb6661..49cbd1dfb866b 100644 --- a/arch/riscv/core/prep_c.c +++ b/arch/riscv/core/prep_c.c @@ -18,9 +18,10 @@ #include #include #include -#include #include #include +#include +#include #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) void soc_interrupt_init(void); @@ -33,14 +34,14 @@ void soc_interrupt_init(void); * This routine prepares for the execution of and runs C code. */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); #endif - z_bss_zero(); - z_data_copy(); + arch_bss_zero(); + arch_data_copy(); #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) soc_interrupt_init(); #endif diff --git a/arch/riscv/core/smp.c b/arch/riscv/core/smp.c index 8607215cab346..b91595fa1a8fd 100644 --- a/arch/riscv/core/smp.c +++ b/arch/riscv/core/smp.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index 4ee23303f1ac6..773bf51479a44 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/rx/Kconfig b/arch/rx/Kconfig index 9e34a16ea099f..c57500f8730cb 100644 --- a/arch/rx/Kconfig +++ b/arch/rx/Kconfig @@ -11,6 +11,11 @@ config ARCH string default "rx" +config HAS_EXCEPT_VECTOR_TABLE + bool + help + Set if the processor has the exception vector table. + config CPU_RXV1 bool help @@ -18,19 +23,16 @@ config CPU_RXV1 config CPU_RXV2 bool + select HAS_EXCEPT_VECTOR_TABLE help Set if the processor supports the Renesas RXv2 instruction set. config CPU_RXV3 bool + select HAS_EXCEPT_VECTOR_TABLE help Set if the processor supports the Renesas RXv3 instruction set. -config HAS_EXCEPT_VECTOR_TABLE - bool - help - Set if the processor has the exception vector table. - config XIP default y diff --git a/arch/rx/core/irq_offload.c b/arch/rx/core/irq_offload.c index 9845bb4da8717..1364c0fda10b6 100644 --- a/arch/rx/core/irq_offload.c +++ b/arch/rx/core/irq_offload.c @@ -17,11 +17,12 @@ #include #include -#define SWINT1_IRQ_LINE 27 -#define SWINT1_PRIO 14 +#define SWINT1_NODE DT_NODELABEL(swint1) +#define SWINT1_IRQ_LINE DT_IRQN(SWINT1_NODE) +#define SWINT1_PRIO DT_IRQ(SWINT1_NODE, priority) /* Address of the software interrupt trigger register for SWINT1 */ -#define SWINT_REGISTER_ADDRESS 0x872E0 -#define SWINTR_SWINT *(uint8_t *)(SWINT_REGISTER_ADDRESS) +#define SWINT_REGISTER_ADDRESS DT_REG_ADDR(SWINT1_NODE) +#define SWINTR_SWINT *(uint8_t *)(SWINT_REGISTER_ADDRESS) static irq_offload_routine_t _offload_routine; static const void *offload_param; diff --git a/arch/rx/core/prep_c.c b/arch/rx/core/prep_c.c index 09d86d10d3634..ab96af5855521 100644 --- a/arch/rx/core/prep_c.c +++ b/arch/rx/core/prep_c.c @@ -15,11 +15,12 @@ * initialization is performed. */ -#include #include #include #include #include +#include +#include K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_initialization_process_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_INITIALIZATION_STACK_SIZE); @@ -30,11 +31,11 @@ K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_initialization_process_stacks, CONFIG_MP_MA * * @return N/A */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { - z_bss_zero(); + arch_bss_zero(); - z_data_copy(); + arch_data_copy(); z_cstart(); CODE_UNREACHABLE; diff --git a/arch/rx/core/thread.c b/arch/rx/core/thread.c index 5855dac3526a2..e307bddcf2d82 100644 --- a/arch/rx/core/thread.c +++ b/arch/rx/core/thread.c @@ -6,7 +6,6 @@ #include #include -#include #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); diff --git a/arch/rx/core/vects.c b/arch/rx/core/vects.c index 6835aeb868017..ff0154475fdcb 100644 --- a/arch/rx/core/vects.c +++ b/arch/rx/core/vects.c @@ -425,6 +425,8 @@ INT_DEMUX(253); INT_DEMUX(254); INT_DEMUX(255); +#if !CONFIG_HAS_EXCEPT_VECTOR_TABLE + const void *FixedVectors[] FVECT_SECT = { /* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */ /* Reserved for OFSM */ @@ -476,6 +478,60 @@ const void *FixedVectors[] FVECT_SECT = { _start, }; +#else + +/* The reset vector ALWAYS is at address 0xFFFFFFFC. Set it to point at + * the start routine (in reset.S) + */ +const FVECT_SECT void *resetVector = _start; + +/* Exception vector table + * (see rx-family-rxv2-instruction-set-architecture-users-manual-software) + */ +const void *ExceptVectors[] EXVECT_SECT = { + /* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* 0x50: Privileged instruction exception */ + INT_Excep_SuperVisorInst, + /* 0x54: Access exception */ + INT_Excep_AccessInst, + /* 0x58: Reserved */ + Dummy, + /* 0x5c: Undefined Instruction Exception */ + INT_Excep_UndefinedInst, + /* 0x60: Reserved */ + Dummy, + /* 0x64: Floating Point Exception */ + INT_Excep_FloatingPoint, + /* 0x68-0x74: Reserved */ + Dummy, + Dummy, + Dummy, + Dummy, + /* 0x78: Non-maskable interrupt */ + INT_NonMaskableInterrupt, +}; +#endif + const fp RelocatableVectors[] RVECT_SECT = { reserved_isr, switch_isr_wrapper, INT_RuntimeFatalInterrupt, reserved_isr, reserved_isr, reserved_isr, diff --git a/arch/sparc/core/prep_c.c b/arch/sparc/core/prep_c.c index 5b4a440a63cd3..129ca4a6c2748 100644 --- a/arch/sparc/core/prep_c.c +++ b/arch/sparc/core/prep_c.c @@ -8,10 +8,11 @@ * @file * @brief Full C support initialization */ - -#include +#include #include #include +#include +#include /** * @brief Prepare to and run C code @@ -19,12 +20,12 @@ * This routine prepares for the execution of and runs C code. */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); #endif - z_data_copy(); + arch_data_copy(); #if CONFIG_ARCH_CACHE arch_cache_init(); #endif diff --git a/arch/sparc/core/reset_trap.S b/arch/sparc/core/reset_trap.S index 6f1f6c037e3c1..dcea15a2a3b1f 100644 --- a/arch/sparc/core/reset_trap.S +++ b/arch/sparc/core/reset_trap.S @@ -57,7 +57,7 @@ SECTION_FUNC(TEXT, __sparc_trap_reset) nop #endif - call z_bss_zero + call arch_bss_zero nop call z_prep_c diff --git a/arch/x86/CMakeLists.txt b/arch/x86/CMakeLists.txt index 9f46f9d149e1b..19621e60582f2 100644 --- a/arch/x86/CMakeLists.txt +++ b/arch/x86/CMakeLists.txt @@ -72,3 +72,35 @@ if(CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c) endif() + +if(CONFIG_X86_CET) + zephyr_compile_options(-fcf-protection=full) + + if(CONFIG_HW_SHADOW_STACK) + set(GEN_SHSTK_ARRAY ${ZEPHYR_BASE}/arch/x86/gen_static_shstk_array.py) + + if(CONFIG_X86_64) + set(gen_shstk_array_arch_param --arch x86_64) + + execute_process( + COMMAND + ${PYTHON_EXECUTABLE} + ${GEN_SHSTK_ARRAY} + --header-output ${PROJECT_BINARY_DIR}/include/generated/zephyr/x86_shstk.h + --config ${DOTCONFIG} + ${gen_shstk_array_arch_param} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + else() + set(gen_shstk_array_arch_param --arch x86) + endif() + + set_property(GLOBAL APPEND PROPERTY post_build_patch_elf_commands + COMMAND + ${PYTHON_EXECUTABLE} + ${GEN_SHSTK_ARRAY} + --kernel $ + ${gen_shstk_array_arch_param} + ) + endif() +endif() diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 27fa6e40dcc27..e014766f63449 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -111,6 +111,10 @@ config X86_CPU_HAS_SSE42 config X86_CPU_HAS_SSE4A bool +config X86_CPU_HAS_CET + select ARCH_HAS_HW_SHADOW_STACK if !USERSPACE && !DYNAMIC_THREAD_ALLOC + bool + if FPU || X86_64 config X86_MMX @@ -492,6 +496,41 @@ config PRIVILEGED_STACK_SIZE # Must be multiple of CONFIG_MMU_PAGE_SIZE default 4096 if X86_MMU +config X86_CET + bool "Control-flow Enforcement Technology" + depends on X86_CPU_HAS_CET + help + This option enables Control-flow Enforcement Technology (CET) support. + +config X86_CET_IBT + bool "Indirect Branch Tracking" + depends on X86_CET && PICOLIBC_USE_MODULE + help + This option enables Indirect Branch Tracking (IBT) support. + +config X86_CET_SHADOW_STACK_ALIGNMENT + int "Shadow Stack alignment" + default 4096 + depends on HW_SHADOW_STACK + help + This option sets the alignment of the Shadow Stack. + +config X86_CET_VERIFY_KERNEL_SHADOW_STACK + bool "Verify kernel shadow stack" + depends on HW_SHADOW_STACK + help + When enabled, when a thread is swapped out, the kernel will verify + if its shadow stack pointer is not null with shadow stack enabled - + which would mean some attempt to tamper with the shadow stack. + +config X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + bool "SOC prepare shadow stack switch" + depends on HW_SHADOW_STACK + help + When enabled, call SoC code just before switching shadow stacks. + Code should be provided via soc_prepare_shadow_stack_switch assembler + macro. + source "arch/x86/core/Kconfig.ia32" source "arch/x86/core/Kconfig.intel64" diff --git a/arch/x86/core/CMakeLists.txt b/arch/x86/core/CMakeLists.txt index c34c6909b0172..80200f4015b57 100644 --- a/arch/x86/core/CMakeLists.txt +++ b/arch/x86/core/CMakeLists.txt @@ -29,6 +29,8 @@ zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) +zephyr_library_sources_ifdef(CONFIG_X86_CET cet.c) + if(CONFIG_X86_64) include(intel64.cmake) else() diff --git a/arch/x86/core/cet.c b/arch/x86/core/cet.c new file mode 100644 index 0000000000000..8636d7bb766d3 --- /dev/null +++ b/arch/x86/core/cet.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** + * @file + * @brief Indirect Branch Tracking + * + * Indirect Branch Tracking (IBT) setup routines. + */ + +#include +#include +#include +#include +#include + +#include +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +#ifdef CONFIG_X86_64 +#define TOKEN_OFFSET 5 +#else +#define TOKEN_OFFSET 4 +#endif + +#ifdef CONFIG_HW_SHADOW_STACK +#ifdef CONFIG_HW_SHADOW_STACK_ALLOW_REUSE +extern void arch_shadow_stack_reset(k_tid_t thread); +#endif /* CONFIG_HW_SHADOW_STACK_ALLOW_REUSE */ + +int arch_thread_hw_shadow_stack_attach(k_tid_t thread, + arch_thread_hw_shadow_stack_t *stack, + size_t stack_size) +{ + /* Can't attach to NULL */ + if (stack == NULL) { + LOG_ERR("Can't set NULL shadow stack for thread %p\n", thread); + return -EINVAL; + } + + /* Or if the thread already has a shadow stack. */ + if (thread->arch.shstk_addr != NULL) { +#ifdef CONFIG_HW_SHADOW_STACK_ALLOW_REUSE + /* Allow reuse of the shadow stack if the base and size are the same */ + if (thread->arch.shstk_base == stack && + thread->arch.shstk_size == stack_size) { + unsigned int key; + + key = arch_irq_lock(); + arch_shadow_stack_reset(thread); + arch_irq_unlock(key); + + return 0; + } +#endif + LOG_ERR("Shadow stack already set up for thread %p\n", thread); + return -EINVAL; + } + + thread->arch.shstk_addr = stack + (stack_size - + TOKEN_OFFSET * sizeof(*stack)) / sizeof(*stack); + thread->arch.shstk_size = stack_size; + thread->arch.shstk_base = stack; + + return 0; +} +#endif + +void z_x86_cet_enable(void) +{ +#ifdef CONFIG_X86_64 + __asm volatile ( + "movq %cr4, %rax\n\t" + "orq $0x800000, %rax\n\t" + "movq %rax, %cr4\n\t" + ); +#else + __asm volatile ( + "movl %cr4, %eax\n\t" + "orl $0x800000, %eax\n\t" + "movl %eax, %cr4\n\t" + ); +#endif +} + +#ifdef CONFIG_X86_CET_IBT +void z_x86_ibt_enable(void) +{ + uint64_t msr = z_x86_msr_read(X86_S_CET_MSR); + + msr |= X86_S_CET_MSR_ENDBR | X86_S_CET_MSR_NO_TRACK; + z_x86_msr_write(X86_S_CET_MSR, msr); +} +#endif + +#ifdef CONFIG_X86_CET_VERIFY_KERNEL_SHADOW_STACK +void z_x86_cet_shadow_stack_panic(k_tid_t *thread) +{ + LOG_ERR("Shadow stack enabled, but outgoing thread [%p] struct " + "missing shadow stack pointer", thread); + + k_panic(); +} +#endif diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c index a5c3986deb7e8..398388c030fbd 100644 --- a/arch/x86/core/fatal.c +++ b/arch/x86/core/fatal.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include @@ -265,6 +264,14 @@ static void dump_regs(const struct arch_esf *esf) esf->rsp, esf->rflags, esf->cs & 0xFFFFU, get_cr3(esf)); EXCEPTION_DUMP("RIP: 0x%016lx", esf->rip); +#ifdef CONFIG_HW_SHADOW_STACK + { + uintptr_t ssp; + + __asm__ volatile("rdsspq %0" : "=r"(ssp)); + EXCEPTION_DUMP("SSP: 0x%016lx", ssp); + } +#endif /* CONFIG_HW_SHADOW_STACK */ } #else /* 32-bit */ __pinned_func @@ -278,6 +285,14 @@ static void dump_regs(const struct arch_esf *esf) esf->cs & 0xFFFFU, get_cr3(esf)); EXCEPTION_DUMP("EIP: 0x%08x", esf->eip); +#ifdef CONFIG_HW_SHADOW_STACK + { + uintptr_t ssp; + + __asm__ volatile("rdsspd %0" : "=r"(ssp)); + EXCEPTION_DUMP("SSP: 0x%08lx", ssp); + } +#endif /* CONFIG_HW_SHADOW_STACK */ } #endif /* CONFIG_X86_64 */ @@ -343,6 +358,9 @@ static void log_exception(uintptr_t vector, uintptr_t code) case IV_VIRT_EXCEPTION: EXCEPTION_DUMP("Virtualization exception"); break; + case IV_CTRL_PROTECTION_EXCEPTION: + LOG_ERR("Control protection exception (code 0x%lx)", code); + break; case IV_SECURITY_EXCEPTION: EXCEPTION_DUMP("Security exception"); break; diff --git a/arch/x86/core/ia32/crt0.S b/arch/x86/core/ia32/crt0.S index 0c7ea821280b9..3806a6f7fb890 100644 --- a/arch/x86/core/ia32/crt0.S +++ b/arch/x86/core/ia32/crt0.S @@ -22,6 +22,7 @@ #include #include #include +#include /* exports (private APIs) */ @@ -29,8 +30,8 @@ /* externs */ GTEXT(z_prep_c) - GTEXT(z_bss_zero) - GTEXT(z_data_copy) + GTEXT(arch_bss_zero) + GTEXT(arch_data_copy) GDATA(_idt_base_address) GDATA(z_interrupt_stacks) @@ -225,11 +226,11 @@ __csSet: * This is a must is CONFIG_GDT_DYNAMIC is enabled, * as _gdt needs to be in RAM. */ - call z_data_copy + call arch_data_copy #endif /* Note that installing page tables must be done after - * z_data_copy() as the page tables are being copied into + * arch_data_copy() as the page tables are being copied into * RAM there. */ install_page_tables @@ -264,10 +265,10 @@ __csSet: #endif /* Clear BSS */ #ifdef CONFIG_LINKER_USE_BOOT_SECTION - call z_bss_zero_boot + call arch_bss_zero_boot #endif #ifdef CONFIG_LINKER_USE_PINNED_SECTION - call z_bss_zero_pinned + call arch_bss_zero_pinned #endif #ifdef CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT /* Don't clear BSS if the section is not present @@ -275,7 +276,17 @@ __csSet: * faults. Zeroing BSS will be done later once the * paging mechanism has been initialized. */ - call z_bss_zero + call arch_bss_zero +#endif + +#ifdef CONFIG_X86_CET + call z_x86_cet_enable +#ifdef CONFIG_X86_CET_IBT + call z_x86_ibt_enable +#endif +#ifdef CONFIG_HW_SHADOW_STACK + call z_x86_set_irq_shadow_stack +#endif #endif /* load 32-bit operand size IDT */ diff --git a/arch/x86/core/ia32/excstub.S b/arch/x86/core/ia32/excstub.S index 6c0a13a37cde3..9ca3dacc053f4 100644 --- a/arch/x86/core/ia32/excstub.S +++ b/arch/x86/core/ia32/excstub.S @@ -233,6 +233,7 @@ nestedException: KPTI_IRET SECTION_FUNC(PINNED_TEXT, _kernel_oops_handler) + endbr32 push $0 /* dummy error code */ push $z_x86_do_kernel_oops jmp _exception_enter diff --git a/arch/x86/core/ia32/fatal.c b/arch/x86/core/ia32/fatal.c index a4c8c73689fdd..a935722eda38d 100644 --- a/arch/x86/core/ia32/fatal.c +++ b/arch/x86/core/ia32/fatal.c @@ -115,6 +115,7 @@ EXC_FUNC_CODE(IV_GENERAL_PROTECTION, 0); EXC_FUNC_NOCODE(IV_X87_FPU_FP_ERROR, 0); EXC_FUNC_CODE(IV_ALIGNMENT_CHECK, 0); EXC_FUNC_NOCODE(IV_MACHINE_CHECK, 0); +EXC_FUNC_CODE(IV_CTRL_PROTECTION_EXCEPTION, 0); #endif _EXCEPTION_CONNECT_CODE(z_x86_page_fault_handler, IV_PAGE_FAULT, 0); diff --git a/arch/x86/core/ia32/intstub.S b/arch/x86/core/ia32/intstub.S index dd454670dd886..d1daf81223224 100644 --- a/arch/x86/core/ia32/intstub.S +++ b/arch/x86/core/ia32/intstub.S @@ -19,6 +19,11 @@ #include #include #include +#include + +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH +#include +#endif /* exports (internal APIs) */ @@ -112,12 +117,14 @@ SECTION_FUNC(PINNED_TEXT, _interrupt_enter) * EAX = isr_param, EDX = isr */ - /* Push EBP as we will use it for scratch space. - * Also it helps in stack unwinding + /* Push some registers we will use it for scratch space. + * Also it helps in stack unwinding * Rest of the callee-saved regs get saved by invocation of C * functions (isr handler, arch_swap(), etc) */ pushl %ebp + pushl %edi + pushl %ebx /* load %ecx with &_kernel */ @@ -144,6 +151,55 @@ SECTION_FUNC(PINNED_TEXT, _interrupt_enter) pushl %ebp /* Save stack pointer */ +#ifdef CONFIG_HW_SHADOW_STACK + movl _kernel_offset_to_current(%ecx), %ebp + cmpl $0, _thread_offset_to_shstk_addr(%ebp) + jz __sh_stk_verify + + /* Create restore SSP token. We can't use saveprevssp as it may + * conflict with the prepare_shadow_stack_switch from an SoC. + * Note that first scratch register will contain SSP after this + * macro runs. + */ + save_ssp_restore_token %ebx, %edi + movl %ebx, _thread_offset_to_shstk_addr(%ebp) + +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + pushl %eax + pushl %edx + pushl %ecx + soc_prepare_irq_shadow_stack_switch + popl %ecx + popl %edx + popl %eax +#endif + + movl _kernel_offset_to_shstk_addr(%ecx), %edi + rstorssp (%edi) + discard_previous_ssp_token %edi + + pushl %ebx /* Save SSP */ + jmp __sh_stk_out +__sh_stk_verify: +#ifdef CONFIG_X86_CET_VERIFY_KERNEL_SHADOW_STACK + pushl %eax + pushl %edx + pushl %ecx + movl $X86_S_CET_MSR, %ecx + rdmsr + testl $X86_S_CET_MSR_SHSTK_EN, %eax + jz __sh_stk_verify_out + pushl %ebp + call z_x86_cet_shadow_stack_panic + +__sh_stk_verify_out: + popl %ecx + popl %edx + popl %eax +#endif +__sh_stk_out: +#endif + #ifdef CONFIG_PM cmpl $0, _kernel_offset_to_idle(%ecx) jne handle_idle @@ -237,6 +293,28 @@ alreadyOnIntStack: * a switch to the new thread. */ +#ifdef CONFIG_HW_SHADOW_STACK + movl _kernel_offset_to_current(%ecx), %edi + cmpl $0, _thread_offset_to_shstk_addr(%edi) + jz __sh_stk_out_reschedule + + /* No need to save SSP on _kernel as it should always be at the + * same location. But we need to have a token there. + */ + save_ssp_restore_token %edi, %ebx + +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + pushl %edi + soc_prepare_shadow_stack_switch + popl %edi +#endif + + popl %ebp /* Get previous SSP token */ + rstorssp (%ebp) + discard_previous_ssp_token %ebp +__sh_stk_out_reschedule: +#endif + popl %esp /* switch back to outgoing thread's stack */ #ifdef CONFIG_STACK_SENTINEL @@ -266,6 +344,8 @@ alreadyOnIntStack: #endif /* CONFIG_LAZY_FPU_SHARING */ /* Restore volatile registers and return to the interrupted thread */ + popl %ebx + popl %edi popl %ebp popl %ecx popl %edx @@ -283,6 +363,28 @@ noReschedule: * interrupted thread's stack and restore volatile registers */ +#ifdef CONFIG_HW_SHADOW_STACK + movl _kernel_offset_to_current(%ecx), %ebp + cmpl $0, _thread_offset_to_shstk_addr(%ebp) + jz __sh_stk_out_no_reschedule + + /* No need to save SSP on _kernel as it should always be at the + * same location. But we need to have a token there. + */ + save_ssp_restore_token %edi, %ebx + +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + pushl %ebp + soc_prepare_shadow_stack_switch + popl %ebp +#endif + + popl %ebp /* Get previous SSP token position */ + rstorssp (%ebp) + discard_previous_ssp_token %ebp +__sh_stk_out_no_reschedule: +#endif + popl %esp /* pop thread stack pointer */ #ifdef CONFIG_STACK_SENTINEL @@ -299,6 +401,8 @@ noReschedule: */ nestedInterrupt: + popl %ebx + popl %edi popl %ebp popl %ecx /* pop volatile registers in reverse order */ popl %edx @@ -357,6 +461,7 @@ handle_idle: */ SECTION_FUNC(PINNED_TEXT, z_SpuriousIntNoErrCodeHandler) + endbr32 pushl $0 /* push dummy err code onto stk */ /* fall through to z_SpuriousIntHandler */ @@ -364,6 +469,7 @@ SECTION_FUNC(PINNED_TEXT, z_SpuriousIntNoErrCodeHandler) SECTION_FUNC(PINNED_TEXT, z_SpuriousIntHandler) + endbr32 cld /* Clear direction flag */ /* Create the ESF */ @@ -391,6 +497,7 @@ SECTION_FUNC(PINNED_TEXT, z_SpuriousIntHandler) #if CONFIG_IRQ_OFFLOAD SECTION_FUNC(PINNED_TEXT, _irq_sw_handler) + endbr32 push $0 push $z_irq_do_offload jmp _interrupt_enter @@ -429,6 +536,10 @@ stub_num = 0 .rept Z_DYN_STUB_PER_BLOCK .if stub_num < CONFIG_X86_DYNAMIC_IRQ_STUBS INT_STUB_NUM stub_num + /* + * 4-byte endbr32 + */ + endbr32 /* * 2-byte push imm8. */ diff --git a/arch/x86/core/ia32/irq_manage.c b/arch/x86/core/ia32/irq_manage.c index 4a3b5d03e26dc..6b3b554ac19bc 100644 --- a/arch/x86/core/ia32/irq_manage.c +++ b/arch/x86/core/ia32/irq_manage.c @@ -22,6 +22,9 @@ #include #include #include +#include + +#define TOKEN_OFFSET 4 extern void z_SpuriousIntHandler(void *handler); extern void z_SpuriousIntNoErrCodeHandler(void *handler); @@ -43,6 +46,21 @@ void arch_isr_direct_footer_swap(unsigned int key) (void)z_swap_irqlock(key); } +#ifdef CONFIG_HW_SHADOW_STACK +void z_x86_set_irq_shadow_stack(void) +{ + size_t stack_size = sizeof(__z_interrupt_stacks_shstk_arr); + arch_thread_hw_shadow_stack_t *stack; + + stack = (arch_thread_hw_shadow_stack_t *)__z_interrupt_stacks_shstk_arr; + + _kernel.cpus[0].arch.shstk_addr = stack + + (stack_size - TOKEN_OFFSET * sizeof(*stack)) / sizeof(*stack); + _kernel.cpus[0].arch.shstk_size = stack_size; + _kernel.cpus[0].arch.shstk_base = stack; +} +#endif + #if CONFIG_X86_DYNAMIC_IRQ_STUBS > 0 /* diff --git a/arch/x86/core/ia32/swap.S b/arch/x86/core/ia32/swap.S index 6103e4bbe5382..4baa0070b9b8d 100644 --- a/arch/x86/core/ia32/swap.S +++ b/arch/x86/core/ia32/swap.S @@ -16,6 +16,11 @@ #include #include #include +#include + +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH +#include +#endif /* exports (internal APIs) */ @@ -23,6 +28,10 @@ GTEXT(z_x86_thread_entry_wrapper) GTEXT(_x86_user_thread_entry_wrapper) +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + GTEXT(arch_shadow_stack_reset) +#endif + /* externs */ #if !defined(CONFIG_X86_KPTI) && defined(CONFIG_X86_USERSPACE) GTEXT(z_x86_swap_update_page_tables) @@ -291,9 +300,9 @@ restoreContext_NoFloatSwap: * or XMM register. */ - movl %cr0, %edx - orl $0x8, %edx - movl %edx, %cr0 + movl %cr0, %ebx + orl $0x8, %ebx + movl %ebx, %cr0 CROHandlingDone: @@ -304,6 +313,7 @@ CROHandlingDone: movl %eax, _kernel_offset_to_current(%edi) #if defined(CONFIG_X86_USE_THREAD_LOCAL_STORAGE) + pushl %edx pushl %eax call z_x86_tls_update_gdt @@ -313,6 +323,43 @@ CROHandlingDone: movw %ax, %gs popl %eax + popl %edx +#endif + +#ifdef CONFIG_HW_SHADOW_STACK + cmpl $0, _thread_offset_to_shstk_addr(%edx) + jz __sh_stk_verify + + /* Create a ssp token "by hand", as next thread may not have shadow + * stack enabled to use rstorssp/saveprevssp pair. Note that the token + * has 64 bits and needs to be aligned to 8 bytes. + */ + save_ssp_restore_token %ecx, %ebx + + /* Finally, save SSP on thread struct */ + movl %ecx, _thread_offset_to_shstk_addr(%edx) + + jmp __sh_stk_out + +__sh_stk_verify: +#ifdef CONFIG_X86_CET_VERIFY_KERNEL_SHADOW_STACK + /* Outgoing thread doesn't have a SSP, so shadow stack is disabled for + * it. Let's just check if shadow stack is enabled now, which would + * imply something is tampering with the pointer. */ + pushl %eax + pushl %edx + movl $X86_S_CET_MSR, %ecx + rdmsr + testl $X86_S_CET_MSR_SHSTK_EN, %eax + jz __sh_stk_verify_out + /* Stack already has k_thread* */ + call z_x86_cet_shadow_stack_panic + +__sh_stk_verify_out: + popl %edx + popl %eax +#endif /* CONFIG_X86_CET_VERIFY_KERNEL_SHADOW_STACK */ +__sh_stk_out: #endif /* recover thread stack pointer from k_thread */ @@ -339,16 +386,53 @@ CROHandlingDone: * - -EINVAL */ - /* Utilize the 'eflags' parameter to arch_swap() */ +#ifdef CONFIG_HW_SHADOW_STACK + pushl %eax + pushl %ebx + pushl %edi + + movl $_kernel, %eax + movl _kernel_offset_to_current(%eax), %edi + movl _thread_offset_to_shstk_addr(%edi), %ebx + testl %ebx, %ebx + jz __sh_stk_disable + movl $X86_S_CET_MSR, %ecx + rdmsr + orl $X86_S_CET_MSR_SHSTK_EN, %eax + wrmsr + +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + pushl %edi + soc_prepare_shadow_stack_switch + popl %edi +#endif - pushl 4(%esp) - popfl + rstorssp (%ebx) + discard_previous_ssp_token %ebx + jmp __sh_stk_done + +__sh_stk_disable: + movl $X86_S_CET_MSR, %ecx + rdmsr + andl $~X86_S_CET_MSR_SHSTK_EN, %eax + wrmsr +__sh_stk_done: + popl %edi + popl %ebx + popl %eax +#endif #if defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) pushl %eax call z_thread_mark_switched_in popl %eax #endif + + /* Utilize the 'eflags' parameter to arch_swap() */ + + pushl 4(%esp) + popfl + ret #ifdef _THREAD_WRAPPER_REQUIRED @@ -404,3 +488,59 @@ SECTION_FUNC(PINNED_TEXT, z_x86_thread_entry_wrapper) movl $0, (%esp) jmp *%edi #endif /* _THREAD_WRAPPER_REQUIRED */ + +#ifdef CONFIG_HW_SHADOW_STACK_ALLOW_REUSE + /* + * C function prototype: + * + * void arch_shadow_stack_reset(k_thread *thread); + */ +SECTION_FUNC(PINNED_TEXT, arch_shadow_stack_reset) + movl 0x4(%esp), %eax /* *thread on EAX */ + pushl %ebx + + /* As we are touching other thread shadow stack memory, SoC may + * need to do some house keeping. + */ +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + pushl %eax + soc_prepare_shadow_stack_switch + popl %eax +#endif + + movl _thread_offset_to_shstk_base(%eax), %ecx + movl _thread_offset_to_shstk_size(%eax), %edx + + /* Set "shstk[-2]", z_thread_entry/z_x86_thread_entry_wrapper */ + subl $8, %edx + addl %edx, %ecx + movl %ecx, %edx /* Save "&stsk[-2]" */ +#ifdef CONFIG_X86_DEBUG_INFO + movl $z_x86_thread_entry_wrapper, %ebx +#else + movl $z_thread_entry, %ebx +#endif + wrssd %ebx, (%ecx) + + /* Set "shstk[-3]", token high bits, 0 */ + xorl %ebx, %ebx + wrssd %ebx, -4(%ecx) + + /* Set "shstk[-4]", token low bits */ + wrssd %edx, -8(%ecx) + + /* Set thread->shstk_addr to point to the token on the stack */ + subl $8, %ecx + movl %ecx, _thread_offset_to_shstk_addr(%eax) + +#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH + movl $_kernel, %eax + movl _kernel_offset_to_current(%eax), %ecx + pushl %ecx + soc_prepare_shadow_stack_switch + popl %ecx +#endif + + popl %ebx + ret +#endif diff --git a/arch/x86/core/ia32/thread.c b/arch/x86/core/ia32/thread.c index 21d03ca216080..43b3bcc757b0a 100644 --- a/arch/x86/core/ia32/thread.c +++ b/arch/x86/core/ia32/thread.c @@ -13,7 +13,6 @@ */ #include -#include #include #include #include diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c index 31dbf060d6c9c..325e4d8f294e8 100644 --- a/arch/x86/core/intel64/cpu.c +++ b/arch/x86/core/intel64/cpu.c @@ -13,6 +13,9 @@ #include #include #include +#include +#include +#include #ifdef CONFIG_ACPI #include #include @@ -42,6 +45,16 @@ struct x86_cpuboot x86_cpuboot[] = { LISTIFY(CONFIG_MP_MAX_NUM_CPUS, X86_CPU_BOOT_INIT, (,)), }; +#ifdef CONFIG_HW_SHADOW_STACK +#define _CPU_IDX(n, _) n +FOR_EACH(X86_INTERRUPT_SHADOW_STACK_DEFINE, (;), + LISTIFY(CONFIG_MP_MAX_NUM_CPUS, _CPU_IDX, (,))); + +struct x86_interrupt_ssp_table issp_table[] = { + LISTIFY(CONFIG_MP_MAX_NUM_CPUS, X86_INTERRUPT_SSP_TABLE_INIT, (,)), +}; +#endif + /* * Send the INIT/STARTUP IPI sequence required to start up CPU 'cpu_num', which * will enter the kernel at fn(arg), running on the specified stack. @@ -105,8 +118,8 @@ FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot) if (cpuboot->cpu_id == 0U) { /* Only need to do these once per boot */ - z_bss_zero(); - z_data_copy(); + arch_bss_zero(); + arch_data_copy(); } z_loapic_enable(cpuboot->cpu_id); @@ -122,6 +135,19 @@ FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot) z_x86_msr_write(X86_FMASK_MSR, EFLAGS_SYSCALL); #endif +#ifdef CONFIG_X86_CET + z_x86_cet_enable(); +#ifdef CONFIG_X86_CET_IBT + z_x86_ibt_enable(); +#endif /* CONFIG_X86_CET_IBT */ +#ifdef CONFIG_HW_SHADOW_STACK + z_x86_setup_interrupt_ssp_table((uintptr_t)&issp_table[cpuboot->cpu_id]); + cpuboot->gs_base->shstk_addr = &issp_table[cpuboot->cpu_id].ist1; + cpuboot->gs_base->exception_shstk_addr = issp_table[cpuboot->cpu_id].ist7; +#endif /* CONFIG_HW_SHADOW_STACK */ + +#endif /* CONFIG_X86_CET */ + /* Enter kernel, never return */ cpuboot->ready++; cpuboot->fn(cpuboot->arg); diff --git a/arch/x86/core/intel64/fatal.c b/arch/x86/core/intel64/fatal.c index 941a982100c95..a7b127cd7cf26 100644 --- a/arch/x86/core/intel64/fatal.c +++ b/arch/x86/core/intel64/fatal.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/x86/core/intel64/irq.c b/arch/x86/core/intel64/irq.c index 51410646dbaf9..794ef17eb5d78 100644 --- a/arch/x86/core/intel64/irq.c +++ b/arch/x86/core/intel64/irq.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/x86/core/intel64/locore.S b/arch/x86/core/intel64/locore.S index 108d9f15d378f..e2076814141a9 100644 --- a/arch/x86/core/intel64/locore.S +++ b/arch/x86/core/intel64/locore.S @@ -14,6 +14,9 @@ #include #include #include +#ifdef CONFIG_HW_SHADOW_STACK +#include +#endif /* * Definitions/macros for enabling paging @@ -373,6 +376,71 @@ z_x86_switch: movq $X86_KERNEL_CS, _thread_offset_to_cs(%rsi) movq $X86_KERNEL_DS, _thread_offset_to_ss(%rsi) #endif + +#ifdef CONFIG_HW_SHADOW_STACK + cmpq $0, _thread_offset_to_shstk_addr(%rsi) + jz __sh_stk_verify + + movq %gs:(__x86_tss64_t_exception_shstk_addr_OFFSET), %rax + testq $1, (%rax) + jnz __switching_from_exception + + /* Create the shadow stack restore token by hand, as using + * saveprevssp is cumbersome when some threads don't use shadow + * stack. Note that as we return using iretq, we also need to add + * current CS and LIP (return pointer) to the shadow stack. It should + * currently be pointing to return pointer. + */ + rdsspq %rcx + movq (%rcx), %r10 /* LIP */ + + /* Save CS, overwriting current top of stack */ + movq $X86_KERNEL_CS, %r9 + wrssq %r9, (%rcx) + + /* Save LIP */ + wrssq %r10, -8(%rcx) + + /* Save SSP */ + movq %rcx, %r11 + addq $8, %r11 /* SSP has to point to before previous entry. */ + wrssq %r11, -16(%rcx) + + /* Create and "push" new token */ + movq %rcx, %r11 + subq $16, %r11 + orq $1, %r11 + wrssq %r11, -24(%rcx) + + /* Finally, save SSP on thread struct */ + subq $24, %rcx + movq %rcx, _thread_offset_to_shstk_addr(%rsi) + jmp __sh_stk_out + +__switching_from_exception: + /* We are switching from an exception, IOW, aborting current thread. + * The exception shadow stack needs to be marked as not busy so that it + * can be used again in case of a new exception. + */ + clrssbsy (%rax) + jmp __sh_stk_out + +__sh_stk_verify: +#ifdef CONFIG_X86_CET_VERIFY_KERNEL_SHADOW_STACK + /* Outgoing thread doesn't have a SSP, so shadow stack is disabled for + * it. Let's just check if shadow stack is enabled now, which would + * imply something is tampering with the pointer. + */ + movl $X86_S_CET_MSR, %ecx + rdmsr + testl $X86_S_CET_MSR_SHSTK_EN, %eax + jz __sh_stk_out + movq %rsi, %rdi + call z_x86_cet_shadow_stack_panic +#endif +__sh_stk_out: +#endif + /* Store the handle (i.e. our thread struct address) into the * switch handle field, this is a synchronization signal that * must occur after the last data from the old context is @@ -407,6 +475,29 @@ __resume: shrq $32, %rdx wrmsr #endif + +#ifdef CONFIG_HW_SHADOW_STACK + movq _thread_offset_to_shstk_addr(%rdi), %r10 + testq %r10, %r10 + jz __sh_stk_disable + + movl $X86_S_CET_MSR, %ecx + rdmsr + orl $X86_S_CET_MSR_SHSTK_EN, %eax + wrmsr + rstorssp (%r10) + movq $1, %r10 + incsspq %r10 /* Ignore previous ssp token */ + jmp __sh_stk_done +__sh_stk_disable: + movl $X86_S_CET_MSR, %ecx + rdmsr + andl $~X86_S_CET_MSR_SHSTK_EN, %eax + andl $~X86_S_CET_MSR_WR_SHSTK, %eax + wrmsr +__sh_stk_done: +#endif + #if (!defined(CONFIG_X86_KPTI) && defined(CONFIG_USERSPACE)) \ || defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) pushq %rdi /* Caller-saved, stash it */ @@ -449,7 +540,6 @@ __resume: movq $0xB9, _thread_offset_to_rip(%rdi) #endif - movq _thread_offset_to_rbx(%rdi), %rbx movq _thread_offset_to_rbp(%rdi), %rbp movq _thread_offset_to_r12(%rdi), %r12 @@ -498,17 +588,17 @@ __resume: #ifdef CONFIG_X86_KPTI #define EXCEPT_CODE(nr, ist) \ - vector_ ## nr: pushq %gs:__x86_tss64_t_ist ## ist ## _OFFSET; \ + vector_ ## nr: endbr64; pushq %gs:__x86_tss64_t_ist ## ist ## _OFFSET; \ pushq $nr; \ jmp except #define EXCEPT(nr, ist) \ - vector_ ## nr: pushq $0; \ + vector_ ## nr: endbr64; pushq $0; \ pushq %gs:__x86_tss64_t_ist ## ist ## _OFFSET; \ pushq $nr; \ jmp except #else -#define EXCEPT_CODE(nr) vector_ ## nr: pushq $nr; jmp except -#define EXCEPT(nr) vector_ ## nr: pushq $0; pushq $nr; jmp except +#define EXCEPT_CODE(nr) vector_ ## nr: endbr64; pushq $nr; jmp except +#define EXCEPT(nr) vector_ ## nr: endbr64; pushq $0; pushq $nr; jmp except #endif /* @@ -646,7 +736,7 @@ EXCEPT ( 4, 7); EXCEPT ( 5, 7); EXCEPT (6, 7); EXCEPT ( 7, EXCEPT_CODE ( 8, 7); EXCEPT ( 9, 7); EXCEPT_CODE (10, 7); EXCEPT_CODE (11, 7) EXCEPT_CODE (12, 7); EXCEPT_CODE (13, 7); EXCEPT_CODE (14, 7); EXCEPT (15, 7) EXCEPT (16, 7); EXCEPT_CODE (17, 7); EXCEPT (18, 7); EXCEPT (19, 7) -EXCEPT (20, 7); EXCEPT (21, 7); EXCEPT (22, 7); EXCEPT (23, 7) +EXCEPT (20, 7); EXCEPT_CODE (21, 7); EXCEPT (22, 7); EXCEPT (23, 7) EXCEPT (24, 7); EXCEPT (25, 7); EXCEPT (26, 7); EXCEPT (27, 7) EXCEPT (28, 7); EXCEPT (29, 7); EXCEPT (30, 7); EXCEPT (31, 7) @@ -660,7 +750,7 @@ EXCEPT ( 4); EXCEPT ( 5); EXCEPT ( 6); EXCEPT ( 7) EXCEPT_CODE ( 8); EXCEPT ( 9); EXCEPT_CODE (10); EXCEPT_CODE (11) EXCEPT_CODE (12); EXCEPT_CODE (13); EXCEPT_CODE (14); EXCEPT (15) EXCEPT (16); EXCEPT_CODE (17); EXCEPT (18); EXCEPT (19) -EXCEPT (20); EXCEPT (21); EXCEPT (22); EXCEPT (23) +EXCEPT (20); EXCEPT_CODE (21); EXCEPT (22); EXCEPT (23) EXCEPT (24); EXCEPT (25); EXCEPT (26); EXCEPT (27) EXCEPT (28); EXCEPT (29); EXCEPT (30); EXCEPT (31) @@ -733,6 +823,12 @@ irq: incl ___cpu_t_nested_OFFSET(%rsi) subq $CONFIG_ISR_SUBSTACK_SIZE, %gs:__x86_tss64_t_ist1_OFFSET +#ifdef CONFIG_HW_SHADOW_STACK + pushq %rsi + movq %gs:(__x86_tss64_t_shstk_addr_OFFSET), %rsi + subq $X86_CET_IRQ_SHADOW_SUBSTACK_SIZE, (%rsi) + popq %rsi +#endif cmpl $CONFIG_ISR_DEPTH, ___cpu_t_nested_OFFSET(%rsi) jz 1f sti @@ -801,6 +897,67 @@ irq_enter_unnested: /* Not nested: dump state to thread struct for __resume */ movq %rax, _thread_offset_to_ss(%rsi) #endif +#ifdef CONFIG_HW_SHADOW_STACK + cmpq $0, _thread_offset_to_shstk_addr(%rsi) + jz __sh_stk_verify_irq + + /* We are on a interrupt shadow stack, which contains the three + * entries needed to iretq. However, we may return to other + * thread, not the one interrupted. So we need to place these + * entries on the interrupted thread shadow stack, so it can be + * restored later. + */ + + rdsspq %rax + + /* Load entries from current shadow stack */ + movq (%rax), %r10 /* SSP */ + movq 8(%rax), %r11 /* LIP */ + movq 16(%rax), %r9 /* CS */ + + movq %r10, %rax /* rax now points to old shadow stack */ + + /* Save CS */ + wrssq %r9, -8(%rax) + + /* Save LIP */ + wrssq %r11, -16(%rax) + + /* Save SSP */ + wrssq %r10, -24(%rax) + + /* Create and "push" new token */ + movq %rax, %r10 + subq $24, %r10 + orq $1, %r10 + wrssq %r10, -32(%rax) + + /* Finally, save SSP on thread struct */ + subq $32, %rax + movq %rax, _thread_offset_to_shstk_addr(%rsi) + + jmp __sh_stk_out_irq + +__sh_stk_verify_irq: +#ifdef CONFIG_X86_CET_VERIFY_KERNEL_SHADOW_STACK + /* Outgoing thread doesn't have a SSP, so shadow stack is disabled for + * it. Let's just check if shadow stack is enabled now, which would + * imply something is tampering with the pointer. + */ + + pushq %rcx + movl $X86_S_CET_MSR, %ecx + rdmsr + popq %rcx + testl $X86_S_CET_MSR_SHSTK_EN, %eax + jz __sh_stk_out_irq + movq %rsi, %rdi + call z_x86_cet_shadow_stack_panic +#endif + +__sh_stk_out_irq: +#endif + irq_dispatch: #ifdef CONFIG_SCHED_THREAD_USAGE pushq %rcx @@ -825,6 +982,10 @@ irq_dispatch: cli addq $CONFIG_ISR_SUBSTACK_SIZE, %gs:__x86_tss64_t_ist1_OFFSET +#ifdef CONFIG_HW_SHADOW_STACK + movq %gs:(__x86_tss64_t_shstk_addr_OFFSET), %rax + addq $X86_CET_IRQ_SHADOW_SUBSTACK_SIZE, (%rax) +#endif decl ___cpu_t_nested_OFFSET(%rsi) jnz irq_exit_nested @@ -833,6 +994,23 @@ irq_dispatch: movq ___cpu_t_current_OFFSET(%rsi), %rdi call z_get_next_switch_handle movq %rax, %rdi + +#ifdef CONFIG_HW_SHADOW_STACK + /* __resume will change to next thread shadow stack (if any), so + * we need to mark IRQ shadow stack as free (not busy). + */ + movl $X86_S_CET_MSR, %ecx + rdmsr + testl $X86_S_CET_MSR_SHSTK_EN, %eax + jz 1f + + movq $3, %rax /* Discard SSP, LIP and CS from shadow stack */ + incsspq %rax + rdsspq %rax + clrssbsy (%rax) /* Free shadow stack */ +1: +#endif + jmp __resume irq_exit_nested: @@ -849,7 +1027,46 @@ irq_exit_nested: popq %rax iretq -#define IRQ(nr) vector_ ## nr: pushq $(nr - IV_IRQS); jmp irq +#ifdef CONFIG_HW_SHADOW_STACK_ALLOW_REUSE + /* + * C function prototype: + * + * void arch_shadow_stack_reset(k_thread *thread); + */ +.globl arch_shadow_stack_reset +arch_shadow_stack_reset: + movq _thread_offset_to_shstk_base(%rdi), %rcx + movq _thread_offset_to_shstk_size(%rdi), %rdx + + /* Set "shstk[-2]", CS */ + subq $16, %rdx + addq %rdx, %rcx + movq $X86_KERNEL_CS, %rsi + wrssq %rsi, (%rcx) + + /* Set "shstk[-3]", z_thread_entry */ + movq $z_thread_entry, %rsi + wrssq %rsi, -8(%rcx) + + /* Set "shstk[-4]", ssp, "&shstk[-1]" */ + movq %rcx, %rsi + addq $8, %rsi + wrssq %rsi, -16(%rcx) + + /* Set "shstk[-5]", token, "&shstk[-4] | 1" */ + movq %rcx, %rsi + subq $16, %rsi + orq $1, %rsi + wrssq %rsi, -24(%rcx) + + /* Set thread->shstk_addr to point to the token on the stack */ + subq $24, %rcx + movq %rcx, _thread_offset_to_shstk_addr(%rdi) + + ret +#endif + +#define IRQ(nr) vector_ ## nr: endbr64; pushq $(nr - IV_IRQS); jmp irq IRQ( 33); IRQ( 34); IRQ( 35); IRQ( 36); IRQ( 37); IRQ( 38); IRQ( 39) IRQ( 40); IRQ( 41); IRQ( 42); IRQ( 43); IRQ( 44); IRQ( 45); IRQ( 46); IRQ( 47) diff --git a/arch/x86/core/intel64/smp.c b/arch/x86/core/intel64/smp.c index d6c18cec9e669..f3d31aecf6d71 100644 --- a/arch/x86/core/intel64/smp.c +++ b/arch/x86/core/intel64/smp.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #define NR_IRQ_VECTORS (IV_NR_VECTORS - IV_IRQS) /* # vectors free for IRQs */ diff --git a/arch/x86/core/intel64/thread.c b/arch/x86/core/intel64/thread.c index bc326b2b17066..2b42bcb4c4918 100644 --- a/arch/x86/core/intel64/thread.c +++ b/arch/x86/core/intel64/thread.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include diff --git a/arch/x86/core/offsets/ia32_offsets.c b/arch/x86/core/offsets/ia32_offsets.c index dcbf3d7d6806e..d08db0cf06b57 100644 --- a/arch/x86/core/offsets/ia32_offsets.c +++ b/arch/x86/core/offsets/ia32_offsets.c @@ -48,6 +48,18 @@ GEN_OFFSET_SYM(_thread_arch_t, ptables); GEN_OFFSET_SYM(_thread_arch_t, preempFloatReg); +#ifdef CONFIG_HW_SHADOW_STACK +GEN_OFFSET_SYM(_thread_arch_t, shstk_addr); +GEN_OFFSET_SYM(_thread_arch_t, shstk_size); +GEN_OFFSET_SYM(_thread_arch_t, shstk_base); + +GEN_OFFSET_SYM(_kernel_t, cpus); +GEN_OFFSET_SYM(_cpu_t, arch); +GEN_OFFSET_SYM(_cpu_arch_t, shstk_addr); +GEN_OFFSET_SYM(_cpu_arch_t, shstk_size); +GEN_OFFSET_SYM(_cpu_arch_t, shstk_base); +#endif + /** * size of the struct k_thread structure sans save area for floating * point regs diff --git a/arch/x86/core/offsets/intel64_offsets.c b/arch/x86/core/offsets/intel64_offsets.c index 1ce29aa3b32f7..61bf0c282387c 100644 --- a/arch/x86/core/offsets/intel64_offsets.c +++ b/arch/x86/core/offsets/intel64_offsets.c @@ -34,12 +34,21 @@ GEN_OFFSET_SYM(_thread_arch_t, psp); GEN_OFFSET_SYM(_thread_arch_t, ptables); #endif #endif /* CONFIG_USERSPACE */ +#ifdef CONFIG_HW_SHADOW_STACK +GEN_OFFSET_SYM(_thread_arch_t, shstk_addr); +GEN_OFFSET_SYM(_thread_arch_t, shstk_base); +GEN_OFFSET_SYM(_thread_arch_t, shstk_size); +#endif GEN_OFFSET_SYM(x86_tss64_t, ist1); GEN_OFFSET_SYM(x86_tss64_t, ist2); GEN_OFFSET_SYM(x86_tss64_t, ist6); GEN_OFFSET_SYM(x86_tss64_t, ist7); GEN_OFFSET_SYM(x86_tss64_t, cpu); +#ifdef CONFIG_HW_SHADOW_STACK +GEN_OFFSET_SYM(x86_tss64_t, shstk_addr); +GEN_OFFSET_SYM(x86_tss64_t, exception_shstk_addr); +#endif #ifdef CONFIG_USERSPACE GEN_OFFSET_SYM(x86_tss64_t, psp); GEN_OFFSET_SYM(x86_tss64_t, usp); diff --git a/arch/x86/core/pcie.c b/arch/x86/core/pcie.c index 878e6886d7b8f..cf298cc1f9cfa 100644 --- a/arch/x86/core/pcie.c +++ b/arch/x86/core/pcie.c @@ -249,18 +249,24 @@ uint8_t arch_pcie_msi_vectors_allocate(unsigned int priority, for (i = 0; i < n_vector; i++) { if (n_vector == 1) { - /* This path is taken by PCIE device with fixed - * or single MSI: IRQ has been already allocated - * and/or set on the PCIe bus. Thus we only require - * to get it. + /* For PCIE device with fixed or single MSI: IRQ has + * been already allocated and/or set on the PCIe bus. + * We only need to retrieve it. */ irq = pcie_get_irq(vectors->bdf); + + /* If that is not the case, we will need to allocate + * IRQ before proceeding. + */ + if (irq == PCIE_CONF_INTR_IRQ_NONE) { + irq = arch_irq_allocate(); + } } else { irq = arch_irq_allocate(); } if ((irq == PCIE_CONF_INTR_IRQ_NONE) || (irq == -1)) { - return -1; + return 0; } vector = z_x86_allocate_vector(priority, prev_vector); diff --git a/arch/x86/core/prep_c.c b/arch/x86/core/prep_c.c index 2b371d8bfb134..0239c602fb0fe 100644 --- a/arch/x86/core/prep_c.c +++ b/arch/x86/core/prep_c.c @@ -5,14 +5,19 @@ */ #include -#include +#include +#include #include #include #include #include -#include +#include +#include + +K_KERNEL_PINNED_STACK_ARRAY_DECLARE(z_interrupt_stacks, + CONFIG_MP_MAX_NUM_CPUS, + CONFIG_ISR_STACK_SIZE); -extern FUNC_NORETURN void z_cstart(void); extern void x86_64_irq_init(void); #if !defined(CONFIG_X86_64) diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c index 436bc18edb73d..d2f38bc32800c 100644 --- a/arch/x86/core/userspace.c +++ b/arch/x86/core/userspace.c @@ -7,10 +7,10 @@ #include #include +#include #include #include #include -#include #include BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) && diff --git a/arch/x86/gen_idt.py b/arch/x86/gen_idt.py index 3ef957c952de6..7de21ea84f9cb 100755 --- a/arch/x86/gen_idt.py +++ b/arch/x86/gen_idt.py @@ -44,7 +44,7 @@ KERNEL_CODE_SEG = 0x08 # These exception vectors push an error code onto the stack. -ERR_CODE_VECTORS = [8, 10, 11, 12, 13, 14, 17] +ERR_CODE_VECTORS = [8, 10, 11, 12, 13, 14, 17, 21] def debug(text): diff --git a/arch/x86/gen_mmu.py b/arch/x86/gen_mmu.py index e09e3208e7965..638f13356d0fa 100755 --- a/arch/x86/gen_mmu.py +++ b/arch/x86/gen_mmu.py @@ -94,6 +94,7 @@ def bit(pos): FLAG_RW = bit(1) FLAG_US = bit(2) FLAG_CD = bit(4) +FLAG_D = bit(6) FLAG_SZ = bit(7) FLAG_G = bit(8) FLAG_XD = bit(63) @@ -163,6 +164,9 @@ def dump_flags(flags): if flags & FLAG_CD: ret += "CD " + if flags & FLAG_D: + ret += "D " + return ret.strip() @@ -320,7 +324,7 @@ class Pt(MMUTable): addr_mask = 0xFFFFF000 type_code = 'I' num_entries = 1024 - supported_flags = (FLAG_P | FLAG_RW | FLAG_US | FLAG_G | FLAG_CD | + supported_flags = (FLAG_P | FLAG_RW | FLAG_US | FLAG_G | FLAG_CD | FLAG_D | FLAG_IGNORED0 | FLAG_IGNORED1) class PtXd(Pt): @@ -329,7 +333,7 @@ class PtXd(Pt): type_code = 'Q' num_entries = 512 supported_flags = (FLAG_P | FLAG_RW | FLAG_US | FLAG_G | FLAG_XD | FLAG_CD | - FLAG_IGNORED0 | FLAG_IGNORED1 | FLAG_IGNORED2) + FLAG_D | FLAG_IGNORED0 | FLAG_IGNORED1 | FLAG_IGNORED2) class PtableSet(): @@ -909,6 +913,9 @@ def main(): pt.set_region_perms("_locore", FLAG_P | flag_user) pt.set_region_perms("_lorodata", FLAG_P | ENTRY_XD | flag_user) + if isdef("CONFIG_HW_SHADOW_STACK"): + pt.set_region_perms("__x86shadowstack", FLAG_P | FLAG_D | ENTRY_XD) + written_size = pt.write_output(args.output) debug("Written %d bytes to %s" % (written_size, args.output)) diff --git a/arch/x86/gen_static_shstk_array.py b/arch/x86/gen_static_shstk_array.py new file mode 100644 index 0000000000000..29183da50c85a --- /dev/null +++ b/arch/x86/gen_static_shstk_array.py @@ -0,0 +1,233 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2025 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +import argparse +import struct + +from elftools.elf.elffile import ELFFile +from elftools.elf.sections import SymbolTableSection + + +def parse_args(): + global args + parser = argparse.ArgumentParser( + description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter, + allow_abbrev=False, + ) + + parser.add_argument("-k", "--kernel", required=False, help="Zephyr kernel image") + parser.add_argument("-o", "--header-output", required=False, help="Header output file") + parser.add_argument("-c", "--config", required=False, help="Configuration file (.config)") + parser.add_argument( + "-a", + "--arch", + required=False, + help="Architecture to generate shadow stack for", + choices=["x86", "x86_64"], + default="x86", + ) + args = parser.parse_args() + + +def get_symbols(obj): + for section in obj.iter_sections(): + if isinstance(section, SymbolTableSection): + return {sym.name: sym for sym in section.iter_symbols()} + + raise LookupError("Could not find symbol table") + + +shstk_irq_top_fmt = " #include #include +#include #ifndef _ASMLANGUAGE #include @@ -73,4 +74,14 @@ extern void z_x86_tls_update_gdt(struct k_thread *thread); #endif /* _ASMLANGUAGE */ +#define X86_IRQ_SHADOW_STACK_DEFINE(name, size) \ + arch_thread_hw_shadow_stack_t Z_GENERIC_SECTION(.x86shadowstack) \ + __aligned(CONFIG_X86_CET_SHADOW_STACK_ALIGNMENT) \ + name[size / sizeof(arch_thread_hw_shadow_stack_t)] = \ + { [size / sizeof(arch_thread_hw_shadow_stack_t) - 4] = \ + (uintptr_t)name + size - 2 * sizeof(arch_thread_hw_shadow_stack_t), \ + [size / sizeof(arch_thread_hw_shadow_stack_t) - 3] = 0, \ + [size / sizeof(arch_thread_hw_shadow_stack_t) - 2] = 0, \ + } + #endif /* ZEPHYR_ARCH_X86_INCLUDE_IA32_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/x86/include/ia32/offsets_short_arch.h b/arch/x86/include/ia32/offsets_short_arch.h index b818cf60b550b..2497a659a9080 100644 --- a/arch/x86/include/ia32/offsets_short_arch.h +++ b/arch/x86/include/ia32/offsets_short_arch.h @@ -17,6 +17,17 @@ #define _kernel_offset_to_fpu_owner \ (___kernel_t_cpus_OFFSET + ___cpu_t_arch_OFFSET + ___cpu_arch_t_fpu_owner_OFFSET) +#ifdef CONFIG_HW_SHADOW_STACK +#define _kernel_offset_to_shstk_addr \ + (___kernel_t_cpus_OFFSET + ___cpu_t_arch_OFFSET + ___cpu_arch_t_shstk_addr_OFFSET) + +#define _kernel_offset_to_shstk_size \ + (___kernel_t_cpus_OFFSET + ___cpu_t_arch_OFFSET + ___cpu_arch_t_shstk_size_OFFSET) + +#define _kernel_offset_to_shstk_base \ + (___kernel_t_cpus_OFFSET + ___cpu_t_arch_OFFSET + ___cpu_arch_t_shstk_base_OFFSET) +#endif + /* end - kernel */ /* threads */ @@ -30,6 +41,17 @@ #define _thread_offset_to_preempFloatReg \ (___thread_t_arch_OFFSET + ___thread_arch_t_preempFloatReg_OFFSET) +#ifdef CONFIG_HW_SHADOW_STACK +#define _thread_offset_to_shstk_addr \ + (___thread_t_arch_OFFSET + ___thread_arch_t_shstk_addr_OFFSET) + +#define _thread_offset_to_shstk_size \ + (___thread_t_arch_OFFSET + ___thread_arch_t_shstk_size_OFFSET) + +#define _thread_offset_to_shstk_base \ + (___thread_t_arch_OFFSET + ___thread_arch_t_shstk_base_OFFSET) +#endif + /* end - threads */ #endif /* ZEPHYR_ARCH_X86_INCLUDE_IA32_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/x86/include/intel64/kernel_arch_data.h b/arch/x86/include/intel64/kernel_arch_data.h index af3b0d1c8165e..a1e4c25427200 100644 --- a/arch/x86/include/intel64/kernel_arch_data.h +++ b/arch/x86/include/intel64/kernel_arch_data.h @@ -7,6 +7,7 @@ #define ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_ #include +#include #ifndef _ASMLANGUAGE @@ -31,8 +32,18 @@ struct x86_cpuboot { typedef struct x86_cpuboot x86_cpuboot_t; -extern uint8_t x86_cpu_loapics[]; /* CPU logical ID -> local APIC ID */ +struct x86_interrupt_ssp_table { + uintptr_t not_used; + uintptr_t ist1; + uintptr_t ist2; + uintptr_t ist3; + uintptr_t ist4; + uintptr_t ist5; + uintptr_t ist6; + uintptr_t ist7; +}; +extern uint8_t x86_cpu_loapics[]; /* CPU logical ID -> local APIC ID */ #endif /* _ASMLANGUAGE */ #ifdef CONFIG_X86_KPTI @@ -74,6 +85,41 @@ extern uint8_t x86_cpu_loapics[]; /* CPU logical ID -> local APIC ID */ .arg = &x86_cpu_boot_arg, \ } +#define SHSTK_TOKEN_ENTRY(i, name, size) \ + [size * (i + 1) / sizeof(arch_thread_hw_shadow_stack_t) - 1] = \ + (uintptr_t)name + size * (i + 1) - 1 * \ + sizeof(arch_thread_hw_shadow_stack_t) + +#define X86_EXCEPTION_SHADOW_STACK_SIZE \ + K_THREAD_HW_SHADOW_STACK_SIZE(CONFIG_X86_EXCEPTION_STACK_SIZE) + +#define X86_IRQ_SHADOW_STACK_DEFINE(name, size) \ + arch_thread_hw_shadow_stack_t Z_GENERIC_SECTION(.x86shadowstack) \ + __aligned(CONFIG_X86_CET_SHADOW_STACK_ALIGNMENT) \ + name[CONFIG_ISR_DEPTH * size / sizeof(arch_thread_hw_shadow_stack_t)] = \ + { \ + LISTIFY(CONFIG_ISR_DEPTH, SHSTK_TOKEN_ENTRY, (,), name, size) \ + } + +#define X86_INTERRUPT_SHADOW_STACK_DEFINE(n) \ + X86_IRQ_SHADOW_STACK_DEFINE(z_x86_nmi_shadow_stack##n, \ + X86_EXCEPTION_SHADOW_STACK_SIZE); \ + X86_IRQ_SHADOW_STACK_DEFINE(z_x86_exception_shadow_stack##n, \ + X86_EXCEPTION_SHADOW_STACK_SIZE) + +#define SHSTK_LAST_ENTRY (X86_EXCEPTION_SHADOW_STACK_SIZE * \ + CONFIG_ISR_DEPTH / sizeof(arch_thread_hw_shadow_stack_t) - 1) + +#define IRQ_SHSTK_LAST_ENTRY sizeof(__z_interrupt_stacks_shstk_arr[0]) / \ + sizeof(arch_thread_hw_shadow_stack_t) - 1 + +#define X86_INTERRUPT_SSP_TABLE_INIT(n, _) \ + { \ + .ist1 = (uintptr_t)&__z_interrupt_stacks_shstk_arr[n][IRQ_SHSTK_LAST_ENTRY], \ + .ist6 = (uintptr_t)&z_x86_nmi_shadow_stack##n[SHSTK_LAST_ENTRY], \ + .ist7 = (uintptr_t)&z_x86_exception_shadow_stack##n[SHSTK_LAST_ENTRY], \ + } + #define STACK_ARRAY_IDX(n, _) n #define DEFINE_STACK_ARRAY_IDX\ diff --git a/arch/x86/include/intel64/offsets_short_arch.h b/arch/x86/include/intel64/offsets_short_arch.h index 1ffabc899c204..1637906067206 100644 --- a/arch/x86/include/intel64/offsets_short_arch.h +++ b/arch/x86/include/intel64/offsets_short_arch.h @@ -71,4 +71,15 @@ #define _thread_offset_to_cs \ (___thread_t_arch_OFFSET + ___thread_arch_t_cs_OFFSET) +#ifdef CONFIG_HW_SHADOW_STACK +#define _thread_offset_to_shstk_addr \ + (___thread_t_arch_OFFSET + ___thread_arch_t_shstk_addr_OFFSET) + +#define _thread_offset_to_shstk_base \ + (___thread_t_arch_OFFSET + ___thread_arch_t_shstk_base_OFFSET) + +#define _thread_offset_to_shstk_size \ + (___thread_t_arch_OFFSET + ___thread_arch_t_shstk_size_OFFSET) +#endif + #endif /* ZEPHYR_ARCH_X86_INCLUDE_INTEL64_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/x86/include/kernel_arch_data.h b/arch/x86/include/kernel_arch_data.h index 7b32e125d28a9..cf9b3eb0169f7 100644 --- a/arch/x86/include/kernel_arch_data.h +++ b/arch/x86/include/kernel_arch_data.h @@ -32,6 +32,7 @@ #define IV_MACHINE_CHECK 18 #define IV_SIMD_FP 19 #define IV_VIRT_EXCEPTION 20 +#define IV_CTRL_PROTECTION_EXCEPTION 21 #define IV_SECURITY_EXCEPTION 30 #define IV_IRQS 32 /* start of vectors available for IRQs */ diff --git a/arch/xtensa/core/coredump.c b/arch/xtensa/core/coredump.c index 8e4b08ee2fa04..761cf9a05ac13 100644 --- a/arch/xtensa/core/coredump.c +++ b/arch/xtensa/core/coredump.c @@ -92,6 +92,10 @@ struct xtensa_arch_block { */ static struct xtensa_arch_block arch_blk; +#if defined(CONFIG_DEBUG_COREDUMP_THREAD_STACK_TOP) +static uint32_t xtensa_coredump_fault_sp; +#endif + void arch_coredump_info_dump(const struct arch_esf *esf) { struct coredump_arch_hdr_t hdr = { @@ -127,6 +131,9 @@ void arch_coredump_info_dump(const struct arch_esf *esf) /* Set in top-level CMakeLists.txt for use with Xtensa coredump */ arch_blk.toolchain = XTENSA_TOOLCHAIN_VARIANT; +#if defined(CONFIG_DEBUG_COREDUMP_THREAD_STACK_TOP) + xtensa_coredump_fault_sp = (uint32_t)esf; +#endif __asm__ volatile("rsr.exccause %0" : "=r"(arch_blk.r.exccause)); @@ -205,3 +212,10 @@ void arch_coredump_priv_stack_dump(struct k_thread *thread) coredump_memory_dump(start_addr, end_addr); } #endif /* CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK */ + +#if defined(CONFIG_DEBUG_COREDUMP_THREAD_STACK_TOP) +uintptr_t arch_coredump_stack_ptr_get(const struct k_thread *thread) +{ + return (thread == _current) ? xtensa_coredump_fault_sp : (uintptr_t)thread->switch_handle; +} +#endif /* CONFIG_DEBUG_COREDUMP_THREAD_STACK_TOP */ diff --git a/arch/xtensa/core/prep_c.c b/arch/xtensa/core/prep_c.c index 771ad7e423077..8a399196d1bb0 100644 --- a/arch/xtensa/core/prep_c.c +++ b/arch/xtensa/core/prep_c.c @@ -4,9 +4,11 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include +#include +#include #include -#include +#include +#include extern FUNC_NORETURN void z_cstart(void); @@ -27,7 +29,7 @@ BUILD_ASSERT(CONFIG_DCACHE_LINE_SIZE == XCHAL_DCACHE_LINESIZE); * This routine prepares for the execution of and runs C code. * */ -void z_prep_c(void) +FUNC_NORETURN void z_prep_c(void) { #if defined(CONFIG_SOC_PREP_HOOK) soc_prep_hook(); diff --git a/arch/xtensa/core/vector_handlers.c b/arch/xtensa/core/vector_handlers.c index 7ef4e4a79958d..2f4a7012a1eff 100644 --- a/arch/xtensa/core/vector_handlers.c +++ b/arch/xtensa/core/vector_handlers.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -653,7 +652,7 @@ void *xtensa_excint1_c(void *esf) * this code. * * Another intentionally ill is from xtensa_arch_kernel_oops. - * Kernel OOPS has to be explicity raised so we can simply + * Kernel OOPS has to be explicitly raised so we can simply * set the reason and continue. */ if (cause == EXCCAUSE_ILLEGAL) { diff --git a/boards/96boards/nitrogen/doc/index.rst b/boards/96boards/nitrogen/doc/index.rst index df3d0236ca596..3984192308681 100644 --- a/boards/96boards/nitrogen/doc/index.rst +++ b/boards/96boards/nitrogen/doc/index.rst @@ -311,7 +311,7 @@ You can debug an application in the usual way. Here is an example for the :goals: debug .. _pyOCD: - https://github.com/mbedmicro/pyOCD + https://github.com/pyocd/pyOCD .. _CMSIS DAP: https://developer.mbed.org/handbook/CMSIS-DAP @@ -323,7 +323,7 @@ You can debug an application in the usual way. Here is an example for the http://wiki.seeed.cc/BLE_Nitrogen/ .. _pyOCD issue 259: - https://github.com/mbedmicro/pyOCD/issues/259 + https://github.com/pyocd/pyOCD/issues/259 .. _96Boards IE Specification: https://linaro.co/ie-specification diff --git a/boards/actinius/icarus_som_dk/arduino_connector.dtsi b/boards/actinius/icarus_som_dk/arduino_connector.dtsi index a22fe22a37b69..67011b7181f4e 100644 --- a/boards/actinius/icarus_som_dk/arduino_connector.dtsi +++ b/boards/actinius/icarus_som_dk/arduino_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: arduino_connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 15 0>, /* A0 */ - <1 0 &gpio0 16 0>, /* A1 */ - <2 0 &gpio0 17 0>, /* A2 */ - <3 0 &gpio0 18 0>, /* A3 */ - <4 0 &gpio0 19 0>, /* A4 */ - <5 0 &gpio0 20 0>, /* A5 */ - <6 0 &gpio0 4 0>, /* D0 */ - <7 0 &gpio0 5 0>, /* D1 */ - <8 0 &gpio0 2 0>, /* D2 */ - <9 0 &gpio0 1 0>, /* D3 */ - <10 0 &gpio0 23 0>, /* D4 */ - <11 0 &gpio0 0 0>, /* D5 */ - <12 0 &gpio0 26 0>, /* D6 */ - <13 0 &gpio0 27 0>, /* D7 */ - <14 0 &gpio0 30 0>, /* D8 */ - <15 0 &gpio0 31 0>, /* D9 */ - <16 0 &gpio0 7 0>, /* D10 */ - <17 0 &gpio0 13 0>, /* D11 */ - <18 0 &gpio0 14 0>, /* D12 */ - <19 0 &gpio0 3 0>, /* D13 */ - <20 0 &gpio0 10 0>, /* SDA */ - <21 0 &gpio0 11 0>; /* SCL */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog_connector { diff --git a/boards/adafruit/feather_canbus_rp2040/Kconfig b/boards/adafruit/feather_canbus_rp2040/Kconfig new file mode 100644 index 0000000000000..12a5ea08677f9 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_CANBUS_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/adafruit/feather_canbus_rp2040/Kconfig.adafruit_feather_canbus_rp2040 b/boards/adafruit/feather_canbus_rp2040/Kconfig.adafruit_feather_canbus_rp2040 new file mode 100644 index 0000000000000..dc1da65f17e61 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/Kconfig.adafruit_feather_canbus_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_CANBUS_RP2040 + select SOC_RP2040 diff --git a/boards/adafruit/feather_canbus_rp2040/Kconfig.defconfig b/boards/adafruit/feather_canbus_rp2040/Kconfig.defconfig new file mode 100644 index 0000000000000..06e39958ee6f4 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER_CANBUS_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_FEATHER_CANBUS_RP2040 diff --git a/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040-pinctrl.dtsi b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040-pinctrl.dtsi new file mode 100644 index 0000000000000..c1b3f17618379 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040-pinctrl.dtsi @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = ; + input-enable; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + spi1_default: spi1_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + + group3 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + group1 { + pinmux = ; + }; + }; +}; diff --git a/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts new file mode 100644 index 0000000000000..b63dd3cce29a5 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "adafruit_feather_canbus_rp2040-pinctrl.dtsi" +#include "feather_connector.dtsi" + +/ { + model = "Adafruit Feather RP2040 Canbus"; + compatible = "adafruit,feather_canbus_rp2040"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + zephyr,canbus = &mcp2515; + }; + + aliases { + watchdog0 = &wdt0; + led-strip = &ws2812; + led0 = &red_led; + sw0 = &user_button; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "User"; + gpios = <&gpio0 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + stemma_connector: stemma_connector { + compatible = "stemma-qt-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 3 0>, /* SCL */ + <1 0 &gpio0 2 0>; /* SDA */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(8)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 8 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(8) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; + + /* Power to Neopixel */ + neopixel-power-enable { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + + mcp2515: mcp2515@0 { + compatible = "microchip,mcp2515"; + spi-max-frequency = <1000000>; + int-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + status = "okay"; + reg = <0x0>; + osc-freq = <16000000>; + + can-transceiver { + max-bitrate = <1000000>; + }; + }; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pio0 { + status = "okay"; + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.yaml b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.yaml new file mode 100644 index 0000000000000..35485ab707494 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.yaml @@ -0,0 +1,23 @@ +identifier: adafruit_feather_canbus_rp2040 +name: Adafruit Feather RP2040 Adalogger +type: mcu +arch: arm +flash: 8192 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - can + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040_defconfig b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040_defconfig new file mode 100644 index 0000000000000..656d975cf1127 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/adafruit/feather_canbus_rp2040/board.cmake b/boards/adafruit/feather_canbus_rp2040/board.cmake new file mode 100644 index 0000000000000..affc290a869d6 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 TOKITA Hiroshi + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/adafruit/feather_canbus_rp2040/board.yml b/boards/adafruit/feather_canbus_rp2040/board.yml new file mode 100644 index 0000000000000..55fea85bd5444 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_feather_canbus_rp2040 + full_name: Feather RP2040 CAN bus + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/adafruit/feather_canbus_rp2040/doc/img/adafruit_feather_canbus_rp2040.webp b/boards/adafruit/feather_canbus_rp2040/doc/img/adafruit_feather_canbus_rp2040.webp new file mode 100644 index 0000000000000..edbd4550d3909 Binary files /dev/null and b/boards/adafruit/feather_canbus_rp2040/doc/img/adafruit_feather_canbus_rp2040.webp differ diff --git a/boards/adafruit/feather_canbus_rp2040/doc/index.rst b/boards/adafruit/feather_canbus_rp2040/doc/index.rst new file mode 100644 index 0000000000000..d9e87ad4dad30 --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/doc/index.rst @@ -0,0 +1,142 @@ +.. zephyr:board:: adafruit_feather_canbus_rp2040 + +Overview +******** + +The `Adafruit RP2040 CANBUS Feather`_ board is based on the RP2040 +microcontroller from Raspberry Pi Ltd. The board has a CAN bus +controller, and a Stemma QT connector for easy sensor usage. +It is compatible with the Feather board form factor, and has +a USB type C connector. + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 8 Mbyte QSPI flash +- 17 GPIO pins +- 4 ADC pins +- I2C +- SPI +- UART +- USB type C connector +- Reset and boot buttons +- Red LED +- RGB LED (Neopixel) +- Stemma QT I2C connector +- CAN bus controller +- Built-in lithium ion battery charger + + +Default Zephyr Peripheral Mapping +================================= + +.. rst-class:: rst-columns + + - A0 ADC0 : GPIO26 + - A1 ADC1 : GPIO27 + - A2 ADC2 : GPIO28 + - A3 ADC3 : GPIO29 + - D24 : GPIO24 + - D25 : GPIO25 + - SCK SPI1 SCK : GPIO14 + - MO SPI1 MOSI : GPIO15 + - MI SPI1 MISO : GPIO8 + - RX UART0 : GPIO1 + - TX UART0 : GPIO0 + - D4 : GPIO4 + - SDA I2C1 : GPIO2 + - SCL I2C1 : GPIO3 + - D5 : GPIO5 + - D6 : GPIO6 + - D9 : GPIO9 + - D10 : GPIO10 + - D11 : GPIO11 + - D12 : GPIO12 + - D13 and red LED : GPIO13 + - Button BOOT : GPIO7 + - RGB LED (Neopixel) signal : GPIO21 + - RGB LED (Neopixel) power : GPIO20 + - CAN controller CS : GPIO19 + - CAN controller INTERRUPT : GPIO22 + - CAN controller RESET (not used) : GPIO18 + - CAN controller STANDBY (not used) : GPIO16 + - CAN controller TX0RTS (not used) : GPIO17 + - CAN controller RX0BF (not used) : GPIO23 + +The CAN controller is also connected to the SPI1 pins SCK, MOSI and MISO. + +See also `pinout`_ and `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The Adafruit RP2040 CANBUS Feather board does not expose +the SWDIO and SWCLK pins, so programming must be done via the USB +port. Press and hold the BOOT button, and then press the RST button, +and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board +will be reprogrammed. + +For more details on programming RP2040-based boards, see +:ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: adafruit_feather_canbus_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`led-strip`, :zephyr:code-sample:`input-dump`, +:zephyr:code-sample:`usb-cdc-acm-console` and :zephyr:code-sample:`adc_dt` samples. + +To run the :zephyr:code-sample:`can-counter` CAN sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/can/counter + :board: adafruit_feather_canbus_rp2040 + :goals: build flash + :build-args: -DCONFIG_LOOPBACK_MODE=n + +Connect the other end of the CAN cable to a CAN interface connected to your laptop. +If you are using a Linux laptop, receive the CAN frames by:: + + sudo ip link set can0 up type can bitrate 125000 + candump can0 + +Send CAN frames to control the LED on the board:: + + cansend can0 010#00 + cansend can0 010#01 + + +References +********** + +.. target-notes:: + +.. _Adafruit RP2040 CANBUS Feather: + https://learn.adafruit.com/adafruit-rp2040-can-bus-feather + +.. _pinout: + https://learn.adafruit.com/adafruit-rp2040-can-bus-feather/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-rp2040-can-bus-feather/downloads diff --git a/boards/adafruit/feather_canbus_rp2040/feather_connector.dtsi b/boards/adafruit/feather_canbus_rp2040/feather_connector.dtsi new file mode 100644 index 0000000000000..05ace79ebaefb --- /dev/null +++ b/boards/adafruit/feather_canbus_rp2040/feather_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 26 0>, /* A0 */ + <1 0 &gpio0 27 0>, /* A1 */ + <2 0 &gpio0 28 0>, /* A2 */ + <3 0 &gpio0 29 0>, /* A3 */ + <4 0 &gpio0 24 0>, /* D24 */ + <5 0 &gpio0 25 0>, /* D25 */ + <6 0 &gpio0 14 0>, /* SCK */ + <7 0 &gpio0 15 0>, /* MOSI */ + <8 0 &gpio0 8 0>, /* MISO */ + <9 0 &gpio0 1 0>, /* RX */ + <10 0 &gpio0 0 0>, /* TX */ + <11 0 &gpio0 4 0>, /* D4 */ + <12 0 &gpio0 2 0>, /* SDA */ + <13 0 &gpio0 3 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart0 {}; +feather_i2c: &i2c1 {}; +feather_spi: &spi1 {}; diff --git a/boards/adafruit/feather_esp32/Kconfig b/boards/adafruit/feather_esp32/Kconfig new file mode 100644 index 0000000000000..1efedd6b9e5fb --- /dev/null +++ b/boards/adafruit/feather_esp32/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Lena Voytek +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ADAFRUIT_FEATHER_ESP32_ESP32_PROCPU + default 256 if BOARD_ADAFRUIT_FEATHER_ESP32_ESP32_APPCPU diff --git a/boards/adafruit/feather_esp32/Kconfig.adafruit_feather_esp32 b/boards/adafruit/feather_esp32/Kconfig.adafruit_feather_esp32 new file mode 100644 index 0000000000000..46b91f8babb89 --- /dev/null +++ b/boards/adafruit/feather_esp32/Kconfig.adafruit_feather_esp32 @@ -0,0 +1,9 @@ +# Adafruit Feather ESP32 board configuration + +# Copyright (c) 2025 Lena Voytek +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_ESP32 + select SOC_ESP32_PICO_V3_02 + select SOC_ESP32_PROCPU if BOARD_ADAFRUIT_FEATHER_ESP32_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ADAFRUIT_FEATHER_ESP32_ESP32_APPCPU diff --git a/boards/adafruit/feather_esp32/adafruit_feather_esp32-pinctrl.dtsi b/boards/adafruit/feather_esp32/adafruit_feather_esp32-pinctrl.dtsi new file mode 100644 index 0000000000000..1f5d5e9586840 --- /dev/null +++ b/boards/adafruit/feather_esp32/adafruit_feather_esp32-pinctrl.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2025 Lena Voytek + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_ws2812_led: spi3_ws2812_led { + group1 { + pinmux = ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu.dts b/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu.dts new file mode 100644 index 0000000000000..3f01dbda27ab9 --- /dev/null +++ b/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "Adafruit Feather ESP32 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu.yaml b/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu.yaml new file mode 100644 index 0000000000000..423360ea7b16f --- /dev/null +++ b/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: adafruit_feather_esp32/esp32/appcpu +name: Adafruit Feather ESP32 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: adafruit diff --git a/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu_defconfig b/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu_defconfig new file mode 100644 index 0000000000000..48546641cadd6 --- /dev/null +++ b/boards/adafruit/feather_esp32/adafruit_feather_esp32_appcpu_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu.dts b/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu.dts new file mode 100644 index 0000000000000..d3760f4530686 --- /dev/null +++ b/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu.dts @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2025 Lena Voytek + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "adafruit_feather_esp32-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Adafruit Feather ESP32 PROCPU"; + compatible = "adafruit,adafruit_feather_esp32"; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + i2c-0 = &i2c0; + led-strip = &led_strip; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0: led_0 { + label = "Red-LED"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; // GPIO 38 + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; + + neopixel_power_enable { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + sda-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 20 GPIO_OPEN_DRAIN>; + +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +/* used for SK6812 */ +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + line-idle-low; + pinctrl-0 = <&spim3_ws2812_led>; + pinctrl-names = "default"; + + led_strip: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + reg = <0>; + spi-max-frequency = ; + + chain-length = <1>; + color-mapping = , + , + ; + spi-one-frame = ; + spi-zero-frame = ; + }; +}; + +&wdt0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu.yaml b/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu.yaml new file mode 100644 index 0000000000000..0c0c3fb0f1a0f --- /dev/null +++ b/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu.yaml @@ -0,0 +1,23 @@ +identifier: adafruit_feather_esp32/esp32/procpu +name: Adafruit Feather ESP32 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - nvs + - counter + - entropy + - pwm + - dma + - input + - feather_serial + - feather_i2c + - feather_spi +vendor: adafruit diff --git a/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu_defconfig b/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu_defconfig new file mode 100644 index 0000000000000..bff67f69b1af0 --- /dev/null +++ b/boards/adafruit/feather_esp32/adafruit_feather_esp32_procpu_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/adafruit/feather_esp32/board.cmake b/boards/adafruit/feather_esp32/board.cmake new file mode 100644 index 0000000000000..91b3caa2c75d5 --- /dev/null +++ b/boards/adafruit/feather_esp32/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +# the default ESP32 baud rate is not supported +board_runner_args(esp32 "--esp-baud-rate=1500000") diff --git a/boards/adafruit/feather_esp32/board.yml b/boards/adafruit/feather_esp32/board.yml new file mode 100644 index 0000000000000..24824fe1d8593 --- /dev/null +++ b/boards/adafruit/feather_esp32/board.yml @@ -0,0 +1,11 @@ +board: + name: adafruit_feather_esp32 + full_name: Adafruit Feather ESP32 + vendor: adafruit + socs: + - name: esp32 + revision: + format: number + default: "2" + revisions: + - name: "2" diff --git a/boards/adafruit/feather_esp32/doc/img/adafruit_feather_esp32.webp b/boards/adafruit/feather_esp32/doc/img/adafruit_feather_esp32.webp new file mode 100644 index 0000000000000..9f50d39efd11d Binary files /dev/null and b/boards/adafruit/feather_esp32/doc/img/adafruit_feather_esp32.webp differ diff --git a/boards/adafruit/feather_esp32/doc/index.rst b/boards/adafruit/feather_esp32/doc/index.rst new file mode 100644 index 0000000000000..9c6141ae0d7e9 --- /dev/null +++ b/boards/adafruit/feather_esp32/doc/index.rst @@ -0,0 +1,113 @@ +.. zephyr:board:: adafruit_feather_esp32 + +Overview +******** + +The Adafruit ESP32 Feather is an ESP32-based development board using the +Feather standard layout. + +It features the following integrated components: + +- ESP32-PICO-V3-02 chip (240MHz dual core, Wi-Fi + BLE) +- 520KB SRAM +- USB-C port connected to USB to Serial converter +- LiPo battery connector and charger +- Charging indicator LED and user LED +- NeoPixel RGB LED +- Reset and user buttons +- STEMMA QT I2C connector + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run +the commands below to retrieve the files. + +.. code-block:: shell + + west update + west blobs fetch hal_espressif + +Building & flashing +------------------- + +Use the standard build and flash process for this board. See +:ref:`build_an_application` and :ref:`application_run` for more details. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32/esp32/procpu + :goals: build flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +After flashing, view the serial monitor with the espressif monitor command. + +.. code-block:: shell + + west espressif monitor + +Testing +======= + +On-board LED +------------ + +Test the functionality of the user LED connected to pin 13 with the blinky +sample program. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather_esp32/esp32/procpu + :goals: build flash + +NeoPixel +-------- + +Test the on-board NeoPixel using the led_strip sample program. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip + :board: adafruit_feather_esp32/esp32/procpu + :goals: build flash + +User button +----------- + +Test the button labeled SW38 using the button input sample program. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: adafruit_feather_esp32/esp32/procpu + :goals: build flash + +Wi-Fi +----- + +Test ESP32 Wi-Fi functionality using the Wi-Fi shell module. + +.. note:: + The hal_espressif blobs must be fetched first. + +.. zephyr-app-commands:: + :zephyr-app: samples/net/wifi/shell + :board: adafruit_feather_esp32/esp32/procpu + :goals: build flash + +References +********** +- `Adafruit ESP32 Feather V2 `_ +- `Adafruit ESP32 Feather V2 Pinouts `_ +- `Adafruit ESP32 Feather V2 Schematic `_ +- `ESP32-PICO-MINI-02 Datasheet `_ (PDF) +- `STEMMA QT `_ diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts index 07536e62985df..67dad00a85d83 100644 --- a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts @@ -25,8 +25,8 @@ chosen { zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,bt-hci = &esp32_bt_hci; @@ -79,7 +79,7 @@ }; &usb_serial { - status = "disabled"; + status = "okay"; }; &uart0 { diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts index dd425efd5c226..ef025c82bd29a 100644 --- a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts @@ -27,8 +27,8 @@ chosen { zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,bt-hci = &esp32_bt_hci; @@ -126,7 +126,7 @@ }; &usb_serial { - status = "disabled"; + status = "okay"; }; &uart0 { diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml index 31369a0280cf1..2f9551d9ae007 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml @@ -7,7 +7,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - watchdog - counter diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml index 236e5aafd0732..b1e358d8ce6d9 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml @@ -7,7 +7,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - watchdog - counter diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml index 3756dc3c2a44e..8033b1a7c270a 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml @@ -7,7 +7,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - watchdog - counter diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml index c61e5ae36f93c..968b30bd6d4fd 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml @@ -7,7 +7,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - watchdog - counter diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml index 79072d2d015f1..f954fc16b41c5 100644 --- a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml @@ -15,6 +15,6 @@ supported: - i2c - pwm - spi - - usb_device + - usbd - watchdog vendor: adafruit diff --git a/boards/adafruit/itsybitsy_rp2040/Kconfig b/boards/adafruit/itsybitsy_rp2040/Kconfig new file mode 100644 index 0000000000000..d283fb10b61b5 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_ITSYBITSY_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/adafruit/itsybitsy_rp2040/Kconfig.adafruit_itsybitsy_rp2040 b/boards/adafruit/itsybitsy_rp2040/Kconfig.adafruit_itsybitsy_rp2040 new file mode 100644 index 0000000000000..ee3fa9b145a87 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/Kconfig.adafruit_itsybitsy_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_ITSYBITSY_RP2040 + select SOC_RP2040 diff --git a/boards/adafruit/itsybitsy_rp2040/Kconfig.defconfig b/boards/adafruit/itsybitsy_rp2040/Kconfig.defconfig new file mode 100644 index 0000000000000..7db2dc4a4a3c5 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_ITSYBITSY_RP2040 + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_ITSYBITSY_RP2040 diff --git a/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040-pinctrl.dtsi b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040-pinctrl.dtsi new file mode 100644 index 0000000000000..9747fb4d34188 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040-pinctrl.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + ws2812 { + pinmux = ; + }; + }; +}; diff --git a/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.dts b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.dts new file mode 100644 index 0000000000000..3329a0f25d472 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.dts @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "adafruit_itsybitsy_rp2040-pinctrl.dtsi" + +/ { + model = "Adafruit Itsybitsy RP2040"; + compatible = "adafruit,itsybitsy_rp2040"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + led-strip = &ws2812; + led0 = &red_led; + sw0 = &user_button; + }; + + zephyr,user { + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "User"; + gpios = <&gpio0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(8)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 8 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(8) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; + + /* Power to Neopixel */ + neopixel-power-enable { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +zephyr_i2c: &i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.yaml b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.yaml new file mode 100644 index 0000000000000..c0f2437fd49c8 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040.yaml @@ -0,0 +1,22 @@ +identifier: adafruit_itsybitsy_rp2040 +name: Adafruit Itsybitsy RP2040 +type: mcu +arch: arm +flash: 8192 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog diff --git a/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040_defconfig b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040_defconfig new file mode 100644 index 0000000000000..40aec62529fa0 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/adafruit_itsybitsy_rp2040_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PIO_RPI_PICO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/adafruit/itsybitsy_rp2040/board.cmake b/boards/adafruit/itsybitsy_rp2040/board.cmake new file mode 100644 index 0000000000000..5a702fc5e030f --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/board.cmake @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico/board.cmake + +# This configuration allows selecting what debug adapter debugging rpi_pico +# by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b rpi_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is store to CMakeCache.txt. +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/adafruit/itsybitsy_rp2040/board.yml b/boards/adafruit/itsybitsy_rp2040/board.yml new file mode 100644 index 0000000000000..34156e600a571 --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_itsybitsy_rp2040 + full_name: Itsybitsy RP2040 + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/adafruit/itsybitsy_rp2040/doc/img/adafruit_itsybitsy_rp2040.webp b/boards/adafruit/itsybitsy_rp2040/doc/img/adafruit_itsybitsy_rp2040.webp new file mode 100644 index 0000000000000..c1bb34c537abc Binary files /dev/null and b/boards/adafruit/itsybitsy_rp2040/doc/img/adafruit_itsybitsy_rp2040.webp differ diff --git a/boards/adafruit/itsybitsy_rp2040/doc/index.rst b/boards/adafruit/itsybitsy_rp2040/doc/index.rst new file mode 100644 index 0000000000000..2da890a48d1cb --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/doc/index.rst @@ -0,0 +1,124 @@ +.. zephyr:board:: adafruit_itsybitsy_rp2040 + +Overview +******** + +The `Adafruit Itsybitsy RP2040`_ board is based on the RP2040 +microcontroller from Raspberry Pi Ltd. +It is compatible with the Itsybitsy board form factor, and has +a USB micro B connector. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 8 Mbyte QSPI flash +- 12 GPIO pins +- 4 ADC pins +- SWDIO and SWCLK pins for programming and debugging +- I2C +- SPI +- UART +- USB micro B connector +- Reset and boot buttons +- Red LED +- RGB LED (Neopixel) + + +Default Zephyr Peripheral Mapping +================================= + +.. rst-class:: rst-columns + + - A0 ADC0 : GPIO26 + - A1 ADC1 : GPIO27 + - A2 ADC2 : GPIO28 + - A3 ADC3 : GPIO29 + - D24: GPIO24 + - D25: GPIO25 + - SCK SPI0 SCK : GPIO18 + - MO SPI0 MOSI : GPIO19 + - MI SPI0 MISO : GPIO20 + - D2 : GPIO12 + - ENABLE : - + - SWDIO : - + - SWCLK : - + - D3 : GPIO5 + - D4 : GPIO4 + - RX UART0: GPIO1 + - TX UART0: GPIO0 + - SDA I2C1 : GPIO2 + - SCL I2C1 : GPIO3 + - D5 (5 Volt digital out): GPIO14 + - D7 : GPIO6 + - D9 : GPIO7 + - D10 : GPIO8 + - D11 : GPIO9 + - D12 : GPIO10 + - D13 and red LED : GPIO11 + - Button USBBOOT : GPIO13 + - RGB LED (Neopixel) signal : GPIO17 + - RGB LED (Neopixel) power : GPIO16 + +See also `pinout`_ and `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. +Press and hold the BOOT button, and then press the RST button, +and the device will appear as a USB mass storage unit. +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board +will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pins. +Then a separate programming hardware tool is required, and +for example the :command:`openocd` software is used. Typically the +``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` +values should be set when building, and the ``--runner openocd`` +argument should be used when flashing. +For more details on programming RP2040-based boards, see +:ref:`rpi_pico_programming_and_debugging`. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: adafruit_itsybitsy_rp2040 + :goals: build flash + +Try also the :zephyr:code-sample:`hello_world`, :zephyr:code-sample:`led-strip`, +:zephyr:code-sample:`input-dump`, :zephyr:code-sample:`usb-cdc-acm-console` and +:zephyr:code-sample:`adc_dt` samples. + + +References +********** + +.. target-notes:: + +.. _Adafruit Itsybitsy RP2040: + https://learn.adafruit.com/adafruit-itsybitsy-rp2040 + +.. _pinout: + https://learn.adafruit.com/adafruit-itsybitsy-rp2040/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-itsybitsy-rp2040/downloads diff --git a/boards/adafruit/itsybitsy_rp2040/support/openocd.cfg b/boards/adafruit/itsybitsy_rp2040/support/openocd.cfg new file mode 100644 index 0000000000000..34ab592b1861d --- /dev/null +++ b/boards/adafruit/itsybitsy_rp2040/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts index f0aa1093431c5..d6a84d7d2ab84 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.dts +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -60,28 +61,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio3 0 0>, /* A0 */ - <1 0 &gpio3 1 0>, /* A1 */ - <2 0 &gpio3 2 0>, /* A2 */ - <3 0 &gpio3 3 0>, /* A3 */ - <4 0 &gpio3 4 0>, /* A4 */ - <5 0 &gpio3 5 0>, /* A5 */ - <6 0 &gpio2 14 0>, /* D0 */ - <7 0 &gpio2 16 0>, /* D1 */ - <8 0 &gpio2 13 0>, /* D2 */ - <9 0 &gpio2 15 0>, /* D3 */ - <10 0 &gpio0 8 0>, /* D4 */ - <11 0 &gpio0 7 0>, /* D5 */ - <12 0 &gpio1 24 0>, /* D6 */ - <13 0 &gpio1 25 0>, /* D7 */ - <14 0 &gpio1 31 0>, /* D8 */ - <15 0 &gpio1 30 0>, /* D9 */ - <16 0 &gpio1 23 0>, /* D10 */ - <17 0 &gpio1 29 0>, /* D11 */ - <18 0 &gpio1 28 0>, /* D12 */ - <19 0 &gpio1 26 0>, /* D13 */ - <20 0 &gpio2 17 0>, /* D14 */ - <21 0 &gpio2 18 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; pmod_header: pmod-header { diff --git a/boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi b/boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi index ffea9d90e4808..b21a685729d97 100644 --- a/boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi +++ b/boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0/D14 */ - <1 0 &gpioc 1 0>, /* A1/D15 */ - <2 0 &gpioc 2 0>, /* A2/D16 */ - <3 0 &gpioc 3 0>, /* A3/D17 */ - <4 0 &gpioc 4 0>, /* A4/D18 */ - <5 0 &gpioc 5 0>, /* A5/D19 */ - <6 0 &gpioa 0 0>, /* D0 */ - <7 0 &gpioa 1 0>, /* D1 */ - <8 0 &gpioa 2 0>, /* D2 */ - <9 0 &gpiod 2 0>, /* D3 */ - <10 0 &gpiod 6 0>, /* D4 */ - <11 0 &gpiob 7 0>, /* D5 */ - <12 0 &gpiob 8 0>, /* D6 */ - <13 0 &gpiob 9 0>, /* D7 */ - <14 0 &gpiob 6 0>, /* D8 */ - <15 0 &gpiob 5 0>, /* D9 */ - <16 0 &gpiog 12 0>, /* D10 */ - <17 0 &gpioc 12 0>, /* D11 */ - <18 0 &gpioc 11 0>, /* D12 */ - <19 0 &gpioc 10 0>, /* D13 */ - <20 0 &gpioc 0 0>, /* D14 */ - <21 0 &gpioc 1 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/adi/max32657evkit/doc/index.rst b/boards/adi/max32657evkit/doc/index.rst index e96410f6a1e18..ded0c6c239bc0 100644 --- a/boards/adi/max32657evkit/doc/index.rst +++ b/boards/adi/max32657evkit/doc/index.rst @@ -478,7 +478,7 @@ by non-secure. All others is going to be accessible by NS world. endif() -As an alternative method (which recommended) user can configurate ownership peripheral by +As an alternative method (which recommended) user can configure ownership peripheral by an cmake overlay file too without touching TF-M source files. For this path create ``s_ns_access_overlay.cmake`` file under your project root folder and put peripheral/memory you would like to be accessible by secure world. diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst index cc3d42c03a98f..32135be01292f 100644 --- a/boards/adi/max32662evkit/doc/index.rst +++ b/boards/adi/max32662evkit/doc/index.rst @@ -104,7 +104,7 @@ Connections and IOs | JP4 | I2C1_SDA_PU | +-----------+ | +-------------------------------------------------------------------------------+ | | | | | 1-2 | | | Connects the pull-up to I2C1A_SDA (P0.9); sourced by V_AUX. | | | | | +-----------+ | +-------------------------------------------------------------------------------+ | -| | | | Oepn | | | Disconnects the pull-up from I2C1A_SDA (P0.9); sourced by V_AUX. | | +| | | | Open | | | Disconnects the pull-up from I2C1A_SDA (P0.9); sourced by V_AUX. | | | | | +-----------+ | +-------------------------------------------------------------------------------+ | | | | | | +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts index 58a71b0917b4b..07dad12a1e1e6 100644 --- a/boards/adi/max32662evkit/max32662evkit.dts +++ b/boards/adi/max32662evkit/max32662evkit.dts @@ -10,7 +10,6 @@ #include #include #include -#include #include / { diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts index a04fcd6a4e897..47695227c2f15 100644 --- a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts @@ -10,7 +10,6 @@ #include #include #include -#include / { model = "Analog Devices MAX32666EVKIT"; diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts index 5aa45a1c5ce2a..523b5bba1d104 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts @@ -10,7 +10,6 @@ #include #include #include -#include / { model = "Analog Devices MAX32666FTHR"; diff --git a/boards/adi/max32675evkit/max32675evkit.dts b/boards/adi/max32675evkit/max32675evkit.dts index 3c5bfccd8b59c..eeed02741b4cc 100644 --- a/boards/adi/max32675evkit/max32675evkit.dts +++ b/boards/adi/max32675evkit/max32675evkit.dts @@ -10,7 +10,6 @@ #include #include #include -#include / { model = "Analog Devices MAX32675EVKIT"; diff --git a/boards/adi/sdp_k1/arduino_r3_connector.dtsi b/boards/adi/sdp_k1/arduino_r3_connector.dtsi index 53c9a87117382..d308a9cf0053d 100644 --- a/boards/adi/sdp_k1/arduino_r3_connector.dtsi +++ b/boards/adi/sdp_k1/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 2 0>, /* A0 */ - <1 0 &gpioa 4 0>, /* A1 */ - <2 0 &gpioa 6 0>, /* A2 */ - <3 0 &gpioc 1 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpioa 1 0>, /* D0 */ - <7 0 &gpioa 0 0>, /* D1 */ - <8 0 &gpiog 7 0>, /* D2 */ - <9 0 &gpiod 12 0>, /* D3 */ - <10 0 &gpiog 9 0>, /* D4 */ - <11 0 &gpioa 11 0>, /* D5 */ - <12 0 &gpioa 10 0>, /* D6 */ - <13 0 &gpiog 10 0>, /* D7 */ - <14 0 &gpiog 11 0>, /* D8 */ - <15 0 &gpiob 15 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpiob 4 0>, /* D12 */ - <19 0 &gpiob 3 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/aithinker/ai_m62_12f/ai_m62_12f.dts b/boards/aithinker/ai_m62_12f/ai_m62_12f.dts index 9801310d9c292..c9b53f78b1954 100644 --- a/boards/aithinker/ai_m62_12f/ai_m62_12f.dts +++ b/boards/aithinker/ai_m62_12f/ai_m62_12f.dts @@ -21,6 +21,49 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; }; + + aliases { + led0 = &blue_led; + sw0 = &button_0; + }; + + leds { + compatible = "gpio-leds"; + + blue_led: led_0 { + gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + label = "Blue - LED0"; + }; + + green_led: led_1 { + gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + label = "Green - LED1"; + }; + + red_led: led_2 { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + label = "Red - LED2"; + }; + + white_led: led_3 { + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + label = "White - LED3"; + }; + + warmwhite_led: led_4 { + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + label = "Warm White - LED4"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button_0: sw0 { + gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH)>; + zephyr,code = ; + }; + }; }; &cpu0 { @@ -61,3 +104,7 @@ pinctrl-1 = <&uart0_sleep>; pinctrl-names = "default", "sleep"; }; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.yaml b/boards/ambiq/apollo3_evb/apollo3_evb.yaml index 048f2ed0a72ca..4363de7177fdf 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.yaml +++ b/boards/ambiq/apollo3_evb/apollo3_evb.yaml @@ -15,6 +15,7 @@ supported: - gpio - spi - i2c + - logging testing: ignore_tags: - net diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml b/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml index 2a490611cae3c..c5ea5b0039ac3 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.yaml @@ -16,6 +16,7 @@ supported: - spi - i2c - mspi + - logging testing: ignore_tags: - net diff --git a/boards/amd/kv260_r5/doc/index.rst b/boards/amd/kv260_r5/doc/index.rst index d939718e58aa4..1750e1e406b31 100644 --- a/boards/amd/kv260_r5/doc/index.rst +++ b/boards/amd/kv260_r5/doc/index.rst @@ -66,7 +66,7 @@ remoteproc support, it is based around 5.15 Xilinx maintained kernel, as describ https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#PetaLinux The other option is to use the reference image from the openAMP project, the link -below points, betweem the options, to the kv260 target: +below points, between the options, to the kv260 target: https://github.com/OpenAMP/openamp-ci-builds/releases/tag/v2022.12 diff --git a/boards/amd/kv260_r5/kv260_r5.dts b/boards/amd/kv260_r5/kv260_r5.dts index 53ec1923e5d0c..d1b80928ac1a2 100644 --- a/boards/amd/kv260_r5/kv260_r5.dts +++ b/boards/amd/kv260_r5/kv260_r5.dts @@ -12,6 +12,11 @@ model = "KV260 Cortex-R5"; compatible = "xlnx,zynqmp-r5"; + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 DT_SIZE_M(64)>; + }; + chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; @@ -40,7 +45,7 @@ &ttc0 { status = "okay"; - clock-frequency = <5000000>; + clock-frequency = <100000000>; }; &psgpio { diff --git a/boards/amd/versalnet_apu/CMakeLists.txt b/boards/amd/versalnet_apu/CMakeLists.txt new file mode 100644 index 0000000000000..bd0a687ea487e --- /dev/null +++ b/boards/amd/versalnet_apu/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# + +find_package(Dtc 1.4.6 REQUIRED) + +# Check if the board-specific qemu.dts file exists +if(EXISTS "${BOARD_DIR}/${BOARD}-qemu.dts") + # Ensure DTC executable is available + if(DTC_FOUND) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${DTC} -I dts -O dtb -q "${BOARD_DIR}/${BOARD}-qemu.dts" -o "${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb" + ) + else() + message(FATAL_ERROR "DTC not found, but required for compiling ${BOARD}-qemu.dts") + endif() +endif() diff --git a/boards/amd/versalnet_apu/Kconfig.versalnet_apu b/boards/amd/versalnet_apu/Kconfig.versalnet_apu new file mode 100644 index 0000000000000..feb28a17b275f --- /dev/null +++ b/boards/amd/versalnet_apu/Kconfig.versalnet_apu @@ -0,0 +1,8 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_VERSALNET_APU + select SOC_AMD_VERSALNET_APU diff --git a/boards/amd/versalnet_apu/board.cmake b/boards/amd/versalnet_apu/board.cmake new file mode 100644 index 0000000000000..c086f6706de16 --- /dev/null +++ b/boards/amd/versalnet_apu/board.cmake @@ -0,0 +1,22 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH xilinx-aarch64) +set(QEMU_CPU_TYPE_${ARCH} cortexa78) + +set(QEMU_FLAGS_${ARCH} + -machine arm-generic-fdt + -hw-dtb ${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb + -device loader,addr=0xEC200300,data=0x3EE,data-len=4 -device loader,addr=0xEC200300,data=0x3DD,data-len=4 + -nographic + -m 2g +) + +set(QEMU_KERNEL_OPTION + -device loader,cpu-num=0,file=\$ +) diff --git a/boards/amd/versalnet_apu/board.yml b/boards/amd/versalnet_apu/board.yml new file mode 100644 index 0000000000000..230690e7c71c1 --- /dev/null +++ b/boards/amd/versalnet_apu/board.yml @@ -0,0 +1,5 @@ +board: + name: versalnet_apu + vendor: amd + socs: + - name: amd_versalnet_apu diff --git a/boards/amd/versalnet_apu/doc/index.rst b/boards/amd/versalnet_apu/doc/index.rst new file mode 100644 index 0000000000000..23e160649de47 --- /dev/null +++ b/boards/amd/versalnet_apu/doc/index.rst @@ -0,0 +1,74 @@ +.. zephyr:board:: versalnet_apu + +Overview +******** +This configuration provides support for the APU(A78), ARM processing unit on AMD +Versal Net SOC, it can operate as following: + +* Four independent A78 clusters each having 4 A78 cores + +This processing unit is based on an ARM Cortex-A78 CPU, it also enables the following devices: + +* ARM GIC v3 Interrupt Controller +* Global Timer Counter +* SBSA UART + +Hardware +******** +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======= +System Timer +------------ + +This board configuration uses a system timer tick frequency of 100 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +on-chip UART0. + +Memories +-------- + +Although Flash, DDR and OCM memory regions are defined in the DTS file, +all the code plus data of the application will be loaded in the sram0 region, +which points to the DDR memory. The ocm0 memory area is currently available +for usage, although nothing is placed there by default. + +Known Problems or Limitations +============================= + +The following platform features are unsupported: + +* Only the first cpu in the first cluster of the A78 subsystem is supported. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: versalnet_apu + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! versalnet_apu/amd_versalnet_apu + + +References +********** + +1. ARMv8‑A Architecture Reference Manual (ARM DDI 0487) +2. Arm Cortex‑A78 Core Technical Reference Manual (Doc ID 101430) diff --git a/boards/amd/versalnet_apu/support/xsdb.cfg b/boards/amd/versalnet_apu/support/xsdb.cfg new file mode 100644 index 0000000000000..323c22e188234 --- /dev/null +++ b/boards/amd/versalnet_apu/support/xsdb.cfg @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +proc load_image args { + set elf_file [lindex $args 0] + set pdi_file [lindex $args 1] + set bl31_file [lindex $args 2] + + if { [info exists ::env(HW_SERVER_URL)] } { + connect -url $::env(HW_SERVER_URL) + } else { + connect + } + + device program $pdi_file + targets -set -nocase -filter {name =~ "Versal*"} + after 100 + targets -set -filter {name =~ "Cortex-A78AE*0.0"} + rst -proc + after 100 + dow -force $elf_file + dow -force $bl31_file + con + exit +} + +load_image {*}$argv diff --git a/boards/amd/versalnet_apu/versalnet_apu-qemu.dts b/boards/amd/versalnet_apu/versalnet_apu-qemu.dts new file mode 100644 index 0000000000000..7de829d9a4877 --- /dev/null +++ b/boards/amd/versalnet_apu/versalnet_apu-qemu.dts @@ -0,0 +1,5422 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + + pmc_ppu0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x246>; + phandle = <0xbe>; + }; + + pmc_ppu1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x247>; + phandle = <0xbf>; + }; + + psm_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x238>; + phandle = <0xc0>; + }; + + ddrmc_ub0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x00>; + phandle = <0xc1>; + }; + + ddrmc_ub1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x00>; + phandle = <0xc2>; + }; + + pmc_dma0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x248>; + phandle = <0x68>; + }; + + pmc_dma1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x24b>; + phandle = <0x69>; + }; + + pmc_qspi_dma_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x244>; + phandle = <0x5d>; + }; + + pmc_qspi_dma_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x244>; + phandle = <0x5b>; + }; + + apu0_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x260>; + phandle = <0xc3>; + }; + + apu0_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x260>; + phandle = <0xc4>; + }; + + apu1_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x261>; + phandle = <0xc5>; + }; + + apu1_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x261>; + phandle = <0xc6>; + }; + + rpu0_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x200>; + phandle = <0xad>; + }; + + rpu1_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x204>; + phandle = <0xb0>; + }; + + gem0_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x234>; + phandle = <0x14>; + }; + + gem0_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x234>; + phandle = <0x15>; + }; + + gem1_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x235>; + phandle = <0x19>; + }; + + gem1_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x235>; + phandle = <0x1a>; + }; + + ospi_dma_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x245>; + phandle = <0x61>; + }; + + ospi_dma_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x245>; + phandle = <0x5c>; + }; + + sd0_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x242>; + phandle = <0x57>; + }; + + sd0_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x242>; + phandle = <0x58>; + }; + + sd1_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x243>; + phandle = <0x59>; + }; + + sd1_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x243>; + phandle = <0x5a>; + }; + + usb0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x230>; + phandle = <0x1c>; + }; + + amba_root@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0xffff>; + interrupt-map = <0x00 0x00 0x00 0x01 0x00 0x00 0x04 0x00 0x00 0x01 0x01 0x00 0x01 +0x04 0x00 0x00 0x02 0x01 0x00 0x02 0x04 0x00 0x00 0x03 0x01 0x00 0x03 0x04 0x00 0x00 0x04 0x01 +0x00 0x04 0x04 0x00 0x00 0x05 0x01 0x00 0x05 0x04 0x00 0x00 0x06 0x01 0x00 0x06 0x04 0x00 +0x00 0x07 0x01 0x00 0x07 0x04 0x00 0x00 0x08 0x01 0x00 0x08 0x04 0x00 0x00 0x09 0x01 0x00 +0x09 0x04 0x00 0x00 0x0a 0x01 0x00 0x0a 0x04 0x00 0x00 0x0b 0x01 0x00 0x0b 0x04 0x00 0x00 +0x0c 0x01 0x00 0x0c 0x04 0x00 0x00 0x0d 0x01 0x00 0x0d 0x04 0x00 0x00 0x0e 0x01 0x00 0x0e +0x04 0x00 0x00 0x0f 0x01 0x00 0x0f 0x04 0x00 0x00 0x10 0x01 0x00 0x10 0x04 0x00 0x00 0x11 +0x01 0x00 0x11 0x04 0x00 0x00 0x12 0x01 0x00 0x12 0x04 0x00 0x00 0x13 0x01 0x00 0x13 0x04 +0x00 0x00 0x14 0x01 0x00 0x14 0x04 0x00 0x00 0x15 0x01 0x00 0x15 0x04 0x00 0x00 0x16 0x01 +0x00 0x16 0x04 0x00 0x00 0x17 0x01 0x00 0x17 0x04 0x00 0x00 0x18 0x01 0x00 0x18 0x04 0x00 +0x00 0x19 0x01 0x00 0x19 0x04 0x00 0x00 0x1a 0x01 0x00 0x1a 0x04 0x00 0x00 0x1b 0x01 0x00 +0x1b 0x04 0x00 0x00 0x1c 0x01 0x00 0x1c 0x04 0x00 0x00 0x1d 0x01 0x00 0x1d 0x04 0x00 0x00 +0x1e 0x01 0x00 0x1e 0x04 0x00 0x00 0x1f 0x01 0x00 0x1f 0x04 0x00 0x00 0x20 0x01 0x00 0x20 +0x04 0x00 0x00 0x21 0x01 0x00 0x21 0x04 0x00 0x00 0x22 0x01 0x00 0x22 0x04 0x00 0x00 0x23 +0x01 0x00 0x23 0x04 0x00 0x00 0x24 0x01 0x00 0x24 0x04 0x00 0x00 0x25 0x01 0x00 0x25 0x04 +0x00 0x00 0x26 0x01 0x00 0x26 0x04 0x00 0x00 0x27 0x01 0x00 0x27 0x04 0x00 0x00 0x28 0x01 +0x00 0x28 0x04 0x00 0x00 0x29 0x01 0x00 0x29 0x04 0x00 0x00 0x2a 0x01 0x00 0x2a 0x04 0x00 +0x00 0x2b 0x01 0x00 0x2b 0x04 0x00 0x00 0x2c 0x01 0x00 0x2c 0x04 0x00 0x00 0x2d 0x01 0x00 +0x2d 0x04 0x00 0x00 0x2e 0x01 0x00 0x2e 0x04 0x00 0x00 0x2f 0x01 0x00 0x2f 0x04 0x00 0x00 +0x30 0x01 0x00 0x30 0x04 0x00 0x00 0x31 0x01 0x00 0x31 0x04 0x00 0x00 0x32 0x01 0x00 0x32 +0x04 0x00 0x00 0x33 0x01 0x00 0x33 0x04 0x00 0x00 0x34 0x01 0x00 0x34 0x04 0x00 0x00 0x35 +0x01 0x00 0x35 0x04 0x00 0x00 0x36 0x01 0x00 0x36 0x04 0x00 0x00 0x37 0x01 0x00 0x37 0x04 +0x00 0x00 0x38 0x01 0x00 0x38 0x04 0x00 0x00 0x39 0x01 0x00 0x39 0x04 0x00 0x00 0x3a 0x01 +0x00 0x3a 0x04 0x00 0x00 0x3b 0x01 0x00 0x3b 0x04 0x00 0x00 0x3c 0x01 0x00 0x3c 0x04 0x00 +0x00 0x3d 0x01 0x00 0x3d 0x04 0x00 0x00 0x3e 0x01 0x00 0x3e 0x04 0x00 0x00 0x3f 0x01 0x00 +0x3f 0x04 0x00 0x00 0x40 0x01 0x00 0x40 0x04 0x00 0x00 0x41 0x01 0x00 0x41 0x04 0x00 0x00 +0x42 0x01 0x00 0x42 0x04 0x00 0x00 0x43 0x01 0x00 0x43 0x04 0x00 0x00 0x44 0x01 0x00 0x44 +0x04 0x00 0x00 0x45 0x01 0x00 0x45 0x04 0x00 0x00 0x46 0x01 0x00 0x46 0x04 0x00 0x00 0x47 +0x01 0x00 0x47 0x04 0x00 0x00 0x48 0x01 0x00 0x48 0x04 0x00 0x00 0x49 0x01 0x00 0x49 0x04 +0x00 0x00 0x4a 0x01 0x00 0x4a 0x04 0x00 0x00 0x4b 0x01 0x00 0x4b 0x04 0x00 0x00 0x4c 0x01 +0x00 0x4c 0x04 0x00 0x00 0x4d 0x01 0x00 0x4d 0x04 0x00 0x00 0x4e 0x01 0x00 0x4e 0x04 0x00 +0x00 0x4f 0x01 0x00 0x4f 0x04 0x00 0x00 0x50 0x01 0x00 0x50 0x04 0x00 0x00 0x51 0x01 0x00 +0x51 0x04 0x00 0x00 0x52 0x01 0x00 0x52 0x04 0x00 0x00 0x53 0x01 0x00 0x53 0x04 0x00 0x00 +0x54 0x01 0x00 0x54 0x04 0x00 0x00 0x55 0x01 0x00 0x55 0x04 0x00 0x00 0x56 0x01 0x00 0x56 +0x04 0x00 0x00 0x57 0x01 0x00 0x57 0x04 0x00 0x00 0x58 0x01 0x00 0x58 0x04 0x00 0x00 0x59 +0x01 0x00 0x59 0x04 0x00 0x00 0x5a 0x01 0x00 0x5a 0x04 0x00 0x00 0x5b 0x01 0x00 0x5b 0x04 +0x00 0x00 0x5c 0x01 0x00 0x5c 0x04 0x00 0x00 0x5d 0x01 0x00 0x5d 0x04 0x00 0x00 0x5e 0x01 +0x00 0x5e 0x04 0x00 0x00 0x5f 0x01 0x00 0x5f 0x04 0x00 0x00 0x60 0x01 0x00 0x60 0x04 0x00 +0x00 0x61 0x01 0x00 0x61 0x04 0x00 0x00 0x62 0x01 0x00 0x62 0x04 0x00 0x00 0x63 0x01 0x00 +0x63 0x04 0x00 0x00 0x64 0x01 0x00 0x64 0x04 0x00 0x00 0x65 0x01 0x00 0x65 0x04 0x00 0x00 +0x66 0x01 0x00 0x66 0x04 0x00 0x00 0x67 0x01 0x00 0x67 0x04 0x00 0x00 0x68 0x01 0x00 0x68 +0x04 0x00 0x00 0x69 0x01 0x00 0x69 0x04 0x00 0x00 0x6a 0x01 0x00 0x6a 0x04 0x00 0x00 0x6b +0x01 0x00 0x6b 0x04 0x00 0x00 0x6c 0x01 0x00 0x6c 0x04 0x00 0x00 0x6d 0x01 0x00 0x6d 0x04 +0x00 0x00 0x6e 0x01 0x00 0x6e 0x04 0x00 0x00 0x6f 0x01 0x00 0x6f 0x04 0x00 0x00 0x70 0x01 +0x00 0x70 0x04 0x00 0x00 0x71 0x01 0x00 0x71 0x04 0x00 0x00 0x72 0x01 0x00 0x72 0x04 0x00 +0x00 0x73 0x01 0x00 0x73 0x04 0x00 0x00 0x74 0x01 0x00 0x74 0x04 0x00 0x00 0x75 0x01 0x00 +0x75 0x04 0x00 0x00 0x76 0x01 0x00 0x76 0x04 0x00 0x00 0x77 0x01 0x00 0x77 0x04 0x00 0x00 +0x78 0x01 0x00 0x78 0x04 0x00 0x00 0x79 0x01 0x00 0x79 0x04 0x00 0x00 0x7a 0x01 0x00 0x7a +0x04 0x00 0x00 0x7b 0x01 0x00 0x7b 0x04 0x00 0x00 0x7c 0x01 0x00 0x7c 0x04 0x00 0x00 0x7d +0x01 0x00 0x7d 0x04 0x00 0x00 0x7e 0x01 0x00 0x7e 0x04 0x00 0x00 0x7f 0x01 0x00 0x7f 0x04 +0x00 0x00 0x80 0x01 0x00 0x80 0x04 0x00 0x00 0x81 0x01 0x00 0x81 0x04 0x00 0x00 0x82 0x01 +0x00 0x82 0x04 0x00 0x00 0x83 0x01 0x00 0x83 0x04 0x00 0x00 0x84 0x01 0x00 0x84 0x04 0x00 +0x00 0x85 0x01 0x00 0x85 0x04 0x00 0x00 0x86 0x01 0x00 0x86 0x04 0x00 0x00 0x87 0x01 0x00 +0x87 0x04 0x00 0x00 0x88 0x01 0x00 0x88 0x04 0x00 0x00 0x89 0x01 0x00 0x89 0x04 0x00 0x00 +0x8a 0x01 0x00 0x8a 0x04 0x00 0x00 0x8b 0x01 0x00 0x8b 0x04 0x00 0x00 0x8c 0x01 0x00 0x8c +0x04 0x00 0x00 0x8d 0x01 0x00 0x8d 0x04 0x00 0x00 0x8e 0x01 0x00 0x8e 0x04 0x00 0x00 0x8f +0x01 0x00 0x8f 0x04 0x00 0x00 0x90 0x01 0x00 0x90 0x04 0x00 0x00 0x91 0x01 0x00 0x91 0x04 +0x00 0x00 0x92 0x01 0x00 0x92 0x04 0x00 0x00 0x93 0x01 0x00 0x93 0x04 0x00 0x00 0x94 0x01 +0x00 0x94 0x04 0x00 0x00 0x95 0x01 0x00 0x95 0x04 0x00 0x00 0x96 0x01 0x00 0x96 0x04 0x00 +0x00 0x97 0x01 0x00 0x97 0x04 0x00 0x00 0x98 0x01 0x00 0x98 0x04 0x00 0x00 0x99 0x01 0x00 +0x99 0x04 0x00 0x00 0x9a 0x01 0x00 0x9a 0x04 0x00 0x00 0x9b 0x01 0x00 0x9b 0x04 0x00 0x00 +0x9c 0x01 0x00 0x9c 0x04 0x00 0x00 0x9d 0x01 0x00 0x9d 0x04 0x00 0x00 0x9e 0x01 0x00 0x9e +0x04 0x00 0x00 0x9f 0x01 0x00 0x9f 0x04 0x00 0x00 0xa0 0x01 0x00 0xa0 0x04 0x00 0x00 0xa1 +0x01 0x00 0xa1 0x04 0x00 0x00 0xa2 0x01 0x00 0xa2 0x04 0x00 0x00 0xa3 0x01 0x00 0xa3 0x04 +0x00 0x00 0xa4 0x01 0x00 0xa4 0x04 0x00 0x00 0xa5 0x01 0x00 0xa5 0x04 0x00 0x00 0xa6 0x01 +0x00 0xa6 0x04 0x00 0x00 0xa7 0x01 0x00 0xa7 0x04 0x00 0x00 0xa8 0x01 0x00 0xa8 0x04 0x00 +0x00 0xa9 0x01 0x00 0xa9 0x04 0x00 0x00 0xaa 0x01 0x00 0xaa 0x04 0x00 0x00 0xab 0x01 0x00 +0xab 0x04 0x00 0x00 0xac 0x01 0x00 0xac 0x04 0x00 0x00 0xad 0x01 0x00 0xad 0x04 0x00 0x00 +0xae 0x01 0x00 0xae 0x04 0x00 0x00 0xaf 0x01 0x00 0xaf 0x04 0x00 0x00 0xb0 0x01 0x00 0xb0 +0x04 0x00 0x00 0xb1 0x01 0x00 0xb1 0x04 0x00 0x00 0xb2 0x01 0x00 0xb2 0x04 0x00 0x00 0xb3 +0x01 0x00 0xb3 0x04 0x00 0x00 0xb4 0x01 0x00 0xb4 0x04 0x00 0x00 0xb5 0x01 0x00 0xb5 0x04 +0x00 0x00 0xb6 0x01 0x00 0xb6 0x04 0x00 0x00 0xb7 0x01 0x00 0xb7 0x04 0x00 0x00 0xb8 0x01 +0x00 0xb8 0x04 0x00 0x00 0xb9 0x01 0x00 0xb9 0x04 0x00 0x00 0xba 0x01 0x00 0xba 0x04 0x00 +0x00 0xbb 0x01 0x00 0xbb 0x04 0x00 0x00 0xbc 0x01 0x00 0xbc 0x04 0x00 0x00 0xbd 0x01 0x00 +0xbd 0x04 0x00 0x00 0xbe 0x01 0x00 0xbe 0x04 0x00 0x00 0xbf 0x01 0x00 0xbf 0x04 0x00 0x00 +0xc0 0x01 0x00 0xc0 0x04 0x00 0x00 0xc1 0x01 0x00 0xc1 0x04 0x00 0x00 0xc2 0x01 0x00 0xc2 +0x04 0x00 0x00 0xc3 0x01 0x00 0xc3 0x04 0x00 0x00 0xc4 0x01 0x00 0xc4 0x04 0x00 0x00 0xc5 +0x01 0x00 0xc5 0x04 0x00 0x00 0xc6 0x01 0x00 0xc6 0x04 0x00 0x00 0xc7 0x01 0x00 0xc7 0x04 +0x00 0x00 0xc8 0x01 0x00 0xc8 0x04 0x00 0x00 0xc9 0x01 0x00 0xc9 0x04 0x00 0x00 0xca 0x01 +0x00 0xca 0x04 0x00 0x00 0xcb 0x01 0x00 0xcb 0x04 0x00 0x00 0xcc 0x01 0x00 0xcc 0x04 0x00 +0x00 0xcd 0x01 0x00 0xcd 0x04 0x00 0x00 0xce 0x01 0x00 0xce 0x04 0x00 0x00 0xcf 0x01 0x00 +0xcf 0x04 0x00 0x00 0xd0 0x01 0x00 0xd0 0x04 0x00 0x00 0xd1 0x01 0x00 0xd1 0x04 0x00 0x00 +0xd2 0x01 0x00 0xd2 0x04 0x00 0x00 0xd3 0x01 0x00 0xd3 0x04 0x00 0x00 0xd4 0x01 0x00 0xd4 +0x04 0x00 0x00 0xd5 0x01 0x00 0xd5 0x04 0x00 0x00 0xd6 0x01 0x00 0xd6 0x04 0x00 0x00 0xd7 +0x01 0x00 0xd7 0x04 0x00 0x00 0xd8 0x01 0x00 0xd8 0x04 0x00 0x00 0xd9 0x01 0x00 0xd9 0x04 +0x00 0x00 0xda 0x01 0x00 0xda 0x04 0x00 0x00 0xdb 0x01 0x00 0xdb 0x04 0x00 0x00 0xdc 0x01 +0x00 0xdc 0x04 0x00 0x00 0xdd 0x01 0x00 0xdd 0x04 0x00 0x00 0xa0 0x01 0x00 0xa0 0x04 0x00 +0x00 0x00 0x02 0x00 0x00 0x04 0x00 0x00 0x01 0x02 0x00 0x01 0x04 0x00 0x00 0x02 0x02 0x00 +0x02 0x04 0x00 0x00 0x03 0x02 0x00 0x03 0x04 0x00 0x00 0x04 0x02 0x00 0x04 0x04 0x00 0x00 +0x05 0x02 0x00 0x05 0x04 0x00 0x00 0x06 0x02 0x00 0x06 0x04 0x00 0x00 0x07 0x02 0x00 0x07 +0x04 0x00 0x00 0x08 0x02 0x00 0x08 0x04 0x00 0x00 0x09 0x02 0x00 0x09 0x04 0x00 0x00 0x0a +0x02 0x00 0x0a 0x04 0x00 0x00 0x0b 0x02 0x00 0x0b 0x04 0x00 0x00 0x0c 0x02 0x00 0x0c 0x04 +0x00 0x00 0x0d 0x02 0x00 0x0d 0x04 0x00 0x00 0x0e 0x02 0x00 0x0e 0x04 0x00 0x00 0x0f 0x02 +0x00 0x0f 0x04 0x00 0x00 0x10 0x02 0x00 0x10 0x04 0x00 0x00 0x11 0x02 0x00 0x11 0x04 0x00 +0x00 0x12 0x02 0x00 0x12 0x04 0x00 0x00 0x13 0x02 0x00 0x13 0x04 0x00 0x00 0x14 0x02 0x00 +0x14 0x04 0x00 0x00 0x15 0x02 0x00 0x15 0x04 0x00 0x00 0x16 0x02 0x00 0x16 0x04 0x00 0x00 +0x17 0x02 0x00 0x17 0x04 0x00 0x00 0x18 0x02 0x00 0x18 0x04 0x00 0x00 0x19 0x02 0x00 0x19 +0x04 0x00 0x00 0x1a 0x02 0x00 0x1a 0x04 0x00 0x00 0x1b 0x02 0x00 0x1b 0x04 0x00 0x00 0x1c +0x02 0x00 0x1c 0x04 0x00 0x00 0x1d 0x02 0x00 0x1d 0x04 0x00 0x00 0x1e 0x02 0x00 0x1e 0x04 +0x00 0x00 0x1f 0x02 0x00 0x1f 0x04 0x00 0x00 0x20 0x02 0x00 0x20 0x04 0x00 0x00 0x21 0x02 +0x00 0x21 0x04 0x00 0x00 0x22 0x02 0x00 0x22 0x04 0x00 0x00 0x23 0x02 0x00 0x23 0x04 0x00 +0x00 0x24 0x02 0x00 0x24 0x04 0x00 0x00 0x25 0x02 0x00 0x25 0x04 0x00 0x00 0x26 0x02 0x00 +0x26 0x04 0x00 0x00 0x27 0x02 0x00 0x27 0x04 0x00 0x00 0x28 0x02 0x00 0x28 0x04 0x00 0x00 +0x29 0x02 0x00 0x29 0x04 0x00 0x00 0x2a 0x02 0x00 0x2a 0x04 0x00 0x00 0x2b 0x02 0x00 0x2b +0x04 0x00 0x00 0x2c 0x02 0x00 0x2c 0x04 0x00 0x00 0x2d 0x02 0x00 0x2d 0x04 0x00 0x00 0x2e +0x02 0x00 0x2e 0x04 0x00 0x00 0x2f 0x02 0x00 0x2f 0x04 0x00 0x00 0x30 0x02 0x00 0x30 0x04 +0x00 0x00 0x31 0x02 0x00 0x31 0x04 0x00 0x00 0x32 0x02 0x00 0x32 0x04 0x00 0x00 0x33 0x02 +0x00 0x33 0x04 0x00 0x00 0x34 0x02 0x00 0x34 0x04 0x00 0x00 0x35 0x02 0x00 0x35 0x04 0x00 +0x00 0x36 0x02 0x00 0x36 0x04 0x00 0x00 0x37 0x02 0x00 0x37 0x04 0x00 0x00 0x38 0x02 0x00 +0x38 0x04 0x00 0x00 0x39 0x02 0x00 0x39 0x04 0x00 0x00 0x3a 0x02 0x00 0x3a 0x04 0x00 0x00 +0x3b 0x02 0x00 0x3b 0x04 0x00 0x00 0x3c 0x02 0x00 0x3c 0x04 0x00 0x00 0x3d 0x02 0x00 0x3d +0x04 0x00 0x00 0x3e 0x02 0x00 0x3e 0x04 0x00 0x00 0x3f 0x02 0x00 0x3f 0x04 0x00 0x00 0x40 +0x02 0x00 0x40 0x04 0x00 0x00 0x41 0x02 0x00 0x41 0x04 0x00 0x00 0x42 0x02 0x00 0x42 0x04 +0x00 0x00 0x43 0x02 0x00 0x43 0x04 0x00 0x00 0x44 0x02 0x00 0x44 0x04 0x00 0x00 0x45 0x02 +0x00 0x45 0x04 0x00 0x00 0x46 0x02 0x00 0x46 0x04 0x00 0x00 0x47 0x02 0x00 0x47 0x04 0x00 +0x00 0x48 0x02 0x00 0x48 0x04 0x00 0x00 0x49 0x02 0x00 0x49 0x04 0x00 0x00 0x4a 0x02 0x00 +0x4a 0x04 0x00 0x00 0x4b 0x02 0x00 0x4b 0x04 0x00 0x00 0x4c 0x02 0x00 0x4c 0x04 0x00 0x00 +0x4d 0x02 0x00 0x4d 0x04 0x00 0x00 0x4e 0x02 0x00 0x4e 0x04 0x00 0x00 0x4f 0x02 0x00 0x4f +0x04 0x00 0x00 0x50 0x02 0x00 0x50 0x04 0x00 0x00 0x51 0x02 0x00 0x51 0x04 0x00 0x00 0x52 +0x02 0x00 0x52 0x04 0x00 0x00 0x53 0x02 0x00 0x53 0x04 0x00 0x00 0x54 0x02 0x00 0x54 0x04 +0x00 0x00 0x55 0x02 0x00 0x55 0x04 0x00 0x00 0x56 0x02 0x00 0x56 0x04 0x00 0x00 0x57 0x02 +0x00 0x57 0x04 0x00 0x00 0x58 0x02 0x00 0x58 0x04 0x00 0x00 0x59 0x02 0x00 0x59 0x04 0x00 +0x00 0x5a 0x02 0x00 0x5a 0x04 0x00 0x00 0x5b 0x02 0x00 0x5b 0x04 0x00 0x00 0x5c 0x02 0x00 +0x5c 0x04 0x00 0x00 0x5d 0x02 0x00 0x5d 0x04 0x00 0x00 0x5e 0x02 0x00 0x5e 0x04 0x00 0x00 +0x5f 0x02 0x00 0x5f 0x04 0x00 0x00 0x60 0x02 0x00 0x60 0x04 0x00 0x00 0x61 0x02 0x00 0x61 +0x04 0x00 0x00 0x62 0x02 0x00 0x62 0x04 0x00 0x00 0x63 0x02 0x00 0x63 0x04 0x00 0x00 0x64 +0x02 0x00 0x64 0x04 0x00 0x00 0x65 0x02 0x00 0x65 0x04 0x00 0x00 0x66 0x02 0x00 0x66 0x04 +0x00 0x00 0x67 0x02 0x00 0x67 0x04 0x00 0x00 0x68 0x02 0x00 0x68 0x04 0x00 0x00 0x69 0x02 +0x00 0x69 0x04 0x00 0x00 0x6a 0x02 0x00 0x6a 0x04 0x00 0x00 0x6b 0x02 0x00 0x6b 0x04 0x00 +0x00 0x6c 0x02 0x00 0x6c 0x04 0x00 0x00 0x6d 0x02 0x00 0x6d 0x04 0x00 0x00 0x6e 0x02 0x00 +0x6e 0x04 0x00 0x00 0x6f 0x02 0x00 0x6f 0x04 0x00 0x00 0x70 0x02 0x00 0x70 0x04 0x00 0x00 +0x71 0x02 0x00 0x71 0x04 0x00 0x00 0x72 0x02 0x00 0x72 0x04 0x00 0x00 0x73 0x02 0x00 0x73 +0x04 0x00 0x00 0x74 0x02 0x00 0x74 0x04 0x00 0x00 0x75 0x02 0x00 0x75 0x04 0x00 0x00 0x76 +0x02 0x00 0x76 0x04 0x00 0x00 0x77 0x02 0x00 0x77 0x04 0x00 0x00 0x78 0x02 0x00 0x78 0x04 +0x00 0x00 0x79 0x02 0x00 0x79 0x04 0x00 0x00 0x7a 0x02 0x00 0x7a 0x04 0x00 0x00 0x7b 0x02 +0x00 0x7b 0x04 0x00 0x00 0x7c 0x02 0x00 0x7c 0x04 0x00 0x00 0x7d 0x02 0x00 0x7d 0x04 0x00 +0x00 0x7e 0x02 0x00 0x7e 0x04 0x00 0x00 0x7f 0x02 0x00 0x7f 0x04 0x00 0x00 0x80 0x02 0x00 +0x80 0x04 0x00 0x00 0x81 0x02 0x00 0x81 0x04 0x00 0x00 0x82 0x02 0x00 0x82 0x04 0x00 0x00 +0x83 0x02 0x00 0x83 0x04 0x00 0x00 0x84 0x02 0x00 0x84 0x04 0x00 0x00 0x85 0x02 0x00 0x85 +0x04 0x00 0x00 0x86 0x02 0x00 0x86 0x04 0x00 0x00 0x87 0x02 0x00 0x87 0x04 0x00 0x00 0x88 +0x02 0x00 0x88 0x04 0x00 0x00 0x89 0x02 0x00 0x89 0x04 0x00 0x00 0x8a 0x02 0x00 0x8a 0x04 +0x00 0x00 0x8b 0x02 0x00 0x8b 0x04 0x00 0x00 0x8c 0x02 0x00 0x8c 0x04 0x00 0x00 0x8d 0x02 +0x00 0x8d 0x04 0x00 0x00 0x8e 0x02 0x00 0x8e 0x04 0x00 0x00 0x8f 0x02 0x00 0x8f 0x04 0x00 +0x00 0x90 0x02 0x00 0x90 0x04 0x00 0x00 0x91 0x02 0x00 0x91 0x04 0x00 0x00 0x92 0x02 0x00 +0x92 0x04 0x00 0x00 0x93 0x02 0x00 0x93 0x04 0x00 0x00 0x94 0x02 0x00 0x94 0x04 0x00 0x00 +0x95 0x02 0x00 0x95 0x04 0x00 0x00 0x96 0x02 0x00 0x96 0x04 0x00 0x00 0x97 0x02 0x00 0x97 +0x04 0x00 0x00 0x98 0x02 0x00 0x98 0x04 0x00 0x00 0x99 0x02 0x00 0x99 0x04 0x00 0x00 0x9a +0x02 0x00 0x9a 0x04 0x00 0x00 0x9b 0x02 0x00 0x9b 0x04 0x00 0x00 0x9c 0x02 0x00 0x9c 0x04 +0x00 0x00 0x9d 0x02 0x00 0x9d 0x04 0x00 0x00 0x9e 0x02 0x00 0x9e 0x04 0x00 0x00 0x9f 0x02 +0x00 0x9f 0x04 0x00 0x00 0xa0 0x02 0x00 0xa0 0x04 0x00 0x00 0xa1 0x02 0x00 0xa1 0x04 0x00 +0x00 0xa2 0x02 0x00 0xa2 0x04 0x00 0x00 0xa3 0x02 0x00 0xa3 0x04 0x00 0x00 0xa4 0x02 0x00 +0xa4 0x04 0x00 0x00 0xa5 0x02 0x00 0xa5 0x04 0x00 0x00 0xa6 0x02 0x00 0xa6 0x04 0x00 0x00 +0xa7 0x02 0x00 0xa7 0x04 0x00 0x00 0xa8 0x02 0x00 0xa8 0x04 0x00 0x00 0xa9 0x02 0x00 0xa9 +0x04 0x00 0x00 0xaa 0x02 0x00 0xaa 0x04 0x00 0x00 0xab 0x02 0x00 0xab 0x04 0x00 0x00 0xac +0x02 0x00 0xac 0x04 0x00 0x00 0xad 0x02 0x00 0xad 0x04 0x00 0x00 0xae 0x02 0x00 0xae 0x04 +0x00 0x00 0xaf 0x02 0x00 0xaf 0x04 0x00 0x00 0xb0 0x02 0x00 0xb0 0x04 0x00 0x00 0xb1 0x02 +0x00 0xb1 0x04 0x00 0x00 0xb2 0x02 0x00 0xb2 0x04 0x00 0x00 0xb3 0x02 0x00 0xb3 0x04 0x00 +0x00 0xb4 0x02 0x00 0xb4 0x04 0x00 0x00 0xb5 0x02 0x00 0xb5 0x04 0x00 0x00 0xb6 0x02 0x00 +0xb6 0x04 0x00 0x00 0xb7 0x02 0x00 0xb7 0x04 0x00 0x00 0xb8 0x02 0x00 0xb8 0x04 0x00 0x00 +0xb9 0x02 0x00 0xb9 0x04 0x00 0x00 0xba 0x02 0x00 0xba 0x04 0x00 0x00 0xbb 0x02 0x00 0xbb +0x04 0x00 0x00 0xbc 0x02 0x00 0xbc 0x04 0x00 0x00 0xbd 0x02 0x00 0xbd 0x04 0x00 0x00 0xbe +0x02 0x00 0xbe 0x04 0x00 0x00 0xbf 0x02 0x00 0xbf 0x04 0x00 0x00 0xc0 0x02 0x00 0xc0 0x04 +0x00 0x00 0xc1 0x02 0x00 0xc1 0x04 0x00 0x00 0xc2 0x02 0x00 0xc2 0x04 0x00 0x00 0xc3 0x02 +0x00 0xc3 0x04 0x00 0x00 0xc4 0x02 0x00 0xc4 0x04 0x00 0x00 0xc5 0x02 0x00 0xc5 0x04 0x00 +0x00 0xc6 0x02 0x00 0xc6 0x04 0x00 0x00 0xc7 0x02 0x00 0xc7 0x04 0x00 0x00 0xc8 0x02 0x00 +0xc8 0x04 0x00 0x00 0xc9 0x02 0x00 0xc9 0x04 0x00 0x00 0xca 0x02 0x00 0xca 0x04 0x00 0x00 +0xcb 0x02 0x00 0xcb 0x04 0x00 0x00 0xcc 0x02 0x00 0xcc 0x04 0x00 0x00 0xcd 0x02 0x00 0xcd +0x04 0x00 0x00 0xce 0x02 0x00 0xce 0x04 0x00 0x00 0xcf 0x02 0x00 0xcf 0x04 0x00 0x00 0xd0 +0x02 0x00 0xd0 0x04 0x00 0x00 0xd1 0x02 0x00 0xd1 0x04 0x00 0x00 0xd2 0x02 0x00 0xd2 0x04 +0x00 0x00 0xd3 0x02 0x00 0xd3 0x04 0x00 0x00 0xd4 0x02 0x00 0xd4 0x04 0x00 0x00 0xd5 0x02 +0x00 0xd5 0x04 0x00 0x00 0xd6 0x02 0x00 0xd6 0x04 0x00 0x00 0xd7 0x02 0x00 0xd7 0x04 0x00 +0x00 0xd8 0x02 0x00 0xd8 0x04 0x00 0x00 0xd9 0x02 0x00 0xd9 0x04 0x00 0x00 0xda 0x02 0x00 +0xda 0x04 0x00 0x00 0xdb 0x02 0x00 0xdb 0x04 0x00 0x00 0xdc 0x02 0x00 0xdc 0x04 0x00 0x00 +0xdd 0x02 0x00 0xdd 0x04 0x00 0x00 0xa0 0x02 0x00 0xa0 0x04 0x00 0x00 0x00 0x03 0x00 0x00 +0x04 0x00 0x00 0x01 0x03 0x00 0x01 0x04 0x00 0x00 0x02 0x03 0x00 0x02 0x04 0x00 0x00 0x03 +0x03 0x00 0x03 0x04 0x00 0x00 0x04 0x03 0x00 0x04 0x04 0x00 0x00 0x05 0x03 0x00 0x05 0x04 +0x00 0x00 0x06 0x03 0x00 0x06 0x04 0x00 0x00 0x07 0x03 0x00 0x07 0x04 0x00 0x00 0x08 0x03 +0x00 0x08 0x04 0x00 0x00 0x09 0x03 0x00 0x09 0x04 0x00 0x00 0x0a 0x03 0x00 0x0a 0x04 0x00 +0x00 0x0b 0x03 0x00 0x0b 0x04 0x00 0x00 0x0c 0x03 0x00 0x0c 0x04 0x00 0x00 0x0d 0x03 0x00 +0x0d 0x04 0x00 0x00 0x0e 0x03 0x00 0x0e 0x04 0x00 0x00 0x0f 0x03 0x00 0x0f 0x04 0x00 0x00 +0x10 0x03 0x00 0x10 0x04 0x00 0x00 0x11 0x03 0x00 0x11 0x04 0x00 0x00 0x12 0x03 0x00 0x12 +0x04 0x00 0x00 0x13 0x03 0x00 0x13 0x04 0x00 0x00 0x14 0x03 0x00 0x14 0x04 0x00 0x00 0x15 +0x03 0x00 0x15 0x04 0x00 0x00 0x16 0x03 0x00 0x16 0x04 0x00 0x00 0x17 0x03 0x00 0x17 0x04 +0x00 0x00 0x18 0x03 0x00 0x18 0x04 0x00 0x00 0x19 0x03 0x00 0x19 0x04 0x00 0x00 0x1a 0x03 +0x00 0x1a 0x04 0x00 0x00 0x1b 0x03 0x00 0x1b 0x04 0x00 0x00 0x1c 0x03 0x00 0x1c 0x04 0x00 +0x00 0x1d 0x03 0x00 0x1d 0x04 0x00 0x00 0x1e 0x03 0x00 0x1e 0x04 0x00 0x00 0x1f 0x03 0x00 +0x1f 0x04 0x00 0x00 0x20 0x03 0x00 0x20 0x04 0x00 0x00 0x21 0x03 0x00 0x21 0x04 0x00 0x00 +0x22 0x03 0x00 0x22 0x04 0x00 0x00 0x23 0x03 0x00 0x23 0x04 0x00 0x00 0x24 0x03 0x00 0x24 +0x04 0x00 0x00 0x25 0x03 0x00 0x25 0x04 0x00 0x00 0x26 0x03 0x00 0x26 0x04 0x00 0x00 0x27 +0x03 0x00 0x27 0x04 0x00 0x00 0x28 0x03 0x00 0x28 0x04 0x00 0x00 0x29 0x03 0x00 0x29 0x04 +0x00 0x00 0x2a 0x03 0x00 0x2a 0x04 0x00 0x00 0x2b 0x03 0x00 0x2b 0x04 0x00 0x00 0x2c 0x03 +0x00 0x2c 0x04 0x00 0x00 0x2d 0x03 0x00 0x2d 0x04 0x00 0x00 0x2e 0x03 0x00 0x2e 0x04 0x00 +0x00 0x2f 0x03 0x00 0x2f 0x04 0x00 0x00 0x30 0x03 0x00 0x30 0x04 0x00 0x00 0x31 0x03 0x00 +0x31 0x04 0x00 0x00 0x32 0x03 0x00 0x32 0x04 0x00 0x00 0x33 0x03 0x00 0x33 0x04 0x00 0x00 +0x34 0x03 0x00 0x34 0x04 0x00 0x00 0x35 0x03 0x00 0x35 0x04 0x00 0x00 0x36 0x03 0x00 0x36 +0x04 0x00 0x00 0x37 0x03 0x00 0x37 0x04 0x00 0x00 0x38 0x03 0x00 0x38 0x04 0x00 0x00 0x39 +0x03 0x00 0x39 0x04 0x00 0x00 0x3a 0x03 0x00 0x3a 0x04 0x00 0x00 0x3b 0x03 0x00 0x3b 0x04 +0x00 0x00 0x3c 0x03 0x00 0x3c 0x04 0x00 0x00 0x3d 0x03 0x00 0x3d 0x04 0x00 0x00 0x3e 0x03 +0x00 0x3e 0x04 0x00 0x00 0x3f 0x03 0x00 0x3f 0x04 0x00 0x00 0x40 0x03 0x00 0x40 0x04 0x00 +0x00 0x41 0x03 0x00 0x41 0x04 0x00 0x00 0x42 0x03 0x00 0x42 0x04 0x00 0x00 0x43 0x03 0x00 +0x43 0x04 0x00 0x00 0x44 0x03 0x00 0x44 0x04 0x00 0x00 0x45 0x03 0x00 0x45 0x04 0x00 0x00 +0x46 0x03 0x00 0x46 0x04 0x00 0x00 0x47 0x03 0x00 0x47 0x04 0x00 0x00 0x48 0x03 0x00 0x48 +0x04 0x00 0x00 0x49 0x03 0x00 0x49 0x04 0x00 0x00 0x4a 0x03 0x00 0x4a 0x04 0x00 0x00 0x4b +0x03 0x00 0x4b 0x04 0x00 0x00 0x4c 0x03 0x00 0x4c 0x04 0x00 0x00 0x4d 0x03 0x00 0x4d 0x04 +0x00 0x00 0x4e 0x03 0x00 0x4e 0x04 0x00 0x00 0x4f 0x03 0x00 0x4f 0x04 0x00 0x00 0x50 0x03 +0x00 0x50 0x04 0x00 0x00 0x51 0x03 0x00 0x51 0x04 0x00 0x00 0x52 0x03 0x00 0x52 0x04 0x00 +0x00 0x53 0x03 0x00 0x53 0x04 0x00 0x00 0x54 0x03 0x00 0x54 0x04 0x00 0x00 0x55 0x03 0x00 +0x55 0x04 0x00 0x00 0x56 0x03 0x00 0x56 0x04 0x00 0x00 0x57 0x03 0x00 0x57 0x04 0x00 0x00 +0x58 0x03 0x00 0x58 0x04 0x00 0x00 0x59 0x03 0x00 0x59 0x04 0x00 0x00 0x5a 0x03 0x00 0x5a +0x04 0x00 0x00 0x5b 0x03 0x00 0x5b 0x04 0x00 0x00 0x5c 0x03 0x00 0x5c 0x04 0x00 0x00 0x5d +0x03 0x00 0x5d 0x04 0x00 0x00 0x5e 0x03 0x00 0x5e 0x04 0x00 0x00 0x5f 0x03 0x00 0x5f 0x04 +0x00 0x00 0x60 0x03 0x00 0x60 0x04 0x00 0x00 0x61 0x03 0x00 0x61 0x04 0x00 0x00 0x62 0x03 +0x00 0x62 0x04 0x00 0x00 0x63 0x03 0x00 0x63 0x04 0x00 0x00 0x64 0x03 0x00 0x64 0x04 0x00 +0x00 0x65 0x03 0x00 0x65 0x04 0x00 0x00 0x66 0x03 0x00 0x66 0x04 0x00 0x00 0x67 0x03 0x00 +0x67 0x04 0x00 0x00 0x68 0x03 0x00 0x68 0x04 0x00 0x00 0x69 0x03 0x00 0x69 0x04 0x00 0x00 +0x6a 0x03 0x00 0x6a 0x04 0x00 0x00 0x6b 0x03 0x00 0x6b 0x04 0x00 0x00 0x6c 0x03 0x00 0x6c +0x04 0x00 0x00 0x6d 0x03 0x00 0x6d 0x04 0x00 0x00 0x6e 0x03 0x00 0x6e 0x04 0x00 0x00 0x6f +0x03 0x00 0x6f 0x04 0x00 0x00 0x70 0x03 0x00 0x70 0x04 0x00 0x00 0x71 0x03 0x00 0x71 0x04 +0x00 0x00 0x72 0x03 0x00 0x72 0x04 0x00 0x00 0x73 0x03 0x00 0x73 0x04 0x00 0x00 0x74 0x03 +0x00 0x74 0x04 0x00 0x00 0x75 0x03 0x00 0x75 0x04 0x00 0x00 0x76 0x03 0x00 0x76 0x04 0x00 +0x00 0x77 0x03 0x00 0x77 0x04 0x00 0x00 0x78 0x03 0x00 0x78 0x04 0x00 0x00 0x79 0x03 0x00 +0x79 0x04 0x00 0x00 0x7a 0x03 0x00 0x7a 0x04 0x00 0x00 0x7b 0x03 0x00 0x7b 0x04 0x00 0x00 +0x7c 0x03 0x00 0x7c 0x04 0x00 0x00 0x7d 0x03 0x00 0x7d 0x04 0x00 0x00 0x7e 0x03 0x00 0x7e +0x04 0x00 0x00 0x7f 0x03 0x00 0x7f 0x04 0x00 0x00 0x80 0x03 0x00 0x80 0x04 0x00 0x00 0x81 +0x03 0x00 0x81 0x04 0x00 0x00 0x82 0x03 0x00 0x82 0x04 0x00 0x00 0x83 0x03 0x00 0x83 0x04 +0x00 0x00 0x84 0x03 0x00 0x84 0x04 0x00 0x00 0x85 0x03 0x00 0x85 0x04 0x00 0x00 0x86 0x03 +0x00 0x86 0x04 0x00 0x00 0x87 0x03 0x00 0x87 0x04 0x00 0x00 0x88 0x03 0x00 0x88 0x04 0x00 +0x00 0x89 0x03 0x00 0x89 0x04 0x00 0x00 0x8a 0x03 0x00 0x8a 0x04 0x00 0x00 0x8b 0x03 0x00 +0x8b 0x04 0x00 0x00 0x8c 0x03 0x00 0x8c 0x04 0x00 0x00 0x8d 0x03 0x00 0x8d 0x04 0x00 0x00 +0x8e 0x03 0x00 0x8e 0x04 0x00 0x00 0x8f 0x03 0x00 0x8f 0x04 0x00 0x00 0x90 0x03 0x00 0x90 +0x04 0x00 0x00 0x91 0x03 0x00 0x91 0x04 0x00 0x00 0x92 0x03 0x00 0x92 0x04 0x00 0x00 0x93 +0x03 0x00 0x93 0x04 0x00 0x00 0x94 0x03 0x00 0x94 0x04 0x00 0x00 0x95 0x03 0x00 0x95 0x04 +0x00 0x00 0x96 0x03 0x00 0x96 0x04 0x00 0x00 0x97 0x03 0x00 0x97 0x04 0x00 0x00 0x98 0x03 +0x00 0x98 0x04 0x00 0x00 0x99 0x03 0x00 0x99 0x04 0x00 0x00 0x9a 0x03 0x00 0x9a 0x04 0x00 +0x00 0x9b 0x03 0x00 0x9b 0x04 0x00 0x00 0x9c 0x03 0x00 0x9c 0x04 0x00 0x00 0x9d 0x03 0x00 +0x9d 0x04 0x00 0x00 0x9e 0x03 0x00 0x9e 0x04 0x00 0x00 0x9f 0x03 0x00 0x9f 0x04 0x00 0x00 +0xa0 0x03 0x00 0xa0 0x04 0x00 0x00 0xa1 0x03 0x00 0xa1 0x04 0x00 0x00 0xa2 0x03 0x00 0xa2 +0x04 0x00 0x00 0xa3 0x03 0x00 0xa3 0x04 0x00 0x00 0xa4 0x03 0x00 0xa4 0x04 0x00 0x00 0xa5 +0x03 0x00 0xa5 0x04 0x00 0x00 0xa6 0x03 0x00 0xa6 0x04 0x00 0x00 0xa7 0x03 0x00 0xa7 0x04 +0x00 0x00 0xa8 0x03 0x00 0xa8 0x04 0x00 0x00 0xa9 0x03 0x00 0xa9 0x04 0x00 0x00 0xaa 0x03 +0x00 0xaa 0x04 0x00 0x00 0xab 0x03 0x00 0xab 0x04 0x00 0x00 0xac 0x03 0x00 0xac 0x04 0x00 +0x00 0xad 0x03 0x00 0xad 0x04 0x00 0x00 0xae 0x03 0x00 0xae 0x04 0x00 0x00 0xaf 0x03 0x00 +0xaf 0x04 0x00 0x00 0xb0 0x03 0x00 0xb0 0x04 0x00 0x00 0xb1 0x03 0x00 0xb1 0x04 0x00 0x00 +0xb2 0x03 0x00 0xb2 0x04 0x00 0x00 0xb3 0x03 0x00 0xb3 0x04 0x00 0x00 0xb4 0x03 0x00 0xb4 +0x04 0x00 0x00 0xb5 0x03 0x00 0xb5 0x04 0x00 0x00 0xb6 0x03 0x00 0xb6 0x04 0x00 0x00 0xb7 +0x03 0x00 0xb7 0x04 0x00 0x00 0xb8 0x03 0x00 0xb8 0x04 0x00 0x00 0xb9 0x03 0x00 0xb9 0x04 +0x00 0x00 0xba 0x03 0x00 0xba 0x04 0x00 0x00 0xbb 0x03 0x00 0xbb 0x04 0x00 0x00 0xbc 0x03 +0x00 0xbc 0x04 0x00 0x00 0xbd 0x03 0x00 0xbd 0x04 0x00 0x00 0xbe 0x03 0x00 0xbe 0x04 0x00 +0x00 0xbf 0x03 0x00 0xbf 0x04 0x00 0x00 0xc0 0x03 0x00 0xc0 0x04 0x00 0x00 0xc1 0x03 0x00 +0xc1 0x04 0x00 0x00 0xc2 0x03 0x00 0xc2 0x04 0x00 0x00 0xc3 0x03 0x00 0xc3 0x04 0x00 0x00 +0xc4 0x03 0x00 0xc4 0x04 0x00 0x00 0xc5 0x03 0x00 0xc5 0x04 0x00 0x00 0xc6 0x03 0x00 0xc6 +0x04 0x00 0x00 0xc7 0x03 0x00 0xc7 0x04 0x00 0x00 0xc8 0x03 0x00 0xc8 0x04 0x00 0x00 0xc9 +0x03 0x00 0xc9 0x04 0x00 0x00 0xca 0x03 0x00 0xca 0x04 0x00 0x00 0xcb 0x03 0x00 0xcb 0x04 +0x00 0x00 0xcc 0x03 0x00 0xcc 0x04 0x00 0x00 0xcd 0x03 0x00 0xcd 0x04 0x00 0x00 0xce 0x03 +0x00 0xce 0x04 0x00 0x00 0xcf 0x03 0x00 0xcf 0x04 0x00 0x00 0xd0 0x03 0x00 0xd0 0x04 0x00 +0x00 0xd1 0x03 0x00 0xd1 0x04 0x00 0x00 0xd2 0x03 0x00 0xd2 0x04 0x00 0x00 0xd3 0x03 0x00 +0xd3 0x04 0x00 0x00 0xd4 0x03 0x00 0xd4 0x04 0x00 0x00 0xd5 0x03 0x00 0xd5 0x04 0x00 0x00 +0xd6 0x03 0x00 0xd6 0x04 0x00 0x00 0xd7 0x03 0x00 0xd7 0x04 0x00 0x00 0xd8 0x03 0x00 0xd8 +0x04 0x00 0x00 0xd9 0x03 0x00 0xd9 0x04 0x00 0x00 0xda 0x03 0x00 0xda 0x04 0x00 0x00 0xdb +0x03 0x00 0xdb 0x04 0x00 0x00 0xdc 0x03 0x00 0xdc 0x04 0x00 0x00 0xdd 0x03 0x00 0xdd 0x04 +0x00 0x00 0xa0 0x03 0x00 0xa0 0x04 0x00 0x00 0x00 0x04 0x00 0x00 0x04 0x00 0x00 0x01 0x04 +0x00 0x01 0x04 0x00 0x00 0x02 0x04 0x00 0x02 0x04 0x00 0x00 0x03 0x04 0x00 0x03 0x04 0x00 +0x00 0x04 0x04 0x00 0x04 0x04 0x00 0x00 0x05 0x04 0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00 +0x06 0x04 0x00 0x00 0x07 0x04 0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00 0x08 0x04 0x00 0x00 +0x09 0x04 0x00 0x09 0x04 0x00 0x00 0x0a 0x04 0x00 0x0a 0x04 0x00 0x00 0x0b 0x04 0x00 0x0b +0x04 0x00 0x00 0x0c 0x04 0x00 0x0c 0x04 0x00 0x00 0x0d 0x04 0x00 0x0d 0x04 0x00 0x00 0x0e +0x04 0x00 0x0e 0x04 0x00 0x00 0x0f 0x04 0x00 0x0f 0x04 0x00 0x00 0x10 0x04 0x00 0x10 0x04 +0x00 0x00 0x11 0x04 0x00 0x11 0x04 0x00 0x00 0x12 0x04 0x00 0x12 0x04 0x00 0x00 0x13 0x04 +0x00 0x13 0x04 0x00 0x00 0x14 0x04 0x00 0x14 0x04 0x00 0x00 0x15 0x04 0x00 0x15 0x04 0x00 +0x00 0x16 0x04 0x00 0x16 0x04 0x00 0x00 0x17 0x04 0x00 0x17 0x04 0x00 0x00 0x18 0x04 0x00 +0x18 0x04 0x00 0x00 0x19 0x04 0x00 0x19 0x04 0x00 0x00 0x1a 0x04 0x00 0x1a 0x04 0x00 0x00 +0x1b 0x04 0x00 0x1b 0x04 0x00 0x00 0x1c 0x04 0x00 0x1c 0x04 0x00 0x00 0x1d 0x04 0x00 0x1d +0x04 0x00 0x00 0x1e 0x04 0x00 0x1e 0x04 0x00 0x00 0x1f 0x04 0x00 0x1f 0x04 0x00 0x00 0x20 +0x04 0x00 0x20 0x04 0x00 0x00 0x21 0x04 0x00 0x21 0x04 0x00 0x00 0x22 0x04 0x00 0x22 0x04 +0x00 0x00 0x23 0x04 0x00 0x23 0x04 0x00 0x00 0x24 0x04 0x00 0x24 0x04 0x00 0x00 0x25 0x04 +0x00 0x25 0x04 0x00 0x00 0x26 0x04 0x00 0x26 0x04 0x00 0x00 0x27 0x04 0x00 0x27 0x04 0x00 +0x00 0x28 0x04 0x00 0x28 0x04 0x00 0x00 0x29 0x04 0x00 0x29 0x04 0x00 0x00 0x2a 0x04 0x00 +0x2a 0x04 0x00 0x00 0x2b 0x04 0x00 0x2b 0x04 0x00 0x00 0x2c 0x04 0x00 0x2c 0x04 0x00 0x00 +0x2d 0x04 0x00 0x2d 0x04 0x00 0x00 0x2e 0x04 0x00 0x2e 0x04 0x00 0x00 0x2f 0x04 0x00 0x2f +0x04 0x00 0x00 0x30 0x04 0x00 0x30 0x04 0x00 0x00 0x31 0x04 0x00 0x31 0x04 0x00 0x00 0x32 +0x04 0x00 0x32 0x04 0x00 0x00 0x33 0x04 0x00 0x33 0x04 0x00 0x00 0x34 0x04 0x00 0x34 0x04 +0x00 0x00 0x35 0x04 0x00 0x35 0x04 0x00 0x00 0x36 0x04 0x00 0x36 0x04 0x00 0x00 0x37 0x04 +0x00 0x37 0x04 0x00 0x00 0x38 0x04 0x00 0x38 0x04 0x00 0x00 0x39 0x04 0x00 0x39 0x04 0x00 +0x00 0x3a 0x04 0x00 0x3a 0x04 0x00 0x00 0x3b 0x04 0x00 0x3b 0x04 0x00 0x00 0x3c 0x04 0x00 +0x3c 0x04 0x00 0x00 0x3d 0x04 0x00 0x3d 0x04 0x00 0x00 0x3e 0x04 0x00 0x3e 0x04 0x00 0x00 +0x3f 0x04 0x00 0x3f 0x04 0x00 0x00 0x40 0x04 0x00 0x40 0x04 0x00 0x00 0x41 0x04 0x00 0x41 +0x04 0x00 0x00 0x42 0x04 0x00 0x42 0x04 0x00 0x00 0x43 0x04 0x00 0x43 0x04 0x00 0x00 0x44 +0x04 0x00 0x44 0x04 0x00 0x00 0x45 0x04 0x00 0x45 0x04 0x00 0x00 0x46 0x04 0x00 0x46 0x04 +0x00 0x00 0x47 0x04 0x00 0x47 0x04 0x00 0x00 0x48 0x04 0x00 0x48 0x04 0x00 0x00 0x49 0x04 +0x00 0x49 0x04 0x00 0x00 0x4a 0x04 0x00 0x4a 0x04 0x00 0x00 0x4b 0x04 0x00 0x4b 0x04 0x00 +0x00 0x4c 0x04 0x00 0x4c 0x04 0x00 0x00 0x4d 0x04 0x00 0x4d 0x04 0x00 0x00 0x4e 0x04 0x00 +0x4e 0x04 0x00 0x00 0x4f 0x04 0x00 0x4f 0x04 0x00 0x00 0x50 0x04 0x00 0x50 0x04 0x00 0x00 +0x51 0x04 0x00 0x51 0x04 0x00 0x00 0x52 0x04 0x00 0x52 0x04 0x00 0x00 0x53 0x04 0x00 0x53 +0x04 0x00 0x00 0x54 0x04 0x00 0x54 0x04 0x00 0x00 0x55 0x04 0x00 0x55 0x04 0x00 0x00 0x56 +0x04 0x00 0x56 0x04 0x00 0x00 0x57 0x04 0x00 0x57 0x04 0x00 0x00 0x58 0x04 0x00 0x58 0x04 +0x00 0x00 0x59 0x04 0x00 0x59 0x04 0x00 0x00 0x5a 0x04 0x00 0x5a 0x04 0x00 0x00 0x5b 0x04 +0x00 0x5b 0x04 0x00 0x00 0x5c 0x04 0x00 0x5c 0x04 0x00 0x00 0x5d 0x04 0x00 0x5d 0x04 0x00 +0x00 0x5e 0x04 0x00 0x5e 0x04 0x00 0x00 0x5f 0x04 0x00 0x5f 0x04 0x00 0x00 0x60 0x04 0x00 +0x60 0x04 0x00 0x00 0x61 0x04 0x00 0x61 0x04 0x00 0x00 0x62 0x04 0x00 0x62 0x04 0x00 0x00 +0x63 0x04 0x00 0x63 0x04 0x00 0x00 0x64 0x04 0x00 0x64 0x04 0x00 0x00 0x65 0x04 0x00 0x65 +0x04 0x00 0x00 0x66 0x04 0x00 0x66 0x04 0x00 0x00 0x67 0x04 0x00 0x67 0x04 0x00 0x00 0x68 +0x04 0x00 0x68 0x04 0x00 0x00 0x69 0x04 0x00 0x69 0x04 0x00 0x00 0x6a 0x04 0x00 0x6a 0x04 +0x00 0x00 0x6b 0x04 0x00 0x6b 0x04 0x00 0x00 0x6c 0x04 0x00 0x6c 0x04 0x00 0x00 0x6d 0x04 +0x00 0x6d 0x04 0x00 0x00 0x6e 0x04 0x00 0x6e 0x04 0x00 0x00 0x6f 0x04 0x00 0x6f 0x04 0x00 +0x00 0x70 0x04 0x00 0x70 0x04 0x00 0x00 0x71 0x04 0x00 0x71 0x04 0x00 0x00 0x72 0x04 0x00 +0x72 0x04 0x00 0x00 0x73 0x04 0x00 0x73 0x04 0x00 0x00 0x74 0x04 0x00 0x74 0x04 0x00 0x00 +0x75 0x04 0x00 0x75 0x04 0x00 0x00 0x76 0x04 0x00 0x76 0x04 0x00 0x00 0x77 0x04 0x00 0x77 +0x04 0x00 0x00 0x78 0x04 0x00 0x78 0x04 0x00 0x00 0x79 0x04 0x00 0x79 0x04 0x00 0x00 0x7a +0x04 0x00 0x7a 0x04 0x00 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x00 0x7c 0x04 0x00 0x7c 0x04 +0x00 0x00 0x7d 0x04 0x00 0x7d 0x04 0x00 0x00 0x7e 0x04 0x00 0x7e 0x04 0x00 0x00 0x7f 0x04 +0x00 0x7f 0x04 0x00 0x00 0x80 0x04 0x00 0x80 0x04 0x00 0x00 0x81 0x04 0x00 0x81 0x04 0x00 +0x00 0x82 0x04 0x00 0x82 0x04 0x00 0x00 0x83 0x04 0x00 0x83 0x04 0x00 0x00 0x84 0x04 0x00 +0x84 0x04 0x00 0x00 0x85 0x04 0x00 0x85 0x04 0x00 0x00 0x86 0x04 0x00 0x86 0x04 0x00 0x00 +0x87 0x04 0x00 0x87 0x04 0x00 0x00 0x88 0x04 0x00 0x88 0x04 0x00 0x00 0x89 0x04 0x00 0x89 +0x04 0x00 0x00 0x8a 0x04 0x00 0x8a 0x04 0x00 0x00 0x8b 0x04 0x00 0x8b 0x04 0x00 0x00 0x8c +0x04 0x00 0x8c 0x04 0x00 0x00 0x8d 0x04 0x00 0x8d 0x04 0x00 0x00 0x8e 0x04 0x00 0x8e 0x04 +0x00 0x00 0x8f 0x04 0x00 0x8f 0x04 0x00 0x00 0x90 0x04 0x00 0x90 0x04 0x00 0x00 0x91 0x04 +0x00 0x91 0x04 0x00 0x00 0x92 0x04 0x00 0x92 0x04 0x00 0x00 0x93 0x04 0x00 0x93 0x04 0x00 +0x00 0x94 0x04 0x00 0x94 0x04 0x00 0x00 0x95 0x04 0x00 0x95 0x04 0x00 0x00 0x96 0x04 0x00 +0x96 0x04 0x00 0x00 0x97 0x04 0x00 0x97 0x04 0x00 0x00 0x98 0x04 0x00 0x98 0x04 0x00 0x00 +0x99 0x04 0x00 0x99 0x04 0x00 0x00 0x9a 0x04 0x00 0x9a 0x04 0x00 0x00 0x9b 0x04 0x00 0x9b +0x04 0x00 0x00 0x9c 0x04 0x00 0x9c 0x04 0x00 0x00 0x9d 0x04 0x00 0x9d 0x04 0x00 0x00 0x9e +0x04 0x00 0x9e 0x04 0x00 0x00 0x9f 0x04 0x00 0x9f 0x04 0x00 0x00 0xa0 0x04 0x00 0xa0 0x04 +0x00 0x00 0xa1 0x04 0x00 0xa1 0x04 0x00 0x00 0xa2 0x04 0x00 0xa2 0x04 0x00 0x00 0xa3 0x04 +0x00 0xa3 0x04 0x00 0x00 0xa4 0x04 0x00 0xa4 0x04 0x00 0x00 0xa5 0x04 0x00 0xa5 0x04 0x00 +0x00 0xa6 0x04 0x00 0xa6 0x04 0x00 0x00 0xa7 0x04 0x00 0xa7 0x04 0x00 0x00 0xa8 0x04 0x00 +0xa8 0x04 0x00 0x00 0xa9 0x04 0x00 0xa9 0x04 0x00 0x00 0xaa 0x04 0x00 0xaa 0x04 0x00 0x00 +0xab 0x04 0x00 0xab 0x04 0x00 0x00 0xac 0x04 0x00 0xac 0x04 0x00 0x00 0xad 0x04 0x00 0xad +0x04 0x00 0x00 0xae 0x04 0x00 0xae 0x04 0x00 0x00 0xaf 0x04 0x00 0xaf 0x04 0x00 0x00 0xb0 +0x04 0x00 0xb0 0x04 0x00 0x00 0xb1 0x04 0x00 0xb1 0x04 0x00 0x00 0xb2 0x04 0x00 0xb2 0x04 +0x00 0x00 0xb3 0x04 0x00 0xb3 0x04 0x00 0x00 0xb4 0x04 0x00 0xb4 0x04 0x00 0x00 0xb5 0x04 +0x00 0xb5 0x04 0x00 0x00 0xb6 0x04 0x00 0xb6 0x04 0x00 0x00 0xb7 0x04 0x00 0xb7 0x04 0x00 +0x00 0xb8 0x04 0x00 0xb8 0x04 0x00 0x00 0xb9 0x04 0x00 0xb9 0x04 0x00 0x00 0xba 0x04 0x00 +0xba 0x04 0x00 0x00 0xbb 0x04 0x00 0xbb 0x04 0x00 0x00 0xbc 0x04 0x00 0xbc 0x04 0x00 0x00 +0xbd 0x04 0x00 0xbd 0x04 0x00 0x00 0xbe 0x04 0x00 0xbe 0x04 0x00 0x00 0xbf 0x04 0x00 0xbf +0x04 0x00 0x00 0xc0 0x04 0x00 0xc0 0x04 0x00 0x00 0xc1 0x04 0x00 0xc1 0x04 0x00 0x00 0xc2 +0x04 0x00 0xc2 0x04 0x00 0x00 0xc3 0x04 0x00 0xc3 0x04 0x00 0x00 0xc4 0x04 0x00 0xc4 0x04 +0x00 0x00 0xc5 0x04 0x00 0xc5 0x04 0x00 0x00 0xc6 0x04 0x00 0xc6 0x04 0x00 0x00 0xc7 0x04 +0x00 0xc7 0x04 0x00 0x00 0xc8 0x04 0x00 0xc8 0x04 0x00 0x00 0xc9 0x04 0x00 0xc9 0x04 0x00 +0x00 0xca 0x04 0x00 0xca 0x04 0x00 0x00 0xcb 0x04 0x00 0xcb 0x04 0x00 0x00 0xcc 0x04 0x00 +0xcc 0x04 0x00 0x00 0xcd 0x04 0x00 0xcd 0x04 0x00 0x00 0xce 0x04 0x00 0xce 0x04 0x00 0x00 +0xcf 0x04 0x00 0xcf 0x04 0x00 0x00 0xd0 0x04 0x00 0xd0 0x04 0x00 0x00 0xd1 0x04 0x00 0xd1 +0x04 0x00 0x00 0xd2 0x04 0x00 0xd2 0x04 0x00 0x00 0xd3 0x04 0x00 0xd3 0x04 0x00 0x00 0xd4 +0x04 0x00 0xd4 0x04 0x00 0x00 0xd5 0x04 0x00 0xd5 0x04 0x00 0x00 0xd6 0x04 0x00 0xd6 0x04 +0x00 0x00 0xd7 0x04 0x00 0xd7 0x04 0x00 0x00 0xd8 0x04 0x00 0xd8 0x04 0x00 0x00 0xd9 0x04 +0x00 0xd9 0x04 0x00 0x00 0xda 0x04 0x00 0xda 0x04 0x00 0x00 0xdb 0x04 0x00 0xdb 0x04 0x00 +0x00 0xdc 0x04 0x00 0xdc 0x04 0x00 0x00 0xdd 0x04 0x00 0xdd 0x04 0x00 0x00 0xa0 0x04 0x00 +0xa0 0x04 0x00 0x00 0x00 0x05 0x00 0x00 0x04 0x00 0x00 0x01 0x05 0x00 0x01 0x04 0x00 0x00 +0x02 0x05 0x00 0x02 0x04 0x00 0x00 0x03 0x05 0x00 0x03 0x04 0x00 0x00 0x04 0x05 0x00 0x04 +0x04 0x00 0x00 0x05 0x05 0x00 0x05 0x04 0x00 0x00 0x06 0x05 0x00 0x06 0x04 0x00 0x00 0x07 +0x05 0x00 0x07 0x04 0x00 0x00 0x08 0x05 0x00 0x08 0x04 0x00 0x00 0x09 0x05 0x00 0x09 0x04 +0x00 0x00 0x0a 0x05 0x00 0x0a 0x04 0x00 0x00 0x0b 0x05 0x00 0x0b 0x04 0x00 0x00 0x0c 0x05 +0x00 0x0c 0x04 0x00 0x00 0x0d 0x05 0x00 0x0d 0x04 0x00 0x00 0x0e 0x05 0x00 0x0e 0x04 0x00 +0x00 0x0f 0x05 0x00 0x0f 0x04 0x00 0x00 0x10 0x05 0x00 0x10 0x04 0x00 0x00 0x11 0x05 0x00 +0x11 0x04 0x00 0x00 0x12 0x05 0x00 0x12 0x04 0x00 0x00 0x13 0x05 0x00 0x13 0x04 0x00 0x00 +0x14 0x05 0x00 0x14 0x04 0x00 0x00 0x15 0x05 0x00 0x15 0x04 0x00 0x00 0x16 0x05 0x00 0x16 +0x04 0x00 0x00 0x17 0x05 0x00 0x17 0x04 0x00 0x00 0x18 0x05 0x00 0x18 0x04 0x00 0x00 0x19 +0x05 0x00 0x19 0x04 0x00 0x00 0x1a 0x05 0x00 0x1a 0x04 0x00 0x00 0x1b 0x05 0x00 0x1b 0x04 +0x00 0x00 0x1c 0x05 0x00 0x1c 0x04 0x00 0x00 0x1d 0x05 0x00 0x1d 0x04 0x00 0x00 0x1e 0x05 +0x00 0x1e 0x04 0x00 0x00 0x1f 0x05 0x00 0x1f 0x04 0x00 0x00 0x20 0x05 0x00 0x20 0x04 0x00 +0x00 0x21 0x05 0x00 0x21 0x04 0x00 0x00 0x22 0x05 0x00 0x22 0x04 0x00 0x00 0x23 0x05 0x00 +0x23 0x04 0x00 0x00 0x24 0x05 0x00 0x24 0x04 0x00 0x00 0x25 0x05 0x00 0x25 0x04 0x00 0x00 +0x26 0x05 0x00 0x26 0x04 0x00 0x00 0x27 0x05 0x00 0x27 0x04 0x00 0x00 0x28 0x05 0x00 0x28 +0x04 0x00 0x00 0x29 0x05 0x00 0x29 0x04 0x00 0x00 0x2a 0x05 0x00 0x2a 0x04 0x00 0x00 0x2b +0x05 0x00 0x2b 0x04 0x00 0x00 0x2c 0x05 0x00 0x2c 0x04 0x00 0x00 0x2d 0x05 0x00 0x2d 0x04 +0x00 0x00 0x2e 0x05 0x00 0x2e 0x04 0x00 0x00 0x2f 0x05 0x00 0x2f 0x04 0x00 0x00 0x30 0x05 +0x00 0x30 0x04 0x00 0x00 0x31 0x05 0x00 0x31 0x04 0x00 0x00 0x32 0x05 0x00 0x32 0x04 0x00 +0x00 0x33 0x05 0x00 0x33 0x04 0x00 0x00 0x34 0x05 0x00 0x34 0x04 0x00 0x00 0x35 0x05 0x00 +0x35 0x04 0x00 0x00 0x36 0x05 0x00 0x36 0x04 0x00 0x00 0x37 0x05 0x00 0x37 0x04 0x00 0x00 +0x38 0x05 0x00 0x38 0x04 0x00 0x00 0x39 0x05 0x00 0x39 0x04 0x00 0x00 0x3a 0x05 0x00 0x3a +0x04 0x00 0x00 0x3b 0x05 0x00 0x3b 0x04 0x00 0x00 0x3c 0x05 0x00 0x3c 0x04 0x00 0x00 0x3d +0x05 0x00 0x3d 0x04 0x00 0x00 0x3e 0x05 0x00 0x3e 0x04 0x00 0x00 0x3f 0x05 0x00 0x3f 0x04 +0x00 0x00 0x40 0x05 0x00 0x40 0x04 0x00 0x00 0x41 0x05 0x00 0x41 0x04 0x00 0x00 0x42 0x05 +0x00 0x42 0x04 0x00 0x00 0x43 0x05 0x00 0x43 0x04 0x00 0x00 0x44 0x05 0x00 0x44 0x04 0x00 +0x00 0x45 0x05 0x00 0x45 0x04 0x00 0x00 0x46 0x05 0x00 0x46 0x04 0x00 0x00 0x47 0x05 0x00 +0x47 0x04 0x00 0x00 0x48 0x05 0x00 0x48 0x04 0x00 0x00 0x49 0x05 0x00 0x49 0x04 0x00 0x00 +0x4a 0x05 0x00 0x4a 0x04 0x00 0x00 0x4b 0x05 0x00 0x4b 0x04 0x00 0x00 0x4c 0x05 0x00 0x4c +0x04 0x00 0x00 0x4d 0x05 0x00 0x4d 0x04 0x00 0x00 0x4e 0x05 0x00 0x4e 0x04 0x00 0x00 0x4f +0x05 0x00 0x4f 0x04 0x00 0x00 0x50 0x05 0x00 0x50 0x04 0x00 0x00 0x51 0x05 0x00 0x51 0x04 +0x00 0x00 0x52 0x05 0x00 0x52 0x04 0x00 0x00 0x53 0x05 0x00 0x53 0x04 0x00 0x00 0x54 0x05 +0x00 0x54 0x04 0x00 0x00 0x55 0x05 0x00 0x55 0x04 0x00 0x00 0x56 0x05 0x00 0x56 0x04 0x00 +0x00 0x57 0x05 0x00 0x57 0x04 0x00 0x00 0x58 0x05 0x00 0x58 0x04 0x00 0x00 0x59 0x05 0x00 +0x59 0x04 0x00 0x00 0x5a 0x05 0x00 0x5a 0x04 0x00 0x00 0x5b 0x05 0x00 0x5b 0x04 0x00 0x00 +0x5c 0x05 0x00 0x5c 0x04 0x00 0x00 0x5d 0x05 0x00 0x5d 0x04 0x00 0x00 0x5e 0x05 0x00 0x5e +0x04 0x00 0x00 0x5f 0x05 0x00 0x5f 0x04 0x00 0x00 0x60 0x05 0x00 0x60 0x04 0x00 0x00 0x61 +0x05 0x00 0x61 0x04 0x00 0x00 0x62 0x05 0x00 0x62 0x04 0x00 0x00 0x63 0x05 0x00 0x63 0x04 +0x00 0x00 0x64 0x05 0x00 0x64 0x04 0x00 0x00 0x65 0x05 0x00 0x65 0x04 0x00 0x00 0x66 0x05 +0x00 0x66 0x04 0x00 0x00 0x67 0x05 0x00 0x67 0x04 0x00 0x00 0x68 0x05 0x00 0x68 0x04 0x00 +0x00 0x69 0x05 0x00 0x69 0x04 0x00 0x00 0x6a 0x05 0x00 0x6a 0x04 0x00 0x00 0x6b 0x05 0x00 +0x6b 0x04 0x00 0x00 0x6c 0x05 0x00 0x6c 0x04 0x00 0x00 0x6d 0x05 0x00 0x6d 0x04 0x00 0x00 +0x6e 0x05 0x00 0x6e 0x04 0x00 0x00 0x6f 0x05 0x00 0x6f 0x04 0x00 0x00 0x70 0x05 0x00 0x70 +0x04 0x00 0x00 0x71 0x05 0x00 0x71 0x04 0x00 0x00 0x72 0x05 0x00 0x72 0x04 0x00 0x00 0x73 +0x05 0x00 0x73 0x04 0x00 0x00 0x74 0x05 0x00 0x74 0x04 0x00 0x00 0x75 0x05 0x00 0x75 0x04 +0x00 0x00 0x76 0x05 0x00 0x76 0x04 0x00 0x00 0x77 0x05 0x00 0x77 0x04 0x00 0x00 0x78 0x05 +0x00 0x78 0x04 0x00 0x00 0x79 0x05 0x00 0x79 0x04 0x00 0x00 0x7a 0x05 0x00 0x7a 0x04 0x00 +0x00 0x7b 0x05 0x00 0x7b 0x04 0x00 0x00 0x7c 0x05 0x00 0x7c 0x04 0x00 0x00 0x7d 0x05 0x00 +0x7d 0x04 0x00 0x00 0x7e 0x05 0x00 0x7e 0x04 0x00 0x00 0x7f 0x05 0x00 0x7f 0x04 0x00 0x00 +0x80 0x05 0x00 0x80 0x04 0x00 0x00 0x81 0x05 0x00 0x81 0x04 0x00 0x00 0x82 0x05 0x00 0x82 +0x04 0x00 0x00 0x83 0x05 0x00 0x83 0x04 0x00 0x00 0x84 0x05 0x00 0x84 0x04 0x00 0x00 0x85 +0x05 0x00 0x85 0x04 0x00 0x00 0x86 0x05 0x00 0x86 0x04 0x00 0x00 0x87 0x05 0x00 0x87 0x04 +0x00 0x00 0x88 0x05 0x00 0x88 0x04 0x00 0x00 0x89 0x05 0x00 0x89 0x04 0x00 0x00 0x8a 0x05 +0x00 0x8a 0x04 0x00 0x00 0x8b 0x05 0x00 0x8b 0x04 0x00 0x00 0x8c 0x05 0x00 0x8c 0x04 0x00 +0x00 0x8d 0x05 0x00 0x8d 0x04 0x00 0x00 0x8e 0x05 0x00 0x8e 0x04 0x00 0x00 0x8f 0x05 0x00 +0x8f 0x04 0x00 0x00 0x90 0x05 0x00 0x90 0x04 0x00 0x00 0x91 0x05 0x00 0x91 0x04 0x00 0x00 +0x92 0x05 0x00 0x92 0x04 0x00 0x00 0x93 0x05 0x00 0x93 0x04 0x00 0x00 0x94 0x05 0x00 0x94 +0x04 0x00 0x00 0x95 0x05 0x00 0x95 0x04 0x00 0x00 0x96 0x05 0x00 0x96 0x04 0x00 0x00 0x97 +0x05 0x00 0x97 0x04 0x00 0x00 0x98 0x05 0x00 0x98 0x04 0x00 0x00 0x99 0x05 0x00 0x99 0x04 +0x00 0x00 0x9a 0x05 0x00 0x9a 0x04 0x00 0x00 0x9b 0x05 0x00 0x9b 0x04 0x00 0x00 0x9c 0x05 +0x00 0x9c 0x04 0x00 0x00 0x9d 0x05 0x00 0x9d 0x04 0x00 0x00 0x9e 0x05 0x00 0x9e 0x04 0x00 +0x00 0x9f 0x05 0x00 0x9f 0x04 0x00 0x00 0xa0 0x05 0x00 0xa0 0x04 0x00 0x00 0xa1 0x05 0x00 +0xa1 0x04 0x00 0x00 0xa2 0x05 0x00 0xa2 0x04 0x00 0x00 0xa3 0x05 0x00 0xa3 0x04 0x00 0x00 +0xa4 0x05 0x00 0xa4 0x04 0x00 0x00 0xa5 0x05 0x00 0xa5 0x04 0x00 0x00 0xa6 0x05 0x00 0xa6 +0x04 0x00 0x00 0xa7 0x05 0x00 0xa7 0x04 0x00 0x00 0xa8 0x05 0x00 0xa8 0x04 0x00 0x00 0xa9 +0x05 0x00 0xa9 0x04 0x00 0x00 0xaa 0x05 0x00 0xaa 0x04 0x00 0x00 0xab 0x05 0x00 0xab 0x04 +0x00 0x00 0xac 0x05 0x00 0xac 0x04 0x00 0x00 0xad 0x05 0x00 0xad 0x04 0x00 0x00 0xae 0x05 +0x00 0xae 0x04 0x00 0x00 0xaf 0x05 0x00 0xaf 0x04 0x00 0x00 0xb0 0x05 0x00 0xb0 0x04 0x00 +0x00 0xb1 0x05 0x00 0xb1 0x04 0x00 0x00 0xb2 0x05 0x00 0xb2 0x04 0x00 0x00 0xb3 0x05 0x00 +0xb3 0x04 0x00 0x00 0xb4 0x05 0x00 0xb4 0x04 0x00 0x00 0xb5 0x05 0x00 0xb5 0x04 0x00 0x00 +0xb6 0x05 0x00 0xb6 0x04 0x00 0x00 0xb7 0x05 0x00 0xb7 0x04 0x00 0x00 0xb8 0x05 0x00 0xb8 +0x04 0x00 0x00 0xb9 0x05 0x00 0xb9 0x04 0x00 0x00 0xba 0x05 0x00 0xba 0x04 0x00 0x00 0xbb +0x05 0x00 0xbb 0x04 0x00 0x00 0xbc 0x05 0x00 0xbc 0x04 0x00 0x00 0xbd 0x05 0x00 0xbd 0x04 +0x00 0x00 0xbe 0x05 0x00 0xbe 0x04 0x00 0x00 0xbf 0x05 0x00 0xbf 0x04 0x00 0x00 0xc0 0x05 +0x00 0xc0 0x04 0x00 0x00 0xc1 0x05 0x00 0xc1 0x04 0x00 0x00 0xc2 0x05 0x00 0xc2 0x04 0x00 +0x00 0xc3 0x05 0x00 0xc3 0x04 0x00 0x00 0xc4 0x05 0x00 0xc4 0x04 0x00 0x00 0xc5 0x05 0x00 +0xc5 0x04 0x00 0x00 0xc6 0x05 0x00 0xc6 0x04 0x00 0x00 0xc7 0x05 0x00 0xc7 0x04 0x00 0x00 +0xc8 0x05 0x00 0xc8 0x04 0x00 0x00 0xc9 0x05 0x00 0xc9 0x04 0x00 0x00 0xca 0x05 0x00 0xca +0x04 0x00 0x00 0xcb 0x05 0x00 0xcb 0x04 0x00 0x00 0xcc 0x05 0x00 0xcc 0x04 0x00 0x00 0xcd +0x05 0x00 0xcd 0x04 0x00 0x00 0xce 0x05 0x00 0xce 0x04 0x00 0x00 0xcf 0x05 0x00 0xcf 0x04 +0x00 0x00 0xd0 0x05 0x00 0xd0 0x04 0x00 0x00 0xd1 0x05 0x00 0xd1 0x04 0x00 0x00 0xd2 0x05 +0x00 0xd2 0x04 0x00 0x00 0xd3 0x05 0x00 0xd3 0x04 0x00 0x00 0xd4 0x05 0x00 0xd4 0x04 0x00 +0x00 0xd5 0x05 0x00 0xd5 0x04 0x00 0x00 0xd6 0x05 0x00 0xd6 0x04 0x00 0x00 0xd7 0x05 0x00 +0xd7 0x04 0x00 0x00 0xd8 0x05 0x00 0xd8 0x04 0x00 0x00 0xd9 0x05 0x00 0xd9 0x04 0x00 0x00 +0xda 0x05 0x00 0xda 0x04 0x00 0x00 0xdb 0x05 0x00 0xdb 0x04 0x00 0x00 0xdc 0x05 0x00 0xdc +0x04 0x00 0x00 0xdd 0x05 0x00 0xdd 0x04 0x00 0x00 0xa0 0x05 0x00 0xa0 0x04 0x00 0x00 0xbca +0x06 0x12 0x00 0x00 0xbd4 0x06 0x1c 0x00 0x00 0xbd5 0x06 0x1d 0x00 0x00 0xfb2 0x07 0x12>; + phandle = <0xc7>; + + amba@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0b>; + + downstream_amba_lpd { + compatible = "qemu:memory-region"; + alias = <0x08>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_fpd { + compatible = "qemu:memory-region"; + alias = <0x09>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_internal { + compatible = "qemu:memory-region"; + alias = <0x0a>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_ocm@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x13>; + reg-extended = <0x0b 0x00 0xeb400000 0x00 0x10000 +0x00 0x0b 0x00 0xbbf00000 0x00 0x80000 0x02>; + protected-mr = <0x0c>; + mr-0 = <0x0b>; + protected-base = <0xbbf00000>; + phandle = <0xc8>; + }; + + xmpu_ocm2@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x13>; + reg-extended = <0x0b 0x00 0xeb970000 0x00 0x10000 +0x00 0x0d 0x00 0xea800000 0x00 0x800000 0x02>; + protected-mr = <0x0e>; + mr-0 = <0x08>; + protected-base = <0xea800000>; + phandle = <0xc9>; + }; + + loader_write_cpu0_0x1@0xF1110880 { + compatible = "loader"; + addr = <0xf1110880>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0xca>; + }; + + loader_write_cpu0_0x5@0xFD1A0050 { + compatible = "loader"; + addr = <0xfd1a0050>; + data = <0x05>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0xcb>; + }; + + loader_write_cpu0_0xFF@0xF111010C { + compatible = "loader"; + addr = <0xf111010c>; + data = <0xff>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0xcc>; + }; + + s_axi_tcm_a@0 { + compatible = "qemu:memory-region"; + alias = <0x0f>; + reg = <0x00 0xeba00000 0x00 0x800000 0x00>; + phandle = <0x28>; + }; + + s_axi_tcm_b@0 { + compatible = "qemu:memory-region"; + alias = <0x10>; + reg = <0x00 0xeba80000 0x00 0x800000 0x00>; + phandle = <0x2c>; + }; + + loader_write_cpu0_0x80C@0xF12B0100 { + compatible = "loader"; + addr = <0xf12b0100>; + data = <0x80c>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0xcd>; + }; + }; + + amba_lpd@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x08>; + + downstream_amba_psm { + compatible = "qemu:memory-region"; + alias = <0x11>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_xram { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xppu_lpd@0xeb990000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x08 0x00 0xeb990000 0x00 0x10000 0x00 0x12 +0x00 0xff000000 0x00 0xe00000 0x02 0x12 0x00 0xfe000000 0x00 0x1000000 0x02 0x0b 0x00 0xe0000000 +0x00 0x10000000 0x02>; + mr = <0x08>; + interrupts = <0x50>; + region = <0x00>; + phandle = <0xce>; + }; + + ethernet@0xf19e0000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + interrupts = <0x27 0x27>; + dma = <0x13>; + memattr = <0x14>; + memattr-write = <0x15>; + reg = <0x00 0xf19e0000 0x00 0x10000 0x00>; + num-priority-queues = <0x02>; + reset-gpios = <0x16 0x01>; + power-gpios = <0x17 0x20>; + mdio = <0x18>; + phandle = <0xcf>; + }; + + ethernet@0xf19f0000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + interrupts = <0x29 0x29>; + dma = <0x13>; + memattr = <0x19>; + memattr-write = <0x1a>; + reg = <0x00 0xf19f0000 0x00 0x10000 0x00>; + num-priority-queues = <0x02>; + reset-gpios = <0x16 0x02>; + power-gpios = <0x17 0x21>; + mdio = <0x18>; + phandle = <0xd0>; + }; + + serial@0xf1920000 { + compatible = "pl011"; + interrupts = <0x19>; + reg = <0x00 0xf1920000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x05>; + chardev = "con"; + phandle = <0xd1>; + }; + + serial@0xf1930000 { + compatible = "pl011"; + interrupts = <0x1a>; + reg = <0x00 0xf1930000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x06>; + chardev = "serial3"; + phandle = <0xd2>; + }; + + canfdbus@0 { + compatible = "can-bus"; + phandle = <0x1b>; + }; + + can@0xf1980000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1b>; + interrupts = <0x1b>; + reg = <0x00 0xf1980000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x09>; + phandle = <0xd3>; + }; + + can@0xf1990000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1b>; + interrupts = <0x1c>; + reg = <0x00 0xf1990000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x0a>; + phandle = <0xd4>; + }; + + crl@0xeb5e0000 { + compatible = "xlnx,psx_crl"; + reg = <0x00 0xeb5e0000 0x00 0x300000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x16>; + }; + + slcr@0xf19a0000 { + compatible = "xlnx,versal-lpd-iou-slcr"; + reg = <0x00 0xf19a0000 0x00 0x20000 0x00>; + phandle = <0xd5>; + }; + + ipi@0xeb300000 { + compatible = "xlnx,versal-ipi"; + reg = <0x00 0xeb300000 0x00 0x100000 0x00>; + interrupts = <0xfb2 0xbd4 0x39 0x3a 0x3b 0x3c 0x3d 0x3e +0x3f 0xbd5 0x46 0x40 0x41 0x42 0x43 0x44 0x45>; + reset-gpios = <0x16 0x19>; + num-master-ids = <0x20>; + phandle = <0xd6>; + }; + + spi@0xf1960000 { + compatible = "cdns,spi-r1p6"; + interrupts = <0x17>; + num-ss-bits = <0x04>; + reg = <0x00 0xf1960000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + reset-gpios = <0x16 0x07>; + phandle = <0xd7>; + + spi0_flash0@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25p80\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + blockdev-node-name = "spi0_flash0"; + phandle = <0xd8>; + + spi0_flash0@0x00000000 { + label = "spi0_flash0"; + reg = <0x00 0x100000>; + }; + }; + }; + + spi@0xf1970000 { + compatible = "cdns,spi-r1p6"; + interrupts = <0x18>; + num-ss-bits = <0x04>; + reg = <0x00 0xf1970000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + reset-gpios = <0x16 0x08>; + phandle = <0xd9>; + + spi1_flash0@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25p80\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + blockdev-node-name = "spi1_flash0"; + phandle = <0xda>; + + spi1_flash0@0x00000000 { + label = "spi1_flash0"; + reg = <0x00 0x100000>; + }; + }; + }; + + usb2@USB2_0_XHCI { + compatible = "usb_dwc3"; + reg = <0x00 0xf1b0c100 0x00 0x600 0x00 +0x00 0xf1b00000 0x00 0x100000 0x00>; + interrupts = <0x1d 0x1e 0x1f 0x20>; + dma = <0x13>; + memattr = <0x1c>; + reset-gpios = <0x16 0x03>; + intrs = <0x04>; + slots = <0x02>; + phandle = <0xdb>; + }; + + timer@0xf1dc0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2b 0x2c 0x2d>; + reg = <0x00 0xf1dc0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x16 0x12>; + phandle = <0xdc>; + }; + + timer@0xf1dd0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2e 0x2f 0x30>; + reg = <0x00 0xf1dd0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x16 0x13>; + phandle = <0xdd>; + }; + + timer@0xf1de0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x31 0x32 0x33>; + reg = <0x00 0xf1de0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x16 0x14>; + phandle = <0xde>; + }; + + timer@0xf1df0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x34 0x35 0x36>; + reg = <0x00 0xf1df0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x16 0x15>; + phandle = <0xdf>; + }; + + adma0mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x210>; + phandle = <0x1d>; + }; + + dma-controller@0xebd00000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd00000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x48>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x1d>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x00>; + phandle = <0xe0>; + }; + + adma1mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x212>; + phandle = <0x1f>; + }; + + dma-controller@0xebd10000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd10000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x49>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x1f>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x01>; + phandle = <0xe1>; + }; + + adma2mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x214>; + phandle = <0x20>; + }; + + dma-controller@0xebd20000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd20000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4a>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x20>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x02>; + phandle = <0xe2>; + }; + + adma3mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x216>; + phandle = <0x21>; + }; + + dma-controller@0xebd30000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd30000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4b>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x21>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x03>; + phandle = <0xe3>; + }; + + adma4mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x218>; + phandle = <0x22>; + }; + + dma-controller@0xebd40000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd40000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4c>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x22>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x04>; + phandle = <0xe4>; + }; + + adma5mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21a>; + phandle = <0x23>; + }; + + dma-controller@0xebd50000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd50000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4d>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x23>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x05>; + phandle = <0xe5>; + }; + + adma6mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21c>; + phandle = <0x24>; + }; + + dma-controller@0xebd60000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd60000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4e>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x24>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x06>; + phandle = <0xe6>; + }; + + adma7mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21e>; + phandle = <0x25>; + }; + + dma-controller@0xebd70000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd70000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4f>; + #stream-id-cells = <0x01>; + dma = <0x13>; + memattr = <0x25>; + reset-gpios = <0x16 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x1e 0x07>; + phandle = <0xe7>; + }; + + afi_fm@0xeb9b0000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xeb9b0000 0x00 0x10000 0x00>; + }; + + lpd_i2c_wrapper { + + ps_i2c0@0xf1940000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x15>; + reg-extended = <0x08 0x00 0xf1940000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x0b>; + phandle = <0xe8>; + + i2c0_bridge@0 { + compatible = "i2c-wire"; + i2cWire-peer = <0x26>; + phandle = <0x27>; + }; + }; + + ps_i2c0@0xf1950000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x16>; + reg-extended = <0x08 0x00 0xf1950000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x0c>; + phandle = <0xe9>; + + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + size = <0x2000>; + blockdev-node-name = "i2c1.eeprom-54"; + phandle = <0xea>; + }; + + eeprom@51 { + compatible = "at,24c08"; + reg = <0x51>; + size = <0x2000>; + blockdev-node-name = "i2c1.eeprom-51"; + phandle = <0xeb>; + }; + + i2c1_bridge@0 { + compatible = "i2c-wire"; + i2cWire-peer = <0x27>; + phandle = <0x26>; + }; + }; + }; + + ocm_ctrl@OCM { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x10>; + memsize = <0x80000>; + reg = <0x00 0xeb5d0000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x18>; + phandle = <0xec>; + }; + + lpd_slcr@0xeb410000 { + compatible = "xlnx,versal-lpd-slcr"; + reg = <0x00 0xeb410000 0x00 0x100000 0x00>; + }; + + lpd_slcr_secure@0xeb510000 { + compatible = "xlnx,versal-lpd-slcr-secure"; + reg = <0x00 0xeb510000 0x00 0x40000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1e>; + }; + + lpd_iou_slcr_secure@0xf19c0000 { + compatible = "xlnx,versal-lpd-iou-slcr-secure"; + reg = <0x00 0xf19c0000 0x00 0x10000 0x00>; + memattr-gem0 = <0x14>; + memattr-write-gem0 = <0x15>; + memattr-gem1 = <0x19>; + memattr-write-gem1 = <0x1a>; + phandle = <0xed>; + }; + + lpd_gpio@0xf19d0000 { + #gpio-cells = <0x01>; + compatible = "xlnx,zynqmp-gpio"; + gpio-controller; + interrupts = <0x14>; + reg = <0x00 0xf19d0000 0x00 0x10000 0x00>; + reset-gpios = <0x16 0x11>; + phandle = <0xee>; + }; + + intlpd@0xea600000 { + compatible = "xlnx-intlpd-config"; + reg = <0x00 0xea600000 0x00 0x200000 0x00>; + interrupts = <0x50>; + phandle = <0xef>; + }; + + virtio_mmio_0 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e00000 0x00 0x1000 0x00>; + interrupts = <0x05>; + }; + + virtio_mmio_1 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e01000 0x00 0x1000 0x00>; + interrupts = <0x06>; + }; + + virtio_mmio_2 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e02000 0x00 0x1000 0x00>; + interrupts = <0x07>; + }; + + virtio_mmio_3 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e03000 0x00 0x1000 0x00>; + interrupts = <0x08>; + }; + + virtio_mmio_4 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e04000 0x00 0x1000 0x00>; + interrupts = <0x09>; + }; + + virtio_mmio_5 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e05000 0x00 0x1000 0x00>; + interrupts = <0x0a>; + }; + + virtio_mmio_6 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e06000 0x00 0x1000 0x00>; + interrupts = <0x0b>; + }; + + virtio_mmio_7 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e07000 0x00 0x1000 0x00>; + interrupts = <0x0c>; + }; + + rpu_ctrl@0 { + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0xf0>; + }; + + rpu_cluster@0xeb580000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb580000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x28>; + phandle = <0x2a>; + }; + + rpu_ctrl_a0@0xeb588000 { + compatible = "xlnx,psx_rpu_cluster_core0"; + reg = <0x00 0xeb588000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x16 0x23>; + core = <0x29>; + phandle = <0xae>; + }; + + rpu_ctrl_a1@0xeb58c000 { + compatible = "xlnx,psx_rpu_cluster_core1"; + reg = <0x00 0xeb58c000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x16 0x24 0x2a 0x00>; + core = <0x2b>; + phandle = <0xb1>; + }; + + rpu_cluster@0xeb590000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb590000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x2c>; + phandle = <0x2e>; + }; + + rpu_ctrl_b0@0xeb598000 { + compatible = "xlnx,psx_rpu_cluster_core0"; + reg = <0x00 0xeb598000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x16 0x25>; + core = <0x2d>; + phandle = <0xb4>; + }; + + rpu_ctrl_b1@0xeb59c000 { + compatible = "xlnx,psx_rpu_cluster_core1"; + reg = <0x00 0xeb59c000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x16 0x26 0x2e 0x00>; + core = <0x2f>; + phandle = <0xb7>; + }; + + rpu_pcil@0xEB420000 { + compatible = "xlnx,rpu_pcil"; + reg = <0x00 0xeb420000 0x00 0x10000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x91>; + }; + + usb2@USB2_0_XHCI1 { + compatible = "usb_dwc3"; + reg = <0x00 0xf1c0c100 0x00 0x600 0x00 +0x00 0xf1c00000 0x00 0x100000 0x00>; + interrupts = <0x22 0x23 0x24 0x25>; + dma = <0x13>; + memattr = <0x30>; + reset-gpios = <0x16 0x04>; + intrs = <0x04>; + slots = <0x02>; + phandle = <0xf1>; + }; + }; + + amba_fpd@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x09>; + + afi_fm@0xec880000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xec880000 0x00 0x10000 0x00>; + }; + + afi_fm@0xec8a0000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xec8a0000 0x00 0x10000 0x00>; + }; + + cpm_crcpm@0xfca00000 { + compatible = "xlnx,versal_cpm_crcpm"; + reg = <0x00 0xfca00000 0x00 0x10000 0x00>; + }; + + cpm_pcsr@0xfcff0000 { + compatible = "xlnx,versal_cpm_pcsr"; + reg = <0x00 0xfcff0000 0x00 0x10000 0x00>; + }; + + fpd_slcr@0xec8c0000 { + compatible = "xlnx,versal-fpd-slcr"; + interrupts = <0xa3>; + reg = <0x00 0xec8c0000 0x00 0x10000 0x00>; + }; + + fpd_slcr_secure@0xec8c0000 { + compatible = "xlnx,versal-fpd-slcr-secure"; + interrupts = <0xa3>; + reg = <0x00 0xec8e0000 0x00 0x10000 0x00>; + }; + + watchdog@0xecc10000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xecc10000 0x00 0x10000 0x00>; + interrupts = <0x8b 0x8c 0x8d 0x8e>; + pclk = <0x5f5e100>; + reset-gpios = <0x31 0x1b>; + phandle = <0xf2>; + }; + + intfpd@0xec400000 { + compatible = "xlnx-intfpd-config"; + reg = <0x00 0xec400000 0x00 0x400000 0x00>; + interrupts = <0xa3>; + phandle = <0xf3>; + }; + + apu_cluster@MM_FPD_FPD_APU_CLUSTER0 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecc00000 0x00 0x10000 0x00>; + cpu0 = <0x32>; + cpu1 = <0x33>; + cpu2 = <0x34>; + cpu3 = <0x35>; + cores-per-cluster = <0x04>; + phandle = <0xf4>; + }; + + apu_cluster@MM_FPD_FPD_APU_CLUSTER1 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecd00000 0x00 0x10000 0x00>; + cpu0 = <0x36>; + cpu1 = <0x37>; + cpu2 = <0x38>; + cpu3 = <0x39>; + cores-per-cluster = <0x04>; + phandle = <0xf5>; + }; + + apu_cluster@MM_FPD_FPD_APU_CLUSTER2 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xece00000 0x00 0x10000 0x00>; + cpu0 = <0x3a>; + cpu1 = <0x3b>; + cpu2 = <0x3c>; + cpu3 = <0x3d>; + cores-per-cluster = <0x04>; + phandle = <0xf6>; + }; + + apu_cluster@MM_FPD_FPD_APU_CLUSTER3 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecf00000 0x00 0x10000 0x00>; + cpu0 = <0x3e>; + cpu1 = <0x3f>; + cpu2 = <0x40>; + cpu3 = <0x41>; + cores-per-cluster = <0x04>; + phandle = <0xf7>; + }; + + cmn600ae@0xa0000000 { + compatible = "arm,cmn600ae"; + reg = <0x00 0xa0000000 0x00 0x3000000 0x00>; + }; + + smmuv3@MM_FPD_SMMU { + compatible = "arm-smmuv3"; + reg-extended = <0x09 0x00 0xec000000 0x00 0x200000 +0x00 0x13 0x00 0x00 0xffffffff 0xffffffff 0x00 0x42 0x00 0x00 0xffffffff 0xffffffff +0x00 0x43 0x00 0x00 0xffffffff 0xffffffff 0x00 0x44 0x00 0x00 0xffffffff 0xffffffff +0x00 0x45 0x00 0x00 0xffffffff 0xffffffff 0x00 0x46 0x00 0x00 0xffffffff 0xffffffff +0x00 0x47 0x00 0x00 0xffffffff 0xffffffff 0x00 0x48 0x00 0x00 0xffffffff 0xffffffff +0x00 0x49 0x00 0x00 0xffffffff 0xffffffff 0x00 0x4a 0x00 0x00 0xffffffff 0xffffffff +0x00 0x4b 0x00 0x00 0xffffffff 0xffffffff 0x00 0x4c 0x00 0x00 0xffffffff 0xffffffff +0x00 0x4d 0x00 0x00 0xffffffff 0xffffffff 0x00>; + mr-0 = <0x0b>; + mr-1 = <0x0b>; + mr-2 = <0x0b>; + mr-3 = <0x0b>; + mr-4 = <0x0b>; + mr-5 = <0x0b>; + mr-6 = <0x0b>; + mr-7 = <0x0b>; + mr-8 = <0x0b>; + mr-9 = <0x0b>; + mr-10 = <0x0b>; + mr-11 = <0x0b>; + mr-12 = <0x0b>; + dma_mr = <0x0b>; + primary-bus = <0x4e>; + phandle = <0xf8>; + }; + + dummy_pcie@0x6_0000_0000 { + compatible = "PCI"; + phandle = <0x4e>; + }; + + pki_rng@0x20400040000ULL { + compatible = "xlnx,psx-pki-rng"; + reg = <0x204 0x40000 0x00 0x20000 0x00>; + interrupts = <0x9c>; + phandle = <0xf9>; + }; + + apu_pcil@0xecb10000 { + compatible = "xlnx.apu_pcil"; + reg = <0x00 0xecb10000 0x00 0x10000 0x00>; + phandle = <0xfa>; + }; + + cpm5_crx@0xdc0000 { + compatible = "xlnx,cpm5_crx"; + reg = <0x00 0xe4dc0000 0x00 0x10000 0x00>; + phandle = <0xfb>; + }; + + cpm5_slcr_secure@0xde0000 { + compatible = "xlnx,cpm5_slcr_secure"; + reg = <0x00 0xe4de0000 0x00 0x10000 0x00>; + }; + + cpm5_gtyp_cfg@0xd00000 { + compatible = "xlnx,gtyp_npi_slave"; + reg = <0x00 0xe4d00000 0x00 0x20000 0x00>; + }; + + cpm5_gtyp_cfg@0xd20000 { + compatible = "xlnx,gtyp_npi_slave"; + reg = <0x00 0xe4d20000 0x00 0x20000 0x00>; + }; + + cpm5_gtyp_cfg@0xd40000 { + compatible = "xlnx,gtyp_npi_slave"; + reg = <0x00 0xe4d40000 0x00 0x20000 0x00>; + }; + + cpm5_gtyp_cfg@0xd60000 { + compatible = "xlnx,gtyp_npi_slave"; + reg = <0x00 0xe4d60000 0x00 0x20000 0x00>; + }; + }; + + amba_pmc_internal@0 { + doc-ignore = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0a>; + + downstream_amba_pmc_ppu { + compatible = "qemu:memory-region"; + alias = <0x4f>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_iou { + compatible = "qemu:memory-region"; + alias = <0x12>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_sec { + compatible = "qemu:memory-region"; + alias = <0x50>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_sys { + compatible = "qemu:memory-region"; + alias = <0x51>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_pl { + compatible = "qemu:memory-region"; + alias = <0x52>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_bat { + compatible = "qemu:memory-region"; + alias = <0x53>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_pmc@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0xc0>; + reg-extended = <0x0a 0x00 0xf12f0000 0x00 0x10000 0x00 0x0a +0x00 0xf2000000 0x00 0x20000 0x02>; + protected-mr = <0x54>; + mr-0 = <0x0a>; + protected-base = <0xf2000000>; + phandle = <0xfc>; + }; + + xppu_pmc_npi@0xf1300000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0a 0x00 0xf1300000 0x00 0x10000 +0x00 0x0a 0x00 0xf6000000 0x00 0x1000000 0x02 0x0a 0x00 0xf7000000 0x00 0x1000000 0x02>; + mr = <0x52>; + interrupts = <0xc0>; + region = <0x02>; + phandle = <0xfd>; + }; + + xppu_pmc@0xf1310000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0a 0x00 0xf1310000 0x00 0x10000 0x00 0x0b +0x00 0xf1000000 0x00 0x1000000 0x02 0x0b 0x00 0xf0000000 0x00 0x1000000 0x02 0x0b 0x00 +0xc0000000 0x00 0x20000000 0x02>; + mr = <0x0a>; + interrupts = <0xc0>; + region = <0x01>; + phandle = <0xfe>; + }; + }; + + amba_pmc@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x55>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0b>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_internal { + compatible = "qemu:memory-region"; + alias = <0x0a>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_pmc_cfu@0xf1340000 { + compatible = "xlnx,versal-xmpu"; + reg-extended = <0x55 0x00 0xf1340000 0x00 0x10000 0x00 0x52 +0x00 0xf12b0000 0x00 0x11000 0x02 0x52 0x00 0xf1f80000 0x00 0x40000 0x02>; + protected-mr = <0x56>; + mr-0 = <0x52>; + protected-base = <0xf12b0000>; + phandle = <0xff>; + }; + + pmx_err_mng@0xf1110000 { + compatible = "xlnx,pmx-err-mng"; + reg = <0x00 0xf1130000 0x00 0x10000 0x01>; + phandle = <0x100>; + }; + }; + + amba_pmc_iou@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC IOU"; + doc-status = "partial"; + phandle = <0x12>; + + pmc_iou_slcr@0xf1060000 { + doc-status = "partial"; + compatible = "xlnx,versal-pmx-iou-slcr"; + reg = <0x00 0xf1060000 0x00 0x1000 0x00>; + interrupts = <0xbc>; + gpio-controller; + #gpio-cells = <0x02>; + phandle = <0x65>; + }; + + pmc_iou_slcr_secure@0xf1070000 { + compatible = "xlnx,versal-pmc-iou-slcr-secure"; + reg = <0x00 0xf1070000 0x00 0x10000 0x00>; + interrupts = <0xbca>; + memattr-sd0 = <0x57>; + memattr-write-sd0 = <0x58>; + memattr-sd1 = <0x59>; + memattr-write-sd1 = <0x5a>; + memattr-write-qspi = <0x5b>; + memattr-write-ospi = <0x5c>; + phandle = <0x101>; + }; + + pmc_qspi_dma@QSPI_DMA { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xb7>; + #stream-id-cells = <0x01>; + reg = <0x00 0xf1030800 0x00 0x800 0x00>; + dma = <0x55>; + memattr = <0x5d>; + memattr-write = <0x5b>; + is-dst = <0x01>; + reset-gpios = <0x5e 0x00>; + phandle = <0x5f>; + }; + + pmc_qspi@0xf1030000 { + doc-status = "complete"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "xlnx,usmp-gqspi\0cdns,spi-r1p6"; + stream-connected-dma = <0x5f>; + dma = <0x55>; + interrupts = <0xb7>; + num-ss-bits = <0x02>; + reg-extended = <0x12 0x00 0xf1030000 0x00 0x1000 0x00 0x60 +0x00 0x00 0x00 0x20000000 0x00>; + speed-hz = <0x989680>; + xlnx,fb-clk = <0x01>; + xlnx,qspi-clk-freq-hz = <0xbebc200>; + xlnx,qspi-mode = <0x02>; + reset-gpios = <0x5e 0x00>; + phandle = <0x102>; + + qspi_flash_lcs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + drive-index = <0x00>; + phandle = <0x103>; + + qspi_flash_lcs_lb@0x00000000 { + label = "qspi_flash_lcs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + qspi_flash_ucs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x03 0x01>; + drive-index = <0x03>; + phandle = <0x104>; + + qspi_flash_ucs_ub@0x00000000 { + label = "qspi_flash_ucs_ub"; + reg = <0x00 0x2000000>; + }; + }; + }; + + ospi_dst_dma@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xb6>; + reg = <0x00 0xf1011800 0x00 0x800 0x00>; + dma = <0x55>; + memattr = <0x61>; + memattr-write = <0x5c>; + is-dst = <0x01>; + reset-gpios = <0x5e 0x01>; + phandle = <0x63>; + }; + + ospi_src_dma@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xb6>; + reg = <0x00 0xf1011000 0x00 0x800 0x00>; + dma = <0x62>; + memattr = <0x61>; + memattr-write = <0x5c>; + stream-connected-dma = <0x63>; + reset-gpios = <0x5e 0x01>; + phandle = <0x64>; + }; + + spi@0xf1010000 { + doc-status = "complete"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "xlnx,versal-ospi"; + reg-extended = <0x12 0x00 0xf1010000 0x00 0x1000 0x00 0x62 +0x00 0x00 0x00 0x20000000 0x00>; + dma-src = <0x64>; + interrupts = <0xb6>; + reset-gpios = <0x5e 0x01>; + gpios = <0x65 0x03 0x00>; + phandle = <0x105>; + }; + + gpio_mr_mux@0xc0000000 { + doc-status = "complete"; + compatible = "gpio-mr-mux"; + reg = <0x00 0xc0000000 0x00 0x20000000 0x00>; + gpios = <0x65 0x02 0x00 0x65 0x03 0x00>; + mr-size = <0x20000000>; + mr0 = <0x60>; + mr1 = <0x62>; + mr2 = <0x60>; + mr3 = <0x62>; + phandle = <0x106>; + }; + + pmc_gpio@0xf1020000 { + #gpio-cells = <0x01>; + compatible = "xlnx,zynqmp-gpio"; + gpio-controller; + interrupts = <0xb4>; + reg = <0x00 0xf1020000 0x00 0x10000 0x00>; + reset-gpios = <0x5e 0x05>; + phandle = <0x107>; + }; + + mmc@0xf1040000 { + doc-status = "complete"; + compatible = "xilinx,zynqmp-sdhci\0generic-sdhci"; + drive-index = <0x00>; + reg = <0x00 0xf1040000 0x00 0x10000 0x00>; + interrupts = <0xb8>; + dma = <0x13>; + memattr = <0x57>; + memattr-write = <0x58>; + gpios = <0x65 0x00 0x00>; + gpio-names = "SLOTTYPE"; + reset-gpios = <0x5e 0x08>; + is-mmc = <0x00>; + xlnx,has-cd = <0x01>; + xlnx,has-power = <0x00>; + xlnx,has-wp = <0x01>; + xlnx,sdio-clk-freq-hz = <0x2faf080>; + phandle = <0x108>; + }; + + mmc@0xf1050000 { + doc-status = "complete"; + compatible = "xlnx,versalnet-emmc"; + drive-index = <0x01>; + reg = <0x00 0xf1050200 0x00 0x100 0x00 +0x00 0xf1050000 0x00 0x100 0x00>; + interrupts = <0xba>; + dma = <0x13>; + memattr = <0x59>; + memattr-write = <0x5a>; + gpios = <0x65 0x01 0x00>; + gpio-names = "SLOTTYPE"; + reset-gpios = <0x5e 0x03>; + is-mmc = <0x00>; + xlnx,has-cd = <0x01>; + xlnx,has-power = <0x00>; + xlnx,has-wp = <0x01>; + xlnx,sdio-clk-freq-hz = <0x2faf080>; + phandle = <0x109>; + }; + + pmc_tap@0xf11a0000 { + doc-status = "complete"; + doc-comments = "Just a stub."; + compatible = "xlnx,pmc-tap"; + interrupts-extended = <0x66 0x1e>; + interrupt-names = "sec-dbg-int"; + reg = <0x00 0xf11a0000 0x00 0x80000 0x00>; + idcode = <0x14d80093>; + platform-ver = <0x05>; + phandle = <0x10a>; + }; + + pmc_i2c_wrapper { + }; + + wwdt@0xf03f0000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xf03f0000 0x00 0x10000 0x00>; + pclk = <0x5f5e100>; + phandle = <0x10b>; + }; + }; + + amba_pmc_sec@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC Secure"; + doc-status = "in-progress"; + qemu-fdt-abort-on-error = "Unable to create PMC security models.\n +Cannot continue.Try installing libgcrypt."; + phandle = <0x50>; + + trng@0xf1230000 { + doc-status = "complete"; + compatible = "xlnx,versal-trng"; + reg = <0x00 0xf1230000 0x00 0x1000 0x00>; + interrupts = <0xc7>; + }; + + pmc_dma0_src@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + stream-connected-dma0 = <0x67>; + reg = <0x00 0xf11c0000 0x00 0x800 0x00>; + dma = <0x55>; + memattr = <0x68>; + dma-width = <0x10>; + interrupts = <0xbe>; + reset-gpios = <0x5e 0x13>; + byte-align = <0x01>; + phandle = <0x10c>; + }; + + pmc_dma0_dst@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xf11c0800 0x00 0x800 0x00>; + dma = <0x55>; + memattr = <0x68>; + is-dst = <0x01>; + dma-width = <0x10>; + interrupts = <0xbe>; + reset-gpios = <0x5e 0x13>; + byte-align = <0x01>; + phandle = <0x6a>; + }; + + pmc_dma1_src@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + stream-connected-dma1 = <0x67>; + reg = <0x00 0xf11d0000 0x00 0x800 0x00>; + dma = <0x55>; + memattr = <0x69>; + dma-width = <0x10>; + interrupts = <0xbf>; + reset-gpios = <0x5e 0x14>; + byte-align = <0x01>; + phandle = <0x10d>; + }; + + pmc_dma1_dst@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xf11d0800 0x00 0x800 0x00>; + dma = <0x55>; + memattr = <0x69>; + is-dst = <0x01>; + dma-width = <0x10>; + interrupts = <0xbf>; + reset-gpios = <0x5e 0x14>; + byte-align = <0x01>; + phandle = <0x6b>; + }; + + pmc_stream_switch@0 { + doc-status = "complete"; + compatible = "versal,pmc-sss"; + reg-extended = <0x51 0x00 0xf1110500 0x00 0x04 0x01>; + stream-connected-dma0 = <0x6a>; + stream-connected-dma1 = <0x6b>; + stream-connected-aes = <0x6c>; + stream-connected-sha = <0x6d>; + stream-connected-sbi = <0x6e>; + stream-connected-sha1 = <0x6f>; + phandle = <0x67>; + }; + + pmc_sha@0xf1210000 { + doc-status = "complete"; + compatible = "zynqmp,csu-sha3"; + reg = <0x00 0xf1210000 0x00 0x100 0x00>; + interrupts = <0xc5>; + phandle = <0x6d>; + }; + + pmc_aes@0xf11e0000 { + doc-status = "in-progress"; + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-aes"; + stream-connected-aes = <0x67>; + reg = <0x00 0xf11e0000 0x00 0x100 0x00>; + interrupts = <0xc2>; + gpios = <0x70 0x00 0x70 0x01>; + gpio-names = "busy\0done"; + aes-core = <0x70>; + phandle = <0x6c>; + + xlnx_aes@0 { + #gpio-cells = <0x01>; + compatible = "xlnx-aes"; + gpios = <0x6c 0x00>; + gpio-names = "reset"; + phandle = <0x70>; + }; + }; + + pmc_rsa@0xf1200000 { + doc-status = "complete"; + reg = <0x00 0xf1200000 0x00 0x6c 0x00>; + interrupts = <0xc3>; + ram-nr-words = <0x100>; + phandle = <0x10e>; + }; + + xlnx_pmc_efuse_cache@0xf1250000 { + doc-status = "complete"; + compatible = "xlnx,pmx_efuse_cache"; + reg = <0x00 0xf1250000 0x00 0x10000 0x00>; + efuse = <0x71>; + phandle = <0x75>; + }; + + pmc_puf_ctrl@0 { + compatible = "xlnx,versal-puf-ctrl"; + zynqmp-aes-key-sink-puf = <0x6c>; + efuse = <0x71>; + reg = <0x00 0xf1150000 0x00 0x10000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x73>; + }; + + pmc_efuse@0xf1240000 { + doc-status = "complete"; + compatible = "xlnx,pmx_efuse_ctrl"; + #gpio-cells = <0x02>; + zynqmp-aes-key-sink-efuses = <0x6c>; + zynqmp-aes-key-sink-efuses-user0 = <0x6c>; + zynqmp-aes-key-sink-efuses-user1 = <0x6c>; + reg = <0x00 0xf1240000 0x00 0x10000 0x00>; + interrupts = <0xc4>; + efuse = <0x71>; + phandle = <0x10f>; + + xlnx_efuse@0 { + doc-ignore = <0x01>; + compatible = "xlnx,efuse"; + efuse-nr = <0x03>; + efuse-size = <0x2000>; + init-factory-extidcode = <0x01>; + phandle = <0x71>; + }; + }; + + pmc_bbram@0xf11f0000 { + doc-status = "partial"; + doc-limitations = "Missing AES key connections."; + compatible = "xlnx,bbram-ctrl"; + reg = <0x00 0xf11f0000 0x00 0x10000 0x00>; + interrupts = <0xbca>; + zynqmp-aes-key-sink-bbram = <0x6c>; + crc-zpads = <0x00>; + phandle = <0x74>; + }; + + pmc_sbi@0xf1220000 { + doc-status = "complete"; + compatible = "pmc,slave-boot"; + reg = <0x00 0xf1220000 0x00 0x10000 0x00 +0x00 0xf2100000 0x00 0x10000 0x00>; + interrupts = <0xc1>; + stream-connected-sbi = <0x67>; + reset-gpios = <0x5e 0x12>; + phandle = <0x6e>; + }; + + pmc_sha1@0xF1800000 { + doc-status = "complete"; + compatible = "zynqmp,csu-sha3"; + reg = <0x00 0xf1800000 0x00 0x10000 0x00>; + phandle = <0x6f>; + }; + }; + + amba_pmc_ppu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x4f>; + + pmc_gic_proxy@0 { + doc-status = "complete"; + #interrupt-cells = <0x03>; + interrupt-controller; + compatible = "xlnx,zynqmp-gicp"; + reg = <0x00 0xf1140000 0x00 0x100 0x00>; + interrupt-parent = <0x06>; + interrupts = <0x10>; + max-ints = <0x100>; + phandle = <0x04>; + }; + }; + + amba_pmc_sys@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC System"; + doc-status = "partial"; + phandle = <0x51>; + + pmc_clk_rst@0xf1260000 { + doc-status = "partial"; + compatible = "xlnx,pmx_crp"; + reg = <0x00 0xf1260000 0x00 0x80000 0x00>; + interrupts = <0xbca>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x5e>; + }; + + pmc_int@0xf1400000 { + doc-status = "partial"; + compatible = "xlnx,versal-pmc-int"; + reg = <0x00 0xf1400000 0x00 0x300000 0x00>; + interrupts = <0xc0>; + phandle = <0x110>; + }; + + pmc_reset_domain@0 { + compatible = "qemu,reset-device"; + gpios = <0x5e 0x02>; + }; + + pmc_global@0xf1110000 { + doc-status = "partial"; + #gpio-cells = <0x01>; + gpio-controller; + interrupts-extended = <0x06 0x10 0x06 0x1b 0x06 0x1b 0x06 +0x1b 0x06 0x1b 0x06 0x11 0x06 0x11 0x72 0x00 0x66 0x10 0x66 0x11 0x66 0x12 0x66 0x13 0x66 +0x14 0x66 0x15 0x66 0x16 0x66 0x17 0x66 0x18 0x66 0x19 0x66 0x1a 0x66 0x1b 0x72 0x00 0x66 0x1d>; + reg = <0x00 0xf1110000 0x00 0x50000 0x00>; + gpios = <0x73 0x00>; + bbram = <0x74>; + efuse = <0x75>; + compatible = "xlnx,pmx_global"; + phandle = <0x76>; + }; + + pmc_err_mng@0xF1130000 { + compatible = "xlnx,PmcErrMngmnt"; + reg = <0x00 0xf1130000 0x00 0x10000 0x00>; + interrupts = <0xbca>; + phandle = <0x111>; + }; + + pmc_stream_zero@ { + compatible = "xlnx,pmc-stream-zero"; + reg = <0x00 0xf1110518 0x00 0x04 0x01>; + stream-connected-pzm = <0x67>; + phandle = <0x112>; + }; + + pmc_analog@0xf1160000 { + compatible = "xlnx,pmx_anlg"; + reg = <0x00 0xf1160000 0x00 0x40000 0x00>; + interrupts-extended = <0x04 0x00 0xdd 0x00>; + tamper-sink = <0x76>; + }; + + pmc_sysmon@0xf1270000 { + compatible = "xlnx,pmc-sysmon"; + reg = <0x00 0xf1270000 0x00 0x30000 0x00>; + interrupts = <0xca 0xcb>; + reset-gpios = <0x5e 0x15>; + efuse = <0x75>; + ams-sats = <0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d>; + tamper-sink = <0x76>; + phandle = <0x113>; + }; + + pmc_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xf1280000 0x00 0x10000 0x01>; + phandle = <0x77>; + }; + + pmc_ams_sat@1 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xf1290000 0x00 0x10000 0x01>; + phandle = <0x78>; + }; + + versal_pmc_tamper@ { + compatible = "xlnx,pmc_tamper"; + reg-extended = <0x51 0x00 0xf1110530 0x00 0x38 0x01 0x7e +0x00 0xf0041100 0x00 0x38 0x02>; + phandle = <0x114>; + }; + + lpd_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xeb550000 0x00 0x10000 0x01>; + phandle = <0x79>; + }; + + fpd_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecc30000 0x00 0x10000 0x01>; + phandle = <0x7a>; + }; + + fpd_ams_sat@1 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecd30000 0x00 0x10000 0x01>; + phandle = <0x7b>; + }; + + fpd_ams_sat@2 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xece30000 0x00 0x10000 0x01>; + phandle = <0x7c>; + }; + + fpd_ams_sat@3 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecf30000 0x00 0x10000 0x01>; + phandle = <0x7d>; + }; + }; + + amba_pmc_pl@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC PL"; + doc-status = "partial"; + phandle = <0x52>; + + noc_npi_nir@0xf6000000 { + compatible = "xlnx.npi-nir"; + reg = <0x00 0xf6000000 0x00 0x10000 0x01>; + phandle = <0x115>; + }; + + npi_ddrmc_ub0@0xf67c0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf67c0000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x116>; + }; + + npi_ddrmc_main0@0xf6790000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6790000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0xa5>; + }; + + npi_ddrmc_noc0@0xf67a0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf67a0000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x117>; + }; + + npi_ddrmc_ub1@0xf68b0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf68b0000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x118>; + }; + + npi_ddrmc_main1@0xf6880000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6880000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x119>; + }; + + npi_ddrmc_noc1@0xf6890000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6890000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x11a>; + }; + + npi_ddrmc_ub2@0xf6dc0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf6dc0000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x11b>; + }; + + npi_ddrmc_main2@0xf6d90000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6d90000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x11c>; + }; + + npi_ddrmc_noc2@0xf6da0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6da0000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x11d>; + }; + + npi_ddrmc_ub3@0xf6eb0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf6eb0000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x11e>; + }; + + npi_ddrmc_main3@0xf6e80000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6e80000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x11f>; + }; + + npi_ddrmc_noc3@0xf6e90000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6e90000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x120>; + }; + + npi_ddrmc_ub4@0xf6f70000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf6f70000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x121>; + }; + + npi_ddrmc_main4@0xf6f40000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6f40000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x122>; + }; + + npi_ddrmc_noc4@0xf6f50000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6f50000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x123>; + }; + + npi_ddrmc_ub5@0xf7060000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf7060000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x124>; + }; + + npi_ddrmc_main5@0xf7030000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf7030000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x125>; + }; + + npi_ddrmc_noc5@0xf7040000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf7040000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x126>; + }; + + npi_ddrmc_ub6@0xf7320000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf7320000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x127>; + }; + + npi_ddrmc_main6@0xf72f0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf72f0000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x128>; + }; + + npi_ddrmc_noc6@0xf7300000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf7300000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x129>; + }; + + npi_ddrmc_ub7@0xf7400000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf7400000 0x00 0x40000 0x01>; + reset-gpios = <0x5e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x12a>; + }; + + npi_ddrmc_main7@0xf73d0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf73d0000 0x00 0x10000 0x01>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x12b>; + }; + + npi_ddrmc_noc7@0xf73e0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf73e0000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x5e 0x0f>; + phandle = <0x12c>; + }; + + npi_ddrmc_xmpu0@0xf67a0000 { + compatible = "xlnx,versal-ddrmc-xmpu"; + reg-extended = <0x52 0x00 0xf67b0000 0x00 0x10000 0x01 0x0b +0x00 0x00 0x00 0x80000000 0x00>; + protected-mr = <0x7f>; + mr-0 = <0x0b>; + protected-base = <0x00>; + phandle = <0x12d>; + }; + + noc_npi_devs@0 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xf6000000 0x00 0x2000000 0x00>; + phandle = <0x12e>; + }; + + cfu_fdro@0xf12c2000 { + compatible = "xlnx,versal-cfu-fdro"; + reg = <0x00 0xf12c2000 0x00 0x1000 0x00>; + phandle = <0x81>; + }; + + cfu_sfr@0xf12c1000 { + compatible = "xlnx,versal-cfu-sfr"; + reg = <0x00 0xf12c1000 0x00 0x1000 0x00>; + cfu = <0x80>; + phandle = <0x12f>; + }; + + cframe0_reg@0xf12d0000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d0000 0x00 0x1000 0x00 +0x00 0xf12d1000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + blktype0-frames = <0x853f>; + blktype1-frames = <0xdc8>; + blktype2-frames = <0x3200>; + blktype3-frames = <0x0b>; + blktype4-frames = <0x05>; + blktype5-frames = <0x01>; + blktype6-frames = <0x01>; + phandle = <0x82>; + }; + + cframe1_reg@0xf12d2000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d2000 0x00 0x1000 0x00 +0x00 0xf12d3000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0x83>; + }; + + cframe2_reg@0xf12d4000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d4000 0x00 0x1000 0x00 +0x00 0xf12d5000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0x84>; + }; + + cframe3_reg@0xf12d6000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d6000 0x00 0x1000 0x00 +0x00 0xf12d7000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0x85>; + }; + + cframe4_reg@0xf12d8000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d8000 0x00 0x1000 0x00 +0x00 0xf12d9000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x86>; + }; + + cframe5_reg@0xf12da000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12da000 0x00 0x1000 0x00 +0x00 0xf12db000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x87>; + }; + + cframe6_reg@0xf12dc000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12dc000 0x00 0x1000 0x00 +0x00 0xf12dd000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x88>; + }; + + cframe7_reg@0xf12de000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12de000 0x00 0x1000 0x00 +0x00 0xf12df000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x89>; + }; + + cframe8_reg@0xf12e0000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e0000 0x00 0x1000 0x00 +0x00 0xf12e1000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x8a>; + }; + + cframe9_reg@0xf12e2000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e2000 0x00 0x1000 0x00 +0x00 0xf12e3000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x8b>; + }; + + cframe10_reg@0xf12e4000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e4000 0x00 0x1000 0x00 +0x00 0xf12e5000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x8c>; + }; + + cframe11_reg@0xf12e6000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e6000 0x00 0x1000 0x00 +0x00 0xf12e7000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x8d>; + }; + + cframe12_reg@0xf12e8000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e8000 0x00 0x1000 0x00 0x00 +0xf12e9000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x8e>; + }; + + cframe13_reg@0xf12ea000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12ea000 0x00 0x1000 0x00 0x00 +0xf12eb000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x8f>; + }; + + cframe14_reg@0xf12ec000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12ec000 0x00 0x1000 0x00 0x00 +0xf12ed000 0x00 0x1000 0x00>; + interrupts = <0xb3>; + cfu-fdro = <0x81>; + phandle = <0x90>; + }; + + cframe_bcast_reg@0xf12ee000 { + compatible = "xlnx.cframe-bcast-reg"; + reg = <0x00 0xf12ee000 0x00 0x1000 0x00 +0x00 0xf12ef000 0x00 0x1000 0x00>; + cframe0 = <0x82>; + cframe1 = <0x83>; + cframe2 = <0x84>; + cframe3 = <0x85>; + cframe4 = <0x86>; + cframe5 = <0x87>; + cframe6 = <0x88>; + cframe7 = <0x89>; + cframe8 = <0x8a>; + cframe9 = <0x8b>; + cframe10 = <0x8c>; + cframe11 = <0x8d>; + cframe12 = <0x8e>; + cframe13 = <0x8f>; + cframe14 = <0x90>; + phandle = <0x130>; + }; + + gtm_npi_slave_0@0xf6ca0000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf6ca0000 0x00 0x20000 0x00>; + }; + + gtm_npi_slave_1@0xf6d10000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf6d10000 0x00 0x20000 0x00>; + }; + + hnicx_npi_0@0xf6af0000 { + compatible = "xlnx,hnicx_npi"; + reg = <0x00 0xf6af0000 0x00 0x20000 0x01>; + doc-limitations = "Just a stub"; + phandle = <0x131>; + }; + + hnicx_pllpor_0@0xf6b30000 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xf6b30000 0x00 0x10000 0x01>; + custom = <0x01>; + pcsr-status = <0x8011>; + phandle = <0x132>; + }; + + dummy_cfu_mem@0xf12b0000 { + compatible = "qemu:memory-region"; + phandle = <0x56>; + + cfu@0x0 { + doc-status = "partial"; + doc-comments = "Stub"; + doc-limitations = "No way to extract CFRAME data."; + compatible = "xlnx,versal-cfu"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x10000 0x00 0x1000 +0x00 0x00 0xcd0000 0x00 0x40000 0x00>; + chardev = "pmc-cfu"; + dma = <0x55>; + phandle = <0x80>; + }; + }; + }; + + amba_pmc_bat@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC BAT"; + doc-status = "partial"; + phandle = <0x53>; + + rtc@0xf12a0000 { + doc-status = "complete"; + doc-comments = "Versal PMC RTC"; + compatible = "xlnx,zynqmp-rtc"; + interrupts = <0xbca 0xc8 0xc9>; + reg = <0x00 0xf12a0000 0x00 0x10000 0x00>; + xlnx,version = "2.0.0"; + phandle = <0x133>; + }; + }; + + amba_psm@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x11>; + + psm_ram_instr@0xebc00000 { + device_type = "memory"; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + reg = <0x00 0xebc00000 0x00 0x20000 0x01>; + phandle = <0x134>; + }; + + psm_ram_data@0xebc20000 { + device_type = "memory"; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + reg = <0x00 0xebc20000 0x00 0x8000 0x01>; + phandle = <0x135>; + }; + + psm_gic_proxy@0 { + doc-status = "complete"; + #interrupt-cells = <0x03>; + interrupt-controller; + compatible = "xlnx,zynqmp-gicp"; + reg = <0x00 0xebc92000 0x00 0x100 0x00>; + interrupt-parent = <0x07>; + interrupts = <0x16>; + max-ints = <0x100>; + phandle = <0x05>; + }; + + psm_global_reg@0xebc90000 { + compatible = "xlnx,psmx_global_reg"; + reg = <0x00 0xebc90000 0x00 0xf000 0x00>; + interrupt-parent = <0x07>; + interrupts = <0x1c 0x1e 0x1a 0x1b 0x1f 0x18 0x19>; + #gpio-cells = <0x01>; + gpios = <0x17 0x23 0x17 0x24 0x17 0x25 0x17 0x26 0x17 0x27 +0x17 0x28 0x17 0x29 0x17 0x2a 0x17 0x2b 0x17 0x2c 0x17 0x2d 0x17 0x2e 0x17 0x2f 0x17 0x30 +0x17 0x31 0x17 0x32 0x17 0x33 0x17 0x34 0x17 0x35 0x17 0x36 0x17 0x37 0x17 0x38 0x17 0x39 +0x17 0x3a 0x17 0x3b 0x17 0x3c 0x17 0x3d 0x17 0x3e 0x17 0x3f 0x17 0x40 0x17 0x41 0x17 0x42 +0x17 0x43 0x17 0x44 0x17 0x45 0x17 0x46 0x17 0x47 0x17 0x48 0x17 0x49 0x17 0x4a 0x17 0x4b +0x17 0x4c 0x17 0x4d 0x17 0x4e 0x17 0x4f 0x17 0x50 0x17 0x51 0x17 0x52 0x17 0x53 0x17 0x54 +0x17 0x55 0x17 0x56 0x17 0x57 0x17 0x58 0x17 0x59 0x17 0x5a 0x17 0x5b 0x17 0x5c 0x17 0x5d +0x17 0x5e 0x17 0x5f 0x17 0x60 0x17 0x61 0x17 0x62 0x17 0x63 0x17 0x64 0x17 0x65 0x91 0x00 +0x91 0x01 0x91 0x02 0x91 0x03 0x02 0x00 0x02 0x01 0x03 0x00 0x03 0x01>; + gpio-controller; + phandle = <0xab>; + }; + + psm_err_mng@0xebc90000 { + compatible = "xlnx.psmx_err_reg"; + reg = <0x00 0xebc91000 0x00 0x100 0x00>; + phandle = <0x136>; + }; + + psm_reset_domain@0 { + compatible = "qemu,reset-domain"; + mr0 = <0x92>; + mr1 = <0x11>; + reset-gpios = <0x5e 0x07>; + }; + }; + + amba_xram@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0d>; + + xram_ctrl_0 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb8e0000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_1 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb8f0000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_2 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb900000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_3 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb910000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + }; + + crf@0xec200000 { + compatible = "xlnx,versal-psx-crf"; + reg-extended = <0x09 0x00 0xec200000 0x00 0x100000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x31>; + }; + }; + + lmb_pmc_ppu0@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB PPU0"; + doc-status = "complete"; + phandle = <0x7e>; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x55>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + pmc_rom@0xf0000000 { + reg = <0x00 0xf0000000 0x00 0x40000 0x01>; + compatible = "qemu:memory-region"; + container = <0x7e>; + qemu,ram = <0x01>; + read-only; + phandle = <0x137>; + }; + + ppu0_ram@0xf0060000 { + reg = <0x00 0xf0060000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + container = <0x7e>; + qemu,ram = <0x01>; + phandle = <0x138>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0x7e>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_1"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x139>; + + pmc_ppu0_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0x93 0x00>; + reg = <0x00 0xf008000c 0x04 0x00 0xf0080030 0x10 +0x00 0xf0080080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x66>; + }; + + pmc_ppu0_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x66>; + interrupts = <0x0b>; + reg = <0x00 0xf0080020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x13a>; + }; + + pmc_ppu0_gpi@24 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x66>; + interrupts = <0x0c>; + reg = <0x00 0xf0080024 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x13b>; + }; + + pmc_ppu0_gpi@28 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x66>; + interrupts = <0x0d>; + reg = <0x00 0xf0080028 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x13c>; + }; + + pmc_ppu0_gpi@2c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x66>; + interrupts = <0x0e>; + reg = <0x00 0xf008002c 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x13d>; + }; + + pmc_ppu0_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x09>; + xlnx,use-gpo = <0x01>; + phandle = <0x94>; + }; + + pmc_ppu0_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x13e>; + }; + + pmc_ppu0_gpo@18 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080018 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x13f>; + }; + + pmc_ppu0_gpo@1c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf008001c 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x140>; + }; + + pmc_ppu0_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x66>; + interrupts = <0x03>; + reg = <0x00 0xf0080040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0x94 0x01 0x95 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x141>; + }; + + pmc_ppu0_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x66>; + interrupts = <0x04>; + reg = <0x00 0xf0080050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x95>; + }; + + pmc_ppu0_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x66>; + interrupts = <0x05>; + reg = <0x00 0xf0080060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0x94 0x06 0x96 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x142>; + }; + + pmc_ppu0_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x66>; + interrupts = <0x06>; + reg = <0x00 0xf0080070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x96>; + }; + }; + }; + + lmb_pmc_ppu1@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB PPU1"; + doc-status = "complete"; + phandle = <0x97>; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x55>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0x97>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_1"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x143>; + + pmc_ppu1_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0x98 0x00>; + reg = <0x00 0xf030000c 0x04 0x00 0xf0300030 0x10 +0x00 0xf0300080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x06>; + }; + + pmc_ppu1_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x06>; + interrupts = <0x0b>; + reg = <0x00 0xf0300020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x144>; + }; + + pmc_ppu1_gpi@24 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x06>; + interrupts = <0x0c>; + reg = <0x00 0xf0300024 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x145>; + }; + + pmc_ppu1_gpi@28 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x06>; + interrupts = <0x0d>; + reg = <0x00 0xf0300028 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x146>; + }; + + pmc_ppu1_gpi@2c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x06>; + interrupts = <0x0e>; + reg = <0x00 0xf030002c 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x147>; + }; + + pmc_ppu1_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x09>; + xlnx,use-gpo = <0x01>; + phandle = <0x99>; + }; + + pmc_ppu1_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x148>; + }; + + pmc_ppu1_gpo@18 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300018 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x149>; + }; + + pmc_ppu1_gpo@1c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf030001c 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x14a>; + }; + + pmc_ppu1_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x06>; + interrupts = <0x03>; + reg = <0x00 0xf0300040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpios = <0x99 0x01 0x9a 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x14b>; + }; + + pmc_ppu1_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x06>; + interrupts = <0x04>; + reg = <0x00 0xf0300050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x9a>; + }; + + pmc_ppu1_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x06>; + interrupts = <0x05>; + reg = <0x00 0xf0300060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpios = <0x99 0x06 0x9b 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + windows-frequency = <0x13d620>; + phandle = <0x14c>; + }; + + pmc_ppu1_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x06>; + interrupts = <0x06>; + reg = <0x00 0xf0300070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x9b>; + }; + }; + }; + + lmb_psm@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB PPU0"; + doc-status = "in-progress"; + phandle = <0x92>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0b>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x11>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "simple-bus"; + priority = <0xffffffff>; + container = <0x92>; + phandle = <0x14d>; + + psm0_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0x93 0x00>; + reg = <0x00 0xebc8000c 0x04 0x00 0xebc80030 0x10 +0x00 0xebc80080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x07>; + }; + + psm0_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xebc80010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x03>; + xlnx,use-gpo = <0x01>; + phandle = <0x9c>; + }; + + psm0_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x07>; + interrupts = <0x03>; + reg = <0x00 0xebc80040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0x9c 0x01 0x9d 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x14e>; + }; + + psm0_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x07>; + interrupts = <0x04>; + reg = <0x00 0xebc80050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x9d>; + }; + + psm0_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x07>; + interrupts = <0x05>; + reg = <0x00 0xebc80060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0x9c 0x06 0x9e 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x14f>; + }; + + psm0_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x07>; + interrupts = <0x06>; + reg = <0x00 0xebc80070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x9e>; + }; + }; + + psm_local_reg@0xebc88000 { + gpio-controller; + #gpio-cells = <0x01>; + compatible = "xlnx,psmx_local_reg"; + reg = <0x00 0xebc88000 0x00 0x8000 0x00>; + phandle = <0x17>; + }; + }; + + lmb_ddrmc@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB DDRMC0"; + doc-status = "partial"; + phandle = <0x9f>; + + ddrmc0_ram_data@0x1c000 { + reg = <0x00 0x1c000 0x00 0x4000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x150>; + }; + + ddrmc0_ram_instr@0x20000 { + reg = <0x00 0x20000 0x00 0x20000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x151>; + }; + + ddrmc0_ram_exchange@0x08000 { + reg = <0x00 0x8000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x152>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "simple-bus"; + container = <0x9f>; + priority = <0xffffffff>; + phandle = <0x153>; + + ddrmc0_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xa0 0x00>; + reg = <0x00 0x1b00c 0x04 0x00 0x1b030 0x10 0x00 0x1b080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0xa1>; + }; + + ddrmc0_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0x1b010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x03>; + xlnx,use-gpo = <0x01>; + phandle = <0xa2>; + }; + + ddrmc0_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xa1>; + interrupts = <0x03>; + reg = <0x00 0x1b040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xa2 0x01 0xa3 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x154>; + }; + + ddrmc0_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xa1>; + interrupts = <0x04>; + reg = <0x00 0x1b050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xa3>; + }; + + ddrmc0_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xa1>; + interrupts = <0x05>; + reg = <0x00 0x1b060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xa2 0x06 0xa4 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x155>; + }; + + ddrmc0_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xa1>; + interrupts = <0x06>; + reg = <0x00 0x1b070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xa4>; + }; + }; + + ddrmc_uart0@0 { + compatible = "xlnx,io_uart"; + reg = <0x00 0x1b000 0x0c 0x1b04c 0x04>; + xlnx,use-uart-rx = <0x01>; + xlnx,use-uart-tx = <0x01>; + chardev = "ddrmc-uart0\0serial1"; + phandle = <0x156>; + }; + + alias_npi_ddrmc_main { + compatible = "qemu:memory-region"; + alias = <0xa5>; + reg = <0x00 0x00 0x00 0x8000 0x00>; + }; + }; + + lmb_ddrmc@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x157>; + + ddrmc1_ram_data@0x1c000 { + reg = <0x00 0x1c000 0x00 0x4000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x158>; + }; + + ddrmc1_ram_instr@0x20000 { + reg = <0x00 0x20000 0x00 0x20000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x159>; + }; + + ddrmc1_ram_exchange@0x08000 { + reg = <0x00 0x8000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x15a>; + }; + }; + + amba_rpu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xa6>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0b>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + timer_a { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x02>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_b { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x03>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + }; + + amba_r5@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xac>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xa6>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0xa7>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic0 { + compatible = "qemu:memory-region"; + alias = <0xa8>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + }; + + amba_r5@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xaf>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xa6>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0xa9>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic0 { + compatible = "qemu:memory-region"; + alias = <0xa8>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + }; + + dummy1@0 { + doc-ignore = <0x01>; + interrupt-controller; + #interrupt-cells = <0x01>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x72>; + }; + + tbu0_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x13>; + }; + + tbu1_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x42>; + }; + + tbu2_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x43>; + }; + + tbu3_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x44>; + }; + + tbu4_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x45>; + }; + + tbu5_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x46>; + }; + + tbu6_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x47>; + }; + + memory@00000000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0b>; + phandle = <0xb9>; + }; + + memory@8_0000_0000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0b>; + phandle = <0xba>; + }; + + memory@0x50000000000ULL { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0b>; + phandle = <0x15b>; + }; + + ocm_mem@0xbbf00000 { + compatible = "qemu:memory-region"; + phandle = <0x0c>; + }; + + ocm_mem_bank_0@ { + compatible = "qemu:memory-region"; + container = <0x0c>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x20000 0x00>; + phandle = <0x15c>; + }; + + ocm_mem_bank_1@ { + compatible = "qemu:memory-region"; + container = <0x0c>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x20000 0x00>; + phandle = <0x15d>; + }; + + ocm_mem_bank_2@ { + compatible = "qemu:memory-region"; + container = <0x0c>; + qemu,ram = <0x01>; + reg = <0x00 0x40000 0x00 0x20000 0x00>; + phandle = <0x15e>; + }; + + ocm_mem_bank_3@ { + compatible = "qemu:memory-region"; + container = <0x0c>; + qemu,ram = <0x01>; + reg = <0x00 0x60000 0x00 0x20000 0x00>; + phandle = <0x15f>; + }; + + xram_mem@0xea800000 { + compatible = "qemu:memory-region"; + phandle = <0x0e>; + }; + + xram_mem_bank_0@0x0 { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x200000 0x00>; + phandle = <0x160>; + }; + + xram_mem_bank_1@0x200000 { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x200000 0x00 0x200000 0x00>; + phandle = <0x161>; + }; + + xram_mem_bank_2@0x400000 { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x400000 0x00 0x200000 0x00>; + phandle = <0x162>; + }; + + xram_mem_bank_3@0x600000 { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x600000 0x00 0x200000 0x00>; + phandle = <0x163>; + }; + + ipi_msgbuf@0 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x08>; + qemu,ram = <0x01>; + reg = <0x00 0xeb3f0000 0x00 0x1000 0x00>; + phandle = <0x164>; + }; + + pmc_ram@0xf2000000 { + compatible = "qemu:memory-region"; + phandle = <0x54>; + }; + + pmc_ram_bank_0@0x0 { + compatible = "qemu:memory-region"; + container = <0x54>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x20000 0x00>; + phandle = <0x165>; + }; + + pmc_ppu1_ram@0xf0200000 { + compatible = "qemu:memory-region"; + container = <0x0b>; + qemu,ram = <0x01>; + reg = <0x00 0xf0200000 0x00 0x80000 0x00>; + phandle = <0x166>; + }; + + pmc_ppu1_ram@0xf0280000 { + compatible = "qemu:memory-region"; + container = <0x0b>; + qemu,ram = <0x01>; + reg = <0x00 0xf0280000 0x00 0x20000 0x00>; + phandle = <0x167>; + }; + + ppu0_mdm_uart@0xf0110000 { + doc-status = "complete"; + compatible = "xlnx,xps-uartlite"; + reg-extended = <0x7e 0x00 0xf0110000 0x00 0x10 0x01>; + chardev = "serial0"; + }; + + ppu1_mdm_uart@0xf0310000 { + doc-status = "complete"; + compatible = "xlnx,xps-uartlite"; + reg-extended = <0x97 0x00 0xf0310000 0x00 0x10 0x01>; + chardev = "serial1"; + }; + + lqspi_mr@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x60>; + }; + + lospi_mr@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x62>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + apu_cpu@0 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x00>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 0"; + #interrupt-cells = <0x01>; + reset-gpios = <0x31 0x00>; + gpios = <0xab 0x43>; + gpio-names = "wfi"; + power-gpios = <0x17 0x00>; + mp-affinity = <0x00>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x32>; + }; + + apu_cpu@1 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x01>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 1"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x01>; + gpios = <0xab 0x44>; + gpio-names = "wfi"; + power-gpios = <0x17 0x01>; + mp-affinity = <0x100>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x33>; + }; + + apu_cpu@2 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x02>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 2"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x02>; + gpios = <0xab 0x45>; + gpio-names = "wfi"; + power-gpios = <0x17 0x02>; + mp-affinity = <0x200>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x34>; + }; + + apu_cpu@3 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x03>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 3"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x03>; + gpios = <0xab 0x46>; + gpio-names = "wfi"; + power-gpios = <0x17 0x03>; + mp-affinity = <0x300>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x35>; + }; + + apu_cpu@4 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x04>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 4"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x04>; + gpios = <0xab 0x47>; + gpio-names = "wfi"; + power-gpios = <0x17 0x04>; + mp-affinity = <0x10000>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x36>; + }; + + apu_cpu@5 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x05>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 5"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x05>; + gpios = <0xab 0x48>; + gpio-names = "wfi"; + power-gpios = <0x17 0x05>; + mp-affinity = <0x10100>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x37>; + }; + + apu_cpu@6 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x06>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 6"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x06>; + gpios = <0xab 0x49>; + gpio-names = "wfi"; + power-gpios = <0x17 0x06>; + mp-affinity = <0x10200>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x38>; + }; + + apu_cpu@7 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x07>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 7"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x07>; + gpios = <0xab 0x4a>; + gpio-names = "wfi"; + power-gpios = <0x17 0x07>; + mp-affinity = <0x10300>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x39>; + }; + + apu_cpu@8 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x08>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 8"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x08>; + gpios = <0xab 0x4b>; + gpio-names = "wfi"; + power-gpios = <0x17 0x08>; + mp-affinity = <0x20000>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x3a>; + }; + + apu_cpu@9 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x09>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 9"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x09>; + gpios = <0xab 0x4c>; + gpio-names = "wfi"; + power-gpios = <0x17 0x09>; + mp-affinity = <0x20100>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x3b>; + }; + + apu_cpu@10 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x0a>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 10"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x0a>; + gpios = <0xab 0x4d>; + gpio-names = "wfi"; + power-gpios = <0x17 0x0a>; + mp-affinity = <0x20200>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x3c>; + }; + + apu_cpu@11 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x0b>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 11"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x0b>; + gpios = <0xab 0x4e>; + gpio-names = "wfi"; + power-gpios = <0x17 0x0b>; + mp-affinity = <0x20300>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x3d>; + }; + + apu_cpu@12 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x0c>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 12"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x0c>; + gpios = <0xab 0x4f>; + gpio-names = "wfi"; + power-gpios = <0x17 0x0c>; + mp-affinity = <0x30000>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x3e>; + }; + + apu_cpu@13 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x0d>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 13"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x0d>; + gpios = <0xab 0x50>; + gpio-names = "wfi"; + power-gpios = <0x17 0x0d>; + mp-affinity = <0x30100>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x3f>; + }; + + apu_cpu@14 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x0e>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 14"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x0e>; + gpios = <0xab 0x51>; + gpio-names = "wfi"; + power-gpios = <0x17 0x0e>; + mp-affinity = <0x30200>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x40>; + }; + + apu_cpu@15 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x0f>; + core-count = <0x04>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xaa>; + memory = <0xaa>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 15"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + reset-gpios = <0x31 0x0f>; + gpios = <0xab 0x52>; + gpio-names = "wfi"; + power-gpios = <0x17 0x0f>; + mp-affinity = <0x30300>; + generic-timer-frequency = <0x5f5e100>; + phandle = <0x41>; + }; + + rpu_a@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x168>; + + rpu_cpu_a@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x00>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xac>; + qemu,halt = <0x01>; + memattr_ns = <0xad>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #a0"; + gpios = <0x16 0x23 0xae 0x00 0x91 0x04>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + phandle = <0x29>; + }; + + rpu_cpu_a@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x01>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xaf>; + qemu,halt = <0x01>; + memattr_ns = <0xb0>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #a1"; + gpios = <0x16 0x24 0xb1 0x00 0x91 0x05>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + phandle = <0x2b>; + }; + }; + + rpu_b@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x169>; + + rpu_cpu_b@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x100>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xb2>; + qemu,halt = <0x01>; + memattr_ns = <0xb3>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #b0"; + gpios = <0x16 0x25 0xb4 0x00 0x91 0x06>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + phandle = <0x2d>; + }; + + rpu_cpu_b@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x101>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xb5>; + qemu,halt = <0x01>; + memattr_ns = <0xb6>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #b1"; + gpios = <0x16 0x26 0xb7 0x00 0x91 0x07>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + phandle = <0x2f>; + }; + }; + }; + + amba_apu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xaa>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0b>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x01>; + interrupts = <0x1000001 0x0d 0xffffff01 0x1000001 0x0e +0xffffff01 0x1000001 0x0b 0xffffff01 0x1000001 0x0a 0xffffff01>; + clock-frequency = <0x5f5e100>; + phandle = <0x16a>; + }; + }; + + amba_apu_gic@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + container = <0x09>; + priority = <0xffffffff>; + phandle = <0x16b>; + + interrupt-controller@0xe2000000 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0xe2000000 0x00 0x10000 0x00 0x00 0xe2060000 +0x00 0x400000 0x00>; + interrupt-controller; + interrupts-extended = <0x32 0x00 0x33 0x00 0x34 0x00 0x35 0x00 0x36 0x00 +0x37 0x00 0x38 0x00 0x39 0x00 0x3a 0x00 0x3b 0x00 0x3c 0x00 0x3d 0x00 0x3e 0x00 0x3f 0x00 0x40 0x00 +0x41 0x00 0x32 0x01 0x33 0x01 0x34 0x01 0x35 0x01 0x36 0x01 0x37 0x01 0x38 0x01 0x39 0x01 0x3a +0x01 0x3b 0x01 0x3c 0x01 0x3d 0x01 0x3e 0x01 0x3f 0x01 0x40 0x01 0x41 0x01 0x32 0x02 0x33 +0x02 0x34 0x02 0x35 0x02 0x36 0x02 0x37 0x02 0x38 0x02 0x39 0x02 0x3a 0x02 0x3b 0x02 0x3c +0x02 0x3d 0x02 0x3e 0x02 0x3f 0x02 0x40 0x02 0x41 0x02 0x32 0x03 0x33 0x03 0x34 0x03 0x35 +0x03 0x36 0x03 0x37 0x03 0x38 0x03 0x39 0x03 0x3a 0x03 0x3b 0x03 0x3c 0x03 0x3d 0x03 0x3e +0x03 0x3f 0x03 0x40 0x03 0x41 0x03 0x01 0x01 0x09 0x104 0x01 0x01 0x09 0x204 0x01 0x01 +0x09 0x404 0x01 0x01 0x09 0x804 0x01 0x01 0x09 0x1004 0x01 0x01 0x09 0x2004 0x01 0x01 0x09 +0x4004 0x01 0x01 0x09 0x8004 0x01 0x01 0x09 0x10004 0x01 0x01 0x09 0x20004 0x01 0x01 0x09 +0x40004 0x01 0x01 0x09 0x80004 0x01 0x01 0x09 0x100004 0x01 0x01 0x09 0x200004 0x01 0x01 +0x09 0x400004>; + num-cpu = <0x10>; + num-irq = <0x220>; + has-security-extensions = <0x01>; + redist-region-count = <0x10>; + has-lpi = <0x01>; + sysmem = <0x0b>; + phandle = <0x01>; + }; + + git_its@0xe2040000 { + compatible = "arm-gicv3-its"; + reg = <0x00 0xe2040000 0x00 0x20000 0x00>; + parent-gicv3 = <0x01>; + }; + }; + + lpd_reset_domain@0 { + compatible = "qemu,reset-domain"; + mr0 = <0x08>; + reset-gpios = <0x5e 0x07 0x5e 0x0a>; + }; + + fpd_reset_domain@0 { + compatible = "qemu,reset-domain"; + mr0 = <0x09>; + reset-gpios = <0x5e 0x07 0x5e 0x0a 0x16 0x1c 0x16 0x1d>; + }; + + amba_alias@0 { + compatible = "qemu:memory-region"; + container = <0xb8>; + alias = <0x0b>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x01>; + phandle = <0x16c>; + }; + + qemu_sysmem@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:system-memory"; + phandle = <0xb8>; + }; + + dummy_ppu0@0 { + #interrupt-cells = <0x01>; + phandle = <0x93>; + }; + + dummy_ppu1@0 { + #interrupt-cells = <0x01>; + phandle = <0x98>; + }; + + dummy_ddrmc0@0 { + #interrupt-cells = <0x01>; + phandle = <0xa0>; + }; + + dummy_ddrmc1@0 { + #interrupt-cells = <0x01>; + phandle = <0x16d>; + }; + + ddr@0x00000000 { + compatible = "qemu:memory-region"; + container = <0xb9>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x80000000 0x00>; + phandle = <0x7f>; + }; + + ddr_2@0x800000000ULL { + compatible = "qemu:memory-region-spec"; + container = <0xba>; + qemu,ram = <0x01>; + reg = <0x08 0x00 0x08 0x00 0x00>; + phandle = <0x16e>; + }; + + mdio { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "mdio"; + phandle = <0x18>; + + phy@1 { + compatible = "dp83867"; + device_type = "ethernet-phy"; + reg = <0x01>; + phandle = <0x16f>; + }; + }; + + cpu_dummy { + phandle = <0x170>; + }; + + tbu7_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x48>; + }; + + tbu8_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x49>; + }; + + tbu9_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x4a>; + }; + + tbu10_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x4b>; + }; + + tbu11_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x4c>; + }; + + tbu12_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x4d>; + }; + + mr_rpu_gic_a@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0xa8>; + + rpu_gic_a@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x29 0x00 0x2b 0x00 0x29 0x01 0x2b 0x01 0x29 0x02 +0x2b 0x02 0x29 0x03 0x2b 0x03 0x02 0x01 0x09 0x104 0x02 0x01 0x09 0x204>; + first-cpu-idx = <0x10>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x02>; + }; + }; + + mr_rpu_gic_b@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0xbd>; + + rpu_gic_b@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x2d 0x00 0x2f 0x00 0x2d 0x01 0x2f 0x01 0x2d 0x02 +0x2f 0x02 0x2d 0x03 0x2f 0x03 0x03 0x01 0x09 0x104 0x03 0x01 0x09 0x204>; + first-cpu-idx = <0x12>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x03>; + }; + }; + + tcm_core@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0xa7>; + + atcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0xa7>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x171>; + }; + + btcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0xa7>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x172>; + }; + + ctcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0xa7>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x173>; + }; + }; + + tcm_core@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0xa9>; + + atcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0xa9>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x174>; + }; + + btcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0xa9>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x175>; + }; + + ctcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0xa9>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x176>; + }; + }; + + tcm_core@2 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0xbb>; + + atcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0xbb>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x177>; + }; + + btcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0xbb>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x178>; + }; + + ctcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0xbb>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x179>; + }; + }; + + tcm_core@3 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0xbc>; + + atcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0xbc>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x17a>; + }; + + btcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0xbc>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x17b>; + }; + + ctcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0xbc>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x17c>; + }; + }; + + tcm_cluster_a@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x0f>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0xa7>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0xa9>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_b@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x10>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0xbb>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0xbc>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + amba_r5@2 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xb2>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0xbb>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic1 { + compatible = "qemu:memory-region"; + alias = <0xbd>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xa6>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@3 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xb5>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0xbc>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic1 { + compatible = "qemu:memory-region"; + alias = <0xbd>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xa6>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + rpu2_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xb3>; + }; + + rpu3_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xb6>; + }; + + usb1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x232>; + phandle = <0x30>; + }; + + __symbols__ { + pmc_ppu0_memattr = "/pmc_ppu0_ma"; + pmc_ppu1_memattr = "/pmc_ppu1_ma"; + psm_memattr = "/psm_ma"; + ddrmc_ub0_memattr = "/ddrmc_ub0_ma"; + ddrmc_ub1_memattr = "/ddrmc_ub1_ma"; + pmc_dma0_memattr = "/pmc_dma0_ma"; + pmc_dma1_memattr = "/pmc_dma1_ma"; + pmc_qspi_dma_memattr_smid = "/pmc_qspi_dma_ma_smid"; + pmc_qspi_dma_w_memattr_smid = "/pmc_qspi_dma_w_ma_smid"; + apu0_s_memattr = "/apu0_s_ma"; + apu0_ns_memattr = "/apu0_ns_ma"; + apu1_s_memattr = "/apu1_s_ma"; + apu1_ns_memattr = "/apu1_ns_ma"; + rpu0_s_memattr = "/rpu0_s_ma"; + rpu1_s_memattr = "/rpu1_s_ma"; + gem0_memattr_smid = "/gem0_ma_smid"; + gem0_w_memattr_smid = "/gem0_w_ma_smid"; + gem1_memattr_smid = "/gem1_ma_smid"; + gem1_w_memattr_smid = "/gem1_w_ma_smid"; + ospi_dma_memattr_smid = "/ospi_dma_ma_smid"; + ospi_dma_w_memattr_smid = "/ospi_dma_w_ma_smid"; + sd0_memattr_smid = "/sd0_ma_smid"; + sd0_w_memattr_smid = "/sd0_w_ma_smid"; + sd1_memattr_smid = "/sd1_ma_smid"; + sd1_w_memattr_smid = "/sd1_w_ma_smid"; + usb0_memattr = "/usb0_ma"; + amba_root = "/amba_root@0"; + amba = "/amba_root@0/amba@0"; + xmpu_ocm = "/amba_root@0/amba@0/xmpu_ocm@0"; + xmpu_ocm2 = "/amba_root@0/amba@0/xmpu_ocm2@0"; + loader_write_0xF1110880 = "/amba_root@0/amba@0/loader_write_cpu0_0x1@0xF1110880"; + loader_write_0xFD1A0050 = "/amba_root@0/amba@0/loader_write_cpu0_0x5@0xFD1A0050"; + loader_write_0xF111010C = "/amba_root@0/amba@0/loader_write_cpu0_0xFF@0xF111010C"; + s_axi_tcm_a = "/amba_root@0/amba@0/s_axi_tcm_a@0"; + s_axi_tcm_b = "/amba_root@0/amba@0/s_axi_tcm_b@0"; + loader_write_0xF12B0100 = "/amba_root@0/amba@0/loader_write_cpu0_0x80C@0xF12B0100"; + amba_lpd = "/amba_root@0/amba_lpd@0"; + xppu_lpd = "/amba_root@0/amba_lpd@0/xppu_lpd@0xeb990000"; + gem0 = "/amba_root@0/amba_lpd@0/ethernet@0xf19e0000"; + gem1 = "/amba_root@0/amba_lpd@0/ethernet@0xf19f0000"; + serial0 = "/amba_root@0/amba_lpd@0/serial@0xf1920000"; + serial1 = "/amba_root@0/amba_lpd@0/serial@0xf1930000"; + canfdbus0 = "/amba_root@0/amba_lpd@0/canfdbus@0"; + can0 = "/amba_root@0/amba_lpd@0/can@0xf1980000"; + can1 = "/amba_root@0/amba_lpd@0/can@0xf1990000"; + crl = "/amba_root@0/amba_lpd@0/crl@0xeb5e0000"; + lpd_iou_slcr = "/amba_root@0/amba_lpd@0/slcr@0xf19a0000"; + ipi = "/amba_root@0/amba_lpd@0/ipi@0xeb300000"; + spi0 = "/amba_root@0/amba_lpd@0/spi@0xf1960000"; + spi0_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf1960000/spi0_flash0@0"; + spi1 = "/amba_root@0/amba_lpd@0/spi@0xf1970000"; + spi1_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf1970000/spi1_flash0@0"; + dwc3_0 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI"; + ttc0 = "/amba_root@0/amba_lpd@0/timer@0xf1dc0000"; + ttc1 = "/amba_root@0/amba_lpd@0/timer@0xf1dd0000"; + ttc2 = "/amba_root@0/amba_lpd@0/timer@0xf1de0000"; + ttc3 = "/amba_root@0/amba_lpd@0/timer@0xf1df0000"; + adma0_mattr = "/amba_root@0/amba_lpd@0/adma0mattr"; + adma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd00000"; + adma1_mattr = "/amba_root@0/amba_lpd@0/adma1mattr"; + adma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd10000"; + adma2_mattr = "/amba_root@0/amba_lpd@0/adma2mattr"; + adma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd20000"; + adma3_mattr = "/amba_root@0/amba_lpd@0/adma3mattr"; + adma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd30000"; + adma4_mattr = "/amba_root@0/amba_lpd@0/adma4mattr"; + adma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd40000"; + adma5_mattr = "/amba_root@0/amba_lpd@0/adma5mattr"; + adma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd50000"; + adma6_mattr = "/amba_root@0/amba_lpd@0/adma6mattr"; + adma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd60000"; + adma7_mattr = "/amba_root@0/amba_lpd@0/adma7mattr"; + adma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd70000"; + ps_i2c0 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1940000"; + i2c0_bridge = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1940000/ +i2c0_bridge@0"; + ps_i2c1 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000"; + eeprom0 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000/eeprom@54"; + eeprom1 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000/eeprom@51"; + i2c1_bridge = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000/ +i2c1_bridge@0"; + ocm_ctrl0 = "/amba_root@0/amba_lpd@0/ocm_ctrl@OCM"; + lpd_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_slcr_secure@0xeb510000"; + lpd_iou_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_iou_slcr_secure@0xf19c0000"; + lpd_gpio = "/amba_root@0/amba_lpd@0/lpd_gpio@0xf19d0000"; + intlpd = "/amba_root@0/amba_lpd@0/intlpd@0xea600000"; + rpu_ctrl = "/amba_root@0/amba_lpd@0/rpu_ctrl@0"; + rpu_ctrl_a = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb580000"; + rpu_ctrl_a0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a0@0xeb588000"; + rpu_ctrl_a1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a1@0xeb58c000"; + rpu_ctrl_b = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb590000"; + rpu_ctrl_b0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b0@0xeb598000"; + rpu_ctrl_b1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b1@0xeb59c000"; + rpu_pcil = "/amba_root@0/amba_lpd@0/rpu_pcil@0xEB420000"; + dwc3_1 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI1"; + amba_fpd = "/amba_root@0/amba_fpd@0"; + wwdt0 = "/amba_root@0/amba_fpd@0/watchdog@0xecc10000"; + intfpd = "/amba_root@0/amba_fpd@0/intfpd@0xec400000"; + apu_cluster0 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER0"; + apu_cluster1 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER1"; + apu_cluster2 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER2"; + apu_cluster3 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER3"; + smmu = "/amba_root@0/amba_fpd@0/smmuv3@MM_FPD_SMMU"; + pcie = "/amba_root@0/amba_fpd@0/dummy_pcie@0x6_0000_0000"; + pki_rng = "/amba_root@0/amba_fpd@0/pki_rng@0x20400040000ULL"; + apu_pcil = "/amba_root@0/amba_fpd@0/apu_pcil@0xecb10000"; + cpm5_crx = "/amba_root@0/amba_fpd@0/cpm5_crx@0xdc0000"; + amba_pmc_internal = "/amba_root@0/amba_pmc_internal@0"; + xmpu_pmc = "/amba_root@0/amba_pmc_internal@0/xmpu_pmc@0"; + xppu_pmc_npi = "/amba_root@0/amba_pmc_internal@0/xppu_pmc_npi@0xf1300000"; + xppu_pmc = "/amba_root@0/amba_pmc_internal@0/xppu_pmc@0xf1310000"; + amba_pmc = "/amba_root@0/amba_pmc@0"; + xmpu_pmc_cfu = "/amba_root@0/amba_pmc@0/xmpu_pmc_cfu@0xf1340000"; + pmx_err_mng = "/amba_root@0/amba_pmc@0/pmx_err_mng@0xf1110000"; + amba_pmc_iou = "/amba_root@0/amba_pmc_iou@0"; + pmc_iou_slcr = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr@0xf1060000"; + pmc_iou_slcr_secure = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr_secure@0xf1070000"; + pmc_qspi_dma_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi_dma@QSPI_DMA"; + pmc_qspi_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000"; + qspi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_lcs_lb@0"; + qspi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_ucs_ub@0"; + ospi_dma_dst = "/amba_root@0/amba_pmc_iou@0/ospi_dst_dma@0"; + ospi_dma_src = "/amba_root@0/amba_pmc_iou@0/ospi_src_dma@0"; + ospi = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000"; + gpio_mr_mux = "/amba_root@0/amba_pmc_iou@0/gpio_mr_mux@0xc0000000"; + pmc_gpio = "/amba_root@0/amba_pmc_iou@0/pmc_gpio@0xf1020000"; + sdhci0 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1040000"; + sdhci1 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1050000"; + pmc_tap = "/amba_root@0/amba_pmc_iou@0/pmc_tap@0xf11a0000"; + pmx_wwdt = "/amba_root@0/amba_pmc_iou@0/wwdt@0xf03f0000"; + amba_pmc_sec = "/amba_root@0/amba_pmc_sec@0"; + pmc_dma0_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_src@0"; + pmc_dma0_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_dst@0"; + pmc_dma1_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_src@0"; + pmc_dma1_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_dst@0"; + pmc_stream_switch = "/amba_root@0/amba_pmc_sec@0/pmc_stream_switch@0"; + pmc_sha3 = "/amba_root@0/amba_pmc_sec@0/pmc_sha@0xf1210000"; + pmc_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000"; + xlnx_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000/xlnx_aes@0"; + pmc_rsa = "/amba_root@0/amba_pmc_sec@0/pmc_rsa@0xf1200000"; + xlnx_pmc_efuse_cache = "/amba_root@0/amba_pmc_sec@0/ +xlnx_pmc_efuse_cache@0xf1250000"; + pmc_puf_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_puf_ctrl@0"; + pmc_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000"; + xlnx_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000/xlnx_efuse@0"; + pmc_bbram_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_bbram@0xf11f0000"; + pmc_sbi = "/amba_root@0/amba_pmc_sec@0/pmc_sbi@0xf1220000"; + pmc_sha3_1 = "/amba_root@0/amba_pmc_sec@0/pmc_sha1@0xF1800000"; + amba_pmc_ppu = "/amba_root@0/amba_pmc_ppu@0"; + pmc_gic_proxy = "/amba_root@0/amba_pmc_ppu@0/pmc_gic_proxy@0"; + amba_pmc_sys = "/amba_root@0/amba_pmc_sys@0"; + pmc_clk_rst = "/amba_root@0/amba_pmc_sys@0/pmc_clk_rst@0xf1260000"; + pmc_int = "/amba_root@0/amba_pmc_sys@0/pmc_int@0xf1400000"; + pmc_global = "/amba_root@0/amba_pmc_sys@0/pmc_global@0xf1110000"; + pmc_err_mng = "/amba_root@0/amba_pmc_sys@0/pmc_err_mng@0xF1130000"; + pmc_stream_zero = "/amba_root@0/amba_pmc_sys@0/pmc_stream_zero@"; + pmc_sysmon = "/amba_root@0/amba_pmc_sys@0/pmc_sysmon@0xf1270000"; + pmc_ams_sat0 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@0"; + pmc_ams_sat1 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@1"; + pmc_global_tamper = "/amba_root@0/amba_pmc_sys@0/versal_pmc_tamper@"; + lpd_sysmon_sat = "/amba_root@0/amba_pmc_sys@0/lpd_ams_sat@0"; + fpd_sysmon_sat0 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@0"; + fpd_sysmon_sat1 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@1"; + fpd_sysmon_sat2 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@2"; + fpd_sysmon_sat3 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@3"; + amba_pmc_pl = "/amba_root@0/amba_pmc_pl@0"; + noc_npi_nir = "/amba_root@0/amba_pmc_pl@0/noc_npi_nir@0xf6000000"; + npi_ddrmc_ub0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub0@0xf67c0000"; + npi_ddrmc_main0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main0@0xf6790000"; + npi_ddrmc_noc0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc0@0xf67a0000"; + npi_ddrmc_ub1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub1@0xf68b0000"; + npi_ddrmc_main1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main1@0xf6880000"; + npi_ddrmc_noc1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc1@0xf6890000"; + npi_ddrmc_ub2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub2@0xf6dc0000"; + npi_ddrmc_main2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main2@0xf6d90000"; + npi_ddrmc_noc2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc2@0xf6da0000"; + npi_ddrmc_ub3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub3@0xf6eb0000"; + npi_ddrmc_main3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main3@0xf6e80000"; + npi_ddrmc_noc3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc3@0xf6e90000"; + npi_ddrmc_ub4 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub4@0xf6f70000"; + npi_ddrmc_main4 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main4@0xf6f40000"; + npi_ddrmc_noc4 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc4@0xf6f50000"; + npi_ddrmc_ub5 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub5@0xf7060000"; + npi_ddrmc_main5 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main5@0xf7030000"; + npi_ddrmc_noc5 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc5@0xf7040000"; + npi_ddrmc_ub6 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub6@0xf7320000"; + npi_ddrmc_main6 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main6@0xf72f0000"; + npi_ddrmc_noc6 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc6@0xf7300000"; + npi_ddrmc_ub7 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub7@0xf7400000"; + npi_ddrmc_main7 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main7@0xf73d0000"; + npi_ddrmc_noc7 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc7@0xf73e0000"; + npi_ddrmc_xmpu0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_xmpu0@0xf67a0000"; + noc_npi_devs = "/amba_root@0/amba_pmc_pl@0/noc_npi_devs@0"; + cfu_fdro = "/amba_root@0/amba_pmc_pl@0/cfu_fdro@0xf12c2000"; + cfu_sfr = "/amba_root@0/amba_pmc_pl@0/cfu_sfr@0xf12c1000"; + cframe0_reg = "/amba_root@0/amba_pmc_pl@0/cframe0_reg@0xf12d0000"; + cframe1_reg = "/amba_root@0/amba_pmc_pl@0/cframe1_reg@0xf12d2000"; + cframe2_reg = "/amba_root@0/amba_pmc_pl@0/cframe2_reg@0xf12d4000"; + cframe3_reg = "/amba_root@0/amba_pmc_pl@0/cframe3_reg@0xf12d6000"; + cframe4_reg = "/amba_root@0/amba_pmc_pl@0/cframe4_reg@0xf12d8000"; + cframe5_reg = "/amba_root@0/amba_pmc_pl@0/cframe5_reg@0xf12da000"; + cframe6_reg = "/amba_root@0/amba_pmc_pl@0/cframe6_reg@0xf12dc000"; + cframe7_reg = "/amba_root@0/amba_pmc_pl@0/cframe7_reg@0xf12de000"; + cframe8_reg = "/amba_root@0/amba_pmc_pl@0/cframe8_reg@0xf12e0000"; + cframe9_reg = "/amba_root@0/amba_pmc_pl@0/cframe9_reg@0xf12e2000"; + cframe10_reg = "/amba_root@0/amba_pmc_pl@0/cframe10_reg@0xf12e4000"; + cframe11_reg = "/amba_root@0/amba_pmc_pl@0/cframe11_reg@0xf12e6000"; + cframe12_reg = "/amba_root@0/amba_pmc_pl@0/cframe12_reg@0xf12e8000"; + cframe13_reg = "/amba_root@0/amba_pmc_pl@0/cframe13_reg@0xf12ea000"; + cframe14_reg = "/amba_root@0/amba_pmc_pl@0/cframe14_reg@0xf12ec000"; + cframe_bcast_reg = "/amba_root@0/amba_pmc_pl@0/cframe_bcast_reg@0xf12ee000"; + hnicx_npi_0 = "/amba_root@0/amba_pmc_pl@0/hnicx_npi_0@0xf6af0000"; + hnicx_pllpor_0 = "/amba_root@0/amba_pmc_pl@0/hnicx_pllpor_0@0xf6b30000"; + dummy_cfu_mem = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000"; + cfu = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000/cfu@0x0"; + amba_pmc_bat = "/amba_root@0/amba_pmc_bat@0"; + rtc = "/amba_root@0/amba_pmc_bat@0/rtc@0xf12a0000"; + amba_psm = "/amba_root@0/amba_psm@0"; + psm_ram_instr = "/amba_root@0/amba_psm@0/psm_ram_instr@0xebc00000"; + psm_ram_data = "/amba_root@0/amba_psm@0/psm_ram_data@0xebc20000"; + psm_gic_proxy = "/amba_root@0/amba_psm@0/psm_gic_proxy@0"; + psm_global = "/amba_root@0/amba_psm@0/psm_global_reg@0xebc90000"; + psm_err_mng = "/amba_root@0/amba_psm@0/psm_err_mng@0xebc90000"; + amba_xram = "/amba_root@0/amba_xram@0"; + crf = "/amba_root@0/crf@0xec200000"; + lmb_pmc_ppu0 = "/lmb_pmc_ppu0@0"; + pmc_rom = "/lmb_pmc_ppu0@0/pmc_rom@0xf0000000"; + pmc_ppu0_ram = "/lmb_pmc_ppu0@0/ppu0_ram@0xf0060000"; + pmc_ppu0_io_module = "/lmb_pmc_ppu0@0/io-module@00"; + pmc_ppu0_io_intc = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_intc@0C"; + pmc_ppu0_io_gpi1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@20"; + pmc_ppu0_io_gpi2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@24"; + pmc_ppu0_io_gpi3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@28"; + pmc_ppu0_io_gpi4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@2c"; + pmc_ppu0_io_gpo1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@10"; + pmc_ppu0_io_gpo2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@14"; + pmc_ppu0_io_gpo3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@18"; + pmc_ppu0_io_gpo4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@1c"; + pmc_ppu0_io_pit1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@40"; + pmc_ppu0_io_pit2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@50"; + pmc_ppu0_io_pit3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@60"; + pmc_ppu0_io_pit4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@70"; + lmb_pmc_ppu1 = "/lmb_pmc_ppu1@0"; + pmc_ppu1_io_module = "/lmb_pmc_ppu1@0/io-module@00"; + pmc_ppu1_io_intc = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_intc@0C"; + pmc_ppu1_io_gpi1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@20"; + pmc_ppu1_io_gpi2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@24"; + pmc_ppu1_io_gpi3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@28"; + pmc_ppu1_io_gpi4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@2c"; + pmc_ppu1_io_gpo1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@10"; + pmc_ppu1_io_gpo2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@14"; + pmc_ppu1_io_gpo3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@18"; + pmc_ppu1_io_gpo4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@1c"; + pmc_ppu1_io_pit1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@40"; + pmc_ppu1_io_pit2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@50"; + pmc_ppu1_io_pit3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@60"; + pmc_ppu1_io_pit4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@70"; + lmb_psm = "/lmb_psm@0"; + psm_0_io_module = "/lmb_psm@0/io-module@00"; + psm0_io_intc = "/lmb_psm@0/io-module@00/psm0_intc@0C"; + psm0_io_gpo1 = "/lmb_psm@0/io-module@00/psm0_gpo@10"; + psm0_io_pit1 = "/lmb_psm@0/io-module@00/psm0_pit@40"; + psm0_io_pit2 = "/lmb_psm@0/io-module@00/psm0_pit@50"; + psm0_io_pit3 = "/lmb_psm@0/io-module@00/psm0_pit@60"; + psm0_io_pit4 = "/lmb_psm@0/io-module@00/psm0_pit@70"; + psm_local = "/lmb_psm@0/psm_local_reg@0xebc88000"; + lmb_ddrmc0 = "/lmb_ddrmc@0"; + ddrmc0_ram_data = "/lmb_ddrmc@0/ddrmc0_ram_data@0x1c000"; + ddrmc0_ram_instr = "/lmb_ddrmc@0/ddrmc0_ram_instr@0x20000"; + ddrmc0_ram_exchange = "/lmb_ddrmc@0/ddrmc0_ram_exchange@0x08000"; + ddrmc_0_io_module = "/lmb_ddrmc@0/io-module@00"; + ddrmc0_io_intc = "/lmb_ddrmc@0/io-module@00/ddrmc0_intc@0C"; + ddrmc0_io_gpo1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_gpo@10"; + ddrmc0_io_pit1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@40"; + ddrmc0_io_pit2 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@50"; + ddrmc0_io_pit3 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@60"; + ddrmc0_io_pit4 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@70"; + ddrmc_uart0 = "/lmb_ddrmc@0/ddrmc_uart0@0"; + lmb_ddrmc1 = "/lmb_ddrmc@1"; + ddrmc1_ram_data = "/lmb_ddrmc@1/ddrmc1_ram_data@0x1c000"; + ddrmc1_ram_instr = "/lmb_ddrmc@1/ddrmc1_ram_instr@0x20000"; + ddrmc1_ram_exchange = "/lmb_ddrmc@1/ddrmc1_ram_exchange@0x08000"; + amba_rpu = "/amba_rpu@0"; + amba_r5_0 = "/amba_r5@0"; + amba_r5_1 = "/amba_r5@1"; + dummy1 = "/dummy1@0"; + smmu_tbu0 = "/tbu0_slave@0"; + smmu_tbu1 = "/tbu1_slave@0"; + smmu_tbu2 = "/tbu2_slave@0"; + smmu_tbu3 = "/tbu3_slave@0"; + smmu_tbu4 = "/tbu4_slave@0"; + smmu_tbu5 = "/tbu5_slave@0"; + smmu_tbu6 = "/tbu6_slave@0"; + ddr_mem = "/memory@00000000"; + ddr_2_mem = "/memory@8_0000_0000"; + ddr_3_mem = "/memory@0x50000000000ULL"; + ocm_mem = "/ocm_mem@0xbbf00000"; + ocm_mem_bank_0 = "/ocm_mem_bank_0@"; + ocm_mem_bank_1 = "/ocm_mem_bank_1@"; + ocm_mem_bank_2 = "/ocm_mem_bank_2@"; + ocm_mem_bank_3 = "/ocm_mem_bank_3@"; + xram_mem = "/xram_mem@0xea800000"; + xram_mem_bank_0 = "/xram_mem_bank_0@0x0"; + xram_mem_bank_1 = "/xram_mem_bank_1@0x200000"; + xram_mem_bank_2 = "/xram_mem_bank_2@0x400000"; + xram_mem_bank_3 = "/xram_mem_bank_3@0x600000"; + ipi_msgbuf = "/ipi_msgbuf@0"; + pmc_ram = "/pmc_ram@0xf2000000"; + pmc_ram_bank_0 = "/pmc_ram_bank_0@0x0"; + pmc_ppu1_insn_ram = "/pmc_ppu1_ram@0xf0200000"; + pmc_ppu1_data_ram = "/pmc_ppu1_ram@0xf0280000"; + lqspi_mr = "/lqspi_mr@0"; + lospi_mr = "/lospi_mr@0"; + cpu0 = "/cpus/apu_cpu@0"; + cpu1 = "/cpus/apu_cpu@1"; + cpu2 = "/cpus/apu_cpu@2"; + cpu3 = "/cpus/apu_cpu@3"; + cpu4 = "/cpus/apu_cpu@4"; + cpu5 = "/cpus/apu_cpu@5"; + cpu6 = "/cpus/apu_cpu@6"; + cpu7 = "/cpus/apu_cpu@7"; + cpu8 = "/cpus/apu_cpu@8"; + cpu9 = "/cpus/apu_cpu@9"; + cpu10 = "/cpus/apu_cpu@10"; + cpu11 = "/cpus/apu_cpu@11"; + cpu12 = "/cpus/apu_cpu@12"; + cpu13 = "/cpus/apu_cpu@13"; + cpu14 = "/cpus/apu_cpu@14"; + cpu15 = "/cpus/apu_cpu@15"; + rpu_a = "/cpus/rpu_a@0"; + rpu_cpu0 = "/cpus/rpu_a@0/rpu_cpu_a@0"; + rpu_cpu1 = "/cpus/rpu_a@0/rpu_cpu_a@1"; + rpu_b = "/cpus/rpu_b@0"; + rpu_cpu2 = "/cpus/rpu_b@0/rpu_cpu_b@0"; + rpu_cpu3 = "/cpus/rpu_b@0/rpu_cpu_b@1"; + amba_apu = "/amba_apu@0"; + timer = "/amba_apu@0/timer"; + amba_apu_gic = "/amba_apu_gic@0"; + gic = "/amba_apu_gic@0/interrupt-controller@0xe2000000"; + amba_alias = "/amba_alias@0"; + qemu_sysmem = "/qemu_sysmem@0"; + psm0 = "/dummy_ppu0@0"; + pmc_ppu0 = "/dummy_ppu0@0"; + pmc_ppu1 = "/dummy_ppu1@0"; + ddrmc_ub0 = "/dummy_ddrmc0@0"; + ddrmc_ub1 = "/dummy_ddrmc1@0"; + ddr = "/ddr@0x00000000"; + ddr_2 = "/ddr_2@0x800000000ULL"; + mdio0 = "/mdio"; + phy0 = "/mdio/phy@1"; + cpunone = "/cpu_dummy"; + smmu_tbu7 = "/tbu7_slave@0"; + smmu_tbu8 = "/tbu8_slave@0"; + smmu_tbu9 = "/tbu9_slave@0"; + smmu_tbu10 = "/tbu10_slave@0"; + smmu_tbu11 = "/tbu11_slave@0"; + smmu_tbu12 = "/tbu12_slave@0"; + mr_rpu_gic_a = "/mr_rpu_gic_a@0"; + rpu_gic_a = "/mr_rpu_gic_a@0/rpu_gic_a@0x0"; + mr_rpu_gic_b = "/mr_rpu_gic_b@0"; + rpu_gic_b = "/mr_rpu_gic_b@0/rpu_gic_b@0x0"; + tcm_core0 = "/tcm_core@0"; + atcm_rpu_core0 = "/tcm_core@0/atcm_rpu_core0@0x00000"; + btcm_rpu_core0 = "/tcm_core@0/btcm_rpu_core0@0x00000"; + ctcm_rpu_core0 = "/tcm_core@0/ctcm_rpu_core0@0x00000"; + tcm_core1 = "/tcm_core@1"; + atcm_rpu_core1 = "/tcm_core@1/atcm_rpu_core1@0x00000"; + btcm_rpu_core1 = "/tcm_core@1/btcm_rpu_core1@0x00000"; + ctcm_rpu_core1 = "/tcm_core@1/ctcm_rpu_core1@0x00000"; + tcm_core2 = "/tcm_core@2"; + atcm_rpu_core2 = "/tcm_core@2/atcm_rpu_core2@0x00000"; + btcm_rpu_core2 = "/tcm_core@2/btcm_rpu_core2@0x00000"; + ctcm_rpu_core2 = "/tcm_core@2/ctcm_rpu_core2@0x00000"; + tcm_core3 = "/tcm_core@3"; + atcm_rpu_core3 = "/tcm_core@3/atcm_rpu_core3@0x00000"; + btcm_rpu_core3 = "/tcm_core@3/btcm_rpu_core3@0x00000"; + ctcm_rpu_core3 = "/tcm_core@3/ctcm_rpu_core3@0x00000"; + tcm_cluster_a = "/tcm_cluster_a@0"; + tcm_cluster_b = "/tcm_cluster_b@0"; + amba_r5_2 = "/amba_r5@2"; + amba_r5_3 = "/amba_r5@3"; + rpu2_s_memattr = "/rpu2_s_ma"; + rpu3_s_memattr = "/rpu3_s_ma"; + usb1_memattr = "/usb1_ma"; + }; +}; diff --git a/boards/amd/versalnet_apu/versalnet_apu.dts b/boards/amd/versalnet_apu/versalnet_apu.dts new file mode 100644 index 0000000000000..5ee2b9710f60c --- /dev/null +++ b/boards/amd/versalnet_apu/versalnet_apu.dts @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = <100000000>; +}; + +&soc { + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0x0 0x0 0x0 DT_SIZE_M(2048)>; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; diff --git a/boards/amd/versalnet_apu/versalnet_apu.yaml b/boards/amd/versalnet_apu/versalnet_apu.yaml new file mode 100644 index 0000000000000..2a3825fdd5721 --- /dev/null +++ b/boards/amd/versalnet_apu/versalnet_apu.yaml @@ -0,0 +1,11 @@ +identifier: versalnet_apu +name: AMD Development board for Versal NET APU +arch: arm +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth + - fpu +vendor: amd diff --git a/boards/amd/versalnet_apu/versalnet_apu_defconfig b/boards/amd/versalnet_apu/versalnet_apu_defconfig new file mode 100644 index 0000000000000..7cfeda9524115 --- /dev/null +++ b/boards/amd/versalnet_apu/versalnet_apu_defconfig @@ -0,0 +1,27 @@ +# The Zephyr build from this defconfig is expected to boot from +# Xilinx Arm Trusted Firmware (ATF). +# Boot Flow is: Boot PDI -> TF-A -> Zephyr + +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y + +# This should be commented in order to test at EL1 S (EL1 Secure) +CONFIG_ARMV8_A_NS=y + +# FPU support is disabled due to QEMU limitations. When CONFIG_FPU_SHARING +# is enabled, it uses the swpal instruction which QEMU does not emulate. +# If testing is targeted on real hardware and FPU operations are needed, +# comment the lines below. +CONFIG_FPU=n +CONFIG_FPU_SHARING=n diff --git a/boards/arduino/due/arduino_r3_connector.dtsi b/boards/arduino/due/arduino_r3_connector.dtsi index 16fcfa2674fce..ad492c17030a2 100644 --- a/boards/arduino/due/arduino_r3_connector.dtsi +++ b/boards/arduino/due/arduino_r3_connector.dtsi @@ -4,33 +4,35 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = < 0 0 &pioa 16 0>, /* A0 */ - < 1 0 &pioa 24 0>, /* A1 */ - < 2 0 &pioa 23 0>, /* A2 */ - < 3 0 &pioa 22 0>, /* A3 */ - < 4 0 &pioa 6 0>, /* A4 */ - < 5 0 &pioa 4 0>, /* A5 */ - < 6 0 &pioa 8 0>, /* D0 */ - < 7 0 &pioa 9 0>, /* D1 */ - < 8 0 &piob 25 0>, /* D2 */ - < 9 0 &pioc 28 0>, /* D3 */ - <10 0 &pioa 29 0>, /* D4 */ - <11 0 &pioc 25 0>, /* D5 */ - <12 0 &pioc 24 0>, /* D6 */ - <13 0 &pioc 23 0>, /* D7 */ - <14 0 &pioc 22 0>, /* D8 */ - <15 0 &pioc 21 0>, /* D9 */ - <16 0 &pioa 28 0>, /* D10 */ - <17 0 &piod 7 0>, /* D11 */ - <18 0 &piod 8 0>, /* D12 */ - <19 0 &piob 27 0>, /* D13 */ - <20 0 &pioa 17 0>, /* D20 */ - <21 0 &pioa 18 0>; /* D21 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/arduino/giga_r1/arduino_r3_connector.dtsi b/boards/arduino/giga_r1/arduino_r3_connector.dtsi index 7415a4537aa81..a7787b1ba2e06 100644 --- a/boards/arduino/giga_r1/arduino_r3_connector.dtsi +++ b/boards/arduino/giga_r1/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = < 0 0 &gpioc 4 0>, /* A0 */ - < 1 0 &gpioc 5 0>, /* A1 */ - < 2 0 &gpiob 0 0>, /* A2 */ - < 3 0 &gpiob 1 0>, /* A3 */ - < 4 0 &gpioc 3 0>, /* A4 */ - < 5 0 &gpioc 2 0>, /* A5 */ - < 6 0 &gpiob 7 0>, /* D0 */ - < 7 0 &gpioa 9 0>, /* D1 */ - < 8 0 &gpioa 3 0>, /* D2 */ - < 9 0 &gpioa 2 0>, /* D3 */ - <10 0 &gpioj 8 0>, /* D4 */ - <11 0 &gpioa 7 0>, /* D5 */ - <12 0 &gpiod 13 0>, /* D6 */ - <13 0 &gpiob 4 0>, /* D7 */ - <14 0 &gpiob 8 0>, /* D8 */ - <15 0 &gpiob 9 0>, /* D9 */ - <16 0 &gpiok 1 0>, /* D10 */ - <17 0 &gpioj 10 0>, /* D11 */ - <18 0 &gpioj 11 0>, /* D12 */ - <19 0 &gpioh 6 0>, /* D13 */ - <20 0 &gpioh 12 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml index 7dc36b141900d..bd7d06eb249f1 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml @@ -14,5 +14,5 @@ supported: - spi - qspi - memc - - usb_device + - usbd vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml index 456ae5871e3b0..a5e81cd574ea4 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml @@ -14,6 +14,5 @@ supported: - spi - qspi - memc - - usb_cdc - - usb_device + - usbd vendor: arduino diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst deleted file mode 100644 index 080d316e6b783..0000000000000 --- a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst +++ /dev/null @@ -1,105 +0,0 @@ -.. _fvp_baser_aemv8r_aarch32: - -Arm FVP BaseR AEMv8-R AArch32 -############################# - -Overview -******** - -This board configuration uses Armv8-R AEM FVP [1]_ to emulate a generic -Armv8-R [2]_ 32-bit hardware platform. - -Fixed Virtual Platforms (FVP) are complete simulations of an Arm system, -including processor, memory and peripherals. These are set out in a -"programmer's view", which gives you a comprehensive model on which to build -and test your software. - -The Armv8-R AEM FVP is a free of charge Armv8-R Fixed Virtual Platform. It -supports the latest Armv8-R feature set. Please refer to FVP documentation -page [3]_ for more details about FVP. - -To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM -FVP" from Arm developer [1]_ (This might require the user to register) and -install it on your host PC. - -Hardware -******** - -Supported Features -================== - -The following hardware features are supported: - -+-----------------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+=======================+============+======================+ -| GICv3 | on-chip | interrupt controller | -+-----------------------+------------+----------------------+ -| PL011 UART | on-chip | serial port | -+-----------------------+------------+----------------------+ -| Arm GENERIC TIMER | on-chip | system clock | -+-----------------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -When FVP is launched with ``-a, --application FILE`` option, the kernel will be -loaded into DRAM region ``[0x0-0x7FFFFFFF]``. For more information, please refer -to the official Armv8-R AEM FVP memory map document [4]_. - -Devices -======= - -System Clock ------------- - -This board configuration uses a system clock frequency of 100 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -UART0. - -Programming and Debugging -************************* - -Environment -=========== - -First, set the ``ARMFVP_BIN_PATH`` environment variable before building. -Optionally, set ``ARMFVP_EXTRA_FLAGS`` to pass additional arguments to the FVP. - -.. code-block:: bash - - export ARMFVP_BIN_PATH=/path/to/fvp/directory - -Programming -=========== - -Use this configuration to build basic Zephyr applications and kernel tests in the -Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: fvp_baser_aemv8r/fvp_aemv8r_aarch32 - :goals: build - -This will build an image with the synchronization sample app. -Then you can run it with ``west build -t run``. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. - -References -********** - -.. target-notes:: - -.. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models -.. [2] Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch32 architecture profile - https://developer.arm.com/documentation/ddi0568/latest -.. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs -.. [4] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst deleted file mode 100644 index 0f9a28d0a8107..0000000000000 --- a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst +++ /dev/null @@ -1,116 +0,0 @@ -.. _fvp_baser_aemv8r: - -Arm FVP BaseR AEMv8-R -##################### - -.. toctree:: - :maxdepth: 1 - - debug-with-arm-ds.rst - -Overview -******** - -This board configuration uses Armv8-R AEM FVP [1]_ to emulate a generic -Armv8-R [2]_ 64-bit hardware platform. - -Fixed Virtual Platforms (FVP) are complete simulations of an Arm system, -including processor, memory and peripherals. These are set out in a -"programmer's view", which gives you a comprehensive model on which to build -and test your software. - -The Armv8-R AEM FVP is a free of charge Armv8-R Fixed Virtual Platform. It -supports the latest Armv8-R feature set. Please refer to FVP documentation -page [3]_ for more details about FVP. - -To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM -FVP" from Arm developer [1]_ (This might require the user to register) and -install it on your host PC. - -The current minimum required version of "Armv8-R AEM FVP" is 11.16.16. - -Hardware -******** - -Supported Features -================== - -The following hardware features are supported: - -+-----------------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+=======================+============+======================+ -| GICv3 | on-chip | interrupt controller | -+-----------------------+------------+----------------------+ -| PL011 UART | on-chip | serial port | -+-----------------------+------------+----------------------+ -| Arm GENERIC TIMER | on-chip | system clock | -+-----------------------+------------+----------------------+ -| SMSC_91C111 | on-chip | ethernet device | -+-----------------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -When FVP is launched with ``-a, --application FILE`` option, the kernel will be -loaded into DRAM region ``[0x0-0x7FFFFFFF]``. For more information, please refer -to the official Armv8-R AEM FVP memory map document [4]_. - -Devices -======= - -System Clock ------------- - -This board configuration uses a system clock frequency of 100 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -UART0. - -Programming and Debugging -************************* - -Environment -=========== - -First, set the ``ARMFVP_BIN_PATH`` environment variable before building. -Optionally, set ``ARMFVP_EXTRA_FLAGS`` to pass additional arguments to the FVP. - -.. code-block:: bash - - export ARMFVP_BIN_PATH=/path/to/fvp/directory - -Programming -=========== - -Use this configuration to build basic Zephyr applications and kernel tests in the -Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: fvp_baser_aemv8r/fvp_aemv8r_aarch64 - :goals: build - -This will build an image with the synchronization sample app. -Then you can run it with ``west build -t run``. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. -See :ref:`debug_with_arm_ds` for how to debug with Arm Development Studio [5]_. - -References -********** - -.. target-notes:: - -.. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models -.. [2] Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile - https://developer.arm.com/documentation/ddi0600/latest/ -.. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs -.. [4] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map -.. [5] https://developer.arm.com/tools-and-software/embedded/arm-development-studio diff --git a/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst b/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst deleted file mode 100644 index 79b48aca53568..0000000000000 --- a/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst +++ /dev/null @@ -1,147 +0,0 @@ -.. _debug_with_arm_ds: - -Debug with Arm DS -################# - -Install Arm DS -************** - -Please refer to the official Arm Development Studio Page [1]_ for details. Here -``Version: 2020.b Build: 2020110909`` is used in the following example. - -.. image:: images/version-info.jpg - :align: center - :alt: Arm DS Version - -Download Arm FVP BaseR AEMv8-R -****************************** - -Please refer to official FVP page [2]_ for download instructions. Here ``$FVP_D`` -is used to indicate which directory is FVP located. - -Use DS perspective -****************** - -From menu choose ``Window -> Perspective -> Open Perspective -> Other...``: - -.. image:: images/perspective-choose-other.jpg - :align: center - :alt: Arm DS Perspective choose Other... - -In the opened window, choose ``Development Studio (default)``: - -.. image:: images/perspective-choose-ds.jpg - :align: center - :alt: Arm DS Perspective choose DS - -Create a new configuration database -*********************************** - -Create a new configuration database by selecting ``File -> New -> Other... -> Configuration Database``: - -.. image:: images/create-new-configuration-database.jpg - :align: center - :alt: Arm DS create new configuration database - -Choose a name for the database. Here ``Zephyr`` is used: - -.. image:: images/create-new-configuration-database_database-name.jpg - :align: center - :alt: Arm DS create new configuration database: choose database name - -Click ``Finish`` and the new configuration database can be seen in ``Project Explorer``: - -.. image:: images/create-new-configuration-database_shown-in-project-explorer.jpg - :align: center - :alt: Arm DS create new configuration database: shown in project explorer - -Create a new model configuration -******************************** - -Right click ``Zephyr`` in ``Project Explorer``, choose ``New -> Model Configuration``: - -.. image:: images/create-new-model-configuration.jpg - :align: center - :alt: Arm DS create new model configuration - -In the opened window: - -1. Choose ``Iris`` for ``Model Interface``, then ``Next >``. -2. Choose ``Launch and connect to specific model``, then ``Next >``. -3. Set ``Model Path`` to ``$FVP_D/FVP_BaseR_AEMv8R``, then ``Finish``. - -.. image:: images/create-new-model-configuration_model-path.jpg - :align: center - :alt: Arm DS create new model configuration: set model path - -Then in ``FVP_BaseR_AEMv8R`` tab, change ``ARMAEMv8-R_`` to ``V8R64-Generic``, -click ``Save`` and then click ``Import``: - -.. image:: images/create-new-model-configuration_model-use-V8R64-Generic.jpg - :align: center - :alt: Arm DS create new model configuration: import - -Create a new launch configuration -********************************* - -From ``Project Explorer``, right click ``FVP_BaseR_AEMv8R`` and select ``Debug as -> Debug configurations...``: - -.. image:: images/create-new-launch-configuration_context-menu.jpg - :align: center - :alt: Arm DS create new launch configuration: context menu - -Select ``Generic Arm C/C++ Application`` and click ``New launch configuration`` button. -A new configuration named ``New_configuration`` will be created. - -1. In ``Connection`` tab: - - - In ``Select target`` box, select ``Imported -> FVP_BaseR_AEMv8R -> Bare Metal Debug -> ARMAEMv8-R_MP_0`` - - In ``Connections`` box, set ``Model parameters`` to:: - - -C bp.dram.enable_atomic_ops=1 -C bp.sram.enable_atomic_ops=1 -C bp.refcounter.non_arch_start_at_default=1 -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 -C gic_distributor.has-two-security-states=0 -C bp.vis.disable_visualisation=1 -C cluster0.has_aarch64=1 -a /home/fengqi/zephyrproject/build/zephyr/zephyr.elf - - These parameters are passed to ``FVP_BaseR_AEMv8R`` when launches. Run ``FVP_BaseR_AEMv8R --help`` - to see all command line options. Run ``FVP_BaseR_AEMv8R --list-params`` to see all supported parameters. - The file ``zephyr.elf`` specified by ``-a`` is the binary built from Zephyr. - -.. image:: images/create-new-launch-configuration_connection.jpg - :align: center - :alt: Arm DS create new launch configuration: connection - -2. In ``Files`` tab: - - In ``Files`` box, set ``Load symbols from file`` to full path of ``zephyr.elf`` that you built. - -.. image:: images/create-new-launch-configuration_files.jpg - :align: center - :alt: Arm DS create new launch configuration: files - -3. In ``Debugger`` tab: - - - In ``Run control`` box, check ``Execute debugger commands`` and insert:: - - add-symbol-file "/home/fengqi/zephyrproject/build/zephyr/zephyr.elf" EL1S:0 - - Replace ``/home/fengqi/zephyrproject/build/zephyr/zephyr.elf`` with your local path. - - - In ``Paths`` box, set ``Source search directory`` to the path to Zephyr source code. - -.. image:: images/create-new-launch-configuration_debugger.jpg - :align: center - :alt: Arm DS create new launch configuration: debugger - -After all these changes are made, click ``Apply``, then click ``Debug``. DS will -launch ``FVP_BaseR_AEMv8R`` and connect to it. You can see a new session is -connected in ``Debug Control`` window. - -.. image:: images/DS-debug-working.jpg - :align: center - :alt: Arm DS working - -References -********** - -.. target-notes:: - -.. [1] https://developer.arm.com/tools-and-software/embedded/arm-development-studio -.. [2] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models diff --git a/boards/arm/fvp_baser_aemv8r/doc/images/perspective-choose-other.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/perspective-choose-other.jpg deleted file mode 100644 index cbaa0a2104953..0000000000000 Binary files a/boards/arm/fvp_baser_aemv8r/doc/images/perspective-choose-other.jpg and /dev/null differ diff --git a/boards/arm/fvp_baser_aemv8r/doc/index.rst b/boards/arm/fvp_baser_aemv8r/doc/index.rst new file mode 100644 index 0000000000000..a61e6031f0ff7 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/doc/index.rst @@ -0,0 +1,273 @@ +.. zephyr:board:: fvp_baser_aemv8r + +Overview +******** + +This board configuration uses Armv8-R AEM FVP [1]_ to emulate a generic +Armv8-R [2]_ hardware platform supporting both 32-bit (AArch32) and 64-bit (AArch64) architectures. + +Fixed Virtual Platforms (FVP) are complete simulations of an Arm system, +including processor, memory and peripherals. These are set out in a +"programmer's view", which gives you a comprehensive model on which to build +and test your software. + +The Armv8-R AEM FVP is a free of charge Armv8-R Fixed Virtual Platform. It +supports the latest Armv8-R feature set. Please refer to FVP documentation +page [3]_ for more details about FVP. + +To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM +FVP" from Arm developer [1]_ (This might require the user to register) and +install it on your host PC. + +The current minimum required version of "Armv8-R AEM FVP" is 11.16.16. + +Hardware +******** + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +When FVP is launched with ``-a, --application FILE`` option, the kernel will be +loaded into DRAM region ``[0x0-0x7FFFFFFF]``. For more information, please refer +to the official Armv8-R AEM FVP memory map document [4]_. + +Devices +======= + +System Clock +------------ + +This board configuration uses a system clock frequency of 100 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +UART0. + +Programming and Debugging +************************* + +Environment +=========== + +First, set the ``ARMFVP_BIN_PATH`` environment variable before building. +Optionally, set ``ARMFVP_EXTRA_FLAGS`` to pass additional arguments to the FVP. + +.. code-block:: bash + + export ARMFVP_BIN_PATH=/path/to/fvp/directory + +Programming +=========== + +Use this configuration to build basic Zephyr applications and kernel tests in the +Arm FVP emulated environment. + +For AArch64 (64-bit) applications, use the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: fvp_baser_aemv8r/fvp_aemv8r_aarch64 + :goals: build + +For AArch32 (32-bit) applications, use: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: fvp_baser_aemv8r/fvp_aemv8r_aarch32 + :goals: build + +This will build an image with the synchronization sample app. +Then you can run it with ``west build -t run``. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. + +You may use the instructions below to debug with Arm Development Studio [5]_. + +Debugging with Arm DS +--------------------- + +Install Arm DS +^^^^^^^^^^^^^^ + +Please refer to the official Arm Development Studio Page [5]_ for details. Here +``Version: 2020.b Build: 2020110909`` is used in the following example. + +.. image:: images/version-info.jpg + :align: center + :alt: Arm DS Version + +Download Arm FVP BaseR AEMv8-R +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Please refer to official FVP page [1]_ for download instructions. Here ``$FVP_D`` +is used to indicate which directory is FVP located. + +Use DS perspective +^^^^^^^^^^^^^^^^^^ + +- From menu choose :menuselection:`Window --> Perspective --> Open Perspective --> Other...`: + +- In the opened window, choose :guilabel:`Development Studio (default)`: + + .. figure:: images/perspective-choose-ds.jpg + :align: center + :alt: Arm DS Perspective choose DS + + Select the Development Studio perspective + +Create a new configuration database +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- Create a new configuration database by selecting + :menuselection:`File --> New --> Other... --> Configuration Database`: + + .. figure:: images/create-new-configuration-database.jpg + :align: center + :alt: Arm DS create new configuration database + + Create new configuration database + +- Choose a name for the database. Here :guilabel:`Zephyr` is used: + + .. figure:: images/create-new-configuration-database_database-name.jpg + :align: center + :alt: Arm DS create new configuration database: choose database name + + Choose a database name + +- Click :guilabel:`Finish` and the new configuration database can be seen in + :guilabel:`Project Explorer`: + + .. figure:: images/create-new-configuration-database_shown-in-project-explorer.jpg + :align: center + :alt: Arm DS create new configuration database: shown in project explorer + + New configuration database can be seen in Project Explorer + +Create a new model configuration +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- Right click :guilabel:`Zephyr` in :guilabel:`Project Explorer`, choose + :menuselection:`New --> Model Configuration`: + + .. figure:: images/create-new-model-configuration.jpg + :align: center + :alt: Arm DS create new model configuration + + Create new model configuration + +- In the opened window: + + 1. Choose :guilabel:`Iris` for :guilabel:`Model Interface`, then :guilabel:`Next >`. + 2. Choose :guilabel:`Launch and connect to specific model`, then :guilabel:`Next >`. + 3. Set :guilabel:`Model Path` to ``$FVP_D/FVP_BaseR_AEMv8R``, then :guilabel:`Finish`. + + .. figure:: images/create-new-model-configuration_model-path.jpg + :align: center + :alt: Arm DS create new model configuration: set model path + + Set model path + +- Then in :guilabel:`FVP_BaseR_AEMv8R` tab, change :guilabel:`ARMAEMv8-R_` to + :guilabel:`V8R64-Generic`, click :guilabel:`Save` and then click :guilabel:`Import`: + + .. figure:: images/create-new-model-configuration_model-use-V8R64-Generic.jpg + :align: center + :alt: Arm DS create new model configuration: import + + Import model configuration + +Create a new launch configuration +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- From :guilabel:`Project Explorer`, right click :guilabel:`FVP_BaseR_AEMv8R` and select + :menuselection:`Debug as --> Debug configurations...`: + + .. figure:: images/create-new-launch-configuration_context-menu.jpg + :align: center + :alt: Arm DS create new launch configuration: context menu + + Create new launch configuration: context menu + +- Select :guilabel:`Generic Arm C/C++ Application` and click :guilabel:`New launch configuration` + button. + + A new configuration named :guilabel:`New_configuration` will be created. + +1. In :guilabel:`Connection` tab: + + - In :guilabel:`Select target` box, select + :guilabel:`Imported -> FVP_BaseR_AEMv8R -> Bare Metal Debug -> ARMAEMv8-R_MP_0` + - In :guilabel:`Connections` box, set :guilabel:`Model parameters` to:: + + -C bp.dram.enable_atomic_ops=1 -C bp.sram.enable_atomic_ops=1 -C bp.refcounter.non_arch_start_at_default=1 -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 -C gic_distributor.has-two-security-states=0 -C bp.vis.disable_visualisation=1 -C cluster0.has_aarch64=1 -a /home/fengqi/zephyrproject/build/zephyr/zephyr.elf + + These parameters are passed to :guilabel:`FVP_BaseR_AEMv8R` when launches. + Run :guilabel:`FVP_BaseR_AEMv8R --help` to see all command line options. + Run :guilabel:`FVP_BaseR_AEMv8R --list-params` to see all supported parameters. + The file ``zephyr.elf`` specified by ``-a`` is the binary built from Zephyr. + +.. figure:: images/create-new-launch-configuration_connection.jpg + :align: center + :alt: Arm DS create new launch configuration: connection + + Create new launch configuration: connection + +2. In :guilabel:`Files` tab: + + In the :guilabel:`Files` group, set :guilabel:`Load symbols from file` to full path of + :guilabel:`zephyr.elf` that you built. + +.. figure:: images/create-new-launch-configuration_files.jpg + :align: center + :alt: Arm DS create new launch configuration: files + + Create new launch configuration: files + +3. In :guilabel:`Debugger` tab: + + - In :guilabel:`Run control` box, check :guilabel:`Execute debugger commands` and insert:: + + add-symbol-file "/home/fengqi/zephyrproject/build/zephyr/zephyr.elf" EL1S:0 + + Replace :guilabel:`/home/fengqi/zephyrproject/build/zephyr/zephyr.elf` with your local path. + + - In :guilabel:`Paths` box, set :guilabel:`Source search directory` to the path to Zephyr source + code. + +.. figure:: images/create-new-launch-configuration_debugger.jpg + :align: center + :alt: Arm DS create new launch configuration: debugger + + Create new launch configuration: debugger + +After all these changes are made, click :guilabel:`Apply`, then click :guilabel:`Debug`. DS will +launch :guilabel:`FVP_BaseR_AEMv8R` and connect to it. You can see a new session is +connected in :guilabel:`Debug Control` window. + +.. figure:: images/DS-debug-working.jpg + :align: center + :alt: Arm DS working + + Arm DS is now working! + +References +********** + +.. target-notes:: + +.. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models +.. [2] Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile + https://developer.arm.com/documentation/ddi0600/latest/ +.. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs +.. [4] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map +.. [5] https://developer.arm.com/tools-and-software/embedded/arm-development-studio diff --git a/boards/arm/mps2/doc/index.rst b/boards/arm/mps2/doc/index.rst index b102b37fd8046..fbdfd3d0aa0ec 100644 --- a/boards/arm/mps2/doc/index.rst +++ b/boards/arm/mps2/doc/index.rst @@ -1,10 +1,10 @@ .. zephyr:board:: mps2 -ARM Ltd. -######## +The MPS2 board family includes the following board targets. Click on +the links below to get more information about each board target. -.. toctree:: - :maxdepth: 1 - :glob: +* :ref:`mps2_an521_board` +* :ref:`mps2_armv6m_board` +* :ref:`mps2_armv7m_board` - * +.. zephyr:board-supported-hw:: diff --git a/boards/arm/mps2/doc/mps2_armv6m.rst b/boards/arm/mps2/doc/mps2_armv6m.rst index 11666d3cf626d..b390c27d96a61 100644 --- a/boards/arm/mps2/doc/mps2_armv6m.rst +++ b/boards/arm/mps2/doc/mps2_armv6m.rst @@ -260,7 +260,7 @@ Running an applicatoin with FVP ------------------------------- Here is the same example for running with FVP. -Set the ``ARMFVP_BIN_PATH`` environemnt variable to the location of your FVP you have downloaded from `here `_ +Set the ``ARMFVP_BIN_PATH`` environment variable to the location of your FVP you have downloaded from `here `_ .. code-block:: console diff --git a/boards/arm/mps2/doc/mps2_armv7m.rst b/boards/arm/mps2/doc/mps2_armv7m.rst index ab6fab5d2928d..72ef21d3884c2 100644 --- a/boards/arm/mps2/doc/mps2_armv7m.rst +++ b/boards/arm/mps2/doc/mps2_armv7m.rst @@ -281,7 +281,7 @@ Running an applicatoin with FVP ------------------------------- Here is the same example for running with FVP. -Set the ``ARMFVP_BIN_PATH`` environemnt variable to the location of your FVP you have downloaded from `here `_ +Set the ``ARMFVP_BIN_PATH`` environment variable to the location of your FVP you have downloaded from `here `_ .. code-block:: console diff --git a/boards/arm/mps3/board.cmake b/boards/arm/mps3/board.cmake index e6204c4c2eabd..e129eec1e345c 100644 --- a/boards/arm/mps3/board.cmake +++ b/boards/arm/mps3/board.cmake @@ -43,6 +43,11 @@ elseif(CONFIG_BOARD_MPS3_CORSTONE310_FVP OR CONFIG_BOARD_MPS3_CORSTONE310_FVP_NS -C cpu0.MPU_S=16 ) endif() + if(CONFIG_ARM_PAC OR CONFIG_ARM_BTI) + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} + -C cpu0.CFGPACBTI=1 + ) + endif() endif() board_set_debugger_ifnset(qemu) diff --git a/boards/arm/mps4/board.cmake b/boards/arm/mps4/board.cmake index 4e5044ab1b7c1..9c4d4a0ef3376 100644 --- a/boards/arm/mps4/board.cmake +++ b/boards/arm/mps4/board.cmake @@ -26,6 +26,12 @@ if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP) ) endif() +if(CONFIG_ARM_PAC OR CONFIG_ARM_BTI) + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} + -C mps4_board.subsystem.cpu0.CFGPACBTI=1 + ) +endif() + if(CONFIG_BUILD_WITH_TFM) set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex) endif() diff --git a/boards/atmarktechno/degu_evk/degu_evk.yaml b/boards/atmarktechno/degu_evk/degu_evk.yaml index 3fd220f4df26f..8d946e8ee5a85 100644 --- a/boards/atmarktechno/degu_evk/degu_evk.yaml +++ b/boards/atmarktechno/degu_evk/degu_evk.yaml @@ -7,5 +7,5 @@ toolchain: supported: - i2c - adc - - usb_device + - usbd vendor: atmarktechno diff --git a/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts index 253d5ba48d1d9..51448f0e2b9ba 100644 --- a/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts @@ -52,75 +52,87 @@ compatible = "atmel-xplained-pro-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &piob 2 0>, /* AFE AD0 */ - <1 0 &piob 3 0>, /* AFE AD1 */ - <2 0 &pioa 24 0>, /* GPIO */ - <3 0 &pioa 25 0>, /* GPIO */ - <4 0 &pioa 15 0>, /* TIOA1 */ - <5 0 &pioa 16 0>, /* TIOB1 */ - <6 0 &pioa 11 0>, /* WKUP7 */ - <7 0 &piod 25 0>, /* GPIO */ - <8 0 &pioa 3 0>, /* TWD0 EXTx */ - <9 0 &pioa 4 0>, /* TWCK0 EXTx */ - <10 0 &pioa 21 0>, /* RXD1 */ - <11 0 &pioa 22 0>, /* TXD1 */ - <12 0 &piob 14 0>, /* SPI(NPCS1) */ - <13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */ - <14 0 &pioa 12 0>, /* SPI(MISO) EXTx */ - <15 0 &pioa 14 0>; /* SPI(SCK) EXTx */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &piob 2 0>, /* AFE AD0 */ + <1 0 &piob 3 0>, /* AFE AD1 */ + <2 0 &pioa 24 0>, /* GPIO */ + <3 0 &pioa 25 0>, /* GPIO */ + <4 0 &pioa 15 0>, /* TIOA1 */ + <5 0 &pioa 16 0>, /* TIOB1 */ + <6 0 &pioa 11 0>, /* WKUP7 */ + <7 0 &piod 25 0>, /* GPIO */ + <8 0 &pioa 3 0>, /* TWD0 EXTx */ + <9 0 &pioa 4 0>, /* TWCK0 EXTx */ + <10 0 &pioa 21 0>, /* RXD1 */ + <11 0 &pioa 22 0>, /* TXD1 */ + <12 0 &piob 14 0>, /* SPI(NPCS1) */ + <13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */ + <14 0 &pioa 12 0>, /* SPI(MISO) EXTx */ + <15 0 &pioa 14 0>; /* SPI(SCK) EXTx */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; ext2_header: xplained-pro-connector2 { compatible = "atmel-xplained-pro-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = /*<0 0 - - 0>, - */ - /*<1 0 - - 0>, - */ - <2 0 &pioe 2 0>, /* GPIO EBDG */ - <3 0 &piob 5 0>, /* GPIO EDBG */ - <4 0 &piod 21 0>, /* PWMHI1 */ - /*<5 0 - - 0>, - */ - <6 0 &piod 29 0>, /* GPIO ETH */ - <7 0 &piob 4 0>, /* GPIO */ - <8 0 &pioa 3 0>, /* TWD0 EXTx */ - <9 0 &pioa 4 0>, /* TWCK0 EXTx */ - <10 0 &pioa 5 0>, /* URXD1 EXT3 */ - <11 0 &pioa 6 0>, /* UTXD1 EXT3 */ - <12 0 &piod 23 0>, /* GPIO */ - <13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */ - <14 0 &pioa 12 0>, /* SPI(MISO) EXTx */ - <15 0 &pioa 14 0>; /* SPI(SCK) EXTx */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = /*<0 0 - - 0>, - */ + /*<1 0 - - 0>, - */ + <2 0 &pioe 2 0>, /* GPIO EBDG */ + <3 0 &piob 5 0>, /* GPIO EDBG */ + <4 0 &piod 21 0>, /* PWMHI1 */ + /*<5 0 - - 0>, - */ + <6 0 &piod 29 0>, /* GPIO ETH */ + <7 0 &piob 4 0>, /* GPIO */ + <8 0 &pioa 3 0>, /* TWD0 EXTx */ + <9 0 &pioa 4 0>, /* TWCK0 EXTx */ + <10 0 &pioa 5 0>, /* URXD1 EXT3 */ + <11 0 &pioa 6 0>, /* UTXD1 EXT3 */ + <12 0 &piod 23 0>, /* GPIO */ + <13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */ + <14 0 &pioa 12 0>, /* SPI(MISO) EXTx */ + <15 0 &pioa 14 0>; /* SPI(SCK) EXTx */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; ext3_header: xplained-pro-connector3 { compatible = "atmel-xplained-pro-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &pioa 17 0>, /* AFE AD0 */ - <1 0 &pioc 13 0>, /* AFE AD6 */ - <2 0 &piod 28 0>, /* GPIO */ - <3 0 &piod 17 0>, /* GPIO */ - <4 0 &piod 20 0>, /* PWMH0 */ - <5 0 &piod 24 0>, /* PWML0 */ - <6 0 &pioe 1 0>, /* GPIO */ - <7 0 &piod 26 0>, /* GPIO */ - <8 0 &pioa 3 0>, /* TWD0 EXTx */ - <9 0 &pioa 4 0>, /* TWCK0 EXTx */ - <10 0 &pioa 5 0>, /* URXD1 EXT2 */ - <11 0 &pioa 6 0>, /* UTXD1 EXT2 */ - <12 0 &piod 30 0>, /* GPIO */ - <13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */ - <14 0 &pioa 12 0>, /* SPI(MISO) EXTx */ - <15 0 &pioa 14 0>; /* SPI(SCK) EXTx */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &pioa 17 0>, /* AFE AD0 */ + <1 0 &pioc 13 0>, /* AFE AD6 */ + <2 0 &piod 28 0>, /* GPIO */ + <3 0 &piod 17 0>, /* GPIO */ + <4 0 &piod 20 0>, /* PWMH0 */ + <5 0 &piod 24 0>, /* PWML0 */ + <6 0 &pioe 1 0>, /* GPIO */ + <7 0 &piod 26 0>, /* GPIO */ + <8 0 &pioa 3 0>, /* TWD0 EXTx */ + <9 0 &pioa 4 0>, /* TWCK0 EXTx */ + <10 0 &pioa 5 0>, /* URXD1 EXT2 */ + <11 0 &pioa 6 0>, /* UTXD1 EXT2 */ + <12 0 &piod 30 0>, /* GPIO */ + <13 0 &pioa 13 0>, /* SPI(MOSI) EXTx */ + <14 0 &pioa 12 0>, /* SPI(MISO) EXTx */ + <15 0 &pioa 14 0>; /* SPI(SCK) EXTx */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; }; diff --git a/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts index eb777a75b1769..7b781ebe3ce8d 100644 --- a/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts +++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts @@ -69,68 +69,84 @@ compatible = "atmel-xplained-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */ - <1 0 &pioa 4 0>, /* TWCK0 y */ - <2 0 &piob 2 0>, /* URXD1 */ - <3 0 &piob 3 0>, /* UTXD1 */ - <4 0 &pioa 31 0>, /* SPI(CS) */ - <5 0 &pioa 13 0>, /* SPI(MOSI) y */ - <6 0 &pioa 12 0>, /* SPI(MISO) y */ - <7 0 &pioa 14 0>; /* SPI(SCK) y */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */ + <1 0 &pioa 4 0>, /* TWCK0 y */ + <2 0 &piob 2 0>, /* URXD1 */ + <3 0 &piob 3 0>, /* UTXD1 */ + <4 0 &pioa 31 0>, /* SPI(CS) */ + <5 0 &pioa 13 0>, /* SPI(MOSI) y */ + <6 0 &pioa 12 0>, /* SPI(MISO) y */ + <7 0 &pioa 14 0>; /* SPI(SCK) y */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; xplained2_header: xplained-connector2 { compatible = "atmel-xplained-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &pioa 22 0>, /* GPIO */ - <1 0 &pioc 12 0>, /* GPIO */ - <2 0 &piob 0 0>, /* GPIO */ - <3 0 &piob 1 0>, /* GPIO */ - <4 0 &pioa 17 0>, /* GPIO */ - <5 0 &pioa 21 0>, /* GPIO */ - <6 0 &pioc 13 0>, /* GPIO */ - <7 0 &pioc 15 0>; /* GPIO */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &pioa 22 0>, /* GPIO */ + <1 0 &pioc 12 0>, /* GPIO */ + <2 0 &piob 0 0>, /* GPIO */ + <3 0 &piob 1 0>, /* GPIO */ + <4 0 &pioa 17 0>, /* GPIO */ + <5 0 &pioa 21 0>, /* GPIO */ + <6 0 &pioc 13 0>, /* GPIO */ + <7 0 &pioc 15 0>; /* GPIO */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; xplained3_header: xplained-connector3 { compatible = "atmel-xplained-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &pioa 20 0>, /* GPIO */ - <1 0 &pioa 11 0>, /* GPIO */ - <2 0 &pioa 23 0>, /* GPIO */ - <3 0 &pioa 18 0>, /* GPIO */ - <4 0 &pioa 15 0>, /* GPIO */ - <5 0 &pioa 16 0>, /* GPIO */ - <6 0 &pioa 2 0>, /* GPIO */ - <7 0 &pioc 2 0>; /* GPIO */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &pioa 20 0>, /* GPIO */ + <1 0 &pioa 11 0>, /* GPIO */ + <2 0 &pioa 23 0>, /* GPIO */ + <3 0 &pioa 18 0>, /* GPIO */ + <4 0 &pioa 15 0>, /* GPIO */ + <5 0 &pioa 16 0>, /* GPIO */ + <6 0 &pioa 2 0>, /* GPIO */ + <7 0 &pioc 2 0>; /* GPIO */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; xplained4_header: xplained-connector4 { compatible = "atmel-xplained-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */ - <1 0 &pioa 4 0>, /* TWCK0 y */ - <2 0 &piob 2 0>, /* URXD1 */ - <3 0 &piob 3 0>, /* UTXD1 */ - <4 0 &pioa 30 0>, /* SPI(CS) */ - <5 0 &pioa 13 0>, /* SPI(MOSI) y */ - <6 0 &pioa 12 0>, /* SPI(MISO) y */ - <7 0 &pioa 14 0>; /* SPI(SCK) y */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &pioa 3 0>, /* TWD0 y */ + <1 0 &pioa 4 0>, /* TWCK0 y */ + <2 0 &piob 2 0>, /* URXD1 */ + <3 0 &piob 3 0>, /* UTXD1 */ + <4 0 &pioa 30 0>, /* SPI(CS) */ + <5 0 &pioa 13 0>, /* SPI(MOSI) y */ + <6 0 &pioa 12 0>, /* SPI(MISO) y */ + <7 0 &pioa 14 0>; /* SPI(SCK) y */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; }; diff --git a/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake b/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake deleted file mode 100644 index 3b32c9ca51816..0000000000000 --- a/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/ethernet@40050000 & /soc/mdio@40050000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi index b156ff7a91fdc..e11bf1ccc39e4 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi @@ -8,6 +8,7 @@ */ #include "sam_v71_xult-pinctrl.dtsi" +#include #include / { @@ -76,79 +77,91 @@ compatible = "atmel-xplained-pro-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &pioc 31 0>, /* AFE1 AD6 */ - <1 0 &pioa 19 0>, /* AFE0 AD8 */ - <2 0 &piob 3 0>, /* RTS0 */ - <3 0 &piob 2 0>, /* CTS0 */ - <4 0 &pioa 0 0>, /* PWMC0_H0 */ - <5 0 &pioc 30 0>, /* TIOB5 */ - <6 0 &piod 28 0>, /* WKUP5 */ - <7 0 &pioa 5 0>, /* GPIO */ - <8 0 &pioa 3 0>, /* TWD0 EXT2 */ - <9 0 &pioa 4 0>, /* TWCK0 EXT2 */ - <10 0 &piob 0 0>, /* RXD0 */ - <11 0 &piob 1 0>, /* TXD0 */ - <12 0 &piod 25 0>, /* SPI0(NPCS1) */ - <13 0 &piod 21 0>, /* SPI0(MOSI) EXT2 */ - <14 0 &piod 20 0>, /* SPI0(MISO) EXT2 */ - <15 0 &piod 22 0>; /* SPI0(SCK) EXT2 */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &pioc 31 0>, /* AFE1 AD6 */ + <1 0 &pioa 19 0>, /* AFE0 AD8 */ + <2 0 &piob 3 0>, /* RTS0 */ + <3 0 &piob 2 0>, /* CTS0 */ + <4 0 &pioa 0 0>, /* PWMC0_H0 */ + <5 0 &pioc 30 0>, /* TIOB5 */ + <6 0 &piod 28 0>, /* WKUP5 */ + <7 0 &pioa 5 0>, /* GPIO */ + <8 0 &pioa 3 0>, /* TWD0 EXT2 */ + <9 0 &pioa 4 0>, /* TWCK0 EXT2 */ + <10 0 &piob 0 0>, /* RXD0 */ + <11 0 &piob 1 0>, /* TXD0 */ + <12 0 &piod 25 0>, /* SPI0(NPCS1) */ + <13 0 &piod 21 0>, /* SPI0(MOSI) EXT2 */ + <14 0 &piod 20 0>, /* SPI0(MISO) EXT2 */ + <15 0 &piod 22 0>; /* SPI0(SCK) EXT2 */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; ext2_header: xplained-pro-connector2 { compatible = "atmel-xplained-pro-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &piod 30 0>, /* AFE0 AD0 */ - <1 0 &pioc 13 0>, /* AFE1 AD1 */ - <2 0 &pioa 6 0>, /* GPIO */ - <3 0 &piod 11 0>, /* GPIO */ - <4 0 &pioc 19 0>, /* PWMC0_H2 */ - <5 0 &piod 26 0>, /* PWMC0_L2 */ - <6 0 &pioa 2 0>, /* WKUP2 */ - <7 0 &pioa 24 0>, /* GPIO */ - <8 0 &pioa 3 0>, /* TWD0 EXT1 */ - <9 0 &pioa 4 0>, /* TWCK0 EXT1 */ - <10 0 &pioa 21 0>, /* RXD1 */ - <11 0 &piob 4 0>, /* TXD1 */ - <12 0 &piod 27 0>, /* SPI0(NPCS3) */ - <13 0 &piod 21 0>, /* SPI0(MOSI) EXT1 */ - <14 0 &piod 20 0>, /* SPI0(MISO) EXT1 */ - <15 0 &piod 22 0>; /* SPI0(SCK) EXT1 */ - /* GND */ - /* +3.3V */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &piod 30 0>, /* AFE0 AD0 */ + <1 0 &pioc 13 0>, /* AFE1 AD1 */ + <2 0 &pioa 6 0>, /* GPIO */ + <3 0 &piod 11 0>, /* GPIO */ + <4 0 &pioc 19 0>, /* PWMC0_H2 */ + <5 0 &piod 26 0>, /* PWMC0_L2 */ + <6 0 &pioa 2 0>, /* WKUP2 */ + <7 0 &pioa 24 0>, /* GPIO */ + <8 0 &pioa 3 0>, /* TWD0 EXT1 */ + <9 0 &pioa 4 0>, /* TWCK0 EXT1 */ + <10 0 &pioa 21 0>, /* RXD1 */ + <11 0 &piob 4 0>, /* TXD1 */ + <12 0 &piod 27 0>, /* SPI0(NPCS3) */ + <13 0 &piod 21 0>, /* SPI0(MOSI) EXT1 */ + <14 0 &piod 20 0>, /* SPI0(MISO) EXT1 */ + <15 0 &piod 22 0>; /* SPI0(SCK) EXT1 */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &piod 26 0>, /* A0-TD */ - <1 0 &pioc 31 0>, /* A1-AFE1 AD6 y */ - <2 0 &pioa 19 0>, /* A2-AFE0 AD8 y */ - <3 0 &piod 30 0>, /* A3-AFE0 AD0 y */ - <4 0 &pioc 13 0>, /* A4-AFE1 AD1 y */ - <5 0 &pioe 0 0>, /* A5-AFE1 AD11 */ - <6 0 &piod 28 0>, /* D0-URXD3 */ - <7 0 &piod 30 0>, /* D1-UTXD3 */ - <8 0 &pioa 0 0>, /* D2-PWMC0_H0 */ - <9 0 &pioa 6 0>, /* D3-GPIO */ - <10 0 &piod 27 0>, /* D4-SPI0_NPCS3 y */ - <11 0 &piod 11 0>, /* D5-PWMC0_H0 */ - <12 0 &pioc 19 0>, /* D6-PWMC0_H2 */ - <13 0 &pioa 2 0>, /* D7-PWMC0_H1 */ - <14 0 &pioa 5 0>, /* D8-PWMC1_PWML3 */ - <15 0 &pioc 9 0>, /* D9-TIOB7 */ - <16 0 &piod 25 0>, /* D10-SPI0_NPCS1 y */ - <17 0 &piod 21 0>, /* D11-SPI0_MOSI y */ - <18 0 &piod 20 0>, /* D12-SPI0_MISO y */ - <19 0 &piod 22 0>, /* D13-SPI0_SPCK y */ - <20 0 &pioa 3 0>, /* D14-TWD0 y */ - <21 0 &pioa 4 0>; /* D15-TWCK0 y */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = , /* TD */ + , /* AFE1 AD6 y */ + , /* AFE0 AD8 y */ + , /* AFE0 AD0 y */ + , /* AFE1 AD1 y */ + , /* AFE1 AD11 */ + , /* URXD3 */ + , /* UTXD3 */ + , /* PWMC0_H0 */ + , /* GPIO */ + , /* SPI0_NPCS3 y */ + , /* PWMC0_H0 */ + , /* PWMC0_H2 */ + , /* PWMC0_H1 */ + , /* PWMC1_PWML3 */ + , /* TIOB7 */ + , /* SPI0_NPCS1 y */ + , /* SPI0_MOSI y */ + , /* SPI0_MISO y */ + , /* SPI0_SPCK y */ + , /* TWD0 y */ + ; /* TWCK0 y */ + /* dts-format on */ }; }; diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts index 5b7514c26d872..501c64fcd4b3f 100644 --- a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts @@ -59,46 +59,58 @@ compatible = "atmel-xplained-pro-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &porta 6 0>, /* ADC6 */ - <1 0 &porta 7 0>, /* ADC7 */ - <2 0 &porta 13 0>, /* GPIO */ - <3 0 &porta 28 0>, /* GPIO */ - <4 0 &porta 18 0>, /* PWM_T0_W2 */ - <5 0 &porta 19 0>, /* PWM_T0_W3 */ - <6 0 &porta 22 0>, /* GPIO */ - <7 0 &porta 23 0>, /* GPIO */ - <8 0 &porta 16 0>, /* TWD1 EXT2 */ - <9 0 &porta 17 0>, /* TWCK1 EXT2 */ - <10 0 &porta 5 0>, /* RXD0 */ - <11 0 &porta 4 0>, /* TXD0 */ - <12 0 &portb 3 0>, /* SPI5(SS) */ - <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ - <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ - <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = <0 0 &porta 6 0>, /* ADC6 */ + <1 0 &porta 7 0>, /* ADC7 */ + <2 0 &porta 13 0>, /* GPIO */ + <3 0 &porta 28 0>, /* GPIO */ + <4 0 &porta 18 0>, /* PWM_T0_W2 */ + <5 0 &porta 19 0>, /* PWM_T0_W3 */ + <6 0 &porta 22 0>, /* GPIO */ + <7 0 &porta 23 0>, /* GPIO */ + <8 0 &porta 16 0>, /* TWD1 EXT2 */ + <9 0 &porta 17 0>, /* TWCK1 EXT2 */ + <10 0 &porta 5 0>, /* RXD0 */ + <11 0 &porta 4 0>, /* TXD0 */ + <12 0 &portb 3 0>, /* SPI5(SS) */ + <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ + <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ + <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; ext2_header: xplained-pro-connector2 { compatible = "atmel-xplained-pro-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = /*<0 0 - - 0>, - */ - /*<1 0 - - 0>, - */ - <2 0 &porta 15 0>, /* GPIO */ - /*<3 0 - - 0>, - */ - /*<4 0 - - 0>, - */ - /*<5 0 - - 0>, - */ - /*<6 0 - - 0>, - */ - <7 0 &porta 8 0>, /* GPIO */ - <8 0 &porta 16 0>, /* TWD1 EXT1 */ - <9 0 &porta 17 0>, /* TWCK1 EXT1 */ - /*<11 0 - - 0>, - */ - /*<12 0 - - 0>, - */ - <12 0 &porta 14 0>, /* GPIO */ - <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ - <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ - <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + gpio-map-pass-thru = <0 0x3f>; + + /* dts-format off */ + /* Shared */ + gpio-map = /*<0 0 - - 0>, - */ + /*<1 0 - - 0>, - */ + <2 0 &porta 15 0>, /* GPIO */ + /*<3 0 - - 0>, - */ + /*<4 0 - - 0>, - */ + /*<5 0 - - 0>, - */ + /*<6 0 - - 0>, - */ + <7 0 &porta 8 0>, /* GPIO */ + <8 0 &porta 16 0>, /* TWD1 EXT1 */ + <9 0 &porta 17 0>, /* TWCK1 EXT1 */ + /*<10 0 - - 0>, - */ + /*<11 0 - - 0>, - */ + <12 0 &porta 14 0>, /* GPIO */ + <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ + <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ + <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + /* GND */ + /* +3.3V */ + /* dts-format on */ }; }; @@ -176,8 +188,8 @@ slptr-gpios = <&porta 20 GPIO_ACTIVE_HIGH>; dig2-gpios = <&portb 17 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; status = "okay"; - tx-pwr-min = [01 11]; /* -17.0 dBm */ - tx-pwr-max = [00 04]; /* 4.0 dBm */ + tx-pwr-min = [01 11]; /* -17.0 dBm */ + tx-pwr-max = [00 04]; /* 4.0 dBm */ tx-pwr-table = [00 01 03 04 05 05 06 06 07 07 07 08 08 09 09 0a 0a 0a 0b 0b 0b 0b 0c 0c diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig index d7ee894fcf4cd..1827514f24940 100644 --- a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig @@ -30,3 +30,5 @@ CONFIG_UART_CONSOLE=y # Multicore Support CONFIG_SMP=y +CONFIG_PM_CPU_OPS=y +CONFIG_MP_MAX_NUM_CPUS=2 diff --git a/boards/ct/ctcc/ctcc_nrf52840.yaml b/boards/ct/ctcc/ctcc_nrf52840.yaml index 332273c3a4257..6ca082d8d2765 100644 --- a/boards/ct/ctcc/ctcc_nrf52840.yaml +++ b/boards/ct/ctcc/ctcc_nrf52840.yaml @@ -8,7 +8,7 @@ toolchain: supported: - ble - gpio - - usb_device + - usbd - watchdog - counter vendor: ct diff --git a/boards/ct/ctcc/doc/index.rst b/boards/ct/ctcc/doc/index.rst index 5a890893c230f..f157c53409d08 100644 --- a/boards/ct/ctcc/doc/index.rst +++ b/boards/ct/ctcc/doc/index.rst @@ -194,7 +194,7 @@ with the additional step of connecting an external debugger. To test flashed software, plug in ``ctcc`` card to mPCIe/M.2 slot or use mPCIe/M.2 adapter to USB and plug such adapter to USB port. * For ``ctcc/nrf52840`` check on Linux system by entering ``lsusb`` command if the following device appears: ``NordicSemiconductor MCUBOOT`` or ``NordicSemiconductor USB-DEV`` (when booted into blinky example). - * For ``ctcc/nrf9161`` it's not possible to see a change in ``lsusb`` due to the on-board USB-UART converter. Intead, connect to the UART console using a terminal emulation program of your choice. + * For ``ctcc/nrf9161`` it's not possible to see a change in ``lsusb`` due to the on-board USB-UART converter. Instead, connect to the UART console using a terminal emulation program of your choice. References ********** diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi index 764348106c9f7..988f974e2db8b 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include / { @@ -34,29 +35,29 @@ compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* shared */ - gpio-map = <0 0 &gpio_prt9 0 0>, /* A0- */ - <1 0 &gpio_prt9 1 0>, /* A1- */ - <2 0 &gpio_prt9 2 0>, /* A2- */ - <3 0 &gpio_prt9 3 0>, /* A3- */ - <4 0 &gpio_prt9 4 0>, /* A4- */ - <5 0 &gpio_prt9 5 0>, /* A5- */ - <6 0 &gpio_prt5 0 0>, /* D0-RX-5 */ - <7 0 &gpio_prt5 1 0>, /* D1-TX-5 */ - <8 0 &gpio_prt5 2 0>, /* D2-RTS-5 */ - <9 0 &gpio_prt5 3 0>, /* D3-CTS-5 */ - <10 0 &gpio_prt5 4 0>, /* D4- */ - <11 0 &gpio_prt5 5 0>, /* D5- */ - <12 0 &gpio_prt5 6 0>, /* D6- */ - <13 0 &gpio_prt0 2 0>, /* D7- */ - <14 0 &gpio_prt13 0 0>, /* D8-RX-6 y */ - <15 0 &gpio_prt13 1 0>, /* D9-TX-6 y */ - <16 0 &gpio_prt12 3 0>, /* D10-SPI6_SEL0 y */ - <17 0 &gpio_prt12 0 0>, /* D11-SPI6_MOSI y */ - <18 0 &gpio_prt12 1 0>, /* D12-SPI6_MISO y */ - <19 0 &gpio_prt12 2 0>, /* D13-SPI6_CLK y */ - <20 0 &gpio_prt6 1 0>, /* D14-SDAx */ - <21 0 &gpio_prt6 0 0>; /* D15-SCLx */ + gpio-map-pass-thru = <0 0x3f>; /* shared */ + gpio-map = , + , + , + , + , + , + , /* RX-5 */ + , /* TX-5 */ + , /* RTS-5 */ + , /* CTS-5 */ + , + , + , + , + , /* RX-6 y */ + , /* TX-6 y */ + , /* SPI6_SEL0 y */ + , /* SPI6_MOSI y */ + , /* SPI6_MISO y */ + , /* SPI6_CLK y */ + , /* SDAx */ + ; /* SCLx */ }; }; diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index c2d72844f5af7..1cc3856cee8ad 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -46,6 +46,9 @@ set(mimxrt1060_evkb_DEPRECATED set(neorv32_DEPRECATED neorv32/neorv32/up5kdemo ) +set(panb511evb_DEPRECATED + panb611evb +) set(xiao_esp32c6_DEPRECATED xiao_esp32c6/esp32c6/hpcore ) diff --git a/boards/enclustra/mercury_xu/mercury_xu.dts b/boards/enclustra/mercury_xu/mercury_xu.dts index c0abbec19a3ac..ddd7c43d8498c 100644 --- a/boards/enclustra/mercury_xu/mercury_xu.dts +++ b/boards/enclustra/mercury_xu/mercury_xu.dts @@ -12,6 +12,11 @@ model = "Mercury XU"; compatible = "enclustra,mercury_xu"; + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 DT_SIZE_M(64)>; + }; + chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst index 4be450d341ac9..140619f24bea5 100644 --- a/boards/espressif/esp32_ethernet_kit/doc/index.rst +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -150,7 +150,7 @@ corner and going clockwise. PoE Board (B) ------------- -This board coverts power delivered over the Ethernet cable (PoE) to provide a +This board converts power delivered over the Ethernet cable (PoE) to provide a power supply for the Ethernet Board (A). The main components of the PoE Board (B) are shown on the block diagram under `Functionality Overview`_. diff --git a/boards/espressif/esp32h2_devkitm/Kconfig b/boards/espressif/esp32h2_devkitm/Kconfig new file mode 100644 index 0000000000000..c96fa92d3431f --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp32h2_devkitm/Kconfig.esp32h2_devkitm b/boards/espressif/esp32h2_devkitm/Kconfig.esp32h2_devkitm new file mode 100644 index 0000000000000..905e66f73c662 --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/Kconfig.esp32h2_devkitm @@ -0,0 +1,7 @@ +# ESP32-H2 DevKitM board configuration + +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32H2_DEVKITM + select SOC_ESP32_H2_MINI_H4 diff --git a/boards/espressif/esp32h2_devkitm/Kconfig.sysbuild b/boards/espressif/esp32h2_devkitm/Kconfig.sysbuild new file mode 100644 index 0000000000000..95e4e1d103975 --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32h2_devkitm/board.cmake b/boards/espressif/esp32h2_devkitm/board.cmake new file mode 100644 index 0000000000000..2f04d1fe8861e --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32h2_devkitm/board.yml b/boards/espressif/esp32h2_devkitm/board.yml new file mode 100644 index 0000000000000..55e4ccba12051 --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/board.yml @@ -0,0 +1,6 @@ +board: + name: esp32h2_devkitm + full_name: ESP32-H2-DevKitM + vendor: espressif + socs: + - name: esp32h2 diff --git a/boards/espressif/esp32h2_devkitm/doc/img/esp32h2_devkitm.webp b/boards/espressif/esp32h2_devkitm/doc/img/esp32h2_devkitm.webp new file mode 100644 index 0000000000000..187f8192d5fb2 Binary files /dev/null and b/boards/espressif/esp32h2_devkitm/doc/img/esp32h2_devkitm.webp differ diff --git a/boards/espressif/esp32h2_devkitm/doc/index.rst b/boards/espressif/esp32h2_devkitm/doc/index.rst new file mode 100644 index 0000000000000..5e653fbf564c4 --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/doc/index.rst @@ -0,0 +1,124 @@ +.. zephyr:board:: esp32h2_devkitm + +Overview +******** + +ESP32-H2-DevKitM-1 is an entry-level development board based on the ESP32-H2-MINI-1 module, +which integrates Bluetooth® Low Energy (LE) and IEEE 802.15.4 connectivity. It features +the ESP32-H2 SoC — a 32-bit RISC-V core designed for low-power, secure wireless communication, +supporting Bluetooth 5 (LE), Bluetooth Mesh, Thread, Matter, and Zigbee protocols. +This module is ideal for a wide range of low-power IoT applications. + +For details on getting started, check `ESP32-H2-DevKitM-1`_. + +Hardware +******** + +ESP32-H2 combines IEEE 802.15.4 connectivity with Bluetooth 5 (LE). The SoC is powered by +a single-core, 32-bit RISC-V microcontroller that can be clocked up to 96 MHz. The ESP32-H2 has +been designed to ensure low power consumption and security for connected devices. ESP32-H2 has +320 KB of SRAM with 16 KB of Cache, 128 KB of ROM, 4 KB LP of memory, and a built-in 2 MB or 4 MB +SiP flash. It has 19 programmable GPIOs with support for ADC, SPI, UART, I2C, I2S, RMT, GDMA +and LED PWM. + +Most of ESP32-H2-DevKitM-1's I/O pins are broken out to the pin headers on both sides for easy +interfacing. Developers can either connect peripherals with jumper wires or mount the board +on a breadboard. + +ESP32-H2 main features: + +- RISC-V 32-bit single-core microprocessor +- 320 KB of internal RAM +- 4 KB LP Memory +- Bluetooth LE: Bluetooth 5.3 certified +- IEEE 802.15.4 (Zigbee and Thread) +- 19 programmable GPIOs +- Numerous peripherals (details below) + +Digital interfaces: + +- 19x GPIOs +- 2x UART +- 2x I2C +- 1x General-purpose SPI +- 1x I2S +- 1x Pulse counter +- 1x USB Serial/JTAG controller +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- 1x LED PWM controller, up to 6 channels +- 1x Motor Control PWM (MCPWM) +- 1x Remote Control peripheral (RMT), with up to 2 TX and 2 RX channels +- 1x Parallel IO interface (PARLIO) +- General DMA controller (GDMA), with 3 transmit channels and 3 receive channels +- Event Task Matrix (ETM) + +Analog interfaces: + +- 1x 12-bit SAR ADCs, up to 5 channels +- 1x Temperature sensor (die) + +Timers: + +- 1x 52-bit system timer +- 2x 54-bit general-purpose timers +- 3x Watchdog timers + +Low Power: + +- Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, ECC, HMAC, RSA, SHA, Digital signature, Hash) +- Random number generator (RNG) + +For detailed information, check the datasheet at `ESP32-H2 Datasheet`_ or the Technical Reference +Manual at `ESP32-H2 Technical Reference Manual`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System requirements +******************* + +Espressif HAL requires Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Runners +******* + +.. zephyr:board-supported-runners:: + +.. include:: ../../../espressif/common/building-flashing.rst + :start-after: espressif-building-flashing + +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + +Debugging +********* + +.. include:: ../../../espressif/common/openocd-debugging.rst + :start-after: espressif-openocd-debugging + +References +********** + +.. target-notes:: + +.. _`ESP32-H2-DevKitM-1`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32h2/esp32-h2-devkitm-1/user_guide.html +.. _`ESP32-H2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf +.. _`ESP32-H2 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-h2_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32h2_devkitm/esp32h2_devkitm-pinctrl.dtsi b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm-pinctrl.dtsi new file mode 100644 index 0000000000000..1dc64fda31b8c --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm-pinctrl.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; +}; diff --git a/boards/espressif/esp32h2_devkitm/esp32h2_devkitm.dts b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm.dts new file mode 100644 index 0000000000000..238ba3cdd17cf --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm.dts @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32h2_devkitm-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32H2-DevkitM"; + compatible = "espressif,esp32h2"; + + chosen { + zephyr,sram = &sramhp; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button1; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&coretemp { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/espressif/esp32h2_devkitm/esp32h2_devkitm.yaml b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm.yaml new file mode 100644 index 0000000000000..786b700e77eaf --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm.yaml @@ -0,0 +1,14 @@ +identifier: esp32h2_devkitm/esp32h2 +name: ESP32-H2-DevKitM +vendor: espressif +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - watchdog + - uart + - counter + - entropy + - spi diff --git a/boards/espressif/esp32h2_devkitm/esp32h2_devkitm_defconfig b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm_defconfig new file mode 100644 index 0000000000000..187793c76e8cc --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/esp32h2_devkitm_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/espressif/esp32h2_devkitm/support/openocd.cfg b/boards/espressif/esp32h2_devkitm/support/openocd.cfg new file mode 100644 index 0000000000000..5dac2bad03f9e --- /dev/null +++ b/boards/espressif/esp32h2_devkitm/support/openocd.cfg @@ -0,0 +1,4 @@ +# ESP32H2 has built-in JTAG interface over USB port in pins GPIO26/GPIO27 (D-/D+). +set ESP_RTOS none + +source [find board/esp32h2-builtin.cfg] diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts index 39a986ae2b670..e7883bcbfaba8 100644 --- a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts @@ -32,8 +32,8 @@ / { /* * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support. - * - Lowest 96 kB SRAM allocated to Secure image (sram0_s). - * - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns). + * - Lowest 72 kB SRAM allocated to Secure image (sram0_s). + * - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns). * * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for * the FLPR MCU. @@ -59,14 +59,11 @@ }; &cpuapp_rram { - /* TODO: revert this hack when TF-M update is available that fixes partition sizes */ - reg = <0x0 DT_SIZE_K(1022)>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - /* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the + /* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the * last 62kB are reserved for the FLPR MCU. * * This static layout needs to be the same with the upstream TF-M layout in the @@ -95,12 +92,12 @@ slot0_ns_partition: partition@6A000 { label = "image-0-nonsecure"; - reg = <0x0006A000 DT_SIZE_K(504)>; + reg = <0x0006A000 DT_SIZE_K(494)>; }; - storage_partition: partition@E8000 { + storage_partition: partition@E5800 { label = "storage"; - reg = <0x000E8000 DT_SIZE_K(32)>; + reg = <0x000E5800 DT_SIZE_K(32)>; }; }; }; diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml index d2ad19f03c4a9..19bb368fc6134 100644 --- a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml +++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml @@ -11,7 +11,7 @@ toolchain: - zephyr sysbuild: true ram: 192 -flash: 1022 +flash: 1012 supported: - adc - gpio diff --git a/boards/ezurio/bl654_usb/bl654_usb.yaml b/boards/ezurio/bl654_usb/bl654_usb.yaml index 660ee57e4672a..4551f47dd61b2 100644 --- a/boards/ezurio/bl654_usb/bl654_usb.yaml +++ b/boards/ezurio/bl654_usb/bl654_usb.yaml @@ -8,7 +8,7 @@ toolchain: - zephyr - gnuarmemb supported: - - usb_device + - usbd - ble - pwm - watchdog diff --git a/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.yaml b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.yaml index 4d92d331a2fd6..e3bd3adcc9f64 100644 --- a/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.yaml +++ b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.yaml @@ -8,7 +8,7 @@ toolchain: - zephyr - gnuarmemb supported: - - usb_device + - usbd - ble - pwm - watchdog diff --git a/boards/fanke/fk723m1_zgt6/Kconfig.defconfig b/boards/fanke/fk723m1_zgt6/Kconfig.defconfig new file mode 100644 index 0000000000000..ef751e6df5828 --- /dev/null +++ b/boards/fanke/fk723m1_zgt6/Kconfig.defconfig @@ -0,0 +1,13 @@ +# FK723M1-ZGT6 board configuration +# +# Copyright The Zephyr Project Contributors +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_FK723M1_ZGT6 + +config SDMMC_STM32_CLOCK_CHECK + default n + +endif # BOARD_FK723M1_ZGT6 diff --git a/boards/fanke/fk723m1_zgt6/Kconfig.fk723m1_zgt6 b/boards/fanke/fk723m1_zgt6/Kconfig.fk723m1_zgt6 index 3f76aecc92d02..265f3cd474426 100644 --- a/boards/fanke/fk723m1_zgt6/Kconfig.fk723m1_zgt6 +++ b/boards/fanke/fk723m1_zgt6/Kconfig.fk723m1_zgt6 @@ -3,10 +3,3 @@ config BOARD_FK723M1_ZGT6 select SOC_STM32H723XX - -if BOARD_FK723M1_ZGT6 - -config SDMMC_STM32_CLOCK_CHECK - default n - -endif # BOARD_FK723M1_ZGT6 diff --git a/boards/fanke/fk723m1_zgt6/fk723m1_zgt6.dts b/boards/fanke/fk723m1_zgt6/fk723m1_zgt6.dts index 603f80fdd0065..924f3aa192b39 100644 --- a/boards/fanke/fk723m1_zgt6/fk723m1_zgt6.dts +++ b/boards/fanke/fk723m1_zgt6/fk723m1_zgt6.dts @@ -120,7 +120,7 @@ zephyr_udc0: &usbotg_hs { pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; pinctrl-names = "default"; - clocks = <&rcc STM32_CLOCK(AHB3, 16U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 16)>, <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; disk-name = "SD"; status = "okay"; diff --git a/boards/fobe/index.rst b/boards/fobe/index.rst new file mode 100644 index 0000000000000..1a6475357f0aa --- /dev/null +++ b/boards/fobe/index.rst @@ -0,0 +1,10 @@ +.. _boards-fobe: + +FoBE Studio +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/fobe/quill_nrf52840_mesh/Kconfig.defconfig b/boards/fobe/quill_nrf52840_mesh/Kconfig.defconfig new file mode 100644 index 0000000000000..22e40e741e7c4 --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/Kconfig.defconfig @@ -0,0 +1,10 @@ +# QUILL NRF52840 MESH board configuration + +# Copyright (c) 2025 Chiho Sin +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QUILL_NRF52840_MESH + +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" + +endif # BOARD_QUILL_NRF52840_MESH diff --git a/boards/fobe/quill_nrf52840_mesh/Kconfig.quill_nrf52840_mesh b/boards/fobe/quill_nrf52840_mesh/Kconfig.quill_nrf52840_mesh new file mode 100644 index 0000000000000..0e4ed3d8ca01e --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/Kconfig.quill_nrf52840_mesh @@ -0,0 +1,7 @@ +# QUILL NRF52840 MESH board configuration + +# Copyright (c) 2025 Chiho Sin +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QUILL_NRF52840_MESH + select SOC_NRF52840_QIAA diff --git a/boards/fobe/quill_nrf52840_mesh/board.cmake b/boards/fobe/quill_nrf52840_mesh/board.cmake new file mode 100644 index 0000000000000..72087dbc1ca80 --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/board.cmake @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(nrfjprog "--nrf-family=NRF52") +board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +board_runner_args(uf2 "--board-id=nRF52840-FoBEF1101-rev1a") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/fobe/quill_nrf52840_mesh/board.yml b/boards/fobe/quill_nrf52840_mesh/board.yml new file mode 100644 index 0000000000000..ff5febf8ca36e --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/board.yml @@ -0,0 +1,6 @@ +board: + name: quill_nrf52840_mesh + full_name: Quill nRF52840 Mesh + vendor: fobe + socs: + - name: nrf52840 diff --git a/boards/fobe/quill_nrf52840_mesh/doc/img/quill_nrf52840_mesh.webp b/boards/fobe/quill_nrf52840_mesh/doc/img/quill_nrf52840_mesh.webp new file mode 100644 index 0000000000000..93ec819fb551a Binary files /dev/null and b/boards/fobe/quill_nrf52840_mesh/doc/img/quill_nrf52840_mesh.webp differ diff --git a/boards/fobe/quill_nrf52840_mesh/doc/index.rst b/boards/fobe/quill_nrf52840_mesh/doc/index.rst new file mode 100644 index 0000000000000..029b99345195c --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/doc/index.rst @@ -0,0 +1,156 @@ +.. zephyr:board:: quill_nrf52840_mesh + +Overview +******** + +The FoBE Quill nRF52840 Mesh is a development kit featuring the nRF52840 SoC and an integrated +SX1262 LoRa® transceiver. + +For more details see the `FoBE Quill nRF52840 Mesh`_ documentation page. + +Hardware +******** + +The FoBE Quill nRF52840 Mesh is a compact and versatile development platform for IoT solutions. +It combines Nordic's high-end multiprotocol SoC, the nRF52840, with Semtech's ultra-low-power +sub-GHz radio transceiver, the SX1262 (packaged using SiP technology). +Designed for IoT applications, it offers a comprehensive wireless connectivity solution, +supporting protocols such as Bluetooth 5, Thread, Zigbee, IEEE 802.15.4, and LoRa®. + +This development board is feature-rich, including a battery charger, +dedicated power path management, an ultra-low quiescent current DC-DC converter, +a 1.14-inch color IPS display, user-programmable LEDs and buttons, an MFP expansion connector, +a reversible USB-C connector, and header sockets for easy expansion. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The `FoBE Quill nRF52840 Mesh`_ Documentation has detailed information about board +connections. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The Quill nRF52840 Mesh ships with the `FoBE nRF52 Bootloader`_ which supports flashing +using `UF2`_. Doing so allows easy flashing of new images, but does not support debugging the +device. For debugging please use `External Debugger`_. + +UF2 Flashing +============ + +To enter the bootloader, connect the USB port of the Quill nRF52840 Mesh to your host, +and double tap the reset button. A mass storage device named ``FOBEBOOT`` should appear +on the host. Using the command line, or your file manager copy the :file:`zephyr/zephyr.uf2` +file from your build to the base of the ``FOBEBOOT`` mass storage device. The board will +automatically reset and launch the newly flashed application. + +External Debugger +================= + +In order to support debugging the device, instead of using the bootloader, you can use an +:ref:`External Debug Probe `. To flash and debug Zephyr applications you need to +connect an SWD debugger to the SWD pins on the board. + +For Segger J-Link debug probes, follow the instructions in the :ref:`jlink-external-debug-probe` +page to install and configure all the necessary software. + +Building & Flashing +******************* + +Simple build and flash +====================== + +Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` +for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: quill_nrf52840_mesh + :goals: build + +The usual ``flash`` target will work with the ``quill_nrf52840_mesh`` board configuration. +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: quill_nrf52840_mesh + :goals: flash + +Flashing with External Debugger +-------------------------------- + +Setup and connect a supported debug probe (JLink, instructions at +:ref:`jlink-external-debug-probe` or BlackMagic Probe). Then build and flash applications as usual. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board can be found. For example, +under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application. Just add ``CONFIG_BOOT_DELAY=5000`` to the configuration, +so that USB CDC ACM is initialized before any text is printed: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: quill_nrf52840_mesh + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +Debugging +********* + +Refer to the :ref:`jlink-external-debug-probe` page to learn about debugging +boards with a Segger IC. + +Debugging using a BlackMagic Probe is also supported. + +Here is an example for building and debugging the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: quill_nrf52840_mesh + :goals: debug + +Testing the LEDs +***************** + +There is a sample that allows to test that LEDs on the board are working properly with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: quill_nrf52840_mesh + :goals: build flash + +You can build and flash the examples to make sure Zephyr is running correctly on your board. + +Testing shell over USB +*********************** + +There is a sample that allows to test shell interface over USB CDC ACM interface with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :board: quill_nrf52840_mesh + :goals: build flash + +References +********** + +.. target-notes:: + +.. _`FoBE Quill nRF52840 Mesh`: https://docs.fobestudio.com/product/f1101 +.. _`FoBE nRF52 Bootloader`: https://github.com/fobe-projects/fobe-nrf52-bootloader +.. _`UF2`: https://github.com/microsoft/uf2 diff --git a/boards/fobe/quill_nrf52840_mesh/fobe_quill_connector.dtsi b/boards/fobe/quill_nrf52840_mesh/fobe_quill_connector.dtsi new file mode 100644 index 0000000000000..b44a7d77e6f6b --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/fobe_quill_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Chiho Sin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + quill_header: connector { + compatible = "fobe,quill-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 12 0>, /* D0 */ + <1 0 &gpio1 11 0>, /* D1 */ + <2 0 &gpio1 14 0>, /* D2 */ + <3 0 &gpio1 0 0>, /* D3 */ + <4 0 &gpio0 24 0>, /* D4 */ + <5 0 &gpio0 22 0>, /* D5 */ + <6 0 &gpio0 20 0>, /* D6 */ + <7 0 &gpio0 17 0>, /* D7 */ + <8 0 &gpio0 15 0>, /* D8 */ + <9 0 &gpio0 13 0>, /* D9 */ + <10 0 &gpio0 16 0>, /* D10 */ + <11 0 &gpio0 14 0>, /* D11 */ + <12 0 &gpio0 11 0>, /* D12 */ + <13 0 &gpio1 8 0>, /* D13 */ + <14 0 &gpio0 3 0>, /* A0 */ + <15 0 &gpio0 28 0>, /* A1 */ + <16 0 &gpio0 2 0>, /* A2 */ + <17 0 &gpio0 29 0>, /* A3 */ + <18 0 &gpio0 31 0>, /* A4 */ + <19 0 &gpio0 30 0>; /* A5 */ + }; +}; + +quill_spi: &spi2 {}; +quill_i2c: &i2c0 {}; +quill_serial: &uart0 {}; +quill_adc: &adc {}; diff --git a/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake b/boards/fobe/quill_nrf52840_mesh/pre_dt_board.cmake similarity index 56% rename from boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake rename to boards/fobe/quill_nrf52840_mesh/pre_dt_board.cmake index 3b32c9ca51816..3369c21d3af5b 100644 --- a/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake +++ b/boards/fobe/quill_nrf52840_mesh/pre_dt_board.cmake @@ -1,6 +1,7 @@ -# Copyright (c) 2024 Gerson Fernando Budke +# Copyright (c) 2022 Nordic Semiconductor # SPDX-License-Identifier: Apache-2.0 # Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/ethernet@40050000 & /soc/mdio@40050000 +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh-pinctrl.dtsi b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh-pinctrl.dtsi new file mode 100644 index 0000000000000..d91cb7067db02 --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh-pinctrl.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2025 Chiho Sin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = ; + }; + + group2 { + psels = ; + bias-pull-up; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = ; + nordic,invert; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + spi2_default: spi2_default { + group1 { + psels = , + , + ; + }; + }; + + spi2_sleep: spi2_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh.dts b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh.dts new file mode 100644 index 0000000000000..8c0967ba4449c --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh.dts @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 Chiho Sin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "quill_nrf52840_mesh_common.dtsi" + +/ { + model = "FoBE Quill nRF52840 Mesh"; + compatible = "fobe,quill-nrf52840-mesh"; +}; diff --git a/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh.yaml b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh.yaml new file mode 100644 index 0000000000000..14823a53fcbd5 --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh.yaml @@ -0,0 +1,23 @@ +identifier: quill_nrf52840_mesh +name: Quill nRF52840 Mesh +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - ble + - counter + - gpio + - lora + - i2c + - i2s + - pwm + - spi + - usbd + - watchdog + - netif:openthread +vendor: fobe diff --git a/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_common.dtsi b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_common.dtsi new file mode 100644 index 0000000000000..aac440914bdfb --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_common.dtsi @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2025 Chiho Sin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include "quill_nrf52840_mesh-pinctrl.dtsi" +#include "fobe_quill_connector.dtsi" + +/ { + chosen { + zephyr,ieee802154 = &ieee802154; + zephyr,display = &st7789v_tft; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + label = "Blue LED"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + led1: led_1 { + label = "Backlight LED"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + disp_pwr: disp_pwr { + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + startup-delay-us = <5000>; + }; + + peri_reg: peri_reg { + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi3>; + dc-gpios = <&gpio0 6 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + reset-gpios = <&gpio0 26 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + st7789v_tft: st7789v_tft@0 { + compatible = "sitronix,st7789v"; + power-domains = <&disp_pwr>; + status = "okay"; + reg = <0>; + mipi-max-frequency = ; + width = <135>; + height = <240>; + x-offset = <52>; + y-offset = <40>; + vcom = <0x3F>; + gctrl = <0x05>; + vrhs = <0x0F>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x05>; + lcm = <0x2C>; + porch-param = [05 05 00 33 33]; + cmd2en-param = [5A 69 02 00]; + pwctrl1-param = [A4 A1]; + pvgam-param = [D0 05 09 09 08 14 28 33 3F 07 13 14 28 30]; + nvgam-param = [D0 05 09 09 08 03 24 32 32 3B 14 13 28 2F]; + ram-param = [00 F0]; + rgb-param = [40 02 14]; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "USR Button"; + zephyr,code = ; + }; + }; + + vbatt { + compatible = "voltage-divider"; + io-channels = <&adc 3>; + output-ohms = <1000000>; + full-ohms = <(1000000 + 1500000)>; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + mcuboot-led0 = &led0; + backlight = &led1; + lora0 = &lora0; + sw0 = &button0; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi2 { + status = "okay"; + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + + lora0: lora@0 { + compatible = "semtech,sx1262"; + label = "sx1262"; + reg = <0>; + reset-gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + busy-gpios = <&gpio1 4 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + rx-enable-gpios = <&gpio0 25 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + dio1-gpios = <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + dio2-tx-enable; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <2>; + spi-max-frequency = ; + }; +}; + +&spi3 { + status = "okay"; + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; + cs-gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; +}; + +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + +&adc { + status = "okay"; +}; + +&uicr { + gpio-as-nreset; +}; + +&ieee802154 { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_defconfig b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_defconfig new file mode 100644 index 0000000000000..ecc290a695a39 --- /dev/null +++ b/boards/fobe/quill_nrf52840_mesh/quill_nrf52840_mesh_defconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y + +# Enable Power +CONFIG_POWER_DOMAIN=y +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_POWER_DOMAIN=y + +# Build UF2 by default, supported by the Adafruit nRF52 Bootloader +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/google/dragonclaw/doc/index.rst b/boards/google/dragonclaw/doc/index.rst index ed5c8c1113592..a084015a9a085 100644 --- a/boards/google/dragonclaw/doc/index.rst +++ b/boards/google/dragonclaw/doc/index.rst @@ -15,7 +15,7 @@ Hardware - STM32F412CGU6 UFQFPN48 package -Peripherial Mapping +Peripheral Mapping =================== - USART_1 TX/RX : PA9/PA10 diff --git a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts index 4ba5a5b9fdaf3..c7f799cee7428 100644 --- a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts +++ b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include / { model = "Infineon PSOC 62S4 Pioneer Kit"; @@ -34,26 +35,26 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; /* shared */ - gpio-map = <0 0 &gpio_prt10 0 0>, /* A0 */ - <1 0 &gpio_prt10 1 0>, /* A1 */ - <2 0 &gpio_prt10 2 0>, /* A2 */ - <3 0 &gpio_prt10 3 0>, /* A3 */ - <4 0 &gpio_prt10 4 0>, /* A4 */ - <5 0 &gpio_prt10 5 0>, /* A5 */ - <6 0 &gpio_prt0 2 0>, /* D0-RX-5 */ - <7 0 &gpio_prt0 3 0>, /* D1-TX-5 */ - <8 0 &gpio_prt5 0 0>, /* D2-RTS-5 */ - <9 0 &gpio_prt5 1 0>, /* D3-CTS-5 */ - <10 0 &gpio_prt5 6 0>, /* D4 */ - <11 0 &gpio_prt5 7 0>, /* D5 */ - <12 0 &gpio_prt6 2 0>, /* D6 */ - <13 0 &gpio_prt6 3 0>, /* D7 */ - <14 0 &gpio_prt2 4 0>, /* D8-RX-6 */ - <15 0 &gpio_prt2 6 0>, /* D9-TX-6 */ - <16 0 &gpio_prt2 3 0>, /* D10 */ - <17 0 &gpio_prt2 0 0>, /* D11 */ - <18 0 &gpio_prt2 1 0>, /* D12 */ - <19 0 &gpio_prt2 2 0>; /* D13 */ + gpio-map = , + , + , + , + , + , + , /* RX-5 */ + , /* TX-5 */ + , /* RTS-5 */ + , /* CTS-5 */ + , + , + , + , + , /* RX-6 */ + , /* TX-6 */ + , + , + , + ; }; }; diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml index 7d4185c860ec7..292026530011b 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml @@ -26,4 +26,5 @@ supported: - uart - dma - timer + - watchdog vendor: infineon diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts index b398836798019..ad9096784857d 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts @@ -110,7 +110,7 @@ uart2: &scb2 { #address-cells = <1>; #size-cells = <1>; - /* Keep bootstrap_region node to know size, finaly it will + /* Keep bootstrap_region node to know size, finally it will * locate on beginning of code-partition. The BootROM copies * bootstrap application in RAM and launches it. */ diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml index 3244d698080f8..7ec7dd723d7e3 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml @@ -24,5 +24,5 @@ supported: - rtc - dma - pwm - + - watchdog vendor: infineon diff --git a/boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi b/boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi index 557df23766bb5..89ac3f712d56d 100644 --- a/boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi +++ b/boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi @@ -3,34 +3,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio14 0 0>, /* A0 */ - <1 0 &gpio14 1 0>, /* A1 */ - <2 0 &gpio14 2 0>, /* A2 */ - <3 0 &gpio14 3 0>, /* A3 */ - <4 0 &gpio14 4 0>, /* A4 */ - <5 0 &gpio14 5 0>, /* A5 */ - <6 0 &gpio2 15 0>, /* D0 */ - <7 0 &gpio2 14 0>, /* D1 */ - <8 0 &gpio1 0 0>, /* D2 */ - <9 0 &gpio1 1 0>, /* D3 */ - <10 0 &gpio1 8 0>, /* D4 */ - <11 0 &gpio2 12 0>, /* D5 */ - <12 0 &gpio2 11 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio3 10 0>, /* D10 */ - <17 0 &gpio3 8 0>, /* D11 */ - <18 0 &gpio3 7 0>, /* D12 */ - <19 0 &gpio3 9 0>, /* D13 */ - <20 0 &gpio3 15 0>, /* D14 */ - <21 0 &gpio0 13 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/intel/adsp/Kconfig.defconfig b/boards/intel/adsp/Kconfig.defconfig index 8c804c48c7508..3feaea882ca26 100644 --- a/boards/intel/adsp/Kconfig.defconfig +++ b/boards/intel/adsp/Kconfig.defconfig @@ -21,5 +21,7 @@ config MAIN_STACK_SIZE default 4096 if BOARD_INTEL_ADSP_ACE30 default 4096 if BOARD_INTEL_ADSP_ACE30_PTL default 4096 if BOARD_INTEL_ADSP_ACE30_PTL_SIM + default 4096 if BOARD_INTEL_ADSP_ACE30_WCL + default 4096 if BOARD_INTEL_ADSP_ACE30_WCL_SIM endif # BOARD_INTEL_ADSP diff --git a/boards/intel/ish/doc/index.rst b/boards/intel/ish/doc/index.rst index d9c3c179b2376..cfb85cde35579 100644 --- a/boards/intel/ish/doc/index.rst +++ b/boards/intel/ish/doc/index.rst @@ -67,7 +67,7 @@ Run ish_fw.bin on ADL RVP board for Chrome $ /usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --partitions $ reboot -- Go to the ISH firmware direcoty: +- Go to the ISH firmware directory: .. code-block:: console diff --git a/boards/intel/ptl/intel_ptl_h_crb.dts b/boards/intel/ptl/intel_ptl_h_crb.dts index 13a4906c6f940..09c83b2cccb91 100644 --- a/boards/intel/ptl/intel_ptl_h_crb.dts +++ b/boards/intel/ptl/intel_ptl_h_crb.dts @@ -43,3 +43,7 @@ &tco_wdt { status = "okay"; }; + +&pwm0 { + status = "okay"; +}; diff --git a/boards/intel/ptl/intel_ptl_h_crb.yaml b/boards/intel/ptl/intel_ptl_h_crb.yaml index 98e6763401d07..585596c382927 100644 --- a/boards/intel/ptl/intel_ptl_h_crb.yaml +++ b/boards/intel/ptl/intel_ptl_h_crb.yaml @@ -12,6 +12,7 @@ supported: - watchdog - uart - rtc + - pwm testing: ignore_tags: - net diff --git a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst index 7e6a426238aca..6e6c0cde31628 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst +++ b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst @@ -106,7 +106,7 @@ Golden Reference Design ======================= The Golden System Reference Design (GSRD) provides a set of essential hardware -and software system componets that can be used as a starting point for various +and software system components that can be used as a starting point for various custom user designs. The Zephyr support for Cyclone® V SoC Development Kit is based on GSRD hardware. @@ -123,7 +123,7 @@ a Intel® Quartus® project: * soc_system.qsf : Quartus® Prime Settings File * soc_system.qsys : Platform Designer file (contains the SoC system) * soc_system.sopcinfo : SOPC Information file contains details about modules instantiated in the project, parameter names and values. -* soc_system_timing.sdc : Synopsys Desing Constraint FILE. +* soc_system_timing.sdc : Synopsys Design Constraint FILE. * output_files/soc_system.sof : FPGA configuration file. diff --git a/boards/ite/it8xxx2_evb/doc/index.rst b/boards/ite/it8xxx2_evb/doc/index.rst index 751294a77b683..7fe794da52045 100644 --- a/boards/ite/it8xxx2_evb/doc/index.rst +++ b/boards/ite/it8xxx2_evb/doc/index.rst @@ -127,7 +127,7 @@ to the it8xxx2 board flash. #. Using winflash tool flash zephyr.bin into your ITE board. First, click ``Load`` button and select your zephyr.bin file. - Second, click ``run`` to flash the iamge into board. + Second, click ``run`` to flash the image into board. .. figure:: WinFlashTool_P3.jpg :align: center diff --git a/boards/m5stack/m5stack_fire/doc/index.rst b/boards/m5stack/m5stack_fire/doc/index.rst index cf9faa32f1c29..0a5f940cc2fe7 100644 --- a/boards/m5stack/m5stack_fire/doc/index.rst +++ b/boards/m5stack/m5stack_fire/doc/index.rst @@ -45,8 +45,8 @@ of the M5Stack Core2 board. +------------------+------------------------------------------------------------------------+-----------+ | Power Switch | Power on/off button. | supported | +------------------+------------------------------------------------------------------------+-----------+ -| General purpose | Three buttons on the front face of the device accesible using the GPIO | supported | -| buttons | interface. | | +| General purpose | Three buttons on the front face of the device accessible using the | supported | +| buttons | GPIO interface. | | +------------------+------------------------------------------------------------------------+-----------+ | LCD screen | Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) | supported | | | controlled via SPI interface | | diff --git a/boards/makerbase/mks_canable_v20/mks_canable_v20.dts b/boards/makerbase/mks_canable_v20/mks_canable_v20.dts index beb75ca55fd7a..aecf03c838fc6 100644 --- a/boards/makerbase/mks_canable_v20/mks_canable_v20.dts +++ b/boards/makerbase/mks_canable_v20/mks_canable_v20.dts @@ -73,7 +73,7 @@ stm32_lp_tick_source: &lptim1 { zephyr_udc0: &usb { pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; pinctrl-names = "default"; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + clocks = <&rcc STM32_CLOCK(APB1, 23)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; status = "okay"; }; @@ -81,7 +81,7 @@ zephyr_udc0: &usb { &fdcan1 { pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; pinctrl-names = "default"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>, + clocks = <&rcc STM32_CLOCK(APB1, 25)>, <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>; status = "okay"; }; diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml index f0fa9668e557f..a261191604149 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml @@ -8,7 +8,7 @@ toolchain: - zephyr - gnuarmemb supported: - - usb_device + - usbd - ble - watchdog - counter diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml index 04a7c550fed34..a858483a0bf17 100644 --- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml @@ -11,3 +11,4 @@ flash: 256 supported: - gpio - uart + - i2c diff --git a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml index 361df15777756..7c2e100373059 100644 --- a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml +++ b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml @@ -12,5 +12,5 @@ supported: - gpio - i2c - spi - - usb_device + - usbd vendor: mikroe diff --git a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts index ea8b2a592e0a5..5abefad20f1be 100644 --- a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts +++ b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts @@ -25,6 +25,8 @@ red-pwm-led = &red_pwm_led; green-pwm-led = &green_pwm_led; blue-pwm-led = &blue_pwm_led; + + accel0 = &lsm6dsl; }; chosen { @@ -140,7 +142,7 @@ clock-frequency = ; status = "okay"; - lsm6dsl@6a { + lsm6dsl: lsm6dsl@6a { compatible = "st,lsm6dsl"; reg = <0x6a>; }; diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst index 38b730a5f448d..784a695cfa76e 100644 --- a/boards/native/doc/arch_soc.rst +++ b/boards/native/doc/arch_soc.rst @@ -34,7 +34,7 @@ Types of POSIX arch based boards ================================ Today there are two types of POSIX boards: -:ref:`native_sim`, and the :ref:`bsim boards`. +:zephyr:board:`native_sim`, and the :ref:`bsim boards`. While they share the main objectives and principles, the first is intended as a HW agnostic test platform which in some cases utilizes the host OS peripherals, while the second intend to simulate a particular HW platform, @@ -320,8 +320,8 @@ Architecture and design Relationship between Zephyr, the native_sim target and the native simulator -When building targeting Zephyr's :ref:`native_sim` board, we build our embedded SW, -that is, our application, the Zephyr kernel, and any subsystems and drivers we have selected, +When building targeting Zephyr's :zephyr:board:`native_sim` board, we build our embedded +SW, that is, our application, the Zephyr kernel, and any subsystems and drivers we have selected, with the :ref:`POSIX architecture` and the :ref:`inf_clock` SOC layers. The result of this build is a pre-linked elf library, which contains what we can call the @@ -449,9 +449,9 @@ Busy waits ========== Busy waits work thanks to logic provided by the board and native simulator. -This does not need to be the same for all boards, but both :ref:`native_sim` and the -:ref:`nrf*bsim boards` work similarly through the combination of a board specific -:c:func:`arch_busy_wait()` and an special fake HW timer provided by the native simulator. +This does not need to be the same for all boards, but both :zephyr:board:`native_sim` +and the :ref:`nrf*bsim boards` work similarly through the combination of a board +specific :c:func:`arch_busy_wait()` and an special fake HW timer provided by the native simulator. Please check the `native simulator busy wait design documentation `_ diff --git a/boards/native/doc/bsim_boards_design.rst b/boards/native/doc/bsim_boards_design.rst index e09deed2cc07f..3f83099d8c264 100644 --- a/boards/native/doc/bsim_boards_design.rst +++ b/boards/native/doc/bsim_boards_design.rst @@ -60,7 +60,7 @@ These tests are run in workstation, that is, without using real embedded HW. The intention being to be able to run tests much faster than real time, without the need for real HW, and in a deterministic/reproducible fashion. -Unlike :ref:`native_sim `, bsim boards do not interact directly with any host +Unlike :zephyr:board:`native_sim `, bsim boards do not interact directly with any host peripherals, and their execution is independent of the host load, or timing. These boards are also designed to be used as prototyping and development environments, @@ -106,12 +106,12 @@ to these boards. an special driver that handles the EDTT communication (its RPC transport) and an embedded application that handles the RPC calls themselves, while the python test scripts provide the test logic. - - Using Zephyr's :ref:`native_sim ` board: It also allows integration testing of + - Using Zephyr's :zephyr:board:`native_sim ` board: It also allows integration testing of the embedded code, but without any specific HW. In that way, many embedded components which are dependent on the HW would not be suited for testing in that platform. Just like the bsim boards, this Zephyr target board can be used with or without Zephyr's ztest system and twister. - The :ref:`native_sim ` board shares the :ref:`POSIX architecture`, + The :zephyr:board:`native_sim ` board shares the :ref:`POSIX architecture`, and native simulator runner with the bsim boards. - Zephyr's ztest infrastructure and Zephyr's twister: @@ -335,7 +335,7 @@ Instead the equivalent ``bs_tests`` provided hooks should be used. Note also that, for AMP targets like the :ref:`nrf5340bsim `, each embedded MCU has its own separate ``bs_tests`` built with that MCU. You can select if and what test is used -for each MCU separatedly with the command line options. +for each MCU separately with the command line options. Command line argument parsing ============================= diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig index 15950566594f9..33ce032af849e 100644 --- a/boards/native/native_sim/Kconfig +++ b/boards/native/native_sim/Kconfig @@ -14,7 +14,7 @@ config BOARD_NATIVE_SIM if BOARD_NATIVE_SIM -comment "Native Simular (Single Core) options" +comment "Native Simulator (Single Core) options" config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME bool "Slow down execution to real time" diff --git a/boards/native/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst index d7b6cea697a14..2e2eb74ee67b4 100644 --- a/boards/native/native_sim/doc/index.rst +++ b/boards/native/native_sim/doc/index.rst @@ -1,12 +1,4 @@ -.. _native_sim: - -native_sim -########## - -.. contents:: - :depth: 1 - :backlinks: entry - :local: +.. zephyr:board:: native_sim Overview ******** @@ -293,7 +285,9 @@ All times are kept in microseconds. Peripherals *********** -The following peripherals are currently provided with this board: +.. zephyr:board-supported-hw:: + +Here are more details on the peripherals that are currently provided with this board: **Interrupt controller** A simple yet generic interrupt controller is provided. It can nest interrupts @@ -721,6 +715,7 @@ host libC (:kconfig:option:`CONFIG_EXTERNAL_LIBC`): FUSE, :ref:`Host based filesystem access `, :kconfig:option:`CONFIG_FUSE_FS_ACCESS`, All GPIO, GPIO emulator, :kconfig:option:`CONFIG_GPIO_EMUL`, All GPIO, SDL GPIO emulator, :kconfig:option:`CONFIG_GPIO_EMUL_SDL`, All + HWINFO, :kconfig:option:`CONFIG_HWINFO_NATIVE`, All I2C, I2C emulator, :kconfig:option:`CONFIG_I2C_EMUL`, All Input, Input SDL touch, :kconfig:option:`CONFIG_INPUT_SDL_TOUCH`, All Input, Linux evdev, :kconfig:option:`CONFIG_NATIVE_LINUX_EVDEV`, All diff --git a/boards/native/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts index 4ab4ef76f4150..58730877aac2c 100644 --- a/boards/native/native_sim/native_sim.dts +++ b/boards/native/native_sim/native_sim.dts @@ -236,4 +236,22 @@ compatible = "zephyr,bt-hci-userchan"; status = "okay"; }; + + performance-states { + pstate_0: pstate_0 { + compatible = "zephyr,native-sim-pstate"; + load-threshold = <50>; + pstate-id = <0>; + }; + pstate_1: pstate_1 { + compatible = "zephyr,native-sim-pstate"; + load-threshold = <20>; + pstate-id = <1>; + }; + pstate_2: pstate_2 { + compatible = "zephyr,native-sim-pstate"; + load-threshold = <0>; + pstate-id = <2>; + }; + }; }; diff --git a/boards/native/native_sim/native_sim.yaml b/boards/native/native_sim/native_sim.yaml index 8a476ba2771a2..2e16e91981bd8 100644 --- a/boards/native/native_sim/native_sim.yaml +++ b/boards/native/native_sim/native_sim.yaml @@ -23,6 +23,7 @@ supported: - spi - gpio - rtc + - hwinfo testing: default: true vendor: zephyr diff --git a/boards/native/native_sim/native_sim_native_64.yaml b/boards/native/native_sim/native_sim_native_64.yaml index 24a4bb082ea8a..4656497412ff3 100644 --- a/boards/native/native_sim/native_sim_native_64.yaml +++ b/boards/native/native_sim/native_sim_native_64.yaml @@ -20,4 +20,5 @@ supported: - adc - gpio - rtc + - hwinfo vendor: zephyr diff --git a/boards/native/nrf_bsim/doc/nrf5340bsim.rst b/boards/native/nrf_bsim/doc/nrf5340bsim.rst index 7e252511f3388..1068646c59874 100644 --- a/boards/native/nrf_bsim/doc/nrf5340bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf5340bsim.rst @@ -115,7 +115,7 @@ ARM's TrustZone is not modelled in these boards. This means that: * There is no differentiation between secure and non secure execution states or bus accesses. * All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their own interconnect master ports can, in principle, access any other peripheral or RAM area. -* There is no nrf5340bsim/nrf5340/cpuapp/ns board/build target, or posibility of mixing secure +* There is no nrf5340bsim/nrf5340/cpuapp/ns board/build target, or possibility of mixing secure and non-secure images. * Currently there is no model of the SPU, and therefore neither flash, RAM areas or peripherals can be labelled as restricted for secure or non secure access. diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts index 5b9f2f5682584..7368127a72a6b 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts @@ -8,6 +8,7 @@ /dts-v1/; #include #include "nrf21540dk_nrf52840-pinctrl.dtsi" +#include #include / { @@ -91,28 +92,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts index 0ef9d46809bc6..d7f5b3ba0b927 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "nrf52833dk_nrf52833-pinctrl.dtsi" +#include #include / { @@ -90,28 +91,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio0 17 0>, /* D8 */ - <15 0 &gpio0 19 0>, /* D9 */ - <16 0 &gpio0 20 0>, /* D10 */ - <17 0 &gpio0 21 0>, /* D11 */ - <18 0 &gpio0 22 0>, /* D12 */ - <19 0 &gpio0 23 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; /* These aliases are provided for compatibility with samples */ diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts index 753fbca029f9f..6ceead2d589db 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts @@ -8,6 +8,7 @@ #include #include #include "nrf52840dk_nrf52840-pinctrl.dtsi" +#include #include / { @@ -89,28 +90,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml index 7eb89aa894b48..d12aca5fc52f7 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml @@ -9,7 +9,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - pwm - spi diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.yaml b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.yaml index 516cd385264e9..7ab56a99e46bd 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.yaml +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.yaml @@ -9,7 +9,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - pwm - spi diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts index 3a3029550e9eb..2f7a08013580e 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts @@ -8,6 +8,7 @@ /dts-v1/; #include #include "nrf52dk_nrf52832-pinctrl.dtsi" +#include #include / { @@ -90,28 +91,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio0 11 0>, /* D0 */ - <7 0 &gpio0 12 0>, /* D1 */ - <8 0 &gpio0 13 0>, /* D2 */ - <9 0 &gpio0 14 0>, /* D3 */ - <10 0 &gpio0 15 0>, /* D4 */ - <11 0 &gpio0 16 0>, /* D5 */ - <12 0 &gpio0 17 0>, /* D6 */ - <13 0 &gpio0 18 0>, /* D7 */ - <14 0 &gpio0 19 0>, /* D8 */ - <15 0 &gpio0 20 0>, /* D9 */ - <16 0 &gpio0 22 0>, /* D10 */ - <17 0 &gpio0 23 0>, /* D11 */ - <18 0 &gpio0 24 0>, /* D12 */ - <19 0 &gpio0 25 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts index be8718003320f..8891612a9b57a 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts @@ -24,3 +24,6 @@ &uicr { nfct-pins-as-gpios; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi index 5c2b1545e265a..fadd2188f04ad 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi @@ -263,6 +263,4 @@ zephyr_udc0: &usbd { }; }; -/* Include default memory partition configuration file */ -#include #include "nrf5340_audio_dk_nrf5340_shared.dtsi" diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts index 19e2231ba7e9f..8b906eb1c9a23 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts @@ -18,3 +18,6 @@ zephyr,code-partition = &slot0_ns_partition; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi index aff29f4e9d3f2..9e50873e4cc77 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi @@ -1,3 +1,4 @@ +#include #include / { @@ -89,28 +90,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 9 0>, /* D0 */ - <7 0 &gpio1 8 0>, /* D1 */ - <8 0 &gpio0 31 0>, /* D2 */ - <9 0 &gpio1 0 0>, /* D3 */ - <10 0 &gpio1 1 0>, /* D4 */ - <11 0 &gpio1 14 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 11 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 13 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio0 9 0>, /* D11 */ - <18 0 &gpio0 10 0>, /* D12 */ - <19 0 &gpio0 8 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; aliases { diff --git a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi index 8af1da7ae1cf7..f0bc677c294c0 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi @@ -170,6 +170,3 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; - -/* Include default memory partition configuration file */ -#include diff --git a/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi index 77611791afc34..9e2765382d4fe 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { leds { compatible = "gpio-leds"; @@ -62,28 +64,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; /* These aliases are provided for compatibility with samples */ diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts index c459033b46ac9..7c14fabd114ea 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Nordic Semiconductor ASA + * Copyright (c) 2020-2025 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,3 +31,6 @@ reg = <0x0 0x1>; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts index bf295aecc3a5d..dbd4a770be3dc 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Nordic Semiconductor ASA + * Copyright (c) 2020-2025 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,3 +18,6 @@ zephyr,code-partition = &slot0_ns_partition; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi index f31d909b6f94a..f7e7d63d548de 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi @@ -32,6 +32,7 @@ cpuapp_cpusys_ipc: ipc-2-12 { compatible = "zephyr,ipc-icmsg"; + unbound = "enable"; status = "disabled"; dcache-alignment = <32>; mboxes = <&cpuapp_bellboard 6>, @@ -56,6 +57,7 @@ cpurad_cpusys_ipc: ipc-3-12 { compatible = "zephyr,ipc-icmsg"; + unbound = "enable"; status = "disabled"; dcache-alignment = <32>; mboxes = <&cpurad_bellboard 6>, diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index b6a53955c60e3..e14426c59fc85 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -166,5 +166,13 @@ periphconf_partition: partition@1ae000 { reg = <0x1ae000 DT_SIZE_K(8)>; }; + + secondary_partition: partition@1b0000 { + reg = <0x1b0000 DT_SIZE_K(64)>; + }; + + secondary_periphconf_partition: partition@1c0000 { + reg = <0x1c0000 DT_SIZE_K(8)>; + }; }; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 9d99754c3c0fe..ba22403a9acd2 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -279,6 +279,13 @@ slot3_partition: &cpurad_slot1_partition { 30 b0 30 b0 f4 bd d5 5c 00 00 00 ff 10 10 00 20 00 00 00 00 00 00 7c 23 48 00 00 00 00 00 88 88 ]; + sfdp-ff05 = [ + 00 ee c0 69 72 72 71 71 00 d8 f7 f6 00 0a 00 00 + 14 45 98 80 + ]; + sfdp-ff84 = [ + 43 06 0f 00 21 dc ff ff + ]; size = <67108864>; has-dpd; t-enter-dpd = <10000>; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi b/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi index 6740544b524a4..c030c2c551891 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi @@ -108,9 +108,5 @@ pinctrl-names = "default", "sleep"; }; -&hfxo { - startup-time-us = <854>; -}; - /* Get a node label for wi-fi spi to use in shield files */ wifi_spi: &spi22 {}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts index cd644d845d5e5..cfb02b6817a5e 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts @@ -31,8 +31,8 @@ / { /* * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support. - * - Lowest 96 kB SRAM allocated to Secure image (sram0_s). - * - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns). + * - Lowest 72 kB SRAM allocated to Secure image (sram0_s). + * - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns). * * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for * the FLPR MCU. @@ -58,14 +58,11 @@ }; &cpuapp_rram { - /* TODO: revert this hack when TF-M update is available that fixes partition sizes */ - reg = <0x0 DT_SIZE_K(1022)>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - /* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the + /* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the * last 62kB are reserved for the FLPR MCU. * * This static layout needs to be the same with the upstream TF-M layout in the @@ -94,12 +91,12 @@ slot0_ns_partition: partition@6A000 { label = "image-0-nonsecure"; - reg = <0x0006A000 DT_SIZE_K(504)>; + reg = <0x0006A000 DT_SIZE_K(494)>; }; - storage_partition: partition@E8000 { + storage_partition: partition@E5800 { label = "storage"; - reg = <0x000E8000 DT_SIZE_K(32)>; + reg = <0x000E5800 DT_SIZE_K(32)>; }; }; }; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml index 9f42daedf4e35..22fbcbc32c3c4 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml @@ -9,7 +9,7 @@ toolchain: - gnuarmemb - zephyr ram: 192 -flash: 1022 +flash: 1012 supported: - adc - gpio diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.yaml index 927773e0d5ac5..2bc2cde2c7230 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.yaml +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.yaml @@ -15,4 +15,3 @@ supported: - gpio - i2c - spi - - watchdog diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.yaml index d82dea6491fd9..67a9c9b526aba 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.yaml +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr_xip.yaml @@ -15,4 +15,3 @@ supported: - gpio - i2c - spi - - watchdog diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.yaml b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.yaml index 765845fa27f06..e5a2b89087de7 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.yaml +++ b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.yaml @@ -20,4 +20,5 @@ supported: - i2s - pwm - spi + - usbd - watchdog diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi index 70d2639e75c73..07281e3bcdff3 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "nrf5340_cpuapp_common_pinctrl.dtsi" +#include #include / { @@ -61,28 +62,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { @@ -244,6 +245,3 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; - -/* Include default memory partition configuration file */ -#include diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts index 9b62eafea174b..c991ffb1edee0 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts @@ -35,3 +35,6 @@ #include "nrf70_common_5g.dtsi" }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts index 8d955c67fc72c..ffcf9d34d4611 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts @@ -34,3 +34,6 @@ #include "nrf70_common.dtsi" }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts index 61cae0bb7ce9e..feaa3ca91d14e 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "nrf7002dk_nrf5340_cpunet_pinctrl.dtsi" +#include #include / { @@ -62,28 +63,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; nrf_radio_coex: coex { diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi index 209608d840da6..e65e3215bc421 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "nrf9151dk_nrf9151_common-pinctrl.dtsi" +#include #include / { @@ -87,28 +88,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 14 0>, /* A0 */ - <1 0 &gpio0 15 0>, /* A1 */ - <2 0 &gpio0 16 0>, /* A2 */ - <3 0 &gpio0 17 0>, /* A3 */ - <4 0 &gpio0 18 0>, /* A4 */ - <5 0 &gpio0 19 0>, /* A5 */ - <6 0 &gpio0 0 0>, /* D0 */ - <7 0 &gpio0 1 0>, /* D1 */ - <8 0 &gpio0 2 0>, /* D2 */ - <9 0 &gpio0 3 0>, /* D3 */ - <10 0 &gpio0 4 0>, /* D4 */ - <11 0 &gpio0 5 0>, /* D5 */ - <12 0 &gpio0 6 0>, /* D6 */ - <13 0 &gpio0 7 0>, /* D7 */ - <14 0 &gpio0 8 0>, /* D8 */ - <15 0 &gpio0 9 0>, /* D9 */ - <16 0 &gpio0 10 0>, /* D10 */ - <17 0 &gpio0 11 0>, /* D11 */ - <18 0 &gpio0 12 0>, /* D12 */ - <19 0 &gpio0 13 0>, /* D13 */ - <20 0 &gpio0 30 0>, /* D14 */ - <21 0 &gpio0 31 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi index 235613449734d..d7b5612f2922a 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "nrf9160dk_nrf9160_common-pinctrl.dtsi" +#include #include / { @@ -114,28 +115,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 14 0>, /* A0 */ - <1 0 &gpio0 15 0>, /* A1 */ - <2 0 &gpio0 16 0>, /* A2 */ - <3 0 &gpio0 17 0>, /* A3 */ - <4 0 &gpio0 18 0>, /* A4 */ - <5 0 &gpio0 19 0>, /* A5 */ - <6 0 &gpio0 0 0>, /* D0 */ - <7 0 &gpio0 1 0>, /* D1 */ - <8 0 &gpio0 2 0>, /* D2 */ - <9 0 &gpio0 3 0>, /* D3 */ - <10 0 &gpio0 4 0>, /* D4 */ - <11 0 &gpio0 5 0>, /* D5 */ - <12 0 &gpio0 6 0>, /* D6 */ - <13 0 &gpio0 7 0>, /* D7 */ - <14 0 &gpio0 8 0>, /* D8 */ - <15 0 &gpio0 9 0>, /* D9 */ - <16 0 &gpio0 10 0>, /* D10 */ - <17 0 &gpio0 11 0>, /* D11 */ - <18 0 &gpio0 12 0>, /* D12 */ - <19 0 &gpio0 13 0>, /* D13 */ - <20 0 &gpio0 30 0>, /* D14 */ - <21 0 &gpio0 31 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts index b4237bb57fb83..1bac60d26622e 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts @@ -11,7 +11,7 @@ / { chosen { zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; + zephyr,sram = &sram0_ns_app; zephyr,code-partition = &slot0_ns_partition; }; }; diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi index a17a19c295bd0..5948a31c6db88 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "nrf9161dk_nrf9161_common-pinctrl.dtsi" +#include #include / { @@ -87,28 +88,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 14 0>, /* A0 */ - <1 0 &gpio0 15 0>, /* A1 */ - <2 0 &gpio0 16 0>, /* A2 */ - <3 0 &gpio0 17 0>, /* A3 */ - <4 0 &gpio0 18 0>, /* A4 */ - <5 0 &gpio0 19 0>, /* A5 */ - <6 0 &gpio0 0 0>, /* D0 */ - <7 0 &gpio0 1 0>, /* D1 */ - <8 0 &gpio0 2 0>, /* D2 */ - <9 0 &gpio0 3 0>, /* D3 */ - <10 0 &gpio0 4 0>, /* D4 */ - <11 0 &gpio0 5 0>, /* D5 */ - <12 0 &gpio0 6 0>, /* D6 */ - <13 0 &gpio0 7 0>, /* D7 */ - <14 0 &gpio0 8 0>, /* D8 */ - <15 0 &gpio0 9 0>, /* D9 */ - <16 0 &gpio0 10 0>, /* D10 */ - <17 0 &gpio0 11 0>, /* D11 */ - <18 0 &gpio0 12 0>, /* D12 */ - <19 0 &gpio0 13 0>, /* D13 */ - <20 0 &gpio0 30 0>, /* D14 */ - <21 0 &gpio0 31 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/nordic/nrf9280pdk/board.yml b/boards/nordic/nrf9280pdk/board.yml index 2cce133d95c36..274b9a84a7b7c 100644 --- a/boards/nordic/nrf9280pdk/board.yml +++ b/boards/nordic/nrf9280pdk/board.yml @@ -9,3 +9,10 @@ board: cpucluster: cpuppr - name: iron cpucluster: cpuapp + revision: + format: major.minor.patch + default: 0.2.0 + exact: false + revisions: + - name: 0.1.0 + - name: 0.2.0 diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi new file mode 100644 index 0000000000000..41ca41e073e47 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart135_default: uart135_default { + group1 { + psels = , + ; + }; + + group3 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart135_sleep: uart135_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; + + /omit-if-no-ref/ uart136_default: uart136_default { + group1 { + psels = , + ; + }; + + group3 { + bias-pull-up; + psels = , + ; + }; + }; + + /omit-if-no-ref/ uart136_sleep: uart136_sleep { + group1 { + low-power-enable; + psels = , + , + , + ; + }; + }; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts index f4cce12f4b1a0..622fc04e96af0 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts @@ -24,7 +24,6 @@ zephyr,flash = &mram1x; zephyr,sram = &cpuapp_data; zephyr,shell-uart = &uart136; - zephyr,ieee802154 = &cpuapp_ieee802154; zephyr,bt-hci = &bt_hci_ipc0; nordic,802154-spinel-ipc = &ipc0; }; @@ -260,6 +259,13 @@ ipc0: &cpuapp_cpurad_ipc { 30 b0 30 b0 f4 bd d5 5c 00 00 00 ff 10 10 00 20 00 00 00 00 00 00 7c 23 48 00 00 00 00 00 88 88 ]; + sfdp-ff05 = [ + 00 ee c0 69 72 72 71 71 00 d8 f7 f6 00 0a 00 00 + 14 45 98 80 + ]; + sfdp-ff84 = [ + 43 06 0f 00 21 dc ff ff + ]; size = <67108864>; has-dpd; t-enter-dpd = <10000>; @@ -278,10 +284,6 @@ ipc0: &cpuapp_cpurad_ipc { }; }; -&cpuapp_ieee802154 { - status = "okay"; -}; - zephyr_udc0: &usbhs { status = "okay"; }; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_0_2_0.overlay b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_0_2_0.overlay new file mode 100644 index 0000000000000..4fa3f667eadda --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_0_2_0.overlay @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi" + +/ { + aliases { + pwm-led0 = &pwm_led2; /* Alias for compatibility with samples that use pwm-led0 */ + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + /delete-node/ pwm_led_0; + + /* + * There is no valid hardware configuration to pass PWM signal on pins 0 and 1. + * First valid config is P9.2. This corresponds to LED 2. + * Signal on PWM130's channel 0 can be passed directly on GPIO Port 9 pin 2. + */ + pwm_led2: pwm_led_2 { + pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; +}; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_0_2_0.overlay b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_0_2_0.overlay new file mode 100644 index 0000000000000..f2d986e6cb065 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_0_2_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi" diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_0_2_0.overlay b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_0_2_0.overlay new file mode 100644 index 0000000000000..f2d986e6cb065 --- /dev/null +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_0_2_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi" diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi index 545c3147b1fc3..fabd5d177a99e 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi @@ -325,6 +325,3 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; - -/* Include default memory partition configuration file */ -#include diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts index 9f3d7d46674c2..6310c27be2199 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts @@ -42,3 +42,6 @@ load-capacitors = "internal"; load-capacitance-picofarad = <7>; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml index 568512216bdfb..ea3c467ee0dea 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml @@ -13,6 +13,6 @@ supported: - i2c - pwm - watchdog - - usb_device + - usbd - netif:openthread vendor: nordic diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts index 8a754664325ba..fee8c98c10b28 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts @@ -40,3 +40,6 @@ load-capacitors = "internal"; load-capacitance-picofarad = <7>; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml index e672b5080c4b0..8d1b8e4c677c9 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml @@ -12,7 +12,7 @@ supported: - i2c - pwm - watchdog - - usb_device + - usbd - netif:openthread vendor: nordic sysbuild: true diff --git a/boards/nuvoton/numaker_m5531/Kconfig.defconfig b/boards/nuvoton/numaker_m5531/Kconfig.defconfig new file mode 100644 index 0000000000000..e1011f144c4d5 --- /dev/null +++ b/boards/nuvoton/numaker_m5531/Kconfig.defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton NuMaker M5531 board configuration +# +# Copyright (c) 2025 Nuvoton Technology Corporation. + +if BOARD_NUMAKER_M5531 + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_NUMAKER_M5531 diff --git a/boards/nuvoton/numaker_m5531/Kconfig.numaker_m5531 b/boards/nuvoton/numaker_m5531/Kconfig.numaker_m5531 new file mode 100644 index 0000000000000..c23d635152a78 --- /dev/null +++ b/boards/nuvoton/numaker_m5531/Kconfig.numaker_m5531 @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton NuMaker M5531 board configuration +# +# Copyright (c) 2025 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_M5531 + select SOC_M55M1XXX diff --git a/boards/nuvoton/numaker_m5531/board.cmake b/boards/nuvoton/numaker_m5531/board.cmake new file mode 100644 index 0000000000000..834a265466e1b --- /dev/null +++ b/boards/nuvoton/numaker_m5531/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=m55m1h2ljae") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/nuvoton/numaker_m5531/board.yml b/boards/nuvoton/numaker_m5531/board.yml new file mode 100644 index 0000000000000..d9cfd9a27c324 --- /dev/null +++ b/boards/nuvoton/numaker_m5531/board.yml @@ -0,0 +1,6 @@ +board: + name: numaker_m5531 + full_name: NUMAKER M5531 + vendor: nuvoton + socs: + - name: m55m1xxx diff --git a/boards/nuvoton/numaker_m5531/doc/index.rst b/boards/nuvoton/numaker_m5531/doc/index.rst new file mode 100644 index 0000000000000..5a5cf0303420d --- /dev/null +++ b/boards/nuvoton/numaker_m5531/doc/index.rst @@ -0,0 +1,78 @@ +.. zephyr:board:: numaker_m5531 + +Overview +******** + +The NuMaker M5531 is an Internet of Things (IoT) application focused platform +specially developed by Nuvoton. The NuMaker-M5531 is based on the NuMicro® M5531 +series MCU with ARM® -Cortex®-M55 core. + +Features +======== +- 32-bit Arm Cortex®-M55 M5531H2LJAE MCU +- Core clock up to 220 MHz +- 2 MB embedded Dual Bank Flash and 1344 KB SRAM +- 128 KB DTCM and 64 KB ITCM +- USB 2.0 Full-Speed OTG / Device +- USB 1.1 Host +- Arduino UNO compatible interface +- One push-button is for reset +- Two LEDs: one is for power indication and the other is for user-defined +- On-board NU-Link2 ICE debugger/programmer with SWD connector + +More information about the board can be found at the `NuMaker M5531 User Manual`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 220 MHz. + +More details about the supported peripherals are available in `M5531 TRM`_ + +Building and Flashing +********************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb, +To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. +Connect the NuMaker-M5531 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_m5531 + :goals: flash + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_m5531 + :goals: debug + +Step through the application in your debugger. + +References +********** + +.. target-notes:: + +.. _NuMaker M5531 User Manual: + https://www.nuvoton.com/products/microcontrollers/arm-cortex-m55-mcus/m5531-series/ +.. _M5531 TRM: + https://www.nuvoton.com/products/microcontrollers/arm-cortex-m55-mcus/m5531-series/ diff --git a/boards/nuvoton/numaker_m5531/doc/m5531.webp b/boards/nuvoton/numaker_m5531/doc/m5531.webp new file mode 100644 index 0000000000000..9978d0f6e7e0a Binary files /dev/null and b/boards/nuvoton/numaker_m5531/doc/m5531.webp differ diff --git a/boards/nuvoton/numaker_m5531/numaker_m5531-pinctrl.dtsi b/boards/nuvoton/numaker_m5531/numaker_m5531-pinctrl.dtsi new file mode 100644 index 0000000000000..6e76b0f6a231c --- /dev/null +++ b/boards/nuvoton/numaker_m5531/numaker_m5531-pinctrl.dtsi @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "pinctrl/m55m1h2l-pinctrl.h" + +&pinctrl { + uart0_default: uart0_default { + group0 { + pinmux = , + ; + }; + }; + + /* TX/RX/RTS/CTS/RST --> D1/D0/A2/A3/D2 --> PB3/PB2/PB8/PB9/PC9 */ + uart1_default: uart1_default { + group0 { + pinmux = , + , + , + , + ; + }; + }; + + /* USBD multi-function pins for VBUS, D+, D-, and ID pins */ + usbd_default: usbd_default { + group0 { + pinmux = , + , + , + ; + }; + }; +}; diff --git a/boards/nuvoton/numaker_m5531/numaker_m5531.dts b/boards/nuvoton/numaker_m5531/numaker_m5531.dts new file mode 100644 index 0000000000000..9c6bcccdd85da --- /dev/null +++ b/boards/nuvoton/numaker_m5531/numaker_m5531.dts @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "numaker_m5531-pinctrl.dtsi" +#include + +/ { + model = "Nuvoton NuMaker M5531 board"; + compatible = "nuvoton,numaker-m5531"; + + aliases { + led0 = &green_led; + led1 = &yellow_led; + sw0 = &btn0; + sw1 = &btn1; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &canfd0; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led_0 { + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + label = "User LD0"; + }; + + yellow_led: led_1 { + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + label = "User LD1"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + btn0: btn0 { + label = "BTN0"; + gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn1: btn1 { + label = "BTN1"; + gpios = <&gpioh 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&gpiod { + status = "okay"; +}; + +&gpioh { + status = "okay"; +}; + +&gpioi { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x8000>; + }; + + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x8000 0xf8000>; + }; + + slot1_partition: partition@100000 { + label = "image-1"; + reg = <0x100000 0xf8000>; + }; + + storage_partition: partition@1f8000 { + label = "storage"; + reg = <0x1f8000 0x8000>; + }; + }; +}; + +&sram0 { + reg = <0x20100000 DT_SIZE_K(1344)>; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* On enabled, usbd is required to be clocked in 48MHz. */ +zephyr_udc0: &usbd { + pinctrl-0 = <&usbd_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nuvoton/numaker_m5531/numaker_m5531.yaml b/boards/nuvoton/numaker_m5531/numaker_m5531.yaml new file mode 100644 index 0000000000000..bb83ec2dc1cf6 --- /dev/null +++ b/boards/nuvoton/numaker_m5531/numaker_m5531.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +identifier: numaker_m5531 +name: NUVOTON NUMAKER-M5531 Kit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 1536 +flash: 2048 +supported: + - gpio +vendor: nuvoton diff --git a/boards/nuvoton/numaker_m5531/numaker_m5531_defconfig b/boards/nuvoton/numaker_m5531/numaker_m5531_defconfig new file mode 100644 index 0000000000000..903b011703251 --- /dev/null +++ b/boards/nuvoton/numaker_m5531/numaker_m5531_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +# Enable system clock controller driver +CONFIG_CLOCK_CONTROL=y +CONFIG_CLOCK_CONTROL_NUMAKER_SCC=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/numaker_m5531/support/openocd.cfg b/boards/nuvoton/numaker_m5531/support/openocd.cfg new file mode 100644 index 0000000000000..c393f756c4def --- /dev/null +++ b/boards/nuvoton/numaker_m5531/support/openocd.cfg @@ -0,0 +1,2 @@ +source [find interface/nulink.cfg] +source [find target/numicro.cfg] diff --git a/boards/nxp/frdm_imx93/Kconfig.defconfig b/boards/nxp/frdm_imx93/Kconfig.defconfig new file mode 100644 index 0000000000000..fb6693be0a184 --- /dev/null +++ b/boards/nxp/frdm_imx93/Kconfig.defconfig @@ -0,0 +1,63 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_IMX93 + +if BOARD_FRDM_IMX93_MIMX9352_A55 + +if GPIO + +# CAN Phy must be initialized after board mux +config I2C + default y + +endif # GPIO + +if CAN + +# CAN Phy must be initialized after board mux +config GPIO_PCA_SERIES_INIT_PRIORITY + default 60 + +config CAN_TRANSCEIVER_INIT_PRIORITY + default 65 + +endif # CAN + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +if NET_SOCKETS_SERVICE + +config NET_SOCKETS_SERVICE_STACK_SIZE + default 8192 + +endif # NET_SOCKETS_SERVICE + +endif # NETWORKING + +endif # BOARD_FRDM_IMX93_MIMX9352_A55 + +endif # BOARD_FRDM_IMX93 diff --git a/boards/nxp/frdm_imx93/Kconfig.frdm_imx93 b/boards/nxp/frdm_imx93/Kconfig.frdm_imx93 new file mode 100644 index 0000000000000..b38a5c5195ab0 --- /dev/null +++ b/boards/nxp/frdm_imx93/Kconfig.frdm_imx93 @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_IMX93 + select SOC_MIMX9352_A55 if BOARD_FRDM_IMX93_MIMX9352_A55 + select SOC_PART_NUMBER_MIMX9352DVVXM diff --git a/boards/nxp/frdm_imx93/board.yml b/boards/nxp/frdm_imx93/board.yml new file mode 100644 index 0000000000000..5be8992b93091 --- /dev/null +++ b/boards/nxp/frdm_imx93/board.yml @@ -0,0 +1,6 @@ +board: + name: frdm_imx93 + full_name: FRDM-IMX93 + vendor: nxp + socs: + - name: mimx9352 diff --git a/boards/nxp/frdm_imx93/doc/frdm_imx93.webp b/boards/nxp/frdm_imx93/doc/frdm_imx93.webp new file mode 100644 index 0000000000000..7f4bed35f98a4 Binary files /dev/null and b/boards/nxp/frdm_imx93/doc/frdm_imx93.webp differ diff --git a/boards/nxp/frdm_imx93/doc/index.rst b/boards/nxp/frdm_imx93/doc/index.rst new file mode 100644 index 0000000000000..ff4a26eabe6dc --- /dev/null +++ b/boards/nxp/frdm_imx93/doc/index.rst @@ -0,0 +1,164 @@ +.. zephyr:board:: frdm_imx93 + +Overview +******** + +The FRDM-IMX93 board is a low-cost and compact platform designed to show +the most commonly used features of the i.MX 93 Applications Processor in a +small and low cost package. The FRDM-IMX93 board is an entry-level development +board, which helps developers to get familiar with the processor before +investing a large amount of resources in more specific designs. + +i.MX93 MPU is composed of one cluster of 2x Cortex®-A55 cores and a single +Cortex®-M33 core. Zephyr RTOS is ported on Cortex®-A55 core. + +Hardware +******** + +- i.MX 93 applications processor + + - The processor integrates up to two Arm Cortex-A55 cores, and supports + built-in Arm Cortex-M33 core. + +- RAM: 2GB LPDDR4 +- Storage: + + - SanDisk 16GB eMMC5.1 + - microSD Socket +- Wireless: + + - Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, + which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, + and 802.15.4 +- USB: + + - One USB 2.0 Type C connector + - One USB 2.0 Type A connector +- Ethernet +- PCI-E M.2 +- Connectors: + + - 40-Pin Dual Row Header +- LEDs: + + - 1x Power status LED + - 1x RGB LED +- Debug + + - JTAG 3-pin connector + - USB-C port for UART debug, two COM ports for A55 and M33 + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A55 Core runs up to 1.7 GHz. +Cortex-M33 Core runs up to 200MHz in which SYSTICK runs on same frequency. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART2 for A55 core and M33 core. + +User Button GPIO Option +-------------------------- + +The user buttons USER_BTN1 and USER_BTN2 are connected to onboard GPIO expander +PCAL6524 by default, but can be changed to connect to FRDM-IMX93 GPIO. A devicetree +overlay is included to support this. + +Run following command to test user buttons connected to FRDM-IMX93 GPIO: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :host-os: unix + :board: frdm_imx93/mimx9352/a55 + :goals: build + :gen-args: -DEXTRA_DTC_OVERLAY_FILE=frdm_imx93_mimx9352_native_btn.overlay + +Note: The overlay only supports ``mimx9352/a55``, but can be extended to support +``mimx9352/m33`` if I2C and PCAL6524 is enabled. + +Programming and Debugging (A55) +******************************* + +U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently +it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, +xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example +"uboot_v2023.04-2.9.0" branch is U-Boot v2023.04 used in Real-Time Edge Software release +v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Software`_. + +.. _Real-Time Edge U-Boot: + https://github.com/nxp-real-time-edge-sw/real-time-edge-uboot +.. _Real-Time Edge Software: + https://www.nxp.com/rtedge + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000 + + +Or use the following command to kick zephyr.bin to Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache off; icache flush; go 0xd0000000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: frdm_imx93/mimx9352/a55 + :goals: build + +This will build an image with the synchronization sample app, boot it and +display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-41-g6395333e3d18 *** + thread_a: Hello World from cpu 0 on frdm_imx93! + thread_b: Hello World from cpu 0 on frdm_imx93! + thread_a: Hello World from cpu 0 on frdm_imx93! + thread_b: Hello World from cpu 0 on frdm_imx93! + +System Reboot (A55) +=================== + +Currently i.MX93 only support cold reboot and doesn't support warm reboot. +Use this configuratiuon to verify cold reboot with :zephyr:code-sample:`shell-module` +sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :host-os: unix + :board: frdm_imx93/mimx9352/a55 + :goals: build + +This will build an image with the shell sample app, boot it and execute +kernel reboot command in shell command line: + +.. code-block:: console + + uart:~$ kernel reboot cold + +.. include:: ../../common/board-footer.rst + :start-after: nxp-board-footer diff --git a/boards/nxp/frdm_imx93/dts/frdm_imx93_mimx9352_native_btn.overlay b/boards/nxp/frdm_imx93/dts/frdm_imx93_mimx9352_native_btn.overlay new file mode 100644 index 0000000000000..3ace231edfbfd --- /dev/null +++ b/boards/nxp/frdm_imx93/dts/frdm_imx93_mimx9352_native_btn.overlay @@ -0,0 +1,35 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * Apply this overlay to test USER_BTN1 and USER_BTN2 on PCAL6524. + * + * The user buttons USER_BTN1 and USER_BTN2 is connected to onboard GPIO expander PCAL6524 + * by default, but can be changed to connect to FRDM-IMX93 GPIO. To do this, remove R2608 + * and R2610, populate R2611 and R2612. + */ + +/* Remove default keys */ +/delete-node/ &btn_1; +/delete-node/ &btn_2; + +/ { + keys { + compatible = "gpio-keys"; + + btn_1: btn_1 { + label = "BTN1"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn_2: btn_2 { + label = "BTN2"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; diff --git a/boards/nxp/frdm_imx93/frdm_imx93-pinctrl.dtsi b/boards/nxp/frdm_imx93/frdm_imx93-pinctrl.dtsi new file mode 100644 index 0000000000000..08e85ca05660d --- /dev/null +++ b/boards/nxp/frdm_imx93/frdm_imx93-pinctrl.dtsi @@ -0,0 +1,130 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include + +&pinctrl { + uart1_default: uart1_default { + group0 { + pinmux = <&iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx>, + <&iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>, + <&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; + + i2c1_default: i2c1_default { + group0 { + pinmux = <&iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl>, + <&iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda>; + drive-strength = "x5"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + i2c2_default: i2c2_default { + group0 { + pinmux = <&iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl>, + <&iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda>; + drive-strength = "x5"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + i2c3_default: i2c3_default { + group0 { + pinmux = <&iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl>, + <&iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda>; + drive-strength = "x5"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + i2c4_default: i2c4_default { + group0 { + pinmux = <&iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl>, + <&iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda>; + drive-strength = "x5"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + spi3_default: spi3_default { + group0 { + pinmux = <&iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1>, + <&iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0>, + <&iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin>, + <&iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout>, + <&iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck>; + slew-rate = "fast"; + drive-strength = "x5"; + }; + }; + + flexcan2_default: flexcan2_default { + group0 { + pinmux = <&iomuxc1_gpio_io25_can_tx_can2_tx>, + <&iomuxc1_gpio_io27_can_rx_can2_rx>; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; + + pinmux_mdio: pinmux_mdio { + group0 { + pinmux = <&iomuxc1_enet2_mdc_enet_mdc_enet1_mdc>, + <&iomuxc1_enet2_mdio_enet_mdio_enet1_mdio>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + }; + + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0>, + <&iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1>, + <&iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2>, + <&iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3>, + <&iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>, + <&iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0>, + <&iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1>, + <&iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2>, + <&iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3>, + <&iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + + group1 { + pinmux = <&iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>, + <&iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; +}; diff --git a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts new file mode 100644 index 0000000000000..d6cc1058974f5 --- /dev/null +++ b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.dts @@ -0,0 +1,129 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_imx93-pinctrl.dtsi" +#include + +/ { + model = "NXP FRDM-IMX93 A55"; + compatible = "fsl,mimx93"; + + aliases { + led0 = &led_r; + led1 = &led_g; + sw0 = &btn_1; + }; + + chosen { + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,sram = &dram; + zephyr,canbus = &flexcan2; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + dram: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; + + leds { + compatible = "gpio-leds"; + + led_r: led_r { + label = "LED_R"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + + led_g: led_g { + label = "LED_G"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + }; + + led_b: led_b { + label = "LED_B"; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn_1: btn_1 { + label = "BTN1"; + gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn_2: btn_2 { + label = "BTN2"; + gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + can_phy0: can-phy0 { + compatible = "nxp,tja1051", "can-transceiver-gpio"; + standby-gpios = <&gpio_exp0 23 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + #phy-cells = <0>; + status = "okay"; + }; +}; + +&lpuart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c2 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; + + gpio_exp0: pcal6524@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <24>; + int-gpios = <&gpio3 27 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; + status = "okay"; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&flexcan2_default>; + pinctrl-names = "default"; + phys = <&can_phy0>; + status = "okay"; +}; diff --git a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.yaml b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.yaml new file mode 100644 index 0000000000000..c0c782189056d --- /dev/null +++ b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55.yaml @@ -0,0 +1,25 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_imx93/mimx9352/a55 +name: NXP FRDM-IMX93 A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - gpio + - uart + - i2c + - spi + - can + - net +testing: + ignore_tags: + - bluetooth +vendor: nxp diff --git a/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55_defconfig b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55_defconfig new file mode 100644 index 0000000000000..46119bc58ceb0 --- /dev/null +++ b/boards/nxp/frdm_imx93/frdm_imx93_mimx9352_a55_defconfig @@ -0,0 +1,30 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/nxp/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts index 75c3bd27858de..909976689b1de 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f.dts +++ b/boards/nxp/frdm_k22f/frdm_k22f.dts @@ -10,6 +10,7 @@ #include #include #include "frdm_k22f-pinctrl.dtsi" +#include #include / { @@ -93,28 +94,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiob 0 0>, /* A0 */ - <1 0 &gpiob 1 0>, /* A1 */ - <2 0 &gpioc 1 0>, /* A2 */ - <3 0 &gpioc 2 0>, /* A3 */ - <4 0 &gpiob 3 0>, /* A4 */ - <5 0 &gpiob 2 0>, /* A5 */ - <6 0 &gpiod 2 0>, /* D0 */ - <7 0 &gpiod 3 0>, /* D1 */ - <8 0 &gpiob 16 0>, /* D2 */ - <9 0 &gpioa 2 0>, /* D3 */ - <10 0 &gpioa 4 0>, /* D4 */ - <11 0 &gpiob 18 0>, /* D5 */ - <12 0 &gpioc 3 0>, /* D6 */ - <13 0 &gpioc 6 0>, /* D7 */ - <14 0 &gpiob 19 0>, /* D8 */ - <15 0 &gpioa 1 0>, /* D9 */ - <16 0 &gpiod 4 0>, /* D10 */ - <17 0 &gpiod 6 0>, /* D11 */ - <18 0 &gpiod 7 0>, /* D12 */ - <19 0 &gpiod 5 0>, /* D13 */ - <20 0 &gpioe 0 0>, /* D14 */ - <21 0 &gpioe 1 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts index bc9a440a8dc12..ec2f65c41427b 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f.dts +++ b/boards/nxp/frdm_k64f/frdm_k64f.dts @@ -4,6 +4,7 @@ #include #include "frdm_k64f-pinctrl.dtsi" +#include #include / { @@ -67,31 +68,31 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiob 2 0>, /* A0 */ - <1 0 &gpiob 3 0>, /* A1 */ - <2 0 &gpiob 10 0>, /* A2 */ - <3 0 &gpiob 11 0>, /* A3 */ - <4 0 &gpioc 11 0>, /* A4 */ - <5 0 &gpioc 10 0>, /* A5 */ - <6 0 &gpioc 16 0>, /* D0 */ - <7 0 &gpioc 17 0>, /* D1 */ - <8 0 &gpiob 9 0>, /* D2 */ - <9 0 &gpioa 1 0>, /* D3 */ - <10 0 &gpiob 23 0>, /* D4 */ - <11 0 &gpioa 2 0>, /* D5 */ - <12 0 &gpioc 2 0>, /* D6 */ - <13 0 &gpioc 3 0>, /* D7 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , /* NOTE: HW Rev D and below use: */ - /* <14 0 &gpioa 0 0>, */ + /* , */ /* NOTE: HW Rev E and on use: */ - <14 0 &gpioc 12 0>, /* D8 */ - <15 0 &gpioc 4 0>, /* D9 */ - <16 0 &gpiod 0 0>, /* D10 */ - <17 0 &gpiod 2 0>, /* D11 */ - <18 0 &gpiod 3 0>, /* D12 */ - <19 0 &gpiod 1 0>, /* D13 */ - <20 0 &gpioe 25 0>, /* D14 */ - <21 0 &gpioe 24 0>; /* D15 */ + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts index f2c5290da3579..6aec6ad90f631 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f.dts +++ b/boards/nxp/frdm_k82f/frdm_k82f.dts @@ -10,6 +10,7 @@ #include #include #include "frdm_k82f-pinctrl.dtsi" +#include #include / { @@ -95,28 +96,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiob 0 0>, /* A0 */ - <1 0 &gpiob 1 0>, /* A1 */ - <2 0 &gpioc 1 0>, /* A2 */ - <3 0 &gpioc 2 0>, /* A3 */ - <4 0 &gpiob 3 0>, /* A4 */ - <5 0 &gpiob 2 0>, /* A5 */ - <6 0 &gpiob 16 0>, /* D0 */ - <7 0 &gpiob 17 0>, /* D1 */ - <8 0 &gpioc 12 0>, /* D2 */ - <9 0 &gpiod 0 0>, /* D3 */ - <10 0 &gpioc 11 0>, /* D4 */ - <11 0 &gpioc 10 0>, /* D5 */ - <12 0 &gpioc 8 0>, /* D6 */ - <13 0 &gpioc 9 0>, /* D7 */ - <14 0 &gpioc 3 0>, /* D8 */ - <15 0 &gpioc 5 0>, /* D9 */ - <16 0 &gpiod 4 0>, /* D10 */ - <17 0 &gpiod 2 0>, /* D11 */ - <18 0 &gpiod 3 0>, /* D12 */ - <19 0 &gpiod 1 0>, /* D13 */ - <20 0 &gpioa 1 0>, /* D14 */ - <21 0 &gpioa 2 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z.dts b/boards/nxp/frdm_ke15z/frdm_ke15z.dts index 81a7afd06ac52..9236179d7741a 100644 --- a/boards/nxp/frdm_ke15z/frdm_ke15z.dts +++ b/boards/nxp/frdm_ke15z/frdm_ke15z.dts @@ -8,6 +8,7 @@ #include #include "frdm_ke15z-pinctrl.dtsi" +#include #include / { @@ -64,28 +65,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 6 0>, /* A2 */ - <3 0 &gpioa 7 0>, /* A3 */ - <4 0 &gpioa 2 0>, /* A4 */ - <5 0 &gpioa 3 0>, /* A5 */ - <6 0 &gpioc 8 0>, /* D0 */ - <7 0 &gpioc 9 0>, /* D1 */ - <8 0 &gpiod 12 0>, /* D2 */ - <9 0 &gpioc 15 0>, /* D3 */ - <10 0 &gpioe 9 0>, /* D4 */ - <11 0 &gpioc 5 0>, /* D5 */ - <12 0 &gpioa 16 0>, /* D6 */ - <13 0 &gpioa 17 0>, /* D7 */ - <14 0 &gpioe 8 0>, /* D8 */ - <15 0 &gpioe 7 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpioe 2 0>, /* D11 */ - <18 0 &gpioe 1 0>, /* D12 */ - <19 0 &gpioe 0 0>, /* D13 */ - <20 0 &gpiod 8 0>, /* D14 */ - <21 0 &gpiod 9 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts index 8be3c16f01815..65db544b2376f 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z.dts +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts @@ -8,6 +8,7 @@ #include #include "frdm_ke17z-pinctrl.dtsi" +#include #include #include @@ -88,28 +89,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 17 0>, /* A0 */ - <1 0 &gpioc 16 0>, /* A1 */ - <2 0 &gpiod 16 0>, /* A2 */ - <3 0 &gpiod 15 0>, /* A3 */ - <4 0 &gpioa 1 0>, /* A4 */ - <5 0 &gpioa 0 0>, /* A5 */ - <6 0 &gpiod 17 0>, /* D0 */ - <7 0 &gpioe 12 0>, /* D1 */ - <8 0 &gpiod 8 0>, /* D2 */ - <9 0 &gpiod 9 0>, /* D3 */ - <10 0 &gpioc 14 0>, /* D4 */ - <11 0 &gpioa 15 0>, /* D5 */ - <12 0 &gpioa 17 0>, /* D6 */ - <13 0 &gpioa 14 0>, /* D7 */ - <14 0 &gpioe 11 0>, /* D8 */ - <15 0 &gpiob 11 0>, /* D9 */ - <16 0 &gpiob 5 0>, /* D10 */ - <17 0 &gpiob 4 0>, /* D11 */ - <18 0 &gpiob 3 0>, /* D12 */ - <19 0 &gpiob 2 0>, /* D13 */ - <20 0 &gpioa 16 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts index 6d8440243063c..3e54851108798 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts @@ -8,6 +8,7 @@ #include #include "frdm_ke17z512-pinctrl.dtsi" +#include #include #include @@ -88,28 +89,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0 */ - <1 0 &gpioc 1 0>, /* A1 */ - <2 0 &gpiob 4 0>, /* A2 */ - <3 0 &gpioe 3 0>, /* A3 */ - <4 0 &gpioc 16 0>, /* A4 */ - <5 0 &gpioc 17 0>, /* A5 */ - <6 0 &gpioc 6 0>, /* D0 */ - <7 0 &gpioc 7 0>, /* D1 */ - <8 0 &gpiob 9 0>, /* D2 */ - <9 0 &gpioe 4 0>, /* D3 */ - <10 0 &gpioc 14 0>, /* D4 */ - <11 0 &gpioa 15 0>, /* D5 */ - <12 0 &gpioa 17 0>, /* D6 */ - <13 0 &gpioa 14 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpiob 11 0>, /* D9 */ - <16 0 &gpioe 6 0>, /* D10 */ - <17 0 &gpioe 2 0>, /* D11 */ - <18 0 &gpioe 1 0>, /* D12 */ - <19 0 &gpioe 0 0>, /* D13 */ - <20 0 &gpioa 2 0>, /* D14 */ - <21 0 &gpioa 3 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_kl25z/frdm_kl25z.dts b/boards/nxp/frdm_kl25z/frdm_kl25z.dts index 0f272c00da59c..079363da427ba 100644 --- a/boards/nxp/frdm_kl25z/frdm_kl25z.dts +++ b/boards/nxp/frdm_kl25z/frdm_kl25z.dts @@ -4,6 +4,7 @@ #include #include "frdm_kl25z-pinctrl.dtsi" +#include #include / { @@ -61,28 +62,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiob 0 0>, /* A0 */ - <1 0 &gpiob 1 0>, /* A1 */ - <2 0 &gpiob 2 0>, /* A2 */ - <3 0 &gpiob 3 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpioc 1 0>, /* A5 */ - <6 0 &gpioa 1 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpiod 4 0>, /* D2 */ - <9 0 &gpioa 12 0>, /* D3 */ - <10 0 &gpioa 4 0>, /* D4 */ - <11 0 &gpioa 5 0>, /* D5 */ - <12 0 &gpioc 8 0>, /* D6 */ - <13 0 &gpioc 9 0>, /* D7 */ - <14 0 &gpioa 13 0>, /* D8 */ - <15 0 &gpiod 5 0>, /* D9 */ - <16 0 &gpiod 0 0>, /* D10 */ - <17 0 &gpiod 2 0>, /* D11 */ - <18 0 &gpiod 3 0>, /* D12 */ - <19 0 &gpiod 1 0>, /* D13 */ - <20 0 &gpioe 0 0>, /* D14 */ - <21 0 &gpioe 1 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_kw41z/frdm_kw41z.dts b/boards/nxp/frdm_kw41z/frdm_kw41z.dts index 47b44f3e6179a..bbb7f6a9bad0e 100644 --- a/boards/nxp/frdm_kw41z/frdm_kw41z.dts +++ b/boards/nxp/frdm_kw41z/frdm_kw41z.dts @@ -4,6 +4,7 @@ #include #include "frdm_kw41z-pinctrl.dtsi" +#include #include / { @@ -88,26 +89,26 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = /* A0 cannot be muxed as gpio */ - <1 0 &gpiob 18 0>, /* A1 */ - <2 0 &gpiob 2 0>, /* A2 */ - <3 0 &gpiob 3 0>, /* A3 */ - <4 0 &gpiob 1 0>, /* A4 */ - <6 0 &gpioc 6 0>, /* D0 */ - <7 0 &gpioc 7 0>, /* D1 */ - <8 0 &gpioc 19 0>, /* D2 */ - <9 0 &gpioc 16 0>, /* D3 */ - <10 0 &gpioc 4 0>, /* D4 */ - <11 0 &gpioc 17 0>, /* D5 */ - <12 0 &gpioc 18 0>, /* D6 */ - <13 0 &gpioa 1 0>, /* D7 */ - <14 0 &gpioa 0 0>, /* D8 */ - <15 0 &gpioc 1 0>, /* D9 */ - <16 0 &gpioa 19 0>, /* D10 */ - <17 0 &gpioa 16 0>, /* D11 */ - <18 0 &gpioa 17 0>, /* D12 */ - <19 0 &gpioa 18 0>, /* D13 */ - <20 0 &gpioc 3 0>, /* D14 */ - <21 0 &gpioc 2 0>; /* D15 */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts index 91f1df5c5d273..6f68b3dabb2b8 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts @@ -8,6 +8,7 @@ #include #include "frdm_mcxa156-pinctrl.dtsi" +#include #include #include @@ -87,28 +88,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 10 0>, /* A0 */ - <1 0 &gpio2 5 0>, /* A1 */ - <2 0 &gpio2 3 0>, /* A2 */ - <3 0 &gpio2 4 0>, /* A3 */ - <4 0 &gpio1 12 0>, /* A4 */ - <5 0 &gpio1 13 0>, /* A5 */ - <6 0 &gpio2 11 0>, /* D0 */ - <7 0 &gpio2 10 0>, /* D1 */ - <8 0 &gpio3 1 0>, /* D2 */ - <9 0 &gpio3 12 0>, /* D3 */ - <10 0 &gpio3 31 0>, /* D4 */ - <11 0 &gpio3 14 0>, /* D5 */ - <12 0 &gpio3 16 0>, /* D6 */ - <13 0 &gpio1 14 0>, /* D7 */ - <14 0 &gpio1 15 0>, /* D8 */ - <15 0 &gpio3 17 0>, /* D9 */ - <16 0 &gpio3 13 0>, /* D10 */ - <17 0 &gpio3 15 0>, /* D11 */ - <18 0 &gpio2 16 0>, /* D12 */ - <19 0 &gpio2 12 0>, /* D13 */ - <20 0 &gpio0 16 0>, /* D14 */ - <21 0 &gpio0 17 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_mcxa266/board.cmake b/boards/nxp/frdm_mcxa266/board.cmake index 361bb67183382..0b36efc599994 100644 --- a/boards/nxp/frdm_mcxa266/board.cmake +++ b/boards/nxp/frdm_mcxa266/board.cmake @@ -5,7 +5,7 @@ # board_runner_args(jlink "--device=MCXA266") -board_runner_args(linkserver "--device=MCXA266:FRDM-MCXA266") +board_runner_args(linkserver "--device=MCXA346:FRDM-MCXA346") board_runner_args(pyocd "--target=mcxa266") include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts index 39d96481303b2..1ff38715b1354 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts @@ -9,6 +9,7 @@ #include #include "frdm_mcxn236-pinctrl.dtsi" #include +#include #include #include @@ -75,28 +76,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio4 6 0>, /* A0 */ - <1 0 &gpio4 15 0>, /* A1 */ - <2 0 &gpio4 16 0>, /* A2 */ - <3 0 &gpio4 17 0>, /* A3 */ - <4 0 &gpio4 12 0>, /* A4 */ - <5 0 &gpio4 13 0>, /* A5 */ - <6 0 &gpio4 3 0>, /* D0 */ - <7 0 &gpio4 2 0>, /* D1 */ - <8 0 &gpio2 0 0>, /* D2 */ - <9 0 &gpio3 12 0>, /* D3 */ - <10 0 &gpio0 21 0>, /* D4 */ - <11 0 &gpio2 7 0>, /* D5 */ - <12 0 &gpio3 17 0>, /* D6 */ - <13 0 &gpio0 22 0>, /* D7 */ - <14 0 &gpio0 23 0>, /* D8 */ - <15 0 &gpio3 14 0>, /* D9 */ - <16 0 &gpio1 3 0>, /* D10 */ - <17 0 &gpio1 0 0>, /* D11 */ - <18 0 &gpio1 2 0>, /* D12 */ - <19 0 &gpio1 1 0>, /* D13 */ - <20 0 &gpio1 16 0>, /* D14 */ - <21 0 &gpio1 17 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; /* diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 68e56f31e5334..a02106df76d19 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -6,8 +6,9 @@ #include "frdm_mcxn947-pinctrl.dtsi" #include -#include +#include #include +#include / { aliases{ @@ -60,26 +61,26 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <2 0 &gpio0 14 0>, /* A2 */ - <3 0 &gpio0 22 0>, /* A3 */ - <4 0 &gpio0 15 0>, /* A4 */ - <5 0 &gpio0 23 0>, /* A5 */ - <6 0 &gpio4 3 0>, /* D0 */ - <7 0 &gpio4 2 0>, /* D1 */ - <8 0 &gpio0 29 0>, /* D2 */ - <9 0 &gpio1 23 0>, /* D3 */ - <10 0 &gpio0 30 0>, /* D4 */ - <11 0 &gpio1 21 0>, /* D5 */ - <12 0 &gpio1 2 0>, /* D6 */ - <13 0 &gpio0 31 0>, /* D7 */ - <14 0 &gpio0 28 0>, /* D8 */ - <15 0 &gpio0 10 0>, /* D9 */ - <16 0 &gpio0 27 0>, /* D10 */ - <17 0 &gpio0 24 0>, /* D11 */ - <18 0 &gpio0 26 0>, /* D12 */ - <19 0 &gpio0 25 0>, /* D13 */ - <20 0 &gpio4 0 0>, /* D14 */ - <21 0 &gpio4 1 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; /* @@ -260,7 +261,7 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { phy: ethernet-phy@0 { compatible = "ethernet-phy"; reg = <0>; - status = "okay"; + status = "disabled"; }; }; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi index d74efb27ac64e..f4549f8efadb2 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi @@ -161,6 +161,10 @@ status = "okay"; }; +&phy { + status = "okay"; +}; + &wwdt0 { status = "okay"; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index e67859dbf5af5..4c96bf85551f3 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -7,6 +7,7 @@ #include #include "frdm_mcxw71-pinctrl.dtsi" +#include #include / { @@ -68,28 +69,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiod 1 0>, /* A0 */ - <1 0 &gpiod 2 0>, /* A1 */ - <2 0 &gpiod 3 0>, /* A2 */ - <3 0 &gpioa 4 0>, /* A3 */ - <4 0 &gpioc 3 0>, /* A4 */ - <5 0 &gpioc 2 0>, /* A5 */ - <6 0 &gpioa 16 0>, /* D0 */ - <7 0 &gpioa 17 0>, /* D1 */ - <8 0 &gpioc 4 0>, /* D2 */ - <9 0 &gpioc 5 0>, /* D3 */ - <10 0 &gpioa 19 0>, /* D4 */ - <11 0 &gpioc 1 0>, /* D5 */ - <12 0 &gpioa 20 0>, /* D6 */ - <13 0 &gpioa 21 0>, /* D7 */ - <14 0 &gpioc 4 0>, /* D8 */ - <15 0 &gpioa 18 0>, /* D9 */ - <16 0 &gpiob 0 0>, /* D10 */ - <17 0 &gpiob 3 0>, /* D11 */ - <18 0 &gpiob 1 0>, /* D12 */ - <19 0 &gpiob 2 0>, /* D13 */ - <20 0 &gpiob 4 0>, /* D14 */ - <21 0 &gpiob 5 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts index 3cdd5b2b41091..de1e7c5e6ba99 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts @@ -7,6 +7,7 @@ #include #include "frdm_mcxw72-pinctrl.dtsi" +#include #include / { @@ -67,28 +68,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiod 1 0>, /* A0 */ - <1 0 &gpiod 2 0>, /* A1 */ - <2 0 &gpiod 3 0>, /* A2 */ - <3 0 &gpioa 4 0>, /* A3 */ - <4 0 &gpioc 3 0>, /* A4 */ - <5 0 &gpioc 2 0>, /* A5 */ - <6 0 &gpioa 16 0>, /* D0 */ - <7 0 &gpioa 17 0>, /* D1 */ - <8 0 &gpioc 4 0>, /* D2 */ - <9 0 &gpioc 5 0>, /* D3 */ - <10 0 &gpioa 19 0>, /* D4 */ - <11 0 &gpioc 1 0>, /* D5 */ - <12 0 &gpioa 20 0>, /* D6 */ - <13 0 &gpioa 21 0>, /* D7 */ - <14 0 &gpioc 4 0>, /* D8 */ - <15 0 &gpioa 18 0>, /* D9 */ - <16 0 &gpiob 0 0>, /* D10 */ - <17 0 &gpiob 3 0>, /* D11 */ - <18 0 &gpiob 1 0>, /* D12 */ - <19 0 &gpiob 2 0>, /* D13 */ - <20 0 &gpiob 4 0>, /* D14 */ - <21 0 &gpiob 5 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi index 1f0d336cbd70c..aeb3f68d8f468 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi @@ -5,6 +5,7 @@ */ #include "frdm_rw612-pinctrl.dtsi" +#include #include / { @@ -61,25 +62,25 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &hsgpio1 10 0>, /* A0 */ - <1 0 &hsgpio1 11 0>, /* A1 */ - <2 0 &hsgpio1 13 0>, /* A2 */ - <6 0 &hsgpio0 9 0>, /* D0 */ - <7 0 &hsgpio0 8 0>, /* D1 */ - <8 0 &hsgpio0 11 0>, /* D2 */ - <9 0 &hsgpio0 15 0>, /* D3 */ - <10 0 &hsgpio0 18 0>, /* D4 */ - <11 0 &hsgpio0 27 0>, /* D5 */ - <12 0 &hsgpio0 0 0>, /* D6 */ - <13 0 &hsgpio0 20 0>, /* D7 */ - <14 0 &hsgpio1 18 0>, /* D8 */ - <15 0 &hsgpio1 20 0>, /* D9 */ - <16 0 &hsgpio0 6 0>, /* D10 */ - <17 0 &hsgpio0 9 0>, /* D11 */ - <18 0 &hsgpio0 8 0>, /* D12 */ - <19 0 &hsgpio0 7 0>, /* D13 */ - <20 0 &hsgpio0 16 0>, /* D14 */ - <21 0 &hsgpio0 17 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/imx943_evk/Kconfig.defconfig b/boards/nxp/imx943_evk/Kconfig.defconfig index 3b836c3aa60ec..429d51113bb0c 100644 --- a/boards/nxp/imx943_evk/Kconfig.defconfig +++ b/boards/nxp/imx943_evk/Kconfig.defconfig @@ -1,12 +1,80 @@ # Copyright 2025 NXP # SPDX-License-Identifier: Apache-2.0 +if SOC_MIMX94398_A55 + +if ETH_NXP_IMX_NETC + +config GIC_V3_ITS + default y + +endif # ETH_NXP_IMX_NETC + +# GIC ITS depends on kernel heap which init priority is 30, so set +# GIC to be 31, mailbox and SCMI will be initialized by the order +# according to dts dependency although they use the same init priority. +config INTC_INIT_PRIORITY + default 31 + +config MBOX_INIT_PRIORITY + default 31 + +config ARM_SCMI_SHMEM_INIT_PRIORITY + default 31 if SOC_MIMX94398_A55 + +config ARM_SCMI_TRANSPORT_INIT_PRIORITY + default 31 if SOC_MIMX94398_A55 + +config CLOCK_CONTROL_INIT_PRIORITY + default 31 if SOC_MIMX94398_A55 + +# Enlarge default networking stack +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +if NET_SOCKETS_SERVICE + +config NET_SOCKETS_SERVICE_STACK_SIZE + default 8192 + +endif # NET_SOCKETS_SERVICE + +endif # NETWORKING + +endif # SOC_MIMX94398_A55 + +if SOC_MIMX94398_M33 + config INTC_INIT_PRIORITY default 2 config MBOX_INIT_PRIORITY default 3 +endif # SOC_MIMX94398_M33 + if ETH_NXP_IMX_NETC config ETH_NXP_IMX_RX_RING_LEN diff --git a/boards/nxp/imx943_evk/board.c b/boards/nxp/imx943_evk/board.c index f131042c2a879..992a731060c0b 100644 --- a/boards/nxp/imx943_evk/board.c +++ b/boards/nxp/imx943_evk/board.c @@ -10,7 +10,8 @@ static int board_init(void) { -#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) +#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) \ + && !defined(CONFIG_CPU_CORTEX_A) /* * PCS(Physical Coding Sublayer) protocols on link0-5, * xxxx xxxx xxxx xxx1: 1G SGMII diff --git a/boards/nxp/imx943_evk/doc/index.rst b/boards/nxp/imx943_evk/doc/index.rst index 92bd31f614ea0..03cf30aa7ba93 100644 --- a/boards/nxp/imx943_evk/doc/index.rst +++ b/boards/nxp/imx943_evk/doc/index.rst @@ -69,7 +69,26 @@ NETC driver supports to manage the Physical Station Interface (PSI), and TSN swi The ENET0, ENETC1, ENETC2 ports could be enabled for M33 by west build option ``-DEXTRA_DTC_OVERLAY_FILE=enetc.overlay``. -The two switch ports could be verified via :zephyr:code-sample:`dsa`. +For A55 Core, ENET0, ENETC1, ENETC2 ports are enabled by default, so no overlay is +needed, but NETC depends on GIC ITS, so need to make sure to allocate heap memory to +be larger than 851968 byes by setting CONFIG_HEAP_MEM_POOL_SIZE. + +The two switch ports could be verified via :zephyr:code-sample:`dsa` on M33 core +or on A55 Core, for example for A55 Core: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/dsa + :host-os: unix + :board: imx943_evk/mimx94398/a55 + :goals: flash + +Or for M33 Core: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/dsa + :host-os: unix + :board: imx943_evk/mimx94398/m33/ddr + :goals: build Programming and Debugging (A55) ******************************* diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts index 92c34f41d6be2..ae6ab2dee6686 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts @@ -35,7 +35,7 @@ }; dram: memory@d0000000 { - reg = <0xd0000000 DT_SIZE_M(1)>; + reg = <0xd0000000 DT_SIZE_M(10)>; }; }; @@ -45,3 +45,91 @@ pinctrl-0 = <&lpuart1_default>; pinctrl-names = "default"; }; + +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy0: phy@2 { + compatible = "ethernet-phy"; + reg = <0xf>; + status = "disabled"; + }; + + phy1: phy@3 { + compatible = "ethernet-phy"; + reg = <0x10>; + status = "disabled"; + }; + + phy2: phy@5 { + compatible = "realtek,rtl8211f"; + reg = <0x5>; + status = "okay"; + }; + + phy3: phy@6 { + compatible = "realtek,rtl8211f"; + reg = <0x6>; + status = "okay"; + }; + + phy4: phy@7 { + compatible = "realtek,rtl8211f"; + reg = <0x7>; + status = "okay"; + }; +}; + +&enetc_psi0 { + pinctrl-0 = <ð2_default>; + pinctrl-names = "default"; + phy-handle = <&phy2>; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enetc_psi1 { + pinctrl-0 = <ð3_default>; + pinctrl-names = "default"; + phy-handle = <&phy3>; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enetc_psi2 { + pinctrl-0 = <ð4_default>; + pinctrl-names = "default"; + phy-handle = <&phy4>; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&netc_ptp_clock0 { + status = "okay"; +}; + +&switch_port0 { + zephyr,random-mac-address; + pinctrl-0 = <ð0_default>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-connection-type = "mii"; + status = "disabled"; +}; + +&switch_port1 { + zephyr,random-mac-address; + pinctrl-0 = <ð1_default>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-connection-type = "mii"; + status = "disabled"; +}; + +/* Internal port */ +&switch_port3 { + zephyr,random-mac-address; + status = "disabled"; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml index 470b86e0f4586..3d6e04cf34d36 100644 --- a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml @@ -11,8 +11,9 @@ arch: arm64 toolchain: - zephyr - cross-compile -ram: 1024 +ram: 10240 supported: - gpio + - net - uart vendor: nxp diff --git a/boards/nxp/imx95_evk/board.cmake b/boards/nxp/imx95_evk/board.cmake index daca6ade79faf..691814e7f94f7 100644 --- a/boards/nxp/imx95_evk/board.cmake +++ b/boards/nxp/imx95_evk/board.cmake @@ -21,6 +21,6 @@ if(CONFIG_BOARD_NXP_SPSDK_IMAGE OR (DEFINED ENV{USE_NXP_SPSDK_IMAGE} endif() if(CONFIG_SOC_MIMX9596_A55) - board_runner_args(jlink "--device=MIMX9556_A55_0" "--no-reset" "--flash-sram") + board_runner_args(jlink "--device=MIMX9596_A55_0" "--no-reset" "--flash-sram") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) endif() diff --git a/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts index 22e2e9f97f515..7cb9c4c979557 100644 --- a/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts +++ b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include "lpcxpresso11u68-pinctrl.dtsi" @@ -65,28 +66,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 9 0>, /* A0 */ - <1 0 &gpio0 14 0>, /* A1 */ - <2 0 &gpio0 13 0>, /* A2 */ - <3 0 &gpio0 12 0>, /* A3 */ - <4 0 &gpio0 23 0>, /* A4 */ - <5 0 &gpio0 11 0>, /* A5 */ - <6 0 &gpio2 11 0>, /* D0 */ - <7 0 &gpio2 12 0>, /* D1 */ - <8 0 &gpio1 18 0>, /* D2 */ - <9 0 &gpio1 24 0>, /* D3 */ - <10 0 &gpio1 19 0>, /* D4 */ - <11 0 &gpio1 26 0>, /* D5 */ - <12 0 &gpio1 27 0>, /* D6 */ - <13 0 &gpio1 25 0>, /* D7 */ - <14 0 &gpio1 28 0>, /* D8 */ - <15 0 &gpio2 3 0>, /* D9 */ - <16 0 &gpio0 2 0>, /* D10 */ - <17 0 &gpio0 9 0>, /* D11 */ - <18 0 &gpio0 9 0>, /* D12 */ - <19 0 &gpio1 29 0>, /* D13 */ - <20 0 &gpio0 5 0>, /* D14 */ - <21 0 &gpio0 4 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi index 20f427b3b93d0..ef0edf48384e6 100644 --- a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi @@ -6,6 +6,7 @@ */ #include "lpcxpresso55s06-pinctrl.dtsi" +#include #include / { @@ -95,26 +96,26 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 16 0>, /* A0 */ - <1 0 &gpio0 23 0>, /* A1 */ - <2 0 &gpio0 9 0>, /* A2 */ - <3 0 &gpio0 0 0>, /* A3 */ - <4 0 &gpio0 13 0>, /* A4 */ - <5 0 &gpio0 14 0>, /* A5 */ - <6 0 &gpio1 10 0>, /* D0 */ - <7 0 &gpio1 11 0>, /* D1 */ - <8 0 &gpio0 15 0>, /* D2 */ - <9 0 &gpio0 23 0>, /* D3 */ - <10 0 &gpio0 22 0>, /* D4 */ - <11 0 &gpio0 19 0>, /* D5 */ - <12 0 &gpio0 18 0>, /* D6 */ - <13 0 &gpio0 2 0>, /* D7 */ - <14 0 &gpio0 10 0>, /* D8 */ - <15 0 &gpio0 25 0>, /* D9 */ - <16 0 &gpio1 1 0>, /* D10 */ - <17 0 &gpio0 26 0>, /* D11 */ - <18 0 &gpio1 3 0>, /* D12 */ - <19 0 &gpio1 2 0>; /* D13 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi index 55e2e661ac491..c04466f7c383f 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi @@ -6,6 +6,7 @@ */ #include "lpcxpresso55s16-pinctrl.dtsi" +#include #include / { @@ -97,29 +98,29 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 16 0>, /* A0 */ - <1 0 &gpio0 23 0>, /* A1 */ - <2 0 &gpio0 0 0>, /* A2 */ + gpio-map = , + , + , /* R63 DNP, A3 not connected */ - /* <3 0 &gpio1 31 0>,*/ /* A3 */ - <4 0 &gpio0 13 0>, /* A4 */ - <5 0 &gpio0 14 0>, /* A5 */ - <6 0 &gpio1 24 0>, /* D0 */ - <7 0 &gpio0 27 0>, /* D1 */ - <8 0 &gpio0 15 0>, /* D2 */ - <9 0 &gpio1 6 0>, /* D3 */ - <10 0 &gpio1 7 0>, /* D4 */ - <11 0 &gpio1 4 0>, /* D5 */ - <12 0 &gpio1 10 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 8 0>, /* D8 */ - <15 0 &gpio1 5 0>, /* D9 */ - <16 0 &gpio1 1 0>, /* D10 */ - <17 0 &gpio0 26 0>, /* D11 */ - <18 0 &gpio1 3 0>, /* D12 */ - <19 0 &gpio1 2 0>, /* D13 */ - <20 0 &gpio1 21 0>, /* D14 */ - <21 0 &gpio1 20 0>; /* D15 */ + /* ,*/ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi index 0bd079c743e12..d703ad0cd41f1 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi @@ -5,6 +5,7 @@ */ #include "lpcxpresso55s28-pinctrl.dtsi" +#include / { aliases{ @@ -63,28 +64,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 16 0>, /* A0 */ - <1 0 &gpio0 23 0>, /* A1 */ - <2 0 &gpio0 0 0>, /* A2 */ - <3 0 &gpio1 31 0>, /* A3 */ - <4 0 &gpio0 13 0>, /* A4 */ - <5 0 &gpio0 14 0>, /* A5 */ - <6 0 &gpio1 24 0>, /* D0 */ - <7 0 &gpio0 27 0>, /* D1 */ - <8 0 &gpio0 15 0>, /* D2 */ - <9 0 &gpio1 6 0>, /* D3 */ - <10 0 &gpio1 7 0>, /* D4 */ - <11 0 &gpio1 4 0>, /* D5 */ - <12 0 &gpio1 10 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 8 0>, /* D8 */ - <15 0 &gpio1 5 0>, /* D9 */ - <16 0 &gpio1 1 0>, /* D10 */ - <17 0 &gpio0 26 0>, /* D11 */ - <18 0 &gpio1 3 0>, /* D12 */ - <19 0 &gpio1 2 0>, /* D13 */ - <20 0 &gpio1 21 0>, /* D14 */ - <21 0 &gpio1 20 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts index acec993930727..80c72bf5eed78 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts @@ -8,6 +8,7 @@ #include #include "lpcxpresso55s36-pinctrl.dtsi" +#include #include / { @@ -94,28 +95,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 15 0>, /* A0 */ - <1 0 &gpio0 16 0>, /* A1 */ - <2 0 &gpio0 0 0>, /* A2 */ - <3 0 &gpio1 13 0>, /* A3 */ - <4 0 &gpio1 21 0>, /* A4 */ - <5 0 &gpio1 30 0>, /* A5 */ - <6 0 &gpio2 0 0>, /* D0 */ - <7 0 &gpio2 1 0>, /* D1 */ - <8 0 &gpio1 26 0>, /* D2 */ - <9 0 &gpio1 23 0>, /* D3 */ - <10 0 &gpio1 8 0>, /* D4 */ - <11 0 &gpio1 25 0>, /* D5 */ - <12 0 &gpio1 0 0>, /* D6 */ - <13 0 &gpio1 28 0>, /* D7 */ - <14 0 &gpio1 27 0>, /* D8 */ - <15 0 &gpio1 29 0>, /* D9 */ - <16 0 &gpio1 26 0>, /* D10 */ - <17 0 &gpio0 26 0>, /* D11 */ - <18 0 &gpio1 3 0>, /* D12 */ - <19 0 &gpio1 2 0>, /* D13 */ - <20 0 &gpio0 3 0>, /* D14 */ - <21 0 &gpio0 2 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi index af651dc9c90a0..d61f8f310fb49 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi @@ -5,6 +5,7 @@ */ #include "lpcxpresso55s69-pinctrl.dtsi" +#include / { aliases{ @@ -62,28 +63,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 16 0>, /* A0 */ - <1 0 &gpio0 23 0>, /* A1 */ - <2 0 &gpio0 0 0>, /* A2 */ - <3 0 &gpio1 31 0>, /* A3 */ - <4 0 &gpio0 13 0>, /* A4 */ - <5 0 &gpio0 14 0>, /* A5 */ - <6 0 &gpio1 24 0>, /* D0 */ - <7 0 &gpio0 27 0>, /* D1 */ - <8 0 &gpio0 15 0>, /* D2 */ - <9 0 &gpio1 6 0>, /* D3 */ - <10 0 &gpio1 7 0>, /* D4 */ - <11 0 &gpio1 4 0>, /* D5 */ - <12 0 &gpio1 10 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 8 0>, /* D8 */ - <15 0 &gpio1 5 0>, /* D9 */ - <16 0 &gpio1 1 0>, /* D10 */ - <17 0 &gpio0 26 0>, /* D11 */ - <18 0 &gpio1 3 0>, /* D12 */ - <19 0 &gpio1 2 0>, /* D13 */ - <20 0 &gpio1 21 0>, /* D14 */ - <21 0 &gpio1 20 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; reserved-memory { diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts index 751541d3d260d..fbc0ec48c43fd 100644 --- a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts +++ b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts @@ -7,6 +7,7 @@ #include #include "mcxw72_evk-pinctrl.dtsi" +#include #include / { @@ -67,28 +68,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiod 1 0>, /* A0 */ - <1 0 &gpiod 2 0>, /* A1 */ - <2 0 &gpiod 3 0>, /* A2 */ - <3 0 &gpioa 4 0>, /* A3 */ - <4 0 &gpioc 3 0>, /* A4 */ - <5 0 &gpioc 2 0>, /* A5 */ - <6 0 &gpioa 16 0>, /* D0 */ - <7 0 &gpioa 17 0>, /* D1 */ - <8 0 &gpioc 4 0>, /* D2 */ - <9 0 &gpioc 5 0>, /* D3 */ - <10 0 &gpioa 19 0>, /* D4 */ - <11 0 &gpioc 1 0>, /* D5 */ - <12 0 &gpioa 20 0>, /* D6 */ - <13 0 &gpioa 21 0>, /* D7 */ - <14 0 &gpioc 4 0>, /* D8 */ - <15 0 &gpioa 18 0>, /* D9 */ - <16 0 &gpiob 0 0>, /* D10 */ - <17 0 &gpiob 3 0>, /* D11 */ - <18 0 &gpiob 1 0>, /* D12 */ - <19 0 &gpiob 2 0>, /* D13 */ - <20 0 &gpiob 4 0>, /* D14 */ - <21 0 &gpiob 5 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst index 66809750946ea..c34f2f6fb4fb8 100644 --- a/boards/nxp/mimxrt1010_evk/doc/index.rst +++ b/boards/nxp/mimxrt1010_evk/doc/index.rst @@ -141,7 +141,7 @@ Configuring a Debug Probe ========================= For the RT1010, J61/J62 are the SWD isolation jumpers, J22 is the DFU -mode jumper, and J16 is the 10 pin JTAG/SWD header. +mode jumper, and J55 is the 10 pin JTAG/SWD header. .. include:: ../../common/rt1xxx-lpclink2-debug.rst :start-after: rt1xxx-lpclink2-probes diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts index 93c22b64a902b..32832ac649020 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts @@ -9,6 +9,7 @@ #include #include "mimxrt1010_evk-pinctrl.dtsi" +#include #include / { @@ -55,28 +56,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 21 0>, /* A0 */ - <1 0 &gpio1 23 0>, /* A1 */ - <2 0 &gpio1 24 0>, /* A2 */ - <3 0 &gpio1 28 0>, /* A3 */ - <4 0 &gpio1 15 0>, /* A4 (shared with D6) */ - <5 0 &gpio1 16 0>, /* A5 (shared with D7) */ - <6 0 &gpio1 9 0>, /* D0 */ - <7 0 &gpio1 10 0>, /* D1 */ - <8 0 &gpio1 19 0>, /* D2 (shared with D10) */ - <9 0 &gpio1 20 0>, /* D3 (shared with D13) */ + gpio-map = , + , + , + , + , /* shared with D6 */ + , /* shared with D7 */ + , + , + , /* shared with D10 */ + , /* shared with D13 */ /* R800 not populated, D4 */ /* R793 not populated, D5 (shared with D14) */ - <12 0 &gpio1 15 0>, /* D6 (shared with A4) */ - <13 0 &gpio1 16 0>, /* D7 (shared with A5) */ - <14 0 &gpio2 2 0>, /* D8 */ - <15 0 &gpio2 3 0>, /* D9 R795 not populated */ - <16 0 &gpio1 19 0>, /* D10 (shared with D2) */ - <17 0 &gpio1 18 0>, /* D11 */ - <18 0 &gpio1 17 0>, /* D12 */ - <19 0 &gpio1 20 0>, /* D13 (shared with D3) */ - <20 0 &gpio1 1 0>, /* D14 */ - <21 0 &gpio1 2 0>; /* D15 */ + , /* shared with A4 */ + , /* shared with A5 */ + , + , /* R795 not populated */ + , /* shared with D2 */ + , + , + , /* shared with D3 */ + , + ; }; }; diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts index f79a57c265255..4d2f63a21c05c 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts @@ -8,6 +8,7 @@ #include #include "mimxrt1015_evk-pinctrl.dtsi" +#include #include / { @@ -54,28 +55,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 29 0>, /* A0 */ - <1 0 &gpio1 14 0>, /* A1 */ - <2 0 &gpio1 28 0>, /* A2 */ - <3 0 &gpio1 26 0>, /* A3 */ - <4 0 &gpio1 31 0>, /* A4 */ - <5 0 &gpio1 30 0>, /* A5 */ - <6 0 &gpio3 1 0>, /* D0 */ - <7 0 &gpio3 0 0>, /* D1 */ - <8 0 &gpio2 20 0>, /* D2 */ - <9 0 &gpio2 26 0>, /* D3 */ - <10 0 &gpio3 2 0>, /* D4 */ - <11 0 &gpio2 27 0>, /* D5 */ - <12 0 &gpio1 27 0>, /* D6 */ - <13 0 &gpio1 15 0>, /* D7 */ - <14 0 &gpio2 21 0>, /* D8 */ - <15 0 &gpio2 22 0>, /* D9 */ - <16 0 &gpio1 11 0>, /* D10 */ - <17 0 &gpio1 12 0>, /* D11 */ - <18 0 &gpio1 13 0>, /* D12 */ - <19 0 &gpio1 10 0>, /* D13 */ - <20 0 &gpio1 31 0>, /* D14 */ - <21 0 &gpio1 30 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts index e52069371936a..5ff130237b2d8 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts @@ -8,6 +8,7 @@ #include #include "mimxrt1020_evk-pinctrl.dtsi" +#include #include / { @@ -61,28 +62,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 26 0>, /* A0 */ - <1 0 &gpio1 27 0>, /* A1 */ - <2 0 &gpio1 28 0>, /* A2 */ - <3 0 &gpio1 29 0>, /* A3 */ - <4 0 &gpio1 31 0>, /* A4 */ - <5 0 &gpio1 30 0>, /* A5 */ - <6 0 &gpio1 25 0>, /* D0 */ - <7 0 &gpio1 24 0>, /* D1 */ - <8 0 &gpio1 9 0>, /* D2 */ - <9 0 &gpio1 7 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 14 0>, /* D6 */ - <13 0 &gpio1 22 0>, /* D7 */ - <14 0 &gpio1 23 0>, /* D8 */ - <15 0 &gpio1 15 0>, /* D9 */ - <16 0 &gpio1 11 0>, /* D10 */ - <17 0 &gpio1 12 0>, /* D11 */ - <18 0 &gpio1 13 0>, /* D12 */ - <19 0 &gpio1 10 0>, /* D13 */ - <20 0 &gpio3 23 0>, /* D14 */ - <21 0 &gpio3 22 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts index 6ccdb91db4232..b8118497f5d82 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts @@ -8,6 +8,7 @@ #include #include "mimxrt1024_evk-pinctrl.dtsi" +#include #include / { @@ -65,28 +66,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 26 0>, /* A0 */ - <1 0 &gpio1 27 0>, /* A1 */ - <2 0 &gpio1 28 0>, /* A2 */ - <3 0 &gpio1 29 0>, /* A3 */ - <4 0 &gpio1 31 0>, /* A4 */ - <5 0 &gpio1 30 0>, /* A5 */ - <6 0 &gpio1 25 0>, /* D0 */ - <7 0 &gpio1 24 0>, /* D1 */ - <8 0 &gpio1 9 0>, /* D2 */ - <9 0 &gpio1 7 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 14 0>, /* D6 */ - <13 0 &gpio1 22 0>, /* D7 */ - <14 0 &gpio1 23 0>, /* D8 */ - <15 0 &gpio1 15 0>, /* D9 */ - <16 0 &gpio1 11 0>, /* D10 */ - <17 0 &gpio1 12 0>, /* D11 */ - <18 0 &gpio1 13 0>, /* D12 */ - <19 0 &gpio1 10 0>, /* D13 */ - <20 0 &gpio3 23 0>, /* D14 */ - <21 0 &gpio3 22 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts index 744e8776dba03..76b275954387f 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts @@ -8,6 +8,7 @@ #include #include "mimxrt1040_evk-pinctrl.dtsi" +#include #include / { @@ -89,28 +90,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 14 0>, /* A0 */ - <1 0 &gpio1 15 0>, /* A1 */ - <2 0 &gpio1 20 0>, /* A2 */ - <3 0 &gpio1 21 0>, /* A3 */ - <4 0 &gpio1 22 0>, /* A4 */ - <5 0 &gpio1 23 0>, /* A5 */ - <6 0 &gpio3 1 0>, /* D0 */ - <7 0 &gpio3 0 0>, /* D1 */ - <8 0 &gpio1 11 0>, /* D2 */ - <9 0 &gpio3 2 0>, /* D3 */ - <10 0 &gpio1 9 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 18 0>, /* D6 */ - <13 0 &gpio1 19 0>, /* D7 */ - <14 0 &gpio2 30 0>, /* D8 */ - <15 0 &gpio2 31 0>, /* D9 */ - <16 0 &gpio3 13 0>, /* D10 */ - <17 0 &gpio3 14 0>, /* D11 */ - <18 0 &gpio3 15 0>, /* D12 */ - <19 0 &gpio3 12 0>, /* D13 */ - <20 0 &gpio1 17 0>, /* D14 */ - <21 0 &gpio1 16 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi index d9f27f8c29c7d..0e6b1235e60de 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi @@ -8,6 +8,7 @@ #include #include "mimxrt1050_evk-pinctrl.dtsi" +#include #include / { @@ -88,28 +89,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 26 0>, /* A0 */ - <1 0 &gpio1 27 0>, /* A1 */ - <2 0 &gpio1 20 0>, /* A2 */ - <3 0 &gpio1 21 0>, /* A3 */ - <4 0 &gpio1 17 0>, /* A4 */ - <5 0 &gpio1 16 0>, /* A5 */ - <6 0 &gpio1 23 0>, /* D0 */ - <7 0 &gpio1 22 0>, /* D1 */ - <8 0 &gpio1 11 0>, /* D2 */ - <9 0 &gpio1 24 0>, /* D3 */ - <10 0 &gpio1 9 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 18 0>, /* D6 */ - <13 0 &gpio1 19 0>, /* D7 */ - <14 0 &gpio1 3 0>, /* D8 */ - <15 0 &gpio1 2 0>, /* D9 */ - <16 0 &gpio3 13 0>, /* D10 */ - <17 0 &gpio3 14 0>, /* D11 */ - <18 0 &gpio3 15 0>, /* D12 */ - <19 0 &gpio3 12 0>, /* D13 */ - <20 0 &gpio1 1 0>, /* D14 */ - <21 0 &gpio1 0 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi index 3fefd221c0ffc..6291fb277935f 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi @@ -8,6 +8,7 @@ #include #include "mimxrt1060_evk-pinctrl.dtsi" +#include #include / { @@ -95,28 +96,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 26 0>, /* A0 */ - <1 0 &gpio1 27 0>, /* A1 */ - <2 0 &gpio1 20 0>, /* A2 */ - <3 0 &gpio1 21 0>, /* A3 */ - <4 0 &gpio1 17 0>, /* A4 */ - <5 0 &gpio1 16 0>, /* A5 */ - <6 0 &gpio1 23 0>, /* D0 */ - <7 0 &gpio1 22 0>, /* D1 */ - <8 0 &gpio1 11 0>, /* D2 */ - <9 0 &gpio1 24 0>, /* D3 */ - <10 0 &gpio1 9 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 18 0>, /* D6 */ - <13 0 &gpio1 19 0>, /* D7 */ - <14 0 &gpio1 3 0>, /* D8 */ - <15 0 &gpio1 2 0>, /* D9 */ - <16 0 &gpio3 13 0>, /* D10 */ - <17 0 &gpio3 14 0>, /* D11 */ - <18 0 &gpio3 15 0>, /* D12 */ - <19 0 &gpio3 12 0>, /* D13 */ - <20 0 &gpio1 17 0>, /* D14 */ - <21 0 &gpio1 16 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts index c57860d7f221e..1b436ffd484e1 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts @@ -8,6 +8,7 @@ #include #include "mimxrt1064_evk-pinctrl.dtsi" +#include #include / { @@ -105,28 +106,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 26 0>, /* A0 */ - <1 0 &gpio1 27 0>, /* A1 */ - <2 0 &gpio1 20 0>, /* A2 */ - <3 0 &gpio1 21 0>, /* A3 */ - <4 0 &gpio1 17 0>, /* A4 */ - <5 0 &gpio1 16 0>, /* A5 */ - <6 0 &gpio1 23 0>, /* D0 */ - <7 0 &gpio1 22 0>, /* D1 */ - <8 0 &gpio1 11 0>, /* D2 */ - <9 0 &gpio1 24 0>, /* D3 */ - <10 0 &gpio1 9 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 18 0>, /* D6 */ - <13 0 &gpio1 19 0>, /* D7 */ - <14 0 &gpio1 3 0>, /* D8 */ - <15 0 &gpio1 2 0>, /* D9 */ - <16 0 &gpio3 13 0>, /* D10 */ - <17 0 &gpio3 14 0>, /* D11 */ - <18 0 &gpio3 15 0>, /* D12 */ - <19 0 &gpio3 12 0>, /* D13 */ - <20 0 &gpio1 17 0>, /* D14 */ - <21 0 &gpio1 16 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi index 91bd93ac8eaf8..93e08baee22a7 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi @@ -6,6 +6,7 @@ #include "mimxrt1170_evk-pinctrl.dtsi" #include +#include #include / { @@ -60,28 +61,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio9 9 0>, /* A0 */ - <1 0 &gpio9 10 0>, /* A1 */ - <2 0 &gpio9 11 0>, /* A2 */ - <3 0 &gpio9 12 0>, /* A3 */ - <4 0 &gpio9 8 0>, /* A4 */ - <5 0 &gpio9 7 0>, /* A5 */ - <6 0 &gpio11 12 0>, /* D0 */ - <7 0 &gpio11 11 0>, /* D1 */ - <8 0 &gpio11 13 0>, /* D2 */ - <9 0 &gpio9 3 0>, /* D3 */ - <10 0 &gpio9 5 0>, /* D4 */ - <11 0 &gpio9 4 0>, /* D5 */ - <12 0 &gpio8 31 0>, /* D6 */ - <13 0 &gpio9 13 0>, /* D7 */ - <14 0 &gpio9 6 0>, /* D8 */ - <15 0 &gpio9 0 0>, /* D9 */ - <16 0 &gpio9 28 0>, /* D10 */ - <17 0 &gpio9 29 0>, /* D11 */ - <18 0 &gpio9 30 0>, /* D12 */ - <19 0 &gpio9 27 0>, /* D13 */ - <20 0 &gpio12 4 0>, /* D14 */ - <21 0 &gpio12 5 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts index e6d9905bedaf9..9ac6bcd04cb7a 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts @@ -102,3 +102,7 @@ zephyr_udc1: &usb2{ tx-cal-45-dp-ohms = <6>; tx-cal-45-dm-ohms = <6>; }; + +&kpp { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml index bd7fedb8e97b3..9534ab199b1dd 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml @@ -31,4 +31,5 @@ supported: - usbd - sdhc - dac + - kpp vendor: nxp diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts index 4a5a7ab25c173..4ff556d70f400 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts @@ -100,3 +100,7 @@ zephyr_udc1: &usb2{ tx-cal-45-dp-ohms = <6>; tx-cal-45-dm-ohms = <6>; }; + +&kpp { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml index 6ec060575dc8c..5de44c44d720a 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml @@ -28,4 +28,5 @@ supported: - spi - uart - dac + - kpp vendor: nxp diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts index f0b56d3296ac6..ef1fbb07c3a54 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi" @@ -78,28 +79,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 5 0>, /* A0 */ - <1 0 &gpio0 6 0>, /* A1 */ - <2 0 &gpio0 19 0>, /* A2 */ - <3 0 &gpio0 13 0>, /* A3 */ - <4 0 &gpio4 22 0>, /* A4 */ - <5 0 &gpio4 21 0>, /* A5 */ - <6 0 &gpio4 31 0>, /* D0 */ - <7 0 &gpio4 30 0>, /* D1 */ - <8 0 &gpio4 20 0>, /* D2 */ - <9 0 &gpio4 23 0>, /* D3 */ - <10 0 &gpio4 24 0>, /* D4 */ - <11 0 &gpio4 25 0>, /* D5 */ - <12 0 &gpio4 26 0>, /* D6 */ - <13 0 &gpio4 27 0>, /* D7 */ - <14 0 &gpio4 28 0>, /* D8 */ - <15 0 &gpio4 29 0>, /* D9 */ - <16 0 &gpio5 0 0>, /* D10 */ - <17 0 &gpio5 1 0>, /* D11 */ - <18 0 &gpio5 2 0>, /* D12 */ - <19 0 &gpio5 3 0>, /* D13 */ - <20 0 &gpio4 22 0>, /* D14 */ - <21 0 &gpio4 21 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; /* diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts index 4b244bc4ef691..e216eb1650b1a 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts @@ -8,6 +8,7 @@ #include #include +#include #include #include "mimxrt685_evk-pinctrl.dtsi" @@ -102,28 +103,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 5 0>, /* A0 */ - <1 0 &gpio0 6 0>, /* A1 */ - <2 0 &gpio0 19 0>, /* A2 */ - <3 0 &gpio0 20 0>, /* A3 */ - <4 0 &gpio0 17 0>, /* A4 */ - <5 0 &gpio0 18 0>, /* A5 */ - <6 0 &gpio0 30 0>, /* D0 */ - <7 0 &gpio0 29 0>, /* D1 */ - <8 0 &gpio0 28 0>, /* D2 */ - <9 0 &gpio0 27 0>, /* D3 */ - <10 0 &gpio1 0 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 2 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 9 0>, /* D8 */ - <15 0 &gpio1 7 0>, /* D9 */ - <16 0 &gpio1 6 0>, /* D10 */ - <17 0 &gpio1 5 0>, /* D11 */ - <18 0 &gpio1 4 0>, /* D12 */ - <19 0 &gpio1 3 0>, /* D13 */ - <20 0 &gpio0 17 0>, /* D14 */ - <21 0 &gpio0 18 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index 47dfdcc20b996..700ef27896a64 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -45,7 +45,7 @@ bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank). The GPIO controller provides the option to route external input pad interrupts to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, -unless they are explicity configured to be directed to the WKPU interrupt +unless they are explicitly configured to be directed to the WKPU interrupt controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,s32-gpio.yaml`. To find information about which GPIOs are compatible with each interrupt @@ -239,7 +239,7 @@ Ethernet This board has a single instance of Ethernet Media Access Controller (EMAC) interfacing with a `NXP TJA1103`_ 100Base-T1 Ethernet PHY. Currently, there is -limited driver for this PHY that allows for overiding the default pin strapping configuration for +limited driver for this PHY that allows for overriding the default pin strapping configuration for the PHY (RMII, master, autonomous mode enabled, polarity correction enabled) to slave mode. diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index eea6fc3a4fbd4..9f4f1f3fefc40 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -6,6 +6,7 @@ #include #include "rd_rw612_bga-pinctrl.dtsi" +#include #include / { @@ -46,28 +47,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &hsgpio1 14 0>, /* A0 */ - <1 0 &hsgpio1 15 0>, /* A1 */ - <2 0 &hsgpio1 16 0>, /* A2 */ - <3 0 &hsgpio1 17 0>, /* A3 */ - <4 0 &hsgpio0 16 0>, /* A4 */ - <5 0 &hsgpio0 17 0>, /* A5 */ - <6 0 &hsgpio0 24 0>, /* D0 */ - <7 0 &hsgpio0 26 0>, /* D1 */ - <8 0 &hsgpio0 11 0>, /* D2 */ - <9 0 &hsgpio0 15 0>, /* D3 */ - <10 0 &hsgpio0 18 0>, /* D4 */ - <11 0 &hsgpio0 27 0>, /* D5 */ - <12 0 &hsgpio0 6 0>, /* D6 */ - <13 0 &hsgpio0 10 0>, /* D7 */ - <14 0 &hsgpio1 18 0>, /* D8 */ - <15 0 &hsgpio1 13 0>, /* D9 */ - <16 0 &hsgpio0 0 0>, /* D10 */ - <17 0 &hsgpio0 2 0>, /* D11 */ - <18 0 &hsgpio0 3 0>, /* D12 */ - <19 0 &hsgpio0 4 0>, /* D13 */ - <20 0 &hsgpio0 16 0>, /* D14 */ - <21 0 &hsgpio0 17 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi index f23b0ddd2e1b8..3ac4e89a02874 100644 --- a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi @@ -4,6 +4,7 @@ */ #include "rv32m1_vega_openisa_rv32m1-pinctrl.dtsi" +#include #include / { @@ -91,28 +92,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 11 0>, /* A0 */ - <1 0 &gpioc 12 0>, /* A1 */ - <2 0 &gpiob 9 0>, /* A2 */ - <3 0 &gpioe 4 0>, /* A3 */ - <4 0 &gpioe 10 0>, /* A4 */ - <5 0 &gpioe 11 0>, /* A5 */ - <6 0 &gpioa 25 0>, /* D0 */ - <7 0 &gpioa 26 0>, /* D1 */ - <8 0 &gpioa 27 0>, /* D2 */ - <9 0 &gpiob 13 0>, /* D3 */ - <10 0 &gpiob 14 0>, /* D4 */ - <11 0 &gpioa 30 0>, /* D5 */ - <12 0 &gpioa 31 0>, /* D6 */ - <13 0 &gpiob 1 0>, /* D7 */ - <14 0 &gpiob 2 0>, /* D8 */ - <15 0 &gpiob 3 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiob 7 0>, /* D12 */ - <19 0 &gpiob 4 0>, /* D13 */ - <20 0 &gpioc 9 0>, /* D14 */ - <21 0 &gpioc 10 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/others/esp32c3_supermini/doc/index.rst b/boards/others/esp32c3_supermini/doc/index.rst index 234129ef32c44..cf7e1841e05dd 100644 --- a/boards/others/esp32c3_supermini/doc/index.rst +++ b/boards/others/esp32c3_supermini/doc/index.rst @@ -5,7 +5,7 @@ Overview ESP32-C3-SUPERMINI is based on the ESP32-C3, a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, based on the open-source RISC-V architecture. This board also includes a Type-C USB Serial/JTAG port. -There may be multiple variations depending on the specific vendor. For more information a reasonbly well documented version of this board can be found at `ESP32-C3-SUPERMINI`_ +There may be multiple variations depending on the specific vendor. For more information a reasonably well documented version of this board can be found at `ESP32-C3-SUPERMINI`_ Hardware ******** diff --git a/boards/others/promicro_nrf52840/doc/index.rst b/boards/others/promicro_nrf52840/doc/index.rst index de0f284d63ada..d2e9f5ae31038 100644 --- a/boards/others/promicro_nrf52840/doc/index.rst +++ b/boards/others/promicro_nrf52840/doc/index.rst @@ -56,7 +56,7 @@ built in the usual way (see :ref:`build_an_application` for more details). Flashing ======== -The board is factory-programmed with Adafruit's UF2 booloader +The board is factory-programmed with Adafruit's UF2 bootloader #. Reset the board into the bootloader by bridging ground and RST 2 times quickly diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840.yaml b/boards/others/promicro_nrf52840/promicro_nrf52840.yaml index 0f8ccd9b1a283..ef54516b38766 100644 --- a/boards/others/promicro_nrf52840/promicro_nrf52840.yaml +++ b/boards/others/promicro_nrf52840/promicro_nrf52840.yaml @@ -9,7 +9,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - pwm - spi diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml index 7aa472b784d35..f5228a763eda2 100644 --- a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml @@ -9,7 +9,7 @@ toolchain: - gnuarmemb supported: - adc - - usb_device + - usbd - ble - pwm - spi diff --git a/boards/panasonic/pan1770_evb/pan1770_evb.dts b/boards/panasonic/pan1770_evb/pan1770_evb.dts index 6a4d6502583bd..09e26d9a1e42e 100644 --- a/boards/panasonic/pan1770_evb/pan1770_evb.dts +++ b/boards/panasonic/pan1770_evb/pan1770_evb.dts @@ -8,6 +8,7 @@ /dts-v1/; #include #include "pan1770_evb-pinctrl.dtsi" +#include #include / { @@ -82,28 +83,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio0 12 0>, /* D10 */ - <17 0 &gpio0 13 0>, /* D11 */ - <18 0 &gpio0 14 0>, /* D12 */ - <19 0 &gpio0 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/panasonic/pan1780_evb/pan1780_evb.dts b/boards/panasonic/pan1780_evb/pan1780_evb.dts index 9bf6d4344d976..c6360554ccef1 100644 --- a/boards/panasonic/pan1780_evb/pan1780_evb.dts +++ b/boards/panasonic/pan1780_evb/pan1780_evb.dts @@ -8,6 +8,7 @@ /dts-v1/; #include #include "pan1780_evb-pinctrl.dtsi" +#include #include / { @@ -82,28 +83,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio0 12 0>, /* D10 */ - <17 0 &gpio0 13 0>, /* D11 */ - <18 0 &gpio0 14 0>, /* D12 */ - <19 0 &gpio0 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts index 27bfbbc52e98c..e239b1a1c4ad6 100644 --- a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts @@ -19,3 +19,6 @@ zephyr,sram-secure-partition = &sram0_s; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi index 1ad125207eb2d..44c01804b5120 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "pan1783_nrf5340_cpuapp_common-pinctrl.dtsi" +#include #include / { @@ -98,28 +99,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { @@ -268,6 +269,3 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; - -/* Include default memory partition configuration file */ -#include diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi index 62df4a9d677b4..4e5207e732d3c 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "pan1783_nrf5340_cpunet-pinctrl.dtsi" +#include #include / { @@ -91,28 +92,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; /* These aliases are provided for compatibility with samples */ diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts index b47b14510fe0b..aefeb9561063d 100644 --- a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts @@ -19,3 +19,6 @@ zephyr,sram-secure-partition = &sram0_s; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts index 1bddfdb986292..c1155e2c35bd9 100644 --- a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts @@ -28,3 +28,6 @@ gpios = <&gpio0 19 0>, <&gpio0 21 0>; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/panasonic/panb511evb/Kconfig.panb511evb b/boards/panasonic/panb511evb/Kconfig.panb511evb deleted file mode 100644 index 12878fd47d4a0..0000000000000 --- a/boards/panasonic/panb511evb/Kconfig.panb511evb +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PANB511EVB - select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP || BOARD_PANB511EVB_NRF54L15_CPUAPP_NS - select SOC_NRF54L15_CPUFLPR if BOARD_PANB511EVB_NRF54L15_CPUFLPR || \ - BOARD_PANB511EVB_NRF54L15_CPUFLPR_XIP diff --git a/boards/panasonic/panb511evb/Kconfig b/boards/panasonic/panb611evb/Kconfig similarity index 89% rename from boards/panasonic/panb511evb/Kconfig rename to boards/panasonic/panb611evb/Kconfig index 7b00e24412160..93fcd9b78f980 100644 --- a/boards/panasonic/panb511evb/Kconfig +++ b/boards/panasonic/panb611evb/Kconfig @@ -1,9 +1,9 @@ # Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -# PANB511EVB configuration +# PANB611EVB configuration -if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS +if BOARD_PANB611EVB_NRF54L15_CPUAPP_NS DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) @@ -27,4 +27,4 @@ config NRF_TRUSTZONE_RAM_REGION_SIZE This abstraction allows us to configure TrustZone without depending on peripheral specific symbols. -endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS +endif # BOARD_PANB611EVB_NRF54L15_CPUAPP_NS diff --git a/boards/panasonic/panb511evb/Kconfig.defconfig b/boards/panasonic/panb611evb/Kconfig.defconfig similarity index 81% rename from boards/panasonic/panb511evb/Kconfig.defconfig rename to boards/panasonic/panb611evb/Kconfig.defconfig index 595e01692ccf7..6ad6d9426dbf0 100644 --- a/boards/panasonic/panb511evb/Kconfig.defconfig +++ b/boards/panasonic/panb611evb/Kconfig.defconfig @@ -5,14 +5,14 @@ DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition -if BOARD_PANB511EVB_NRF54L15_CPUAPP +if BOARD_PANB611EVB_NRF54L15_CPUAPP config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT -endif # BOARD_PANB511EVB_NRF54L15_CPUAPP +endif # BOARD_PANB611EVB_NRF54L15_CPUAPP -if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS +if BOARD_PANB611EVB_NRF54L15_CPUAPP_NS config HAS_BT_CTLR default BT @@ -28,4 +28,4 @@ config FLASH_LOAD_SIZE config BUILD_WITH_TFM default y -endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS +endif # BOARD_PANB611EVB_NRF54L15_CPUAPP_NS diff --git a/boards/panasonic/panb611evb/Kconfig.panb611evb b/boards/panasonic/panb611evb/Kconfig.panb611evb new file mode 100644 index 0000000000000..d941810714d7a --- /dev/null +++ b/boards/panasonic/panb611evb/Kconfig.panb611evb @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PANB611EVB + select SOC_NRF54L15_CPUAPP if BOARD_PANB611EVB_NRF54L15_CPUAPP || BOARD_PANB611EVB_NRF54L15_CPUAPP_NS + select SOC_NRF54L15_CPUFLPR if BOARD_PANB611EVB_NRF54L15_CPUFLPR || \ + BOARD_PANB611EVB_NRF54L15_CPUFLPR_XIP diff --git a/boards/panasonic/panb511evb/board.cmake b/boards/panasonic/panb611evb/board.cmake similarity index 92% rename from boards/panasonic/panb511evb/board.cmake rename to boards/panasonic/panb611evb/board.cmake index d6d51e58a39f6..3a7eb3103be84 100644 --- a/boards/panasonic/panb511evb/board.cmake +++ b/boards/panasonic/panb611evb/board.cmake @@ -7,7 +7,7 @@ elseif(CONFIG_SOC_NRF54L15_CPUFLPR) board_runner_args(jlink "--device=nRF54L15_RV32") endif() -if(CONFIG_BOARD_PANB511EVB_NRF54L15_CPUAPP_NS) +if(CONFIG_BOARD_PANB611EVB_NRF54L15_CPUAPP_NS) set(TFM_PUBLIC_KEY_FORMAT "full") endif() diff --git a/boards/panasonic/panb511evb/board.yml b/boards/panasonic/panb611evb/board.yml similarity index 50% rename from boards/panasonic/panb511evb/board.yml rename to boards/panasonic/panb611evb/board.yml index 6e2d60bf4a079..365e6156d5eaa 100644 --- a/boards/panasonic/panb511evb/board.yml +++ b/boards/panasonic/panb611evb/board.yml @@ -1,6 +1,6 @@ board: - name: panb511evb - full_name: PAN B511 Evaluation Board + name: panb611evb + full_name: PAN B611 Evaluation Board vendor: panasonic socs: - name: nrf54l15 @@ -18,10 +18,10 @@ runners: run: first groups: - boards: - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip + - panb611evb/nrf54l15/cpuapp + - panb611evb/nrf54l15/cpuapp/ns + - panb611evb/nrf54l15/cpuflpr + - panb611evb/nrf54l15/cpuflpr/xip '--erase': - runners: - nrfjprog @@ -30,10 +30,10 @@ runners: run: first groups: - boards: - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip + - panb611evb/nrf54l15/cpuapp + - panb611evb/nrf54l15/cpuapp/ns + - panb611evb/nrf54l15/cpuflpr + - panb611evb/nrf54l15/cpuflpr/xip '--reset': - runners: - nrfjprog @@ -42,7 +42,7 @@ runners: run: last groups: - boards: - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip + - panb611evb/nrf54l15/cpuapp + - panb611evb/nrf54l15/cpuapp/ns + - panb611evb/nrf54l15/cpuflpr + - panb611evb/nrf54l15/cpuflpr/xip diff --git a/boards/panasonic/panb511evb/doc/img/panb511evb.webp b/boards/panasonic/panb611evb/doc/img/panb611evb.webp similarity index 100% rename from boards/panasonic/panb511evb/doc/img/panb511evb.webp rename to boards/panasonic/panb611evb/doc/img/panb611evb.webp diff --git a/boards/panasonic/panb511evb/doc/index.rst b/boards/panasonic/panb611evb/doc/index.rst similarity index 57% rename from boards/panasonic/panb511evb/doc/index.rst rename to boards/panasonic/panb611evb/doc/index.rst index 25920e774820d..e9cf2d9778fc8 100644 --- a/boards/panasonic/panb511evb/doc/index.rst +++ b/boards/panasonic/panb611evb/doc/index.rst @@ -1,19 +1,19 @@ -.. zephyr:board:: panb511evb +.. zephyr:board:: panb611evb Overview ******** -The PAN B511 Evaluation Board (panb511evb) is a development tool -for the PAN B511 module which is based on the nRF54L15 chipset +The PAN B611 Evaluation Board (panb611evb) is a development tool +for the PAN B611 module which is based on the nRF54L15 chipset from Nordic Semiconductor. -More information about the PAN B511 Module Variants and Evaluation Board can be found +More information about the PAN B611 Module Variants and Evaluation Board can be found on the `product website`_. Usage ***** -You can find the `panb511evb user guide`_ for the PAN B511 Evaluation Board in the +You can find the `panb611evb user guide`_ for the PAN B611 Evaluation Board in the `Panasonic Wireless Connectivity Development Hub`_. The User Guide contains (amongst other things) detailed information about @@ -26,15 +26,15 @@ The User Guide contains (amongst other things) detailed information about and other things. -The schematics for the PANB511 Evaluation Boards are available in the -`download section PANB511`_ of the `Panasonic Wireless Connectivity Development Hub`_. +The schematics for the PANB611 Evaluation Boards are available in the +`download section PANB611`_ of the `Panasonic Wireless Connectivity Development Hub`_. Programming and Debugging ************************* .. zephyr:board-supported-runners:: -Applications for the ``panb511evb/nrf54l15/cpuapp`` board target can +Applications for the ``panb611evb/nrf54l15/cpuapp`` board target can be built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. @@ -42,5 +42,5 @@ building and running. .. target-notes:: .. _product website: https://industry.panasonic.eu/products/devices/wireless-connectivity/bluetooth-low-energy-modules .. _Panasonic Wireless Connectivity Development Hub: https://pideu.panasonic.de/development-hub/ -.. _panb511evb user guide: https://pideu.panasonic.de/development-hub/panb511/evaluation_board/user_guide/ -.. _download section PANB511: https://pideu.panasonic.de/development-hub/panb511/downloads/ +.. _panb611evb user guide: https://pideu.panasonic.de/development-hub/panb611/evaluation_board/user_guide/ +.. _download section PANB611: https://pideu.panasonic.de/development-hub/panb611/downloads/ diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi b/boards/panasonic/panb611evb/panb611evb_nrf54l15-pinctrl.dtsi similarity index 100% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi rename to boards/panasonic/panb611evb/panb611evb_nrf54l15-pinctrl.dtsi diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_common.dtsi b/boards/panasonic/panb611evb/panb611evb_nrf54l15_common.dtsi similarity index 76% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_common.dtsi rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_common.dtsi index fc300f888b92a..990ed6261f1cb 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_common.dtsi +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_common.dtsi @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "panb511evb_nrf54l15-pinctrl.dtsi" +#include "panb611evb_nrf54l15-pinctrl.dtsi" +#include / { leds { @@ -101,28 +102,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 6 0>, /* A0 */ - <1 0 &gpio1 7 0>, /* A1 */ - <2 0 &gpio1 11 0>, /* A2 */ - <3 0 &gpio1 12 0>, /* A3 */ - <4 0 &gpio1 13 0>, /* A4 */ - <5 0 &gpio1 14 0>, /* A5 */ - <6 0 &gpio1 4 0>, /* D0 */ - <7 0 &gpio1 5 0>, /* D1 */ - <8 0 &gpio0 0 0>, /* D2 */ - <9 0 &gpio1 2 0>, /* D3 */ - <10 0 &gpio1 3 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 13 0>, /* D6 */ - <13 0 &gpio1 14 0>, /* D7 */ - <14 0 &gpio1 15 0>, /* D8 */ - <15 0 &gpio2 7 0>, /* D9 */ - <16 0 &gpio2 10 0>, /* D10 */ - <17 0 &gpio2 8 0>, /* D11 */ - <18 0 &gpio2 9 0>, /* D12 */ - <19 0 &gpio2 6 0>, /* D13 */ - <20 0 &gpio1 9 0>, /* D14 */ - <21 0 &gpio1 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.dts b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.dts similarity index 68% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.dts rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.dts index 04616affd1461..25b838667289d 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.dts +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.dts @@ -7,11 +7,11 @@ /dts-v1/; #include -#include "panb511evb_nrf54l15_cpuapp_common.dtsi" +#include "panb611evb_nrf54l15_cpuapp_common.dtsi" / { - compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuapp"; - model = "Panasonic PAN B511 EVB nRF54L15 Application MCU"; + compatible = "panasonic-industrial-devices-europe-gmbh,panb611evb-cpuapp"; + model = "Panasonic PAN B611 EVB nRF54L15 Application MCU"; chosen { zephyr,code-partition = &slot0_partition; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.yaml similarity index 79% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.yaml index db252d56047d3..3bfef0b99b527 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp.yaml @@ -1,8 +1,8 @@ # Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -identifier: panb511evb/nrf54l15/cpuapp -name: PANB511-EVB-nRF54l15-Application +identifier: panb611evb/nrf54l15/cpuapp +name: PANB611-EVB-nRF54l15-Application type: mcu arch: arm toolchain: diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_common.dtsi similarity index 97% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_common.dtsi index 634f758d531a7..ba978a5412866 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_common.dtsi @@ -6,7 +6,7 @@ /* This file is common to the secure and non-secure domain */ -#include "panb511evb_nrf54l15_common.dtsi" +#include "panb611evb_nrf54l15_common.dtsi" / { chosen { diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_defconfig similarity index 100% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_defconfig diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.dts similarity index 90% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.dts index 4f5ea30331650..cebc30ff08996 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.dts @@ -9,11 +9,11 @@ #define USE_NON_SECURE_ADDRESS_MAP 1 #include -#include "panb511evb_nrf54l15_cpuapp_common.dtsi" +#include "panb611evb_nrf54l15_cpuapp_common.dtsi" / { - model = "Panasonic PAN B511 EVB nRF54L15 Application MCU"; - compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuapp"; + model = "Panasonic PAN B611 EVB nRF54L15 Application MCU"; + compatible = "panasonic-industrial-devices-europe-gmbh,panb611evb-cpuapp"; chosen { zephyr,code-partition = &slot0_ns_partition; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.yaml similarity index 74% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.yaml index 2a092dea13dff..dee107967bfc5 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns.yaml @@ -1,8 +1,8 @@ # Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -identifier: panb511evb/nrf54l15/cpuapp/ns -name: PANB511-EVB-nRF54l15-Application-Non-Secure +identifier: panb611evb/nrf54l15/cpuapp/ns +name: PANB611-EVB-nRF54l15-Application-Non-Secure type: mcu arch: arm toolchain: diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns_defconfig similarity index 100% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuapp_ns_defconfig diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.dts b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.dts similarity index 86% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.dts rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.dts index 5a238b48a6ba1..bd40a2f837be4 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.dts +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.dts @@ -6,11 +6,11 @@ /dts-v1/; #include -#include "panb511evb_nrf54l15_common.dtsi" +#include "panb611evb_nrf54l15_common.dtsi" / { - model = "Panasonic PAN B511 EVB nRF54L15 FLPR MCU"; - compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuflpr"; + model = "Panasonic PAN B611 EVB nRF54L15 FLPR MCU"; + compatible = "panasonic-industrial-devices-europe-gmbh,panb611evb-cpuflpr"; chosen { zephyr,console = &uart20; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.yaml b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.yaml similarity index 69% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.yaml rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.yaml index 481fcb00bd05d..d99c2f99aee62 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.yaml +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr.yaml @@ -1,8 +1,8 @@ # Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -identifier: panb511evb/nrf54l15/cpuflpr -name: PANB511-EVB-nRF54L15-Fast-Lightweight-Peripheral-Processor +identifier: panb611evb/nrf54l15/cpuflpr +name: PANB611-EVB-nRF54L15-Fast-Lightweight-Peripheral-Processor type: mcu arch: riscv toolchain: diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_defconfig b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_defconfig similarity index 100% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_defconfig rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_defconfig diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.dts b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip.dts similarity index 82% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.dts rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip.dts index f14f44e097597..7c506af954912 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.dts +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip.dts @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "panb511evb_nrf54l15_cpuflpr.dts" +#include "panb611evb_nrf54l15_cpuflpr.dts" &cpuflpr_sram { reg = <0x2002f000 DT_SIZE_K(68)>; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.yaml b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip.yaml similarity index 69% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.yaml rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip.yaml index e54c5a7b9fdd6..ec4984b963bf8 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.yaml +++ b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip.yaml @@ -1,8 +1,8 @@ # Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -identifier: panb511evb/nrf54l15/cpuflpr/xip -name: PANB511-EVB-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) +identifier: panb611evb/nrf54l15/cpuflpr/xip +name: PANB611-EVB-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) type: mcu arch: riscv toolchain: diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip_defconfig b/boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip_defconfig similarity index 100% rename from boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip_defconfig rename to boards/panasonic/panb611evb/panb611evb_nrf54l15_cpuflpr_xip_defconfig diff --git a/boards/panasonic/panb511evb/support/nrf54l15_cpuflpr.JLinkScript b/boards/panasonic/panb611evb/support/nrf54l15_cpuflpr.JLinkScript similarity index 100% rename from boards/panasonic/panb511evb/support/nrf54l15_cpuflpr.JLinkScript rename to boards/panasonic/panb611evb/support/nrf54l15_cpuflpr.JLinkScript diff --git a/boards/peregrine/sam4l_wm400_cape/doc/index.rst b/boards/peregrine/sam4l_wm400_cape/doc/index.rst index 586c7cb5f8b8f..4598abcd84bf6 100644 --- a/boards/peregrine/sam4l_wm400_cape/doc/index.rst +++ b/boards/peregrine/sam4l_wm400_cape/doc/index.rst @@ -6,7 +6,7 @@ Overview The SAM4L WM-400 Cape is a full featured design to enable IEEE 802.15.4 low power nodes. It is a Beaglebone Black cape concept with an Atmel AT86RF233 radio transceiver. User can develop Touch interface and have access to many -sensors and conectivity buses. +sensors and connectivity buses. Hardware ******** diff --git a/boards/phytec/phyboard_polis/doc/index.rst b/boards/phytec/phyboard_polis/doc/index.rst index f1229b4b17b27..bf80e7e0ab062 100644 --- a/boards/phytec/phyboard_polis/doc/index.rst +++ b/boards/phytec/phyboard_polis/doc/index.rst @@ -266,7 +266,7 @@ you can copy it from the output of the last command. u-boot=> cp.b 0x48000000 0x7e0000 27240 -And finaly starting the M4-Core at the right memory address: +And finally starting the M4-Core at the right memory address: .. code-block:: console diff --git a/boards/phytec/phyboard_pollux/doc/index.rst b/boards/phytec/phyboard_pollux/doc/index.rst index dee06c512d1e1..17fadbd781d2a 100644 --- a/boards/phytec/phyboard_pollux/doc/index.rst +++ b/boards/phytec/phyboard_pollux/doc/index.rst @@ -118,7 +118,7 @@ I2C --- There are multiple on-device I2C devices already connected to -I2C busses. +I2C buses. Some of these devices should not be used by the M7-Core if running the PHYTEC BSP on the A53-Core. diff --git a/boards/phytec/reel_board/dts/reel_board.dtsi b/boards/phytec/reel_board/dts/reel_board.dtsi index daa61da1c56cf..189b237234d5a 100644 --- a/boards/phytec/reel_board/dts/reel_board.dtsi +++ b/boards/phytec/reel_board/dts/reel_board.dtsi @@ -7,6 +7,7 @@ #include #include "reel_board-pinctrl.dtsi" +#include #include / { @@ -57,28 +58,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; aliases { diff --git a/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb b/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb index c5dd6ea59f480..abec19a51d95b 100644 Binary files a/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb and b/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb differ diff --git a/boards/qemu/cortex_r5/qemu_cortex_r5.dts b/boards/qemu/cortex_r5/qemu_cortex_r5.dts index b23e9534ed498..a071506d9ef6b 100644 --- a/boards/qemu/cortex_r5/qemu_cortex_r5.dts +++ b/boards/qemu/cortex_r5/qemu_cortex_r5.dts @@ -12,6 +12,11 @@ model = "QEMU Cortex-R5"; compatible = "xlnx,zynqmp-qemu"; + sram0: memory@4000000 { + compatible = "mmio-sram"; + reg = <0x4000000 DT_SIZE_M(64)>; + }; + chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; diff --git a/boards/qemu/rx/qemu_rx.dts b/boards/qemu/rx/qemu_rx.dts index 4b2f7672769fd..c7855d739663a 100644 --- a/boards/qemu/rx/qemu_rx.dts +++ b/boards/qemu/rx/qemu_rx.dts @@ -11,7 +11,7 @@ / { model = "Renesas QEMU"; - compatible = "qemu,rx","renesas,rxv1"; + compatible = "qemu,rx"; chosen { zephyr,sram = &sram0; diff --git a/boards/raspberrypi/rpi_debug_probe/Kconfig b/boards/raspberrypi/rpi_debug_probe/Kconfig new file mode 100644 index 0000000000000..95ae50fa0f00d --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_DEBUG_PROBE + select RP2_FLASH_W25Q080 diff --git a/boards/raspberrypi/rpi_debug_probe/Kconfig.defconfig b/boards/raspberrypi/rpi_debug_probe/Kconfig.defconfig new file mode 100644 index 0000000000000..982d00f520cf4 --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RPI_DEBUG_PROBE + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_RPI_DEBUG_PROBE diff --git a/boards/raspberrypi/rpi_debug_probe/Kconfig.rpi_debug_probe b/boards/raspberrypi/rpi_debug_probe/Kconfig.rpi_debug_probe new file mode 100644 index 0000000000000..449b3270b2d4f --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/Kconfig.rpi_debug_probe @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_DEBUG_PROBE + select SOC_RP2040 diff --git a/boards/raspberrypi/rpi_debug_probe/board.cmake b/boards/raspberrypi/rpi_debug_probe/board.cmake new file mode 100644 index 0000000000000..5a702fc5e030f --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/board.cmake @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# Adapted from boards/raspberrypi/rpi_pico/board.cmake + +# This configuration allows selecting what debug adapter debugging rpi_pico +# by a command-line argument. +# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd' +# adapter described in "Getting started with Raspberry Pi Pico". +# And any other SWD debug adapter might also be usable with this configuration. + +# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments. +# e.g.) west build -b rpi_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd +# The value is treated as a part of an interface file name that +# the debugger's configuration file. +# The value must be the 'stem' part of the name of one of the files +# in the openocd interface configuration file. +# The setting is store to CMakeCache.txt. +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + +board_runner_args(jlink "--device=RP2040_M0_0") +board_runner_args(uf2 "--board-id=RPI-RP2") +board_runner_args(pyocd "--target=rp2040") + +# Default runner should be listed first +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/raspberrypi/rpi_debug_probe/board.yml b/boards/raspberrypi/rpi_debug_probe/board.yml new file mode 100644 index 0000000000000..1593326162740 --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/board.yml @@ -0,0 +1,6 @@ +board: + name: rpi_debug_probe + full_name: Raspberry Pi Debug Probe + vendor: raspberrypi + socs: + - name: rp2040 diff --git a/boards/raspberrypi/rpi_debug_probe/doc/img/rpi_debug_probe.webp b/boards/raspberrypi/rpi_debug_probe/doc/img/rpi_debug_probe.webp new file mode 100644 index 0000000000000..4387c0a1e1bf6 Binary files /dev/null and b/boards/raspberrypi/rpi_debug_probe/doc/img/rpi_debug_probe.webp differ diff --git a/boards/raspberrypi/rpi_debug_probe/doc/index.rst b/boards/raspberrypi/rpi_debug_probe/doc/index.rst new file mode 100644 index 0000000000000..358dc8744eec1 --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/doc/index.rst @@ -0,0 +1,118 @@ +.. zephyr:board:: rpi_debug_probe + +Overview +******** + +The `Raspberry Pi Debug Probe`_ is a board based on the RP2040 +microcontroller from Raspberry Pi Ltd. The board exposes four GPIO pins +via two 3-pin connectors, and the board has a USB micro B connector. + +.. note:: + + This is for using the Raspberry Pi Debug Probe board as a general-purpose + microcontroller board, not using it as a tool for debugging other boards. + See below for how to load the board with the official firmware, which is + needed if you would use this board for its original debugging purpose. + + +Hardware +******** + +- Microcontroller Raspberry Pi RP2040, with a max frequency of 133 MHz +- Dual ARM Cortex M0+ cores +- 264 kByte SRAM +- 2 Mbyte QSPI flash +- 6 GPIO pins, of which 4 are exposed via 3-pin connectors +- UART +- USB micro B connector +- Boot button +- 5 user LEDs + + +Default Zephyr Peripheral Mapping +================================= + +.. rst-class:: rst-columns + + - LED D1 red : GPIO2 + - LED D2 green (close to UART connector) : GPIO7 + - LED D3 yellow (close to UART connector) : GPIO8 + - LED D4 green (close to DBUG connector) : GPIO15 + - LED D5 yellow (close to DBUG connector) : GPIO16 + - Connector J2 (UART) pin 1 (TX) : GPIO4 UART1 + - Connector J2 (UART) pin 3 (RX) : GPIO6 + - Connector J2 (UART) pin 3 (RX) via input buffer : GPIO5 UART1 + - Connector J3 (DBUG) pin 1 (CLK) : GPIO12 + - Connector J3 (DBUG) pin 3 (DIO) : GPIO14 + - Connector J3 (DBUG) pin 3 (DIO) via input buffer : GPIO13 + - Connector J4 pin 1 : GPIO0 + - Connector J4 pin 3 : GPIO1 + +The pins in the "UART" and "DBUG" connectors are using 100 Ohm +series resistors. + +The connector J4 is not populated by default, so you need to solder +a 3-pin header to the board in order to use that connector. + +See also `schematic`_. + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +By default programming is done via the USB connector. +Press and hold the BOOTSEL button when connecting the board to your +computer. It will appear as a USB mass-storage device named "RPI-RP2". +Building your application will result in a :file:`build/zephyr/zephyr.uf2` file. +Drag and drop the file to the USB mass storage unit, and the board +will be reprogrammed. + +It is also possible to program and debug the board via the SWDIO and SWCLK pads, +exposed as testpads on the back of the board. You need to solder connectors to the pads. +Then a separate programming hardware tool is required, and +for example the :command:`openocd` software is used. Typically the +``OPENOCD`` and ``OPENOCD_DEFAULT_PATH`` +values should be set when building, and the ``--runner openocd`` +argument should be used when flashing. +For more details on programming RP2040-based boards, see +:ref:`rpi_pico_programming_and_debugging`. + +If you would like to restore the official firmware on the Debug Probe, +download the `latest firmware`_. + + +Flashing +======== + +To run the :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: rpi_debug_probe + :goals: build flash + +Try also the :zephyr:code-sample:`hello_world` and +:zephyr:code-sample:`usb-cdc-acm-console` samples. + + +References +********** + +.. target-notes:: + +.. _Raspberry Pi Debug Probe: + https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html + +.. _latest firmware: + https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#updating-the-firmware-on-the-debug-probe + +.. _schematic: + https://datasheets.raspberrypi.com/debug/raspberry-pi-debug-probe-schematics.pdf diff --git a/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe-pincontrol.dtsi b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe-pincontrol.dtsi new file mode 100644 index 0000000000000..404032c9ddc82 --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe-pincontrol.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart1_default: uart1_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; +}; diff --git a/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe.dts b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe.dts new file mode 100644 index 0000000000000..43fc04a15e420 --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe.dts @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2022 Peter Johanson + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rpi_debug_probe-pincontrol.dtsi" + +/ { + model = "Raspberry Pi Debug Probe"; + compatible = "raspberry_pi,debug_probe"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + led0 = &red_led; + }; + + leds: leds { + compatible = "gpio-leds"; + + red_led: red_led { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Red LED D1"; + }; + + green_led_uart: green_led_uart { + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + label = "Green LED UART D2"; + }; + + yellow_led_uart: yellow_led_uart { + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + label = "Yellow LED UART D3"; + }; + + green_led_dbug: green_led_dbug { + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + label = "Green LED DBUG D4"; + }; + + yellow_led_dbug: yellow_led_dbug { + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + label = "Yellow LED DBUG D5"; + }; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(2)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 2 MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(2) - 0x100)>; + read-only; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&uart1 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe.yaml b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe.yaml new file mode 100644 index 0000000000000..111e6e4ee5958 --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe.yaml @@ -0,0 +1,19 @@ +identifier: rpi_debug_probe +name: Raspberry Pi Debug Probe +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - clock + - counter + - dma + - flash + - gpio + - hwinfo + - pwm + - uart + - watchdog diff --git a/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe_defconfig b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe_defconfig new file mode 100644 index 0000000000000..070226ea79889 --- /dev/null +++ b/boards/raspberrypi/rpi_debug_probe/rpi_debug_probe_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/raspberrypi/rpi_pico/board.yml b/boards/raspberrypi/rpi_pico/board.yml index c7378a328018a..cd3858f77bffd 100644 --- a/boards/raspberrypi/rpi_pico/board.yml +++ b/boards/raspberrypi/rpi_pico/board.yml @@ -3,6 +3,9 @@ board: full_name: Raspberry Pi Pico vendor: raspberrypi socs: - - name: rp2040 - variants: - - name: w + - name: rp2040 + variants: + - name: w + variants: + - name: mcuboot + - name: mcuboot diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.dts b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.dts new file mode 100644 index 0000000000000..c07b478eebd2e --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.dts @@ -0,0 +1,9 @@ +#include "rpi_pico.dts" + +/delete-node/ &code_partition; +#include +/ { + chosen { + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.yaml new file mode 100644 index 0000000000000..217130faea82a --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot.yaml @@ -0,0 +1,23 @@ +identifier: rpi_pico/rp2040/mcuboot +name: Raspberry Pi Pico - MCUboot +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio + - adc + - i2c + - spi + - hwinfo + - watchdog + - pwm + - flash + - dma + - counter + - clock + - usbd diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot_defconfig new file mode 100644 index 0000000000000..aaaa51cbdb989 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_mcuboot_defconfig @@ -0,0 +1,10 @@ +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.dts b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.dts new file mode 100644 index 0000000000000..266fd2b3397fa --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.dts @@ -0,0 +1,9 @@ +#include "rpi_pico_rp2040_w.dts" + +/delete-node/ &code_partition; +#include +/ { + chosen { + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.yaml new file mode 100644 index 0000000000000..9471ae9fdd95b --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot.yaml @@ -0,0 +1,23 @@ +identifier: rpi_pico/rp2040/w/mcuboot +name: Raspberry Pi Pico W - MCUboot +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio + - adc + - i2c + - spi + - hwinfo + - watchdog + - pwm + - flash + - dma + - pio + - counter + - clock diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot_defconfig new file mode 100644 index 0000000000000..aaaa51cbdb989 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_mcuboot_defconfig @@ -0,0 +1,10 @@ +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 index 6e7a1a4456953..26bae1a7fdf19 100644 --- a/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 +++ b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 @@ -3,4 +3,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_RPI_PICO2 - select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33 || BOARD_RPI_PICO2_RP2350A_M33_W + select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33 || BOARD_RPI_PICO2_RP2350A_M33_W || BOARD_RPI_PICO2_RP2350A_M33_MCUBOOT || BOARD_RPI_PICO2_RP2350A_M33_W_MCUBOOT diff --git a/boards/raspberrypi/rpi_pico2/board.yml b/boards/raspberrypi/rpi_pico2/board.yml index 46364e8cbd086..54d29f785ff22 100644 --- a/boards/raspberrypi/rpi_pico2/board.yml +++ b/boards/raspberrypi/rpi_pico2/board.yml @@ -3,7 +3,12 @@ board: full_name: Raspberry Pi Pico 2 vendor: raspberrypi socs: - - name: rp2350a - variants: - - name: w - cpucluster: m33 + - name: rp2350a + variants: + - name: w + cpucluster: m33 + variants: + - name: mcuboot + cpucluster: m33 + - name: mcuboot + cpucluster: m33 diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi index 3b49981114797..51076a57dd73d 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi @@ -10,7 +10,6 @@ #include #include "rpi_pico2-pinctrl.dtsi" -#include "../common/rpi_pico-led.dtsi" / { chosen { diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts index f96491f44e2e5..f7238b128cbfb 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts @@ -20,3 +20,4 @@ * implemented) Hazard3 cores. */ #include "rpi_pico2.dtsi" +#include "../common/rpi_pico-led.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.dts b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.dts new file mode 100644 index 0000000000000..f5c34367c1ce8 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +/* The build system assumes that there's a cpucluster-specific file. + * + * This file provides composition of the device tree: + * 1. The common features of the SoC + * 2. Core-specific configuration. + * 3. Board-specific configuration. + */ +#include +#include + +/* there's nothing specific to the Cortex-M33 cores vs the (not yet + * implemented) Hazard3 cores. + */ +#include "rpi_pico2.dtsi" + +/* Partitioning for the RP2350A-M33 board using 4M flash. + */ +#include +/ { + chosen { + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.yaml new file mode 100644 index 0000000000000..a6febee0bae9a --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot.yaml @@ -0,0 +1,22 @@ +identifier: rpi_pico2/rp2350a/m33/mcuboot +name: Raspberry Pi Pico 2 (Cortex-M33) - MCUboot +type: mcu +arch: arm +flash: 4096 +ram: 520 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - usbd + - watchdog diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot_defconfig new file mode 100644 index 0000000000000..4da77bdb95c25 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_mcuboot_defconfig @@ -0,0 +1,13 @@ +# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores +# are in use, but Zephyr does not support providing a qualifier-agnostic +# _defconfig file. +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.dts b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.dts new file mode 100644 index 0000000000000..67d63dfc8024a --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.dts @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2025 Magpie Embedded + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +/* The build system assumes that there's a cpucluster-specific file. + * + * This file provides composition of the device tree: + * 1. The common features of the SoC + * 2. Core-specific configuration. + * 3. Board-specific configuration. + */ +#include +#include + +/* there's nothing specific to the Cortex-M33 cores vs the (not yet + * implemented) Hazard3 cores. + */ +#include "rpi_pico2.dtsi" + +&pinctrl { + pio0_spi0_default: pio0_spi0_default { + /* gpio 25 is used for chip select, not assigned to the PIO */ + group1 { + pinmux = ; + }; + }; + + airoc_wifi_default: airoc_wifi_default { + /* Control of GPIO24 is done through the WiFi driver */ + group1 { + pinmux = ; + input-enable; + }; + }; + + airoc_wifi_host_wake: airoc_wifi_host_wake { + /* Assign GPIO24 to SIO (GPIO) for use as an interrupt source */ + group1 { + pinmux = ; + input-enable; + }; + }; +}; + +&pio0 { + status = "okay"; + + pio0_spi0: pio0_spi0 { + compatible = "raspberrypi,pico-spi-pio"; + clocks = < &clocks RPI_PICO_CLKID_CLK_SYS >; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + clk-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + sio-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pio0_spi0_default>; + pinctrl-names = "default"; + status = "okay"; + + airoc-wifi@0 { + compatible = "infineon,airoc-wifi"; + reg = < 0 >; + wifi-reg-on-gpios = < &gpio0 23 GPIO_ACTIVE_HIGH >; + bus-select-gpios = < &gpio0 24 GPIO_ACTIVE_HIGH >; + wifi-host-wake-gpios = < &gpio0 24 GPIO_ACTIVE_HIGH >; + spi-max-frequency = < 10000000 >; + spi-half-duplex; + spi-data-irq-shared; + pinctrl-0 = <&airoc_wifi_default>; + pinctrl-1 = <&airoc_wifi_host_wake>; + pinctrl-names = "default", "host_wake"; + status = "okay"; + }; + }; +}; + +/* Partitioning for the RP2350A-M33 board using 4M flash. + */ +#include +/ { + chosen { + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.yaml new file mode 100644 index 0000000000000..6efa0e2922da9 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot.yaml @@ -0,0 +1,22 @@ +identifier: rpi_pico2/rp2350a/m33/w/mcuboot +name: Raspberry Pi Pico 2 (Cortex-M33) WiFi - MCUboot +type: mcu +arch: arm +flash: 4096 +ram: 520 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog + - wifi diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot_defconfig new file mode 100644 index 0000000000000..4da77bdb95c25 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_mcuboot_defconfig @@ -0,0 +1,13 @@ +# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores +# are in use, but Zephyr does not support providing a qualifier-agnostic +# _defconfig file. +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi b/boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi index aa07ccff7c4b3..b5a2773b54072 100644 --- a/boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi +++ b/boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi @@ -185,6 +185,3 @@ zephyr_udc0: &usbd { status = "okay"; }; - -/* Include default memory partition configuration file */ -#include diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts index 8bcae1610dbb2..1b9bf1fa37d66 100644 --- a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts @@ -35,3 +35,6 @@ #include "nrf70_common_5g.dtsi" }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.yaml b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.yaml index 90e1c1cde5107..d5ecd05ff73ee 100644 --- a/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.yaml +++ b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.yaml @@ -12,8 +12,7 @@ toolchain: - zephyr - gnuarmemb supported: - - usb_device - - usb_cdc + - usbd - ble - pwm - watchdog diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst index eadb5fad4d2d3..e67ce7e735d05 100644 --- a/boards/raytac/mdbt50q_db_33/doc/index.rst +++ b/boards/raytac/mdbt50q_db_33/doc/index.rst @@ -31,12 +31,12 @@ Hardware - Module Demo Board build by MDBT50Q-512K - Nordic nRF52833 SoC Solution - A recommended 3rd-party module by Nordic Semiconductor. -- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified +- BT5.2&BT5.1&BT5 Bluetooth Specification Certified - Supports BT5 Long Range Features -- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC +- Certifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC - 32-bit ARM® Cortex™ M4F CPU - 512kB Flash Memory/128kB RAM -- RoHs & Reach Compiant. +- RoHs & Reach Compliant. - 42 GPIO - Chip Antenna - Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst index d656eb6e4c91c..99c6421943648 100644 --- a/boards/raytac/mdbt50q_db_40/doc/index.rst +++ b/boards/raytac/mdbt50q_db_40/doc/index.rst @@ -31,12 +31,12 @@ Hardware - Module Demo Board build by MDBT50Q-1MV2 - Nordic nRF52840 SoC Solution Version: 2 - A recommended 3rd-party module by Nordic Semiconductor. -- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified +- BT5.2&BT5.1&BT5 Bluetooth Specification Certified - Supports BT5 Long Range Features -- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC +- Certifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC - 32-bit ARM® Cortex™ M4F CPU - 1MB Flash Memory/256kB RAM -- RoHs & Reach Compiant. +- RoHs & Reach Compliant. - 48 GPIO - Chip Antenna - Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB diff --git a/boards/raytac/mdbt53_db_40/doc/index.rst b/boards/raytac/mdbt53_db_40/doc/index.rst index 3b0e9b221be58..e9beb4f4661e2 100644 --- a/boards/raytac/mdbt53_db_40/doc/index.rst +++ b/boards/raytac/mdbt53_db_40/doc/index.rst @@ -56,7 +56,7 @@ Hardware - Supports Bluetooth Direction Finding & Mesh - Supports Bluetooth low energy audio - Certifications: FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC -- RoHs & Reach Compiant. +- RoHs & Reach Compliant. - 48 GPIO - Chip Antenna - Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts index aed84474a38b5..20808f45c83a2 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts @@ -25,3 +25,6 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts index f8a881736619a..ada70006880a1 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts @@ -204,6 +204,3 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; - -/* Include default memory partition configuration file */ -#include diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts index de907f029e70b..332a163d07a75 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts @@ -18,3 +18,6 @@ zephyr,code-partition = &slot0_ns_partition; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/raytac/mdbt53v_db_40/doc/index.rst b/boards/raytac/mdbt53v_db_40/doc/index.rst index bd8584b78332a..842c88a9a3636 100644 --- a/boards/raytac/mdbt53v_db_40/doc/index.rst +++ b/boards/raytac/mdbt53v_db_40/doc/index.rst @@ -55,8 +55,8 @@ Hardware - Supports BT5 Long Range Features - Supports Bluetooth Direction Finding & Mesh - Supports Bluetooth low energy audio -- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC -- RoHs & Reach Compiant. +- Certifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC +- RoHs & Reach Compliant. - 25 GPIO - Chip Antenna - Interfaces: SPI, UART, I2C, I2S, PWM, ADC, and NFC diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts index 6b5890d747266..a1ebf2d3b1050 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts @@ -20,3 +20,6 @@ zephyr,sram-non-secure-partition = &sram0_ns; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts index 658f3bf515d92..cd33fc0d0f844 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts @@ -157,6 +157,3 @@ &ieee802154 { status = "okay"; }; - -/* Include default memory partition configuration file */ -#include diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts index df5af5e9c3a20..e196d21e1580e 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts @@ -18,3 +18,6 @@ zephyr,code-partition = &slot0_ns_partition; }; }; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts index a5c4aa39c4d36..a8d73b802a7ca 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts @@ -6,6 +6,7 @@ /dts-v1/; #include #include "da1469x_dk_pro-pinctrl.dtsi" +#include #include / { @@ -49,28 +50,28 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = - <0 0 &gpio1 9 0>, /* A0 */ - <1 0 &gpio0 25 0>, /* A1 */ - <2 0 &gpio0 8 0>, /* A2 */ - <3 0 &gpio0 9 0>, /* A3 */ - <4 0 &gpio1 13 0>, /* A4 */ - <5 0 &gpio1 12 0>, /* A5 */ - <6 0 &gpio1 2 0>, /* D0 */ - <7 0 &gpio1 3 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 7 0>, /* D4 */ - <11 0 &gpio1 8 0>, /* D5 */ - <12 0 &gpio0 17 0>, /* D6 */ - <13 0 &gpio0 18 0>, /* D7 */ - <14 0 &gpio0 19 0>, /* D8 */ - <15 0 &gpio0 20 0>, /* D9 */ - <16 0 &gpio0 21 0>, /* D10 */ - <17 0 &gpio0 24 0>, /* D11 */ - <18 0 &gpio0 26 0>, /* D12 */ - <19 0 &gpio0 27 0>, /* D13 */ - <20 0 &gpio0 28 0>, /* D14 */ - <21 0 &gpio0 29 0>; /* D15 */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; aliases { diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts index 6004c429c1e7e..0a52762258b24 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.dts +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts @@ -21,6 +21,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -161,3 +162,7 @@ }; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml index 8d0e59f9c7043..fc6a33639a4c6 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.dts b/boards/renesas/ek_ra2l1/ek_ra2l1.dts index af8a217ea40eb..2821bae5c8b6a 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1.dts +++ b/boards/renesas/ek_ra2l1/ek_ra2l1.dts @@ -28,6 +28,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -113,3 +114,7 @@ interrupts = <15 1>; status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4c1/doc/index.rst b/boards/renesas/ek_ra4c1/doc/index.rst index 3d578a57c2475..6fd9d0d663a80 100644 --- a/boards/renesas/ek_ra4c1/doc/index.rst +++ b/boards/renesas/ek_ra4c1/doc/index.rst @@ -83,7 +83,7 @@ Flashing ======== Program can be flashed to EK-RA4C1 via the on-board SEGGER J-Link debugger. -SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/ +SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/ To flash the program to board diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index 6723f22e3315f..820e4b803a23d 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -23,6 +23,7 @@ zephyr,shell-uart = &uart0; zephyr,canbus = &canfd0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -213,3 +214,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml index b8f7c201c5719..8d7b490792b7a 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml @@ -13,4 +13,5 @@ supported: - watchdog - counter - i3c + - crc vendor: renesas diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.dts b/boards/renesas/ek_ra4l1/ek_ra4l1.dts index 3f7e15acd91a4..348c360c8d86e 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.dts +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.dts @@ -22,6 +22,7 @@ zephyr,console = &uart5; zephyr,shell-uart = &uart5; zephyr,canbus = &canfd0; + zephyr,crc = &crc; }; leds { @@ -225,3 +226,7 @@ }; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1.dts b/boards/renesas/ek_ra4m1/ek_ra4m1.dts index 054adf4c92517..c19d82e5623ed 100644 --- a/boards/renesas/ek_ra4m1/ek_ra4m1.dts +++ b/boards/renesas/ek_ra4m1/ek_ra4m1.dts @@ -21,6 +21,7 @@ zephyr,console = &uart1; zephyr,shell-uart = &uart1; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -139,3 +140,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1.yaml b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml index af2564df95f7b..94bb33605d4f6 100644 --- a/boards/renesas/ek_ra4m1/ek_ra4m1.yaml +++ b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index a3ade121275a5..a7e6135d43e5f 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -56,6 +57,8 @@ aliases { led0 = &led1; + led1 = &led2; + led2 = &led3; sw0 = &button0; sw1 = &button1; watchdog0 = &wdt; @@ -188,3 +191,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index 384da60afca1b..a8a7fec8bcddf 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -188,3 +189,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts index 7ab31de3e89eb..9a4c3742de6e0 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1.dts +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.dts @@ -21,6 +21,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -123,3 +124,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi index f8065c394f96d..df7957e666b92 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi +++ b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi @@ -54,4 +54,16 @@ ; }; }; + + qspi_default: qspi_default { + group1 { + /* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */ + psels = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 7d4911bb9da2a..8f80aac2a0053 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -24,6 +24,7 @@ zephyr,shell-uart = &uart0; zephyr,canbus = &canfd0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -189,3 +190,21 @@ &wdt { status = "okay"; }; + +&qspi0 { + pinctrl-0 = <&qspi_default>; + pinctrl-names = "default"; + status = "okay"; + + at25sf128a: qspi-nor-flash@60000000 { + compatible = "renesas,ra-qspi-nor"; + reg = <0x60000000 DT_SIZE_M(16)>; + status = "okay"; + write-block-size = <1>; + erase-block-size = <4096>; + }; +}; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index 00fd4ff32677c..69a641ed3ac57 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -23,6 +23,7 @@ zephyr,console = &uart8; zephyr,shell-uart = &uart8; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -163,3 +164,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml index 29b29a4efb83b..0750507650619 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml @@ -13,4 +13,5 @@ supported: - usbd - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 46fcc3ad44281..88630e21cc194 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -23,6 +23,7 @@ zephyr,console = &uart7; zephyr,shell-uart = &uart7; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -159,3 +160,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi index b6236c0199a54..1e1c0d7df327b 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi @@ -85,4 +85,16 @@ drive-strength = "high"; }; }; + + qspi_default: qspi_default { + group1 { + /* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */ + psels = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index 409f0549ff30b..c67d8710b850c 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -23,6 +23,7 @@ zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -214,3 +215,21 @@ status = "okay"; }; }; + +&qspi0 { + pinctrl-0 = <&qspi_default>; + pinctrl-names = "default"; + status = "okay"; + + mx25l25645g: qspi-nor-flash@60000000 { + compatible = "renesas,ra-qspi-nor"; + reg = <0x60000000 DT_SIZE_M(32)>; + status = "okay"; + write-block-size = <1>; + erase-block-size = <4096>; + }; +}; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m4/Kconfig.defconfig b/boards/renesas/ek_ra6m4/Kconfig.defconfig new file mode 100644 index 0000000000000..823d16c796cfb --- /dev/null +++ b/boards/renesas/ek_ra6m4/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EK_RA6M4 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config OUTPUT_RPD + default y + +endif # NETWORKING + +endif # BOARD_EK_RA6M4 diff --git a/boards/renesas/ek_ra6m4/board.cmake b/boards/renesas/ek_ra6m4/board.cmake index e6b80a0fddd51..7ccecc26e799f 100644 --- a/boards/renesas/ek_ra6m4/board.cmake +++ b/boards/renesas/ek_ra6m4/board.cmake @@ -3,6 +3,12 @@ board_runner_args(jlink "--device=R7FA6M4AF") board_runner_args(pyocd "--target=R7FA6M4AF") +if(CONFIG_OUTPUT_RPD) + board_runner_args(rfp "--device=RA" "--tool=jlink" "--interface=swd" "--erase" "--rpd-file=${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.rpd") +else() + board_runner_args(rfp "--device=RA" "--tool=jlink" "--interface=swd" "--erase") +endif() include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst index 2dce8bb0fc632..d954c2b8156a6 100644 --- a/boards/renesas/ek_ra6m4/doc/index.rst +++ b/boards/renesas/ek_ra6m4/doc/index.rst @@ -89,6 +89,28 @@ built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. +.. note:: + + In applications using ethernet, ethernet buffers must be placed in non-secure RAM. + This requires configuration of the Implementation Defined Attribution Unit (IDAU), + which must be applied by partition memory using Renesas Flash Programmer. + +Partition Memory +================ + +Renesas Flash Programmer is available at (`Renesas Flash Programmer Download`_). +Once downloaded and installed, check rfp-cli is available or set rfp-cli path manually. + +Renesas partition data file will be available at build/zephyr/zephyr.rpd. +Connect jumper J6 then run Renesas Flash Programmer. + +To partition memory manually, execute: + + .. code-block:: console + + # From the root of the zephyr repository + rfp-cli -device ra -tool jlink -fo boundary-file build/zephyr/zephyr.rpd -p + Flashing ======== @@ -101,12 +123,18 @@ To flash the program to board 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_ -3. Execute west command +3. Execute west command to flash using jlink runner .. code-block:: console west flash -r jlink +4. Or flash using rfp runner, this will partition memory then flash zephyr image. + + .. code-block:: console + + west flash -r rfp + Debugging ========= @@ -128,6 +156,7 @@ References ********** - `EK-RA6M4 Website`_ - `RA6M4 MCU group Website`_ +- `RA6 Ethernet Controller configuration`_ .. _EK-RA6M4 Website: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m4-evaluation-kit-ra6m4-mcu-group @@ -143,3 +172,9 @@ References .. _Segger Ozone Download: https://www.segger.com/downloads/jlink#Ozone + +.. _Renesas Flash Programmer Download: + https://www.renesas.com/en/software-tool/renesas-flash-programmer-programming-gui + +.. _RA6 Ethernet Controller configuration: + https://www.renesas.com/en/blogs/configuration-issues-ra6-ethernet-controller#document diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi index 081e3a74621bf..741ece637587a 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi @@ -55,11 +55,11 @@ }; }; - pwm1_default: pwm1_default { + pwm0_default: pwm0_default { group1 { - /* GTIOC1A GTIOC1B */ - psels = , - ; + /* GTIOC0A GTIOC0B */ + psels = , + ; }; }; @@ -70,4 +70,32 @@ drive-strength = "high"; }; }; + + ether_default: ether_default { + group1 { + psels = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* RMII0_TXD_EN_B */ + , /* RMII0_TXD1_BR */ + , /* RMII0_TXD0_B */ + , /* REF50CK0_B */ + , /* RMII0_RXD0_B */ + , /* RMII0_RXD1_B */ + , /* RMII0_RX_ER_B */ + ; /* RMII0_CRS_DV_B */ + drive-strength = "high"; + }; + }; + + qspi_default: qspi_default { + group1 { + /* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */ + psels = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index c6ed4cbcff021..3e7519d7b7f5a 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -24,6 +24,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -238,8 +239,8 @@ status = "okay"; }; -&pwm1 { - pinctrl-0 = <&pwm1_default>; +&pwm0 { + pinctrl-0 = <&pwm0_default>; pinctrl-names = "default"; interrupts = <63 1>, <64 1>; interrupt-names = "gtioca", "overflow"; @@ -290,3 +291,39 @@ arduino_spi: &spi0 {}; &wdt { status = "okay"; }; + +ð { + local-mac-address = [74 90 50 B0 6D 5D]; + status = "okay"; + phy-handle = <&phy>; +}; + +&mdio { + pinctrl-0 = <ðer_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0>; + status = "okay"; + }; +}; + +&qspi0 { + pinctrl-0 = <&qspi_default>; + pinctrl-names = "default"; + status = "okay"; + + mx25l25645g: qspi-nor-flash@60000000 { + compatible = "renesas,ra-qspi-nor"; + reg = <0x60000000 DT_SIZE_M(32)>; + status = "okay"; + write-block-size = <1>; + erase-block-size = <4096>; + }; +}; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m5/Kconfig.defconfig b/boards/renesas/ek_ra6m5/Kconfig.defconfig new file mode 100644 index 0000000000000..f1d9177c32091 --- /dev/null +++ b/boards/renesas/ek_ra6m5/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EK_RA6M5 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config OUTPUT_RPD + default y + +endif # NETWORKING + +endif # BOARD_EK_RA6M5 diff --git a/boards/renesas/ek_ra6m5/board.cmake b/boards/renesas/ek_ra6m5/board.cmake index aecd6957c40a9..aab8f4e14acc0 100644 --- a/boards/renesas/ek_ra6m5/board.cmake +++ b/boards/renesas/ek_ra6m5/board.cmake @@ -3,6 +3,12 @@ board_runner_args(jlink "--device=R7FA6M5BH") board_runner_args(pyocd "--target=R7FA6M5BH") +if(CONFIG_OUTPUT_RPD) + board_runner_args(rfp "--device=RA" "--tool=jlink" "--interface=swd" "--erase" "--rpd-file=${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.rpd") +else() + board_runner_args(rfp "--device=RA" "--tool=jlink" "--interface=swd" "--erase") +endif() include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst index 4d3691ee6f968..996a1c0c10f08 100644 --- a/boards/renesas/ek_ra6m5/doc/index.rst +++ b/boards/renesas/ek_ra6m5/doc/index.rst @@ -87,6 +87,28 @@ built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. +.. note:: + + In applications using ethernet, ethernet buffers must be placed in non-secure RAM. + This requires configuration of the Implementation Defined Attribution Unit (IDAU), + which must be applied by partition memory using Renesas Flash Programmer. + +Partition Memory +================ + +Renesas Flash Programmer is available at (`Renesas Flash Programmer Download`_). +Once downloaded and installed, check rfp-cli is available or set rfp-cli path manually. + +Renesas partition data file will be available at build/zephyr/zephyr.rpd. +Connect jumper J6 then run Renesas Flash Programmer. + +To partition memory manually, execute: + + .. code-block:: console + + # From the root of the zephyr repository + rfp-cli -device ra -tool jlink -fo boundary-file build/zephyr/zephyr.rpd -p + Flashing ======== @@ -99,12 +121,18 @@ To flash the program to board 2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_ -3. Execute west command +3. Execute west command to flash using jlink runner .. code-block:: console west flash -r jlink +4. Or flash using rfp runner, this will partition memory then flash zephyr image. + + .. code-block:: console + + west flash -r rfp + Debugging ========= @@ -126,6 +154,7 @@ References ********** - `EK-RA6M5 Website`_ - `RA6M5 MCU group Website`_ +- `RA6 Ethernet Controller configuration`_ .. _EK-RA6M5 Website: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group @@ -141,3 +170,9 @@ References .. _Segger Ozone Download: https://www.segger.com/downloads/jlink#Ozone + +.. _Renesas Flash Programmer Download: + https://www.renesas.com/en/software-tool/renesas-flash-programmer-programming-gui + +.. _RA6 Ethernet Controller configuration: + https://www.renesas.com/en/blogs/configuration-issues-ra6-ethernet-controller#document diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi index 203730f335e21..d0dd01230888b 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi @@ -62,11 +62,11 @@ }; }; - pwm1_default: pwm1_default { + pwm0_default: pwm0_default { group1 { - /* GTIOC1A GTIOC1B */ - psels = , - ; + /* GTIOC0A GTIOC0B */ + psels = , + ; }; }; @@ -77,4 +77,32 @@ drive-strength = "high"; }; }; + + ether_default: ether_default { + group1 { + psels = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* RMII0_TXD_EN_B */ + , /* RMII0_TXD1_BR */ + , /* RMII0_TXD0_B */ + , /* REF50CK0_B */ + , /* RMII0_RXD0_B */ + , /* RMII0_RXD1_B */ + , /* RMII0_RX_ER_B */ + ; /* RMII0_CRS_DV_B */ + drive-strength = "high"; + }; + }; + + qspi_default: qspi_default { + group1 { + /* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */ + psels = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index ef397309a0cc7..913f3deba3b01 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -24,6 +24,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -249,8 +250,8 @@ status = "okay"; }; -&pwm1 { - pinctrl-0 = <&pwm1_default>; +&pwm0 { + pinctrl-0 = <&pwm0_default>; pinctrl-names = "default"; interrupts = <63 1>, <64 1>; interrupt-names = "gtioca", "overflow"; @@ -291,3 +292,39 @@ arduino_spi: &spi0 {}; &wdt { status = "okay"; }; + +ð { + local-mac-address = [74 90 50 B0 6D 5C]; + status = "okay"; + phy-handle = <&phy>; +}; + +&mdio { + pinctrl-0 = <ðer_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0>; + status = "okay"; + }; +}; + +&qspi0 { + pinctrl-0 = <&qspi_default>; + pinctrl-names = "default"; + status = "okay"; + + mx25l25645g: qspi-nor-flash@60000000 { + compatible = "renesas,ra-qspi-nor"; + reg = <0x60000000 DT_SIZE_M(32)>; + status = "okay"; + write-block-size = <1>; + erase-block-size = <4096>; + }; +}; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml index 8db264944a319..57cbbf46a3685 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml @@ -10,6 +10,7 @@ toolchain: supported: - gpio - usbd + - crc - watchdog - counter vendor: renesas diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst index b92b707f8107c..5f65464634d33 100644 --- a/boards/renesas/ek_ra8d1/doc/index.rst +++ b/boards/renesas/ek_ra8d1/doc/index.rst @@ -13,7 +13,7 @@ The key features of the EK-RA8D1 board are categorized in three groups as follow **MCU Native Pin Access** - 480MHz Arm Cortex-M85 based RA8D1 MCU in 224 pins, BGA package -- Native pin acces througgh 2 x 50-pin, and 2 x 40-pin male headers +- Native pin access through 2 x 50-pin, and 2 x 40-pin male headers - MCU current measurement points for precision current consumption measurement - Multiple clock sources - RA8D1 MCU oscillator and sub-clock oscillator crystals, providing precision 20.000MHz and 32,768 Hz refeence clocks. diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi index a1bef58722eaf..1458dd2ba8542 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi +++ b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi @@ -125,95 +125,51 @@ sdram_default: sdram_default{ group1 { - /* SDRAM_DQM1 */ - psels = , - /* SDRAM_CKE */ - , - /* SDRAM_WE */ - , - /* SDRAM_CS */ - , - /* SDRAM_A0 */ - , - /* SDRAM_A1 */ - , - /* SDRAM_A2 */ - , - /* SDRAM_A3 */ - , - /* SDRAM_A4 */ - , - /* SDRAM_A5 */ - , - /* SDRAM_A6 */ - , - /* SDRAM_A7 */ - , - /* SDRAM_A8 */ - , - /* SDRAM_A9 */ - , - /* SDRAM_A10 */ - , - /* SDRAM_A11 */ - , - /* SDRAM_A12 */ - , - /* SDRAM_D0 */ - , - /* SDRAM_D1 */ - , - /* SDRAM_D2 */ - , - /* SDRAM_D3 */ - , - /* SDRAM_D4 */ - , - /* SDRAM_D5 */ - , - /* SDRAM_D6 */ - , - /* SDRAM_D8 */ - , - /* SDRAM_D9 */ - , - /* SDRAM_D10 */ - , - /* SDRAM_D11 */ - , - /* SDRAM_D12 */ - , - /* SDRAM_D13 */ - , - /* SDRAM_D14 */ - , - /* SDRAM_BA0 */ - , - /* SDRAM_BA1 */ - , - /* SDRAM_RAS */ - , - /* SDRAM_CAS */ - , - /* SDRAM_SDCLK */ - ; + psels = , /* SDRAM_A1 */ + , /* SDRAM_A2 */ + , /* SDRAM_A3 */ + , /* SDRAM_A4 */ + , /* SDRAM_A5 */ + , /* SDRAM_A6 */ + , /* SDRAM_A7 */ + , /* SDRAM_A8 */ + , /* SDRAM_A9 */ + , /* SDRAM_A10 */ + , /* SDRAM_A11 */ + , /* SDRAM_A12 */ + , /* SDRAM_A13 */ + , /* SDRAM_A14 */ + , /* SDRAM_A15 */ + , /* SDRAM_CAS */ + , /* SDRAM_CKE */ + , /* SDRAM_DQ0 */ + , /* SDRAM_DQ1 */ + , /* SDRAM_DQ2 */ + , /* SDRAM_DQ3 */ + , /* SDRAM_DQ4 */ + , /* SDRAM_DQ5 */ + , /* SDRAM_DQ6 */ + , /* SDRAM_DQ7 */ + , /* SDRAM_DQ8 */ + , /* SDRAM_DQ9 */ + , /* SDRAM_DQ10 */ + , /* SDRAM_DQ11 */ + , /* SDRAM_DQ12 */ + , /* SDRAM_DQ13 */ + , /* SDRAM_DQ14 */ + , /* SDRAM_DQ15 */ + , /* SDRAM_DQM0 */ + , /* SDRAM_DQM1 */ + , /* SDRAM_RAS */ + , /* SDRAM_SDCS */ + ; /* SDRAM_WE */ drive-strength = "high"; }; group2 { - /* SDRAM_SDCLK */ - psels = ; + psels = ; /* SDRAM_SDCLK */ drive-strength = "highspeed-high"; }; - - group3 { - /* SDRAM_D7 */ - psels = , - /* SDRAM_D15 */ - , - /* SDRAM_DQM0 */ - ; - }; }; /* NOTE: pins conflict with ether_default */ diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index fe0c703a1e814..57e0571b2df2c 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -26,6 +26,7 @@ zephyr,entropy = &trng; zephyr,flash-controller = &flash1; zephyr,canbus = &canfd0; + zephyr,crc = &crc; }; leds { @@ -487,5 +488,9 @@ pmod_sd_shield: &sdhc1 {}; }; }; +&crc { + status = "okay"; +}; + mikrobus_serial: &uart3 {}; mikrobus_spi: &spi1 {}; diff --git a/boards/renesas/ek_ra8m1/doc/index.rst b/boards/renesas/ek_ra8m1/doc/index.rst index 4c1ca73df4967..ff6a19322be12 100644 --- a/boards/renesas/ek_ra8m1/doc/index.rst +++ b/boards/renesas/ek_ra8m1/doc/index.rst @@ -13,7 +13,7 @@ The key features of the EK-RA8M1 board are categorized in three groups as follow **MCU Native Pin Access** - 480MHz Arm Cortex-M85 based RA8M1 MCU in 224 pins, BGA package -- Native pin acces througgh 2 x 50-pin, and 2 x 40-pin male headers +- Native pin access through 2 x 50-pin, and 2 x 40-pin male headers - MCU current measurement points for precision current consumption measurement - Multiple clock sources - RA8M1 MCU oscillator and sub-clock oscillator crystals, providing precision 20.000MHz and 32,768 Hz refeence clocks. diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index da52851eff2a8..523a076a5128f 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -24,6 +24,7 @@ zephyr,shell-uart = &uart9; zephyr,entropy = &trng; zephyr,canbus = &canfd0; + zephyr,crc = &crc; }; leds { @@ -495,3 +496,7 @@ pmod_sd_shield: &sdhc0 {}; }; }; }; + +&crc{ + status = "okay"; +}; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml index 1dffeb2effb71..f9a5074829427 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml @@ -15,4 +15,5 @@ supported: - counter - i2s - i3c + - crc vendor: renesas diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi b/boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi index a19b0152fba16..1e74e60ee6208 100644 --- a/boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi +++ b/boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi @@ -69,91 +69,68 @@ sdram_default: sdram_default { group1 { - /* SDRAM_DQM1 */ - psels = , - /* SDRAM_CKE */ - , - /* SDRAM_WE */ - , - /* SDRAM_CS */ - , - /* SDRAM_A0 */ - , - /* SDRAM_A1 */ - , - /* SDRAM_A2 */ - , - /* SDRAM_A3 */ - , - /* SDRAM_A4 */ - , - /* SDRAM_A5 */ - , - /* SDRAM_A6 */ - , - /* SDRAM_A7 */ - , - /* SDRAM_A8 */ - , - /* SDRAM_A9 */ - , - /* SDRAM_A10 */ - , - /* SDRAM_A11 */ - , - /* SDRAM_A12 */ - , - /* SDRAM_D0 */ - , - /* SDRAM_D1 */ - , - /* SDRAM_D2 */ - , - /* SDRAM_D3 */ - , - /* SDRAM_D4 */ - , - /* SDRAM_D5 */ - , - /* SDRAM_D6 */ - , - /* SDRAM_D8 */ - , - /* SDRAM_D9 */ - , - /* SDRAM_D10 */ - , - /* SDRAM_D11 */ - , - /* SDRAM_D12 */ - , - /* SDRAM_D13 */ - , - /* SDRAM_D14 */ - , - /* SDRAM_BA0 */ - , - /* SDRAM_BA1 */ - , - /* SDRAM_RAS */ - , - /* SDRAM_CAS */ - ; + psels = , /* SDRAM_A2 */ + , /* SDRAM_A3 */ + , /* SDRAM_A4 */ + , /* SDRAM_A5 */ + , /* SDRAM_A6 */ + , /* SDRAM_A7 */ + , /* SDRAM_A8 */ + , /* SDRAM_A9 */ + , /* SDRAM_A10 */ + , /* SDRAM_A11 */ + , /* SDRAM_A12 */ + , /* SDRAM_A13 */ + , /* SDRAM_A14 */ + , /* SDRAM_A15 */ + , /* SDRAM_A16 */ + , /* SDRAM_DQ0 */ + , /* SDRAM_DQ1 */ + , /* SDRAM_DQ2 */ + , /* SDRAM_DQ3 */ + , /* SDRAM_DQ4 */ + , /* SDRAM_DQ5 */ + , /* SDRAM_DQ6 */ + , /* SDRAM_DQ7 */ + , /* SDRAM_DQ8 */ + , /* SDRAM_DQ9 */ + , /* SDRAM_DQ10 */ + , /* SDRAM_DQ11 */ + , /* SDRAM_DQ12 */ + , /* SDRAM_DQ13 */ + , /* SDRAM_DQ14 */ + , /* SDRAM_DQ15 */ + , /* SDRAM_DQ16 */ + , /* SDRAM_DQ17 */ + , /* SDRAM_DQ18 */ + , /* SDRAM_DQ19 */ + , /* SDRAM_DQ20 */ + , /* SDRAM_DQ21 */ + , /* SDRAM_DQ22 */ + , /* SDRAM_DQ23 */ + , /* SDRAM_DQ24 */ + , /* SDRAM_DQ25 */ + , /* SDRAM_DQ26 */ + , /* SDRAM_DQ27 */ + , /* SDRAM_DQ28 */ + , /* SDRAM_DQ29 */ + , /* SDRAM_DQ30 */ + , /* SDRAM_DQ31 */ + , /* SDRAM_DQM0 */ + , /* SDRAM_DQM1 */ + , /* SDRAM_DQM2 */ + , /* SDRAM_DQM3 */ + , /* SDRAM_WE */ + , /* SDRAM_CAS */ + , /* SDRAM_RAS */ + , /* SDRAM_CS */ + ; /* SDRAM_CKE */ + drive-strength = "high"; }; group2 { - /* SDRAM_SDCLK */ - psels = ; - drive-strength = "highspeed-high"; - }; - - group3 { - /* SDRAM_D7 */ - psels = , - /* SDRAM_D15 */ - , - /* SDRAM_DQM0 */ - ; + psels = ; /* SDRAM_SDCLK */ + drive-strength = "highspeed-high"; }; }; }; diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts index d25cf464f6914..666f01ddb9672 100644 --- a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts @@ -273,7 +273,7 @@ zephyr_lcdif: &lcdif {}; auto-refresh-interval = ; auto-refresh-count = ; precharge-cycle-count = ; - multiplex-addr-shift = "10-bit"; + multiplex-addr-shift = "9-bit"; edian-mode = "little-endian"; continuous-access; bus-width = "32-bit"; diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts index 7a8396753b8aa..c85c1829741f0 100644 --- a/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts +++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -159,3 +160,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index 7b64e4422785e..95c2d32d2bbfa 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -23,6 +23,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -144,3 +145,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index 60323b043e6aa..bf5c5ed93fbfe 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -134,3 +135,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index dd56259d90985..b1e34d6e31738 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -22,6 +22,7 @@ zephyr,entropy = &trng; zephyr,flash-controller = &flash1; zephyr,canbus = &canfd1; + zephyr,crc = &crc; }; leds { @@ -268,3 +269,7 @@ status = "okay"; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/rcar_h3ulcb/doc/index.rst b/boards/renesas/rcar_h3ulcb/doc/index.rst index 44a126bd28ee1..4203262958b8a 100644 --- a/boards/renesas/rcar_h3ulcb/doc/index.rst +++ b/boards/renesas/rcar_h3ulcb/doc/index.rst @@ -9,7 +9,7 @@ dual lockstep Cortex |reg|-R7. Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R7 core. -More information about the H3 SoC can be fount at `Renesas R-Car H3 chip`_. +More information about the H3 SoC can be found at `Renesas R-Car H3 chip`_. Hardware ******** diff --git a/boards/renesas/rcar_spider_s4/doc/index.rst b/boards/renesas/rcar_spider_s4/doc/index.rst index 7edf20bca23dc..703feb03bde2a 100644 --- a/boards/renesas/rcar_spider_s4/doc/index.rst +++ b/boards/renesas/rcar_spider_s4/doc/index.rst @@ -21,7 +21,7 @@ evaluating features and performance of this SoC. Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R52 core. -More information about the S4 SoC can be fount at `Renesas R-Car S4 chip`_. +More information about the S4 SoC can be found at `Renesas R-Car S4 chip`_. Hardware ******** diff --git a/boards/renesas/rsk_rx130/rsk_rx130.dts b/boards/renesas/rsk_rx130/rsk_rx130.dts index 90be043f2c2c9..0c30d47cd257c 100644 --- a/boards/renesas/rsk_rx130/rsk_rx130.dts +++ b/boards/renesas/rsk_rx130/rsk_rx130.dts @@ -14,7 +14,7 @@ / { model = "Renesas RSK+RX130-512KB KIT"; - compatible = "renesas,rsk_rx130_512kb","renesas,rxv1"; + compatible = "renesas,rsk_rx130_512kb"; chosen { zephyr,sram = &sram0; diff --git a/boards/renesas/rssk_ra2l1/rssk_ra2l1-pinctrl.dtsi b/boards/renesas/rssk_ra2l1/rssk_ra2l1-pinctrl.dtsi index 8002bddb3475a..2602d22f2f70b 100644 --- a/boards/renesas/rssk_ra2l1/rssk_ra2l1-pinctrl.dtsi +++ b/boards/renesas/rssk_ra2l1/rssk_ra2l1-pinctrl.dtsi @@ -12,4 +12,25 @@ ; }; }; + + ctsu_default: ctsu_default { + group1 { + psels = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; }; diff --git a/boards/renesas/rssk_ra2l1/rssk_ra2l1.dts b/boards/renesas/rssk_ra2l1/rssk_ra2l1.dts index 101dd455936bf..4998b0948b6fb 100644 --- a/boards/renesas/rssk_ra2l1/rssk_ra2l1.dts +++ b/boards/renesas/rssk_ra2l1/rssk_ra2l1.dts @@ -12,6 +12,7 @@ #include #include +#include #include "rssk_ra2l1-pinctrl.dtsi" / { @@ -62,6 +63,28 @@ sw1 = &button1; watchdog0 = &wdt; }; + + rtk0eg0019b01002bj_cn1: rtk0eg0019b01002bj-cn1 { + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + ; + }; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; }; &ioport2 { @@ -72,6 +95,18 @@ status = "okay"; }; +&ioport4 { + status = "okay"; +}; + +&ioport5 { + status = "okay"; +}; + +&ioport7 { + status = "okay"; +}; + &port_irq0 { interrupts = <8 3>; status = "okay"; @@ -98,3 +133,13 @@ &wdt { status = "okay"; }; + +&ctsu { + pinctrl-0 = <&ctsu_default>; + pinctrl-names = "default"; + interrupts = <5 3>, <6 3>, <7 3>; + interrupt-names = "ctsuwr", "ctsurd", "ctsufn"; + tscap-gpios = <&ioport1 12 0>; +}; + +rtk0eg0019b01002bj_ctsu: &ctsu {}; diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi index b4d00a2df2048..073e7ebb17181 100644 --- a/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi @@ -27,4 +27,11 @@ pinmux = ; /* MTIOCA */ }; }; + + /omit-if-no-ref/ i2c1_pins: i2c1 { + i2c1-spins { + pins = , ; + input-enable; + }; + }; }; diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts index 482388639d142..9e8a3f7158241 100644 --- a/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts @@ -71,3 +71,9 @@ &adc { status = "okay"; }; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml index 37e6392bab8e2..83bb7cbd3cb35 100644 --- a/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml @@ -10,6 +10,7 @@ supported: - gpio - pwm - adc + - i2c testing: ignore_tags: - bluetooth diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi index c5a1476d9a953..2b338491a4bb3 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi @@ -41,4 +41,11 @@ ; /* GTIOCB */ }; }; + + /omit-if-no-ref/ i2c1_default: i2c1_default { + i2c1-pinmux { + pinmux = , /* SCL */ + ; /* SDA */ + }; + }; }; diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts index 3ee0fcb284eb5..bc733ef5c4558 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts @@ -117,3 +117,9 @@ &adc1 { status = "okay"; }; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml index 3f24eb21145f0..429be2913b37c 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml @@ -9,4 +9,5 @@ supported: - gpio - pwm - adc + - i2c vendor: renesas diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi index 66deaced4294e..6575ee089d6de 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi @@ -33,4 +33,11 @@ ; /* GTIOCB */ }; }; + + /omit-if-no-ref/ i2c1_default: i2c1_default { + i2c1-pinmux { + pinmux = , /* SCL */ + ; /* SDA */ + }; + }; }; diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts index e8713e5c9f161..97ef74bbbe670 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts @@ -86,6 +86,12 @@ status = "okay"; }; +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &gpio10 { irqs = <5 2>; status = "okay"; diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml index 7dc6d48b8803f..2fa52d900dbf7 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml @@ -14,4 +14,5 @@ supported: - gpio - pwm - adc + - i2c vendor: renesas diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi index 35f17d017fa07..0e0b91c4738f1 100644 --- a/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi +++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi @@ -25,4 +25,11 @@ pinmux = ; /* GTIOCA */ }; }; + + /omit-if-no-ref/ i2c3_pins: i2c3 { + i2c3-pinmux { + pinmux = , /* SDA */ + ; /* SCL */ + }; + }; }; diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts index 51e4a2cb74bcd..06534843bab28 100644 --- a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts +++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts @@ -37,3 +37,9 @@ &adc { status = "okay"; }; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml index ae17b32fb8268..146eb34e36ce7 100644 --- a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml +++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml @@ -10,4 +10,5 @@ supported: - gpio - pwm - adc + - i2c vendor: renesas diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1.dts b/boards/renesas/voice_ra4e1/voice_ra4e1.dts index 7cf9ec82e0142..88becd3565ba2 100644 --- a/boards/renesas/voice_ra4e1/voice_ra4e1.dts +++ b/boards/renesas/voice_ra4e1/voice_ra4e1.dts @@ -22,6 +22,7 @@ zephyr,console = &uart3; zephyr,shell-uart = &uart3; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -144,3 +145,7 @@ pinctrl-names = "default"; status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst index 2f2d40bd250ee..64289cebf1d65 100644 --- a/boards/seeed/seeeduino_xiao/doc/index.rst +++ b/boards/seeed/seeeduino_xiao/doc/index.rst @@ -134,4 +134,4 @@ References https://wiki.seeedstudio.com/Seeeduino-XIAO/#hardware-overview .. _schematic: - https://wiki.seeedstudio.com/Seeeduino-XIAO/#resourses + https://wiki.seeedstudio.com/Seeeduino-XIAO/#resources diff --git a/boards/seeed/wio_terminal/wio_terminal.yaml b/boards/seeed/wio_terminal/wio_terminal.yaml index a5445ae3cd036..aa8118b0e6446 100644 --- a/boards/seeed/wio_terminal/wio_terminal.yaml +++ b/boards/seeed/wio_terminal/wio_terminal.yaml @@ -15,6 +15,6 @@ supported: - i2c - pwm - spi - - usb_device + - usbd - watchdog vendor: seeed diff --git a/boards/seeed/xiao_ble/xiao_ble.yaml b/boards/seeed/xiao_ble/xiao_ble.yaml index a6482108e38d7..fea7a4fa769f9 100644 --- a/boards/seeed/xiao_ble/xiao_ble.yaml +++ b/boards/seeed/xiao_ble/xiao_ble.yaml @@ -16,7 +16,7 @@ supported: - i2s - pwm - spi - - usb_device + - usbd - watchdog - netif:openthread - xiao_adc diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml index 9275e38f7f69f..7edb8000612df 100644 --- a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml @@ -16,7 +16,7 @@ supported: - i2s - pwm - spi - - usb_device + - usbd - watchdog - netif:openthread - xiao_adc diff --git a/boards/seeed/xiao_nrf54l15/doc/index.rst b/boards/seeed/xiao_nrf54l15/doc/index.rst index 911574fff9cb3..960b210d772a1 100644 --- a/boards/seeed/xiao_nrf54l15/doc/index.rst +++ b/boards/seeed/xiao_nrf54l15/doc/index.rst @@ -78,7 +78,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: xiao_nrf54l15 + :board: xiao_nrf54l15/nrf54l15/cpuapp :goals: flash Open a serial terminal (minicom, putty, etc.) connecting to the UCB CDC ACM serial port. @@ -87,7 +87,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! xiao_nrf54l15 + Hello World! xiao_nrf54l15/nrf54l15/cpuapp .. _Seeed Studio XIAO nRF54L15: diff --git a/boards/sensry/ganymed_bob/Kconfig.defconfig b/boards/sensry/ganymed_bob/Kconfig.defconfig new file mode 100644 index 0000000000000..f0a5ec770cf7d --- /dev/null +++ b/boards/sensry/ganymed_bob/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +configdefault NET_L2_ETHERNET + default y diff --git a/boards/sensry/ganymed_sk/Kconfig.defconfig b/boards/sensry/ganymed_sk/Kconfig.defconfig new file mode 100644 index 0000000000000..f0a5ec770cf7d --- /dev/null +++ b/boards/sensry/ganymed_sk/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +configdefault NET_L2_ETHERNET + default y diff --git a/boards/shields/adafruit_24lc32/Kconfig.shield b/boards/shields/adafruit_24lc32/Kconfig.shield new file mode 100644 index 0000000000000..5475409ff7b82 --- /dev/null +++ b/boards/shields/adafruit_24lc32/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_24LC32 + def_bool $(shields_list_contains,adafruit_24lc32) diff --git a/boards/shields/adafruit_24lc32/adafruit_24lc32.overlay b/boards/shields/adafruit_24lc32/adafruit_24lc32.overlay new file mode 100644 index 0000000000000..8fcb9917a0bd0 --- /dev/null +++ b/boards/shields/adafruit_24lc32/adafruit_24lc32.overlay @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + eeprom-0 = &eeprom_adafruit_24lc32; + }; +}; + +&zephyr_i2c { + status = "okay"; + + eeprom_adafruit_24lc32: eeprom@50 { + status = "okay"; + compatible = "atmel,at24lc32", "atmel,at24"; + reg = <0x50>; + size = ; + pagesize = <8>; + address-width = <16>; + timeout = <5>; + }; +}; diff --git a/boards/shields/adafruit_24lc32/doc/adafruit_24lc32.webp b/boards/shields/adafruit_24lc32/doc/adafruit_24lc32.webp new file mode 100644 index 0000000000000..a1cbeaac2fde4 Binary files /dev/null and b/boards/shields/adafruit_24lc32/doc/adafruit_24lc32.webp differ diff --git a/boards/shields/adafruit_24lc32/doc/index.rst b/boards/shields/adafruit_24lc32/doc/index.rst new file mode 100644 index 0000000000000..968b9aeff169a --- /dev/null +++ b/boards/shields/adafruit_24lc32/doc/index.rst @@ -0,0 +1,64 @@ +.. _adafruit_24lc32: + +Adafruit 24LC32 EEPROM Shield +############################# + +Overview +******** + +The `Adafruit 24LC32 EEPROM Shield`_ features a `Microchip 24LC32 EEPROM`_ (or +equivalent) and two STEMMA QT connectors. +It has a size of 32 kbit (4 kByte). + +.. figure:: adafruit_24lc32.webp + :align: center + :alt: Adafruit 24LC32 EEPROM Shield + + Adafruit 24LC32 EEPROM Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+------------------------------+ +| Shield Pin | Function | ++==============+==============================+ +| SDA | 24LC32 I2C SDA | ++--------------+------------------------------+ +| SCL | 24LC32 I2C SCL | ++--------------+------------------------------+ +| WP | 24LC32 write protection | ++--------------+------------------------------+ +| A0 - A2 | 24LC32 I2C address selection | ++--------------+------------------------------+ + +See :dtcompatible:`atmel,at24` for documentation on how to adjust the +devicetree file, for example to make the EEPROM read-only. + + +Programming +*********** + +Set ``--shield adafruit_24lc32`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`eeprom` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/eeprom + :board: adafruit_qt_py_rp2040 + :shield: adafruit_24lc32 + :goals: build + +.. _Adafruit 24LC32 EEPROM Shield: + https://learn.adafruit.com/adafruit-24lc32-i2c-eeprom-breakout-32kbit-4-kb + +.. _Microchip 24LC32 EEPROM: + https://www.microchip.com/en-us/product/24lc32 diff --git a/boards/shields/adafruit_24lc32/shield.yml b/boards/shields/adafruit_24lc32/shield.yml new file mode 100644 index 0000000000000..420b3219901c7 --- /dev/null +++ b/boards/shields/adafruit_24lc32/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_24lc32 + full_name: Adafruit 24LC32 EEPROM Shield + vendor: adafruit + supported_features: + - mtd diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/adafruit_2_8_tft_touch_v2_nano.overlay b/boards/shields/adafruit_2_8_tft_touch_v2/adafruit_2_8_tft_touch_v2_nano.overlay index 067c51c0f16ab..6852a7e571ef8 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/adafruit_2_8_tft_touch_v2_nano.overlay +++ b/boards/shields/adafruit_2_8_tft_touch_v2/adafruit_2_8_tft_touch_v2_nano.overlay @@ -5,6 +5,7 @@ */ #include "adafruit_2_8_tft_touch_v2.dtsi" +#include / { /* @@ -16,9 +17,9 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <10 0 &arduino_nano_header 4 0>, /* D4 */ - <15 0 &arduino_nano_header 10 0>, /* D10 */ - <16 0 &arduino_nano_header 9 0>; /* D9 */ + gpio-map = , + , + ; }; }; diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/doc/adafruit_2_8_tft_touch_v2.webp b/boards/shields/adafruit_2_8_tft_touch_v2/doc/adafruit_2_8_tft_touch_v2.webp new file mode 100644 index 0000000000000..9f2cd4b1fbdb9 Binary files /dev/null and b/boards/shields/adafruit_2_8_tft_touch_v2/doc/adafruit_2_8_tft_touch_v2.webp differ diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst index 3d418ac6d905e..68422eae0f30f 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst +++ b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst @@ -15,6 +15,12 @@ touchscreen input is supported only on Capacitive Touch version. More information about the shield can be found at the `Adafruit 2.8" TFT Touch Shield v2 website`_. +.. figure:: adafruit_2_8_tft_touch_v2.webp + :align: center + :alt: Adafruit 2.8" TFT Touch Shield v2 + + Adafruit 2.8" TFT Touch Shield v2 (Credit: Adafruit) + Pins Assignment of the Adafruit 2.8" TFT Touch Shield v2 ======================================================== diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi index b2df10395b14c..eb17fbd561285 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi +++ b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { chosen { @@ -23,7 +24,7 @@ adafruit_2_8_tft_touch_v2_mipi_dbi: adafruit_2_8_tft_touch_v2_mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -48,8 +49,8 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>, /* D10 */ - <&arduino_header 10 GPIO_ACTIVE_LOW>; /* D04 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>, + <&arduino_header ARDUINO_HEADER_R3_D4 GPIO_ACTIVE_LOW>; adafruit_2_8_tft_touch_v2_sdhc: sdhc@1 { compatible = "zephyr,sdhc-spi-slot"; @@ -69,6 +70,6 @@ compatible = "focaltech,ft5336"; reg = <0x38>; /* Uncomment if IRQ line is available (requires to solder jumper) */ - /* int-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; */ /* D7 */ + /* int-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; */ }; }; diff --git a/boards/shields/adafruit_aht20/Kconfig.shield b/boards/shields/adafruit_aht20/Kconfig.shield new file mode 100644 index 0000000000000..acb1abc3ca8cc --- /dev/null +++ b/boards/shields/adafruit_aht20/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_AHT20 + def_bool $(shields_list_contains,adafruit_aht20) diff --git a/boards/shields/adafruit_aht20/adafruit_aht20.overlay b/boards/shields/adafruit_aht20/adafruit_aht20.overlay new file mode 100644 index 0000000000000..f585b24556ca0 --- /dev/null +++ b/boards/shields/adafruit_aht20/adafruit_aht20.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + dht0 = &adafruit_aht20; + }; +}; + +&zephyr_i2c { + status = "okay"; + + adafruit_aht20: aht20@38 { + status = "okay"; + compatible = "aosong,aht20"; + reg = <0x38>; + }; +}; diff --git a/boards/shields/adafruit_aht20/doc/adafruit_aht20.webp b/boards/shields/adafruit_aht20/doc/adafruit_aht20.webp new file mode 100644 index 0000000000000..a2d71165cd372 Binary files /dev/null and b/boards/shields/adafruit_aht20/doc/adafruit_aht20.webp differ diff --git a/boards/shields/adafruit_aht20/doc/index.rst b/boards/shields/adafruit_aht20/doc/index.rst new file mode 100644 index 0000000000000..e025d9461b860 --- /dev/null +++ b/boards/shields/adafruit_aht20/doc/index.rst @@ -0,0 +1,59 @@ +.. _adafruit_aht20: + +Adafruit AHT20 Shield +##################### + +Overview +******** + +The `Adafruit AHT20 Temperature and Humidity Sensor Shield`_ features +an `Aosong AHT20 Humidity and Temperature Sensor`_ and two STEMMA QT connectors. +It measures temperature and humidity. + +.. figure:: adafruit_aht20.webp + :align: center + :alt: Adafruit AHT20 Shield + + Adafruit AHT20 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------+ +| Shield Pin | Function | ++==============+===================+ +| SDA | AHT20 I2C SDA | ++--------------+-------------------+ +| SCL | AHT20 I2C SCL | ++--------------+-------------------+ + +See :dtcompatible:`aosong,aht20` for details on possible devicetree settings. + + +Programming +*********** + +Set ``--shield adafruit_aht20`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`dht_polling` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/dht_polling + :board: adafruit_qt_py_rp2040 + :shield: adafruit_aht20 + :goals: build + +.. _Adafruit AHT20 Temperature and Humidity Sensor Shield: + https://learn.adafruit.com/adafruit-aht20 + +.. _Aosong AHT20 Humidity and Temperature Sensor: + https://www.aosong.com/userfiles/files/media/Data%20Sheet%20AHT20.pdf diff --git a/boards/shields/adafruit_aht20/shield.yml b/boards/shields/adafruit_aht20/shield.yml new file mode 100644 index 0000000000000..e24c214d7508d --- /dev/null +++ b/boards/shields/adafruit_aht20/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_aht20 + full_name: Adafruit AHT20 Temperature and Humidity Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_apds9960/Kconfig.shield b/boards/shields/adafruit_apds9960/Kconfig.shield new file mode 100644 index 0000000000000..51488149eb2c4 --- /dev/null +++ b/boards/shields/adafruit_apds9960/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_APDS9960 + def_bool $(shields_list_contains,adafruit_apds9960) diff --git a/boards/shields/adafruit_apds9960/adafruit_apds9960.overlay b/boards/shields/adafruit_apds9960/adafruit_apds9960.overlay new file mode 100644 index 0000000000000..66925f897f6f5 --- /dev/null +++ b/boards/shields/adafruit_apds9960/adafruit_apds9960.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + adafruit_apds9960: apds9960@39 { + compatible = "avago,apds9960"; + status = "okay"; + reg = <0x39>; + }; +}; diff --git a/boards/shields/adafruit_apds9960/doc/adafruit_apds9960.webp b/boards/shields/adafruit_apds9960/doc/adafruit_apds9960.webp new file mode 100644 index 0000000000000..4c6c5d88ff1c1 Binary files /dev/null and b/boards/shields/adafruit_apds9960/doc/adafruit_apds9960.webp differ diff --git a/boards/shields/adafruit_apds9960/doc/index.rst b/boards/shields/adafruit_apds9960/doc/index.rst new file mode 100644 index 0000000000000..894d894d92155 --- /dev/null +++ b/boards/shields/adafruit_apds9960/doc/index.rst @@ -0,0 +1,62 @@ +.. _adafruit_apds9960: + +Adafruit APDS9960 Shield +######################## + +Overview +******** + +The `Adafruit APDS9960 Proximity, Light, RGB, and Gesture Sensor Shield`_ features +a `Broadcom APDS9960 sensor`_ and two STEMMA QT connectors. + +.. figure:: adafruit_apds9960.webp + :align: center + :alt: Adafruit APDS9960 Shield + + Adafruit APDS9960 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+------------------------+ +| Shield Pin | Function | ++==============+========================+ +| SDA | APDS9960 I2C SDA | ++--------------+------------------------+ +| SCL | APDS9960 I2C SCL | ++--------------+------------------------+ +| INT | APDS9960 interrupt out | ++--------------+------------------------+ + +In order to use interrupts you need to connect a separate wire from the +shield to a GPIO pin on your microcontroller board. See +:dtcompatible:`avago,apds9960` for documentation on how to adjust the +devicetree file. + +Programming +*********** + +Set ``--shield adafruit_apds9960`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`apds9960` proximity and light sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/apds9960 + :board: adafruit_qt_py_rp2040 + :shield: adafruit_apds9960 + :goals: build + +.. _Adafruit APDS9960 Proximity, Light, RGB, and Gesture Sensor Shield: + https://learn.adafruit.com/adafruit-apds9960-breakout + +.. _Broadcom APDS9960 sensor: + https://www.broadcom.com/products/optical-sensors/integrated-ambient-light-and-proximity-sensors/apds-9960 diff --git a/boards/shields/adafruit_apds9960/shield.yml b/boards/shields/adafruit_apds9960/shield.yml new file mode 100644 index 0000000000000..01862e2820885 --- /dev/null +++ b/boards/shields/adafruit_apds9960/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_apds9960 + full_name: Adafruit APDS9960 Proximity, Light, RGB and Gesture Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay b/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay index 1d3ffb8fc7573..9ade204ea115a 100644 --- a/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay +++ b/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ + #include + / { aliases { rtc = &rtc0_adafruit_data_logger; @@ -16,7 +18,7 @@ * pins "L1" and "Digital I/O 3". */ green_led_adafruit_data_logger: led_1__adafruit_data_logger { - gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; /* D3 */ + gpios = <&arduino_header ARDUINO_HEADER_R3_D3 GPIO_ACTIVE_HIGH>; label = "User LED1"; }; /* @@ -24,7 +26,7 @@ * pins "L2" and "Digital I/O 4". */ red_led_adafruit_data_logger: led_2_adafruit_data_logger { - gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 */ + gpios = <&arduino_header ARDUINO_HEADER_R3_D4 GPIO_ACTIVE_HIGH>; label = "User LED2"; }; }; @@ -33,7 +35,7 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; sdhc0_adafruit_data_logger: sdhc@0 { compatible = "zephyr,sdhc-spi-slot"; @@ -61,7 +63,8 @@ * Interrupt connection must be manually established using a jumper wire between * pins "SQ" and "Digital I/O 7". */ - int1-gpios = <&arduino_header 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* D7 */ + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 + (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; status = "okay"; }; }; diff --git a/boards/shields/adafruit_dps310/Kconfig.shield b/boards/shields/adafruit_dps310/Kconfig.shield new file mode 100644 index 0000000000000..3d57425205197 --- /dev/null +++ b/boards/shields/adafruit_dps310/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_DPS310 + def_bool $(shields_list_contains,adafruit_dps310) diff --git a/boards/shields/adafruit_dps310/adafruit_dps310.overlay b/boards/shields/adafruit_dps310/adafruit_dps310.overlay new file mode 100644 index 0000000000000..9befb160a392b --- /dev/null +++ b/boards/shields/adafruit_dps310/adafruit_dps310.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + pressure-sensor = &adafruit_dps310; + }; +}; + +&zephyr_i2c { + status = "okay"; + + adafruit_dps310: dps310@77 { + compatible = "infineon,dps310"; + status = "okay"; + reg = <0x77>; + }; +}; diff --git a/boards/shields/adafruit_dps310/doc/adafruit_dps310.webp b/boards/shields/adafruit_dps310/doc/adafruit_dps310.webp new file mode 100644 index 0000000000000..d3d222ac46456 Binary files /dev/null and b/boards/shields/adafruit_dps310/doc/adafruit_dps310.webp differ diff --git a/boards/shields/adafruit_dps310/doc/index.rst b/boards/shields/adafruit_dps310/doc/index.rst new file mode 100644 index 0000000000000..e824073f02324 --- /dev/null +++ b/boards/shields/adafruit_dps310/doc/index.rst @@ -0,0 +1,64 @@ +.. _adafruit_dps310: + +Adafruit DPS310 Shield +###################### + +Overview +******** + +The `Adafruit DPS310 Precision Barometric Pressure and Altitude Sensor Shield`_ features +a `Infineon DPS310 Pressure Sensor`_ and two STEMMA QT connectors. +It measures air pressure and temperature. + +.. figure:: adafruit_dps310.webp + :align: center + :alt: Adafruit DPS310 Shield + + Adafruit DPS310 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+---------------------------+ +| Shield Pin | Function | ++==============+===========================+ +| SDI | DPS310 I2C SDA | ++--------------+---------------------------+ +| SCK | DPS310 I2C SCL | ++--------------+---------------------------+ +| SDO | DPS310 I2C address adjust | ++--------------+---------------------------+ +| CS | Not used in I2C mode | ++--------------+---------------------------+ + +See :dtcompatible:`infineon,dps310` for documentation on how to adjust the +devicetree file. + + +Programming +*********** + +Set ``--shield adafruit_dps310`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`pressure_polling` pressure and temperature sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/pressure_polling + :board: adafruit_qt_py_rp2040 + :shield: adafruit_dps310 + :goals: build + +.. _Adafruit DPS310 Precision Barometric Pressure and Altitude Sensor Shield: + https://learn.adafruit.com/adafruit-dps310-precision-barometric-pressure-sensor + +.. _Infineon DPS310 Pressure Sensor: + https://www.infineon.com/part/DPS310 diff --git a/boards/shields/adafruit_dps310/shield.yml b/boards/shields/adafruit_dps310/shield.yml new file mode 100644 index 0000000000000..f52eb980c547f --- /dev/null +++ b/boards/shields/adafruit_dps310/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_dps310 + full_name: Adafruit DPS310 Precision Barometric Pressure and Altitude Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_drv2605l/Kconfig.shield b/boards/shields/adafruit_drv2605l/Kconfig.shield new file mode 100644 index 0000000000000..1afa90b3b90dd --- /dev/null +++ b/boards/shields/adafruit_drv2605l/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_DRV2605L + def_bool $(shields_list_contains,adafruit_drv2605l) diff --git a/boards/shields/adafruit_drv2605l/adafruit_drv2605l.overlay b/boards/shields/adafruit_drv2605l/adafruit_drv2605l.overlay new file mode 100644 index 0000000000000..f5d72df10b91a --- /dev/null +++ b/boards/shields/adafruit_drv2605l/adafruit_drv2605l.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + adafruit_drv2605: drv2605@5a { + compatible = "ti,drv2605"; + reg = <0x5a>; + status = "okay"; + actuator-mode = "ERM"; + }; +}; + +/* Alternate node label for samples/drivers/haptics/drv2605 */ +haptic: &adafruit_drv2605 {}; diff --git a/boards/shields/adafruit_drv2605l/doc/adafruit_drv2605l.webp b/boards/shields/adafruit_drv2605l/doc/adafruit_drv2605l.webp new file mode 100644 index 0000000000000..b7735701fd46b Binary files /dev/null and b/boards/shields/adafruit_drv2605l/doc/adafruit_drv2605l.webp differ diff --git a/boards/shields/adafruit_drv2605l/doc/index.rst b/boards/shields/adafruit_drv2605l/doc/index.rst new file mode 100644 index 0000000000000..5fe8d33890f0f --- /dev/null +++ b/boards/shields/adafruit_drv2605l/doc/index.rst @@ -0,0 +1,66 @@ +.. _adafruit_drv2605l: + +Adafruit DRV2605L Shield +######################## + +Overview +******** + +The `Adafruit DRV2605L Haptic Motor Controller Shield`_ features +a `TI DRV2605 Haptic Driver`_ and two STEMMA QT connectors. +Note that DRV2605L is a low-voltage version of DRV2605. + +.. figure:: adafruit_drv2605l.webp + :align: center + :alt: Adafruit DRV2605L Shield + + Adafruit DRV2605L Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+---------------------------------------------+ +| Shield Pin | Function | ++==============+=============================================+ +| SDA | DRV2605 I2C SDA | ++--------------+---------------------------------------------+ +| SCL | DRV2605 I2C SCL | ++--------------+---------------------------------------------+ +| IN/TRIG | Digital input for triggering haptic effects | ++--------------+---------------------------------------------+ + +The haptic motor could be of type eccentric rotating mass (ERM) +or linear resonant actuator (LRA). +By default an ERM motor is specified in the devicetree file for +this shield, as this is the type of motor that Adafruit sells with this shield. +Modify the devicetree file if you use an LRA motor; +see :dtcompatible:`ti,drv2605` for details. + + +Programming +*********** + +Set ``--shield adafruit_drv2605l`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`drv2605` haptics sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/haptics/drv2605 + :board: adafruit_qt_py_rp2040 + :shield: adafruit_drv2605l + :goals: build + +.. _Adafruit DRV2605L Haptic Motor Controller Shield: + https://learn.adafruit.com/adafruit-drv2605-haptic-controller-breakout + +.. _TI DRV2605 Haptic Driver: + https://www.ti.com/product/DRV2605 diff --git a/boards/shields/adafruit_drv2605l/shield.yml b/boards/shields/adafruit_drv2605l/shield.yml new file mode 100644 index 0000000000000..b899583f119de --- /dev/null +++ b/boards/shields/adafruit_drv2605l/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_drv2605l + full_name: Adafruit DRV2605L Haptic Motor Controller Shield + vendor: adafruit + supported_features: + - haptics diff --git a/boards/shields/adafruit_featherwing_128x32_oled/doc/adafruit_featherwing_128x32_oled.webp b/boards/shields/adafruit_featherwing_128x32_oled/doc/adafruit_featherwing_128x32_oled.webp new file mode 100644 index 0000000000000..be47ef85f6397 Binary files /dev/null and b/boards/shields/adafruit_featherwing_128x32_oled/doc/adafruit_featherwing_128x32_oled.webp differ diff --git a/boards/shields/adafruit_featherwing_128x32_oled/doc/index.rst b/boards/shields/adafruit_featherwing_128x32_oled/doc/index.rst index b8bb0367c76fb..d576cb8aba12a 100644 --- a/boards/shields/adafruit_featherwing_128x32_oled/doc/index.rst +++ b/boards/shields/adafruit_featherwing_128x32_oled/doc/index.rst @@ -9,6 +9,13 @@ Overview The `Adafruit OLED FeatherWing Shield`_ features a SSD1306 compatible OLED display with a resolution of 128x32 pixels and three user buttons. +.. figure:: adafruit_featherwing_128x32_oled.webp + :align: center + :alt: Adafruit FeatherWing 128x32 OLED Shield + + Adafruit FeatherWing 128x32 OLED Shield (Credit: Adafruit) + + Pins Assignment of the Adafruit FeatherWing 128x32 OLED shield ============================================================== diff --git a/boards/shields/adafruit_ht16k33/Kconfig.shield b/boards/shields/adafruit_ht16k33/Kconfig.shield new file mode 100644 index 0000000000000..ab91538fbe2d1 --- /dev/null +++ b/boards/shields/adafruit_ht16k33/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_HT16K33 + def_bool $(shields_list_contains,adafruit_ht16k33) diff --git a/boards/shields/adafruit_ht16k33/adafruit_ht16k33.overlay b/boards/shields/adafruit_ht16k33/adafruit_ht16k33.overlay new file mode 100644 index 0000000000000..2614b98f193c5 --- /dev/null +++ b/boards/shields/adafruit_ht16k33/adafruit_ht16k33.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + ht16k33_adafruit_ht16k33: ht16k33@70 { + compatible = "holtek,ht16k33"; + reg = <0x70>; + }; +}; diff --git a/boards/shields/adafruit_ht16k33/doc/adafruit_ht16k33.webp b/boards/shields/adafruit_ht16k33/doc/adafruit_ht16k33.webp new file mode 100644 index 0000000000000..50254f4910005 Binary files /dev/null and b/boards/shields/adafruit_ht16k33/doc/adafruit_ht16k33.webp differ diff --git a/boards/shields/adafruit_ht16k33/doc/index.rst b/boards/shields/adafruit_ht16k33/doc/index.rst new file mode 100644 index 0000000000000..8dea22891f2c1 --- /dev/null +++ b/boards/shields/adafruit_ht16k33/doc/index.rst @@ -0,0 +1,66 @@ +.. _adafruit_ht16k33: + +Adafruit HT16K33 LED Matrix Shield +################################## + +Overview +******** + +The `Adafruit Small 1.2 inch 8x8 LED Matrix with I2C Backpack`_ features +a `Holtek HT16K33 LED Controller Driver`_, an 8x8 LED matrix and two STEMMA QT connectors. + +This shield definition can also be used with other shields having a HT16K33 LED +controller. The controller exposes up to 128 LEDs, and the mapping between a LED number +and a physical LED might differ on different shields. +See `Discussion on other LED backpacks`_. + +.. figure:: adafruit_ht16k33.webp + :align: center + :alt: Adafruit 8x8 LED Matrix Shield + + Adafruit 8x8 LED Matrix Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------+ +| Shield Pin | Function | ++==============+===================+ +| SDA | HT16K33 I2C SDA | ++--------------+-------------------+ +| SCL | HT16K33 I2C SCL | ++--------------+-------------------+ + +See :dtcompatible:`holtek,ht16k33` for documentation on devicetree settings. + + +Programming +*********** + +Set ``--shield adafruit_ht16k33`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`ht16k33` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/ht16k33 + :board: adafruit_qt_py_rp2040 + :shield: adafruit_ht16k33 + :goals: build + +.. _Adafruit Small 1.2 inch 8x8 LED Matrix with I2C Backpack: + https://www.adafruit.com/product/1632 + +.. _Discussion on other LED backpacks: + https://learn.adafruit.com/adafruit-led-backpack + +.. _Holtek HT16K33 LED Controller Driver: + https://www.holtek.com/page/vg/HT16K33A diff --git a/boards/shields/adafruit_ht16k33/shield.yml b/boards/shields/adafruit_ht16k33/shield.yml new file mode 100644 index 0000000000000..242020445834e --- /dev/null +++ b/boards/shields/adafruit_ht16k33/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_ht16k33 + full_name: Adafruit HT16K33 LED Matrix Shield + vendor: adafruit + supported_features: + - led diff --git a/boards/shields/adafruit_ina219/Kconfig.shield b/boards/shields/adafruit_ina219/Kconfig.shield new file mode 100644 index 0000000000000..9ab12e69a55ce --- /dev/null +++ b/boards/shields/adafruit_ina219/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_INA219 + def_bool $(shields_list_contains,adafruit_ina219) diff --git a/boards/shields/adafruit_ina219/adafruit_ina219.overlay b/boards/shields/adafruit_ina219/adafruit_ina219.overlay new file mode 100644 index 0000000000000..33003b0d7c1ae --- /dev/null +++ b/boards/shields/adafruit_ina219/adafruit_ina219.overlay @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + /* The shunt resistor on the board is 0.1 Ohm. + * The default max shunt voltage is +/-320mV, + * resulting in a max current range of +/-3.2 Amps. + * Calculate the current LSB value as 3.2/2^15 A = 122 uA. + * Round the current LSB value upwards to 200 uA. + */ + adafruit_ina219: ina219@40 { + status = "okay"; + compatible = "ti,ina219"; + reg = <0x40>; + shunt-milliohm = <100>; + lsb-microamp = <200>; + }; +}; diff --git a/boards/shields/adafruit_ina219/doc/adafruit_ina219.webp b/boards/shields/adafruit_ina219/doc/adafruit_ina219.webp new file mode 100644 index 0000000000000..61ea6836e415c Binary files /dev/null and b/boards/shields/adafruit_ina219/doc/adafruit_ina219.webp differ diff --git a/boards/shields/adafruit_ina219/doc/index.rst b/boards/shields/adafruit_ina219/doc/index.rst new file mode 100644 index 0000000000000..88aaaec14915a --- /dev/null +++ b/boards/shields/adafruit_ina219/doc/index.rst @@ -0,0 +1,64 @@ +.. _adafruit_ina219: + +Adafruit INA219 Shield +###################### + +Overview +******** + +The `Adafruit INA219 High Side DC Current Sensor Shield`_ features +a `TI INA219 current sensor`_ and two STEMMA QT connectors. +It measures current and bus voltage. + +.. figure:: adafruit_ina219.webp + :align: center + :alt: Adafruit INA219 Shield + + Adafruit INA219 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------+ +| Shield Pin | Function | ++==============+===================+ +| SDA | INA219 I2C SDA | ++--------------+-------------------+ +| SCL | INA219 I2C SCL | ++--------------+-------------------+ +| VIN- | Current sense neg | ++--------------+-------------------+ +| VIN+ | Current sense pos | ++--------------+-------------------+ + +See :dtcompatible:`ti,ina219` for documentation on how to adjust the +devicetree file, for example to adjust the gain. + + +Programming +*********** + +Set ``--shield adafruit_ina219`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`ina219` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/ina219 + :board: adafruit_qt_py_rp2040 + :shield: adafruit_ina219 + :goals: build + +.. _Adafruit INA219 High Side DC Current Sensor Shield: + https://learn.adafruit.com/adafruit-ina219-current-sensor-breakout + +.. _TI INA219 Current sensor: + https://www.ti.com/product/INA219 diff --git a/boards/shields/adafruit_ina219/shield.yml b/boards/shields/adafruit_ina219/shield.yml new file mode 100644 index 0000000000000..6a19654b380fc --- /dev/null +++ b/boards/shields/adafruit_ina219/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_ina219 + full_name: Adafruit INA219 Current Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_ina237/Kconfig.shield b/boards/shields/adafruit_ina237/Kconfig.shield new file mode 100644 index 0000000000000..45621e852485b --- /dev/null +++ b/boards/shields/adafruit_ina237/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_INA237 + def_bool $(shields_list_contains,adafruit_ina237) diff --git a/boards/shields/adafruit_ina237/adafruit_ina237.overlay b/boards/shields/adafruit_ina237/adafruit_ina237.overlay new file mode 100644 index 0000000000000..c86b983a56726 --- /dev/null +++ b/boards/shields/adafruit_ina237/adafruit_ina237.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + /* The shunt resistor on the board is 0.015 Ohm. + * The default max shunt voltage is +/-163.84 mV, + * resulting in a max current range of +/-10.92 Amps. + * For this particular shield is the maximum current rated as 10 A. + * Calculate the current LSB value as 10/2^15 A = 305 uA. + * Round the current LSB value upwards to 500 uA. + */ + adafruit_ina237: ina237@40 { + status = "okay"; + compatible = "ti,ina237"; + reg = <0x40>; + rshunt-micro-ohms= <15000>; + current-lsb-microamps = <500>; + }; +}; diff --git a/boards/shields/adafruit_ina237/doc/adafruit_ina237.webp b/boards/shields/adafruit_ina237/doc/adafruit_ina237.webp new file mode 100644 index 0000000000000..e9a251d740099 Binary files /dev/null and b/boards/shields/adafruit_ina237/doc/adafruit_ina237.webp differ diff --git a/boards/shields/adafruit_ina237/doc/index.rst b/boards/shields/adafruit_ina237/doc/index.rst new file mode 100644 index 0000000000000..0a8fb7fbaa20d --- /dev/null +++ b/boards/shields/adafruit_ina237/doc/index.rst @@ -0,0 +1,62 @@ +.. _adafruit_ina237: + +Adafruit INA237 Shield +###################### + +Overview +******** + +The `Adafruit INA237 DC Current Voltage Power Monitor Sensor Shield`_ features +a `TI INA237 current sensor`_ and two STEMMA QT connectors. +It measures current and bus voltage. + +.. figure:: adafruit_ina237.webp + :align: center + :alt: Adafruit INA237 Shield + + Adafruit INA237 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------+ +| Shield Pin | Function | ++==============+===================+ +| SDA | INA237 I2C SDA | ++--------------+-------------------+ +| SCL | INA237 I2C SCL | ++--------------+-------------------+ +| ALRT | INA237 ALERT out | ++--------------+-------------------+ + +See :dtcompatible:`ti,ina237` for documentation on how to adjust the +devicetree file, for example to adjust the sample averaging. + + +Programming +*********** + +Set ``--shield adafruit_ina237`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`sensor_shell` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: adafruit_qt_py_rp2040 + :shield: adafruit_ina237 + :goals: build + +.. _Adafruit INA237 DC Current Voltage Power Monitor Sensor Shield: + https://learn.adafruit.com/adafruit-ina237-dc-current-voltage-power-monitor + +.. _TI INA237 Current sensor: + https://www.ti.com/product/INA237 diff --git a/boards/shields/adafruit_ina237/shield.yml b/boards/shields/adafruit_ina237/shield.yml new file mode 100644 index 0000000000000..c1a78040fd9f9 --- /dev/null +++ b/boards/shields/adafruit_ina237/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_ina237 + full_name: Adafruit INA237 Current Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_lis2mdl/Kconfig.shield b/boards/shields/adafruit_lis2mdl/Kconfig.shield new file mode 100644 index 0000000000000..0c2323a2ffd3e --- /dev/null +++ b/boards/shields/adafruit_lis2mdl/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_LIS2MDL + def_bool $(shields_list_contains,adafruit_lis2mdl) diff --git a/boards/shields/adafruit_lis2mdl/adafruit_lis2mdl.overlay b/boards/shields/adafruit_lis2mdl/adafruit_lis2mdl.overlay new file mode 100644 index 0000000000000..89931f3b49eca --- /dev/null +++ b/boards/shields/adafruit_lis2mdl/adafruit_lis2mdl.overlay @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + magn0 = &adafruit_lis2mdl; + }; +}; + +&zephyr_i2c { + status = "okay"; + + adafruit_lis2mdl: lis2mdl@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + }; +}; diff --git a/boards/shields/adafruit_lis2mdl/doc/adafruit_lis2mdl.webp b/boards/shields/adafruit_lis2mdl/doc/adafruit_lis2mdl.webp new file mode 100644 index 0000000000000..3ce98a172829b Binary files /dev/null and b/boards/shields/adafruit_lis2mdl/doc/adafruit_lis2mdl.webp differ diff --git a/boards/shields/adafruit_lis2mdl/doc/index.rst b/boards/shields/adafruit_lis2mdl/doc/index.rst new file mode 100644 index 0000000000000..d70555360a44d --- /dev/null +++ b/boards/shields/adafruit_lis2mdl/doc/index.rst @@ -0,0 +1,62 @@ +.. _adafruit_lis2mdl: + +Adafruit LIS2MDL Shield +####################### + +Overview +******** + +The `Adafruit LIS2MDL Triple-axis Magnetometer Sensor Shield`_ features +a `ST LIS2MDL Magnetometer Sensor`_ and two STEMMA QT connectors. + +.. figure:: adafruit_lis2mdl.webp + :align: center + :alt: Adafruit LIS2MDL Shield + + Adafruit LIS2MDL Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+----------------------+ +| Shield Pin | Function | ++==============+======================+ +| SDA | LIS2MDL I2C SDA | ++--------------+----------------------+ +| SCL | LIS2MDL I2C SCL | ++--------------+----------------------+ +| SDO | Not used in I2C mode | ++--------------+----------------------+ +| CS | Not used in I2C mode | ++--------------+----------------------+ + +See :dtcompatible:`st,lis2mdl` for documentation on devicetree settings. + + +Programming +*********** + +Set ``--shield adafruit_lis2mdl`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`magn_polling` magnetometer sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/magn_polling + :board: adafruit_qt_py_rp2040 + :shield: adafruit_lis2mdl + :goals: build + +.. _Adafruit LIS2MDL Triple-axis Magnetometer Sensor Shield: + https://learn.adafruit.com/adafruit-lis2mdl-triple-axis-magnetometer + +.. _ST LIS2MDL Magnetometer Sensor: + https://www.st.com/en/mems-and-sensors/lis2mdl.html diff --git a/boards/shields/adafruit_lis2mdl/shield.yml b/boards/shields/adafruit_lis2mdl/shield.yml new file mode 100644 index 0000000000000..0f1a93cbb6265 --- /dev/null +++ b/boards/shields/adafruit_lis2mdl/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_lis2mdl + full_name: Adafruit LIS2MDL Triple-axis Magnetometer Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_mcp9808/Kconfig.shield b/boards/shields/adafruit_mcp9808/Kconfig.shield new file mode 100644 index 0000000000000..03568e093357e --- /dev/null +++ b/boards/shields/adafruit_mcp9808/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_MCP9808 + def_bool $(shields_list_contains,adafruit_mcp9808) diff --git a/boards/shields/adafruit_mcp9808/adafruit_mcp9808.overlay b/boards/shields/adafruit_mcp9808/adafruit_mcp9808.overlay new file mode 100644 index 0000000000000..c00f436cf4cd4 --- /dev/null +++ b/boards/shields/adafruit_mcp9808/adafruit_mcp9808.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + adafruit_mcp9808: mcp9808@18 { + compatible = "microchip,mcp9808", "jedec,jc-42.4-temp"; + reg = <0x18>; + }; +}; diff --git a/boards/shields/adafruit_mcp9808/doc/adafruit_mcp9808.webp b/boards/shields/adafruit_mcp9808/doc/adafruit_mcp9808.webp new file mode 100644 index 0000000000000..793e64a9f4cb0 Binary files /dev/null and b/boards/shields/adafruit_mcp9808/doc/adafruit_mcp9808.webp differ diff --git a/boards/shields/adafruit_mcp9808/doc/index.rst b/boards/shields/adafruit_mcp9808/doc/index.rst new file mode 100644 index 0000000000000..3fef31010151e --- /dev/null +++ b/boards/shields/adafruit_mcp9808/doc/index.rst @@ -0,0 +1,65 @@ +.. _adafruit_mcp9808: + +Adafruit MCP9808 Shield +####################### + +Overview +******** + +The `Adafruit MCP9808 High Accuracy I2C Temperature Sensor Shield`_ features +a `Microchip MCP9808 Temperature Sensor`_ and two STEMMA QT connectors. + +.. figure:: adafruit_mcp9808.webp + :align: center + :alt: Adafruit MCP9808 Shield + + Adafruit MCP9808 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-----------------------+ +| Shield Pin | Function | ++==============+=======================+ +| SDA | MCP9808 I2C SDA | ++--------------+-----------------------+ +| SCL | MCP9808 I2C SCL | ++--------------+-----------------------+ +| A0 | MCP9808 I2C address | ++--------------+-----------------------+ +| ALERT | MCP9808 interrupt out | ++--------------+-----------------------+ + +In order to use interrupts you need to connect a separate wire from the +shield to a GPIO pin on your microcontroller board. See +:dtcompatible:`jedec,jc-42.4-temp` for documentation on how to adjust the +devicetree file. + + +Programming +*********** + +Set ``--shield adafruit_mcp9808`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`jc42` temperature measurement sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/jc42 + :board: adafruit_qt_py_rp2040 + :shield: adafruit_mcp9808 + :goals: build + +.. _Adafruit MCP9808 High Accuracy I2C Temperature Sensor Shield: + https://learn.adafruit.com/adafruit-mcp9808-precision-i2c-temperature-sensor-guide + +.. _Microchip MCP9808 Temperature Sensor: + https://www.microchip.com/en-us/product/mcp9808 diff --git a/boards/shields/adafruit_mcp9808/shield.yml b/boards/shields/adafruit_mcp9808/shield.yml new file mode 100644 index 0000000000000..135c92d921719 --- /dev/null +++ b/boards/shields/adafruit_mcp9808/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_mcp9808 + full_name: Adafruit MCP9808 High Accuracy I2C Temperature Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_pca9685/doc/adafruit_pca9685.webp b/boards/shields/adafruit_pca9685/doc/adafruit_pca9685.webp new file mode 100644 index 0000000000000..ad72e6bcbd949 Binary files /dev/null and b/boards/shields/adafruit_pca9685/doc/adafruit_pca9685.webp differ diff --git a/boards/shields/adafruit_pca9685/doc/index.rst b/boards/shields/adafruit_pca9685/doc/index.rst index e1d3a43ebf9b7..88329f294d095 100644 --- a/boards/shields/adafruit_pca9685/doc/index.rst +++ b/boards/shields/adafruit_pca9685/doc/index.rst @@ -12,6 +12,13 @@ UNO R3 compatible shield based on the NXP PCA9685 IC. More information about the shield can be found at the `Adafruit 16-channel PWM/Servo Shield webpage`_. +.. figure:: adafruit_pca9685.webp + :align: center + :alt: Adafruit 16-channel PWM/Servo Shield + + Adafruit 16-channel PWM/Servo Shield (Credit: Adafruit) + + Pins Assignments ================ diff --git a/boards/shields/adafruit_tsl2591/Kconfig.shield b/boards/shields/adafruit_tsl2591/Kconfig.shield new file mode 100644 index 0000000000000..94f28e9d0aa52 --- /dev/null +++ b/boards/shields/adafruit_tsl2591/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_TSL2591 + def_bool $(shields_list_contains,adafruit_tsl2591) diff --git a/boards/shields/adafruit_tsl2591/adafruit_tsl2591.overlay b/boards/shields/adafruit_tsl2591/adafruit_tsl2591.overlay new file mode 100644 index 0000000000000..83714223e064c --- /dev/null +++ b/boards/shields/adafruit_tsl2591/adafruit_tsl2591.overlay @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + light-sensor = &adafruit_tsl2591; + }; +}; + +&zephyr_i2c { + status = "okay"; + + adafruit_tsl2591: tsl2591@29 { + compatible = "ams,tsl2591"; + reg = <0x29>; + }; +}; diff --git a/boards/shields/adafruit_tsl2591/doc/adafruit_tsl2591.webp b/boards/shields/adafruit_tsl2591/doc/adafruit_tsl2591.webp new file mode 100644 index 0000000000000..f9681b6a0d979 Binary files /dev/null and b/boards/shields/adafruit_tsl2591/doc/adafruit_tsl2591.webp differ diff --git a/boards/shields/adafruit_tsl2591/doc/index.rst b/boards/shields/adafruit_tsl2591/doc/index.rst new file mode 100644 index 0000000000000..4833c0a7a32c6 --- /dev/null +++ b/boards/shields/adafruit_tsl2591/doc/index.rst @@ -0,0 +1,63 @@ +.. _adafruit_tsl2591: + +Adafruit TSL2591 Shield +####################### + +Overview +******** + +The `Adafruit TSL2591 High Dynamic Range Digital Light Sensor Shield`_ features +an `OSRAM TSL2591 Ambient Light Sensor`_ and two STEMMA QT connectors. + +.. figure:: adafruit_tsl2591.webp + :align: center + :alt: Adafruit TSL2591 Shield + + Adafruit TSL2591 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-----------------------+ +| Shield Pin | Function | ++==============+=======================+ +| SDA | TSL2591 I2C SDA | ++--------------+-----------------------+ +| SCL | TSL2591 I2C SCL | ++--------------+-----------------------+ +| INT | TSL2591 interrupt out | ++--------------+-----------------------+ + +In order to use interrupts you need to connect a separate wire from the +shield to a GPIO pin on your microcontroller board. See +:dtcompatible:`ams,tsl2591` for documentation on how to adjust the +devicetree file. + + +Programming +*********** + +Set ``--shield adafruit_tsl2591`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`light_sensor_polling` light measurement sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: adafruit_qt_py_rp2040 + :shield: adafruit_tsl2591 + :goals: build + +.. _Adafruit TSL2591 High Dynamic Range Digital Light Sensor Shield: + https://learn.adafruit.com/adafruit-tsl2591 + +.. _OSRAM TSL2591 Ambient Light Sensor: + https://ams-osram.com/products/sensor-solutions/ambient-light-color-spectral-proximity-sensors/ams-tsl25911-ambient-light-sensor diff --git a/boards/shields/adafruit_tsl2591/shield.yml b/boards/shields/adafruit_tsl2591/shield.yml new file mode 100644 index 0000000000000..077b3ddae1c3d --- /dev/null +++ b/boards/shields/adafruit_tsl2591/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_tsl2591 + full_name: Adafruit TSL2591 High Dynamic Range Digital Light Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_vcnl4040/Kconfig.shield b/boards/shields/adafruit_vcnl4040/Kconfig.shield new file mode 100644 index 0000000000000..6d221c57a772e --- /dev/null +++ b/boards/shields/adafruit_vcnl4040/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_VCNL4040 + def_bool $(shields_list_contains,adafruit_vcnl4040) diff --git a/boards/shields/adafruit_vcnl4040/adafruit_vcnl4040.overlay b/boards/shields/adafruit_vcnl4040/adafruit_vcnl4040.overlay new file mode 100644 index 0000000000000..d888a2da17159 --- /dev/null +++ b/boards/shields/adafruit_vcnl4040/adafruit_vcnl4040.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + adafruit_vcnl4040: vcnl4040@60 { + compatible = "vishay,vcnl4040"; + reg = <0x60>; + }; +}; diff --git a/boards/shields/adafruit_vcnl4040/doc/adafruit_vcnl4040.webp b/boards/shields/adafruit_vcnl4040/doc/adafruit_vcnl4040.webp new file mode 100644 index 0000000000000..a585be11bd3cc Binary files /dev/null and b/boards/shields/adafruit_vcnl4040/doc/adafruit_vcnl4040.webp differ diff --git a/boards/shields/adafruit_vcnl4040/doc/index.rst b/boards/shields/adafruit_vcnl4040/doc/index.rst new file mode 100644 index 0000000000000..8f03ba6d514be --- /dev/null +++ b/boards/shields/adafruit_vcnl4040/doc/index.rst @@ -0,0 +1,62 @@ +.. _adafruit_vcnl4040: + +Adafruit VCNL4040 Shield +######################## + +Overview +******** + +The `Adafruit VCNL4040 Proximity and Lux Sensor Shield`_ features +a `Vishay VCNL4040 Proximity and Lux Sensor`_ and two STEMMA QT connectors. + +.. figure:: adafruit_vcnl4040.webp + :align: center + :alt: Adafruit VCNL4040 Shield + + Adafruit VCNL4040 Shield (Credit: Adafruit) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+------------------------+ +| Shield Pin | Function | ++==============+========================+ +| SDA | VCNL4040 I2C SDA | ++--------------+------------------------+ +| SCL | VCNL4040 I2C SCL | ++--------------+------------------------+ +| INT | VCNL4040 interrupt out | ++--------------+------------------------+ + +In order to use interrupts you need to connect a separate wire from the +shield to a GPIO pin on your microcontroller board. See +:dtcompatible:`vishay,vcnl4040` for documentation on how to adjust the +devicetree file. + +Programming +*********** + +Set ``--shield adafruit_vcnl4040`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`vcnl4040` proximity and light sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/vcnl4040/ + :board: adafruit_qt_py_rp2040 + :shield: adafruit_vcnl4040 + :goals: build + +.. _Adafruit VCNL4040 Proximity and Lux Sensor Shield: + https://learn.adafruit.com/adafruit-vcnl4040-proximity-sensor + +.. _Vishay VCNL4040 Proximity and Lux Sensor: + https://www.vishay.com/en/product/84274/ diff --git a/boards/shields/adafruit_vcnl4040/shield.yml b/boards/shields/adafruit_vcnl4040/shield.yml new file mode 100644 index 0000000000000..3a65c29773932 --- /dev/null +++ b/boards/shields/adafruit_vcnl4040/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: adafruit_vcnl4040 + full_name: Adafruit VCNL4040 Proximity and Lux Sensor Shield + vendor: adafruit + supported_features: + - sensor diff --git a/boards/shields/adafruit_winc1500/adafruit_winc1500.overlay b/boards/shields/adafruit_winc1500/adafruit_winc1500.overlay index c4f72ac4a3a2e..55b0ae021b7c5 100644 --- a/boards/shields/adafruit_winc1500/adafruit_winc1500.overlay +++ b/boards/shields/adafruit_winc1500/adafruit_winc1500.overlay @@ -4,17 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 0>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 0>; winc1500_adafruit_winc1500: winc1500@0 { status = "ok"; compatible = "atmel,winc1500"; reg = <0x0>; spi-max-frequency = <4000000>; - irq-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ - reset-gpios = <&arduino_header 11 GPIO_ACTIVE_LOW>; /* D5 */ - enable-gpios = <&arduino_header 12 0>; /* D6 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_LOW>; + enable-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 0>; }; }; diff --git a/boards/shields/amg88xx/amg88xx_eval_kit.overlay b/boards/shields/amg88xx/amg88xx_eval_kit.overlay index e233e18526a53..009b873151bfb 100644 --- a/boards/shields/amg88xx/amg88xx_eval_kit.overlay +++ b/boards/shields/amg88xx/amg88xx_eval_kit.overlay @@ -4,14 +4,15 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_i2c { status = "okay"; amg88xx_amg88xx_eval_kit: amg88xx@68 { compatible = "panasonic,amg88xx"; reg = <0x68>; - /* Pin D6 from Arduino Connector */ - int-gpios = <&arduino_header 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; status = "okay"; }; }; diff --git a/boards/shields/amg88xx/amg88xx_grid_eye_eval_shield.overlay b/boards/shields/amg88xx/amg88xx_grid_eye_eval_shield.overlay index c05e6221b1901..d1ebf6fe1e759 100644 --- a/boards/shields/amg88xx/amg88xx_grid_eye_eval_shield.overlay +++ b/boards/shields/amg88xx/amg88xx_grid_eye_eval_shield.overlay @@ -3,13 +3,14 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_i2c { status = "okay"; amg88xx_amg88xx_grid_eye_eval_shield: amg88xx@68 { compatible = "panasonic,amg88xx"; reg = <0x68>; - /* Pin D2 from Arduino Connector */ - int-gpios = <&arduino_header 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; status = "okay"; }; }; diff --git a/boards/shields/arceli_eth_w5500/arceli_eth_w5500.overlay b/boards/shields/arceli_eth_w5500/arceli_eth_w5500.overlay index 9e8b77abf9f3c..2a5a0b15612ad 100644 --- a/boards/shields/arceli_eth_w5500/arceli_eth_w5500.overlay +++ b/boards/shields/arceli_eth_w5500/arceli_eth_w5500.overlay @@ -2,6 +2,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; @@ -9,7 +11,7 @@ compatible = "wiznet,w5500"; reg = <0x0>; spi-max-frequency = <80000000>; - int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; }; }; diff --git a/boards/shields/atmel_rf2xx/atmel_rf2xx_arduino.overlay b/boards/shields/atmel_rf2xx/atmel_rf2xx_arduino.overlay index bdd82491c1aba..c71345277e8bf 100644 --- a/boards/shields/atmel_rf2xx/atmel_rf2xx_arduino.overlay +++ b/boards/shields/atmel_rf2xx/atmel_rf2xx_arduino.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,ieee802154 = &ieee802154_atmel_rf2xx_arduino; @@ -13,21 +15,17 @@ &arduino_spi { status = "okay"; - /* D10 */ - cs-gpios = <&arduino_header 16 + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; ieee802154_atmel_rf2xx_arduino: rf2xx@0 { compatible = "atmel,rf2xx"; reg = <0x0>; spi-max-frequency = <6000000>; - /* D2 */ - irq-gpios = <&arduino_header 8 + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; - /* D8 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; - /* D9 */ - slptr-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; + slptr-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay b/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay index 48261f8b92058..69866276b339f 100644 --- a/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay @@ -5,6 +5,7 @@ */ #include +#include / { chosen { @@ -22,8 +23,8 @@ buydisplay_2_8_tft_touch_arduino_mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ - reset-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; spi-dev = <&arduino_spi>; write-only; #address-cells = <1>; @@ -49,7 +50,7 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; }; &arduino_i2c { @@ -57,6 +58,6 @@ compatible = "focaltech,ft5336"; reg = <0x38>; /* Uncomment if IRQ line is available (requires to solder jumper) */ - /* int-gpios = <&arduino_header 11 GPIO_ACTIVE_LOW>; */ /* D5 */ + /* int-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_LOW>; */ }; }; diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay b/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay index a5ca069697433..7f2faa2df707b 100644 --- a/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay +++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay @@ -5,6 +5,7 @@ */ #include +#include / { chosen { @@ -22,8 +23,8 @@ buydisplay_3_5_tft_touch_arduino_mipi_dbi { compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ - reset-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; spi-dev = <&arduino_spi>; write-only; #address-cells = <1>; @@ -48,7 +49,7 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; }; &arduino_i2c { @@ -56,6 +57,6 @@ compatible = "focaltech,ft5336"; reg = <0x38>; /* Uncomment if IRQ line is available (requires to solder jumper) */ - /* int-gpios = <&arduino_header 11 GPIO_ACTIVE_LOW>; */ /* D5 */ + /* int-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_LOW>; */ }; }; diff --git a/boards/shields/dac80508_evm/dac80508_evm.overlay b/boards/shields/dac80508_evm/dac80508_evm.overlay index 34482b784a9eb..1e5e5715b9dd9 100644 --- a/boards/shields/dac80508_evm/dac80508_evm.overlay +++ b/boards/shields/dac80508_evm/dac80508_evm.overlay @@ -4,9 +4,11 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; dac80508_dac80508_evm: dac80508@0 { compatible = "ti,dac80508"; diff --git a/boards/shields/eval_ad4052_ardz/eval_ad4052_ardz.overlay b/boards/shields/eval_ad4052_ardz/eval_ad4052_ardz.overlay index 856bdf9877c9e..a976612109f48 100644 --- a/boards/shields/eval_ad4052_ardz/eval_ad4052_ardz.overlay +++ b/boards/shields/eval_ad4052_ardz/eval_ad4052_ardz.overlay @@ -4,15 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; adc4052_eval_ad4052_ardz: adc4052@0 { reg = <0>; spi-max-frequency = ; - gp1-gpios = <&arduino_header 14 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; - gp0-gpios = <&arduino_header 15 (GPIO_PULL_DOWN)>; - conversion-gpios = <&arduino_header 12 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; + gp1-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + gp0-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 (GPIO_PULL_DOWN)>; + conversion-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 + (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; diff --git a/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay b/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay index 777730ccf7e73..7efc405971d7a 100644 --- a/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay +++ b/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay @@ -5,6 +5,7 @@ */ #include +#include &arduino_spi { status = "okay"; @@ -13,7 +14,7 @@ compatible = "adi,adxl362"; reg = <0x0>; spi-max-frequency = ; - int1-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_HIGH>; fifo-mode = ; fifo-watermark = <0x80>; status = "okay"; diff --git a/boards/shields/eval_adxl367_ardz/eval_adxl367_ardz.overlay b/boards/shields/eval_adxl367_ardz/eval_adxl367_ardz.overlay index 98ab6236991a0..f9ab3e0c18aee 100644 --- a/boards/shields/eval_adxl367_ardz/eval_adxl367_ardz.overlay +++ b/boards/shields/eval_adxl367_ardz/eval_adxl367_ardz.overlay @@ -5,6 +5,7 @@ */ #include +#include / { aliases { @@ -19,7 +20,7 @@ compatible = "adi,adxl367"; reg = <0x0>; spi-max-frequency = ; - int1-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_HIGH>; fifo-mode = ; status = "okay"; }; diff --git a/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay b/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay index a7579e16c71c7..1f8c33876608e 100644 --- a/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay +++ b/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay @@ -5,6 +5,7 @@ */ #include +#include &arduino_spi { @@ -14,7 +15,7 @@ compatible = "adi,adxl372"; reg = <0x0>; spi-max-frequency = ; - int1-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; fifo-mode = ; fifo-watermark = <0x80>; status = "okay"; diff --git a/boards/shields/frdm_cr20a/frdm_cr20a.overlay b/boards/shields/frdm_cr20a/frdm_cr20a.overlay index c211946b670bb..3d6621ac89a02 100644 --- a/boards/shields/frdm_cr20a/frdm_cr20a.overlay +++ b/boards/shields/frdm_cr20a/frdm_cr20a.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,ieee802154 = &ieee802154_frdm_cr20a; @@ -17,9 +19,9 @@ compatible = "nxp,mcr20a"; reg = <0x0>; spi-max-frequency = <4000000>; - irqb-gpios = <&arduino_header 8 - (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* D2 */ - reset-gpios = <&arduino_header 11 GPIO_ACTIVE_LOW>; /* D5 */ + irqb-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 + (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_LOW>; status = "okay"; }; }; diff --git a/boards/shields/frdm_stbc_agm01/frdm_stbc_agm01.overlay b/boards/shields/frdm_stbc_agm01/frdm_stbc_agm01.overlay index 208888340a3bb..970943815f6a6 100644 --- a/boards/shields/frdm_stbc_agm01/frdm_stbc_agm01.overlay +++ b/boards/shields/frdm_stbc_agm01/frdm_stbc_agm01.overlay @@ -3,6 +3,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { magn0 = &fxos8700_1e_frdm_stbc_agm01; @@ -14,14 +16,14 @@ fxos8700_1e_frdm_stbc_agm01: fxos8700@1e { compatible = "nxp,fxos8700"; reg = <0x1e>; - int1-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; - int2-gpios = <&arduino_header 10 GPIO_ACTIVE_LOW>; + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_LOW>; + int2-gpios = <&arduino_header ARDUINO_HEADER_R3_D4 GPIO_ACTIVE_LOW>; }; fxas21002_frdm_stbc_agm01: fxas21002@20 { compatible = "nxp,fxas21002"; reg = <0x20>; - int1-gpios = <&arduino_header 11 GPIO_ACTIVE_LOW>; - int2-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_LOW>; + int2-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; }; }; diff --git a/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay b/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay index faa68a2a43e72..4ea409e448b21 100644 --- a/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay +++ b/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay @@ -4,19 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - /* D10 */ - cs-gpios = <&arduino_header 16 + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; ft800_ftdi_vm800c: ft800@0 { compatible = "ftdi,ft800"; reg = <0x0>; spi-max-frequency = <8000000>; - /* D2 */ - irq-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_LOW>; pclk = <5>; pclk-pol = <1>; diff --git a/boards/shields/inventek_eswifi/inventek_eswifi_arduino_spi.overlay b/boards/shields/inventek_eswifi/inventek_eswifi_arduino_spi.overlay index bcee3b924cb7c..26a2ffac55495 100644 --- a/boards/shields/inventek_eswifi/inventek_eswifi_arduino_spi.overlay +++ b/boards/shields/inventek_eswifi/inventek_eswifi_arduino_spi.overlay @@ -4,11 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - /* D10 */ - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; wifi0_inventek_eswifi_arduino_spi: iwin@0 { status = "okay"; @@ -16,13 +17,9 @@ spi-max-frequency = <2000000>; reg = <0>; - /* D9 */ - data-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; - /* D7 */ - wakeup-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; - /* D6 */ - resetn-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; - /* D5 */ - boot0-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; + data-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; + resetn-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; + boot0-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/inventek_eswifi/inventek_eswifi_arduino_uart.overlay b/boards/shields/inventek_eswifi/inventek_eswifi_arduino_uart.overlay index c69d4903ccf05..c35193ef1e770 100644 --- a/boards/shields/inventek_eswifi/inventek_eswifi_arduino_uart.overlay +++ b/boards/shields/inventek_eswifi/inventek_eswifi_arduino_uart.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_serial { status = "okay"; @@ -11,9 +13,7 @@ status = "okay"; compatible = "inventek,eswifi-uart"; - /* D7 */ - wakeup-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; - /* D6 */ - resetn-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; + resetn-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/link_board_eth/link_board_eth.overlay b/boards/shields/link_board_eth/link_board_eth.overlay index 56c744a867afb..7c84b70452f99 100644 --- a/boards/shields/link_board_eth/link_board_eth.overlay +++ b/boards/shields/link_board_eth/link_board_eth.overlay @@ -4,14 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; enc424j600_link_board_eth: enc424j600@0 { compatible = "microchip,enc424j600"; spi-max-frequency = <14000000>; - int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; status = "okay"; reg = <0>; }; diff --git a/boards/shields/lmp90100_evb/lmp90100_evb.overlay b/boards/shields/lmp90100_evb/lmp90100_evb.overlay index e30840dd10bde..feb580801582b 100644 --- a/boards/shields/lmp90100_evb/lmp90100_evb.overlay +++ b/boards/shields/lmp90100_evb/lmp90100_evb.overlay @@ -6,6 +6,7 @@ #include #include +#include &arduino_spi { status = "okay"; @@ -15,7 +16,7 @@ reg = <0x0>; spi-max-frequency = <1000000>; /* Uncomment to use IRQ instead of polling: */ - /* drdyb-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; */ + /* drdyb-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; */ #io-channel-cells = <1>; lmp90100_gpio: gpio { diff --git a/boards/shields/ls0xx_generic/ls013b7dh03.overlay b/boards/shields/ls0xx_generic/ls013b7dh03.overlay index 9eb0f09b9489a..2a422f33ded4a 100644 --- a/boards/shields/ls0xx_generic/ls013b7dh03.overlay +++ b/boards/shields/ls0xx_generic/ls013b7dh03.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,display = &ls0xx_ls013b7dh03; @@ -12,7 +14,7 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_HIGH>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_HIGH>; ls0xx_ls013b7dh03: ls0xx@0 { compatible = "sharp,ls0xx"; @@ -20,8 +22,8 @@ reg = <0>; width = <128>; height = <128>; - extcomin-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */ + extcomin-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_HIGH>; extcomin-frequency = <60>; /* required if extcomin-gpios is defined */ - disp-en-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */ + disp-en-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/max3421e/sparkfun_max3421e.overlay b/boards/shields/max3421e/sparkfun_max3421e.overlay index cbad6a3eef1b8..f4eb770c6af5f 100644 --- a/boards/shields/max3421e/sparkfun_max3421e.overlay +++ b/boards/shields/max3421e/sparkfun_max3421e.overlay @@ -4,15 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; zephyr_uhc0: max3421e@0 { compatible = "maxim,max3421e_spi"; spi-max-frequency = <26000000>; - int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ - reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; status = "okay"; reg = <0>; }; diff --git a/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay b/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay index 290522d8c921f..cfdcf78e5c097 100644 --- a/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay +++ b/boards/shields/mcp2515/dfrobot_can_bus_v2_0.overlay @@ -4,14 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; mcp2515_dfrobot_can_bus_v2_0: can@0 { compatible = "microchip,mcp2515"; spi-max-frequency = <1000000>; - int-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */ + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_LOW>; status = "okay"; reg = <0x0>; osc-freq = <16000000>; diff --git a/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay b/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay index d1f988f281ed7..4672c60df2769 100644 --- a/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay +++ b/boards/shields/mcp2515/keyestudio_can_bus_ks0411.overlay @@ -4,14 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; mcp2515_keyestudio_can_bus_ks0411: can@0 { compatible = "microchip,mcp2515"; spi-max-frequency = <1000000>; - int-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; status = "okay"; reg = <0x0>; osc-freq = <16000000>; diff --git a/boards/shields/mikroe_3d_hall_3_click/Kconfig.shield b/boards/shields/mikroe_3d_hall_3_click/Kconfig.shield new file mode 100644 index 0000000000000..233e2e1cd07f8 --- /dev/null +++ b/boards/shields/mikroe_3d_hall_3_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_3D_HALL_3_CLICK + def_bool $(shields_list_contains,mikroe_3d_hall_3_click) diff --git a/boards/shields/mikroe_3d_hall_3_click/doc/images/mikroe_3d_hall_3_click.webp b/boards/shields/mikroe_3d_hall_3_click/doc/images/mikroe_3d_hall_3_click.webp new file mode 100644 index 0000000000000..a416034c07131 Binary files /dev/null and b/boards/shields/mikroe_3d_hall_3_click/doc/images/mikroe_3d_hall_3_click.webp differ diff --git a/boards/shields/mikroe_3d_hall_3_click/doc/index.rst b/boards/shields/mikroe_3d_hall_3_click/doc/index.rst new file mode 100644 index 0000000000000..bd6128f711b66 --- /dev/null +++ b/boards/shields/mikroe_3d_hall_3_click/doc/index.rst @@ -0,0 +1,52 @@ +.. _mikroe_3d_hall_3_click_shield: + +MikroElektronika 3D Hall 3 Click +================================ + +Overview +******** + +`3D Hall 3 Click`_ is a very accurate, magnetic field sensing Click board™, used to measure the +intensity of the magnetic field across three perpendicular axes. + +It is equipped with the LIS2MDL, a low power 3D magnetic sensor. This IC has a separate Hall sensing +element on each axis, which allows a very accurate and reliable measurement of the magnetic field +intensity in a 3D space, offering a basis for accurate positional calculations. Both I2C and SPI +communication protocols are supported by the LIS2MDL. This sensor IC features a powerful +programmable interrupt engine, allowing firmware optimization. + +.. figure:: images/mikroe_3d_hall_3_click.webp + :align: center + :alt: 3D Hall 3 Click + :height: 300px + + 3D Hall 3 Click + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_i2c`` node label for the mikroBUS™ I2C interface. See :ref:`shields` for more details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_3d_hall_3_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/magn_polling + :board: mikroe_clicker_ra4m1/r7fa4m1ab3cfm + :shield: mikroe_3d_hall_3_click + :goals: build + +See :dtcompatible:`st,lis2mdl` for documentation on the additional binding properties available for +the LIS2MDL sensor. + +References +********** + +- `3D Hall 3 Click`_ +- `3D Hall 3 Click schematic`_ + +.. _3D Hall 3 Click: https://www.mikroe.com/3d-hall-3-click +.. _3D Hall 3 Click schematic: https://download.mikroe.com/documents/add-on-boards/click/3d-hall-3/3d-hall-3-click-schematic-v100.pdf diff --git a/boards/shields/mikroe_3d_hall_3_click/mikroe_3d_hall_3_click.overlay b/boards/shields/mikroe_3d_hall_3_click/mikroe_3d_hall_3_click.overlay new file mode 100644 index 0000000000000..3793233e54e2a --- /dev/null +++ b/boards/shields/mikroe_3d_hall_3_click/mikroe_3d_hall_3_click.overlay @@ -0,0 +1,20 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + magn0 = &lis2mdl_mikroe_3d_hall_3_click; + }; +}; + +&mikrobus_i2c { + status = "okay"; + + lis2mdl_mikroe_3d_hall_3_click: lis2mdl@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + irq-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/mikroe_3d_hall_3_click/shield.yml b/boards/shields/mikroe_3d_hall_3_click/shield.yml new file mode 100644 index 0000000000000..0f154a6f63796 --- /dev/null +++ b/boards/shields/mikroe_3d_hall_3_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_3d_hall_3_click + full_name: 3D Hall 3 Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_air_quality_3_click/Kconfig.shield b/boards/shields/mikroe_air_quality_3_click/Kconfig.shield new file mode 100644 index 0000000000000..30f7de4c62375 --- /dev/null +++ b/boards/shields/mikroe_air_quality_3_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_AIR_QUALITY_3_CLICK + def_bool $(shields_list_contains,mikroe_air_quality_3_click) diff --git a/boards/shields/mikroe_air_quality_3_click/doc/images/mikroe_air_quality_3_click.webp b/boards/shields/mikroe_air_quality_3_click/doc/images/mikroe_air_quality_3_click.webp new file mode 100644 index 0000000000000..022972d062532 Binary files /dev/null and b/boards/shields/mikroe_air_quality_3_click/doc/images/mikroe_air_quality_3_click.webp differ diff --git a/boards/shields/mikroe_air_quality_3_click/doc/index.rst b/boards/shields/mikroe_air_quality_3_click/doc/index.rst new file mode 100644 index 0000000000000..268f132a1430e --- /dev/null +++ b/boards/shields/mikroe_air_quality_3_click/doc/index.rst @@ -0,0 +1,51 @@ +.. _mikroe_air_quality_3_click_shield: + +MikroElektronika Air Quality 3 Click +==================================== + +Overview +******** + +`Air Quality 3 Click`_ is the air quality measurement device, which is able to output both +equivalent CO2 levels and total volatile organic compounds (TVOC) concentration in the indoor +environment. + +The Click board™ is equipped with the CCS811 state-of-the-art air quality sensor IC from ScioSense, +which has an integrated MCU and a specially designed metal oxide (MOX) gas sensor microplate, +allowing for high reliability, fast cycle times and a significant reduction in the power +consumption, compared to other MOX sensor-based devices. The Click board™ is also equipped with a +temperature compensating element, which allows for increased measurement accuracy. + +.. figure:: images/mikroe_air_quality_3_click.webp + :align: center + :alt: Air Quality 3 Click + :height: 300px + + Air Quality 3 Click + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_air_quality_3_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/ccs811 + :board: mikroe_clicker_ra4m1 + :shield: mikroe_air_quality_3_click + :goals: build + +References +********** + +- `Air Quality 3 Click`_ +- `Air Quality 3 Click schematic`_ + +.. _Air Quality 3 Click: https://www.mikroe.com/air-quality-3-click +.. _Air Quality 3 Click schematic: https://download.mikroe.com/documents/add-on-boards/click/air-quality-3/air-quality-3-click-schematic-v100.pdf diff --git a/boards/shields/mikroe_air_quality_3_click/mikroe_air_quality_3_click.overlay b/boards/shields/mikroe_air_quality_3_click/mikroe_air_quality_3_click.overlay new file mode 100644 index 0000000000000..a35f7392a4c08 --- /dev/null +++ b/boards/shields/mikroe_air_quality_3_click/mikroe_air_quality_3_click.overlay @@ -0,0 +1,16 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_i2c { + status = "okay"; + + ccs811_mikroe_air_quality_3_click: ccs811@5a { + compatible = "ams,ccs811"; + reg = <0x5a>; + reset-gpios = <&mikrobus_header 1 GPIO_ACTIVE_LOW>; + wake-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + irq-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/mikroe_air_quality_3_click/shield.yml b/boards/shields/mikroe_air_quality_3_click/shield.yml new file mode 100644 index 0000000000000..4561b0cb4d53d --- /dev/null +++ b/boards/shields/mikroe_air_quality_3_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_air_quality_3_click + full_name: Air Quality 3 Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_ambient_2_click/Kconfig.shield b/boards/shields/mikroe_ambient_2_click/Kconfig.shield new file mode 100644 index 0000000000000..6b6e773dee809 --- /dev/null +++ b/boards/shields/mikroe_ambient_2_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_AMBIENT_2_CLICK + def_bool $(shields_list_contains,mikroe_ambient_2_click) diff --git a/boards/shields/mikroe_ambient_2_click/doc/images/mikroe_ambient_2_click.webp b/boards/shields/mikroe_ambient_2_click/doc/images/mikroe_ambient_2_click.webp new file mode 100644 index 0000000000000..524cbfd8ca367 Binary files /dev/null and b/boards/shields/mikroe_ambient_2_click/doc/images/mikroe_ambient_2_click.webp differ diff --git a/boards/shields/mikroe_ambient_2_click/doc/index.rst b/boards/shields/mikroe_ambient_2_click/doc/index.rst new file mode 100644 index 0000000000000..4cdd1678851e9 --- /dev/null +++ b/boards/shields/mikroe_ambient_2_click/doc/index.rst @@ -0,0 +1,51 @@ +.. _mikroe_ambient_2_click_shield: + +MikroElektronika Ambient 2 Click +================================ + +Overview +******** + +`Ambient 2 Click`_ is a compact add-on board that measures only the visible part of the light +spectrum from any source (mimicking how humans see the light). + +This board features the OPT3001, a digital output ambient light sensor with an I2C interface and +interrupt from Texas Instruments. The sensor's spectral response tightly matches the human eye's +photopic response and includes significant (99%) infrared rejection. It has a flexible and wide +operating range for the ambient light sensor with a resolution of 0.01lux and full detectable +illumination of 83865.6lux over a 23-bit effective dynamic range. This Click board |trade| is the +most suitable for obtaining ambient light data in applications such as automatic residential and +commercial lighting management. + +.. figure:: images/mikroe_ambient_2_click.webp + :align: center + :alt: Ambient 2 Click + :height: 300px + + Ambient 2 Click + +Requirements +************ + + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interfac e. See :ref:`shields` for more +details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_ambient_2_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: mikroe_clicker_ra4m1 + :shield: mikroe_ambient_2_click + :goals: build + +References +********** + +- `Ambient 2 Click`_ + +.. _Ambient 2 Click: https://www.mikroe.com/ambient-2-click diff --git a/boards/shields/mikroe_ambient_2_click/mikroe_ambient_2_click.overlay b/boards/shields/mikroe_ambient_2_click/mikroe_ambient_2_click.overlay new file mode 100644 index 0000000000000..65b3063b794e5 --- /dev/null +++ b/boards/shields/mikroe_ambient_2_click/mikroe_ambient_2_click.overlay @@ -0,0 +1,20 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + light-sensor = &opt3001_mikroe_ambient_2_click; + }; +}; + +&mikrobus_i2c { + status = "okay"; + + opt3001_mikroe_ambient_2_click: opt3001@44 { + compatible = "ti,opt3001"; + reg = <0x44>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/mikroe_ambient_2_click/shield.yml b/boards/shields/mikroe_ambient_2_click/shield.yml new file mode 100644 index 0000000000000..ebf6680ccd272 --- /dev/null +++ b/boards/shields/mikroe_ambient_2_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_ambient_2_click + full_name: Ambient 2 Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_h_bridge_4_click/doc/index.rst b/boards/shields/mikroe_h_bridge_4_click/doc/index.rst index 7216d08246ef7..7c55b3d9c8157 100644 --- a/boards/shields/mikroe_h_bridge_4_click/doc/index.rst +++ b/boards/shields/mikroe_h_bridge_4_click/doc/index.rst @@ -33,5 +33,13 @@ Programming .. zephyr-app-commands:: :zephyr-app: samples/drivers/stepper/generic :board: - :west-args: --shield mikroe_h_bridge_4_click + :shield: mikroe_h_bridge_4_click :goals: build flash + +References +********** + +.. target-notes:: + +.. _Mikroe H-Bridge 4 click: + https://www.mikroe.com/h-bridge-4-click diff --git a/boards/shields/mikroe_h_bridge_4_click/mikroe_h_bridge_4_click.overlay b/boards/shields/mikroe_h_bridge_4_click/mikroe_h_bridge_4_click.overlay index 953280a470e4b..1c3143cc7262b 100644 --- a/boards/shields/mikroe_h_bridge_4_click/mikroe_h_bridge_4_click.overlay +++ b/boards/shields/mikroe_h_bridge_4_click/mikroe_h_bridge_4_click.overlay @@ -3,6 +3,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/ { + aliases { + stepper = &mikroe_h_bridge_4_click; + }; +}; + / { mikroe_h_bridge_4_click: h_bridge_4_click { status = "okay"; diff --git a/boards/shields/mikroe_illuminance_click/Kconfig.shield b/boards/shields/mikroe_illuminance_click/Kconfig.shield new file mode 100644 index 0000000000000..da51edc0516f1 --- /dev/null +++ b/boards/shields/mikroe_illuminance_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_ILLUMINANCE_CLICK + def_bool $(shields_list_contains,mikroe_illuminance_click) diff --git a/boards/shields/mikroe_illuminance_click/doc/images/mikroe_illuminance_click.webp b/boards/shields/mikroe_illuminance_click/doc/images/mikroe_illuminance_click.webp new file mode 100644 index 0000000000000..5829926cf6824 Binary files /dev/null and b/boards/shields/mikroe_illuminance_click/doc/images/mikroe_illuminance_click.webp differ diff --git a/boards/shields/mikroe_illuminance_click/doc/index.rst b/boards/shields/mikroe_illuminance_click/doc/index.rst new file mode 100644 index 0000000000000..97c7d4505fbcf --- /dev/null +++ b/boards/shields/mikroe_illuminance_click/doc/index.rst @@ -0,0 +1,50 @@ +.. _mikroe_illuminance_click_shield: + +MikroElektronika Illuminance Click +================================== + +Overview +******** + +`Illuminance Click`_ is a compact add-on board that mimics how humans perceive light. This board +features ams OSRAM TSL2583, a very-high sensitivity light-to-digital converter that transforms light +intensity to a digital signal output capable of the direct I2C interface. It combines one broadband +photodiode (visible plus infrared) and one infrared-responding photodiode on a single CMOS +integrated circuit capable of providing a near-photopic response over an effective 16-bit dynamic +range (16-bit resolution). This Click board |trade| is suitable for general-purpose light sensing +applications to extend battery life and provide optimum viewing in diverse lighting conditions. + +.. figure:: images/mikroe_illuminance_click.webp + :align: center + :alt: Illuminance Click + :height: 300px + + Illuminance Click + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_illuminance_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/light_polling + :board: mikroe_quail + :shield: mikroe_illuminance_click + :goals: build + +See :dtcompatible:`ams,tsl2561` for documentation on the additional binding properties available for +the TSL2561 sensor, for example to adjust the gain and integration time. + +References +********** + +- `Illuminance Click`_ + +.. _Illuminance Click: https://www.mikroe.com/illuminance-click diff --git a/boards/shields/mikroe_illuminance_click/mikroe_illuminance_click.overlay b/boards/shields/mikroe_illuminance_click/mikroe_illuminance_click.overlay new file mode 100644 index 0000000000000..80943eaab1965 --- /dev/null +++ b/boards/shields/mikroe_illuminance_click/mikroe_illuminance_click.overlay @@ -0,0 +1,19 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + light-sensor = &tsl2561_mikroe_illuminance_click; + }; +}; + +&mikrobus_i2c { + status = "okay"; + + tsl2561_mikroe_illuminance_click: tsl2561@49 { + compatible = "ams,tsl2561"; + reg = <0x49>; + }; +}; diff --git a/boards/shields/mikroe_illuminance_click/shield.yml b/boards/shields/mikroe_illuminance_click/shield.yml new file mode 100644 index 0000000000000..b3ed1fde62775 --- /dev/null +++ b/boards/shields/mikroe_illuminance_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_illuminance_click + full_name: Illuminance Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_ir_gesture_click/Kconfig.shield b/boards/shields/mikroe_ir_gesture_click/Kconfig.shield new file mode 100644 index 0000000000000..beafc7b3f5c51 --- /dev/null +++ b/boards/shields/mikroe_ir_gesture_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_IR_GESTURE_CLICK + def_bool $(shields_list_contains,mikroe_ir_gesture_click) diff --git a/boards/shields/mikroe_ir_gesture_click/doc/images/mikroe_ir_gesture_click.webp b/boards/shields/mikroe_ir_gesture_click/doc/images/mikroe_ir_gesture_click.webp new file mode 100644 index 0000000000000..5bd5441c14cce Binary files /dev/null and b/boards/shields/mikroe_ir_gesture_click/doc/images/mikroe_ir_gesture_click.webp differ diff --git a/boards/shields/mikroe_ir_gesture_click/doc/index.rst b/boards/shields/mikroe_ir_gesture_click/doc/index.rst new file mode 100644 index 0000000000000..996e2a3236fcc --- /dev/null +++ b/boards/shields/mikroe_ir_gesture_click/doc/index.rst @@ -0,0 +1,53 @@ +.. _mikroe_ir_gesture_click_shield: + +MikroElektronika IR Gesture Click +================================= + +Overview +******** + +`IR Gesture Click`_ is a compact add-on board that enables contactless recognition, ambient light, +and proximity sensing capabilities. + +This board features the APDS-9960, a digital proximity, ambient light, RGB, and gesture sensor from +Avago Technologies. The sensor integrates an IR LED and four directional photodiodes that receive +the reflected light. An internal gesture engine deduces nearby objects' velocity, direction, and +distance (while canceling the ambient light). Various gestures can be implemented, from basic +directional swipes (up, down, left, or right) to more complex combinations. Since the chip can work +as a proximity sensor, the gesture engine can be configured to wake up automatically when a user's +hand approaches. This Click board™ makes the perfect solution for developing applications based on +gesture detection, color and ambient light sensing, mechanical +switch replacement, and more. + +.. figure:: images/mikroe_ir_gesture_click.webp + :align: center + :alt: IR Gesture Click + :height: 300px + + IR Gesture Click + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_ir_gesture_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/apds9960 + :board: mikroe_clicker_ra4m1 + :shield: mikroe_ir_gesture_click + :gen-args: -DCONFIG_APDS9960_TRIGGER_GLOBAL_THREAD=y + :goals: build + +References +********** + +- `IR Gesture Click`_ + +.. _IR Gesture Click: https://www.mikroe.com/ir-gesture-click diff --git a/boards/shields/mikroe_ir_gesture_click/mikroe_ir_gesture_click.overlay b/boards/shields/mikroe_ir_gesture_click/mikroe_ir_gesture_click.overlay new file mode 100644 index 0000000000000..e27caad984a1e --- /dev/null +++ b/boards/shields/mikroe_ir_gesture_click/mikroe_ir_gesture_click.overlay @@ -0,0 +1,14 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_i2c { + status = "okay"; + + apds9960_mikroe_ir_gesture_click: apds9960@39 { + compatible = "avago,apds9960"; + reg = <0x39>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/mikroe_ir_gesture_click/shield.yml b/boards/shields/mikroe_ir_gesture_click/shield.yml new file mode 100644 index 0000000000000..b5644c9130bc7 --- /dev/null +++ b/boards/shields/mikroe_ir_gesture_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_ir_gesture_click + full_name: IR Gesture Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_lsm6dsl_click/Kconfig.shield b/boards/shields/mikroe_lsm6dsl_click/Kconfig.shield new file mode 100644 index 0000000000000..5b36435784b80 --- /dev/null +++ b/boards/shields/mikroe_lsm6dsl_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_LSM6DSL_CLICK + def_bool $(shields_list_contains,mikroe_lsm6dsl_click) diff --git a/boards/shields/mikroe_lsm6dsl_click/doc/images/mikroe_lsm6dsl_click.webp b/boards/shields/mikroe_lsm6dsl_click/doc/images/mikroe_lsm6dsl_click.webp new file mode 100644 index 0000000000000..234b47052fd8d Binary files /dev/null and b/boards/shields/mikroe_lsm6dsl_click/doc/images/mikroe_lsm6dsl_click.webp differ diff --git a/boards/shields/mikroe_lsm6dsl_click/doc/index.rst b/boards/shields/mikroe_lsm6dsl_click/doc/index.rst new file mode 100644 index 0000000000000..c2284b53da67a --- /dev/null +++ b/boards/shields/mikroe_lsm6dsl_click/doc/index.rst @@ -0,0 +1,47 @@ +.. _mikroe_lsm6dsl_click_shield: + +MikroElektronika LSM6DSL Click +============================== + +Overview +******** + +`LSM6DSL Click`_ measures linear and angular velocity with six degrees of freedom. It carries the +LSM6DSL high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The click is +designed to run on a 3.3V power supply. `LSM6DSL Click`_ communicates with the target +micro-controller over SPI or I2C interface, with additional functionality provided by the INT pin on +the mikroBUS |trade| line. + +.. figure:: images/mikroe_lsm6dsl_click.webp + :align: center + :alt: LSM6DSL Click + :height: 300px + + LSM6DSL Click + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_spi`` node label for the mikroBUS |trade| SPI interface. See :ref:`shields` for more +details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_lsm6dsl_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/accel_trig + :board: mikroe_clicker_ra4m1 + :shield: mikroe_lsm6dsl_click + :goals: build + +References +********** + +- `LSM6DSL Click`_ +- `LSM6DSL Click schematic`_ + +.. _LSM6DSL Click: https://www.mikroe.com/lsm6dsl-click +.. _LSM6DSL Click schematic: https://download.mikroe.com/documents/add-on-boards/click/lsm6dsl/lsm6dsl-click-schematic-v100.pdf diff --git a/boards/shields/mikroe_lsm6dsl_click/mikroe_lsm6dsl_click.overlay b/boards/shields/mikroe_lsm6dsl_click/mikroe_lsm6dsl_click.overlay new file mode 100644 index 0000000000000..078ff38fcbf8f --- /dev/null +++ b/boards/shields/mikroe_lsm6dsl_click/mikroe_lsm6dsl_click.overlay @@ -0,0 +1,21 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + accel0 = &lsm6dsl_mikroe_lsm6dsl_click; + }; +}; + +&mikrobus_spi { + status = "okay"; + + lsm6dsl_mikroe_lsm6dsl_click: lsm6dsl@0 { + compatible = "st,lsm6dsl"; + reg = <0>; + spi-max-frequency = <1000000>; + irq-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/mikroe_lsm6dsl_click/shield.yml b/boards/shields/mikroe_lsm6dsl_click/shield.yml new file mode 100644 index 0000000000000..88b5aee161a0e --- /dev/null +++ b/boards/shields/mikroe_lsm6dsl_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_lsm6dsl_click + full_name: LSM6DSL Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_pressure_3_click/Kconfig.shield b/boards/shields/mikroe_pressure_3_click/Kconfig.shield new file mode 100644 index 0000000000000..543b1cad55365 --- /dev/null +++ b/boards/shields/mikroe_pressure_3_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_PRESSURE_3_CLICK + def_bool $(shields_list_contains,mikroe_pressure_3_click) diff --git a/boards/shields/mikroe_pressure_3_click/doc/images/mikroe_pressure_3_click.webp b/boards/shields/mikroe_pressure_3_click/doc/images/mikroe_pressure_3_click.webp new file mode 100644 index 0000000000000..47c98165ef5cb Binary files /dev/null and b/boards/shields/mikroe_pressure_3_click/doc/images/mikroe_pressure_3_click.webp differ diff --git a/boards/shields/mikroe_pressure_3_click/doc/index.rst b/boards/shields/mikroe_pressure_3_click/doc/index.rst new file mode 100644 index 0000000000000..591a6c63961c7 --- /dev/null +++ b/boards/shields/mikroe_pressure_3_click/doc/index.rst @@ -0,0 +1,50 @@ +.. _mikroe_pressure_3_click_shield: + +MikroElektronika Pressure 3 Click +================================= + +Overview +******** + +`Pressure 3 Click`_ is a compact add-on board that contains a board-mount pressure sensor. + +This board features the DPS310, a digital XENSIV |trade| barometric pressure sensor for portable +devices from Infineon. It is a fast sensor with a typical measurement time of 27.6ms for Standard +mode, down to 3.6ms in Low precision mode. The DPS310 has an operating range from 300 up to 1200hPa +with a relative accuracy of 0.06hPa and absolute accuracy of 1hPa. This Click board |trade| makes +the perfect solution for developing portable weather station applications, indoor navigation, drone +altitude control, and similar applications that rely on barometric pressure measurements. + +.. figure:: images/mikroe_pressure_3_click.webp + :align: center + :alt: Pressure 3 Click + :height: 300px + + Pressure 3 Click + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_pressure_3_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/pressure_polling + :board: mikroe_clicker_ra4m1 + :shield: mikroe_pressure_3_click + :goals: build + +References +********** + +- `Pressure 3 Click`_ +- `Pressure 3 Click schematic`_ + +.. _Pressure 3 Click: https://www.mikroe.com/pressure-3-click +.. _Pressure 3 Click schematic: https://download.mikroe.com/documents/add-on-boards/click/pressure-3/pressure-3-click-schematic-v100.pdf diff --git a/boards/shields/mikroe_pressure_3_click/mikroe_pressure_3_click.overlay b/boards/shields/mikroe_pressure_3_click/mikroe_pressure_3_click.overlay new file mode 100644 index 0000000000000..8d0e12c9c01b1 --- /dev/null +++ b/boards/shields/mikroe_pressure_3_click/mikroe_pressure_3_click.overlay @@ -0,0 +1,19 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + pressure-sensor = &dps310_mikroe_pressure_3_click; + }; +}; + +&mikrobus_i2c { + status = "okay"; + + dps310_mikroe_pressure_3_click: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + }; +}; diff --git a/boards/shields/mikroe_pressure_3_click/shield.yml b/boards/shields/mikroe_pressure_3_click/shield.yml new file mode 100644 index 0000000000000..5e30a648997d0 --- /dev/null +++ b/boards/shields/mikroe_pressure_3_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_pressure_3_click + full_name: Pressure 3 Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_proximity_9_click/Kconfig.shield b/boards/shields/mikroe_proximity_9_click/Kconfig.shield new file mode 100644 index 0000000000000..dd92fe8171fca --- /dev/null +++ b/boards/shields/mikroe_proximity_9_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_PROXIMITY_9_CLICK + def_bool $(shields_list_contains,mikroe_proximity_9_click) diff --git a/boards/shields/mikroe_proximity_9_click/doc/images/mikroe_proximity_9_click.webp b/boards/shields/mikroe_proximity_9_click/doc/images/mikroe_proximity_9_click.webp new file mode 100644 index 0000000000000..7dda88f761eb4 Binary files /dev/null and b/boards/shields/mikroe_proximity_9_click/doc/images/mikroe_proximity_9_click.webp differ diff --git a/boards/shields/mikroe_proximity_9_click/doc/index.rst b/boards/shields/mikroe_proximity_9_click/doc/index.rst new file mode 100644 index 0000000000000..effeb64193458 --- /dev/null +++ b/boards/shields/mikroe_proximity_9_click/doc/index.rst @@ -0,0 +1,54 @@ +.. _mikroe_proximity_9_click_shield: + +MikroElektronika Proximity 9 Click +================================== + +Overview +******** + +`Proximity 9 Click`_ is a very accurate and reliable proximity sensing (PS) and ambient light +sensing (ALS) device, equipped with the VCNL4040, an integrated PS and ALS sensor which features the +Filtron™ technology + +The 940nm IRED emitter, along with the low noise analog front end, and the PS/ALS photo-sensitive +elements, is integrated on the VCNL4040 IC, ensuring very accurate and reliable measurements. The +proprietary Filtron |trade| technology provides response near to the human eye spectral response, +providing the background light cancellation. The programmable interrupt engine allows for the +development of an optimized firmware, reducing the MCU workload and power consumption. + +.. figure:: images/mikroe_proximity_9_click.webp + :align: center + :alt: Proximity 9 Click + :height: 300px + + Proximity 9 Click + +Requirements +************ + +This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a +``mikrobus_i2c`` node label for the mikroBUS |trade| I2C interface. See :ref:`shields` for more +details. + +Programming +*********** + +Set ``-DSHIELD=mikroe_proximity_9_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/proximity_polling + :board: mikroe_clicker_ra4m1 + :shield: mikroe_proximity_9_click + :goals: build + +See :dtcompatible:`vishay,vcnl4040` for documentation on the additional binding properties available +for the VCNL4040 sensor. + +References +********** + +- `Proximity 9 Click`_ +- `Proximity 9 Click schematic`_ + +.. _Proximity 9 Click: https://www.mikroe.com/proximity-9-click +.. _Proximity 9 Click schematic: https://download.mikroe.com/documents/add-on-boards/click/proximity-9/proximity-9-click-schematic-v100.pdf diff --git a/boards/shields/mikroe_proximity_9_click/mikroe_proximity_9_click.overlay b/boards/shields/mikroe_proximity_9_click/mikroe_proximity_9_click.overlay new file mode 100644 index 0000000000000..3db48e18f8489 --- /dev/null +++ b/boards/shields/mikroe_proximity_9_click/mikroe_proximity_9_click.overlay @@ -0,0 +1,20 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + prox-sensor0 = &vcnl4040_mikroe_proximity_9_click; + }; +}; + +&mikrobus_i2c { + status = "okay"; + + vcnl4040_mikroe_proximity_9_click: vcnl4040@60 { + compatible = "vishay,vcnl4040"; + reg = <0x60>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/mikroe_proximity_9_click/shield.yml b/boards/shields/mikroe_proximity_9_click/shield.yml new file mode 100644 index 0000000000000..2029465261806 --- /dev/null +++ b/boards/shields/mikroe_proximity_9_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_proximity_9_click + full_name: Proximity 9 Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/npm1100_ek/npm1100_ek.overlay b/boards/shields/npm1100_ek/npm1100_ek.overlay index dbdbcef703aff..76b2eecee1a86 100644 --- a/boards/shields/npm1100_ek/npm1100_ek.overlay +++ b/boards/shields/npm1100_ek/npm1100_ek.overlay @@ -3,14 +3,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { npm1100_ek_pmic: pmic { compatible = "nordic,npm1100"; - nordic,iset-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; /* D2 */ + nordic,iset-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_HIGH>; npm1100_ek_buck: BUCK { - nordic,mode-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; /* D3 */ + nordic,mode-gpios = <&arduino_header ARDUINO_HEADER_R3_D3 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/boards/shields/nrf7002ek/nrf7002ek_coex.overlay b/boards/shields/nrf7002ek/nrf7002ek_coex.overlay index 60ff3ca6ea42f..09e5ca3fd86d8 100644 --- a/boards/shields/nrf7002ek/nrf7002ek_coex.overlay +++ b/boards/shields/nrf7002ek/nrf7002ek_coex.overlay @@ -4,18 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ + #include + / { nrf_radio_coex: coex { compatible = "nordic,nrf7002-coex"; status = "okay"; - /* D2 */ - status0-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; - /* D3 */ - req-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; - /* D4 */ - grant-gpios = <&arduino_header 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; - /* D6 */ - swctrl1-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; + status0-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_HIGH>; + req-gpios = <&arduino_header ARDUINO_HEADER_R3_D3 GPIO_ACTIVE_HIGH>; + grant-gpios = <&arduino_header ARDUINO_HEADER_R3_D4 + (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; + swctrl1-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/nrf7002ek/nrf7002ek_common.dtsi b/boards/shields/nrf7002ek/nrf7002ek_common.dtsi index c9bbbde4b9269..a8fbb844dd071 100644 --- a/boards/shields/nrf7002ek/nrf7002ek_common.dtsi +++ b/boards/shields/nrf7002ek/nrf7002ek_common.dtsi @@ -6,16 +6,14 @@ /* Common assignments for any nRF70 shield */ -/* D0 */ -iovdd-ctrl-gpios = <&arduino_header 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; -/* D1 */ -bucken-gpios = <&arduino_header 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; -/* D7 */ -host-irq-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; +#include + +iovdd-ctrl-gpios = <&arduino_header ARDUINO_HEADER_R3_D0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; +bucken-gpios = <&arduino_header ARDUINO_HEADER_R3_D1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; +host-irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; /* Short-range (SR) co-existence */ -/* D8 */ -srrf-switch-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; +srrf-switch-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_HIGH>; /* Maximum TX power limits for 2.4 GHz */ wifi-max-tx-pwr-2g-dsss = <21>; diff --git a/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_spi.overlay b/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_spi.overlay index 1d8dc34dededc..ad93f2e4d8ba3 100644 --- a/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_spi.overlay +++ b/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_spi.overlay @@ -8,6 +8,8 @@ * Overlay to enable support for OpenThread's RCP over SPI communication */ +#include + / { chosen { zephyr,hdlc-rcp-if = &hdlc_rcp_if; @@ -23,7 +25,7 @@ reg = <0>; spi-max-frequency = <1000000>; /* 1 MHz to support most devices */ - int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; }; }; diff --git a/boards/shields/reyax_lora/reyax_lora.overlay b/boards/shields/reyax_lora/reyax_lora.overlay index 080d78d92d0dd..7eb5a1e21b05e 100644 --- a/boards/shields/reyax_lora/reyax_lora.overlay +++ b/boards/shields/reyax_lora/reyax_lora.overlay @@ -4,6 +4,7 @@ */ #include +#include /{ aliases { @@ -18,6 +19,6 @@ rylr_lora_modem: rylr_lora_modem { compatible = "reyax,rylrxxx"; status = "okay"; - reset-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; }; }; diff --git a/boards/shields/rk055hdmipi4m/doc/index.rst b/boards/shields/rk055hdmipi4m/doc/index.rst index 17bf9ea4a34ad..852617d1c7cf3 100644 --- a/boards/shields/rk055hdmipi4m/doc/index.rst +++ b/boards/shields/rk055hdmipi4m/doc/index.rst @@ -55,7 +55,7 @@ example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: mixmrt1170_evk_cm7 + :board: mimxrt1170_evk//cm7 :shield: rk055hdmipi4m :goals: build diff --git a/boards/shields/rk055hdmipi4ma0/doc/index.rst b/boards/shields/rk055hdmipi4ma0/doc/index.rst index d34e4bfa80b94..8c809d285522a 100644 --- a/boards/shields/rk055hdmipi4ma0/doc/index.rst +++ b/boards/shields/rk055hdmipi4ma0/doc/index.rst @@ -55,7 +55,7 @@ example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: mixmrt1170_evk_cm7 + :board: mimxrt1170_evk//cm7 :shield: rk055hdmipi4ma0 :goals: build diff --git a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst index 06aa96c6add86..36a6ae0ee9f82 100644 --- a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst +++ b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst @@ -11,7 +11,7 @@ the Raspberry Pi Pico to the Arduino UNO form factor This board is designed to be use with FlexyPin connector pins. The FlexyPin holds Pico and contacts to castellated through-hole. -With simple soldering, it can also be used as a board to convert the Rapsberry Pi Pico +With simple soldering, it can also be used as a board to convert the Raspberry Pi Pico to the Arduino UNO form factor. .. image:: img/rpi_pico_uno_flexypin.png diff --git a/boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay b/boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay index 3ddf287288306..013e4d28ead04 100644 --- a/boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay +++ b/boards/shields/rpi_pico_uno_flexypin/rpi_pico_uno_flexypin.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; @@ -11,28 +13,28 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = - <0 0 &pico_header 26 0>, /* A0 */ - <1 0 &pico_header 27 0>, /* A1 */ - <2 0 &pico_header 28 0>, /* A2 */ - <3 0 &pico_header 13 0>, /* A3 */ - <4 0 &pico_header 14 0>, /* A4 */ - <5 0 &pico_header 15 0>, /* A5 */ - <6 0 &pico_header 1 0>, /* D0 */ - <7 0 &pico_header 0 0>, /* D1 */ - <8 0 &pico_header 4 0>, /* D2 */ - <9 0 &pico_header 5 0>, /* D3 */ - <10 0 &pico_header 6 0>, /* D4 */ - <11 0 &pico_header 7 0>, /* D5 */ - <12 0 &pico_header 8 0>, /* D6 */ - <13 0 &pico_header 9 0>, /* D7 */ - <14 0 &pico_header 2 0>, /* D8 */ - <15 0 &pico_header 3 0>, /* D9 */ - <16 0 &pico_header 17 0>, /* D10 */ - <17 0 &pico_header 19 0>, /* D11 */ - <18 0 &pico_header 16 0>, /* D12 */ - <19 0 &pico_header 18 0>, /* D13 */ - <20 0 &pico_header 20 0>, /* D14 */ - <21 0 &pico_header 21 0>; /* D15 */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/shields/rtk0eg0019b01002bj/Kconfig.defconfig b/boards/shields/rtk0eg0019b01002bj/Kconfig.defconfig new file mode 100644 index 0000000000000..2da067cd79a92 --- /dev/null +++ b/boards/shields/rtk0eg0019b01002bj/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if INPUT_RENESAS_RA_CTSU + +config INPUT_RENESAS_RA_CTSU_NUM_SELF_ELEMENTS + default 12 + depends on !INPUT_RENESAS_RA_QE_TOUCH_CFG + +endif # INPUT_RENESAS_RA_CTSU diff --git a/boards/shields/rtk0eg0019b01002bj/Kconfig.shield b/boards/shields/rtk0eg0019b01002bj/Kconfig.shield new file mode 100644 index 0000000000000..7d5e30c1e4245 --- /dev/null +++ b/boards/shields/rtk0eg0019b01002bj/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_RTK0EG0019B01002BJ + def_bool $(shields_list_contains,rtk0eg0019b01002bj) diff --git a/boards/shields/rtk0eg0019b01002bj/boards/rssk_ra2l1.conf b/boards/shields/rtk0eg0019b01002bj/boards/rssk_ra2l1.conf new file mode 100644 index 0000000000000..e4cd90fa23eb0 --- /dev/null +++ b/boards/shields/rtk0eg0019b01002bj/boards/rssk_ra2l1.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_INPUT_RENESAS_RA_DEVICE_VCC=5000 diff --git a/boards/shields/rtk0eg0019b01002bj/boards/rssk_ra2l1.overlay b/boards/shields/rtk0eg0019b01002bj/boards/rssk_ra2l1.overlay new file mode 100644 index 0000000000000..f33505d135e15 --- /dev/null +++ b/boards/shields/rtk0eg0019b01002bj/boards/rssk_ra2l1.overlay @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&rtk0eg0019b01002bj_ctsu { + clock-div = <1>; + pwr-supply-sel = "internal-power"; + pwr-supply-sel2 = "pwr-supply-sel"; + atune1 = "normal"; + atune12 = <40>; + measure-mode = "self-multi-scan"; + po-sel = "same-pulse"; + status = "okay"; + + group1 { + ssdiv = "4.00", "4.00", "4.00"; + so = <0x03B>, <0x059>, <0x049>; + snum = <0x07>, <0x07>, <0x07>; + sdpa = <0x0F>, <0x0F>, <0x0F>; + num-moving-avg = <4>; + on-freq = <3>; + off-freq = <3>; + drift-freq = <255>; + cancel-freq = <0>; + status = "okay"; + + button1 { + threshold = <769>; + hysteresis = <38>; + status = "okay"; + }; + + button2 { + threshold = <740>; + hysteresis = <37>; + status = "okay"; + }; + + button3 { + threshold = <784>; + hysteresis = <39>; + status = "okay"; + }; + }; + + group2 { + ssdiv = "4.00", "4.00", "4.00", "4.00", "4.00"; + so = <0x02B>, <0x03B>, <0x036>, <0x03B>, <0x03A>; + snum = <0x07>, <0x07>, <0x07>, <0x07>, <0x07>; + sdpa = <0x0F>, <0x0F>, <0x0F>, <0x0F>, <0x0F>; + num-moving-avg = <4>; + on-freq = <3>; + off-freq = <3>; + drift-freq = <255>; + cancel-freq = <0>; + status = "okay"; + + slider { + threshold = <573>; + status = "okay"; + }; + }; + + group3 { + ssdiv = "4.00", "4.00", "4.00", "4.00"; + so = <0x047>, <0x046>, <0x049>, <0x040>; + snum = <0x07>, <0x07>, <0x07>, <0x07>; + sdpa = <0x0F>, <0x0F>, <0x0F>, <0x0F>; + num-moving-avg = <4>; + on-freq = <3>; + off-freq = <3>; + drift-freq = <255>; + cancel-freq = <0>; + status = "okay"; + + wheel { + threshold = <711>; + status = "okay"; + }; + }; +}; diff --git a/boards/shields/rtk0eg0019b01002bj/doc/img/rtk0eg0019b01002bj.webp b/boards/shields/rtk0eg0019b01002bj/doc/img/rtk0eg0019b01002bj.webp new file mode 100644 index 0000000000000..371248495a84e Binary files /dev/null and b/boards/shields/rtk0eg0019b01002bj/doc/img/rtk0eg0019b01002bj.webp differ diff --git a/boards/shields/rtk0eg0019b01002bj/doc/index.rst b/boards/shields/rtk0eg0019b01002bj/doc/index.rst new file mode 100644 index 0000000000000..83fa5d1b73910 --- /dev/null +++ b/boards/shields/rtk0eg0019b01002bj/doc/index.rst @@ -0,0 +1,110 @@ +.. _rtk0eg0019b01002bj: + +RTK0EG0019B01002BJ Capacitive Touch Application Shield +###################################################### + +Overview +******** + +The RTK0EG0019B01002BJ Capacitive Touch Application Shield is designed to work with the Renesas +Capacitive Touch Evaluation Kit. + +The shield features a variety of touch sensors, including buttons, sliders, and wheels, making it +an ideal platform for developing touch-based applications. + +.. figure:: img/rtk0eg0019b01002bj.webp + :width: 300 + :align: center + + RTK0EG0019B01002BJ Capacitive Touch Application Shield (Credit: Renesas Electronics Corporation) + +Pins Assignment of the RTK0EG0019B01002BJ Shield +================================================ + +Application Header 1 (CN1) +-------------------------- + ++---------+-------------+---------+-------------+ +| CN1 Pin | Function | CN1 Pin | Function | ++=========+=============+=========+=============+ +| 15 | VCC | 16 | GND | ++---------+-------------+---------+-------------+ +| 13 | LED_ROW0 | 14 | LED_ROW1 | ++---------+-------------+---------+-------------+ +| 11 | LED_ROW2 | 12 | LED_ROW3 | ++---------+-------------+---------+-------------+ +| 9 | N/C | 10 | N/C | ++---------+-------------+---------+-------------+ +| 7 | LED_COL3 | 8 | N/C | ++---------+-------------+---------+-------------+ +| 5 | LED_COL1 | 6 | LED_COL2 | ++---------+-------------+---------+-------------+ +| 3 | N/C | 4 | LED_COL0 | ++---------+-------------+---------+-------------+ +| 1 | N/C | 2 | N/C | ++---------+-------------+---------+-------------+ + +Application Header 2 (CN2) +-------------------------- + ++---------+-------------------+---------+-------------------+ +| CN2 Pin | Touch Electrode | CN2 Pin | Touch Electrode | ++=========+===================+=========+===================+ +| 39 | N/C | 40 | TSCAP | ++---------+-------------------+---------+-------------------+ +| 37 | N/C | 38 | N/C | ++---------+-------------------+---------+-------------------+ +| 35 | N/C | 36 | TS-W1 | ++---------+-------------------+---------+-------------------+ +| 33 | N/C | 34 | TS-W2 | ++---------+-------------------+---------+-------------------+ +| 31 | TS-W3 | 32 | N/C | ++---------+-------------------+---------+-------------------+ +| 29 | N/C | 30 | N/C | ++---------+-------------------+---------+-------------------+ +| 27 | N/C | 28 | TS-W4 | ++---------+-------------------+---------+-------------------+ +| 25 | N/C | 26 | N/C | ++---------+-------------------+---------+-------------------+ +| 23 | N/C | 24 | N/C | ++---------+-------------------+---------+-------------------+ +| 21 | N/C | 22 | SHIELD-W1 | ++---------+-------------------+---------+-------------------+ +| 19 | N/C | 20 | N/C | ++---------+-------------------+---------+-------------------+ +| 17 | N/C | 18 | N/C | ++---------+-------------------+---------+-------------------+ +| 15 | N/C | 16 | N/C | ++---------+-------------------+---------+-------------------+ +| 13 | N/C | 14 | N/C | ++---------+-------------------+---------+-------------------+ +| 11 | N/C | 12 | N/C | ++---------+-------------------+---------+-------------------+ +| 9 | TS-B1 | 10 | TS-B2 | ++---------+-------------------+---------+-------------------+ +| 7 | SHIELD-B1 | 8 | TS-B3 | ++---------+-------------------+---------+-------------------+ +| 5 | TS-S1 | 6 | SHIELD-S1 | ++---------+-------------------+---------+-------------------+ +| 3 | TS-S3 | 4 | TS-S2 | ++---------+-------------------+---------+-------------------+ +| 1 | TS-S5 | 2 | TS-S4 | ++---------+-------------------+---------+-------------------+ + +Programming +*********** + +Set ``--shield rtk0eg0019b01002bj`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/shields/rtk0eg0019b01002bj + :board: rssk_ra2l1 + :shield: rtk0eg0019b01002bj + :goals: build + +References +********** +- `Capacitive Touch Evaluation System for RA2L1`_ + +.. _Capacitive Touch Evaluation System for RA2L1: + https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0eg0022s01001bj-capacitive-touch-evaluation-system-ra2l1 diff --git a/boards/shields/rtk0eg0019b01002bj/rtk0eg0019b01002bj.overlay b/boards/shields/rtk0eg0019b01002bj/rtk0eg0019b01002bj.overlay new file mode 100644 index 0000000000000..3bdf0c34b5f60 --- /dev/null +++ b/boards/shields/rtk0eg0019b01002bj/rtk0eg0019b01002bj.overlay @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + rtk0eg0019b01002bj_cn1: rtk0eg0019b01002bj-cn1 { + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + }; + + zephyr,user { + rtk0eg0019b01002bj-led-row-gpios = + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_ROW0 GPIO_ACTIVE_LOW>, + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_ROW1 GPIO_ACTIVE_LOW>, + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_ROW2 GPIO_ACTIVE_LOW>, + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_ROW3 GPIO_ACTIVE_LOW>; + rtk0eg0019b01002bj-led-col-gpios = + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_COL0 GPIO_ACTIVE_HIGH>, + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_COL1 GPIO_ACTIVE_HIGH>, + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_COL2 GPIO_ACTIVE_HIGH>, + <&rtk0eg0019b01002bj_cn1 RTK0EG0019B01002BJ_CN1_LED_COL3 GPIO_ACTIVE_HIGH>; + }; +}; + +&rtk0eg0019b01002bj_ctsu { + status = "okay"; + + group1 { + ctsuchac = <0x01 0x0E 0x00 0x00 0x00>; + ctsuchtrc = <0x01 0x00 0x00 0x00 0x00>; + rx-count = <3>; + tx-count = <0>; + status = "okay"; + + rtk0eg0019b01002bj_bt1: button1 { + compatible = "renesas,ra-ctsu-button"; + elements = <2>; + event-code = ; + status = "okay"; + }; + + rtk0eg0019b01002bj_bt2: button2 { + compatible = "renesas,ra-ctsu-button"; + elements = <1>; + event-code = ; + status = "okay"; + }; + + rtk0eg0019b01002bj_bt3: button3 { + compatible = "renesas,ra-ctsu-button"; + elements = <0>; + event-code = ; + status = "okay"; + }; + }; + + group2 { + ctsuchac = <0xF4 0x01 0x00 0x00 0x00>; + ctsuchtrc = <0x00 0x01 0x00 0x00 0x00>; + rx-count = <5>; + tx-count = <0>; + status = "okay"; + + rtk0eg0019b01002bj_slider: slider { + compatible = "renesas,ra-ctsu-slider"; + elements = <1>, <0>, <2>, <4>, <3>; + threshold = <703>; + event-code = ; + status = "okay"; + }; + }; + + group3 { + ctsuchac = <0x00 0x40 0xA4 0x00 0x01>; + ctsuchtrc = <0x00 0x40 0x00 0x00 0x00>; + rx-count = <4>; + tx-count = <0>; + status = "okay"; + + rtk0eg0019b01002bj_wheel: wheel { + compatible = "renesas,ra-ctsu-wheel"; + elements = <0>, <1>, <2>, <3>; + event-code = ; + status = "okay"; + }; + }; +}; diff --git a/boards/shields/rtk0eg0019b01002bj/shield.yml b/boards/shields/rtk0eg0019b01002bj/shield.yml new file mode 100644 index 0000000000000..fe1b02b9ed3a9 --- /dev/null +++ b/boards/shields/rtk0eg0019b01002bj/shield.yml @@ -0,0 +1,7 @@ +shield: + name: rtk0eg0019b01002bj + full_name: RTK0EG0019B01002BJ Capacitive Touch Application Shield + vendor: renesas + supported_features: + - input + - gpio diff --git a/boards/shields/seeed_w5500/seeed_w5500.overlay b/boards/shields/seeed_w5500/seeed_w5500.overlay index 9551c0f0e3ae7..69de57582b984 100644 --- a/boards/shields/seeed_w5500/seeed_w5500.overlay +++ b/boards/shields/seeed_w5500/seeed_w5500.overlay @@ -3,6 +3,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; @@ -10,6 +12,6 @@ compatible = "wiznet,w5500"; reg = <0x0>; spi-max-frequency = ; - int-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */ + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_LOW>; }; }; diff --git a/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay b/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay index 553d296e5aade..d7dea3f076c5b 100644 --- a/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay +++ b/boards/shields/semtech_sx1262mb2das/semtech_sx1262mb2das.overlay @@ -3,6 +3,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { lora0 = &lora_semtech_sx1262mb2das; @@ -12,17 +14,17 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; lora_semtech_sx1262mb2das: sx1262@0 { compatible = "semtech,sx1262"; reg = <0>; spi-max-frequency = ; label = "SX1262"; - reset-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; - busy-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; - antenna-enable-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; - dio1-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 GPIO_ACTIVE_LOW>; + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D3 GPIO_ACTIVE_HIGH>; + antenna-enable-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_HIGH>; + dio1-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; dio2-tx-enable; tcxo-power-startup-delay-ms = <5>; }; diff --git a/boards/shields/semtech_sx1272mb2das/semtech_sx1272mb2das.overlay b/boards/shields/semtech_sx1272mb2das/semtech_sx1272mb2das.overlay index a2ed429c79ebc..3c17e7e42505e 100644 --- a/boards/shields/semtech_sx1272mb2das/semtech_sx1272mb2das.overlay +++ b/boards/shields/semtech_sx1272mb2das/semtech_sx1272mb2das.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { lora0 = &lora_semtech_sx1272mb2das; @@ -13,19 +15,23 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; lora_semtech_sx1272mb2das: lora@0 { compatible = "semtech,sx1272"; reg = <0x0>; spi-max-frequency = <3000000>; - reset-gpios = <&arduino_header 0 GPIO_ACTIVE_HIGH>; /* A0 */ + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 GPIO_ACTIVE_HIGH>; - dio-gpios = <&arduino_header 8 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 is D2 */ - <&arduino_header 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO1 is D3 */ - <&arduino_header 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO2 is D4 */ - <&arduino_header 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO3 is D5 */ + dio-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D3 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D4 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D5 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; power-amplifier-output = "rfo"; }; diff --git a/boards/shields/semtech_sx1276mb1mas/semtech_sx1276mb1mas.overlay b/boards/shields/semtech_sx1276mb1mas/semtech_sx1276mb1mas.overlay index 230531d5559e2..e915c70a1928d 100644 --- a/boards/shields/semtech_sx1276mb1mas/semtech_sx1276mb1mas.overlay +++ b/boards/shields/semtech_sx1276mb1mas/semtech_sx1276mb1mas.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { lora0 = &lora_semtech_sx1276mb1mas; @@ -13,22 +15,28 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; lora_semtech_sx1276mb1mas: lora@0 { compatible = "semtech,sx1276"; reg = <0x0>; spi-max-frequency = ; - reset-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; /* A0 */ + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 GPIO_ACTIVE_LOW>; - dio-gpios = <&arduino_header 8 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 is D2 */ - <&arduino_header 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO1 is D3 */ - <&arduino_header 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO2 is D4 */ - <&arduino_header 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO3 is D5 */ - <&arduino_header 14 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO4 is D8 */ - <&arduino_header 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO5 is D9 */ + dio-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D3 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D4 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D5 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D8 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + <&arduino_header ARDUINO_HEADER_R3_D9 + (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; - rfo-enable-gpios = <&arduino_header 4 GPIO_ACTIVE_HIGH>; /* RXTX_EXT is A4 */ + rfo-enable-gpios = <&arduino_header ARDUINO_HEADER_R3_A4 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/sparkfun_environmental_combo/Kconfig.shield b/boards/shields/sparkfun_environmental_combo/Kconfig.shield new file mode 100644 index 0000000000000..31f7d66c98fdc --- /dev/null +++ b/boards/shields/sparkfun_environmental_combo/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_SPARKFUN_ENVIRONMENTAL_COMBO + def_bool $(shields_list_contains,sparkfun_environmental_combo) diff --git a/boards/shields/sparkfun_environmental_combo/doc/index.rst b/boards/shields/sparkfun_environmental_combo/doc/index.rst new file mode 100644 index 0000000000000..d5e6adb3207b6 --- /dev/null +++ b/boards/shields/sparkfun_environmental_combo/doc/index.rst @@ -0,0 +1,77 @@ +.. _sparkfun_environmental_combo: + +Sparkfun Environmental Combo Shield with ENS160 and BME280 +########################################################## + +Overview +******** + +The `Sparkfun Environmental Combo Shield`_ features +a `ScioSense ENS160 Digital Metal Oxide Multi-Gas Sensor`_, +a `Bosch BME280 Humidity Sensor`_ and two Qwiic connectors. +It measures temperature, humidity, pressure, CO2 and +VOC (volatile organic compounds). + +.. figure:: sparkfun_environmental_combo.webp + :align: center + :alt: Sparkfun Environmental Combo Shield + + Sparkfun Environmental Combo Shield (Credit: Sparkfun) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+---------------------------+ +| Shield Pin | Function | ++==============+===========================+ +| SDA | ENS160 and BME280 I2C SDA | ++--------------+---------------------------+ +| SCL | ENS160 and BME280 I2C SCL | ++--------------+---------------------------+ +| INT | ENS160 interrupt output | ++--------------+---------------------------+ + +To use the interrupt output from the ENS160, you need to connect a wire from +the shield INT output to a suitable GPIO on your microcontroller board, and to +modify the devicetree settings. See :dtcompatible:`sciosense,ens160` for options. + +See also :dtcompatible:`bosch,bme280` for the BME280 sensor. + +Programming +*********** + +Set ``--shield sparkfun_environmental_combo`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`bme280` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/bme280 + :board: adafruit_qt_py_rp2040 + :shield: sparkfun_environmental_combo + :goals: build + +You can also use the :zephyr:code-sample:`sensor_shell` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: adafruit_qt_py_rp2040 + :shield: sparkfun_environmental_combo + :goals: build + +.. _Sparkfun Environmental Combo Shield: + https://www.sparkfun.com/sparkfun-environmental-combo-breakout-ens160-bme280-qwiic.html + +.. _ScioSense ENS160 Digital Metal Oxide Multi-Gas Sensor: + https://www.sciosense.com/wp-content/uploads/2023/12/ENS160-Datasheet.pdf + +.. _Bosch BME280 Humidity Sensor: + https://www.bosch-sensortec.com/products/environmental-sensors/humidity-sensors-bme280/ diff --git a/boards/shields/sparkfun_environmental_combo/doc/sparkfun_environmental_combo.webp b/boards/shields/sparkfun_environmental_combo/doc/sparkfun_environmental_combo.webp new file mode 100644 index 0000000000000..f5f35e4adc2b3 Binary files /dev/null and b/boards/shields/sparkfun_environmental_combo/doc/sparkfun_environmental_combo.webp differ diff --git a/boards/shields/sparkfun_environmental_combo/shield.yml b/boards/shields/sparkfun_environmental_combo/shield.yml new file mode 100644 index 0000000000000..4f97e1130480e --- /dev/null +++ b/boards/shields/sparkfun_environmental_combo/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: sparkfun_environmental_combo + full_name: SparkFun Environmental Combo Breakout with ENS160 and BME280 + vendor: sparkfun + supported_features: + - sensor diff --git a/boards/shields/sparkfun_environmental_combo/sparkfun_environmental_combo.overlay b/boards/shields/sparkfun_environmental_combo/sparkfun_environmental_combo.overlay new file mode 100644 index 0000000000000..cc4eaf4973e84 --- /dev/null +++ b/boards/shields/sparkfun_environmental_combo/sparkfun_environmental_combo.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_i2c { + status = "okay"; + + sparkfun_ens160: ens160@53 { + status = "okay"; + compatible = "sciosense,ens160"; + reg = <0x53>; + }; + + sparkfun_bme280: bme280@77 { + status = "okay"; + compatible = "bosch,bme280"; + reg = <0x77>; + }; +}; diff --git a/boards/shields/sparkfun_rv8803/Kconfig.shield b/boards/shields/sparkfun_rv8803/Kconfig.shield new file mode 100644 index 0000000000000..0272ddcd3b336 --- /dev/null +++ b/boards/shields/sparkfun_rv8803/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_SPARKFUN_RV8803 + def_bool $(shields_list_contains,sparkfun_rv8803) diff --git a/boards/shields/sparkfun_rv8803/doc/index.rst b/boards/shields/sparkfun_rv8803/doc/index.rst new file mode 100644 index 0000000000000..4dfc9c997fb9a --- /dev/null +++ b/boards/shields/sparkfun_rv8803/doc/index.rst @@ -0,0 +1,69 @@ +.. _sparkfun_rv8803: + +Sparkfun RV8803 Shield +###################### + +Overview +******** + +The `SparkFun RV8803 Real Time Clock Shield`_ features +a `Micro Crystal RV-8803-C7 Real-Time-Clock`_ and two Qwiic connectors. +It has a 3 Volt back-up coin-cell battery. + +.. figure:: sparkfun_rv8803.webp + :align: center + :alt: Sparkfun RV8803 Shield + + Sparkfun RV8803 Shield (Credit: Sparkfun) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------------------------------------------------------------------------------------+ +| Shield Pin | Function | ++==============+=================================================================================================+ +| SDA | RV8803 I2C SDA. Also connected to the Qwiic connector. | ++--------------+-------------------------------------------------------------------------------------------------+ +| SCL | RV8803 I2C SCL. Also connected to the Qwiic connector. | ++--------------+-------------------------------------------------------------------------------------------------+ +| EVI | RV8803 event input. Active low by default, with external pull-up and on-shield button. | ++--------------+-------------------------------------------------------------------------------------------------+ +| INT | RV8803 interrupt output. Active low (open drain), with external pull-up. | ++--------------+-------------------------------------------------------------------------------------------------+ +| CLKOUT | RV8803 clock output. 32768, 1024 or 1 Hz (controlled by devicetree setting). Enabled by CLKOE. | ++--------------+-------------------------------------------------------------------------------------------------+ +| CLKOE | RV8803 control of CLKOUT, which is enabled when this pin is high. External pull-down on shield. | ++--------------+-------------------------------------------------------------------------------------------------+ + +To use the interrupt output from the RV-8803, you need to connect a wire from +the shield INT output to a suitable GPIO on your microcontroller board, and to +modify the devicetree settings. See :dtcompatible:`microcrystal,rv8803` for options. + + +Programming +*********** + +Set ``--shield sparkfun_rv8803`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`rtc` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/rtc + :board: adafruit_qt_py_rp2040 + :shield: sparkfun_rv8803 + :goals: build + +.. _SparkFun RV8803 Real Time Clock Shield: + https://www.sparkfun.com/sparkfun-real-time-clock-module-rv-8803-qwiic.html + +.. _Micro Crystal RV-8803-C7 Real-Time-Clock: + https://www.microcrystal.com/en/products/real-time-clock-rtc-modules/rv-8803-c7 diff --git a/boards/shields/sparkfun_rv8803/doc/sparkfun_rv8803.webp b/boards/shields/sparkfun_rv8803/doc/sparkfun_rv8803.webp new file mode 100644 index 0000000000000..0a6aba315fc9c Binary files /dev/null and b/boards/shields/sparkfun_rv8803/doc/sparkfun_rv8803.webp differ diff --git a/boards/shields/sparkfun_rv8803/shield.yml b/boards/shields/sparkfun_rv8803/shield.yml new file mode 100644 index 0000000000000..3a9bfa0d79a19 --- /dev/null +++ b/boards/shields/sparkfun_rv8803/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: sparkfun_rv8803 + full_name: Sparkfun RV8803 Real Time Clock Shield + vendor: sparkfun + supported_features: + - rtc diff --git a/boards/shields/sparkfun_rv8803/sparkfun_rv8803.overlay b/boards/shields/sparkfun_rv8803/sparkfun_rv8803.overlay new file mode 100644 index 0000000000000..8867aacbac45c --- /dev/null +++ b/boards/shields/sparkfun_rv8803/sparkfun_rv8803.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + rtc = &sparkfun_rv8803; + }; +}; + +&zephyr_i2c { + status = "okay"; + + sparkfun_rv8803: rv8803@32 { + status = "okay"; + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; +}; diff --git a/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay b/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay index bea2b37c4f4c7..6da769e26018c 100644 --- a/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay +++ b/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay @@ -4,14 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_serial { current-speed = <115200>; status = "okay"; sara_r4 { compatible = "u-blox,sara-r4"; - mdm-power-gpios = <&arduino_header 11 0>; /* D5 */ - mdm-reset-gpios = <&arduino_header 12 0>; /* D6 */ + mdm-power-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; + mdm-reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/boards/shields/sparkfun_shtc3/Kconfig.shield b/boards/shields/sparkfun_shtc3/Kconfig.shield new file mode 100644 index 0000000000000..6d0149f942c3a --- /dev/null +++ b/boards/shields/sparkfun_shtc3/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jonas Berg +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_SPARKFUN_SHTC3 + def_bool $(shields_list_contains,sparkfun_shtc3) diff --git a/boards/shields/sparkfun_shtc3/doc/index.rst b/boards/shields/sparkfun_shtc3/doc/index.rst new file mode 100644 index 0000000000000..50f6386874768 --- /dev/null +++ b/boards/shields/sparkfun_shtc3/doc/index.rst @@ -0,0 +1,60 @@ +.. _sparkfun_shtc3: + +Sparkfun SHTC3 Shield +##################### + +Overview +******** + +The `Sparkfun SHTC3 Temperature and Humidity Sensor Shield`_ features +a `Sensirion SHTC3 Humidity and Temperature Sensor`_ and two Qwiic connectors. +It measures temperature and humidity. + +.. figure:: sparkfun_shtc3.webp + :align: center + :alt: Sparkfun SHTC3 Shield + + Sparkfun SHTC3 Shield (Credit: Sparkfun) + + +Requirements +************ + +This shield can be used with boards which provide an I2C connector, for +example STEMMA QT or Qwiic connectors. +The target board must define a ``zephyr_i2c`` node label. +See :ref:`shields` for more details. + + +Pin Assignments +=============== + ++--------------+-------------------+ +| Shield Pin | Function | ++==============+===================+ +| SDA | SHTC3 I2C SDA | ++--------------+-------------------+ +| SCL | SHTC3 I2C SCL | ++--------------+-------------------+ + +See :dtcompatible:`sensirion,shtcx` for documentation on how to adjust the +devicetree file, if necessary. + + +Programming +*********** + +Set ``--shield sparkfun_shtc3`` when you invoke ``west build``. For example +when running the :zephyr:code-sample:`dht_polling` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/dht_polling + :board: adafruit_qt_py_rp2040 + :shield: sparkfun_shtc3 + :goals: build + +.. _Sparkfun SHTC3 Temperature and Humidity Sensor Shield: + https://www.sparkfun.com/sparkfun-humidity-sensor-breakout-shtc3-qwiic.html + +.. _Sensirion SHTC3 Humidity and Temperature Sensor: + https://sensirion.com/products/catalog/SHTC3 diff --git a/boards/shields/sparkfun_shtc3/doc/sparkfun_shtc3.webp b/boards/shields/sparkfun_shtc3/doc/sparkfun_shtc3.webp new file mode 100644 index 0000000000000..bb675cbebd9f1 Binary files /dev/null and b/boards/shields/sparkfun_shtc3/doc/sparkfun_shtc3.webp differ diff --git a/boards/shields/sparkfun_shtc3/shield.yml b/boards/shields/sparkfun_shtc3/shield.yml new file mode 100644 index 0000000000000..ddb2b4bddf1e2 --- /dev/null +++ b/boards/shields/sparkfun_shtc3/shield.yml @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025, Jonas Berg + +shield: + name: sparkfun_shtc3 + full_name: Sparkfun SHTC3 Temperature and Humidity Sensor Shield + vendor: sparkfun + supported_features: + - sensor diff --git a/boards/shields/sparkfun_shtc3/sparkfun_shtc3.overlay b/boards/shields/sparkfun_shtc3/sparkfun_shtc3.overlay new file mode 100644 index 0000000000000..27527215bbc91 --- /dev/null +++ b/boards/shields/sparkfun_shtc3/sparkfun_shtc3.overlay @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Jonas Berg + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + dht0 = &sparkfun_shtc3; + }; +}; + +&zephyr_i2c { + status = "okay"; + + sparkfun_shtc3: shtc3@70 { + status = "okay"; + compatible = "sensirion,shtc3", "sensirion,shtcx"; + reg = <0x70>; + measure-mode = "normal"; + clock-stretching; + }; +}; diff --git a/boards/shields/ssd1306/ssd1306_128x64_spi.overlay b/boards/shields/ssd1306/ssd1306_128x64_spi.overlay index ad9301086f1a1..c9ee9e68563c5 100644 --- a/boards/shields/ssd1306/ssd1306_128x64_spi.overlay +++ b/boards/shields/ssd1306/ssd1306_128x64_spi.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,display = &ssd1306_ssd1306_128x64_spi; @@ -26,7 +28,7 @@ segment-remap; com-invdir; prechargep = <0x22>; - data-cmd-gpios = <&arduino_header 15 0>; - /* reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; */ + data-cmd-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 0>; + /* reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; */ }; }; diff --git a/boards/shields/st7735r/st7735r_ada_160x128.overlay b/boards/shields/st7735r/st7735r_ada_160x128.overlay index 1547c6fa28134..c72bb53d406fe 100644 --- a/boards/shields/st7735r/st7735r_ada_160x128.overlay +++ b/boards/shields/st7735r/st7735r_ada_160x128.overlay @@ -5,6 +5,7 @@ */ #include +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_st7735r_ada_160x128 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; @@ -47,5 +48,5 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; }; diff --git a/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay b/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay index 059f9d565b6dd..09f65e682343d 100644 --- a/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay +++ b/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include / { chosen { @@ -13,8 +14,8 @@ mipi_dbi_st7789v_tl019fqv01 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -49,5 +50,5 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; }; diff --git a/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay b/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay index e4128572b446d..bed545e1cc7ff 100644 --- a/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay +++ b/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay @@ -6,6 +6,7 @@ */ #include +#include / { chosen { @@ -15,8 +16,8 @@ mipi_dbi_st7789v_waveshare_240x240 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -51,5 +52,5 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; }; diff --git a/boards/shields/st_b_cams_imx_mb1854/st_b_cams_imx_mb1854.overlay b/boards/shields/st_b_cams_imx_mb1854/st_b_cams_imx_mb1854.overlay index cdf7185b70116..5399867bfc737 100644 --- a/boards/shields/st_b_cams_imx_mb1854/st_b_cams_imx_mb1854.overlay +++ b/boards/shields/st_b_cams_imx_mb1854/st_b_cams_imx_mb1854.overlay @@ -10,7 +10,7 @@ / { chosen { - zephyr,camera = &csi_capture_port; + zephyr,camera = &pipe_main; }; imx335_input_clock: imx335-input-clock { diff --git a/boards/shields/st_mb1897_cam/st_mb1897_cam.overlay b/boards/shields/st_mb1897_cam/st_mb1897_cam.overlay index 61dc9cedb0671..61a54ceade3e6 100644 --- a/boards/shields/st_mb1897_cam/st_mb1897_cam.overlay +++ b/boards/shields/st_mb1897_cam/st_mb1897_cam.overlay @@ -9,7 +9,7 @@ / { chosen { - zephyr,camera = &csi_capture_port; + zephyr,camera = &pipe_dump; }; }; diff --git a/boards/shields/tcan4550evm/tcan4550evm.overlay b/boards/shields/tcan4550evm/tcan4550evm.overlay index 7aeb3022a9a2d..eb8d770bfe316 100644 --- a/boards/shields/tcan4550evm/tcan4550evm.overlay +++ b/boards/shields/tcan4550evm/tcan4550evm.overlay @@ -5,6 +5,7 @@ */ #include +#include / { chosen { @@ -14,7 +15,7 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; tcan4x5x_tcan4550evm: can@0 { compatible = "ti,tcan4x5x"; @@ -23,10 +24,10 @@ spi-max-frequency = <2000000>; status = "okay"; clock-frequency = <40000000>; - device-state-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */ - device-wake-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */ - int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */ + device-state-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_HIGH>; + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>; bosch,mram-cfg = <0x0 15 15 7 7 0 10 10>; status = "okay"; diff --git a/boards/shields/ti_bp_bassensorsmkii/ti_bp_bassensorsmkii.overlay b/boards/shields/ti_bp_bassensorsmkii/ti_bp_bassensorsmkii.overlay index fa4f11bbc7405..1b843545e17a5 100644 --- a/boards/shields/ti_bp_bassensorsmkii/ti_bp_bassensorsmkii.overlay +++ b/boards/shields/ti_bp_bassensorsmkii/ti_bp_bassensorsmkii.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { accel0 = &bmi160_ti_bp_bassensorsmkii; @@ -16,7 +18,7 @@ bmi160_ti_bp_bassensorsmkii: bmi160@69 { compatible = "bosch,bmi160"; reg = <0x69>; - int-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; + int-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_HIGH>; }; opt3001_ti_bp_bassensorsmkii: opt3001@44 { diff --git a/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi b/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi index 80480cf5787f8..0b3b9d6bbedc4 100644 --- a/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi +++ b/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi @@ -4,10 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>, /* D10 */ - <&arduino_header 12 GPIO_ACTIVE_LOW>; /* D04 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>, + <&arduino_header ARDUINO_HEADER_R3_D4 GPIO_ACTIVE_LOW>; waveshare_epaper_sdhc: sdhc@1 { compatible = "zephyr,sdhc-spi-slot"; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay index 6a877a0b08d2c..a1274fd8efbf5 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0154a07.overlay @@ -5,6 +5,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_waveshare_epaper_gdeh0154a07 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; @@ -25,7 +26,7 @@ reg = <0>; width = <200>; height = <200>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; tssv = <0x80>; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay index 1936b48d16a78..6c5e9992c96a7 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b1.overlay @@ -5,6 +5,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_waveshare_epaper_gdeh0213b1 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; @@ -25,7 +26,7 @@ reg = <0>; width = <250>; height = <120>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; full { gdv = [10 0a]; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay index 362e0905079c8..d6a9cca34983e 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh0213b72.overlay @@ -5,6 +5,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_waveshare_epaper_gdeh0213b72 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; @@ -25,7 +26,7 @@ reg = <0>; width = <250>; height = <120>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; full { gdv = [15]; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay index 734786fcc80be..547e7a0732a03 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdeh029a1.overlay @@ -5,6 +5,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_waveshare_epaper_gdeh029a1 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; @@ -25,7 +26,7 @@ reg = <0>; width = <296>; height = <128>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; softstart = [d7 d6 9d]; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay index 2a1024ece0d82..8820a0590e2a6 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2-p.overlay @@ -5,6 +5,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_waveshare_epaper_gdew042t2-p { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -30,7 +31,7 @@ reg = <0>; width = <400>; height = <300>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; softstart = [ 17 17 17 ]; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay index 035110ea5dcd9..c92c580e3a420 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdew042t2.overlay @@ -4,6 +4,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -13,8 +14,8 @@ mipi_dbi_waveshare_epaper_gdew042t2 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -25,7 +26,7 @@ reg = <0>; width = <400>; height = <300>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; softstart = [17 17 17]; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay index 8c8cbd9d636ed..f78a64de90709 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdew075t7.overlay @@ -5,6 +5,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_waveshare_epaper_gdew075t7 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; write-only; #address-cells = <1>; #size-cells = <0>; @@ -26,7 +27,7 @@ reg = <0>; width = <800>; height = <480>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; softstart = [17 17 17 17]; diff --git a/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay b/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay index 8299b7242745d..a22a1cbecef80 100644 --- a/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay +++ b/boards/shields/waveshare_epaper/waveshare_epaper_gdey0213b74.overlay @@ -5,6 +5,7 @@ */ #include "waveshare_epaper_common.dtsi" +#include / { chosen { @@ -14,8 +15,8 @@ mipi_dbi_waveshare_epaper_gdey0213b74 { compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&arduino_spi>; - dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */ + dc-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; @@ -25,7 +26,7 @@ reg = <0>; width = <250>; height = <122>; - busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */ + busy-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_HIGH>; tssv = <0x80>; diff --git a/boards/shields/wnc_m14a2a/boards/frdm_k64f.overlay b/boards/shields/wnc_m14a2a/boards/frdm_k64f.overlay index 546abb40985bc..f7c05bce52d2b 100644 --- a/boards/shields/wnc_m14a2a/boards/frdm_k64f.overlay +++ b/boards/shields/wnc_m14a2a/boards/frdm_k64f.overlay @@ -8,6 +8,9 @@ * WNC-M14A2A shield uses an odd UART available on *some* Arduino-R3-compatible * headers. It needs to be defined individually. */ + +#include + &uart2 { current-speed = <115200>; hw-flow-control; @@ -16,10 +19,10 @@ wnc_m14a2a: wncm14a2a { status = "okay"; compatible = "wnc,m14a2a"; - mdm-boot-mode-sel-gpios = <&arduino_header 7 GPIO_ACTIVE_HIGH>; /* D1 */ - mdm-power-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */ - mdm-keep-awake-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */ - mdm-reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */ - mdm-shld-trans-ena-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ + mdm-boot-mode-sel-gpios = <&arduino_header ARDUINO_HEADER_R3_D1 GPIO_ACTIVE_HIGH>; + mdm-power-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_LOW>; + mdm-keep-awake-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; + mdm-reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_HIGH>; + mdm-shld-trans-ena-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/wnc_m14a2a/boards/nrf52840dk_nrf52840.overlay b/boards/shields/wnc_m14a2a/boards/nrf52840dk_nrf52840.overlay index 8ed695b37d95f..45eaf24a5d5cd 100644 --- a/boards/shields/wnc_m14a2a/boards/nrf52840dk_nrf52840.overlay +++ b/boards/shields/wnc_m14a2a/boards/nrf52840dk_nrf52840.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &pinctrl { uart1_default_alt: uart1_default_alt { group1 { @@ -41,10 +43,10 @@ wnc_m14a2a: wncm14a2a { status = "okay"; compatible = "wnc,m14a2a"; - mdm-boot-mode-sel-gpios = <&arduino_header 7 GPIO_ACTIVE_HIGH>; /* D1 */ - mdm-power-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */ - mdm-keep-awake-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */ - mdm-reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */ - mdm-shld-trans-ena-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ + mdm-boot-mode-sel-gpios = <&arduino_header ARDUINO_HEADER_R3_D1 GPIO_ACTIVE_HIGH>; + mdm-power-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_LOW>; + mdm-keep-awake-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; + mdm-reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D8 GPIO_ACTIVE_HIGH>; + mdm-shld-trans-ena-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay b/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay index 14f9a1548ba6d..4e5795700ed14 100644 --- a/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay +++ b/boards/shields/x_nucleo_bnrg2a1/x_nucleo_bnrg2a1.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,bt-hci = &hci_spi; @@ -11,13 +13,14 @@ }; &arduino_spi { - cs-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; /* A1 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_A1 GPIO_ACTIVE_LOW>; hci_spi: bluenrg-2@0 { compatible = "st,hci-spi-v2"; reg = <0>; - reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ - irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */ + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 + (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; spi-cpha; /* CPHA=1 */ spi-hold-cs; spi-max-frequency = ; diff --git a/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay b/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay index 84f1cda1a3cfa..054c2095913df 100644 --- a/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay +++ b/boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay @@ -6,6 +6,7 @@ #include #include +#include / { aliases { @@ -28,7 +29,7 @@ timeout = <5>; /* if solder-bridge closed: arduino A1 pin on CN8 can wp */ - /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */ + /* wp-gpios = <&arduino_header ARDUINO_HEADER_R3_A1 GPIO_ACTIVE_LOW>; */ }; eeprom1_x_nucleo_eeprma2: eeprom@55 { @@ -41,7 +42,7 @@ timeout = <5>; /* if solder-bridge closed: arduino A1 pin on CN8 can wp */ - /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */ + /* wp-gpios = <&arduino_header ARDUINO_HEADER_R3_A1 GPIO_ACTIVE_LOW>; */ }; eeprom2_x_nucleo_eeprma2: eeprom@56 { @@ -54,7 +55,7 @@ timeout = <5>; /* if solder-bridge closed: arduino A1 pin on CN8 can wp */ - /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */ + /* wp-gpios = <&arduino_header ARDUINO_HEADER_R3_A1 GPIO_ACTIVE_LOW>; */ }; /* U4: unpopulated SO8N footprint for any I2C M24 EEPROM */ @@ -62,9 +63,9 @@ &arduino_spi { status = "okay"; - cs-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>, /* U5: eeprom4 */ - <&arduino_header 15 GPIO_ACTIVE_LOW>, /* U6: eeprom5 */ - <&arduino_header 16 GPIO_ACTIVE_LOW>; /* U7: eeprom6 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D2 GPIO_ACTIVE_LOW>, /* U5: eeprom4 */ + <&arduino_header ARDUINO_HEADER_R3_D9 GPIO_ACTIVE_LOW>, /* U6: eeprom5 */ + <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; /* U7: eeprom6 */ /* * All chip select pins have an on board 10k pull-up resistor to VCC, @@ -91,7 +92,7 @@ timeout = <5>; /* if solder-bridge closed: arduino A0 pin on CN8 can wp */ - /* wp-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; */ + /* wp-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 GPIO_ACTIVE_LOW>; */ }; eeprom5_x_nucleo_eeprma2: eeprom_m95256@1 { @@ -105,7 +106,7 @@ timeout = <5>; /* if solder-bridge closed: arduino A0 pin on CN8 can wp */ - /* wp-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; */ + /* wp-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 GPIO_ACTIVE_LOW>; */ }; eeprom6_x_nucleo_eeprma2: eeprom_m95m04@2 { @@ -120,7 +121,7 @@ timeout = <5>; /* if solder-bridge closed: arduino A0 pin on CN8 can wp */ - /* wp-gpios = <&arduino_header 0 GPIO_ACTIVE_LOW>; */ + /* wp-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 GPIO_ACTIVE_LOW>; */ }; /* U8: unpopulated SO8N footprint for any M95 SPI EEPROM */ diff --git a/boards/shields/x_nucleo_gfx01m2/x_nucleo_gfx01m2.overlay b/boards/shields/x_nucleo_gfx01m2/x_nucleo_gfx01m2.overlay index 0f3d0261a71c6..fff1929494990 100644 --- a/boards/shields/x_nucleo_gfx01m2/x_nucleo_gfx01m2.overlay +++ b/boards/shields/x_nucleo_gfx01m2/x_nucleo_gfx01m2.overlay @@ -56,6 +56,7 @@ compatible = "zephyr,mipi-dbi-spi"; spi-dev = <&st_morpho_lcd_spi>; dc-gpios = <&st_morpho_header ST_MORPHO_R_25 GPIO_ACTIVE_HIGH>; + te-gpios = <&st_morpho_header ST_MORPHO_L_28 GPIO_ACTIVE_HIGH>; reset-gpios = <&st_morpho_header ST_MORPHO_L_30 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; @@ -65,6 +66,10 @@ compatible = "ilitek,ili9341"; mipi-max-frequency = ; mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + /* Transmit on falling edge to avoid tearing, since display + * reads pixels faster than we can transfer. + */ + te-mode = "MIPI_DBI_TE_FALLING_EDGE"; reg = <0>; width = <240>; height = <320>; diff --git a/boards/shields/x_nucleo_idb05a1/boards/stm32mp157c_dk2.overlay b/boards/shields/x_nucleo_idb05a1/boards/stm32mp157c_dk2.overlay index 089654757ac57..54e77e50e94f4 100644 --- a/boards/shields/x_nucleo_idb05a1/boards/stm32mp157c_dk2.overlay +++ b/boards/shields/x_nucleo_idb05a1/boards/stm32mp157c_dk2.overlay @@ -4,9 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { spbtle_rf_x_nucleo_idb05a1: spbtle-rf@0 { - cs-gpios = <&arduino_header 16 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* D10 */ - irq-gpios = <&arduino_header 15 0>; /* D9 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 + (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D9 0>; }; }; diff --git a/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay b/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay index 9991e70665d54..99ff8704836de 100644 --- a/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay +++ b/boards/shields/x_nucleo_idb05a1/x_nucleo_idb05a1.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,bt-hci = &spbtle_rf_x_nucleo_idb05a1; @@ -11,13 +13,14 @@ }; &arduino_spi { - cs-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; /* A1 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_A1 GPIO_ACTIVE_LOW>; spbtle_rf_x_nucleo_idb05a1: spbtle-rf@0 { compatible = "st,hci-spi-v1"; reg = <0>; - reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ - irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */ + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 + (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; spi-max-frequency = ; spi-hold-cs; }; diff --git a/boards/shields/x_nucleo_iks01a1/x_nucleo_iks01a1.overlay b/boards/shields/x_nucleo_iks01a1/x_nucleo_iks01a1.overlay index 0169198e79af8..3c9ca533af18f 100644 --- a/boards/shields/x_nucleo_iks01a1/x_nucleo_iks01a1.overlay +++ b/boards/shields/x_nucleo_iks01a1/x_nucleo_iks01a1.overlay @@ -4,6 +4,9 @@ * * SPDX-License-Identifier: Apache-2.0 */ + +#include + / { aliases { accel0 = &lsm6ds0_x_nucleo_iks01a1; @@ -25,7 +28,7 @@ lis3mdl_magn_x_nucleo_iks01a1: lis3mdl-magn@1e { compatible = "st,lis3mdl-magn"; reg = <0x1e>; - irq-gpios = <&arduino_header 5 GPIO_ACTIVE_HIGH>; /* DRDY on A5 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A5 GPIO_ACTIVE_HIGH>; }; lsm6ds0_x_nucleo_iks01a1: lsm6ds0@6b { diff --git a/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2.overlay b/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2.overlay index fbeb90c551fbc..c4c511d7e9ca1 100644 --- a/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2.overlay +++ b/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2.overlay @@ -5,6 +5,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { magn0 = &lsm303agr_magn_1e_x_nucleo_iks01a2; @@ -28,18 +30,18 @@ lsm6dsl_6b_x_nucleo_iks01a2: lsm6dsl@6b { compatible = "st,lsm6dsl"; reg = <0x6b>; - irq-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D4 GPIO_ACTIVE_HIGH>; }; lsm303agr_magn_1e_x_nucleo_iks01a2: lsm303agr-magn@1e { compatible = "st,lis2mdl","st,lsm303agr-magn"; reg = <0x1e>; - irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A3 GPIO_ACTIVE_HIGH>; }; lsm303agr_accel_19_x_nucleo_iks01a2: lsm303agr-accel@19 { compatible = "st,lis2dh", "st,lsm303agr-accel"; reg = <0x19>; - irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A3 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2_shub.overlay b/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2_shub.overlay index 1976390f306d5..f7f58a90363ae 100644 --- a/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2_shub.overlay +++ b/boards/shields/x_nucleo_iks01a2/x_nucleo_iks01a2_shub.overlay @@ -5,10 +5,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_i2c { lsm6dsl_x_nucleo_iks01a2_shub: lsm6dsl@6b { compatible = "st,lsm6dsl"; reg = <0x6b>; - irq-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D4 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay b/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay index abc28041acc28..0eb2afd552ea7 100644 --- a/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay +++ b/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay @@ -5,6 +5,7 @@ */ #include +#include / { aliases { @@ -24,31 +25,31 @@ lps22hh_x_nucleo_iks01a3: lps22hh@5d { compatible = "st,lps22hh"; reg = <0x5d>; - drdy-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; }; stts751_x_nucleo_iks01a3: stts751@4a { compatible = "st,stts751"; reg = <0x4a>; - drdy-gpios = <&arduino_header 4 GPIO_ACTIVE_LOW>; /* A4 */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_A4 GPIO_ACTIVE_LOW>; }; lis2mdl_1e_x_nucleo_iks01a3: lis2mdl@1e { compatible = "st,lis2mdl"; reg = <0x1e>; - irq-gpios = <&arduino_header 2 GPIO_ACTIVE_HIGH>; /* A2 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A2 GPIO_ACTIVE_HIGH>; }; lis2dw12_19_x_nucleo_iks01a3: lis2dw12@19 { compatible = "st,lis2dw12"; reg = <0x19>; - irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A3 GPIO_ACTIVE_HIGH>; }; lsm6dso_6b_x_nucleo_iks01a3: lsm6dso@6b { compatible = "st,lsm6dso"; reg = <0x6b>; - irq-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; int-pin = <2>; }; }; diff --git a/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3_shub.overlay b/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3_shub.overlay index a6c7021d64095..57cbe2708f262 100644 --- a/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3_shub.overlay +++ b/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3_shub.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { accel0 = &lis2dw12_19_x_nucleo_iks01a3_shub; @@ -16,13 +18,13 @@ lis2dw12_19_x_nucleo_iks01a3_shub: lis2dw12@19 { compatible = "st,lis2dw12"; reg = <0x19>; - irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A3 GPIO_ACTIVE_HIGH>; }; lsm6dso_6b_x_nucleo_iks01a3_shub: lsm6dso@6b { compatible = "st,lsm6dso"; reg = <0x6b>; - irq-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; int-pin = <2>; }; }; diff --git a/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1.overlay b/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1.overlay index 181716b196566..cddef78ce6e96 100644 --- a/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1.overlay +++ b/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1.overlay @@ -13,6 +13,8 @@ * ISM330DHCX, IIS2MDC and IIS2DLPC sensors are accessible from the main board mcu. */ +#include + / { aliases { accel0 = &iis2dlpc_19_x_nucleo_iks02a1; @@ -25,20 +27,20 @@ iis2dlpc_19_x_nucleo_iks02a1: iis2dlpc@19 { compatible = "st,iis2dlpc"; reg = <0x19>; - drdy-gpios = <&arduino_header 4 GPIO_ACTIVE_HIGH>; /* A4 - INT2 */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_A4 GPIO_ACTIVE_HIGH>; drdy-int = <2>; }; iis2mdc_x_nucleo_iks02a1: iis2mdc@1e { compatible = "st,iis2mdc"; reg = <0x1e>; - drdy-gpios = <&arduino_header 2 GPIO_ACTIVE_HIGH>; /* A2 */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_A2 GPIO_ACTIVE_HIGH>; }; ism330dhcx_6b_x_nucleo_iks02a1: ism330dhcx@6b { compatible = "st,ism330dhcx"; reg = <0x6b>; - drdy-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 - INT2 */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; int-pin = <2>; }; }; diff --git a/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1_shub.overlay b/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1_shub.overlay index c18526354f6af..e88498299bfe9 100644 --- a/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1_shub.overlay +++ b/boards/shields/x_nucleo_iks02a1/x_nucleo_iks02a1_shub.overlay @@ -15,6 +15,8 @@ * declared in DTS file. */ +#include + / { aliases { accel0 = &iis2dlpc_19_x_nucleo_iks02a1_shub; @@ -27,14 +29,14 @@ iis2dlpc_19_x_nucleo_iks02a1_shub: iis2dlpc@19 { compatible = "st,iis2dlpc"; reg = <0x19>; - drdy-gpios = <&arduino_header 4 GPIO_ACTIVE_HIGH>; /* A4 - INT2 */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_A4 GPIO_ACTIVE_HIGH>; drdy-int = <2>; }; ism330dhcx_6b_x_nucleo_iks02a1_shub: ism330dhcx@6b { compatible = "st,ism330dhcx"; reg = <0x6b>; - drdy-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 - INT2 */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; int-pin = <2>; }; }; diff --git a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay index eaa60be0f4dae..9d058fbeedf77 100644 --- a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay +++ b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { magn0 = &lis2mdl_1e_x_nucleo_iks4a1; @@ -20,7 +22,7 @@ reg = <0x6a>; accel-odr = <0x1b>; gyro-odr = <0x11>; - irq-gpios = <&arduino_header 5 GPIO_ACTIVE_HIGH>; /* A5 (PC0) */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A5 GPIO_ACTIVE_HIGH>; drdy-pin = <1>; }; @@ -29,7 +31,7 @@ reg = <0x6b>; accel-odr = <0x02>; gyro-odr = <0x02>; - int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ + int2-gpios = <&arduino_header ARDUINO_HEADER_R3_D4 GPIO_ACTIVE_HIGH>; drdy-pin = <2>; drdy-pulsed; }; @@ -37,20 +39,20 @@ lis2mdl_1e_x_nucleo_iks4a1: lis2mdl@1e { compatible = "st,lis2mdl"; reg = <0x1e>; - irq-gpios = <&arduino_header 2 GPIO_ACTIVE_HIGH>; /* A2 (PA4) */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A2 GPIO_ACTIVE_HIGH>; }; lps22df_5d_x_nucleo_iks4a1: lps22df@5d { compatible = "st,lps22df"; reg = <0x5d>; drdy-pulsed; - drdy-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 (PB10) */ + drdy-gpios = <&arduino_header ARDUINO_HEADER_R3_D6 GPIO_ACTIVE_HIGH>; }; lis2duxs12_1e_x_nucleo_iks4a1: lis2duxs12@19 { compatible = "st,lis2duxs12"; reg = <0x19>; - int1-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_A3 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub1.overlay b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub1.overlay index 6560816c25cec..d2410b9cfb7c2 100644 --- a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub1.overlay +++ b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub1.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { accel0 = &lsm6dsv16x_6b_x_nucleo_iks4a1; @@ -16,7 +18,7 @@ reg = <0x6b>; accel-odr = <0x02>; gyro-odr = <0x02>; - int1-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 */ + int1-gpios = <&arduino_header ARDUINO_HEADER_R3_D5 GPIO_ACTIVE_HIGH>; drdy-pin = <1>; }; }; diff --git a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub2.overlay b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub2.overlay index 6c259fb221b63..6bf6254560084 100644 --- a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub2.overlay +++ b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1_shub2.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { aliases { accel0 = &lsm6dso16is_6a_x_nucleo_iks4a1_shub; @@ -14,7 +16,7 @@ lsm6dso16is_6a_x_nucleo_iks4a1_shub: lsm6dso16is@6a { compatible = "st,lsm6dso16is"; reg = <0x6a>; - irq-gpios = <&arduino_header 5 GPIO_ACTIVE_HIGH>; /* A5 */ + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A5 GPIO_ACTIVE_HIGH>; drdy-pin = <1>; }; }; diff --git a/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay index 43cf2be0d2a8e..3c8fd820561b5 100644 --- a/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay +++ b/boards/shields/x_nucleo_wb05kn1/x_nucleo_wb05kn1_spi.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { chosen { zephyr,bt-hci = &hci_spi; @@ -11,13 +13,14 @@ }; &arduino_spi { - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + cs-gpios = <&arduino_header ARDUINO_HEADER_R3_D10 GPIO_ACTIVE_LOW>; hci_spi: wb05n@0 { compatible = "st,hci-spi-v2"; reg = <0>; - reset-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */ - irq-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* A0 */ + reset-gpios = <&arduino_header ARDUINO_HEADER_R3_D7 GPIO_ACTIVE_LOW>; + irq-gpios = <&arduino_header ARDUINO_HEADER_R3_A0 + (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; spi-cpol; /* CPOL=1 */ spi-cpha; /* CPHA=1 */ spi-hold-cs; diff --git a/boards/sifive/hifive1/hifive1.dts b/boards/sifive/hifive1/hifive1.dts index 2034d10bc95fb..dff9a61b2a907 100644 --- a/boards/sifive/hifive1/hifive1.dts +++ b/boards/sifive/hifive1/hifive1.dts @@ -4,6 +4,7 @@ /dts-v1/; #include +#include #include #include "hifive1-pinctrl.dtsi" @@ -66,27 +67,27 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = /* A0 not connected */ - <1 0 &gpio0 9 0>, /* A1, also CS2 */ - <2 0 &gpio0 10 0>, /* A2, also WF_INT */ - <3 0 &gpio0 11 0>, /* A3 */ - <4 0 &gpio0 12 0>, /* A4 */ - <5 0 &gpio0 13 0>, /* A5 */ - <6 0 &gpio0 16 0>, /* D0, also TX */ - <7 0 &gpio0 17 0>, /* D1, also RX */ - <8 0 &gpio0 18 0>, /* D2 */ - <9 0 &gpio0 19 0>, /* D3 */ - <10 0 &gpio0 20 0>, /* D4 */ - <11 0 &gpio0 21 0>, /* D5 */ - <12 0 &gpio0 22 0>, /* D6 */ - <13 0 &gpio0 23 0>, /* D7 */ - <14 0 &gpio0 0 0>, /* D8 */ - <15 0 &gpio0 1 0>, /* D9 */ - <16 0 &gpio0 2 0>, /* D10 */ - <17 0 &gpio0 3 0>, /* D11, also MOSI */ - <18 0 &gpio0 4 0>, /* D12, also MISO */ - <19 0 &gpio0 5 0>, /* D13, also SCK */ - <20 0 &gpio0 12 0>, /* D14, also SDA */ - <21 0 &gpio0 13 0>; /* D15, also SCL */ + , /* also CS2 */ + , /* also WF_INT */ + , + , + , + , /* also TX */ + , /* also RX */ + , + , + , + , + , + , + , + , + , + , /* also MOSI */ + , /* also MISO */ + , /* also SCK */ + , /* also SDA */ + ; /* also SCL */ }; }; diff --git a/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts index b6c14c03159cb..441c8fe2fc665 100644 --- a/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts +++ b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts @@ -78,6 +78,20 @@ zephyr,code = ; }; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <9 0 &gpioa 5 0>, + <11 0 &gpiob 4 0>, + <12 0 &gpiob 5 0>, + <13 0 &gpioc 9 0>, + <14 0 &gpiob 6 0>, + <15 0 &gpioa 8 0>, + <16 0 &gpioa 7 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &timer0 { @@ -213,22 +227,22 @@ read-only; }; - /* Reserve 208 kB for the application in slot 0 */ + /* Reserve 216 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 DT_SIZE_K(208)>; + reg = <0x0000c000 DT_SIZE_K(216)>; label = "image-0"; }; - /* Reserve 208 kB for the application in slot 1 */ - slot1_partition: partition@40000 { - reg = <0x00040000 DT_SIZE_K(208)>; + /* Reserve 216 kB for the application in slot 1 */ + slot1_partition: partition@42000 { + reg = <0x00042000 DT_SIZE_K(216)>; label = "image-1"; }; - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@74000 { - reg = <0x00074000 DT_SIZE_K(32)>; - label = "image-scratch"; + /* Reserve 32 kB for the storage partition */ + storage_partition: partition@78000 { + reg = <0x00078000 DT_SIZE_K(32)>; + label = "storage"; }; }; }; diff --git a/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts index 76184fb5c9a14..d30b4d255517d 100644 --- a/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts +++ b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts @@ -85,6 +85,23 @@ enable-gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; status = "okay"; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <4 0 &gpiod 11 0>, + <6 0 &gpiod 12 0>, + <8 0 &gpiod 13 0>, + <9 0 &gpiob 1 0>, + <10 0 &gpiod 14 0>, + <12 0 &gpiod 7 0>, + <13 0 &gpioc 11 0>, + <14 0 &gpiod 8 0>, + <15 0 &gpiod 10 0>, + <16 0 &gpiod 9 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &timer0 { @@ -221,22 +238,22 @@ read-only; }; - /* Reserve 208 kB for the application in slot 0 */ + /* Reserve 472 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 DT_SIZE_K(208)>; + reg = <0x0000c000 DT_SIZE_K(472)>; label = "image-0"; }; - /* Reserve 208 kB for the application in slot 1 */ - slot1_partition: partition@40000 { - reg = <0x00040000 DT_SIZE_K(208)>; + /* Reserve 472 kB for the application in slot 1 */ + slot1_partition: partition@82000 { + reg = <0x00082000 DT_SIZE_K(472)>; label = "image-1"; }; - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@74000 { - reg = <0x00074000 DT_SIZE_K(32)>; - label = "image-scratch"; + /* Reserve 32 kB for the storage partition */ + storage_partition: partition@f8000 { + reg = <0x000f8000 DT_SIZE_K(32)>; + label = "storage"; }; }; }; diff --git a/boards/silabs/dev_kits/sltb010a/CMakeLists.txt b/boards/silabs/dev_kits/sltb010a/CMakeLists.txt deleted file mode 100644 index ca93e65ac913a..0000000000000 --- a/boards/silabs/dev_kits/sltb010a/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_UART_GECKO) - zephyr_library() - zephyr_library_sources(board.c) -endif() diff --git a/boards/silabs/dev_kits/sltb010a/Kconfig b/boards/silabs/dev_kits/sltb010a/Kconfig deleted file mode 100644 index 6fdb24720ae40..0000000000000 --- a/boards/silabs/dev_kits/sltb010a/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# EFR32 Thunderboard-style boards - -# Copyright (c) 2022, Silicon Labs -# SPDX-License-Identifier: Apache-2.0 - -module = BOARD_SLTB010A -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/silabs/dev_kits/sltb010a/board.c b/boards/silabs/dev_kits/sltb010a/board.c deleted file mode 100644 index ac43052e3628e..0000000000000 --- a/boards/silabs/dev_kits/sltb010a/board.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -LOG_MODULE_REGISTER(thunderboard, CONFIG_BOARD_SLTB010A_LOG_LEVEL); - -static int thunderboard_init(void) -{ - int ret; - - static struct gpio_dt_spec wake_up_gpio_dev = - GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); - - - if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { - LOG_ERR("Wake-up GPIO device was not found!\n"); - return -ENODEV; - } - ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); - if (ret < 0) { - return ret; - } - - return 0; -} - -/* needs to be done after GPIO driver init */ -SYS_INIT(thunderboard_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/sltb010a/dts/bindings/silabs,gecko-wake-up-triggers.yaml b/boards/silabs/dev_kits/sltb010a/dts/bindings/silabs,gecko-wake-up-triggers.yaml deleted file mode 100644 index fd49c3732cad5..0000000000000 --- a/boards/silabs/dev_kits/sltb010a/dts/bindings/silabs,gecko-wake-up-triggers.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -description: GPIO Wake Up Trigger for EFR32BG22/EFR32BG27 - -compatible: "silabs,gecko-wake-up-trigger" - -include: base.yaml - -properties: - gpios: - type: phandle-array - required: true - description: | - GPIO used as wake up trigger from EM4 sleep diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a.dts b/boards/silabs/dev_kits/sltb010a/sltb010a.dts index 1b81fbe390d66..602ef95af048c 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a.dts +++ b/boards/silabs/dev_kits/sltb010a/sltb010a.dts @@ -77,26 +77,26 @@ partitions { /* Reserve 48 KiB for the bootloader */ boot_partition: partition@0 { - reg = <0x00000000 0x0000c000>; + reg = <0x00000000 DT_SIZE_K(48)>; label = "mcuboot"; read-only; }; /* Reserve 224 KiB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x00038000>; + reg = <0x0000c000 DT_SIZE_K(224)>; label = "image-0"; }; /* Reserve 224 KiB for the application in slot 1 */ slot1_partition: partition@44000 { - reg = <0x00044000 0x00038000>; + reg = <0x00044000 DT_SIZE_K(224)>; label = "image-1"; }; /* Set 16 KiB of storage at the end of the 512 KiB of flash */ storage_partition: partition@7c000 { - reg = <0x0007c000 0x00004000>; + reg = <0x0007c000 DT_SIZE_K(16)>; label = "storage"; }; }; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay b/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay index 3b3654f9c60bd..52fceb8c73938 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay @@ -17,3 +17,20 @@ &sw_mic_enable { enable-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; }; + +&exp_header { + gpio-map = <3 0 &gpioa 8 0>, + <4 0 &gpioc 0 0>, + <5 0 &gpioa 7 0>, + <6 0 &gpioc 1 0>, + <7 0 &gpioc 6 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpioc 7 0>, + <10 0 &gpiob 2 0>, + <11 0 &gpiob 0 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpiob 1 0>, + <14 0 &gpioa 6 0>, + <15 0 &gpiod 3 0>, + <16 0 &gpiod 2 0>; +}; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay b/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay index 8365fd71ee07f..a6cf5a3f93f5c 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay @@ -26,3 +26,20 @@ &sw_mic_enable { enable-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; }; + +&exp_header { + gpio-map = <3 0 &gpioa 8 0>, + <4 0 &gpioc 0 0>, + <5 0 &gpioa 7 0>, + <6 0 &gpioc 1 0>, + <7 0 &gpiob 0 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpiob 1 0>, + <10 0 &gpiob 2 0>, + <11 0 &gpioa 4 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpiob 3 0>, + <14 0 &gpioa 6 0>, + <15 0 &gpiod 3 0>, + <16 0 &gpiod 2 0>; +}; diff --git a/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi b/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi index d116c38feefb0..6ace190f6afb4 100644 --- a/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi +++ b/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi @@ -35,9 +35,11 @@ }; }; - wake_up_trigger: gpio-wake-up { - compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; }; /* GPIOs that power up different sensors */ diff --git a/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts index f02d403c312ed..d4e4acbf3bd5d 100644 --- a/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts +++ b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts @@ -181,26 +181,26 @@ /* Reserve 48 KiB for the bootloader */ boot_partition: partition@0 { - reg = <0x00000000 0x0000c000>; + reg = <0x00000000 DT_SIZE_K(48)>; label = "mcuboot"; read-only; }; /* Reserve 224 KiB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x00038000>; + reg = <0x0000c000 DT_SIZE_K(224)>; label = "image-0"; }; /* Reserve 224 KiB for the application in slot 1 */ slot1_partition: partition@44000 { - reg = <0x00044000 0x00038000>; + reg = <0x00044000 DT_SIZE_K(224)>; label = "image-1"; }; /* Set 16 KiB of storage at the end of the 512 KiB of flash */ storage_partition: partition@7c000 { - reg = <0x0007c000 0x00004000>; + reg = <0x0007c000 DT_SIZE_K(16)>; label = "storage"; }; }; diff --git a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig deleted file mode 100644 index f346dac95afe3..0000000000000 --- a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2022, Silicon Labs -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XG24_DK2601B - -module = BOARD_EFR32MG24 -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" - -endif # BOARD_XG24_DK2601B diff --git a/boards/silabs/dev_kits/xg24_dk2601b/board.c b/boards/silabs/dev_kits/xg24_dk2601b/board.c deleted file mode 100644 index 52c2e02e44a37..0000000000000 --- a/boards/silabs/dev_kits/xg24_dk2601b/board.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -LOG_MODULE_REGISTER(efr32xg24_dk2601b, CONFIG_BOARD_EFR32MG24_LOG_LEVEL); - -static int efr32xg24_dk2601b_init(void) -{ - int ret; - - static struct gpio_dt_spec wake_up_gpio_dev = - GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); - - - if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { - LOG_ERR("Wake-up GPIO device was not found!\n"); - return -ENODEV; - } - ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); - if (ret < 0) { - return ret; - } - - return 0; -} - -/* needs to be done after GPIO driver init */ -SYS_INIT(efr32xg24_dk2601b_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/silabs/dev_kits/xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml deleted file mode 100644 index ba8892f2ce0b2..0000000000000 --- a/boards/silabs/dev_kits/xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -description: GPIO Wake Up Trigger for EFR32MG24 - -compatible: "silabs,gecko-wake-up-trigger" - -include: base.yaml - -properties: - gpios: - type: phandle-array - required: true - description: | - GPIO used as wake up trigger from EM4 sleep diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts index 69a9af6a9566c..3d30acb7e2be8 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts @@ -86,17 +86,31 @@ }; }; - wake_up_trigger: gpio-wake-up { - compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - }; - sensor_enable: gpio_switch_0 { compatible = "regulator-fixed"; regulator-boot-on; regulator-name = "sensor_enable"; enable-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpiob 2 0>, + <4 0 &gpioc 3 0>, + <6 0 &gpioc 2 0>, + <8 0 &gpioc 1 0>, + <9 0 &gpiob 0 0>, + <10 0 &gpioa 7 0>, + <11 0 &gpiob 3 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpiod 2 0>, + <14 0 &gpioa 6 0>, + <15 0 &gpioc 4 0>, + <16 0 &gpioc 5 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &timer0 { @@ -256,32 +270,26 @@ /* Reserve 48 kB for the bootloader */ boot_partition: partition@0 { - reg = <0x0 0x0000c000>; + reg = <0x0 DT_SIZE_K(48)>; label = "mcuboot"; read-only; }; - /* Reserve 464 kB for the application in slot 0 */ + /* Reserve 728 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x00074000>; + reg = <0x0000c000 DT_SIZE_K(728)>; label = "image-0"; }; - /* Reserve 464 kB for the application in slot 1 */ - slot1_partition: partition@80000 { - reg = <0x00080000 0x00074000>; + /* Reserve 728 kB for the application in slot 1 */ + slot1_partition: partition@c2000 { + reg = <0x000c2000 DT_SIZE_K(728)>; label = "image-1"; }; - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@f4000 { - reg = <0x000f4000 0x00008000>; - label = "image-scratch"; - }; - - /* Set 528Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fc000 { - reg = <0x000fc000 0x00084000>; + /* Set 32 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@178000 { + reg = <0x00178000 DT_SIZE_K(32)>; label = "storage"; }; }; diff --git a/boards/silabs/dev_kits/xg24_ek2703a/CMakeLists.txt b/boards/silabs/dev_kits/xg24_ek2703a/CMakeLists.txt deleted file mode 100644 index 2e35c87b81db6..0000000000000 --- a/boards/silabs/dev_kits/xg24_ek2703a/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Norik Systems -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(board.c) diff --git a/boards/silabs/dev_kits/xg24_ek2703a/Kconfig b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig deleted file mode 100644 index bcc3f461f6e03..0000000000000 --- a/boards/silabs/dev_kits/xg24_ek2703a/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# EFR32XG24 EK2703A board - -# Copyright (c) 2022, Silicon Labs -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XG24_EK2703A - -config BOARD_XG24_EK2703A - select GPIO - select BOARD_LATE_INIT_HOOK - -module = BOARD_EFR32MG24 -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" - -endif # BOARD_XG24_EK2703A diff --git a/boards/silabs/dev_kits/xg24_ek2703a/board.c b/boards/silabs/dev_kits/xg24_ek2703a/board.c deleted file mode 100644 index 2ffc7aa210db7..0000000000000 --- a/boards/silabs/dev_kits/xg24_ek2703a/board.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -LOG_MODULE_REGISTER(efr32xg24_ek2703a, CONFIG_BOARD_EFR32MG24_LOG_LEVEL); - -void board_late_init_hook(void) -{ - int ret; - - static struct gpio_dt_spec wake_up_gpio_dev = - GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); - - if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { - LOG_ERR("Wake-up GPIO device was not found!\n"); - } - ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); - if (ret < 0) { - LOG_ERR("Failed to configure wake-up GPIO!\n"); - } -} diff --git a/boards/silabs/dev_kits/xg24_ek2703a/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/silabs/dev_kits/xg24_ek2703a/dts/bindings/silabs,gecko-wake-up-trigger.yaml deleted file mode 100644 index ba8892f2ce0b2..0000000000000 --- a/boards/silabs/dev_kits/xg24_ek2703a/dts/bindings/silabs,gecko-wake-up-trigger.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -description: GPIO Wake Up Trigger for EFR32MG24 - -compatible: "silabs,gecko-wake-up-trigger" - -include: base.yaml - -properties: - gpios: - type: phandle-array - required: true - description: | - GPIO used as wake up trigger from EM4 sleep diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts index b837a3167d9b9..824f9aaaa4169 100644 --- a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts +++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts @@ -57,11 +57,6 @@ zephyr,code = ; }; }; - - wake_up_trigger: gpio-wake-up { - compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - }; }; &cpu0 { @@ -172,32 +167,26 @@ /* Reserve 48 kB for the bootloader */ boot_partition: partition@0 { - reg = <0x0 0x0000c000>; + reg = <0x0 DT_SIZE_K(48)>; label = "mcuboot"; read-only; }; - /* Reserve 464 kB for the application in slot 0 */ + /* Reserve 728 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x00074000>; + reg = <0x0000c000 DT_SIZE_K(728)>; label = "image-0"; }; - /* Reserve 464 kB for the application in slot 1 */ - slot1_partition: partition@80000 { - reg = <0x00080000 0x00074000>; + /* Reserve 728 kB for the application in slot 1 */ + slot1_partition: partition@c2000 { + reg = <0x000c2000 DT_SIZE_K(728)>; label = "image-1"; }; - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@f4000 { - reg = <0x000f4000 0x00008000>; - label = "image-scratch"; - }; - - /* Set 528Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fc000 { - reg = <0x000fc000 0x00084000>; + /* Set 32 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@178000 { + reg = <0x00178000 DT_SIZE_K(32)>; label = "storage"; }; }; diff --git a/boards/silabs/dev_kits/xg27_dk2602a/CMakeLists.txt b/boards/silabs/dev_kits/xg27_dk2602a/CMakeLists.txt deleted file mode 100644 index ca93e65ac913a..0000000000000 --- a/boards/silabs/dev_kits/xg27_dk2602a/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_UART_GECKO) - zephyr_library() - zephyr_library_sources(board.c) -endif() diff --git a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig deleted file mode 100644 index 965bfde207a38..0000000000000 --- a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# EFR32 Thunderboard-style boards - -# Copyright (c) 2022, Silicon Labs -# SPDX-License-Identifier: Apache-2.0 - -module = BOARD_XG27_DK2602A -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/silabs/dev_kits/xg27_dk2602a/board.c b/boards/silabs/dev_kits/xg27_dk2602a/board.c deleted file mode 100644 index 7c466f6ee74ca..0000000000000 --- a/boards/silabs/dev_kits/xg27_dk2602a/board.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -LOG_MODULE_REGISTER(dev_kit, CONFIG_BOARD_XG27_DK2602A_LOG_LEVEL); - -static int dev_kit_init(void) -{ - int ret; - - static struct gpio_dt_spec wake_up_gpio_dev = - GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); - - - if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { - LOG_ERR("Wake-up GPIO device was not found!\n"); - return -ENODEV; - } - ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); - if (ret < 0) { - return ret; - } - - return 0; -} - -/* needs to be done after GPIO driver init */ -SYS_INIT(dev_kit_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/xg27_dk2602a/dts/bindings/silabs,gecko-wake-up-triggers.yaml b/boards/silabs/dev_kits/xg27_dk2602a/dts/bindings/silabs,gecko-wake-up-triggers.yaml deleted file mode 100644 index fd49c3732cad5..0000000000000 --- a/boards/silabs/dev_kits/xg27_dk2602a/dts/bindings/silabs,gecko-wake-up-triggers.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -description: GPIO Wake Up Trigger for EFR32BG22/EFR32BG27 - -compatible: "silabs,gecko-wake-up-trigger" - -include: base.yaml - -properties: - gpios: - type: phandle-array - required: true - description: | - GPIO used as wake up trigger from EM4 sleep diff --git a/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi index 31393a809c223..dba0df3881560 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi +++ b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi @@ -35,11 +35,6 @@ }; }; - wake_up_trigger: gpio-wake-up { - compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - }; - /* GPIOs that power up different sensors */ sw_sensor_enable: gpio_switch_0 { compatible = "regulator-fixed"; @@ -61,6 +56,26 @@ startup-delay-us = <100000>; }; + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpioa 8 0>, + <4 0 &gpioc 0 0>, + <5 0 &gpioa 7 0>, + <6 0 &gpioc 1 0>, + <7 0 &gpiob 0 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpiob 1 0>, + <10 0 &gpiob 2 0>, + <11 0 &gpioa 4 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpiob 3 0>, + <14 0 &gpioa 6 0>, + <15 0 &gpiod 3 0>, + <16 0 &gpiod 2 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &cpu0 { diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts index 2e6281674fb3c..0e642f1a5fcb9 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts @@ -86,21 +86,21 @@ read-only; }; - /* Reserve 328 KiB for the application in slot 0 */ + /* Reserve 344 KiB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x00052000>; + reg = <0x0000c000 DT_SIZE_K(344)>; label = "image-0"; }; - /* Reserve 328 KiB for the application in slot 1 */ - slot1_partition: partition@5e000 { - reg = <0x0005e000 0x00052000>; + /* Reserve 344 KiB for the application in slot 1 */ + slot1_partition: partition@62000 { + reg = <0x00062000 DT_SIZE_K(344)>; label = "image-1"; }; - /* Set 64 KiB of storage at the end of the 768 KiB of flash */ - storage_partition: partition@b0000 { - reg = <0x000b0000 0x00010000>; + /* Set 32 KiB of storage at the end of the 768 KiB of flash */ + storage_partition: partition@b8000 { + reg = <0x000b8000 DT_SIZE_K(32)>; label = "storage"; }; }; diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml index 8f8bfd19fb278..73d0ba0dc8d69 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml @@ -16,4 +16,5 @@ supported: - clock_control - comparator - adc + - watchdog vendor: silabs diff --git a/boards/silabs/radio_boards/bg29_rb4420a/Kconfig.bg29_rb4420a b/boards/silabs/radio_boards/bg29_rb4420a/Kconfig.bg29_rb4420a new file mode 100644 index 0000000000000..f6f1948b75750 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/Kconfig.bg29_rb4420a @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BG29_RB4420A + select SOC_EFR32BG29B220F1024CJ45 diff --git a/boards/silabs/radio_boards/bg29_rb4420a/Kconfig.defconfig b/boards/silabs/radio_boards/bg29_rb4420a/Kconfig.defconfig new file mode 100644 index 0000000000000..cf1b81a4735c0 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BG29_RB4420A + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_BG29_RB4420A diff --git a/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a-pinctrl.dtsi b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a-pinctrl.dtsi new file mode 100644 index 0000000000000..453436574c778 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a-pinctrl.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + eusart1_default: eusart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + letimer0_default: letimer0_default { + group0 { + pins = ; + drive-open-drain; + bias-pull-up; + }; + }; + + pti_default: pti_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; +}; diff --git a/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a.dts b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a.dts new file mode 100644 index 0000000000000..7b7b11e774de1 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a.dts @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "bg29_rb4420a-pinctrl.dtsi" + +/ { + model = "Silicon Labs BG29-RB4420A"; + compatible = "silabs,bg29_rb4420a", "silabs,efr32bg29"; + + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart1; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart1; + }; + + aliases { + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + spi-flash0 = &mx25r80; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpiob 2 GPIO_ACTIVE_LOW>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + label = "LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&letimer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpiob 2 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpioa 4 0>, + <4 0 &gpioc 5 0>, + <5 0 &gpioa 0 0>, + <6 0 &gpioc 3 0>, + <7 0 &gpiob 2 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpiob 1 0>, + <10 0 &gpioc 6 0>, + <12 0 &gpioa 5 0>, + <14 0 &gpioa 6 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; +}; + +&cpu0 { + clock-frequency = <76800000>; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +&hfxo { + ctune = <133>; + precision = <50>; + status = "okay"; +}; + +&lfxo { + ctune = <32>; + precision = <50>; + status = "okay"; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&rtccclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&usart1 { + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&eusart1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + status = "okay"; + + cs-gpios = <&gpioc 4 GPIO_ACTIVE_LOW>; + + mx25r80: mx25r8035f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + dpd-wakeup-sequence = <30000 20 35000>; + has-dpd; + jedec-id = [c2 28 14]; + mxicy,mx25r-power-mode = "low-power"; + size = <0x800000>; + spi-max-frequency = ; + t-enter-dpd = <0>; + zephyr,pm-device-runtime-auto; + }; +}; + +&letimer0 { + status = "okay"; + + letimer0_pwm: pwm { + pinctrl-0 = <&letimer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + vcom-enable { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&rtcc0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&radio { + pa-voltage-mv = <1800>; + pa-initial-power-dbm = <0>; + pa-2p4ghz = "lp"; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + reg = <0x00000000 DT_SIZE_K(48)>; + label = "mcuboot"; + }; + + slot0_partition: partition@c000 { + reg = <0x0000C000 DT_SIZE_K(472)>; + label = "image-0"; + }; + + slot1_partition: partition@82000 { + reg = <0x00082000 DT_SIZE_K(472)>; + label = "image-1"; + }; + + storage_partition: partition@F8000 { + reg = <0x000F8000 DT_SIZE_K(32)>; + label = "storage"; + }; + }; +}; diff --git a/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a.yaml b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a.yaml new file mode 100644 index 0000000000000..de47d9a287407 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a.yaml @@ -0,0 +1,23 @@ +identifier: bg29_rb4420a +name: EFR32BG29 Bluetooth LE 4 dBm DCDC Boost WLCSP Radio Board (BG29-RB4420A, BRD4420A) +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - bluetooth + - comparator + - counter + - dma + - entropy + - gpio + - flash + - pwm + - spi + - uart + - watchdog +vendor: silabs diff --git a/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a_defconfig b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a_defconfig new file mode 100644 index 0000000000000..e70f8f5c5197d --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/bg29_rb4420a_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/radio_boards/bg29_rb4420a/board.cmake b/boards/silabs/radio_boards/bg29_rb4420a/board.cmake new file mode 100644 index 0000000000000..8100e9d46dfaa --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/board.cmake @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32BG29BxxxF1024") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=EFR32BG29B220F1024CJ45") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/radio_boards/bg29_rb4420a/board.yml b/boards/silabs/radio_boards/bg29_rb4420a/board.yml new file mode 100644 index 0000000000000..0973e45c54168 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/board.yml @@ -0,0 +1,6 @@ +board: + name: bg29_rb4420a + full_name: EFR32BG29 Bluetooth LE 4 dBm DCDC Boost WLCSP (BG29-RB4420A) + vendor: silabs + socs: + - name: efr32bg29b220f1024cj45 diff --git a/boards/silabs/radio_boards/bg29_rb4420a/doc/bg29-rb4420a-radio-board.webp b/boards/silabs/radio_boards/bg29_rb4420a/doc/bg29-rb4420a-radio-board.webp new file mode 100644 index 0000000000000..8ca8a81172a9c Binary files /dev/null and b/boards/silabs/radio_boards/bg29_rb4420a/doc/bg29-rb4420a-radio-board.webp differ diff --git a/boards/silabs/radio_boards/bg29_rb4420a/doc/index.rst b/boards/silabs/radio_boards/bg29_rb4420a/doc/index.rst new file mode 100644 index 0000000000000..31b2fae557707 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/doc/index.rst @@ -0,0 +1,110 @@ +.. zephyr:board:: bg29_rb4420a + +Overview +******** + +The EFR32BG29 Bluetooth LE +4 dBm DCDC Boost WLCSP Radio Board is a plug-in board for +the Wireless Starter Kit Mainboard (BRD4001A) and the Wireless Pro Kit Mainboard +(BRD4002A). It is a complete reference design for the DCDC Boost mode EFR32xG29 Wireless +SoC, a matching network and a PCB antenna for 4 dBm output power in the 2.4 GHz band. +The EFR32 on the radio board is powered in boost DC-DC configuration from an on-board LDO +for improved efficiency and to demonstrate single-cell operation. +See :ref:`silabs_radio_boards` for more information about the Wireless Mainboard platform. + +Hardware +******** + +- EFR32BG29B220F1024CJ45 SoC +- CPU core: ARM Cortex®-M33 with FPU, DSP and TrustZone +- Memory: 1024 kB Flash, 256 kB RAM +- Transmit power: up to +4 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz) + +For more information about the EFR32BG29 SoC and BRD4420A board, refer to these documents: + +- `BG29-RB4420A Website`_ +- `BG29-RB4420A User Guide`_ +- `EFR32BG29 Website`_ +- `EFR32BG29 Datasheet`_ +- `EFR32BG29 Reference Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The EFR32BG29 SoC is configured to use the HFRCODPLL oscillator at 76.8 MHz as the system +clock, locked to the 38.4 MHz external crystal oscillator on the board. + +Serial Port +=========== + +The EFR32BG29 SoC has two USARTs and two EUSARTs. +USART1 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners :: + +Connect the BRD4002A mainboard with a mounted BRD4420A radio board to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bg29_rb4420a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! bg29_rb4420a + +Bluetooth +========= + +To use Bluetooth functionality, run the command below to retrieve necessary binary +blobs from the Silicon Labs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: bg29_rb4420a + :goals: build + + +.. _BG29-RB4420A Website: + https://www.silabs.com/development-tools/wireless/bluetooth/bg29-rb4420a-efr32bg29-bluetooth-le-dcdc-boost-wlcsp-radio-board?tab=overview + +.. _BG29-RB4420A User Guide: + https://www.silabs.com/documents/public/user-guides/ug623-efr32bg29-brd4420a-user-guide.pdf + +.. _EFR32BG29 Website: + https://www.silabs.com/wireless/bluetooth/efr32bg29-series-2-socs + +.. _EFR32BG29 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32bg29-datasheet.pdf + +.. _EFR32BG29 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg29-rm.pdf diff --git a/boards/silabs/radio_boards/bg29_rb4420a/pre_dt_board.cmake b/boards/silabs/radio_boards/bg29_rb4420a/pre_dt_board.cmake new file mode 100644 index 0000000000000..66dcd771b3e83 --- /dev/null +++ b/boards/silabs/radio_boards/bg29_rb4420a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart/eusart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/doc/index.rst b/boards/silabs/radio_boards/siwx917_rb4338a/doc/index.rst index 4f54be884ab9c..db875d497fb92 100644 --- a/boards/silabs/radio_boards/siwx917_rb4338a/doc/index.rst +++ b/boards/silabs/radio_boards/siwx917_rb4338a/doc/index.rst @@ -77,7 +77,7 @@ Debugging ========= Debuggning relies on JLink tool. JLink is not able to flash the firmware. So -debug session has to be done in two steps. ``west flash`` will flahs the +debug session has to be done in two steps. ``west flash`` will flash the firmware using Simplicity Commander. Then ``west attach`` will use JLink to attach to the board. The Zephyr image may has already booted when user runs ``west attach``. User may execute ``monitor reset`` in the gdb prompt to reset diff --git a/boards/silabs/radio_boards/siwx917_rb4342a/doc/index.rst b/boards/silabs/radio_boards/siwx917_rb4342a/doc/index.rst index 09bafa11f0e34..58a378e200283 100644 --- a/boards/silabs/radio_boards/siwx917_rb4342a/doc/index.rst +++ b/boards/silabs/radio_boards/siwx917_rb4342a/doc/index.rst @@ -70,7 +70,7 @@ Debugging ========= Debuggning relies on JLink tool. JLink is not able to flash the firmware. So -debug session has to be done in two steps. ``west flash`` will flahs the +debug session has to be done in two steps. ``west flash`` will flash the firmware using Simplicity Commander. Then ``west attach`` will use JLink to attach to the board. The Zephyr image may has already booted when user runs ``west attach``. User may execute ``monitor reset`` in the gdb prompt to reset diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts index 769420b593c56..23c09e66e517c 100644 --- a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts @@ -62,6 +62,23 @@ zephyr,code = ; }; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <4 0 &gpioc 0 0>, + <6 0 &gpioc 1 0>, + <7 0 &gpiod 2 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpiod 3 0>, + <10 0 &gpioc 3 0>, + <11 0 &gpiob 0 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpiob 1 0>, + <14 0 &gpioa 6 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &cpu0 { @@ -160,34 +177,27 @@ /* Reserve 48 kB for the bootloader */ boot_partition: partition@0 { - reg = <0x0 0x0000c000>; + reg = <0x0 DT_SIZE_K(48)>; label = "mcuboot"; read-only; }; - /* Reserve 464 kB for the application in slot 0 */ + /* Reserve 472 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x00074000>; + reg = <0x0000c000 DT_SIZE_K(472)>; label = "image-0"; }; - /* Reserve 464 kB for the application in slot 1 */ - slot1_partition: partition@80000 { - reg = <0x00080000 0x00074000>; + /* Reserve 472 kB for the application in slot 1 */ + slot1_partition: partition@82000 { + reg = <0x00082000 DT_SIZE_K(472)>; label = "image-1"; }; - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@f4000 { - reg = <0x000f4000 0x00008000>; - label = "image-scratch"; - }; - - /* Set 16Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fc000 { - reg = <0x000fc000 0x00004000>; + /* Set 32Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@f8000 { + reg = <0x000f8000 DT_SIZE_K(32)>; label = "storage"; }; - }; }; diff --git a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts index 562c7343fab4c..d1a2464d6fdac 100644 --- a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts +++ b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts @@ -60,6 +60,23 @@ zephyr,code = ; }; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <4 0 &gpioc 0 0>, + <6 0 &gpioc 1 0>, + <7 0 &gpiob 0 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpiob 1 0>, + <10 0 &gpioc 3 0>, + <11 0 &gpiod 2 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpiod 3 0>, + <14 0 &gpioa 6 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &cpu0 { diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts index 285fabe29d6d2..eee786a0a5ad7 100644 --- a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts +++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts @@ -86,6 +86,26 @@ regulator-name = "sensor_disp_enable"; status = "okay"; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <4 0 &gpioc 1 0>, + <5 0 &gpioa 0 0>, + <6 0 &gpioc 2 0>, + <7 0 &gpioa 5 0>, + <8 0 &gpioc 3 0>, + <9 0 &gpiod 2 0>, + <10 0 &gpioc 0 0>, + <11 0 &gpioa 6 0>, + <12 0 &gpioa 8 0>, + <13 0 &gpioa 7 0>, + <14 0 &gpioa 9 0>, + <15 0 &gpioc 5 0>, + <16 0 &gpioc 7 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &timer0 { @@ -261,27 +281,21 @@ read-only; }; - /* Reserve 208 kB for the application in slot 0 */ + /* Reserve 216 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 DT_SIZE_K(208)>; + reg = <0x0000c000 DT_SIZE_K(216)>; label = "image-0"; }; - /* Reserve 208 kB for the application in slot 1 */ - slot1_partition: partition@40000 { - reg = <0x00040000 DT_SIZE_K(208)>; + /* Reserve 216 kB for the application in slot 1 */ + slot1_partition: partition@42000 { + reg = <0x00042000 DT_SIZE_K(216)>; label = "image-1"; }; - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@74000 { - reg = <0x00074000 DT_SIZE_K(32)>; - label = "image-scratch"; - }; - - /* Set 16 kB of storage at the end of the 1536 kB of flash */ - storage_partition: partition@7c000 { - reg = <0x0007c000 DT_SIZE_K(16)>; + /* Set 32 kB of storage at the end of the 512 kB of flash */ + storage_partition: partition@78000 { + reg = <0x00078000 DT_SIZE_K(32)>; label = "storage"; }; }; diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts index fc8c86a7185e6..fa0b874bbc2df 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts @@ -70,6 +70,27 @@ enable-gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; regulator-name = "sensor_enable"; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpiob 5 0>, + <4 0 &gpioc 1 0>, + <5 0 &gpioa 0 0>, + <6 0 &gpioc 2 0>, + <7 0 &gpioa 5 0>, + <8 0 &gpioc 3 0>, + <9 0 &gpiod 2 0>, + <10 0 &gpioc 0 0>, + <11 0 &gpioa 6 0>, + <12 0 &gpioa 8 0>, + <13 0 &gpioa 7 0>, + <14 0 &gpioa 9 0>, + <15 0 &gpioc 5 0>, + <16 0 &gpioc 7 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &cpu0 { @@ -236,27 +257,21 @@ read-only; }; - /* Reserve 720 kB for the application in slot 0 */ + /* Reserve 728 kB for the application in slot 0 */ slot0_partition: partition@c000 { - reg = <0x0000c000 0x000B4000>; + reg = <0x0000c000 DT_SIZE_K(728)>; label = "image-0"; }; - /* Reserve 720 kB for the application in slot 1 */ - slot1_partition: partition@C0000 { - reg = <0x000C0000 0x000B4000>; + /* Reserve 728 kB for the application in slot 1 */ + slot1_partition: partition@c2000 { + reg = <0x000c2000 DT_SIZE_K(728)>; label = "image-1"; }; - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@174000 { - reg = <0x00174000 DT_SIZE_K(32)>; - label = "image-scratch"; - }; - - /* Set 16 kB of storage at the end of the 1536 kB of flash */ - storage_partition: partition@17c000 { - reg = <0x0017c000 DT_SIZE_K(16)>; + /* Set 32 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@178000 { + reg = <0x00178000 DT_SIZE_K(32)>; label = "storage"; }; }; diff --git a/boards/silabs/radio_boards/xg28_rb4401c/Kconfig.defconfig b/boards/silabs/radio_boards/xg28_rb4401c/Kconfig.defconfig new file mode 100644 index 0000000000000..766c99a093083 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Shontal Biton +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG28_RB4401C + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +endif # BOARD_XG28_RB4401C diff --git a/boards/silabs/radio_boards/xg28_rb4401c/Kconfig.xg28_rb4401c b/boards/silabs/radio_boards/xg28_rb4401c/Kconfig.xg28_rb4401c new file mode 100644 index 0000000000000..305415a081fcc --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/Kconfig.xg28_rb4401c @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Shontal Biton +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG28_RB4401C + select SOC_EFR32ZG28B322F1024IM68 diff --git a/boards/silabs/radio_boards/xg28_rb4401c/board.cmake b/boards/silabs/radio_boards/xg28_rb4401c/board.cmake new file mode 100644 index 0000000000000..c7fe0494567d1 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32ZG28BxxxF1024") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(silabs_commander "--device=EFR32ZG28B322F1024IM68") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/radio_boards/xg28_rb4401c/board.yml b/boards/silabs/radio_boards/xg28_rb4401c/board.yml new file mode 100644 index 0000000000000..2df430d261ef6 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/board.yml @@ -0,0 +1,6 @@ +board: + name: xg28_rb4401c + full_name: EFR32xG28 868-915 MHz 20 dBm (xG28-RB4401C) + vendor: silabs + socs: + - name: efr32zg28b322f1024im68 diff --git a/boards/silabs/radio_boards/xg28_rb4401c/doc/efr32zg28-xg28-rb4401c.jpg b/boards/silabs/radio_boards/xg28_rb4401c/doc/efr32zg28-xg28-rb4401c.jpg new file mode 100644 index 0000000000000..f4b9282ff30b0 Binary files /dev/null and b/boards/silabs/radio_boards/xg28_rb4401c/doc/efr32zg28-xg28-rb4401c.jpg differ diff --git a/boards/silabs/radio_boards/xg28_rb4401c/doc/index.rst b/boards/silabs/radio_boards/xg28_rb4401c/doc/index.rst new file mode 100644 index 0000000000000..483251d2fe7e6 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/doc/index.rst @@ -0,0 +1,144 @@ +.. zephyr:board:: xg28_rb4401c + +Overview +******** + +The EFR32ZG28 Radio Board is the radio board delivered with +`xG28-PK6025A Website`_. It contains a Wireless System-On-Chip from the +EFR32ZG28 family built on an ARM Cortex®-M33 processor with excellent low +power capabilities. + +The BRD4401C a.k.a. xG28-RB4401C radio board plugs into the Wireless Pro Kit +Mainboard BRD4002A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32ZG28B322F1024IM68 SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1024 kB +- RAM: 256 kB +- Transmit power: up to +20 dBm +- Operation frequency: 868-915 MHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz). +- Silicon Labs Si7021 relative humidity and temperature sensor +- Low-power 128x128 pixel Memory LCD +- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) + +For more information about the EFR32ZG28 SoC and BRD4401C board, refer to these +documents: + +- `EFR32ZG28 Website`_ +- `EFR32ZG28 Datasheet`_ +- `EFR32xG28 Reference Manual`_ +- `XG28-PK6025A Website`_ +- `BRD4401C User Guide`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+--------------+-------------------------------------+ +| Name | Function | Usage | ++=======+==============+=====================================+ +| PA8 | UART_TX | UART Console TX | ++-------+--------------+-------------------------------------+ +| PA9 | UART_RX | UART Console RX | ++-------+--------------+-------------------------------------+ +| PB1 | GPIO | Push Button 0 | ++-------+--------------+-------------------------------------+ +| PB2 | GPIO | LED0 | ++-------+--------------+-------------------------------------+ +| PB3 | GPIO | Push Button 1 | ++-------+--------------+-------------------------------------+ +| PC1 | US1_TX | Display/Flash SPI MOSI | ++-------+--------------+-------------------------------------+ +| PC2 | US1_RX | Serial Flash MISO | ++-------+--------------+-------------------------------------+ +| PC3 | US1_CLK | Serial Flash/Display SPI Clock | ++-------+--------------+-------------------------------------+ +| PC4 | US1_CS | Serial Flash Chip Select | ++-------+--------------+-------------------------------------+ +| PC5 | I2C0_SCL | Si7021 I2C Clock | ++-------+--------------+-------------------------------------+ +| PC6 | GPIO | External COM Inversion Signal | ++-------+--------------+-------------------------------------+ +| PC7 | I2C0_SDA | Si7021 I2C Data | ++-------+--------------+-------------------------------------+ +| PC8 | US1_CS | Display Serial Chip Select | ++-------+--------------+-------------------------------------+ +| PC9 | GPIO | Display Control Access | ++-------+--------------+-------------------------------------+ +| PC11 | GPIO | Si7021 Enable | ++-------+--------------+-------------------------------------+ +| PD3 | GPIO | LED1 | ++-------+--------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c_defconfig` + +System Clock +============ + +The EFR32ZG28 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32ZG28 SoC has one USART and three EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Connect the BRD4002A board with a mounted BRD4401C radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg28_rb4401c + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! xg28_rb4401c/efr32zg28b322f1024im68 + + +.. _xG28-PK6025A Website: + https://www.silabs.com/development-tools/wireless/efr32xg28-pro-kit-20-dbm + +.. _BRD4401C User Guide: + https://www.silabs.com/documents/public/user-guides/ug535-xg28-20dbm-user-guide.pdf + +.. _EFR32ZG28 Website: + https://www.silabs.com/wireless/z-wave/efr32zg28-z-wave-800-socs + +.. _EFR32ZG28 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32zg28-datasheet.pdf + +.. _EFR32xG28 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg28-rm.pdf diff --git a/boards/silabs/radio_boards/xg28_rb4401c/pre_dt_board.cmake b/boards/silabs/radio_boards/xg28_rb4401c/pre_dt_board.cmake new file mode 100644 index 0000000000000..beb76b85552d1 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/xg28_rb4401c/support/openocd.cfg b/boards/silabs/radio_boards/xg28_rb4401c/support/openocd.cfg new file mode 100644 index 0000000000000..38409eb70ad79 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c-pinctrl.dtsi b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c-pinctrl.dtsi new file mode 100644 index 0000000000000..4a00ddebfe880 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c-pinctrl.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2025 Shontal Biton + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + eusart1_default: eusart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; + + timer0_default: timer0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; +}; diff --git a/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c.dts b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c.dts new file mode 100644 index 0000000000000..f39530d3aff40 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c.dts @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2025 Shontal Biton + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "xg28_rb4401c-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4401C"; + compatible = "silabs,xg28_rb4401c", "silabs,efr32zg28"; + + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart0; + zephyr,display = &ls0xx_ls013b7dh03; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart0; + }; + + aliases { + dht0 = &si7021; + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + + pwm_led1: pwm_led_1 { + pwms = <&timer0_pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + sensor_disp_enable: sensor_disp_enable { + compatible = "regulator-fixed"; + enable-gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + regulator-name = "sensor_disp_enable"; + status = "okay"; + }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <3 0 &gpioa 11 0>, + <4 0 &gpiod 7 0>, + <5 0 &gpioa 12 0>, + <6 0 &gpiod 8 0>, + <7 0 &gpioa 13 0>, + <8 0 &gpiod 9 0>, + <9 0 &gpioa 14 0>, + <10 0 &gpiod 10 0>, + <11 0 &gpiob 4 0>, + <12 0 &gpiod 11 0>, + <13 0 &gpiob 5 0>, + <14 0 &gpiod 12 0>, + <15 0 &gpioc 5 0>, + <16 0 &gpioc 7 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; +}; + +&bt_hci_silabs { + status = "okay"; +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <100>; + status = "okay"; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&eusart1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + cs-gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>, <&gpioc 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + ls0xx_ls013b7dh03: ls0xx@0 { + compatible = "sharp,ls0xx"; + reg = <0>; + disp-en-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; + extcomin-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; + extcomin-frequency = <60>; + height = <128>; + width = <128>; + spi-max-frequency = ; + }; + + mx25r80: mx25r8035f@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + dpd-wakeup-sequence = <30000 20 35000>; + has-dpd; + jedec-id = [c2 28 14]; + mxicy,mx25r-power-mode = "low-power"; + size = ; + spi-max-frequency = ; + t-enter-dpd = <0>; + }; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + si7021: si7021@40 { + compatible = "silabs,si7006"; + reg = <0x40>; + vin-supply = <&sensor_disp_enable>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&hfxo { + ctune = <115>; + precision = <50>; + status = "okay"; +}; + +&lfxo { + ctune = <44>; + precision = <50>; + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + reg = <0x0 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 472 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(472)>; + label = "image-0"; + }; + + /* Reserve 472 kB for the application in slot 1 */ + slot1_partition: partition@82000 { + reg = <0x00082000 DT_SIZE_K(472)>; + label = "image-1"; + }; + + /* Set 32 kB of storage at the end of the 1024 kB of flash */ + storage_partition: partition@f8000 { + reg = <0x000f8000 DT_SIZE_K(32)>; + label = "storage"; + }; + }; +}; diff --git a/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c.yaml b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c.yaml new file mode 100644 index 0000000000000..516d1dccdf550 --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c.yaml @@ -0,0 +1,28 @@ +identifier: xg28_rb4401c +name: EFR32xG28 868-915 MHz 20 dBm Radio Board (xG28-RB4401C, BRD4401C) +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - clock_control + - comparator + - counter + - dma + - entropy + - flash + - gpio + - i2c + - led + - pinctrl + - pwm + - spi + - uart + - watchdog +testing: + ignore_tags: + - pm +vendor: silabs diff --git a/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c_defconfig b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c_defconfig new file mode 100644 index 0000000000000..e70f8f5c5197d --- /dev/null +++ b/boards/silabs/radio_boards/xg28_rb4401c/xg28_rb4401c_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.dts b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.dts index 5bec1cebd87b3..15beeca3a2eca 100644 --- a/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.dts +++ b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.dts @@ -34,6 +34,7 @@ sw0 = &button0; sw1 = &button1; watchdog0 = &wdog0; + dht0 = &si7021; }; leds { @@ -79,6 +80,24 @@ enable-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; regulator-name = "sensor_enable"; }; + + exp_header: exp-header { + compatible = "silabs,exp-header"; + #gpio-cells = <2>; + gpio-map = <4 0 &gpioc 0 0>, + <6 0 &gpioc 1 0>, + <7 0 &gpiob 0 0>, + <8 0 &gpioc 2 0>, + <9 0 &gpiob 1 0>, + <10 0 &gpioc 3 0>, + <12 0 &gpioa 5 0>, + <13 0 &gpioa 8 0>, + <14 0 &gpioa 6 0>, + <15 0 &gpiob 2 0>, + <16 0 &gpiob 3 0>; + gpio-map-mask = <0xffffffff 0x0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + }; }; &cpu0 { @@ -144,6 +163,7 @@ si7021: si7021@40 { compatible = "silabs,si7006"; reg = <0x40>; + vin-supply = <&sensor_enable>; }; }; diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts index 92838847f9097..975f24f74b4f3 100644 --- a/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts +++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts @@ -30,6 +30,15 @@ watchdog0 = &wdog0; }; + /* GPIOs that power up different sensors */ + sensor_enable: sensor-enable { + compatible = "regulator-fixed"; + regulator-name = "sensor_enable"; + enable-gpios = <&gpiob 3 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + startup-delay-us = <100000>; + }; + leds { compatible = "gpio-leds"; @@ -100,6 +109,12 @@ pinctrl-0 = <&i2c2_default>; pinctrl-names = "default"; status = "okay"; + + si7210: si7210@30 { + compatible = "silabs,si7210"; + reg = <0x30>; + vin-supply = <&sensor_enable>; + }; }; &rtcc0 { diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig b/boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig index 76b773c1f7c16..61cef12c99236 100644 --- a/boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig +++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig @@ -9,3 +9,4 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000 CONFIG_CMU_HFCLK_HFRCO=y +CONFIG_REGULATOR=y diff --git a/boards/snps/em_starterkit/doc/index.rst b/boards/snps/em_starterkit/doc/index.rst index cbb669a573636..372b61bc43827 100644 --- a/boards/snps/em_starterkit/doc/index.rst +++ b/boards/snps/em_starterkit/doc/index.rst @@ -310,6 +310,6 @@ References .. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules -.. _Putty website: http://www.putty.org +.. _Putty website: https://www.putty.software .. _ARC EM Starter Kit User Guide: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit diff --git a/boards/snps/emsdp/doc/index.rst b/boards/snps/emsdp/doc/index.rst index d880a6ad6da70..eb2b143cce165 100644 --- a/boards/snps/emsdp/doc/index.rst +++ b/boards/snps/emsdp/doc/index.rst @@ -86,7 +86,7 @@ MISO with MOSI, DW SPI register is configured to internally connect them. This t use two different speed to verify data transfer with asynchronous functionality. Note: DW SPI only available on SPI0 and SPI1. -``samples/drivers/spi_flash``: Verfiy DW SPI and SPI-FLASH on SPI1. First erase the +``samples/drivers/spi_flash``: Verify DW SPI and SPI-FLASH on SPI1. First erase the whole flash then write 4 byte data to the flash. Read from the flash and compare the result with buffer to check functionality. @@ -278,4 +278,4 @@ References http://store.digilentinc.com/pmod-modules .. _Putty website: - http://www.putty.org + https://www.putty.software diff --git a/boards/snps/hsdk/doc/index.rst b/boards/snps/hsdk/doc/index.rst index 9e5dee7556c60..c41bb517a87bc 100644 --- a/boards/snps/hsdk/doc/index.rst +++ b/boards/snps/hsdk/doc/index.rst @@ -521,4 +521,4 @@ References .. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules -.. _Putty website: http://www.putty.org +.. _Putty website: https://www.putty.software diff --git a/boards/snps/hsdk/hsdk.dtsi b/boards/snps/hsdk/hsdk.dtsi index 55b2fb82cffdb..2a21d9a107ad5 100644 --- a/boards/snps/hsdk/hsdk.dtsi +++ b/boards/snps/hsdk/hsdk.dtsi @@ -7,6 +7,7 @@ /dts-v1/; #include +#include / { @@ -49,28 +50,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &cy8c95xx_port0 2 0>, /* A0 */ - <1 0 &cy8c95xx_port0 3 0>, /* A1 */ - <2 0 &cy8c95xx_port0 4 0>, /* A2 */ - <3 0 &cy8c95xx_port0 5 0>, /* A3 */ - <4 0 &gpio0 18 0>, /* A4 */ - <5 0 &gpio0 19 0>, /* A5 */ - <6 0 &gpio0 23 0>, /* D0 */ - <7 0 &gpio0 22 0>, /* D1 */ - <8 0 &gpio0 16 0>, /* D2 */ - <9 0 &gpio0 17 0>, /* D3 */ - <10 0 &gpio0 11 0>, /* D4 */ - <11 0 &gpio0 9 0>, /* D5 */ - <12 0 &gpio0 21 0>, /* D6 */ - <13 0 &gpio0 20 0>, /* D7 */ - <14 0 &gpio0 10 0>, /* D8 */ - <15 0 &gpio0 8 0>, /* D9 */ - <16 0 &gpio0 12 0>, /* D10 */ - <17 0 &gpio0 13 0>, /* D11 */ - <18 0 &gpio0 14 0>, /* D12 */ - <19 0 &gpio0 15 0>, /* D13 */ - <20 0 &gpio0 18 0>, /* D14 */ - <21 0 &gpio0 19 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/snps/hsdk4xd/doc/index.rst b/boards/snps/hsdk4xd/doc/index.rst index 52e88da142a41..2e45e3dff118a 100644 --- a/boards/snps/hsdk4xd/doc/index.rst +++ b/boards/snps/hsdk4xd/doc/index.rst @@ -550,4 +550,4 @@ References .. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules -.. _Putty website: http://www.putty.org +.. _Putty website: https://www.putty.software diff --git a/boards/snps/iotdk/doc/index.rst b/boards/snps/iotdk/doc/index.rst index d038451dd05b0..8d23a3746c41b 100644 --- a/boards/snps/iotdk/doc/index.rst +++ b/boards/snps/iotdk/doc/index.rst @@ -192,4 +192,4 @@ References .. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules -.. _Putty website: http://www.putty.org +.. _Putty website: https://www.putty.software diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/CMakeLists.txt b/boards/sparkfun/thing_plus_matter_mgm240p/CMakeLists.txt deleted file mode 100644 index ca93e65ac913a..0000000000000 --- a/boards/sparkfun/thing_plus_matter_mgm240p/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_UART_GECKO) - zephyr_library() - zephyr_library_sources(board.c) -endif() diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig deleted file mode 100644 index 826ce000afd36..0000000000000 --- a/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPARKFUN THING PLUS MGM240P board - -# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. -# Copyright (c) 2022, Silicon Labs -# SPDX-License-Identifier: Apache-2.0 - -module = BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/board.c b/boards/sparkfun/thing_plus_matter_mgm240p/board.c deleted file mode 100644 index beb2b540294f3..0000000000000 --- a/boards/sparkfun/thing_plus_matter_mgm240p/board.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. - * Copyright (c) 2021 Sateesh Kotapati - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -LOG_MODULE_REGISTER(sparkfun_thing_plus_mgm240p, -CONFIG_BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P_LOG_LEVEL); - -static int sparkfun_thing_plus_mgm240p_init(void) -{ - int ret; - - static struct gpio_dt_spec wake_up_gpio_dev = - GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); - - - if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { - LOG_ERR("Wake-up GPIO device was not found!\n"); - return -ENODEV; - } - ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); - if (ret < 0) { - return ret; - } - - return 0; -} - -/* needs to be done after GPIO driver init */ -SYS_INIT(sparkfun_thing_plus_mgm240p_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/sparkfun/thing_plus_matter_mgm240p/dts/bindings/silabs,gecko-wake-up-trigger.yaml deleted file mode 100644 index ba8892f2ce0b2..0000000000000 --- a/boards/sparkfun/thing_plus_matter_mgm240p/dts/bindings/silabs,gecko-wake-up-trigger.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -description: GPIO Wake Up Trigger for EFR32MG24 - -compatible: "silabs,gecko-wake-up-trigger" - -include: base.yaml - -properties: - gpios: - type: phandle-array - required: true - description: | - GPIO used as wake up trigger from EM4 sleep diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts index 084a2d344b6fe..21724fa4be594 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts @@ -49,11 +49,6 @@ label = "blue"; }; }; - - wake_up_trigger: gpio-wake-up { - compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - }; }; &timer0 { diff --git a/boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi b/boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi index 085c7292febfc..25b3b81851645 100644 --- a/boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi +++ b/boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 5 0>, /* A0 */ - <1 0 &gpioc 4 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 2 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 1 0>, /* D0 */ - <7 0 &gpioa 0 0>, /* D1 */ - <8 0 &gpiod 14 0>, /* D2 */ - <9 0 &gpiob 0 0>, /* D3 */ - <10 0 &gpioa 3 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 1 0>, /* D6 */ - <13 0 &gpioa 4 0>, /* D7 */ - <14 0 &gpiob 2 0>, /* D8 */ - <15 0 &gpioa 15 0>, /* D9 */ - <16 0 &gpioa 2 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi b/boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi index fee1444d4059b..50ecffa6b50c4 100644 --- a/boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi +++ b/boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0 */ - <1 0 &gpioc 2 0>, /* A1 */ - <2 0 &gpioc 4 0>, /* A2 */ - <3 0 &gpioc 5 0>, /* A3 */ - <4 0 &gpioa 7 0>, /* A4 */ - <5 0 &gpiob 0 0>, /* A5 */ - <6 0 &gpiod 8 0>, /* D0 */ - <7 0 &gpiod 9 0>, /* D1 */ - <8 0 &gpiod 15 0>, /* D2 */ - <9 0 &gpiob 2 0>, /* D3 */ - <10 0 &gpioe 7 0>, /* D4 */ - <11 0 &gpioe 0 0>, /* D5 */ - <12 0 &gpiob 6 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpioc 1 0>, /* D8 */ - <15 0 &gpioa 8 0>, /* D9 */ - <16 0 &gpioe 12 0>, /* D10 */ - <17 0 &gpioe 15 0>, /* D11 */ - <18 0 &gpioe 14 0>, /* D12 */ - <19 0 &gpioe 13 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi index db1efe1ad36e7..f3713d9c5c6e8 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi @@ -146,16 +146,6 @@ stm32_lp_tick_source: &lptim1 { data-rate = ; four-byte-opcodes; status = "okay"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x00000000 DT_SIZE_M(64)>; - }; - }; }; }; diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts index fc824417d2050..cef7e05831fda 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts @@ -76,6 +76,18 @@ }; }; +&mx25lm51245 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; +}; + &gpdma1 { status = "okay"; }; diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts index 04e24e714947e..997fcd2133e66 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts @@ -34,44 +34,59 @@ /* * Following flash partition is compatible with requirements - * given in TFM configuration given for current board. - * It might require adjustment depending on evolutions on TFM. + * given in TF-M configuration given for current board. + * + * It might require adjustment depending on evolutions on TF-M. */ - boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(224)>; + reg = <0x00000000 DT_SIZE_K(384)>; read-only; }; /* Secure image primary slot */ - slot0_partition: partition@38000 { + slot0_partition: partition@60000 { label = "image-0"; - reg = <0x00038000 DT_SIZE_K(384)>; + reg = <0x00060000 DT_SIZE_K(512)>; }; /* Non-secure image primary slot */ - slot0_ns_partition: partition@98000 { + slot0_ns_partition: partition@e0000 { label = "image-0-nonsecure"; - reg = <0x00098000 DT_SIZE_K(512)>; + reg = <0x000e0000 DT_SIZE_K(1024)>; + }; + + /* Internal Non Volatile Storage */ + storage_partition: partition@1e0000 { + label = "storage"; + reg = <0x001e0000 DT_SIZE_K(128)>; }; + }; +}; + +&mx25lm51245 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - /* Secure image secondary slot */ - slot1_partition: partition@118000 { + /* + * The flash partition (0 and 1) are aligned + * with the TF-M flash layout expectation. + */ + slot1_partition: partition@0 { label = "image-1"; - reg = <0x00118000 DT_SIZE_K(384)>; + reg = <0x00000000 DT_SIZE_K(512)>; }; - /* Non-secure image secondary slot */ - slot1_ns_partition: partition@178000 { + slot1_ns_partition: partition@80000 { label = "image-1-nonsecure"; - reg = <0x00178000 DT_SIZE_K(512)>; + reg = <0x00080000 DT_SIZE_K(1024)>; }; - /* Applicative Non Volatile Storage */ - storage_partition: partition@1f8000 { - label = "storage"; - reg = <0x001f8000 DT_SIZE_K(16)>; + external_partition: partition@180000 { + label = "external"; + reg = <0x00180000 (DT_SIZE_M(64) - DT_SIZE_K(1024) - DT_SIZE_K(512))>; }; }; }; diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst index 7f1e812c89c35..07e12f76eec58 100644 --- a/boards/st/b_u585i_iot02a/doc/index.rst +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -306,7 +306,7 @@ To disable TrustZone, it's necessary to change AT THE SAME TIME the ``TZEN`` and ``RDP`` bits. ``TZEN`` needs to get set from 1 to 0 and ``RDP``, needs to be set from ``DC`` to ``AA`` (step 3 below). -This is docummented in the `AN5347, in section 9`_, "TrustZone deactivation". +This is documented in the `AN5347, in section 9`_, "TrustZone deactivation". However, it's possible that the ``RDP`` bit is not yet set to ``DC``, so you first need to set it to ``DC`` (step 2). diff --git a/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi index 05228c5ccb807..88ac36c452ac0 100644 --- a/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi +++ b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 5 0>, /* A0 */ - <1 0 &gpioc 4 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 2 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 1 0>, /* D0 */ - <7 0 &gpioa 0 0>, /* D1 */ - <8 0 &gpiod 14 0>, /* D2 */ - <9 0 &gpiob 0 0>, /* D3 */ - <10 0 &gpioa 3 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 1 0>, /* D6 */ - <13 0 &gpioa 4 0>, /* D7 */ - <14 0 &gpiob 2 0>, /* D8 */ - <15 0 &gpioa 15 0>, /* D9 */ - <16 0 &gpioa 2 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_c031c6/arduino_r3_connector.dtsi b/boards/st/nucleo_c031c6/arduino_r3_connector.dtsi index aa818d839de24..cc5d41a372314 100644 --- a/boards/st/nucleo_c031c6/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_c031c6/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioa 11 0>, /* A4 */ - <5 0 &gpioa 12 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 10 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 5 0>, /* D6 */ - <13 0 &gpioa 15 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 0 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_c071rb/arduino_r3_connector.dtsi b/boards/st/nucleo_c071rb/arduino_r3_connector.dtsi index 5d62471e418aa..106912db51a6d 100644 --- a/boards/st/nucleo_c071rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_c071rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpioc 7 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpioc 8 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpiob 3 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.dts b/boards/st/nucleo_c071rb/nucleo_c071rb.dts index a13d0d90a063c..924570078740c 100644 --- a/boards/st/nucleo_c071rb/nucleo_c071rb.dts +++ b/boards/st/nucleo_c071rb/nucleo_c071rb.dts @@ -150,7 +150,7 @@ pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1 &adc1_in4_pa4>; pinctrl-names = "default"; st,adc-clock-source = "ASYNC"; - clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>, + clocks = <&rcc STM32_CLOCK(APB1_2, 20)>, <&rcc STM32_SRC_HSI ADC_SEL(2)>; st,adc-prescaler = <4>; status = "okay"; diff --git a/boards/st/nucleo_c092rc/arduino_r3_connector.dtsi b/boards/st/nucleo_c092rc/arduino_r3_connector.dtsi index 434823b1fe273..329bcf4e50390 100644 --- a/boards/st/nucleo_c092rc/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_c092rc/arduino_r3_connector.dtsi @@ -5,34 +5,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpioc 7 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpioc 8 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpiob 3 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f030r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f030r8/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_f030r8/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f030r8/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f070rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f070rb/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_f070rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f070rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f072rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f072rb/arduino_r3_connector.dtsi index 6ed2b49ad15f0..ae2f1d74d3afc 100644 --- a/boards/st/nucleo_f072rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f072rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f091rc/arduino_r3_connector.dtsi b/boards/st/nucleo_f091rc/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_f091rc/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f091rc/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f103rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f103rb/arduino_r3_connector.dtsi index 3e887efebe270..65db82a37c683 100644 --- a/boards/st/nucleo_f103rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f103rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f207zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f207zg/arduino_r3_connector.dtsi index 78c39b2d0c04b..ba1d3bb37cf5f 100644 --- a/boards/st/nucleo_f207zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f207zg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f302r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f302r8/arduino_r3_connector.dtsi index e2776a903b24a..0481e93afdae5 100644 --- a/boards/st/nucleo_f302r8/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f302r8/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpiob 13 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f303re/arduino_r3_connector.dtsi b/boards/st/nucleo_f303re/arduino_r3_connector.dtsi index 115b0a2187a64..bce87033b020f 100644 --- a/boards/st/nucleo_f303re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f303re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpiob 13 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f334r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f334r8/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_f334r8/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f334r8/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f401re/arduino_r3_connector.dtsi b/boards/st/nucleo_f401re/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_f401re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f401re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f410rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f410rb/arduino_r3_connector.dtsi index 94c46e664d7f6..3010a12f7ccd9 100644 --- a/boards/st/nucleo_f410rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f410rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f411re/arduino_r3_connector.dtsi b/boards/st/nucleo_f411re/arduino_r3_connector.dtsi index 9145f689fd7bb..997613ecd3f81 100644 --- a/boards/st/nucleo_f411re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f411re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f412zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f412zg/arduino_r3_connector.dtsi index b02c83fc6533a..be84156e6c74e 100644 --- a/boards/st/nucleo_f412zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f412zg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 1 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f413zh/arduino_r3_connector.dtsi b/boards/st/nucleo_f413zh/arduino_r3_connector.dtsi index b02c83fc6533a..be84156e6c74e 100644 --- a/boards/st/nucleo_f413zh/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f413zh/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 1 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f429zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f429zi/arduino_r3_connector.dtsi index 067c3c6c67654..6b18d2aaa2e06 100644 --- a/boards/st/nucleo_f429zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f429zi/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f439zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f439zi/arduino_r3_connector.dtsi index 067c3c6c67654..6b18d2aaa2e06 100644 --- a/boards/st/nucleo_f439zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f439zi/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f446re/arduino_r3_connector.dtsi b/boards/st/nucleo_f446re/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_f446re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f446re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f446ze/arduino_r3_connector.dtsi b/boards/st/nucleo_f446ze/arduino_r3_connector.dtsi index f65a31b66272b..58beb26cbd692 100644 --- a/boards/st/nucleo_f446ze/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f446ze/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f722ze/arduino_r3_connector.dtsi b/boards/st/nucleo_f722ze/arduino_r3_connector.dtsi index 9072fa9147676..52012fb5d9b68 100644 --- a/boards/st/nucleo_f722ze/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f722ze/arduino_r3_connector.dtsi @@ -5,34 +5,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f746zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f746zg/arduino_r3_connector.dtsi index 43a03a7ab80d9..02938702f5a4f 100644 --- a/boards/st/nucleo_f746zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f746zg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f756zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f756zg/arduino_r3_connector.dtsi index 43a03a7ab80d9..02938702f5a4f 100644 --- a/boards/st/nucleo_f756zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f756zg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_f767zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f767zi/arduino_r3_connector.dtsi index 43a03a7ab80d9..02938702f5a4f 100644 --- a/boards/st/nucleo_f767zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_f767zi/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 3 0>, /* A3 */ - <4 0 &gpiof 5 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_g070rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g070rb/arduino_r3_connector.dtsi index eff3e1b300eec..846015b44420b 100644 --- a/boards/st/nucleo_g070rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_g070rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpiob 11 0>, /* A4 */ - <5 0 &gpiob 12 0>, /* A5 */ - <6 0 &gpioc 5 0>, /* D0 */ - <7 0 &gpioc 4 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 14 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 0 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_g071rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g071rb/arduino_r3_connector.dtsi index d618efc712fd1..6da07b55a0519 100644 --- a/boards/st/nucleo_g071rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_g071rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpiob 11 0>, /* A4 */ - <5 0 &gpiob 12 0>, /* A5 */ - <6 0 &gpioc 5 0>, /* D0 */ - <7 0 &gpioc 4 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 14 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 0 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi b/boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi index d618efc712fd1..6da07b55a0519 100644 --- a/boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpiob 11 0>, /* A4 */ - <5 0 &gpiob 12 0>, /* A5 */ - <6 0 &gpioc 5 0>, /* D0 */ - <7 0 &gpioc 4 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 14 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 0 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi index f83f6bf265809..724c4261b33b6 100644 --- a/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioc 5 0>, /* D0 */ - <7 0 &gpioc 4 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_g474re/arduino_r3_connector.dtsi b/boards/st/nucleo_g474re/arduino_r3_connector.dtsi index 0b96e6c9a80b0..1207cf9fc590f 100644 --- a/boards/st/nucleo_g474re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_g474re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioc 5 0>, /* D0 */ - <7 0 &gpioc 4 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi b/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi index 6a25cd476c534..6bb51a652a23b 100644 --- a/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 2 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpiob 15 0>, /* D0 */ - <7 0 &gpiob 14 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioc 7 0>, /* D8 */ - <15 0 &gpioc 6 0>, /* D9 */ - <16 0 &gpioc 9 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h533re/arduino_r3_connector.dtsi b/boards/st/nucleo_h533re/arduino_r3_connector.dtsi index 7e2ca9b705c8e..1a3726adddc47 100644 --- a/boards/st/nucleo_h533re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h533re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpiob 1 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpiob 15 0>, /* D0 */ - <7 0 &gpiob 14 0>, /* D1 */ - <8 0 &gpioc 8 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioc 7 0>, /* D8 */ - <15 0 &gpioc 6 0>, /* D9 */ - <16 0 &gpioc 9 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi index fa2515d6d0b72..8db1ee574beef 100644 --- a/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi @@ -5,34 +5,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 6 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpiof 11 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 14 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpioe 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiog 12 0>, /* D7 */ - <14 0 &gpiof 3 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiog 9 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi index 12f4f74dd25eb..6e3b812067bb4 100644 --- a/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi @@ -3,34 +3,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 14 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpioe 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiog 12 0>, /* D7 */ - <14 0 &gpiof 3 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi index e9107b9adb9b9..b949683bfad27 100644 --- a/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi @@ -5,34 +5,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 14 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpioe 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiog 12 0>, /* D7 */ - <14 0 &gpiof 3 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi index 0d39ecdd33f1f..cc0acccb15ea1 100644 --- a/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpiof 11 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 14 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpioe 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioa 8 0>, /* D6 */ - <13 0 &gpiog 12 0>, /* D7 */ - <14 0 &gpiog 9 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi index 8af74373f23fa..d1417a2a4fdd0 100644 --- a/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpiof 10 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 14 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpioe 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiog 12 0>, /* D7 */ - <14 0 &gpiof 3 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi index 1b1bf1877932f..be7dd37d49613 100644 --- a/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h755zi_q/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpiof 11 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 14 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpioe 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioa 8 0>, /* D6 */ - <13 0 &gpiog 12 0>, /* D7 */ - <14 0 &gpiog 9 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi index babe33781a474..7a2b818fa3539 100644 --- a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi +++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q.dtsi @@ -13,7 +13,7 @@ compatible = "gpio-leds"; green_led: led_1 { - gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>; label = "User LD1"; }; diff --git a/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi index d56a9f4e58557..bda9a444f279e 100644 --- a/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpiof 11 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 14 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpioe 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioa 8 0>, /* D6 */ - <13 0 &gpiog 12 0>, /* D7 */ - <14 0 &gpiog 9 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_h7s3l8/arduino_r3_connector.dtsi b/boards/st/nucleo_h7s3l8/arduino_r3_connector.dtsi index 13e390200fd43..5941937048b2c 100644 --- a/boards/st/nucleo_h7s3l8/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h7s3l8/arduino_r3_connector.dtsi @@ -3,34 +3,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 4 0>, /* A3 */ - <4 0 &gpioc 5 0>, /* A4 */ - <5 0 &gpiof 11 0>, /* A5 */ - <6 0 &gpioa 10 0>, /* D0 */ - <7 0 &gpiob 14 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 3 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 4 0>, /* D7 */ - <14 0 &gpiof 5 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l053r8/arduino_r3_connector.dtsi b/boards/st/nucleo_l053r8/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_l053r8/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l053r8/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l073rz/arduino_r3_connector.dtsi b/boards/st/nucleo_l073rz/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_l073rz/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l073rz/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l152re/arduino_r3_connector.dtsi b/boards/st/nucleo_l152re/arduino_r3_connector.dtsi index e1ee1ae0bb211..6751c2f15e633 100644 --- a/boards/st/nucleo_l152re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l152re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi b/boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi index fa15a370388ca..0d6d901ecb21c 100644 --- a/boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 2 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 12 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpioa 15 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioc 7 0>, /* D7 */ - <14 0 &gpiob 6 0>, /* D8 */ - <15 0 &gpioa 8 0>, /* D9 */ - <16 0 &gpioa 11 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpiob 13 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l432kc/arduino_nano_connector.dtsi b/boards/st/nucleo_l432kc/arduino_nano_connector.dtsi new file mode 100644 index 0000000000000..efcf317f4522e --- /dev/null +++ b/boards/st/nucleo_l432kc/arduino_nano_connector.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022 Joylab AG + * Copyright (c) 2025 Tomas Jurena + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_header: connector { + compatible = "arduino-nano-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , /* D0 */ + , /* D1 */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 */ + , /* D9 */ + , /* D10 */ + , /* D11 */ + , /* D12 */ + , /* D13 */ + , /* D14 / A0 */ + , /* D15 / A1 */ + , /* D16 / A2 */ + , /* D17 / A3 */ + , /* D18 / A4 */ + , /* D19 / A5 */ + , /* D20 / A6 */ + ; /* D21 / A7 */ + }; +}; + +arduino_spi: &spi1 {}; +arduino_serial: &usart1 {}; +arduino_i2c: &i2c1 {}; diff --git a/boards/st/nucleo_l432kc/nucleo_l432kc.dts b/boards/st/nucleo_l432kc/nucleo_l432kc.dts index 1d8b4647a4157..b94be61c1bf22 100644 --- a/boards/st/nucleo_l432kc/nucleo_l432kc.dts +++ b/boards/st/nucleo_l432kc/nucleo_l432kc.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include +#include "arduino_nano_connector.dtsi" / { model = "STMicroelectronics STM32L432KC-NUCLEO board"; diff --git a/boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi b/boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi index ee1da1d802d2b..481b1ad921a7a 100644 --- a/boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 2 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 12 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpioa 15 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioc 7 0>, /* D7 */ - <14 0 &gpiob 6 0>, /* D8 */ - <15 0 &gpioa 8 0>, /* D9 */ - <16 0 &gpioa 11 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpiob 13 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l452re/arduino_r3_connector.dtsi b/boards/st/nucleo_l452re/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_l452re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l452re/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l476rg/arduino_r3_connector.dtsi b/boards/st/nucleo_l476rg/arduino_r3_connector.dtsi index bccf9e6206ff6..022aff34590bf 100644 --- a/boards/st/nucleo_l476rg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l476rg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l476rg/nucleo_l476rg.dts b/boards/st/nucleo_l476rg/nucleo_l476rg.dts index 34c802047d624..20314275c808f 100644 --- a/boards/st/nucleo_l476rg/nucleo_l476rg.dts +++ b/boards/st/nucleo_l476rg/nucleo_l476rg.dts @@ -199,7 +199,7 @@ stm32_lp_tick_source: &lptim1 { &rng { /* Change clock source to avoid using MSI */ - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>; status = "okay"; }; diff --git a/boards/st/nucleo_l496zg/arduino_r3_connector.dtsi b/boards/st/nucleo_l496zg/arduino_r3_connector.dtsi index 8651d18ff0232..dca43921cdb75 100644 --- a/boards/st/nucleo_l496zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l496zg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 1 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiod 9 0>, /* D0 */ - <7 0 &gpiod 8 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi b/boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi index 5c246eee1f422..b76748208342c 100644 --- a/boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 1 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiod 9 0>, /* D0 */ - <7 0 &gpiod 8 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi b/boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi index ca0af63d0c581..9c51df4171183 100644 --- a/boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioc 0 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 1 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiod 9 0>, /* D0 */ - <7 0 &gpiod 8 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi b/boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi index d8a559c4e81a5..4e767d84153fb 100644 --- a/boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi @@ -4,33 +4,35 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioa 2 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpiod 9 0>, /* D0 */ - <7 0 &gpiod 8 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_n657x0_q/arduino_r3_connector.dtsi b/boards/st/nucleo_n657x0_q/arduino_r3_connector.dtsi index 3d452c84a643a..4b93a48fffef7 100644 --- a/boards/st/nucleo_n657x0_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_n657x0_q/arduino_r3_connector.dtsi @@ -3,34 +3,37 @@ * * SPDX-License-Identifier: Apache-2.0 */ + +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 8 0>, /* A0 */ - <1 0 &gpioa 9 0>, /* A1 */ - <2 0 &gpioa 10 0>, /* A2 */ - <3 0 &gpioa 12 0>, /* A3 */ - <4 0 &gpiof 3 0>, /* A4 */ - <5 0 &gpiog 15 0>, /* A5 */ - <6 0 &gpiod 9 0>, /* D0 */ - <7 0 &gpiod 8 0>, /* D1 */ - <8 0 &gpiod 0 0>, /* D2 */ - <9 0 &gpioe 9 0>, /* D3 */ - <10 0 &gpioe 0 0>, /* D4 */ - <11 0 &gpioe 10 0>, /* D5 */ - <12 0 &gpiod 5 0>, /* D6 */ - <13 0 &gpioe 11 0>, /* D7 */ - <14 0 &gpiod 12 0>, /* D8 */ - <15 0 &gpiod 7 0>, /* D9 */ - <16 0 &gpioa 3 0>, /* D10 */ - <17 0 &gpiog 2 0>, /* D11 */ - <18 0 &gpiog 1 0>, /* D12 */ - <19 0 &gpioe 15 0>, /* D13 */ - <20 0 &gpioc 1 0>, /* D14 */ - <21 0 &gpioh 9 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi index 7c4c4746bde89..8652b42aadcd5 100644 --- a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi +++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi @@ -97,12 +97,6 @@ status = "okay"; }; -&ic3 { - pll-src = <1>; - ic-div = <6>; - status = "okay"; -}; - &ic6 { pll-src = <3>; ic-div = <2>; @@ -231,7 +225,7 @@ zephyr_udc0: &usbotg_hs1 { &xspim_p2_io6_pn10 &xspim_p2_io7_pn11>; pinctrl-names = "default"; clocks = <&rcc STM32_CLOCK(AHB5, 12)>, - <&rcc STM32_SRC_IC3 XSPI1_SEL(2)>, + <&rcc STM32_SRC_HCLK5 XSPI2_SEL(0)>, <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; diff --git a/boards/st/nucleo_u031r8/arduino_r3_connector.dtsi b/boards/st/nucleo_u031r8/arduino_r3_connector.dtsi index 9dbbb45ec52b0..f655304d91c36 100644 --- a/boards/st/nucleo_u031r8/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_u031r8/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_u083rc/arduino_r3_connector.dtsi b/boards/st/nucleo_u083rc/arduino_r3_connector.dtsi index cb596a6c00a45..50bac8cbd7dbc 100644 --- a/boards/st/nucleo_u083rc/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_u083rc/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioa 10 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.dts b/boards/st/nucleo_u083rc/nucleo_u083rc.dts index cf29b8ef0115a..72944b504e127 100644 --- a/boards/st/nucleo_u083rc/nucleo_u083rc.dts +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.dts @@ -148,7 +148,7 @@ }; stm32_lp_tick_source: &lptim1 { - clocks = <&rcc STM32_CLOCK(APB1, 31U)>, + clocks = <&rcc STM32_CLOCK(APB1, 31)>, <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; status = "okay"; }; @@ -169,7 +169,7 @@ stm32_lp_tick_source: &lptim1 { }; &rng { - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 18)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>; status = "okay"; }; @@ -179,7 +179,7 @@ stm32_lp_tick_source: &lptim1 { }; zephyr_udc0: &usb { - clocks = <&rcc STM32_CLOCK(APB1, 13U)>, + clocks = <&rcc STM32_CLOCK(APB1, 13)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>; pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; pinctrl-names = "default"; @@ -187,7 +187,7 @@ zephyr_udc0: &usb { }; &rtc { - clocks = <&rcc STM32_CLOCK(APB1, 10U)>, + clocks = <&rcc STM32_CLOCK(APB1, 10)>, <&rcc STM32_SRC_LSE RTC_SEL(1)>; status = "okay"; }; diff --git a/boards/st/nucleo_u385rg_q/arduino_r3_connector.dtsi b/boards/st/nucleo_u385rg_q/arduino_r3_connector.dtsi index 355a479f5ecb1..c106a77fbc39d 100644 --- a/boards/st/nucleo_u385rg_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_u385rg_q/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioc 8 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioc 7 0>, /* D8 */ - <15 0 &gpioc 6 0>, /* D9 */ - <16 0 &gpioc 9 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi index 5c98bee856140..9f1b608831f9c 100644 --- a/boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioa 2 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpiog 8 0>, /* D0 */ - <7 0 &gpiog 7 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi b/boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi index be1a9c7abccca..84a9d8a1673f2 100644 --- a/boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 3 0>, /* A0 */ - <1 0 &gpioa 2 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpiog 8 0>, /* D0 */ - <7 0 &gpiog 7 0>, /* D1 */ - <8 0 &gpiof 15 0>, /* D2 */ - <9 0 &gpioe 13 0>, /* D3 */ - <10 0 &gpiof 14 0>, /* D4 */ - <11 0 &gpioe 11 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiof 13 0>, /* D7 */ - <14 0 &gpiof 12 0>, /* D8 */ - <15 0 &gpiod 15 0>, /* D9 */ - <16 0 &gpiod 14 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi b/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi index 7b61215ab7902..fb5e4639cc69b 100644 --- a/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; @@ -15,13 +17,13 @@ * connector in default hardware configuration. * Only the connected pins are provided here. */ - gpio-map = <14 0 &gpiob 15 0>, /* D8 */ - <16 0 &gpioa 9 0>, /* D10 */ - <17 0 &gpioa 11 0>, /* D11 */ - <18 0 &gpioa 8 0>, /* D12 */ - <19 0 &gpiob 3 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wb05kz/doc/index.rst b/boards/st/nucleo_wb05kz/doc/index.rst index 2f7cae97d0a1f..517340b073ec0 100644 --- a/boards/st/nucleo_wb05kz/doc/index.rst +++ b/boards/st/nucleo_wb05kz/doc/index.rst @@ -32,8 +32,8 @@ Supported Features .. zephyr:board-supported-hw:: -Bluetooh support ----------------- +Bluetooth support +----------------- BLE support is enabled; however, to build a Zephyr sample using this board, you first need to fetch the Bluetooth controller library into Zephyr as a binary BLOB. diff --git a/boards/st/nucleo_wb07cc/arduino_r3_connector.dtsi b/boards/st/nucleo_wb07cc/arduino_r3_connector.dtsi index 75cb81bccfe23..4c3001473bfed 100644 --- a/boards/st/nucleo_wb07cc/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wb07cc/arduino_r3_connector.dtsi @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; @@ -15,28 +17,28 @@ * connector in default hardware configuration. * Only the connected pins are provided here. */ - gpio-map = <0 0 &gpiob 3 0>, /* A0 */ - <1 0 &gpiob 1 0>, /* A1 */ - <2 0 &gpioa 15 0>, /* A2 */ - <3 0 &gpioa 12 0>, /* A3 */ - <4 0 &gpioa 14 0>, /* A4 */ - <5 0 &gpioa 13 0>, /* A5 */ - /* D0 - N/C (PA8 via SB9) */ - /* D1 - N/C (PA9 via SB7) */ - <8 0 &gpiob 15 0>, /* D2 */ - /* D3 - N/C (PA0 via SB3) */ - <10 0 &gpiob 11 0>, /* D4 */ - <11 0 &gpiob 14 0>, /* D5 */ - <12 0 &gpioa 11 0>, /* D6 */ - <13 0 &gpiob 10 0>, /* D7 */ - <14 0 &gpiob 8 0>, /* D8 */ - <15 0 &gpioa 1 0>, /* D9 */ - <16 0 &gpioa 4 0>, /* D10 */ - <17 0 &gpioa 6 0>, /* D11 */ - <18 0 &gpioa 7 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + /* D0 - N/C (PA8 via SB9) */ + /* D1 - N/C (PA9 via SB7) */ + , + /* D3 - N/C (PA0 via SB3) */ + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wb07cc/doc/index.rst b/boards/st/nucleo_wb07cc/doc/index.rst index de36f37eeb42a..08b39e9003dc8 100644 --- a/boards/st/nucleo_wb07cc/doc/index.rst +++ b/boards/st/nucleo_wb07cc/doc/index.rst @@ -32,8 +32,8 @@ Supported Features .. zephyr:board-supported-hw:: -Bluetooh support ----------------- +Bluetooth support +----------------- BLE support is enabled; however, to build a Zephyr sample using this board, you first need to fetch the Bluetooth controller library into Zephyr as a binary BLOB. diff --git a/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi b/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi index 7b61215ab7902..fb5e4639cc69b 100644 --- a/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; @@ -15,13 +17,13 @@ * connector in default hardware configuration. * Only the connected pins are provided here. */ - gpio-map = <14 0 &gpiob 15 0>, /* D8 */ - <16 0 &gpioa 9 0>, /* D10 */ - <17 0 &gpioa 11 0>, /* D11 */ - <18 0 &gpioa 8 0>, /* D12 */ - <19 0 &gpiob 3 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wb09ke/doc/index.rst b/boards/st/nucleo_wb09ke/doc/index.rst index 854e83c7ed8af..e8ac511a206fb 100644 --- a/boards/st/nucleo_wb09ke/doc/index.rst +++ b/boards/st/nucleo_wb09ke/doc/index.rst @@ -32,8 +32,8 @@ Supported Features .. zephyr:board-supported-hw:: -Bluetooh support ----------------- +Bluetooth support +----------------- BLE support is enabled; however, to build a Zephyr sample using this board, you first need to fetch the Bluetooth controller library into Zephyr as a binary BLOB. diff --git a/boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi b/boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi index 4edd8ac78908a..c796db3e8990a 100644 --- a/boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0 */ - <1 0 &gpioc 1 0>, /* A1 */ - <2 0 &gpioa 1 0>, /* A2 */ - <3 0 &gpioa 0 0>, /* A3 */ - <4 0 &gpioc 3 0>, /* A4 */ - <5 0 &gpioc 2 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioc 6 0>, /* D2 */ - <9 0 &gpioa 10 0>, /* D3 */ - <10 0 &gpioc 10 0>, /* D4 */ - <11 0 &gpioa 15 0>, /* D5 */ - <12 0 &gpioa 8 0>, /* D6 */ - <13 0 &gpioc 13 0>, /* D7 */ - <14 0 &gpioc 12 0>, /* D8 */ - <15 0 &gpioa 9 0>, /* D9 */ - <16 0 &gpioa 4 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi b/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi index 2c82c94d31b0f..763084eb2b973 100644 --- a/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 7 0>, /* A0 */ - <1 0 &gpioa 6 0>, /* A1 */ - <2 0 &gpioa 2 0>, /* A2 */ - <3 0 &gpioa 1 0>, /* A3 */ - <4 0 &gpioa 5 0>, /* A4 */ - <5 0 &gpioa 0 0>, /* A5 */ - <6 0 &gpioa 10 0>, /* D0 */ - <7 0 &gpiob 5 0>, /* D1 */ - <8 0 &gpiob 7 0>, /* D2 */ - <9 0 &gpiob 6 0>, /* D3 */ - <10 0 &gpioa 11 0>, /* D4 */ - <11 0 &gpiob 14 0>, /* D5 */ - <12 0 &gpiob 0 0>, /* D6 */ - <13 0 &gpiob 9 0>, /* D7 */ - <14 0 &gpiob 15 0>, /* D8 */ - <15 0 &gpioa 9 0>, /* D9 */ - <16 0 &gpioa 12 0>, /* D10 */ - <17 0 &gpioa 15 0>, /* D11 */ - <18 0 &gpiob 3 0>, /* D12 */ - <19 0 &gpiob 4 0>, /* D13 */ - <20 0 &gpiob 1 0>, /* D14 */ - <21 0 &gpiob 2 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst index c07b352f17f9f..a14076d8c4a6b 100644 --- a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst +++ b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst @@ -146,8 +146,8 @@ Supported Features .. zephyr:board-supported-hw:: -Bluetooh support ----------------- +Bluetooth support +----------------- BLE support is enabled on nucleo_wba55cg. To build a zephyr sample using this board you first need to install Bluetooth Controller libraries available in Zephyr as binary diff --git a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts index bd2fe2e4b92c4..5b52937e58e1e 100644 --- a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts @@ -90,17 +90,12 @@ }; }; -&clk_lsi { - status = "okay"; -}; - &clk_lse { status = "okay"; }; &clk_hse { status = "okay"; - hse-div2; }; &clk_hsi { @@ -109,9 +104,9 @@ &rcc { clocks = <&clk_hse>; - clock-frequency = ; + clock-frequency = ; /* Lowest value to manage radio events */ ahb-prescaler = <1>; - ahb5-prescaler = <2>; + ahb5-prescaler = <1>; apb1-prescaler = <1>; apb2-prescaler = <2>; apb7-prescaler = <1>; diff --git a/boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi b/boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi index 943e3e8617a07..3132640511a5c 100644 --- a/boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 4 0>, /* A0 */ - <1 0 &gpioa 6 0>, /* A1 */ - <2 0 &gpioa 2 0>, /* A2 */ - <3 0 &gpioa 1 0>, /* A3 */ - <4 0 &gpioa 5 0>, /* A4 */ - <5 0 &gpioa 0 0>, /* A5 */ - <6 0 &gpioa 11 0>, /* D0 */ - <7 0 &gpioa 12 0>, /* D1 */ - <8 0 &gpioe 0 0>, /* D2 */ - <9 0 &gpiob 13 0>, /* D3 */ - <10 0 &gpioa 3 0>, /* D4 */ - <11 0 &gpiob 14 0>, /* D5 */ - <12 0 &gpiob 0 0>, /* D6 */ - <13 0 &gpiod 14 0>, /* D7 */ - <14 0 &gpioa 10 0>, /* D8 */ - <15 0 &gpiob 11 0>, /* D9 */ - <16 0 &gpiob 9 0>, /* D10 */ - <17 0 &gpioc 3 0>, /* D11 */ - <18 0 &gpioa 9 0>, /* D12 */ - <19 0 &gpiob 10 0>, /* D13 */ - <20 0 &gpiob 1 0>, /* D14 */ - <21 0 &gpiob 2 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wba65ri/nucleo_wba65ri.dts b/boards/st/nucleo_wba65ri/nucleo_wba65ri.dts index a44e2f3ef5712..43089c26f7bf9 100644 --- a/boards/st/nucleo_wba65ri/nucleo_wba65ri.dts +++ b/boards/st/nucleo_wba65ri/nucleo_wba65ri.dts @@ -84,7 +84,6 @@ }; &clk_hse { - hse-div2; status = "okay"; }; @@ -94,9 +93,9 @@ &rcc { clocks = <&clk_hse>; - clock-frequency = ; + clock-frequency = ; /* Lowest value to manage radio events */ ahb-prescaler = <1>; - ahb5-prescaler = <2>; + ahb5-prescaler = <1>; apb1-prescaler = <1>; apb2-prescaler = <2>; apb7-prescaler = <1>; diff --git a/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi b/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi index 331817e0a4000..e6b2648f5285e 100644 --- a/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiob 1 0>, /* A0 */ - <1 0 &gpiob 2 0>, /* A1 */ - <2 0 &gpioa 10 0>, /* A2 */ - <3 0 &gpiob 4 0>, /* A3 */ - <4 0 &gpiob 14 0>, /* A4 */ - <5 0 &gpiob 13 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiob 12 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 8 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioc 1 0>, /* D7 */ - <14 0 &gpioc 2 0>, /* D8 */ - <15 0 &gpioa 9 0>, /* D9 */ - <16 0 &gpioa 4 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpioa 11 0>, /* D14 */ - <21 0 &gpioa 12 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts index 6f212ab3ad975..41ccd702d6eb1 100644 --- a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts +++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts @@ -36,7 +36,7 @@ label = "User LED2"; }; - green_led_3: led_2 { + red_led_3: led_2 { gpios = <&gpiob 11 GPIO_ACTIVE_HIGH>; label = "User LED3"; }; diff --git a/boards/st/sensortile_box/sensortile_box.dts b/boards/st/sensortile_box/sensortile_box.dts index c490c8859625c..a9e04463579d7 100644 --- a/boards/st/sensortile_box/sensortile_box.dts +++ b/boards/st/sensortile_box/sensortile_box.dts @@ -252,7 +252,7 @@ zephyr_udc0: &usbotg_fs { &rng { /* Change clock source to avoid using MSI */ - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>; status = "okay"; }; diff --git a/boards/st/stm32f411e_disco/doc/index.rst b/boards/st/stm32f411e_disco/doc/index.rst index 9c7f25ec56a38..efa5b7717fc13 100644 --- a/boards/st/stm32f411e_disco/doc/index.rst +++ b/boards/st/stm32f411e_disco/doc/index.rst @@ -77,6 +77,7 @@ Default Zephyr Peripheral Mapping: - LD4 : PD12 (PWM4 CH1) - LD5 : PD14 (PWM4 CH3) - LD6 : PD15 (PWM4 CH4) +- SPI1: PE3, PA5, PA6, PA7 (CS, SCK, MISO, MOSI) System Clock ============ diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco.dts b/boards/st/stm32f411e_disco/stm32f411e_disco.dts index 6aad31d2af761..818415177da44 100644 --- a/boards/st/stm32f411e_disco/stm32f411e_disco.dts +++ b/boards/st/stm32f411e_disco/stm32f411e_disco.dts @@ -88,6 +88,7 @@ pwm-led3 = &blue_pwm_led; magn0 = &lsm303agr_magn; accel0 = &lsm303agr_accel; + gyro0 = &i3g4250d; mcuboot-button0 = &user_button; mcuboot-led0 = &orange_led_3; die-temp0 = &die_temp; @@ -158,6 +159,19 @@ }; }; +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpioe 3 GPIO_ACTIVE_LOW>; + + i3g4250d: i3g4250d@0 { + compatible = "st,i3g4250d"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + &usart2 { pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; pinctrl-names = "default"; diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay index ea392d6ebefbb..ae75ab7e58a50 100644 --- a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay +++ b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay @@ -8,6 +8,7 @@ aliases { /delete-property/ magn0; accel0 = &lsm303dlhc_accel; + /delete-property/ gyro0; }; }; @@ -29,3 +30,8 @@ <&gpioe 5 GPIO_ACTIVE_HIGH>; }; }; + +/* The B revision has the l3gd20 instead of i3g4250d, but no test board is available. */ +&spi1 { + /delete-node/ i3g4250d@0; +}; diff --git a/boards/st/stm32f412g_disco/arduino_r3_connector.dtsi b/boards/st/stm32f412g_disco/arduino_r3_connector.dtsi index 9e70b69a5a378..99eeddca88cc1 100644 --- a/boards/st/stm32f412g_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32f412g_disco/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 1 0>, /* A0 */ - <1 0 &gpioc 1 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 4 0>, /* A3 */ - <4 0 &gpioc 5 0>, /* A4 */ - <5 0 &gpiob 0 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiog 13 0>, /* D2 */ - <9 0 &gpiof 4 0>, /* D3 */ - <10 0 &gpiog 12 0>, /* D4 */ - <11 0 &gpiof 10 0>, /* D5 */ - <12 0 &gpiof 3 0>, /* D6 */ - <13 0 &gpiog 11 0>, /* D7 */ - <14 0 &gpiog 10 0>, /* D8 */ - <15 0 &gpiob 8 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 10 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32f413h_disco/arduino_r3_connector.dtsi b/boards/st/stm32f413h_disco/arduino_r3_connector.dtsi index 1a5a2bc468ce9..94267ab27f967 100644 --- a/boards/st/stm32f413h_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32f413h_disco/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 2 0>, /* A2 */ - <3 0 &gpioa 5 0>, /* A3 */ - <4 0 &gpiob 1 0>, /* A4 */ - <5 0 &gpioc 4 0>, /* A5 */ - <6 0 &gpiof 6 0>, /* D0 */ - <7 0 &gpiof 7 0>, /* D1 */ - <8 0 &gpiog 13 0>, /* D2 */ - <9 0 &gpiof 10 0>, /* D3 */ - <10 0 &gpiob 6 0>, /* D4 */ - <11 0 &gpioe 6 0>, /* D5 */ - <12 0 &gpiob 0 0>, /* D6 */ - <13 0 &gpioc 13 0>, /* D7 */ - <14 0 &gpioa 4 0>, /* D8 */ - <15 0 &gpiob 8 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiob 4 0>, /* D12 */ - <19 0 &gpiob 12 0>, /* D13 */ - <20 0 &gpiob 11 0>, /* D14 */ - <21 0 &gpiob 10 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32f469i_disco/arduino_r3_connector.dtsi b/boards/st/stm32f469i_disco/arduino_r3_connector.dtsi index b27746b397079..7fb938d0400ae 100644 --- a/boards/st/stm32f469i_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32f469i_disco/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiob 1 0>, /* A0 */ - <1 0 &gpioc 2 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpioc 4 0>, /* A3 */ - <4 0 &gpioc 5 0>, /* A4 */ - <5 0 &gpioa 4 0>, /* A5 */ - <6 0 &gpiog 9 0>, /* D0 */ - <7 0 &gpiog 14 0>, /* D1 */ - <8 0 &gpiog 15 0>, /* D2 */ - <9 0 &gpioa 1 0>, /* D3 */ - <10 0 &gpiog 12 0>, /* D4 */ - <11 0 &gpioa 2 0>, /* D5 */ - <12 0 &gpioa 6 0>, /* D6 */ - <13 0 &gpiog 11 0>, /* D7 */ - <14 0 &gpiog 10 0>, /* D8 */ - <15 0 &gpioa 7 0>, /* D9 */ - <16 0 &gpioh 6 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpiod 3 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32f4_disco/stm32f4_disco.dts b/boards/st/stm32f4_disco/stm32f4_disco.dts index 8726fee77a9a1..88890a93b34f9 100644 --- a/boards/st/stm32f4_disco/stm32f4_disco.dts +++ b/boards/st/stm32f4_disco/stm32f4_disco.dts @@ -157,6 +157,12 @@ zephyr_udc0: &usbotg_fs { status = "okay"; }; +&can1 { + pinctrl-0 = <&can1_rx_pd0 &can1_tx_pd1>; + pinctrl-names = "default"; + status = "okay"; +}; + &can2 { pinctrl-0 = <&can2_rx_pb5 &can2_tx_pb13>; pinctrl-names = "default"; @@ -203,7 +209,7 @@ zephyr_udc0: &usbotg_fs { mck-enabled; pinctrl-0 = <&i2s3_ws_pa4 &i2s3_ck_pc10 &i2s3_sd_pc12 &i2s3_mck_pc7>; pinctrl-names = "default"; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>, + clocks = <&rcc STM32_CLOCK(APB1, 15)>, <&rcc STM32_SRC_PLLI2S_R I2S_SEL(0)>; status = "okay"; }; diff --git a/boards/st/stm32f723e_disco/arduino_r3_connector.dtsi b/boards/st/stm32f723e_disco/arduino_r3_connector.dtsi index 49aae34bf5bfd..d4c1aa2e68db6 100644 --- a/boards/st/stm32f723e_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32f723e_disco/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 6 0>, /* A0 */ - <1 0 &gpioa 4 0>, /* A1 */ - <2 0 &gpioc 4 0>, /* A2 */ - <3 0 &gpiof 10 0>, /* A3 */ - <4 0 &gpioc 0 0>, /* A4 */ - <5 0 &gpioc 1 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioc 5 0>, /* D2 */ - <9 0 &gpioe 5 0>, /* D3 */ - <10 0 &gpioh 3 0>, /* D4 */ - <11 0 &gpiob 0 0>, /* D5 */ - <12 0 &gpioe 6 0>, /* D6 */ - <13 0 &gpioe 3 0>, /* D7 */ - <14 0 &gpioe 4 0>, /* D8 */ - <15 0 &gpioh 6 0>, /* D9 */ - <16 0 &gpioa 1 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiob 4 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpioh 5 0>, /* D14 */ - <21 0 &gpioh 4 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32f746g_disco/arduino_r3_connector.dtsi b/boards/st/stm32f746g_disco/arduino_r3_connector.dtsi index 1f00baef82a28..785c22cf77cee 100644 --- a/boards/st/stm32f746g_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32f746g_disco/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpiof 10 0>, /* A1 */ - <2 0 &gpiof 9 0>, /* A2 */ - <3 0 &gpiof 8 0>, /* A3 */ - <4 0 &gpiof 7 0>, /* A4 */ - <5 0 &gpiof 6 0>, /* A5 */ - <6 0 &gpioc 7 0>, /* D0 */ - <7 0 &gpioc 6 0>, /* D1 */ - <8 0 &gpiog 6 0>, /* D2 */ - <9 0 &gpiob 4 0>, /* D3 */ - <10 0 &gpiog 7 0>, /* D4 */ - <11 0 &gpioi 0 0>, /* D5 */ - <12 0 &gpioh 6 0>, /* D6 */ - <13 0 &gpioi 3 0>, /* D7 */ - <14 0 &gpioi 2 0>, /* D8 */ - <15 0 &gpioa 15 0>, /* D9 */ - <16 0 &gpioa 8 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpioi 1 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32f7508_dk/arduino_r3_connector.dtsi b/boards/st/stm32f7508_dk/arduino_r3_connector.dtsi index 544cc5928114b..83cb1a000926b 100644 --- a/boards/st/stm32f7508_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32f7508_dk/arduino_r3_connector.dtsi @@ -5,34 +5,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpiof 10 0>, /* A1 */ - <2 0 &gpiof 9 0>, /* A2 */ - <3 0 &gpiof 8 0>, /* A3 */ - <4 0 &gpiof 7 0>, /* A4 */ - <5 0 &gpiof 6 0>, /* A5 */ - <6 0 &gpioc 7 0>, /* D0 */ - <7 0 &gpioc 6 0>, /* D1 */ - <8 0 &gpiog 6 0>, /* D2 */ - <9 0 &gpiob 4 0>, /* D3 */ - <10 0 &gpiog 7 0>, /* D4 */ - <11 0 &gpioi 0 0>, /* D5 */ - <12 0 &gpioh 6 0>, /* D6 */ - <13 0 &gpioi 3 0>, /* D7 */ - <14 0 &gpioi 2 0>, /* D8 */ - <15 0 &gpioa 15 0>, /* D9 */ - <16 0 &gpioa 8 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpioi 1 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32f769i_disco/arduino_r3_connector.dtsi b/boards/st/stm32f769i_disco/arduino_r3_connector.dtsi index c2b12e9b39b51..ec0dbc1ea49ed 100644 --- a/boards/st/stm32f769i_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32f769i_disco/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 6 0>, /* A0 */ - <1 0 &gpioa 4 0>, /* A1 */ - <2 0 &gpioc 2 0>, /* A2 */ - <3 0 &gpiof 10 0>, /* A3 */ - <4 0 &gpiof 8 0>, /* A4 */ - <5 0 &gpiof 9 0>, /* A5 */ - <6 0 &gpioc 7 0>, /* D0 */ - <7 0 &gpioc 6 0>, /* D1 */ - <8 0 &gpioj 1 0>, /* D2 */ - <9 0 &gpiof 6 0>, /* D3 */ - <10 0 &gpioj 0 0>, /* D4 */ - <11 0 &gpioc 8 0>, /* D5 */ - <12 0 &gpiof 7 0>, /* D6 */ - <13 0 &gpioj 3 0>, /* D7 */ - <14 0 &gpioj 4 0>, /* D8 */ - <15 0 &gpioh 6 0>, /* D9 */ - <16 0 &gpioa 11 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpioa 12 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi b/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi index 09d0e4bda1ad4..992d0f0bec6d1 100644 --- a/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiob 0 0>, /* A0 */ - <1 0 &gpioa 4 0>, /* A1 */ - <2 0 &gpioa 0 0>, /* A2 */ - <3 0 &gpioa 5 0>, /* A3 */ - <4 0 &gpioa 6 0>, /* A4 */ - <5 0 &gpiof 12 0>, /* A5 */ - <6 0 &gpiob 11 0>, /* D0 */ - <7 0 &gpiob 10 0>, /* D1 */ - <8 0 &gpiog 15 0>, /* D2 */ - <9 0 &gpiob 5 0>, /* D3 */ - <10 0 &gpiog 4 0>, /* D4 */ - <11 0 &gpioh 11 0>, /* D5 */ - <12 0 &gpioh 10 0>, /* D6 */ - <13 0 &gpiog 5 0>, /* D7 */ - <14 0 &gpiog 8 0>, /* D8 */ - <15 0 &gpioa 8 0>, /* D9 */ - <16 0 &gpioa 3 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpioi 2 0>, /* D12 */ - <19 0 &gpioi 1 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi b/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi index 4a30db3ffe32f..05d04836b225e 100644 --- a/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi @@ -5,34 +5,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0 */ - <1 0 &gpiof 8 0>, /* A1 */ - <2 0 &gpioa 0 0>, /* A2 */ - <3 0 &gpioa 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpioc 3 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 3 0>, /* D2 */ - <9 0 &gpioa 6 0>, /* D3 */ - <10 0 &gpiok 1 0>, /* D4 */ - <11 0 &gpioa 8 0>, /* D5 */ - <12 0 &gpioe 6 0>, /* D6 */ - <13 0 &gpioi 6 0>, /* D7 */ - <14 0 &gpioe 3 0>, /* D8 */ - <15 0 &gpioh 15 0>, /* D9 */ - <16 0 &gpiob 4 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpioi 2 0>, /* D12 */ - <19 0 &gpiod 3 0>, /* D13 */ - <20 0 &gpiod 13 0>, /* D14 */ - <21 0 &gpiod 12 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32h747i_disco/arduino_r3_connector.dtsi b/boards/st/stm32h747i_disco/arduino_r3_connector.dtsi index cd347a1eabee3..8bfde98887f94 100644 --- a/boards/st/stm32h747i_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32h747i_disco/arduino_r3_connector.dtsi @@ -4,33 +4,35 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 4 0>, /* A0 */ - <1 0 &gpiof 10 0>, /* A1 */ - <2 0 &gpioa 0 0>, /* A2 */ - <3 0 &gpioa 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpioc 3 0>, /* A5 */ - <6 0 &gpioj 9 0>, /* D0 */ - <7 0 &gpioj 8 0>, /* D1 */ - <8 0 &gpioj 3 0>, /* D2 */ - <9 0 &gpiof 8 0>, /* D3 */ - <10 0 &gpioj 4 0>, /* D4 */ - <11 0 &gpioa 6 0>, /* D5 */ - <12 0 &gpioj 7 0>, /* D6 */ - <13 0 &gpioj 0 0>, /* D7 */ - <14 0 &gpioj 5 0>, /* D8 */ - <15 0 &gpioj 6 0>, /* D9 */ - <16 0 &gpiok 1 0>, /* D10 */ - <17 0 &gpioj 10 0>, /* D11 */ - <18 0 &gpioj 11 0>, /* D12 */ - <19 0 &gpiok 0 0>, /* D13 */ - <20 0 &gpiod 13 0>, /* D14 */ - <21 0 &gpiod 12 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi b/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi index 40ed77d4adfa6..30eab953c4f16 100644 --- a/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0 */ - <1 0 &gpiof 8 0>, /* A1 */ - <2 0 &gpioa 0 0>, /* A2 */ - <3 0 &gpioa 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpioc 3 0>, /* A5 */ - <6 0 &gpiob 7 0>, /* D0 */ - <7 0 &gpiob 6 0>, /* D1 */ - <8 0 &gpiog 3 0>, /* D2 */ - <9 0 &gpioa 6 0>, /* D3 */ - <10 0 &gpiok 1 0>, /* D4 */ - <11 0 &gpioa 8 0>, /* D5 */ - <12 0 &gpioe 6 0>, /* D6 */ - <13 0 &gpioi 8 0>, /* D7 */ - <14 0 &gpioe 3 0>, /* D8 */ - <15 0 &gpioh 15 0>, /* D9 */ - <16 0 &gpiob 4 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpioi 2 0>, /* D12 */ - <19 0 &gpiod 3 0>, /* D13 */ - <20 0 &gpiod 13 0>, /* D14 */ - <21 0 &gpiod 12 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi b/boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi index 2b8eb3d1427c6..320697d8e67bd 100644 --- a/boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 4 0>, /* A0 */ - <1 0 &gpioc 4 0>, /* A1 */ - <2 0 &gpioa 0 0>, /* A2 */ - <3 0 &gpioa 1 0>, /* A3 */ - <4 0 &gpioc 2 0>, /* A4 */ - <5 0 &gpioc 3 0>, /* A5 */ - <6 0 &gpioh 14 0>, /* D0 */ - <7 0 &gpioh 13 0>, /* D1 */ - <8 0 &gpioi 9 0>, /* D2 */ - <9 0 &gpioh 9 0>, /* D3 */ - <10 0 &gpioe 2 0>, /* D4 */ - <11 0 &gpioh 11 0>, /* D5 */ - <12 0 &gpioh 10 0>, /* D6 */ - <13 0 &gpioi 10 0>, /* D7 */ - <14 0 &gpiof 10 0>, /* D8 */ - <15 0 &gpioi 7 0>, /* D9 */ - <16 0 &gpioi 0 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpioa 12 0>, /* D13 */ - <20 0 &gpiod 13 0>, /* D14 */ - <21 0 &gpiod 12 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi b/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi index c1d06e17bc13e..b89c8fe723b2e 100644 --- a/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 0 0>, /* A0 */ - <1 0 &gpioc 2 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 12 0>, /* A3 */ - <4 0 &gpiof 13 0>, /* A4 */ - <5 0 &gpioc 1 0>, /* A5 */ - <6 0 &gpioe 7 0>, /* D0 */ - <7 0 &gpioe 8 0>, /* D1 */ - <8 0 &gpiof 1 0>, /* D2 */ - <9 0 &gpiod 12 0>, /* D3 */ - <10 0 &gpiof 2 0>, /* D4 */ - <11 0 &gpiod 13 0>, /* D5 */ - <12 0 &gpiod 15 0>, /* D6 */ - <13 0 &gpiof 3 0>, /* D7 */ - <14 0 &gpiof 4 0>, /* D8 */ - <15 0 &gpiof 6 0>, /* D9 */ - <16 0 &gpiof 8 0>, /* D10 */ - <17 0 &gpioe 14 0>, /* D11 */ - <18 0 &gpioe 13 0>, /* D12 */ - <19 0 &gpioe 12 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32l496g_disco/arduino_r3_connector.dtsi b/boards/st/stm32l496g_disco/arduino_r3_connector.dtsi index 54b9cd770c996..7cee92756366c 100644 --- a/boards/st/stm32l496g_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32l496g_disco/arduino_r3_connector.dtsi @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; @@ -11,28 +13,28 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = - <0 0 &gpioc 4 0>, /* A0 */ - <1 0 &gpioc 1 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiof 10 0>, /* A3 */ - <4 0 &gpioa 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpiog 8 0>, /* D0 */ - <7 0 &gpiog 7 0>, /* D1 */ - <8 0 &gpiog 13 0>, /* D2 */ - <9 0 &gpioh 15 0>, /* D3 */ - <10 0 &gpioi 11 0>, /* D4 */ - <11 0 &gpiob 9 0>, /* D5 */ - <12 0 &gpioi 6 0>, /* D6 */ - <13 0 &gpiog 6 0>, /* D7 */ - <14 0 &gpiog 15 0>, /* D8 */ - <15 0 &gpioh 13 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiob 4 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi b/boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi index 29b56539b704e..7f5eb1728b522 100644 --- a/boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 7 0>, /* A0 */ - <1 0 &gpioc 4 0>, /* A1 */ - <2 0 &gpioc 3 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioa 0 0>, /* A4 */ - <5 0 &gpioa 5 0>, /* A5 */ - <6 0 &gpioc 0 0>, /* D0 */ - <7 0 &gpioc 1 0>, /* D1 */ - <8 0 &gpiog 11 0>, /* D2 */ - <9 0 &gpiof 10 0>, /* D3 */ - <10 0 &gpiog 6 0>, /* D4 */ - <11 0 &gpioa 1 0>, /* D5 */ - <12 0 &gpiob 4 0>, /* D6 */ - <13 0 &gpioa 4 0>, /* D7 */ - <14 0 &gpioh 15 0>, /* D8 */ - <15 0 &gpioh 13 0>, /* D9 */ - <16 0 &gpioi 0 0>, /* D10 */ - <17 0 &gpiob 15 0>, /* D11 */ - <18 0 &gpiob 14 0>, /* D12 */ - <19 0 &gpiob 13 0>, /* D13 */ - <20 0 &gpiog 8 0>, /* D14 */ - <21 0 &gpiog 7 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32l562e_dk/arduino_r3_connector.dtsi b/boards/st/stm32l562e_dk/arduino_r3_connector.dtsi index b08d153d064b2..104b699945cc8 100644 --- a/boards/st/stm32l562e_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32l562e_dk/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpioa 5 0>, /* A3 */ - <4 0 &gpioc 4 0>, /* A4 */ - <5 0 &gpioc 5 0>, /* A5 */ - <6 0 &gpiob 10 0>, /* D0 */ - <7 0 &gpiob 11 0>, /* D1 */ - <8 0 &gpiod 11 0>, /* D2 */ - <9 0 &gpiod 12 0>, /* D3 */ - <10 0 &gpiof 4 0>, /* D4 */ - <11 0 &gpiod 13 0>, /* D5 */ - <12 0 &gpiob 8 0>, /* D6 */ - <13 0 &gpioc 6 0>, /* D7 */ - <14 0 &gpiog 0 0>, /* D8 */ - <15 0 &gpiob 9 0>, /* D9 */ - <16 0 &gpioe 0 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiob 4 0>, /* D12 */ - <19 0 &gpiog 9 0>, /* D13 */ - <20 0 &gpiob 7 0>, /* D14 */ - <21 0 &gpiob 6 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts index 98cf9d03c713c..9588b2044fcb9 100644 --- a/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts +++ b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts @@ -188,20 +188,14 @@ csi_interface: &dcmipp { &dcmipp_pixclk_pb7 &dcmipp_vsync_pg9 &dcmipp_hsync_ph8>; pinctrl-names = "default"; - ports { - port@0 { - dcmipp_ep_in: endpoint { - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <0>; - bus-type = ; - remote-endpoint-label = "mipid02_2"; - }; - }; - - port@1 { - csi_capture_port: endpoint { }; + port { + dcmipp_ep_in: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + bus-type = ; + remote-endpoint-label = "mipid02_2"; }; }; }; diff --git a/boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi b/boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi index d7d5b268c501e..17d6b1de072d2 100644 --- a/boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi +++ b/boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpiof 14 0>, /* A0 */ - <1 0 &gpiof 13 0>, /* A1 */ + gpio-map = , + , /* ANA0 is not a GPIO A2 */ /* ANA1 is not a GPIO A3 */ - <4 0 &gpioc 3 0>, /* A4 */ - <5 0 &gpiof 12 0>, /* A5 */ - <6 0 &gpioe 7 0>, /* D0 */ - <7 0 &gpioe 8 0>, /* D1 */ - <8 0 &gpioe 1 0>, /* D2 */ - <9 0 &gpiod 14 0>, /* D3 */ - <10 0 &gpioe 10 0>, /* D4 */ - <11 0 &gpiod 15 0>, /* D5 */ - <12 0 &gpioe 9 0>, /* D6 */ - <13 0 &gpiod 1 0>, /* D7 */ - <14 0 &gpiog 3 0>, /* D8 */ - <15 0 &gpioh 6 0>, /* D9 */ - <16 0 &gpioe 11 0>, /* D10 */ - <17 0 &gpioe 14 0>, /* D11 */ - <18 0 &gpioe 13 0>, /* D12 */ - <19 0 &gpioe 12 0>, /* D13 */ - <20 0 &gpioa 12 0>, /* D14 */ - <21 0 &gpioa 11 0>; /* D15 */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32n6570_dk/arduino_r3_connector.dtsi b/boards/st/stm32n6570_dk/arduino_r3_connector.dtsi index b3309965278e5..c77479d17c3da 100644 --- a/boards/st/stm32n6570_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32n6570_dk/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 5 0>, /* A0 */ - <1 0 &gpioa 9 0>, /* A1 */ - <2 0 &gpioa 10 0>, /* A2 */ - <3 0 &gpioa 12 0>, /* A3 */ - <4 0 &gpiof 3 0>, /* A4 */ - <5 0 &gpiob 10 0>, /* A5 */ - <6 0 &gpiof 6 0>, /* D0 */ - <7 0 &gpiod 5 0>, /* D1 */ - <8 0 &gpiod 0 0>, /* D2 */ - <9 0 &gpioe 9 0>, /* D3 */ - <10 0 &gpioh 5 0>, /* D4 */ - <11 0 &gpioe 10 0>, /* D5 */ - <12 0 &gpioe 13 0>, /* D6 */ - <13 0 &gpiod 6 0>, /* D7 */ - <14 0 &gpioe 7 0>, /* D8 */ - <15 0 &gpioe 14 0>, /* D9 */ - <16 0 &gpioa 3 0>, /* D10 */ - <17 0 &gpiog 2 0>, /* D11 */ - <18 0 &gpioh 8 0>, /* D12 */ - <19 0 &gpioe 15 0>, /* D13 */ - <20 0 &gpioc 1 0>, /* D14 */ - <21 0 &gpioh 9 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi index dc69273444f80..24f5d6d097a2f 100644 --- a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi +++ b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi @@ -144,12 +144,6 @@ status = "okay"; }; -&ic3 { - pll-src = <1>; - ic-div = <6>; - status = "okay"; -}; - &ic4 { pll-src = <2>; ic-div = <32>; @@ -342,7 +336,7 @@ zephyr_udc0: &usbotg_hs1 { &xspim_p2_io6_pn10 &xspim_p2_io7_pn11>; pinctrl-names = "default"; clocks = <&rcc STM32_CLOCK(AHB5, 12)>, - <&rcc STM32_SRC_IC3 XSPI1_SEL(2)>, + <&rcc STM32_SRC_HCLK5 XSPI2_SEL(0)>, <&rcc STM32_CLOCK(AHB5, 13)>; status = "okay"; @@ -481,13 +475,7 @@ zephyr_udc0: &usbotg_hs1 { }; csi_interface: &dcmipp { - ports { - port@0 { - csi_ep_in: endpoint { }; - }; - - port@1 { - csi_capture_port: endpoint@1 { }; - }; + port { + csi_ep_in: endpoint { }; }; }; diff --git a/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi index bb444e44c2b85..0d4b7d3933782 100644 --- a/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi @@ -4,34 +4,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioa 0 0>, /* A0 */ - <1 0 &gpioa 1 0>, /* A1 */ - <2 0 &gpioa 4 0>, /* A2 */ - <3 0 &gpiob 0 0>, /* A3 */ - <4 0 &gpioc 1 0>, /* A4 */ - <5 0 &gpioc 0 0>, /* A5 */ - <6 0 &gpioa 3 0>, /* D0 */ - <7 0 &gpioa 2 0>, /* D1 */ - <8 0 &gpioc 12 0>, /* D2 */ - <9 0 &gpiob 3 0>, /* D3 */ - <10 0 &gpiob 5 0>, /* D4 */ - <11 0 &gpiob 4 0>, /* D5 */ - <12 0 &gpiob 10 0>, /* D6 */ - <13 0 &gpioa 8 0>, /* D7 */ - <14 0 &gpioa 9 0>, /* D8 */ - <15 0 &gpioc 7 0>, /* D9 */ - <16 0 &gpioa 15 0>, /* D10 */ - <17 0 &gpioa 7 0>, /* D11 */ - <18 0 &gpioa 6 0>, /* D12 */ - <19 0 &gpioa 5 0>, /* D13 */ - <20 0 &gpiob 9 0>, /* D14 */ - <21 0 &gpiob 8 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; }; diff --git a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts index 7e33fc831d3e1..9fedebdc58f22 100644 --- a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts +++ b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts @@ -332,7 +332,7 @@ zephyr_udc0: &usbotg_hs { }; &xspi1 { - clocks = <&rcc STM32_CLOCK(AHB2_2, 12U)>, + clocks = <&rcc STM32_CLOCK(AHB2_2, 12)>, <&rcc STM32_SRC_PLL2_Q HSPI_SEL(2)>; pinctrl-0 = <&hspi1_dqs0_pi2 &hspi1_ncs_ph9 diff --git a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst index b9718b73ca8c1..f75b70875d260 100644 --- a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst +++ b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst @@ -7,7 +7,7 @@ STM32WB5MMG is an ultra-low-power and small form factor certified 2.4 GHz wireless module. It supports Bluetooth|reg| Low Energy 5.4, Zigbee|reg| 3.0, OpenThread, dynamic, and static concurrent modes, and 802.15.4 proprietary protocols. This board support is added in order to make it possible use this -module on other boards as HCI layer (Specefically B-U585I-IOT02A Development board). +module on other boards as HCI layer (Specifically B-U585I-IOT02A Development board). STM32WB5MMG supports the following features: diff --git a/boards/ti/am243x_evm/doc/index.rst b/boards/ti/am243x_evm/doc/index.rst index 9689e094f9c69..72928a9c6fcae 100644 --- a/boards/ti/am243x_evm/doc/index.rst +++ b/boards/ti/am243x_evm/doc/index.rst @@ -89,7 +89,7 @@ Zephyr dependencies. You can replace ``all/dev.yml`` in the ``west init`` command with ``am243x/dev.yml``, if you want to clone a few less repositories. You also need to follow the "Downloading And Installing Dependencies" section -but you need to replace all ``am263x`` occurences in commands with ``am243x``. +but you need to replace all ``am263x`` occurrences in commands with ``am243x``. Please also take note of the ``tools`` and ``mcu_plus_sdk`` install path. The ``tools`` install path will later be referred to as ``$TI_TOOLS`` and the MCU+ SDK path as ``$MCUPSDK``. You can pass ``--skip_doxygen=true`` and diff --git a/boards/toradex/colibri_imx7d/doc/index.rst b/boards/toradex/colibri_imx7d/doc/index.rst index 10f0b732a21c7..c381a39a49657 100644 --- a/boards/toradex/colibri_imx7d/doc/index.rst +++ b/boards/toradex/colibri_imx7d/doc/index.rst @@ -304,7 +304,7 @@ from its currently loaded dtb file. }; #Add these definitions under / { } just before the __symbols__ - #Disgard the comments with #--> + #Discard the comments with #--> reserved-memory { #address-cells = <0x01>; #size-cells = <0x01>; diff --git a/boards/toradex/verdin_am62/Kconfig.verdin_am62 b/boards/toradex/verdin_am62/Kconfig.verdin_am62 new file mode 100644 index 0000000000000..7ebf0665aa0c1 --- /dev/null +++ b/boards/toradex/verdin_am62/Kconfig.verdin_am62 @@ -0,0 +1,8 @@ +# Toradex Verdin AM62 +# +# Copyright (c) 2025 Toradex +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VERDIN_AM62 + select SOC_AM6234_M4 if BOARD_VERDIN_AM62_AM6234_M4 diff --git a/boards/toradex/verdin_am62/board.yml b/boards/toradex/verdin_am62/board.yml new file mode 100644 index 0000000000000..d70dd5ffe75e7 --- /dev/null +++ b/boards/toradex/verdin_am62/board.yml @@ -0,0 +1,6 @@ +board: + name: verdin_am62 + full_name: Verdin AM62 + vendor: toradex + socs: + - name: am6234 diff --git a/boards/toradex/verdin_am62/doc/img/verdin_am62.webp b/boards/toradex/verdin_am62/doc/img/verdin_am62.webp new file mode 100644 index 0000000000000..10f61dc58e89a Binary files /dev/null and b/boards/toradex/verdin_am62/doc/img/verdin_am62.webp differ diff --git a/boards/toradex/verdin_am62/doc/index.rst b/boards/toradex/verdin_am62/doc/index.rst new file mode 100644 index 0000000000000..6d930cd91d2fe --- /dev/null +++ b/boards/toradex/verdin_am62/doc/index.rst @@ -0,0 +1,113 @@ +.. zephyr:board:: verdin_am62 + +Overview +******** + +The Verdin-AM62 board configuration is used by Zephyr applications that run on +the TI AM62x platform. The board configuration provides support for: + +- ARM Cortex-M4F MCU core and the following features: + + - Nested Vector Interrupt Controller (NVIC) + - System Tick System Clock (SYSTICK) + +The board configuration also enables support for the semihosting debugging console. + +See the `Toradex Verdin AM62 Product Page`_ for details. + +Hardware +******** + +The Toradex Verdin AM62 is a System on Module (SoM) based on the Texas Instruments AM62x family of +processors. It features up to four Arm® Cortex®-A53 cores, a Cortex®-M4F real-time core, and +dedicated peripherals such as PRU cores. + +Zephyr is ported to run on the M4F core. The following listed hardware specifications are used: + +- Low-power ARM Cortex-M4F +- Memory + + - 256KB of SRAM + - 16MB of DDR4 (can go from 512MB to 2GB maximum) + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 400 MHz. + +DDR RAM +------- + +The board can have from 512MB up to 2GB of DDR RAM. This board configuration allocates approximately +16MB of RAM, which includes the resource table, shared memories for IPC and SRAM to be used by the +cortex-M. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +MCU domain UART (MCU_UART0). + +Programming the M4F Core +************************ + +Cortex-M4F core can be programmed by remoteproc on both Linux Kernel or U-Boot bootloader. For the +Linux kernel, the remoteproc uses the resource table to load the firmware into the Cortex-M4F. + +To test the M4F core, build the :zephyr:code-sample:`hello_world` sample with the following command: + +.. code-block:: console + + # From the root of the Zephyr repository + west build -p -b verdin_am62/am6234/m4 samples/hello_world + +This builds the binary, which is located at :file:`build/zephyr` directory as :file:`zephyr.elf`. + +This binary needs to be copied to Verdin AN62 (can be copied to the eMMC, use an SD card, usb +stick...) and place it on :file:`/lib/firmware` directory and name it as :file:`am62-mcu-m4f0_0-fw`. +After that, it can be loaded by Linux remoteproc with the following commands: + +.. code-block:: console + + echo start > /sys/class/remoteproc/remoteproc0/state + +The binary will run and print Hello world to the MCU_UART0 port. + +If instead it is desired to load it with U-Boot, the following commands can be executed into the +bootloader terminal: + +.. code-block:: console + + rproc init + rproc list + load mmc 0:2 ${loadaddr} /lib/firmware/am62-mcu-m4f0_0-fw + rproc load ${loadaddr} 0 0x${filesize} + rproc start 0 + +.. hint:: + For both remoteproc examples, check the id of the remote processor to make sure the firmware is + being loaded into the correct core. + +When the core starts, in this case with the hello world sample, this will be shown into the UART +from the cortex-m (which will be /dev/ttyUSB2 for both Dahlia and Verdin Development boards): + +.. code-block:: console + + *** Booting Zephyr OS build v4.2.0-1172-g242870ac3feb *** + Hello World! verdin_am62/am6234/m4 + +References +********** + +.. _Toradex Verdin AM62 Product Page: + https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + +.. _Toradex Verdin AM62 Developer Page: + https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/ diff --git a/boards/toradex/verdin_am62/verdin_am62_am6234_m4.dts b/boards/toradex/verdin_am62/verdin_am62_am6234_m4.dts new file mode 100644 index 0000000000000..760dce62e21c4 --- /dev/null +++ b/boards/toradex/verdin_am62/verdin_am62_am6234_m4.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2025 Toradex + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "Toradex Verdin AM62"; + compatible = "toradex,verdin_am62"; + + chosen { + zephyr,console = &uart0; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,sram1 = &ddr1; + }; + + cpus { + cpu@0 { + clock-frequency = ; + status = "okay"; + }; + }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox0 0>, <&mbox0 1>; + mbox-names = "tx", "rx"; + }; + + ddr0: memory@9cb00000 { + compatible = "mmio-sram"; + reg = <0x9cb00000 DT_SIZE_M(1)>; + }; + + rsc_table: memory@9cc00000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x9cc00000 DT_SIZE_K(4)>; + zephyr,memory-region = "RSC_TABLE"; + }; + + ddr1: memory@9cc01000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x9cc01000 (DT_SIZE_M(15) - DT_SIZE_K(4))>; + zephyr,memory-region = "DDR"; + }; +}; + +&mbox0 { + status = "okay"; +}; + +&pinctrl { + mcu_uart0_rx_default: mcu_uart0_rx_default { + pinmux = ; + }; + + mcu_uart0_tx_default: mcu_uart0_tx_default { + pinmux = ; + }; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&mcu_uart0_rx_default &mcu_uart0_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/toradex/verdin_am62/verdin_am62_am6234_m4.yaml b/boards/toradex/verdin_am62/verdin_am62_am6234_m4.yaml new file mode 100644 index 0000000000000..c357bf328896a --- /dev/null +++ b/boards/toradex/verdin_am62/verdin_am62_am6234_m4.yaml @@ -0,0 +1,8 @@ +identifier: verdin_am62/am6234/m4 +name: Toradex Verdin AM62 +type: mcu +arch: arm +toolchain: + - zephyr +ram: 192 +vendor: toradex diff --git a/boards/toradex/verdin_am62/verdin_am62_am6234_m4_defconfig b/boards/toradex/verdin_am62/verdin_am62_am6234_m4_defconfig new file mode 100644 index 0000000000000..cc2ab0f9a42f9 --- /dev/null +++ b/boards/toradex/verdin_am62/verdin_am62_am6234_m4_defconfig @@ -0,0 +1,18 @@ +# Toradex Verdin AM62 +# +# Copyright (c) 2025 Toradex +# +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_CORTEX_M_SYSTICK=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Driver +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts index 5d16fa4164b8d..94ea2cb99e001 100644 --- a/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts +++ b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "ubx_bmd300eval_nrf52832-pinctrl.dtsi" +#include #include / { @@ -80,28 +81,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio0 11 0>, /* D0 */ - <7 0 &gpio0 12 0>, /* D1 */ - <8 0 &gpio0 13 0>, /* D2 */ - <9 0 &gpio0 14 0>, /* D3 */ - <10 0 &gpio0 15 0>, /* D4 */ - <11 0 &gpio0 16 0>, /* D5 */ - <12 0 &gpio0 17 0>, /* D6 */ - <13 0 &gpio0 18 0>, /* D7 */ - <14 0 &gpio0 19 0>, /* D8 */ - <15 0 &gpio0 20 0>, /* D9 */ - <16 0 &gpio0 22 0>, /* D10 */ - <17 0 &gpio0 23 0>, /* D11 */ - <18 0 &gpio0 24 0>, /* D12 */ - <19 0 &gpio0 25 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts index 3ad7b44b24bb0..19ab20d80ee42 100644 --- a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts +++ b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "ubx_bmd330eval_nrf52810-pinctrl.dtsi" +#include #include / { @@ -80,28 +81,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio0 11 0>, /* D0 */ - <7 0 &gpio0 12 0>, /* D1 */ - <8 0 &gpio0 13 0>, /* D2 */ - <9 0 &gpio0 14 0>, /* D3 */ - <10 0 &gpio0 15 0>, /* D4 */ - <11 0 &gpio0 16 0>, /* D5 */ - <12 0 &gpio0 17 0>, /* D6 */ - <13 0 &gpio0 18 0>, /* D7 */ - <14 0 &gpio0 19 0>, /* D8 */ - <15 0 &gpio0 20 0>, /* D9 */ - <16 0 &gpio0 22 0>, /* D10 */ - <17 0 &gpio0 23 0>, /* D11 */ - <18 0 &gpio0 24 0>, /* D12 */ - <19 0 &gpio0 25 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts index 66ba3f4ca606e..b8c908549ca33 100644 --- a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts +++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts @@ -9,6 +9,7 @@ #include #include #include "ubx_bmd340eval_nrf52840-pinctrl.dtsi" +#include #include / { @@ -80,28 +81,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts index 36154e17d24b4..7e057f7c29520 100644 --- a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts +++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts @@ -10,6 +10,7 @@ #include #include #include "ubx_bmd345eval_nrf52840-pinctrl.dtsi" +#include #include / { @@ -81,28 +82,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ + gpio-map = , + , + , + , + , + , + , /* not present */ /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ + , /* not present */ /* D3 */ /* not present */ /* D4 */ /* not present */ /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts index b6d4f205639f9..cb8bb87a4a35d 100644 --- a/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts +++ b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "ubx_bmd360eval_nrf52811-pinctrl.dtsi" +#include #include / { @@ -80,28 +81,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio0 11 0>, /* D0 */ - <7 0 &gpio0 12 0>, /* D1 */ - <8 0 &gpio0 13 0>, /* D2 */ - <9 0 &gpio0 14 0>, /* D3 */ - <10 0 &gpio0 15 0>, /* D4 */ - <11 0 &gpio0 16 0>, /* D5 */ - <12 0 &gpio0 17 0>, /* D6 */ - <13 0 &gpio0 18 0>, /* D7 */ - <14 0 &gpio0 19 0>, /* D8 */ - <15 0 &gpio0 20 0>, /* D9 */ - <16 0 &gpio0 22 0>, /* D10 */ - <17 0 &gpio0 23 0>, /* D11 */ - <18 0 &gpio0 24 0>, /* D12 */ - <19 0 &gpio0 25 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts index 890f02370ff1b..37acb9118a30f 100644 --- a/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts +++ b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "ubx_evkannab1_nrf52832-pinctrl.dtsi" +#include #include / { @@ -77,28 +78,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio0 2 0>, /* D0 */ - <7 0 &gpio0 3 0>, /* D1 */ - <8 0 &gpio0 19 0>, /* D2 */ - <9 0 &gpio0 11 0>, /* D3 */ - <10 0 &gpio0 27 0>, /* D4 */ - <11 0 &gpio0 26 0>, /* D5 */ - <12 0 &gpio0 10 0>, /* D6 */ - <13 0 &gpio0 9 0>, /* D7 */ - <14 0 &gpio0 14 0>, /* D8 */ - <15 0 &gpio0 24 0>, /* D9 */ - <16 0 &gpio0 22 0>, /* D10 */ - <17 0 &gpio0 23 0>, /* D11 */ - <18 0 &gpio0 18 0>, /* D12 */ - <19 0 &gpio0 20 0>, /* D13 */ - <20 0 &gpio0 15 0>, /* D14 */ - <21 0 &gpio0 16 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts index 69d59be98517f..c0cccdfb6350c 100644 --- a/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts +++ b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "ubx_evkninab1_nrf52832-pinctrl.dtsi" +#include #include / { @@ -77,28 +78,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 2 0>, /* A1 */ - <2 0 &gpio0 4 0>, /* A2 */ - <3 0 &gpio0 30 0>, /* A3 */ - <4 0 &gpio0 29 0>, /* A4 */ - <5 0 &gpio0 28 0>, /* A5 */ - <6 0 &gpio0 5 0>, /* D0 */ - <7 0 &gpio0 6 0>, /* D1 */ - <8 0 &gpio0 7 0>, /* D2 */ - <9 0 &gpio0 31 0>, /* D3 */ - <10 0 &gpio0 18 0>, /* D4 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , /* 11 SWDIO */ /* D5 */ - <12 0 &gpio0 9 0>, /* D6 */ - <13 0 &gpio0 10 0>, /* D7 */ + , + , /* 14 SWDCLK */ /* D8 */ - <15 0 &gpio0 8 0>, /* D9 */ - <16 0 &gpio0 11 0>, /* D10 */ - <17 0 &gpio0 13 0>, /* D11 */ - <18 0 &gpio0 12 0>, /* D12 */ - <19 0 &gpio0 14 0>, /* D13 */ - <20 0 &gpio0 2 0>, /* D14 */ - <21 0 &gpio0 3 0>; /* D15 */ + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts index fe02494494676..50f91211004e6 100644 --- a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts +++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts @@ -8,6 +8,7 @@ #include #include #include "ubx_evkninab3_nrf52840-pinctrl.dtsi" +#include #include / { @@ -71,28 +72,28 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 04 0>, /* A0 */ - <1 0 &gpio0 30 0>, /* A1 */ - <2 0 &gpio0 5 0>, /* A2 */ - <3 0 &gpio0 2 0>, /* A3 */ - <4 0 &gpio0 28 0>, /* A4 */ - <5 0 &gpio0 3 0>, /* A5 */ - <6 0 &gpio0 29 0>, /* D0 */ - <7 0 &gpio1 13 0>, /* D1 */ - <8 0 &gpio1 12 0>, /* D2 */ - <9 0 &gpio0 31 0>, /* D3 */ - <10 0 &gpio0 13 0>, /* D4 */ - <11 0 &gpio0 11 0>, /* D5 */ - <12 0 &gpio0 9 0>, /* D6 */ - <13 0 &gpio0 10 0>, /* D7 */ - <14 0 &gpio1 9 0>, /* D8 */ - <15 0 &gpio0 12 0>, /* D9 */ - <16 0 &gpio0 14 0>, /* D10 */ - <17 0 &gpio0 15 0>, /* D11 */ - <18 0 &gpio1 0 0>, /* D12 */ - <19 0 &gpio0 7 0>, /* D13 */ - <20 0 &gpio0 16 0>, /* D14 */ - <21 0 &gpio0 24 0>; /* D15 */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; arduino_adc: analog-connector { diff --git a/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts index e753c2d05ba8d..0689748498483 100644 --- a/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts +++ b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "ubx_evkninab4_nrf52833-pinctrl.dtsi" +#include #include / { @@ -78,28 +79,30 @@ #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 30 0>, /* A1 */ - <2 0 &gpio0 5 0>, /* A2 */ - <3 0 &gpio0 2 0>, /* A3 */ - <4 0 &gpio0 28 0>, /* A4 */ - <5 0 &gpio0 3 0>, /* A5 */ - <6 0 &gpio0 29 0>, /* D0 */ - <7 0 &gpio1 5 0>, /* D1 */ - <8 0 &gpio0 23 0>, /* D2 */ - <9 0 &gpio0 31 0>, /* D3 */ - <10 0 &gpio0 13 0>, /* D4 */ - <11 0 &gpio0 11 0>, /* D5 */ - <12 0 &gpio0 9 0>, /* D6 */ /* NFC use by default */ - <13 0 &gpio0 10 0>, /* D7 */ /* NFC use by default */ - <14 0 &gpio1 9 0>, /* D8 */ - <15 0 &gpio0 12 0>, /* D9 */ - <16 0 &gpio0 0 0>, /* D10 */ /* Disconnected, see EVK User Guide */ - <17 0 &gpio0 1 0>, /* D11 */ /* Disconnected, see EVK User Guide */ - <18 0 &gpio1 0 0>, /* D12 */ - <19 0 &gpio0 7 0>, /* D13 */ - <20 0 &gpio0 16 0>, /* D14 */ /* SDA */ - <21 0 &gpio0 17 0>; /* D15 */ /* SCL */ + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , /* NFC use by default */ + , /* NFC use by default */ + , + , + /* D10 is disconnected, see EVK User Guide */ + , + /* D11 is disconnected, see EVK User Guide */ + , + , + , + , /* SDA */ + ; /* SCL */ }; arduino_adc: analog-connector { diff --git a/boards/weact/blackpill_h523ce/Kconfig.blackpill_h523ce b/boards/weact/blackpill_h523ce/Kconfig.blackpill_h523ce new file mode 100644 index 0000000000000..8b5c8ca65b54d --- /dev/null +++ b/boards/weact/blackpill_h523ce/Kconfig.blackpill_h523ce @@ -0,0 +1,5 @@ +# Copyright(c) 2025 Filip Stojanovic +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACKPILL_H523CE + select SOC_STM32H523XX diff --git a/boards/weact/blackpill_h523ce/blackpill_h523ce.dts b/boards/weact/blackpill_h523ce/blackpill_h523ce.dts new file mode 100644 index 0000000000000..b7914b2fe54b9 --- /dev/null +++ b/boards/weact/blackpill_h523ce/blackpill_h523ce.dts @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2025 Filip Stojanovic + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "WeAct Studio Black Pill STM32H523 Board"; + compatible = "weact,blackpill-h523ce"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram1; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + user_led: led { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "KEY"; + gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &user_led; + sw0 = &user_button; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; + }; +}; + +&timers3 { + status = "okay"; + st,prescaler = <24>; + + pwm3: pwm { + status = "okay"; + pinctrl-0 = <&tim3_ch3_pb0 &tim3_ch4_pb1>; + pinctrl-names = "default"; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + status = "okay"; + current-speed = <115200>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_nss_pa4 &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK(APB3, 21)>, <&rcc STM32_SRC_LSE RTC_SEL(1)>; + status = "okay"; +}; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc1 { + clocks = <&rcc STM32_CLOCK(AHB2, 10)>, <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; + pinctrl-0 = <&adc1_inp1_pa1>; + pinctrl-names = "default"; + st,adc-clock-source = "ASYNC"; + st,adc-prescaler = <8>; + status = "okay"; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + status = "okay"; + clock-frequency = ; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; + apb3-prescaler = <1>; +}; + +&pll { + div-m = <1>; + mul-n = <60>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/weact/blackpill_h523ce/blackpill_h523ce.yaml b/boards/weact/blackpill_h523ce/blackpill_h523ce.yaml new file mode 100644 index 0000000000000..c07069ca28f85 --- /dev/null +++ b/boards/weact/blackpill_h523ce/blackpill_h523ce.yaml @@ -0,0 +1,17 @@ +identifier: blackpill_h523ce +name: WeAct Studio Black Pill STM32H523 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 272 +flash: 512 +supported: + - gpio + - counter + - spi + - i2c + - uart + - pwm +vendor: weact diff --git a/boards/weact/blackpill_h523ce/blackpill_h523ce_defconfig b/boards/weact/blackpill_h523ce/blackpill_h523ce_defconfig new file mode 100644 index 0000000000000..d937ad2be9232 --- /dev/null +++ b/boards/weact/blackpill_h523ce/blackpill_h523ce_defconfig @@ -0,0 +1,16 @@ +# Copyright(c) 2025 Filip Stojanovic +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Serial drivers +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/weact/blackpill_h523ce/board.cmake b/boards/weact/blackpill_h523ce/board.cmake new file mode 100644 index 0000000000000..fcf4b775c158d --- /dev/null +++ b/boards/weact/blackpill_h523ce/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32H523CE" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/weact/blackpill_h523ce/board.yml b/boards/weact/blackpill_h523ce/board.yml new file mode 100644 index 0000000000000..70174f1bdaafb --- /dev/null +++ b/boards/weact/blackpill_h523ce/board.yml @@ -0,0 +1,6 @@ +board: + name: blackpill_h523ce + full_name: Black Pill STM32H523 + vendor: weact + socs: + - name: stm32h523xx diff --git a/boards/weact/blackpill_h523ce/doc/img/blackpill_h523ce.webp b/boards/weact/blackpill_h523ce/doc/img/blackpill_h523ce.webp new file mode 100644 index 0000000000000..f8c58c89bd247 Binary files /dev/null and b/boards/weact/blackpill_h523ce/doc/img/blackpill_h523ce.webp differ diff --git a/boards/weact/blackpill_h523ce/doc/index.rst b/boards/weact/blackpill_h523ce/doc/index.rst new file mode 100644 index 0000000000000..dbd0ea928ec05 --- /dev/null +++ b/boards/weact/blackpill_h523ce/doc/index.rst @@ -0,0 +1,107 @@ +.. zephyr:board:: blackpill_h523ce + +Overview +******** + +The WeAct STM32H523CE Core Board is a low-cost and bare-bone development +board made in the famous "blackpill" package. It features the STM32H523CE, a +high-performance microcontroller based on an Arm Cortex-M33 processor. + +Hardware +******** + +The STM32H523CE-based Black Pill board provides the following hardware +components: + +- STM32H523CE in 48-pin package +- ARM 32-bit Cortex-M33 CPU with FPU +- 250 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 274 KB SRAM +- TIM +- ADC +- USART +- I2C +- SPI +- USB FS +- FDCAN +- RTC + +Supported Features +****************** + +.. zephyr:board-supported-hw:: + +Connections and IOs +******************* + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9 / PA10 +- I2C1 SCL/SDA : PB6 / PB7 +- SPI1 CS/SCK/MISO/MOSI : PA4 / PA5 / PA6 / PA7 (routed to footprint for external flash) +- PWM_3_CH3 : PB0 +- PWM_3_CH4 : PB1 +- ADC_1 : PA1 +- USER_PB : PA0 +- USER_LED : PC13 + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +There are 2 main entry points for flashing STM32H5X SoCs: one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +******** + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util `_. The package available in +Debian/Ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig `_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: blackpill_h523ce + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.STM32H523CoreBoard/tree/master + +.. _STM32H523CE website: + https://www.st.com/en/microcontrollers-microprocessors/stm32h523ce.html + +.. _STM32H523CE reference manual: + https://www.st.com/resource/en/reference_manual/rm0481-stm32h52333xx-stm32h56263xx-and-stm32h573xx-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst index e5da27ad8c691..aadbde3ade6f0 100644 --- a/boards/witte/linum/doc/index.rst +++ b/boards/witte/linum/doc/index.rst @@ -5,7 +5,7 @@ Overview Linum is a development board released by Witte Tenology in 2023, and it was developed around the STM32H753BI microcontroller. The board has 2 expansion connectors used by the LCD display with touchscreen and another for access to other peripherals of microcontroller. Also it brings plenty -of communications interfaces like UART with RS232 and RS485 capabillities, CAN bus compatible to +of communications interfaces like UART with RS232 and RS485 capabilities, CAN bus compatible to FD standard, and networking over Ethernet. Hardware diff --git a/cmake/compiler/arcmwdt/target.cmake b/cmake/compiler/arcmwdt/target.cmake index b8aca9c36fc36..3c875007609b0 100644 --- a/cmake/compiler/arcmwdt/target.cmake +++ b/cmake/compiler/arcmwdt/target.cmake @@ -2,6 +2,7 @@ find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}ccac PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) find_program(CMAKE_CXX_COMPILER ${CROSS_COMPILE}ccac PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) find_program(CMAKE_ASM_COMPILER ${CROSS_COMPILE}ccac PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) + # The CMAKE_REQUIRED_FLAGS variable is used by check_c_compiler_flag() # (and other commands which end up calling check_c_source_compiles()) # to add additional compiler flags used during checking. These flags @@ -37,7 +38,7 @@ set(LLEXT_REMOVE_FLAGS # (check_c_compiler_flag function which we wrap with target_cc_option in extensions.cmake) # we rely on default MWDT header locations and don't manually specify headers directories. -# common compile options, no copyright msg, little-endian, no small data, +# Common compile options: no copyright message, little-endian, no small data, # no MWDT stack checking list(APPEND TOOLCHAIN_C_FLAGS -Hnocopyr -HL -Hnosdata) @@ -58,3 +59,7 @@ endif() if(CONFIG_RISCV) list(APPEND TOOLCHAIN_C_FLAGS -D__MW_ASM_RV_MACRO__) endif() + +# The MWDT compiler doesn't need to pass any properties to the linker as for now +function(compiler_set_linker_properties) +endfunction() diff --git a/cmake/compiler/clang/target.cmake b/cmake/compiler/clang/target.cmake index 85eaa5a4d5481..e4ad51794f769 100644 --- a/cmake/compiler/clang/target.cmake +++ b/cmake/compiler/clang/target.cmake @@ -36,10 +36,6 @@ if(NOT "${ARCH}" STREQUAL "posix") include(${ZEPHYR_BASE}/cmake/compiler/gcc/target_riscv.cmake) endif() - if(DEFINED CMAKE_C_COMPILER_TARGET) - set(clang_target_flag "--target=${CMAKE_C_COMPILER_TARGET}") - endif() - foreach(file_name include/stddef.h) execute_process( COMMAND ${CMAKE_C_COMPILER} --print-file-name=${file_name} diff --git a/cmake/compiler/target_template.cmake b/cmake/compiler/target_template.cmake index 0c83868beba3e..e951acf151ce1 100644 --- a/cmake/compiler/target_template.cmake +++ b/cmake/compiler/target_template.cmake @@ -52,8 +52,13 @@ if(NOT COMMAND compiler_file_path) compiler_simple_options(simple_options) + if(DEFINED CMAKE_C_COMPILER_TARGET) + set(target_flag "--target=${CMAKE_C_COMPILER_TARGET}") + endif() + execute_process( COMMAND ${CMAKE_C_COMPILER} ${TOOLCHAIN_C_FLAGS} ${COMPILER_OPTIMIZATION_FLAG} ${simple_options} + ${target_flag} --print-file-name ${filename} OUTPUT_VARIABLE filepath OUTPUT_STRIP_TRAILING_WHITESPACE @@ -80,10 +85,15 @@ if(NOT COMMAND compiler_set_linker_properties) compiler_simple_options(simple_options) + if(DEFINED CMAKE_C_COMPILER_TARGET) + set(target_flag "--target=${CMAKE_C_COMPILER_TARGET}") + endif() + # Compute complete path to the runtime library using the # --print-libgcc-file-name compiler flag execute_process( COMMAND ${CMAKE_C_COMPILER} ${TOOLCHAIN_C_FLAGS} ${COMPILER_OPTIMIZATION_FLAG} ${simple_options} + ${target_flag} --print-libgcc-file-name OUTPUT_VARIABLE library_path OUTPUT_STRIP_TRAILING_WHITESPACE diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake index 02c172e7d138b..734f118ad3e36 100644 --- a/cmake/gcc-m-cpu.cmake +++ b/cmake/gcc-m-cpu.cmake @@ -113,6 +113,8 @@ elseif("${ARCH}" STREQUAL "arm64") set(GCC_M_TUNE cortex-a76.cortex-a55) elseif(CONFIG_CPU_CORTEX_A72) set(GCC_M_CPU cortex-a72) + elseif(CONFIG_CPU_CORTEX_A78) + set(GCC_M_CPU cortex-a78) elseif(CONFIG_CPU_CORTEX_R82) set(GCC_M_CPU cortex-r82) endif() diff --git a/cmake/linker/arcmwdt/target.cmake b/cmake/linker/arcmwdt/target.cmake index 389bbeb5845b3..5e99fdd16252b 100644 --- a/cmake/linker/arcmwdt/target.cmake +++ b/cmake/linker/arcmwdt/target.cmake @@ -168,3 +168,10 @@ macro(toolchain_ld_relocation) ${ZEPHYR_BASE}/kernel/include ${ARCH_DIR}/${ARCH}/include) target_link_libraries(code_relocation_source_lib zephyr_interface) endmacro() + +# Function to map compiler flags into suitable linker flags +# When using the compiler driver to run the linker, just pass +# them all through +function(toolchain_linker_add_compiler_options) + add_link_options(${ARGV}) +endfunction() diff --git a/cmake/linker/iar/linker_flags.cmake b/cmake/linker/iar/linker_flags.cmake index 4d4fc42a44943..12d44ca24cd20 100644 --- a/cmake/linker/iar/linker_flags.cmake +++ b/cmake/linker/iar/linker_flags.cmake @@ -27,7 +27,7 @@ set_property(TARGET linker PROPERTY optimization_size_aggressive --entry_list_in string(APPEND CMAKE_C_LINK_FLAGS --no-wrap-diagnostics) if(CONFIG_IAR_DATA_INIT) - string(APPEND CMAKE_C_LINK_FLAGS " --redirect z_data_copy=__iar_data_init3") + string(APPEND CMAKE_C_LINK_FLAGS " --redirect arch_data_copy=__iar_data_init3") endif() foreach(lang C CXX ASM) set(commands "--log modules,libraries,initialization,redirects,sections") diff --git a/cmake/linker/xt-ld/target.cmake b/cmake/linker/xt-ld/target.cmake index bdaf9829fcdd2..949787836adc9 100644 --- a/cmake/linker/xt-ld/target.cmake +++ b/cmake/linker/xt-ld/target.cmake @@ -11,8 +11,6 @@ find_program(CMAKE_LINKER xt-ld ${LD_SEARCH_PATH}) set_ifndef(LINKERFLAGPREFIX -Wl) -compiler_file_path(crtbegin.o CRTBEGIN_PATH) -compiler_file_path(crtend.o CRTEND_PATH) if(CONFIG_CPP_EXCEPTIONS AND CRTBEGIN_PATH AND CRTEND_PATH) # When building with C++ Exceptions, it is important that crtbegin and crtend # are linked at specific locations. @@ -156,6 +154,10 @@ macro(toolchain_linker_finalize) set(CMAKE_ASM_LINK_EXECUTABLE " ${common_link}") set(CMAKE_C_LINK_EXECUTABLE " ${common_link}") set(CMAKE_CXX_LINK_EXECUTABLE " ${common_link}") + + compiler_file_path(crtbegin.o CRTBEGIN_PATH) + compiler_file_path(crtend.o CRTEND_PATH) + endmacro() # Function to map compiler flags into suitable linker flags diff --git a/cmake/linker_script/arm/linker.cmake b/cmake/linker_script/arm/linker.cmake index 43ace74142e5e..116c2485b0bfe 100644 --- a/cmake/linker_script/arm/linker.cmake +++ b/cmake/linker_script/arm/linker.cmake @@ -149,7 +149,7 @@ zephyr_linker_section(NAME .ramfunc GROUP RAM_REGION SUBALIGN 8) if(CONFIG_USERSPACE) # This is where the app_mem_partition stuff is going to be placed, once it # is generated by gen_app_partitions.py. _app_smem has its own init-copy - # handling in z_data_copy, so put it in RAM_REGIOM rather than DATA_REGION + # handling in arch_data_copy, so put it in RAM_REGION rather than DATA_REGION zephyr_linker_group(NAME APP_SMEM_GROUP GROUP RAM_REGION SYMBOL SECTION) zephyr_linker_symbol(SYMBOL "_app_smem_size" EXPR "@__app_smem_group_size@") zephyr_linker_symbol(SYMBOL "_app_smem_rom_start" EXPR "@__app_smem_group_load_start@") diff --git a/cmake/mcuboot.cmake b/cmake/mcuboot.cmake index 6013eeb5bc314..221666dfd88d8 100644 --- a/cmake/mcuboot.cmake +++ b/cmake/mcuboot.cmake @@ -118,6 +118,14 @@ function(zephyr_mcuboot_tasks) set(imgtool_args --key "${keyfile}" ${imgtool_args}) endif() + if(CONFIG_MCUBOOT_IMGTOOL_UUID_VID) + set(imgtool_args ${imgtool_args} --vid "${CONFIG_MCUBOOT_IMGTOOL_UUID_VID_NAME}") + endif() + + if(CONFIG_MCUBOOT_IMGTOOL_UUID_CID) + set(imgtool_args ${imgtool_args} --cid "${CONFIG_MCUBOOT_IMGTOOL_UUID_CID_NAME}") + endif() + if(CONFIG_MCUBOOT_IMGTOOL_OVERWRITE_ONLY) # Use overwrite-only instead of swap upgrades. set(imgtool_args --overwrite-only --align 1 ${imgtool_args}) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index fc667b06a5484..55ce61fffc6a4 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -449,6 +449,9 @@ macro(zephyr_library_get_current_dir_lib_name base lib_name) # Replace : with __ (C:/zephyrproject => C____zephyrproject) string(REGEX REPLACE ":" "__" name ${name}) + # Replace ~ with - (driver~serial => driver-serial) + string(REGEX REPLACE "~" "-" name ${name}) + set(${lib_name} ${name}) endmacro() diff --git a/cmake/modules/kconfig.cmake b/cmake/modules/kconfig.cmake index 21fe88860948f..de87abfdc1d3a 100644 --- a/cmake/modules/kconfig.cmake +++ b/cmake/modules/kconfig.cmake @@ -134,6 +134,7 @@ zephyr_get(APP_DIR VAR APP_DIR APPLICATION_SOURCE_DIR) set(COMMON_KCONFIG_ENV_SETTINGS PYTHON_EXECUTABLE=${PYTHON_EXECUTABLE} + KCONFIG_ENV_FILE=${KCONFIG_BINARY_DIR}/kconfig_module_dirs.env srctree=${ZEPHYR_BASE} KERNELVERSION=${KERNELVERSION} APPVERSION=${APP_VERSION_STRING} diff --git a/cmake/reports/CMakeLists.txt b/cmake/reports/CMakeLists.txt index fbb4df3a595d8..a65482ac10ac8 100644 --- a/cmake/reports/CMakeLists.txt +++ b/cmake/reports/CMakeLists.txt @@ -11,9 +11,9 @@ elseif(DEFINED WEST_TOPDIR) set(workspace_arg "--workspace=${WEST_TOPDIR}") endif() -foreach(report ram_report rom_report) +foreach(report ram rom) add_custom_target( - ${report} + ${report}_report ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/footprint/size_report -k ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} @@ -21,9 +21,19 @@ foreach(report ram_report rom_report) -o ${CMAKE_BINARY_DIR} ${workspace_arg} -d ${report_depth} - ${flag_for_${report}} + --json ${report}.json + ${flag_for_${report}_report} DEPENDS ${logical_target_for_zephyr_elf} - $ + $ + USES_TERMINAL + WORKING_DIRECTORY ${CMAKE_BINARY_DIR} + ) + add_custom_target( + ${report}_plot + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/footprint/plot.py + ${report}.json + DEPENDS ${report}_report USES_TERMINAL WORKING_DIRECTORY ${CMAKE_BINARY_DIR} ) @@ -51,6 +61,15 @@ if(CONFIG_BUILD_WITH_TFM) USES_TERMINAL WORKING_DIRECTORY ${CMAKE_BINARY_DIR} ) + add_custom_target( + tfm_${report}_plot + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/footprint/plot.py + tfm_${report}.json + DEPENDS tfm_${report}_report + USES_TERMINAL + WORKING_DIRECTORY ${CMAKE_BINARY_DIR} + ) endforeach() add_custom_target( @@ -76,6 +95,15 @@ if(CONFIG_TFM_BL2) USES_TERMINAL WORKING_DIRECTORY ${CMAKE_BINARY_DIR} ) + add_custom_target( + bl2_${report}_plot + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/footprint/plot.py + bl2_${report}.json + DEPENDS bl2_${report}_report + USES_TERMINAL + WORKING_DIRECTORY ${CMAKE_BINARY_DIR} + ) endforeach() add_custom_target( diff --git a/cmake/toolchain/iar/Kconfig b/cmake/toolchain/iar/Kconfig index 4e994e6fc38a3..5733b881eef8c 100644 --- a/cmake/toolchain/iar/Kconfig +++ b/cmake/toolchain/iar/Kconfig @@ -21,7 +21,7 @@ config IAR_DATA_INIT select SKIP_BSS_CLEAR # IAR handles zeroing. help IAR handles initialization of static variables. - Instead of `z_prep_c` calling Zephyrs `z_data_copy` + Instead of `z_prep_c` calling Zephyrs `arch_data_copy` we call IARs own proprietary initialization method which can save time and space. @@ -29,7 +29,7 @@ config IAR_ZEPHYR_INIT bool "Zephyr" help Zephyr handles initialization of static variables. - This is the regular `z_data_copy`. + This is the regular `arch_data_copy`. endchoice diff --git a/doc/_doxygen/groups.dox b/doc/_doxygen/groups.dox index 94d6be6db0fae..0de1c6078f257 100644 --- a/doc/_doxygen/groups.dox +++ b/doc/_doxygen/groups.dox @@ -9,30 +9,29 @@ @defgroup os_services Operating System Services @brief Operating System Services @{ - -@brief MCUmgr -@defgroup mcumgr MCUmgr -@{ -@defgroup mcumgr_transport Transport layers -@{ -@} @} +@defgroup io_interfaces Device Drivers +@brief Interfaces to interact with various hardware peripherals. +@details A collection of hardware-agnostic interfaces used to implement and interact with device + drivers. +@{ @} -@brief Device Driver APIs -@defgroup io_interfaces Device Driver APIs +@defgroup misc_interfaces Miscellaneous Devices +@ingroup io_interfaces +@brief Interfaces for hardware peripherals that do not have a dedicated driver class. @{ @} -@brief Miscellaneous Drivers APIs -@defgroup misc_interfaces Miscellaneous Drivers APIs +@brief Interfaces for USB hardware and associated standards. +@defgroup usb_interfaces USB @ingroup io_interfaces @{ @} -@brief Multi Function Device Drivers APIs -@defgroup mfd_interfaces Multi Function Device Drivers APIs +@brief Interfaces for multi-function devices. +@defgroup mfd_interfaces Multi-function Devices @ingroup io_interfaces @{ @} @@ -48,6 +47,24 @@ @{ @} +@brief Device Management +@defgroup device_mgmt Device Management +@ingroup os_services +@{ +@} + +@brief MCUmgr +@defgroup mcumgr MCUmgr +@ingroup device_mgmt +@{ +@} + +@brief Transport layers for MCUmgr: SMP, UART, etc. +@defgroup mcumgr_transport Transport layers +@ingroup mcumgr +@{ +@} + @brief Connectivity @defgroup connectivity Connectivity @{ @@ -79,7 +96,7 @@ @defgroup modem Modem APIs @ingroup connectivity @since 3.5 -@version 0.1.0 +@version 1.0.0 @{ @} diff --git a/doc/_extensions/zephyr/external_content.py b/doc/_extensions/zephyr/external_content.py index 704e834e96ddb..a2ab020d4c9dd 100644 --- a/doc/_extensions/zephyr/external_content.py +++ b/doc/_extensions/zephyr/external_content.py @@ -108,14 +108,19 @@ def sync_contents(app: Sphinx) -> None: if not f.is_dir() ) + def _pattern_excludes(f): + # backup files + return f.match('.#*') or f.match('*~') + for content in app.config.external_content_contents: prefix_src, glob = content for src in prefix_src.glob(glob): if src.is_dir(): to_copy.extend( - [(f, prefix_src) for f in src.glob("**/*") if not f.is_dir()] + [(f, prefix_src) for f in src.glob("**/*") if + (not f.is_dir() and not _pattern_excludes(f))] ) - else: + elif not _pattern_excludes(src): to_copy.append((src, prefix_src)) for entry in to_copy: diff --git a/doc/_extensions/zephyr/kconfig/__init__.py b/doc/_extensions/zephyr/kconfig/__init__.py index 6bf828a9088e8..cda7430d7ab82 100644 --- a/doc/_extensions/zephyr/kconfig/__init__.py +++ b/doc/_extensions/zephyr/kconfig/__init__.py @@ -70,19 +70,30 @@ ZEPHYR_BASE = Path(__file__).parents[4] -def kconfig_load(app: Sphinx) -> tuple[kconfiglib.Kconfig, dict[str, str]]: +def kconfig_load(app: Sphinx) -> tuple[kconfiglib.Kconfig, kconfiglib.Kconfig, dict[str, str]]: """Load Kconfig""" with TemporaryDirectory() as td: modules = zephyr_module.parse_modules(ZEPHYR_BASE) # generate Kconfig.modules file + kconfig_module_dirs = "" kconfig = "" + sysbuild_kconfig = "" for module in modules: + kconfig_module_dirs += zephyr_module.process_kconfig_module_dir(module.project, + module.meta) kconfig += zephyr_module.process_kconfig(module.project, module.meta) + sysbuild_kconfig += zephyr_module.process_sysbuildkconfig(module.project, module.meta) + + with open(Path(td) / "kconfig_module_dirs.env", "w") as f: + f.write(kconfig_module_dirs) with open(Path(td) / "Kconfig.modules", "w") as f: f.write(kconfig) + with open(Path(td) / "Kconfig.sysbuild.modules", "w") as f: + f.write(sysbuild_kconfig) + # generate dummy Kconfig.dts file kconfig = "" @@ -144,6 +155,14 @@ def kconfig_load(app: Sphinx) -> tuple[kconfiglib.Kconfig, dict[str, str]]: os.environ["BOARD"] = "boards" os.environ["KCONFIG_BOARD_DIR"] = str(Path(td) / "boards") + os.environ["KCONFIG_ENV_FILE"] = str(Path(td) / "kconfig_module_dirs.env") + + # Sysbuild runs first + os.environ["CONFIG_"] = "SB_CONFIG_" + sysbuild_output = kconfiglib.Kconfig(ZEPHYR_BASE / "share" / "sysbuild" / "Kconfig") + + # Normal Kconfig runs second + os.environ["CONFIG_"] = "CONFIG_" # insert external Kconfigs to the environment module_paths = dict() @@ -172,7 +191,7 @@ def kconfig_load(app: Sphinx) -> tuple[kconfiglib.Kconfig, dict[str, str]]: if kconfig.exists(): os.environ[f"ZEPHYR_{name_var}_KCONFIG"] = str(kconfig) - return kconfiglib.Kconfig(ZEPHYR_BASE / "Kconfig"), module_paths + return kconfiglib.Kconfig(ZEPHYR_BASE / "Kconfig"), sysbuild_output, module_paths class KconfigSearchNode(nodes.Element): @@ -332,13 +351,15 @@ def add_option(self, option): def sc_fmt(sc): + prefix = os.environ["CONFIG_"] + if isinstance(sc, kconfiglib.Symbol): if sc.nodes: - return f'CONFIG_{sc.name}' + return f'{prefix}{sc.name}' elif isinstance(sc, kconfiglib.Choice): if not sc.name: return "<choice>" - return f'<choice CONFIG_{sc.name}>' + return f'<choice {prefix}{sc.name}>' return kconfiglib.standard_sc_expr_str(sc) @@ -350,137 +371,139 @@ def kconfig_build_resources(app: Sphinx) -> None: return with progress_message("Building Kconfig database..."): - kconfig, module_paths = kconfig_load(app) + kconfig, sysbuild_kconfig, module_paths = kconfig_load(app) db = list() - for sc in sorted( - chain(kconfig.unique_defined_syms, kconfig.unique_choices), - key=lambda sc: sc.name if sc.name else "", - ): - # skip nameless symbols - if not sc.name: - continue - - # store alternative defaults (from defconfig files) - alt_defaults = list() - for node in sc.nodes: - if "defconfig" not in node.filename: + for kconfig_obj in [kconfig, sysbuild_kconfig]: + os.environ["CONFIG_"] = kconfig_obj.config_prefix + for sc in sorted( + chain(kconfig_obj.unique_defined_syms, kconfig_obj.unique_choices), + key=lambda sc: sc.name if sc.name else "", + ): + # skip nameless symbols + if not sc.name: continue - for value, cond in node.orig_defaults: - fmt = kconfiglib.expr_str(value, sc_fmt) - if cond is not sc.kconfig.y: - fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" - alt_defaults.append([fmt, node.filename]) - - # build list of symbols that select/imply the current one - # note: all reverse dependencies are ORed together, and conditionals - # (e.g. select/imply A if B) turns into A && B. So we first split - # by OR to include all entries, and we split each one by AND to just - # take the first entry. - selected_by = list() - if isinstance(sc, kconfiglib.Symbol) and sc.rev_dep != sc.kconfig.n: - for select in kconfiglib.split_expr(sc.rev_dep, kconfiglib.OR): - sym = kconfiglib.split_expr(select, kconfiglib.AND)[0] - selected_by.append(f"CONFIG_{sym.name}") - - implied_by = list() - if isinstance(sc, kconfiglib.Symbol) and sc.weak_rev_dep != sc.kconfig.n: - for select in kconfiglib.split_expr(sc.weak_rev_dep, kconfiglib.OR): - sym = kconfiglib.split_expr(select, kconfiglib.AND)[0] - implied_by.append(f"CONFIG_{sym.name}") - - # only process nodes with prompt or help - nodes = [node for node in sc.nodes if node.prompt or node.help] - - inserted_paths = list() - for node in nodes: - # avoid duplicate symbols by forcing unique paths. this can - # happen due to dependencies on 0, a trick used by some modules - path = f"{node.filename}:{node.linenr}" - if path in inserted_paths: - continue - inserted_paths.append(path) - - dependencies = None - if node.dep is not sc.kconfig.y: - dependencies = kconfiglib.expr_str(node.dep, sc_fmt) - - defaults = list() - for value, cond in node.orig_defaults: - fmt = kconfiglib.expr_str(value, sc_fmt) - if cond is not sc.kconfig.y: - fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" - defaults.append(fmt) - - selects = list() - for value, cond in node.orig_selects: - fmt = kconfiglib.expr_str(value, sc_fmt) - if cond is not sc.kconfig.y: - fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" - selects.append(fmt) - - implies = list() - for value, cond in node.orig_implies: - fmt = kconfiglib.expr_str(value, sc_fmt) - if cond is not sc.kconfig.y: - fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" - implies.append(fmt) - - ranges = list() - for min, max, cond in node.orig_ranges: - fmt = ( - f"[{kconfiglib.expr_str(min, sc_fmt)}, " - f"{kconfiglib.expr_str(max, sc_fmt)}]" + # store alternative defaults (from defconfig files) + alt_defaults = list() + for node in sc.nodes: + if "defconfig" not in str(node.filename): + continue + + for value, cond in node.orig_defaults: + fmt = kconfiglib.expr_str(value, sc_fmt) + if cond is not sc.kconfig.y: + fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" + alt_defaults.append([fmt, node.filename]) + + # build list of symbols that select/imply the current one + # note: all reverse dependencies are ORed together, and conditionals + # (e.g. select/imply A if B) turns into A && B. So we first split + # by OR to include all entries, and we split each one by AND to just + # take the first entry. + selected_by = list() + if isinstance(sc, kconfiglib.Symbol) and sc.rev_dep != sc.kconfig.n: + for select in kconfiglib.split_expr(sc.rev_dep, kconfiglib.OR): + sym = kconfiglib.split_expr(select, kconfiglib.AND)[0] + selected_by.append(f"{kconfig_obj.config_prefix}{sym.name}") + + implied_by = list() + if isinstance(sc, kconfiglib.Symbol) and sc.weak_rev_dep != sc.kconfig.n: + for select in kconfiglib.split_expr(sc.weak_rev_dep, kconfiglib.OR): + sym = kconfiglib.split_expr(select, kconfiglib.AND)[0] + implied_by.append(f"{kconfig_obj.config_prefix}{sym.name}") + + # only process nodes with prompt or help + nodes = [node for node in sc.nodes if node.prompt or node.help] + + inserted_paths = list() + for node in nodes: + # avoid duplicate symbols by forcing unique paths. this can + # happen due to dependencies on 0, a trick used by some modules + path = f"{node.filename}:{node.linenr}" + if path in inserted_paths: + continue + inserted_paths.append(path) + + dependencies = None + if node.dep is not sc.kconfig.y: + dependencies = kconfiglib.expr_str(node.dep, sc_fmt) + + defaults = list() + for value, cond in node.orig_defaults: + fmt = kconfiglib.expr_str(value, sc_fmt) + if cond is not sc.kconfig.y: + fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" + defaults.append(fmt) + + selects = list() + for value, cond in node.orig_selects: + fmt = kconfiglib.expr_str(value, sc_fmt) + if cond is not sc.kconfig.y: + fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" + selects.append(fmt) + + implies = list() + for value, cond in node.orig_implies: + fmt = kconfiglib.expr_str(value, sc_fmt) + if cond is not sc.kconfig.y: + fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" + implies.append(fmt) + + ranges = list() + for min, max, cond in node.orig_ranges: + fmt = ( + f"[{kconfiglib.expr_str(min, sc_fmt)}, " + f"{kconfiglib.expr_str(max, sc_fmt)}]" + ) + if cond is not sc.kconfig.y: + fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" + ranges.append(fmt) + + choices = list() + if isinstance(sc, kconfiglib.Choice): + for sym in sc.syms: + choices.append(kconfiglib.expr_str(sym, sc_fmt)) + + menupath = "" + iternode = node + while iternode.parent is not iternode.kconfig.top_node: + iternode = iternode.parent + if iternode.prompt: + title = iternode.prompt[0] + else: + title = kconfiglib.standard_sc_expr_str(iternode.item) + menupath = f" > {title}" + menupath + + menupath = "(Top)" + menupath + + filename = str(node.filename) + for name, path in module_paths.items(): + path += "/" + if str(node.filename).startswith(path): + filename = str(node.filename).replace(path, f"/") + break + + db.append( + { + "name": f"{kconfig_obj.config_prefix}{sc.name}", + "prompt": node.prompt[0] if node.prompt else None, + "type": kconfiglib.TYPE_TO_STR[sc.type], + "help": node.help, + "dependencies": dependencies, + "defaults": defaults, + "alt_defaults": alt_defaults, + "selects": selects, + "selected_by": selected_by, + "implies": implies, + "implied_by": implied_by, + "ranges": ranges, + "choices": choices, + "filename": filename, + "linenr": node.linenr, + "menupath": menupath, + } ) - if cond is not sc.kconfig.y: - fmt += f" if {kconfiglib.expr_str(cond, sc_fmt)}" - ranges.append(fmt) - - choices = list() - if isinstance(sc, kconfiglib.Choice): - for sym in sc.syms: - choices.append(kconfiglib.expr_str(sym, sc_fmt)) - - menupath = "" - iternode = node - while iternode.parent is not iternode.kconfig.top_node: - iternode = iternode.parent - if iternode.prompt: - title = iternode.prompt[0] - else: - title = kconfiglib.standard_sc_expr_str(iternode.item) - menupath = f" > {title}" + menupath - - menupath = "(Top)" + menupath - - filename = node.filename - for name, path in module_paths.items(): - path += "/" - if node.filename.startswith(path): - filename = node.filename.replace(path, f"/") - break - - db.append( - { - "name": f"CONFIG_{sc.name}", - "prompt": node.prompt[0] if node.prompt else None, - "type": kconfiglib.TYPE_TO_STR[sc.type], - "help": node.help, - "dependencies": dependencies, - "defaults": defaults, - "alt_defaults": alt_defaults, - "selects": selects, - "selected_by": selected_by, - "implies": implies, - "implied_by": implied_by, - "ranges": ranges, - "choices": choices, - "filename": filename, - "linenr": node.linenr, - "menupath": menupath, - } - ) app.env.kconfig_db = db # type: ignore diff --git a/doc/_extensions/zephyr/kconfig/static/kconfig.mjs b/doc/_extensions/zephyr/kconfig/static/kconfig.mjs index 4f175f4c1cc9f..14c9ffb2f521c 100644 --- a/doc/_extensions/zephyr/kconfig/static/kconfig.mjs +++ b/doc/_extensions/zephyr/kconfig/static/kconfig.mjs @@ -316,10 +316,10 @@ function renderKconfigEntry(entry) { let locationPermalink = getGithubLink(entry.filename, entry.linenr, "blob", zephyr_version); if (locationPermalink) { - const locationPermalink = document.createElement('a'); - locationPermalink.href = locationPermalink; - locationPermalink.appendChild(locationElement); - renderKconfigPropLiteralElement(props, 'Location', locationPermalink); + const locationPermalinkElement = document.createElement('a'); + locationPermalinkElement.href = locationPermalink; + locationPermalinkElement.appendChild(locationElement); + renderKconfigPropLiteralElement(props, 'Location', locationPermalinkElement); } else { renderKconfigPropLiteralElement(props, 'Location', locationElement); } diff --git a/doc/_scripts/gen_boards_catalog.py b/doc/_scripts/gen_boards_catalog.py index e4322e0d24aa5..42f55a16436cb 100755 --- a/doc/_scripts/gen_boards_catalog.py +++ b/doc/_scripts/gen_boards_catalog.py @@ -302,8 +302,9 @@ def get_catalog(generate_hw_features=False, hw_features_vendor_filter=None): if node.matching_compat is None: continue - # skip "zephyr,xxx" compatibles - if node.matching_compat.startswith("zephyr,"): + # skip "zephyr,xxx" compatibles (unless board is native_sim, since in this + # case the "zephyr,"-prefixed peripherals are legitimate) + if node.matching_compat.startswith("zephyr,") and board.name != "native_sim": continue description = DeviceTreeUtils.get_cached_description(node) diff --git a/doc/_scripts/redirects.py b/doc/_scripts/redirects.py index 79174d1d0d988..68100002e1802 100644 --- a/doc/_scripts/redirects.py +++ b/doc/_scripts/redirects.py @@ -16,7 +16,11 @@ # zephyr-keep-sorted-start ('application/index', 'develop/application/index'), ('boards/arduino/uno_r4_minima/doc/index', 'boards/arduino/uno_r4/doc/index'), + ('boards/arm/fvp_baser_aemv8r/doc/aarch32', 'boards/arm/fvp_baser_aemv8r/doc/index'), + ('boards/arm/fvp_baser_aemv8r/doc/aarch64', 'boards/arm/fvp_baser_aemv8r/doc/index'), + ('boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds', 'boards/arm/fvp_baser_aemv8r/doc/index'), ('boards/nordic/nrf54l20pdk/doc/index', 'boards/nordic/nrf54lm20dk/doc/index'), + ('boards/panasonic/panb511evb/doc/index', 'boards/panasonic/panb611evb/doc/index'), ('boards/phytec/mimx8mm_phyboard_polis/doc/index', 'boards/phytec/phyboard_polis/doc/index'), ('boards/phytec/mimx8mp_phyboard_pollux/doc/index', 'boards/phytec/phyboard_pollux/doc/index'), ('boards/rak/index', 'boards/rakwireless/index'), @@ -167,6 +171,8 @@ ('guides/west/zephyr-cmds', 'develop/west/zephyr-cmds'), ('guides/zephyr_cmake_package', 'build/zephyr_cmake_package'), ('hardware/peripherals/eeprom', 'hardware/peripherals/eeprom/index'), + ('hardware/peripherals/mipi_dbi', 'hardware/peripherals/display/index'), + ('hardware/peripherals/mipi_dsi', 'hardware/peripherals/display/index'), ('hardware/peripherals/sensor', 'hardware/peripherals/sensor/index'), ('kernel/libc/index', 'develop/languages/c/index'), ('reference/api/api_lifecycle', 'develop/api/api_lifecycle'), @@ -305,9 +311,13 @@ ('samples/sensor/wsen_hids/README', 'samples/sensor/sensor'), ('samples/sensor/wsen_itds/README', 'samples/sensor/sensor'), ('samples/shields/npm1300_ek/doc/index', 'samples/shields/npm13xx_ek/doc/index'), + ('samples/shields/npm13xx_ek/doc/index', 'samples/shields/npm13xx_ek/index'), + ('samples/shields/npm2100_ek/doc/index', 'samples/shields/npm2100_ek/index'), + ('samples/shields/npm6001_ek/doc/index', 'samples/shields/npm6001_ek/index'), ('samples/subsys/video/capture/README', 'samples/drivers/video/capture/README'), ('samples/subsys/video/tcpserversink/README', 'samples/drivers/video/tcpserversink/README'), ('samples/subsys/video/video', 'samples/drivers/video/video'), + ('services/modbus/index', 'connectivity/modbus/index'), ('services/portability/posix', 'services/portability/posix/index'), ('services/secure_storage', 'services/storage/secure_storage/index'), ('services/settings/index', 'services/storage/settings/index'), diff --git a/doc/build/dts/api/api.rst b/doc/build/dts/api/api.rst index ffa56e5ce5aef..31cfb3842edc6 100644 --- a/doc/build/dts/api/api.rst +++ b/doc/build/dts/api/api.rst @@ -399,6 +399,8 @@ device. into * - zephyr,console - Sets UART device used by console driver + * - zephyr,crc + - Selects the CRC device used as an accelerator by the CRC subsystem * - zephyr,display - Sets the default display controller * - zephyr,keyboard-scan diff --git a/doc/conf.py b/doc/conf.py index f995ad5288d7b..3faa25963e712 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -114,6 +114,14 @@ else: exclude_patterns.append("**/*west-not-found*") +# Ensure only one of the two top-level indexes ever gets included. +# This is a workaround for Sphinx issuing INFO notices about being referenced in +# multiple toctrees. +if tags.has("convertimages"): # pylint: disable=undefined-variable # noqa: F821 + exclude_patterns.append("index.rst") +else: + exclude_patterns.append("index-tex.rst") + pygments_style = "sphinx" highlight_language = "none" diff --git a/doc/connectivity/bluetooth/autopts/autopts-linux.rst b/doc/connectivity/bluetooth/autopts/autopts-linux.rst index d97b5e8dcbd1d..d73ed6a9dbcfe 100644 --- a/doc/connectivity/bluetooth/autopts/autopts-linux.rst +++ b/doc/connectivity/bluetooth/autopts/autopts-linux.rst @@ -13,11 +13,11 @@ Supported methods to test zephyr bluetooth host: - Testing Zephyr Host Stack on QEMU -- Testing Zephyr Host Stack on :ref:`native_sim ` +- Testing Zephyr Host Stack on :zephyr:board:`native_sim ` - Testing Zephyr combined (controller + host) build on Real hardware (such as nRF52) -For running with QEMU or :ref:`native_sim `, see :ref:`bluetooth_qemu_native`. +For running with QEMU or :zephyr:board:`native_sim `, see :ref:`bluetooth_qemu_native`. .. contents:: :local: @@ -325,7 +325,7 @@ Testing Zephyr Host Stack on QEMU: ~/zephyrproject/build/zephyr/zephyr.elf -i SERVER_IP -l LOCAL_IP -Testing Zephyr Host Stack on :ref:`native_sim `: +Testing Zephyr Host Stack on :zephyr:board:`native_sim `: .. code-block:: diff --git a/doc/connectivity/bluetooth/bluetooth-dev.rst b/doc/connectivity/bluetooth/bluetooth-dev.rst index 999eb8f3d4168..a28a85474e1ee 100644 --- a/doc/connectivity/bluetooth/bluetooth-dev.rst +++ b/doc/connectivity/bluetooth/bluetooth-dev.rst @@ -76,7 +76,7 @@ This setup relies on a "dual-chip" :ref:`configuration ` which is comprised of the following devices: #. A :ref:`Host-only ` application running in the - :ref:`QEMU ` emulator or the :ref:`native_sim ` native + :ref:`QEMU ` emulator or the :zephyr:board:`native_sim ` native port of Zephyr #. A Controller, which can be one of the following types: @@ -117,7 +117,7 @@ native_sim .. note:: This is currently only available on GNU/Linux -The :ref:`native_sim ` target builds your Zephyr application +The :zephyr:board:`native_sim ` target builds your Zephyr application with the Zephyr kernel, and some minimal HW emulation as a native Linux executable. @@ -146,8 +146,8 @@ These boards, use: * The POSIX arch and native simulator to emulate the processor, and run natively on your host. * `Models of the nrf5x HW `_ -Just like with the :ref:`native_sim ` target, the build result is a normal Linux -executable. +Just like with the :zephyr:board:`native_sim ` target, the build result is a normal +Linux executable. You can find more information on how to run simulations with one or several devices in either of :ref:`these boards's documentation `. diff --git a/doc/connectivity/bluetooth/bluetooth-tools.rst b/doc/connectivity/bluetooth/bluetooth-tools.rst index 3d8c314a3f909..59112aff67cfe 100644 --- a/doc/connectivity/bluetooth/bluetooth-tools.rst +++ b/doc/connectivity/bluetooth/bluetooth-tools.rst @@ -84,7 +84,7 @@ Running on QEMU or native_sim ***************************** It's possible to run Bluetooth applications using either the :ref:`QEMU -emulator` or :ref:`native_sim `. +emulator` or :zephyr:board:`native_sim `. In either case, a Bluetooth controller needs to be exported from the host OS (Linux) to the emulator. For this purpose you will need some tools @@ -103,7 +103,7 @@ The host OS's Bluetooth controller is connected in the following manner: command-line option passed to the native_sim executable: ``--bt-dev=hci0`` On the host side, BlueZ allows you to export its Bluetooth controller -through a so-called user channel for QEMU and :ref:`native_sim ` to use. +through a so-called user channel for QEMU and :zephyr:board:`native_sim ` to use. .. note:: You only need to run ``btproxy`` when using QEMU. native_sim handles @@ -147,7 +147,7 @@ building and running a sample: the :literal:`bt-server-bredr` UNIX socket, letting the application access the Bluetooth controller. -* To run a Bluetooth application in :ref:`native_sim `, first build it: +* To run a Bluetooth application in :zephyr:board:`native_sim `, first build it: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/ diff --git a/doc/connectivity/bluetooth/shell/audio/bap_broadcast_assistant.rst b/doc/connectivity/bluetooth/shell/audio/bap_broadcast_assistant.rst index 197cbe868889a..1280a7d0e2656 100644 --- a/doc/connectivity/bluetooth/shell/audio/bap_broadcast_assistant.rst +++ b/doc/connectivity/bluetooth/shell/audio/bap_broadcast_assistant.rst @@ -38,6 +38,8 @@ subscribe to all notifications. [] [] [] add_broadcast_id : Add a source by broadcast ID [] [] + add_broadcast_name: Add a source by broadcast name + [] [] add_pa_sync : Add a PA sync as a source [bis_index [bis_index [bix_index [...]]]]> mod_src : Set sync [ | "unknown"] [] diff --git a/doc/connectivity/bluetooth/shell/audio/cap.rst b/doc/connectivity/bluetooth/shell/audio/cap.rst index a620981b60ca4..47ff4781e0cac 100644 --- a/doc/connectivity/bluetooth/shell/audio/cap.rst +++ b/doc/connectivity/bluetooth/shell/audio/cap.rst @@ -208,13 +208,15 @@ The following commands will setup a CAP broadcast source using the 16_2_1 preset bt init bap init - bt adv-create nconn-nscan ext-adv name + bt adv-create nconn-nscan ext-adv bt per-adv-param bap preset broadcast 16_2_1 cap_initiator ac_12 - bt adv-data discov + bt adv-data dev-name discov bt per-adv-data cap_initiator broadcast_start + bt adv-start + bt per-adv on The broadcast source is created by the :code:`cap_initiator ac_12`, :code:`cap_initiator ac_13`, diff --git a/doc/connectivity/bluetooth/shell/audio/ccp.rst b/doc/connectivity/bluetooth/shell/audio/ccp.rst index 0fbf3ed2181df..8aab2829ded49 100644 --- a/doc/connectivity/bluetooth/shell/audio/ccp.rst +++ b/doc/connectivity/bluetooth/shell/audio/ccp.rst @@ -13,12 +13,18 @@ The Server can be controlled locally, or by a remote device (when in a call). Fo example a remote device may initiate a call to the server, or the Server may initiate a call to remote device, without a client. +For all commands that take an optional :code:`index`, if the index is not supplied then it defaults +to :code:`0` which is the GTBS bearer. + .. code-block:: console ccp_call_control_server --help ccp_call_control_server - Bluetooth CCP Call Control Server shell commands Subcommands: - init : Initialize CCP Call Control Server + init : Initialize CCP Call Control Server + set_bearer_name : Set bearer name [index] + get_bearer_name : Get bearer name [index] + Example Usage ============= @@ -34,6 +40,25 @@ Setup Registered bearer[1] uart:~$ bt connect xx:xx:xx:xx:xx:xx public +Setting and getting the bearer name +----------------------------------- + +.. code-block:: console + + uart:~$ ccp_call_control_server get_bearer_name + Bearer[0] name: Generic TBS + uart:~$ ccp_call_control_server set_bearer_name "New name" + Bearer[0] name: New name + uart:~$ ccp_call_control_server get_bearer_name + Bearer[0] name: New name + uart:~$ ccp_call_control_server get_bearer_name 1 + Bearer[1] name: Telephone Bearer #1 + uart:~$ ccp_call_control_server set_bearer_name 1 "New TBS name" + Bearer[1] name: New TBS name + uart:~$ ccp_call_control_server get_bearer_name 1 + Bearer[1] name: New TBS name + + Call Control Client ******************* The Call Control Client is a role that typically resides on resource constrained devices such as diff --git a/doc/connectivity/bluetooth/shell/host/gap.rst b/doc/connectivity/bluetooth/shell/host/gap.rst index 3e2e2f477bf11..c7c8753fbd187 100644 --- a/doc/connectivity/bluetooth/shell/host/gap.rst +++ b/doc/connectivity/bluetooth/shell/host/gap.rst @@ -185,7 +185,7 @@ Let's now have a look at some extended advertising features. To enable extended .. code-block:: console - uart:~$ bt adv-create conn-nscan ext-adv name-ad + uart:~$ bt adv-create conn-nscan ext-adv Created adv id: 0, adv: 0x200022f0 uart:~$ bt adv-start Advertiser[0] 0x200022f0 set started diff --git a/doc/connectivity/bluetooth/shell/host/iso.rst b/doc/connectivity/bluetooth/shell/host/iso.rst index f79b1374123ce..96200001583f9 100644 --- a/doc/connectivity/bluetooth/shell/host/iso.rst +++ b/doc/connectivity/bluetooth/shell/host/iso.rst @@ -23,6 +23,8 @@ Commands term-big :Terminate a BIG +Unicast examples +**************** 1. [Central] Create CIG: Requires to be connected: @@ -62,3 +64,65 @@ Requires to be connected: uart:~$ iso disconnect ISO Disconnect pending... ISO Channel 0x20000f88 disconnected with reason 0x16 + + +Broadcast examples +****************** + +Setting up broadcaster +====================== + +.. code-block:: console + + uart:~$ bt init + Bluetooth initialized + uart:~$ bt adv-create nconn-nscan ext-adv + Created adv id: 0, adv: 0x200025d0 + uart:~$ bt per-adv-param + uart:~$ iso create-big + BIG created + ISO Channel 0x200008c0 connected + uart:~$ + uart:~$ bt adv-start + Advertiser[0] 0x200025d0 set started + uart:~$ + uart:~$ bt per-adv on + Periodic advertising started + uart:~$ + uart:~$ iso broadcast + send: 247 bytes of data with PSN 4350 + ISO broadcasting... + +If encrypted broadcast is required, then a broadcast code can be provided as + +.. code-block:: console + + uart:~$ iso create-big enc 00112233445566778899aabbccddffff + BIG created + +Setting up sync receiver +======================== + +.. code-block:: console + + uart:~$ bt init + Bluetooth initialized + uart:~$ bt scan on + [DEVICE]: 42:0F:7A:40:AE:21 (random), AD evt type 5, RSSI -27 C:0 S:0 D:0 SR:0 E:1 Prim: LE 1M, Secn: LE 2M, Interval: 0x0780 (2400000 us), SID: 0x0 + uart:~$ bt per-adv-sync-create 42:0F:7A:40:AE:21 (random) 0 + Per adv sync pending + PER_ADV_SYNC[0]: [DEVICE]: 42:0F:7A:40:AE:21 (random) synced, Interval 0x0780 (2400000 us), PHY LE 2M, SD 0x0000, PAST peer not present + PER_ADV_SYNC[0]: [DEVICE]: 42:0F:7A:40:AE:21 (random), tx_power 127, RSSI -28, CTE 0, data length 0 + BIG_INFO PER_ADV_SYNC[0]: [DEVICE]: 42:0F:7A:40:AE:21 (random), sid 0x00, num_bis 1, nse 0x04, interval 0x0008 (10000 us), bn 0x01, pto 0x01, irc 0x03, max_pdu 0x00f7, sdu_interval 0x2710, max_sdu 0x00f7, phy LE 2M, framing 0x00, not encrypted + uart:~$ iso sync-big 1 + BIG syncing + ISO Channel 0x200008c0 connected + + +If encrypted broadcast is required, then a broadcast code can be provided as + +.. code-block:: console + + uart:~$ iso sync-big 1 enc 00112233445566778899aabbccddffff + BIG syncing + ISO Channel 0x200008c0 connected diff --git a/doc/connectivity/index.rst b/doc/connectivity/index.rst index be81417d0ba6d..0ba8e078be2c9 100644 --- a/doc/connectivity/index.rst +++ b/doc/connectivity/index.rst @@ -11,3 +11,4 @@ Connectivity networking/index.rst lora_lorawan/index.rst usb/index.rst + modbus/index.rst diff --git a/doc/connectivity/lora_lorawan/index.rst b/doc/connectivity/lora_lorawan/index.rst index 7098c05b4a662..0e67334425f75 100644 --- a/doc/connectivity/lora_lorawan/index.rst +++ b/doc/connectivity/lora_lorawan/index.rst @@ -23,12 +23,25 @@ to the internet through a gateway. The Zephyr implementation is based on Semtech's `LoRaMac-node library`_, which is included as a Zephyr module. +.. note:: + + ``LoRaMac-node`` has been deprecated by Semtech in favor of + `LoRa Basics Modem`_. Porting the Zephyr API's to use + ``LoRa Basics Modem`` as the backend is in progress. + + Currently, only the base LoRa API is supported for the SX1261, SX1262, + SX1272 and SX1276 chipsets through + :kconfig:option:`CONFIG_LORA_MODULE_BACKEND_LORA_BASICS_MODEM`. + + The LoRaWAN specification is published by the `LoRa Alliance`_. .. _`Semtech Corporation`: https://www.semtech.com/ .. _`LoRaMac-node library`: https://github.com/Lora-net/LoRaMac-node +.. _`LoRa Basics Modem`: https://github.com/Lora-net/SWL2001 + .. _`LoRa Alliance`: https://lora-alliance.org/ Configuration Options @@ -82,7 +95,7 @@ API Reference LoRa PHY ======== -.. doxygengroup:: lora_api +.. doxygengroup:: lora_interface LoRaWAN ======= diff --git a/doc/services/modbus/index.rst b/doc/connectivity/modbus/index.rst similarity index 100% rename from doc/services/modbus/index.rst rename to doc/connectivity/modbus/index.rst diff --git a/doc/connectivity/networking/api/gptp.rst b/doc/connectivity/networking/api/gptp.rst index fab99abd26adb..21a78498be108 100644 --- a/doc/connectivity/networking/api/gptp.rst +++ b/doc/connectivity/networking/api/gptp.rst @@ -40,7 +40,7 @@ Boards supported: - :zephyr:board:`nucleo_h745zi_q` - :zephyr:board:`nucleo_f767zi` - :zephyr:board:`sam_e70_xplained` -- :ref:`native_sim` (only usable for simple testing, limited capabilities +- :zephyr:board:`native_sim` (only usable for simple testing, limited capabilities due to lack of hardware clock) - :zephyr:board:`qemu_x86` (emulated, limited capabilities due to lack of hardware clock) diff --git a/doc/connectivity/networking/api/latmon.rst b/doc/connectivity/networking/api/latmon.rst index 2679953be1fec..f3cd5ccdca474 100644 --- a/doc/connectivity/networking/api/latmon.rst +++ b/doc/connectivity/networking/api/latmon.rst @@ -44,7 +44,7 @@ Socket Creation =============== The :c:func:`net_latmon_get_socket()` function is called to create and configure a TCP socket to -communicate with the Latmus service. A connection address can be specified as a paramenter to +communicate with the Latmus service. A connection address can be specified as a parameter to bind the socket to a specific interface and port. Connection Handling diff --git a/doc/connectivity/networking/api/ocpp.rst b/doc/connectivity/networking/api/ocpp.rst index 6c71b473c0653..06962803c44ad 100644 --- a/doc/connectivity/networking/api/ocpp.rst +++ b/doc/connectivity/networking/api/ocpp.rst @@ -25,7 +25,7 @@ with payload in json format. The library can be enabled with core profile is supported. OCPP charge point (CP) require a Central System (CS) server to connect, an open -source SteVe server shall be setup locally for devlopment purpose, See +source SteVe server shall be setup locally for development purpose, See `SteVe server `_ for more information about the setup. @@ -72,7 +72,7 @@ A filled CP, CS structure and user callback needs to be passed in ocpp_init. ret = ocpp_init(&cpi, &csi, user_notify_cb, NULL); A unique session must open for each physical connector before any ocpp -transcation API call. +transaction API call. .. code-block:: c diff --git a/doc/connectivity/networking/eth_bridge_native_sim_setup.rst b/doc/connectivity/networking/eth_bridge_native_sim_setup.rst index 20554e376db37..d64bf3b3da041 100644 --- a/doc/connectivity/networking/eth_bridge_native_sim_setup.rst +++ b/doc/connectivity/networking/eth_bridge_native_sim_setup.rst @@ -8,12 +8,12 @@ Ethernet bridge with native_sim board :depth: 2 This document describes how to set up a bridged Ethernet network between a (Linux) host -and a Zephyr application running in a :ref:`native_sim ` board. +and a Zephyr application running in a :zephyr:board:`native_sim ` board. This setup is useful when testing the Ethernet bridging feature that can be enabled with :kconfig:option:`CONFIG_NET_ETHERNET_BRIDGE` Kconfig option. In this setup, the net-tools configuration creates two host network interfaces ``zeth0`` and ``zeth1`` and connects them -to Zephyr's :ref:`native_sim ` application. +to Zephyr's :zephyr:board:`native_sim ` application. First create the host interfaces. In this example two interfaces are created. diff --git a/doc/connectivity/networking/native_sim_setup.rst b/doc/connectivity/networking/native_sim_setup.rst index 4e6257d22d42a..5eb8ad211c0bf 100644 --- a/doc/connectivity/networking/native_sim_setup.rst +++ b/doc/connectivity/networking/native_sim_setup.rst @@ -11,7 +11,7 @@ Using virtual/TAP Ethernet driver ********************************* This paragraph describes how to set up a virtual network between a (Linux) host -and a Zephyr application running in a :ref:`native_sim ` board. +and a Zephyr application running in a :zephyr:board:`native_sim ` board. In this example, the :zephyr:code-sample:`sockets-echo-server` sample application from the Zephyr source distribution is run in native_sim board. The Zephyr diff --git a/doc/connectivity/usb/device/usb_device.rst b/doc/connectivity/usb/device/usb_device.rst index bd72bb4605a29..6d2292e26041b 100644 --- a/doc/connectivity/usb/device/usb_device.rst +++ b/doc/connectivity/usb/device/usb_device.rst @@ -459,7 +459,7 @@ Testing over USBIP in native_sim A virtual USB controller implemented through USBIP might be used to test the USB device stack. Follow the general build procedure to build the USB sample for -the :ref:`native_sim ` configuration. +the :zephyr:board:`native_sim ` configuration. Run built sample with: diff --git a/doc/connectivity/usb/host/usbip.rst b/doc/connectivity/usb/host/usbip.rst index 5c6495406ccc1..ceebe7228117f 100644 --- a/doc/connectivity/usb/host/usbip.rst +++ b/doc/connectivity/usb/host/usbip.rst @@ -63,7 +63,7 @@ USB/IP with native_sim ********************** The preferred method to develop with USB/IP support enabled is to use -:ref:`native_sim `. Use on real hardware is not really tested yet. +:zephyr:board:`native_sim `. Use on real hardware is not really tested yet. USB/IP requires a network connection, see :ref:`networking_with_native_sim` for how to set up the interface on the client side. diff --git a/doc/contribute/coding_guidelines/index.rst b/doc/contribute/coding_guidelines/index.rst index 9a915beeb99ad..1b9065215d297 100644 --- a/doc/contribute/coding_guidelines/index.rst +++ b/doc/contribute/coding_guidelines/index.rst @@ -28,75 +28,67 @@ should comply with the rules listed below. .. list-table:: Main rules :header-rows: 1 - :widths: 12 45 15 14 12 + :widths: 12 50 15 15 * - Zephyr rule - Description - - MISRA-C 2012 rule - - MISRA-C severity + - MISRA-C 2012 reference - CERT C reference .. _MisraC_Dir_1_1: * - 1 - Any implementation-defined behaviour on which the output of the program depends shall be documented and understood - `Dir 1.1 `_ - - Required - - `MSC09-C `_ + - | `FLP30-C `_ + | `MSC09-C `_ + | `EXP11-C `_ .. _MisraC_Dir_2_1: * - 2 - All source files shall compile without any compilation errors - `Dir 2.1 `_ - - Required - N/A .. _MisraC_Dir_3_1: * - 3 - All code shall be traceable to documented requirements - `Dir 3.1 `_ - - Required - N/A .. _MisraC_Dir_4_1: * - 4 - Run-time failures shall be minimized - `Dir 4.1 `_ - - Required - N/A .. _MisraC_Dir_4_2: * - 5 - All usage of assembly language should be documented - `Dir 4.2 `_ - - Advisory - N/A .. _MisraC_Dir_4_4: * - 6 - Sections of code should not be “commented out” - `Dir 4.4 `_ - - Advisory - `MSC04-C `_ .. _MisraC_Dir_4_5: * - 7 - Identifiers in the same name space with overlapping visibility should be typographically unambiguous - `Dir 4.5 `_ - - Advisory - `DCL02-C `_ .. _MisraC_Dir_4_6: * - 8 - typedefs that indicate size and signedness should be used in place of the basic numerical types - `Dir 4.6 `_ - - Advisory - N/A .. _MisraC_Dir_4_7: * - 9 - If a function returns error information, then that error information shall be tested - `Dir 4.7 `_ - - Required - N/A .. _MisraC_Dir_4_8: @@ -104,63 +96,56 @@ should comply with the rules listed below. - If a pointer to a structure or union is never dereferenced within a translation unit, then the implementation of the object should be hidden - | `Dir 4.8 example 1 `_ | `Dir 4.8 example 2 `_ - - Advisory - `DCL12-C `_ .. _MisraC_Dir_4_9: * - 11 - A function should be used in preference to a function-like macro where they are interchangeable - `Dir 4.9 `_ - - Advisory - `PRE00-C `_ .. _MisraC_Dir_4_10: * - 12 - Precautions shall be taken in order to prevent the contents of a header file being included more than once - `Dir 4.10 `_ - - Required - `PRE06-C `_ .. _MisraC_Dir_4_11: * - 13 - The validity of values passed to library functions shall be checked - `Dir 4.11 `_ - - Required - N/A .. _MisraC_Dir_4_12: * - 14 - Dynamic memory allocation shall not be used - `Dir 4.12 `_ - - Required - - `STR01-C `_ + - | `API03-C `_ + | `API04-C `_ + | `STR01-C `_ .. _MisraC_Dir_4_13: * - 15 - Functions which are designed to provide operations on a resource should be called in an appropriate sequence - `Dir 4.13 `_ - - Advisory - N/A .. _MisraC_Dir_4_14: * - 16 - The validity of values received from external sources shall be checked - `Dir 4.14 `_ - - Required - N/A .. _MisraC_Rule_1_2: * - 17 - Language extensions should not be used - `Rule 1.2 `_ - - Advisory - `MSC04-C `_ .. _MisraC_Rule_1_3: * - 18 - There shall be no occurrence of undefined or critical unspecified behaviour - `Rule 1.3 `_ - - Required - N/A .. _MisraC_Rule_2_1: @@ -168,63 +153,55 @@ should comply with the rules listed below. - A project shall not contain unreachable code - | `Rule 2.1 example 1 `_ | `Rule 2.1 example 2 `_ - - Required - - `MSC07-C `_ + - `MSC12-C `_ .. _MisraC_Rule_2_2: * - 20 - There shall be no dead code - `Rule 2.2 `_ - - Required - - `MSC12-C `_ + - | `DCL22-C `_ + | `MSC12-C `_ .. _MisraC_Rule_2_3: * - 21 - A project should not contain unused type declarations - `Rule 2.3 `_ - - Advisory - N/A .. _MisraC_Rule_2_6: * - 22 - A function should not contain unused label declarations - `Rule 2.6 `_ - - Advisory - N/A .. _MisraC_Rule_2_7: * - 23 - There should be no unused parameters in functions - `Rule 2.7 `_ - - Advisory - N/A .. _MisraC_Rule_3_1: * - 24 - The character sequences /* and // shall not be used within a comment - `Rule 3.1 `_ - - Required - `MSC04-C `_ .. _MisraC_Rule_3_2: * - 25 - Line-splicing shall not be used in // comments - `Rule 3.2 `_ - - Required - N/A .. _MisraC_Rule_4_1: * - 26 - Octal and hexadecimal escape sequences shall be terminated - `Rule 4.1 `_ - - Required - `MSC09-C `_ .. _MisraC_Rule_4_2: * - 27 - Trigraphs should not be used - `Rule 4.2 `_ - - Advisory - `PRE07-C `_ .. _MisraC_Rule_5_1: @@ -232,49 +209,43 @@ should comply with the rules listed below. - External identifiers shall be distinct - | `Rule 5.1 example 1 `_ | `Rule 5.1 example 2 `_ - - Required - `DCL23-C `_ .. _MisraC_Rule_5_2: * - 29 - Identifiers declared in the same scope and name space shall be distinct - `Rule 5.2 `_ - - Required - `DCL23-C `_ .. _MisraC_Rule_5_3: * - 30 - An identifier declared in an inner scope shall not hide an identifier declared in an outer scope - `Rule 5.3 `_ - - Required - - `DCL23-C `_ + - | `DCL01-C `_ + | `DCL23-C `_ .. _MisraC_Rule_5_4: * - 31 - Macro identifiers shall be distinct - `Rule 5.4 `_ - - Required - `DCL23-C `_ .. _MisraC_Rule_5_5: * - 32 - Identifiers shall be distinct from macro names - `Rule 5.5 `_ - - Required - `DCL23-C `_ .. _MisraC_Rule_5_6: * - 33 - A typedef name shall be a unique identifier - `Rule 5.6 `_ - - Required - N/A .. _MisraC_Rule_5_7: * - 34 - A tag name shall be a unique identifier - `Rule 5.7 `_ - - Required - N/A .. _MisraC_Rule_5_8: @@ -282,7 +253,6 @@ should comply with the rules listed below. - Identifiers that define objects or functions with external linkage shall be unique - | `Rule 5.8 example 1 `_ | `Rule 5.8 example 2 `_ - - Required - N/A .. _MisraC_Rule_5_9: @@ -290,85 +260,77 @@ should comply with the rules listed below. - Identifiers that define objects or functions with internal linkage should be unique - | `Rule 5.9 example 1 `_ | `Rule 5.9 example 2 `_ - - Advisory - N/A .. _MisraC_Rule_6_1: * - 37 - Bit-fields shall only be declared with an appropriate type - `Rule 6.1 `_ - - Required - `INT14-C `_ .. _MisraC_Rule_6_2: * - 38 - Single-bit named bit fields shall not be of a signed type - `Rule 6.2 `_ - - Required - `INT14-C `_ .. _MisraC_Rule_7_1: * - 39 - Octal constants shall not be used - `Rule 7.1 `_ - - Required - `DCL18-C `_ .. _MisraC_Rule_7_2: * - 40 - A u or U suffix shall be applied to all integer constants that are represented in an unsigned type - `Rule 7.2 `_ - - Required - N/A .. _MisraC_Rule_7_3: * - 41 - The lowercase character l shall not be used in a literal suffix - `Rule 7.3 `_ - - Required - `DCL16-C `_ .. _MisraC_Rule_7_4: * - 42 - A string literal shall not be assigned to an object unless the objects type is pointer to const-qualified char - `Rule 7.4 `_ - - Required - N/A .. _MisraC_Rule_8_1: * - 43 - Types shall be explicitly specified - `Rule 8.1 `_ - - Required - - N/A + - `DCL31-C `_ .. _MisraC_Rule_8_2: * - 44 - Function types shall be in prototype form with named parameters - `Rule 8.2 `_ - - Required - - `DCL20-C `_ + - | `DCL07-C `_ + | `DCL20-C `_ + | `DCL36-C `_ + | `EXP37-C `_ .. _MisraC_Rule_8_3: * - 45 - All declarations of an object or function shall use the same names and type qualifiers - `Rule 8.3 `_ - - Required - N/A .. _MisraC_Rule_8_4: * - 46 - A compatible declaration shall be visible when an object or function with external linkage is defined - `Rule 8.4 `_ - - Required - - N/A + - | `DCL36-C `_ + | `DCL40-C `_ .. _MisraC_Rule_8_5: * - 47 - An external object or function shall be declared once in one and only one file - | `Rule 8.5 example 1 `_ | `Rule 8.5 example 2 `_ - - Required - N/A .. _MisraC_Rule_8_6: @@ -376,196 +338,187 @@ should comply with the rules listed below. - An identifier with external linkage shall have exactly one external definition - | `Rule 8.6 example 1 `_ | `Rule 8.6 example 2 `_ - - Required - N/A .. _MisraC_Rule_8_8: * - 49 - The static storage class specifier shall be used in all declarations of objects and functions that have internal linkage - `Rule 8.8 `_ - - Required - - `DCL15-C `_ + - | `DCL15-C `_ + | `DCL36-C `_ .. _MisraC_Rule_8_9: * - 50 - An object should be defined at block scope if its identifier only appears in a single function - `Rule 8.9 `_ - - Advisory - `DCL19-C `_ .. _MisraC_Rule_8_10: * - 51 - An inline function shall be declared with the static storage class - `Rule 8.10 `_ - - Required - N/A .. _MisraC_Rule_8_12: * - 52 - Within an enumerator list, the value of an implicitly-specified enumeration constant shall be unique - `Rule 8.12 `_ - - Required - `INT09-C `_ .. _MisraC_Rule_8_14: * - 53 - The restrict type qualifier shall not be used - `Rule 8.14 `_ - - Required - - N/A + - `EXP43-C `_ .. _MisraC_Rule_9_1: * - 54 - The value of an object with automatic storage duration shall not be read before it has been set - `Rule 9.1 `_ - - Mandatory - N/A .. _MisraC_Rule_9_2: * - 55 - The initializer for an aggregate or union shall be enclosed in braces - `Rule 9.2 `_ - - Required - N/A .. _MisraC_Rule_9_3: * - 56 - Arrays shall not be partially initialized - `Rule 9.3 `_ - - Required - N/A .. _MisraC_Rule_9_4: * - 57 - An element of an object shall not be initialized more than once - `Rule 9.4 `_ - - Required - N/A .. _MisraC_Rule_9_5: * - 58 - Where designated initializers are used to initialize an array object the size of the array shall be specified explicitly - `Rule 9.5 `_ - - Required - - N/A + - `ARR02-C `_ .. _MisraC_Rule_10_1: * - 59 - Operands shall not be of an inappropriate essential type - `Rule 10.1 `_ - - Required - - `STR04-C `_ + - | `INT02-C `_ + | `INT07-C `_ + | `INT12-C `_ + | `INT31-C `_ + | `STR04-C `_ + | `STR34-C `_ .. _MisraC_Rule_10_2: * - 60 - Expressions of essentially character type shall not be used inappropriately in addition and subtraction operations - `Rule 10.2 `_ - - Required - - `STR04-C `_ + - | `STR04-C `_ + | `STR34-C `_ .. _MisraC_Rule_10_3: * - 61 - The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category - `Rule 10.3 `_ - - Required - - `STR04-C `_ + - | `INT02-C `_ + | `INT07-C `_ + | `INT31-C `_ + | `STR04-C `_ + | `STR34-C `_ .. _MisraC_Rule_10_4: * - 62 - Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category - `Rule 10.4 `_ - - Required - - `STR04-C `_ + - | `INT02-C `_ + | `INT07-C `_ + | `INT31-C `_ + | `STR04-C `_ + | `STR34-C `_ .. _MisraC_Rule_10_5: * - 63 - The value of an expression should not be cast to an inappropriate essential type - `Rule 10.5 `_ - - Advisory - - N/A + - | `EXP14-C `_ + | `INT02-C `_ .. _MisraC_Rule_10_6: * - 64 - The value of a composite expression shall not be assigned to an object with wider essential type - `Rule 10.6 `_ - - Required - - `INT02-C `_ + - | `INT02-C `_ + | `INT31-C `_ .. _MisraC_Rule_10_7: * - 65 - If a composite expression is used as one operand of an operator in which the usual arithmetic conversions are performed then the other operand shall not have wider essential type - `Rule 10.7 `_ - - Required - - `INT02-C `_ + - | `INT02-C `_ + | `INT31-C `_ .. _MisraC_Rule_10_8: * - 66 - The value of a composite expression shall not be cast to a different essential type category or a wider essential type - `Rule 10.8 `_ - - Required - `INT02-C `_ .. _MisraC_Rule_11_2: * - 67 - Conversions shall not be performed between a pointer to an incomplete type and any other type - `Rule 11.2 `_ - - Required - - N/A + - `EXP36-C `_ .. _MisraC_Rule_11_6: * - 68 - A cast shall not be performed between pointer to void and an arithmetic type - `Rule 11.6 `_ - - Required - N/A .. _MisraC_Rule_11_7: * - 69 - A cast shall not be performed between pointer to object and a noninteger arithmetic type - `Rule 11.7 `_ - - Required - - N/A + - `EXP36-C `_ .. _MisraC_Rule_11_8: * - 70 - A cast shall not remove any const or volatile qualification from the type pointed to by a pointer - `Rule 11.8 `_ - - Required - - `EXP05-C `_ + - | `EXP05-C `_ + | `EXP32-C `_ .. _MisraC_Rule_11_9: * - 71 - The macro NULL shall be the only permitted form of integer null pointer constant - `Rule 11.9 `_ - - Required - N/A .. _MisraC_Rule_12_1: * - 72 - The precedence of operators within expressions should be made explicit - `Rule 12.1 `_ - - Advisory - `EXP00-C `_ .. _MisraC_Rule_12_2: * - 73 - The right hand operand of a shift operator shall lie in the range zero to one less than the width in bits of the essential type of the left hand operand - `Rule 12.2 `_ - - Required - N/A .. _MisraC_Rule_12_4: * - 74 - Evaluation of constant expressions should not lead to unsigned integer wrap-around - `Rule 12.4 `_ - - Advisory - N/A .. _MisraC_Rule_12_5: * - 75 - The sizeof operator shall not have an operand which is a function parameter declared as “array of type” - `Rule 12.5 `_ - - Mandatory - N/A .. _MisraC_Rule_13_1: @@ -573,28 +526,24 @@ should comply with the rules listed below. - Initializer lists shall not contain persistent side effects - | `Rule 13.1 example 1 `_ | `Rule 13.1 example 2 `_ - - Required - N/A .. _MisraC_Rule_13_2: * - 77 - The value of an expression and its persistent side effects shall be the same under all permitted evaluation orders - `Rule 13.2 `_ - - Required - - N/A + - `EXP30-C `_ .. _MisraC_Rule_13_3: * - 78 - A full expression containing an increment (++) or decrement (--) operator should have no other potential side effects other than that caused by the increment or decrement operator - `Rule 13.3 `_ - - Advisory - N/A .. _MisraC_Rule_13_4: * - 79 - The result of an assignment operator should not be used - `Rule 13.4 `_ - - Advisory - N/A .. _MisraC_Rule_13_5: @@ -602,196 +551,175 @@ should comply with the rules listed below. - The right hand operand of a logical && or || operator shall not contain persistent side effects - | `Rule 13.5 example 1 `_ | `Rule 13.5 example 2 `_ - - Required - `EXP10-C `_ .. _MisraC_Rule_13_6: * - 81 - The operand of the sizeof operator shall not contain any expression which has potential side effects - `Rule 13.6 `_ - - Mandatory - N/A .. _MisraC_Rule_14_1: * - 82 - A loop counter shall not have essentially floating type - `Rule 14.1 `_ - - Required - - N/A + - `FLP30-C `_ .. _MisraC_Rule_14_2: * - 83 - A for loop shall be well-formed - `Rule 14.2 `_ - - Required - N/A .. _MisraC_Rule_14_3: * - 84 - Controlling expressions shall not be invariant - `Rule 14.3 `_ - - Required - N/A .. _MisraC_Rule_14_4: * - 85 - The controlling expression of an if statement and the controlling expression of an iteration-statement shall have essentially Boolean type - `Rule 14.4 `_ - - Required - N/A .. _MisraC_Rule_15_2: * - 86 - The goto statement shall jump to a label declared later in the same function - `Rule 15.2 `_ - - Required - N/A .. _MisraC_Rule_15_3: * - 87 - Any label referenced by a goto statement shall be declared in the same block, or in any block enclosing the goto statement - `Rule 15.3 `_ - - Required - N/A .. _MisraC_Rule_15_6: * - 88 - The body of an iteration-statement or a selection-statement shall be a compound-statement - `Rule 15.6 `_ - - Required - `EXP19-C `_ .. _MisraC_Rule_15_7: * - 89 - All if else if constructs shall be terminated with an else statement - `Rule 15.7 `_ - - Required - - CERT, MSC01-C + - `MSC01-C `_ .. _MisraC_Rule_16_1: * - 90 - All switch statements shall be well-formed - `Rule 16.1 `_ - - Required - - N/A + - `DCL41-C `_ .. _MisraC_Rule_16_2: * - 91 - A switch label shall only be used when the most closely-enclosing compound statement is the body of a switch statement - `Rule 16.2 `_ - - Required - `MSC20-C `_ .. _MisraC_Rule_16_3: * - 92 - An unconditional break statement shall terminate every switch-clause - `Rule 16.3 `_ - - Required - N/A .. _MisraC_Rule_16_4: * - 93 - Every switch statement shall have a default label - `Rule 16.4 `_ - - Required - N/A .. _MisraC_Rule_16_5: * - 94 - A default label shall appear as either the first or the last switch label of a switch statement - `Rule 16.5 `_ - - Required - N/A .. _MisraC_Rule_16_6: * - 95 - Every switch statement shall have at least two switch-clauses - `Rule 16.6 `_ - - Required - N/A .. _MisraC_Rule_16_7: * - 96 - A switch-expression shall not have essentially Boolean type - `Rule 16.7 `_ - - Required - N/A .. _MisraC_Rule_17_1: * - 97 - The features of shall not be used - `Rule 17.1 `_ - - Required - - `ERR00-C `_ + - | `DCL10-C `_ + | `DCL11-C `_ + | `ERR00-C `_ .. _MisraC_Rule_17_2: * - 98 - Functions shall not call themselves, either directly or indirectly - `Rule 17.2 `_ - - Required - `MEM05-C `_ .. _MisraC_Rule_17_3: * - 99 - A function shall not be declared implicitly - `Rule 17.3 `_ - - Mandatory - - N/A + - | `DCL36-C `_ + | `EXP37-C `_ .. _MisraC_Rule_17_4: * - 100 - All exit paths from a function with non-void return type shall have an explicit return statement with an expression - `Rule 17.4 `_ - - Mandatory - N/A .. _MisraC_Rule_17_5: * - 101 - The function argument corresponding to a parameter declared to have an array type shall have an appropriate number of elements - `Rule 17.5 `_ - - Advisory - N/A .. _MisraC_Rule_17_6: * - 102 - The declaration of an array parameter shall not contain the static keyword between the [ ] - `Rule 17.6 `_ - - Mandatory - N/A .. _MisraC_Rule_17_7: * - 103 - The value returned by a function having non-void return type shall be used - `Rule 17.7 `_ - - Required - N/A .. _MisraC_Rule_18_1: * - 104 - A pointer resulting from arithmetic on a pointer operand shall address an element of the same array as that pointer operand - `Rule 18.1 `_ - - Required - - `EXP08-C `_ + - | `ARR30-C `_ + | `ARR39-C `_ + | `EXP08-C `_ .. _MisraC_Rule_18_2: * - 105 - Subtraction between pointers shall only be applied to pointers that address elements of the same array - `Rule 18.2 `_ - - Required - - `EXP08-C `_ + - | `ARR39-C `_ + | `EXP08-C `_ .. _MisraC_Rule_18_3: * - 106 - The relational operators >, >=, < and <= shall not be applied to objects of pointer type except where they point into the same object - `Rule 18.3 `_ - - Required - - `EXP08-C `_ + - | `ARR39-C `_ + | `EXP08-C `_ .. _MisraC_Rule_18_5: * - 107 - Declarations should contain no more than two levels of pointer nesting - `Rule 18.5 `_ - - Advisory - N/A .. _MisraC_Rule_18_6: @@ -799,280 +727,243 @@ should comply with the rules listed below. - The address of an object with automatic storage shall not be copied to another object that persists after the first object has ceased to exist - | `Rule 18.6 example 1 `_ | `Rule 18.6 example 2 `_ - - Required - - N/A + - | `DCL30-C `_ + | `MEM30-C `_ .. _MisraC_Rule_18_8: * - 109 - Variable-length array types shall not be used - `Rule 18.8 `_ - - Required - N/A .. _MisraC_Rule_19_1: * - 110 - An object shall not be assigned or copied to an overlapping object - `Rule 19.1 `_ - - Mandatory - N/A .. _MisraC_Rule_20_2: * - 111 - The ', or \ characters and the /* or // character sequences shall not occur in a header file name" - `Rule 20.2 `_ - - Required - N/A .. _MisraC_Rule_20_3: * - 112 - The #include directive shall be followed by either a or "filename" sequence - `Rule 20.3 `_ - - Required - N/A .. _MisraC_Rule_20_4: * - 113 - A macro shall not be defined with the same name as a keyword - `Rule 20.4 `_ - - Required - N/A .. _MisraC_Rule_20_7: * - 114 - Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses - `Rule 20.7 `_ - - Required - `PRE01-C `_ .. _MisraC_Rule_20_8: * - 115 - The controlling expression of a #if or #elif preprocessing directive shall evaluate to 0 or 1 - `Rule 20.8 `_ - - Required - N/A .. _MisraC_Rule_20_9: * - 116 - All identifiers used in the controlling expression of #if or #elif preprocessing directives shall be #defined before evaluation - `Rule 20.9 `_ - - Required - N/A .. _MisraC_Rule_20_11: * - 117 - A macro parameter immediately following a # operator shall not immediately be followed by a ## operator - `Rule 20.11 `_ - - Required - N/A .. _MisraC_Rule_20_12: * - 118 - A macro parameter used as an operand to the # or ## operators, which is itself subject to further macro replacement, shall only be used as an operand to these operators - `Rule 20.12 `_ - - Required - N/A .. _MisraC_Rule_20_13: * - 119 - A line whose first token is # shall be a valid preprocessing directive - `Rule 20.13 `_ - - Required - N/A .. _MisraC_Rule_20_14: * - 120 - All #else, #elif and #endif preprocessor directives shall reside in the same file as the #if, #ifdef or #ifndef directive to which they are related - `Rule 20.14 `_ - - Required - N/A .. _MisraC_Rule_21_1: * - 121 - #define and #undef shall not be used on a reserved identifier or reserved macro name - `Rule 21.1 `_ - - Required - - N/A + - `DCL37-C `_ .. _MisraC_Rule_21_2: * - 122 - A reserved identifier or macro name shall not be declared - `Rule 21.2 `_ - - Required - - N/A + - `DCL37-C `_ .. _MisraC_Rule_21_3: * - 123 - The memory allocation and deallocation functions of shall not be used - `Rule 21.3 `_ - - Required - - `MSC24-C `_ + - | `API03-C `_ + | `API04-C `_ + | `MSC24-C `_ .. _MisraC_Rule_21_4: * - 124 - The standard header file shall not be used - `Rule 21.4 `_ - - Required - N/A .. _MisraC_Rule_21_6: * - 125 - The Standard Library input/output functions shall not be used - `Rule 21.6 `_ - - Required - N/A .. _MisraC_Rule_21_7: * - 126 - The atof, atoi, atol and atoll functions of shall not be used - `Rule 21.7 `_ - - Required - N/A .. _MisraC_Rule_21_9: * - 127 - The library functions bsearch and qsort of shall not be used - `Rule 21.9 `_ - - Required - N/A .. _MisraC_Rule_21_11: * - 128 - The standard header file shall not be used - `Rule 21.11 `_ - - Required - N/A .. _MisraC_Rule_21_12: * - 129 - The exception handling features of should not be used - `Rule 21.12 `_ - - Advisory - N/A .. _MisraC_Rule_21_13: * - 130 - Any value passed to a function in shall be representable as an unsigned char or be the value EOF - `Rule 21.13 `_ - - Mandatory - N/A .. _MisraC_Rule_21_14: * - 131 - The Standard Library function memcmp shall not be used to compare null terminated strings - `Rule 21.14 `_ - - Required - N/A .. _MisraC_Rule_21_15: * - 132 - The pointer arguments to the Standard Library functions memcpy, memmove and memcmp shall be pointers to qualified or unqualified versions of compatible types - `Rule 21.15 `_ - - Required - N/A .. _MisraC_Rule_21_16: * - 133 - The pointer arguments to the Standard Library function memcmp shall point to either a pointer type, an essentially signed type, an essentially unsigned type, an essentially Boolean type or an essentially enum type - `Rule 21.16 `_ - - Required - N/A .. _MisraC_Rule_21_17: * - 134 - Use of the string handling functions from shall not result in accesses beyond the bounds of the objects referenced by their pointer parameters - `Rule 21.17 `_ - - Mandatory - N/A .. _MisraC_Rule_21_18: * - 135 - The size_t argument passed to any function in shall have an appropriate value - `Rule 21.18 `_ - - Mandatory - N/A .. _MisraC_Rule_21_19: * - 136 - The pointers returned by the Standard Library functions localeconv, getenv, setlocale or, strerror shall only be used as if they have pointer to const-qualified type - `Rule 21.19 `_ - - Mandatory - N/A .. _MisraC_Rule_21_20: * - 137 - The pointer returned by the Standard Library functions asctime, ctime, gmtime, localtime, localeconv, getenv, setlocale or strerror shall not be used following a subsequent call to the same function - `Rule 21.20 `_ - - Mandatory - N/A .. _MisraC_Rule_22_1: * - 138 - All resources obtained dynamically by means of Standard Library functions shall be explicitly released - `Rule 22.1 `_ - - Required - N/A .. _MisraC_Rule_22_2: * - 139 - A block of memory shall only be freed if it was allocated by means of a Standard Library function - `Rule 22.2 `_ - - Mandatory - N/A .. _MisraC_Rule_22_3: * - 140 - The same file shall not be open for read and write access at the same time on different streams - `Rule 22.3 `_ - - Required - N/A .. _MisraC_Rule_22_4: * - 141 - There shall be no attempt to write to a stream which has been opened as read-only - `Rule 22.4 `_ - - Mandatory - N/A .. _MisraC_Rule_22_5: * - 142 - A pointer to a FILE object shall not be dereferenced - `Rule 22.5 `_ - - Mandatory - N/A .. _MisraC_Rule_22_6: * - 143 - The value of a pointer to a FILE shall not be used after the associated stream has been closed - `Rule 22.6 `_ - - Mandatory - N/A .. _MisraC_Rule_22_7: * - 144 - The macro EOF shall only be compared with the unmodified return value from any Standard Library function capable of returning EOF - `Rule 22.7 `_ - - Required - N/A .. _MisraC_Rule_22_8: * - 145 - The value of errno shall be set to zero prior to a call to an errno-setting-function - `Rule 22.8 `_ - - Required - N/A .. _MisraC_Rule_22_9: * - 146 - The value of errno shall be tested against zero after calling an errno-setting-function - `Rule 22.9 `_ - - Required - N/A .. _MisraC_Rule_22_10: * - 147 - The value of errno shall only be tested when the last function to be called was an errno-setting-function - `Rule 22.10 `_ - - Required - N/A Additional rules diff --git a/doc/contribute/guidelines.rst b/doc/contribute/guidelines.rst index 640ea4abc1e3b..8fb1725a9a5ed 100644 --- a/doc/contribute/guidelines.rst +++ b/doc/contribute/guidelines.rst @@ -358,6 +358,19 @@ If in doubt, it's advisable to explore existing Pull Requests within the Zephyr repository. Use the search filters and labels to locate PRs related to changes similar to the ones you are proposing. +.. note:: + GitHub's default code UI uses 4-character tabs. However, Zephyr follows the + `Linux kernel coding style`_, which uses 8-character tabs. + + To ensure your view of the code is consistent with other developers, please + go to your `user preferences on GitHub`_ and change the tab width to 8 spaces. + +.. _Linux kernel coding style: + https://kernel.org/doc/html/latest/process/coding-style.html#indentation + +.. _user preferences on GitHub: + https://github.com/settings/appearance + .. _commit-guidelines: Commit Message Guidelines diff --git a/doc/contribute/style/code.rst b/doc/contribute/style/code.rst index 59a363ee50949..4fd45c7708210 100644 --- a/doc/contribute/style/code.rst +++ b/doc/contribute/style/code.rst @@ -16,6 +16,7 @@ subsystem, etc). In general, follow the `Linux kernel coding style`_, with the following exceptions and clarifications: +* Tabs are 8 characters. * Use `snake case`_ for code and variables. * The line length is 100 columns or fewer. In the documentation, longer lines for URL references are an allowed exception. diff --git a/doc/develop/beyond-GSG.rst b/doc/develop/beyond-GSG.rst index fe7e646e9e858..3f2baea422ee8 100644 --- a/doc/develop/beyond-GSG.rst +++ b/doc/develop/beyond-GSG.rst @@ -181,7 +181,7 @@ Build and Run an Application You can build, flash, and run Zephyr applications on real hardware using a supported host system. Depending on your operating system, you can also run it in emulation with QEMU, or as a native application with -:ref:`native_sim `. +:zephyr:board:`native_sim `. Additional information about building applications can be found in the :ref:`build_an_application` section. @@ -308,7 +308,7 @@ Run a Sample Application natively (Linux) ========================================= You can compile some samples to run as host programs -on Linux. See :ref:`native_sim` for more information. On 64-bit host operating systems, you +on Linux. See :zephyr:board:`native_sim` for more information. On 64-bit host operating systems, you need to install a 32-bit C library, or build targeting :ref:`native_sim/native/64`. First, build Hello World for ``native_sim``. diff --git a/doc/develop/debug/index.rst b/doc/develop/debug/index.rst index b96cf263e7271..10571d3151cde 100644 --- a/doc/develop/debug/index.rst +++ b/doc/develop/debug/index.rst @@ -363,4 +363,4 @@ in the log. .. _Eclipse IDE for C/C++ Developers: https://www.eclipse.org/downloads/packages/eclipse-ide-cc-developers/oxygen2 .. _GNU MCU Eclipse plug-ins: https://gnu-mcu-eclipse.github.io/plugins/install/ -.. _pyOCD v0.11.0: https://github.com/mbedmicro/pyOCD/releases/tag/v0.11.0 +.. _pyOCD v0.11.0: https://github.com/pyocd/pyOCD/releases/tag/v0.11.0 diff --git a/doc/develop/optimizations/ram_plot.png b/doc/develop/optimizations/ram_plot.png new file mode 100644 index 0000000000000..9b0b59e6db3ba Binary files /dev/null and b/doc/develop/optimizations/ram_plot.png differ diff --git a/doc/develop/optimizations/rom_plot.png b/doc/develop/optimizations/rom_plot.png new file mode 100644 index 0000000000000..f75ea2769057a Binary files /dev/null and b/doc/develop/optimizations/rom_plot.png differ diff --git a/doc/develop/optimizations/tools.rst b/doc/develop/optimizations/tools.rst index d34443b3e1fb2..e263c011335df 100644 --- a/doc/develop/optimizations/tools.rst +++ b/doc/develop/optimizations/tools.rst @@ -157,6 +157,40 @@ These commands will generate something similar to the output below:: ======================================================================================== 21652 + +Build Targets: ram_plot/rom_plot +================================ + +Similar to the ``ram_report`` and ``rom_report`` build targets, these targets generate memory usage +reports in a sunburst chart as a visual representation. +A user can click on segments to navigate through the directory structures, and hover over segments +to get more details. + +Running the targets will first generate the CLI report and then open a browser window. + +.. zephyr-app-commands:: + :tool: all + :zephyr-app: samples/hello_world + :board: reel_board + :goals: ram_plot + +.. image:: ram_plot.png + :align: center + :alt: RAM usage sunburst chart + +And similarly for the ROM usage. + +.. zephyr-app-commands:: + :tool: all + :zephyr-app: samples/hello_world + :board: reel_board + :goals: rom_plot + +.. image:: rom_plot.png + :align: center + :alt: ROM usage sunburst chart + + Build Target: puncover ====================== diff --git a/doc/develop/test/bsim.rst b/doc/develop/test/bsim.rst index d5484df51b558..d533e96fc24a5 100644 --- a/doc/develop/test/bsim.rst +++ b/doc/develop/test/bsim.rst @@ -34,7 +34,7 @@ Tests without radio activity: bsim tests with twister The :ref:`bsim boards` can be used without radio activity, and in that case, it is not necessary to connect them to a physical layer simulation. Thanks to this, these target boards can -be used just like :ref:`native_sim` with :ref:`twister `, +be used just like :zephyr:board:`native_sim` with :ref:`twister `, to run all standard Zephyr twister tests, but with models of a real SOC HW, and their drivers. Tests with radio activity diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst index b8a81eb0ffb0d..e59b60bc76d2e 100644 --- a/doc/develop/test/twister.rst +++ b/doc/develop/test/twister.rst @@ -1443,6 +1443,33 @@ work. It is equivalent to following west and twister commands. manually according to above example. This is because the serial port of the PTY is not fixed and being allocated in the system at runtime. +If west is not available or does not know how to flash your system, a custom +flash command can be specified using the ``flash-command`` flag. The script is +called with a ``--build-dir`` with the path of the current build, as well as a +``--board-id`` flag to identify the specific device when multiple are available +in a hardware map. + +.. tabs:: + + .. group-tab:: Linux + + .. code-block:: bash + + twister -p npcx9m6f_evb --device-testing --device-serial /dev/ttyACM0 + --flash-command './custom_flash_script.py,--flag,"complex, argument"' + + .. group-tab:: Windows + + .. note:: + + python .\scripts\twister -p npcx9m6f_evb --device-testing + --device-serial COM1 + --flash-command 'custom_flash_script.py,--flag,"complex, argument"' + +Would result in calling ``./custom_flash_script.py +--build-dir --board-id +--flag "complex, argument"``. + Fixtures +++++++++ diff --git a/doc/develop/test/twister/sample_blackbox_test.py b/doc/develop/test/twister/sample_blackbox_test.py index c391669f88928..346ba34d000ef 100644 --- a/doc/develop/test/twister/sample_blackbox_test.py +++ b/doc/develop/test/twister/sample_blackbox_test.py @@ -10,7 +10,7 @@ from unittest import mock import pytest -from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock +from conftest import TEST_DATA, ZEPHYR_BASE, suite_filename_mock from twisterlib.testplan import TestPlan @@ -34,7 +34,7 @@ def teardown_class(cls): @pytest.mark.parametrize( "level, expected_tests", TESTDATA_X, ids=["smoke", "acceptance"] ) - @mock.patch.object(TestPlan, "TESTSUITE_FILENAME", testsuite_filename_mock) + @mock.patch.object(TestPlan, "TESTSUITE_FILENAME", suite_filename_mock) def test_level(self, capfd, out_path, level, expected_tests): # Select platforms used for the tests test_platforms = ["qemu_x86", "frdm_k64f"] diff --git a/doc/develop/test/twister/twister_blackbox.rst b/doc/develop/test/twister/twister_blackbox.rst index fc6231fb90dd5..f40cd40a7e9b0 100644 --- a/doc/develop/test/twister/twister_blackbox.rst +++ b/doc/develop/test/twister/twister_blackbox.rst @@ -63,7 +63,7 @@ Decorators - this is an example of ``pytest`` 's test parametrization. Read up on it `here `__. TESTDATAs are most often declared as class fields. -* ``@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock)`` +* ``@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock)`` - this decorator allows us to use only tests defined in the ``test_data`` and ignore the Zephyr testcases in the ``tests`` directory. **Note that all ``test_data`` tests use** ``test_data.yaml`` **as a filename, not** ``testcase.yaml`` **!** diff --git a/doc/develop/toolchains/zephyr_sdk.rst b/doc/develop/toolchains/zephyr_sdk.rst index f9cb99fac79c8..a93daf03e46b0 100644 --- a/doc/develop/toolchains/zephyr_sdk.rst +++ b/doc/develop/toolchains/zephyr_sdk.rst @@ -229,6 +229,6 @@ Zephyr SDK installation the initial setup. .. _Zephyr SDK Releases: https://github.com/zephyrproject-rtos/sdk-ng/tags -.. _Zephyr SDK Version Compatibility Matrix: https://github.com/zephyrproject-rtos/sdk-ng/wiki/Zephyr-SDK-Version-Compatibility-Matrix +.. _Zephyr SDK Version Compatibility Matrix: https://github.com/zephyrproject-rtos/sdk-ng/wiki/Zephyr-Version-Compatibility#zephyr-sdk-version-compatibility-matrix .. toolchain_zephyr_sdk_install_end diff --git a/doc/develop/west/alias.rst b/doc/develop/west/alias.rst index 5e55652eb4e79..f0093b5d8a61e 100644 --- a/doc/develop/west/alias.rst +++ b/doc/develop/west/alias.rst @@ -59,3 +59,11 @@ Override ``west update`` to check a local cache: .. code-block:: shell west config alias.update "update --path-cache $HOME/.cache/zephyrproject" + +Automatically exclude the 32-bit native simulator target when running :ref:`Twister +` via west. This is especially useful when running on hosts systems without a 32-bit +host C library (i.e. Linux/AArch64): + +.. code-block:: shell + + west config alias.twister "twister --exclude-platform native_sim/native" diff --git a/doc/develop/west/zephyr-cmds.rst b/doc/develop/west/zephyr-cmds.rst index ee5e8b2862817..f4b039fa03882 100644 --- a/doc/develop/west/zephyr-cmds.rst +++ b/doc/develop/west/zephyr-cmds.rst @@ -214,6 +214,12 @@ Additionally the tool allows you to specify the modules you want to list, fetch or clean blobs for by typing the module names as a command-line parameter. +The argument ``--allow-regex`` can be passed ``west blobs fetch`` to restrict +the specific blobs that are fetched, by passing a regular expression:: + + # For example, only download esp32 blobs, skip the other variants + west blobs fetch hal_espressif --allow-regex 'lib/esp32/.*' + .. _west-twister: Twister wrapper: ``west twister`` diff --git a/doc/hardware/arch/arm_cortex_m.rst b/doc/hardware/arch/arm_cortex_m.rst index a42e9eacbbc6b..139f00429d845 100644 --- a/doc/hardware/arch/arm_cortex_m.rst +++ b/doc/hardware/arch/arm_cortex_m.rst @@ -434,35 +434,47 @@ Pointer Authentication and Branch Target Identification (PACBTI) The Armv8.1-M Pointer Authentication and Branch Target Identification (PACBTI) extension is an optional extension for the Armv8.1-M architecture profile and consists of the implementation of the following control-flow integrity approaches: + * Return address signing and authentication (PAC-RET) as a mitigation for Return Oriented Programming (ROP) style attack. * BTI instruction placement (BTI) as a mitigation for Jump Oriented Programming (JOP) style attacks. When hardware support is present (e.g., Cortex-M85) and compiler support is available, PACBTI can be enabled at build time in Zephyr by selecting one of the below configs: -- :kconfig:option:`CONFIG_ARMV8_1_M_PACBTI_STANDARD` -- :kconfig:option:`CONFIG_ARMV8_1_M_PACBTI_PACRET` -- :kconfig:option:`CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF` -- :kconfig:option:`CONFIG_ARMV8_1_M_PACBTI_BTI` -- :kconfig:option:`CONFIG_ARMV8_1_M_PACBTI_PACRET_BTI` -- :kconfig:option:`CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF_BTI` -- :kconfig:option:`CONFIG_ARMV8_1_M_PACBTI_NONE` +- :kconfig:option:`CONFIG_ARM_PACBTI_STANDARD` +- :kconfig:option:`CONFIG_ARM_PACBTI_PACRET` +- :kconfig:option:`CONFIG_ARM_PACBTI_PACRET_LEAF` +- :kconfig:option:`CONFIG_ARM_PACBTI_BTI` +- :kconfig:option:`CONFIG_ARM_PACBTI_PACRET_BTI` +- :kconfig:option:`CONFIG_ARM_PACBTI_PACRET_LEAF_BTI` +- :kconfig:option:`CONFIG_ARM_PACBTI_NONE` The config options ensures that compiler flags enabling PACBTI instructions are added to the build, specifically: - ``-mbranch-protection=`` for GCC toolchains. +Further, :kconfig:option:`CONFIG_ARM_PAC` and :kconfig:option:`CONFIG_ARM_BTI` are +automatically selected based on the branch protection option chosen for +:kconfig:option:`CONFIG_ARM_PACBTI`. These configuration options enforce PACBTI by enabling +corresponding PACBTI bits in CONTROL register and in the FVP. + +To further enhance pointer authentication, Zephyr supports using cryptographically secure, +per-thread PAC keys by enabling :kconfig:option:`CONFIG_ARM_PAC_PER_THREAD`. +For more details on key generation sources and configuration, refer to the Kconfig help for +:kconfig:option:`CONFIG_ARM_PAC_PER_THREAD`. + **Limitations:** - Only builds targeting Armv8.1-M Mainline processors with PACBTI hardware support (e.g., Cortex-M85) are able to fully use this feature. - Zephyr’s integrated SDK currently includes GCC 12.2 which does not support PACBTI so external GCC - toolchains (14.2 or later) must be used for PACBTI support. - Refer [this](https://docs.zephyrproject.org/latest/develop/toolchains/index.html) on how to set up + toolchains (14.3 or later recommended) must be used for PACBTI support. + Refer to `this document `_ on how to set up toolchains. -For more information about PACBTI, refer to the official [Arm documentation](https://developer.arm.com/documentation/109576/latest/). +For more information about PACBTI, refer to the official `Arm documentation `_ +and also `Arm community blog `_ .. _arm_cortex_m_mpu_considerations: diff --git a/doc/hardware/emulator/index.rst b/doc/hardware/emulator/index.rst index a2f042a211e89..4ccacc324015f 100644 --- a/doc/hardware/emulator/index.rst +++ b/doc/hardware/emulator/index.rst @@ -53,7 +53,7 @@ Available Emulators * Emulate an EEPROM on RAM * Main Kconfig option: :kconfig:option:`CONFIG_EEPROM_SIMULATOR` * DT binding: :dtcompatible:`zephyr,sim-eeprom` - * Note: For :ref:`native targets ` it is also possible to keep the content + * Note: For :zephyr:board:`native targets ` it is also possible to keep the content as a file on the host filesystem. **External bus and bus connected peripheral emulators** diff --git a/doc/hardware/peripherals/can/controller.rst b/doc/hardware/peripherals/can/controller.rst index 99cda14a36196..4eba0e1a73460 100644 --- a/doc/hardware/peripherals/can/controller.rst +++ b/doc/hardware/peripherals/can/controller.rst @@ -317,4 +317,4 @@ We have two ready-to-build samples demonstrating use of the Zephyr CAN API: CAN Controller API Reference **************************** -.. doxygengroup:: can_interface +.. doxygengroup:: can_controller diff --git a/doc/hardware/peripherals/crc.rst b/doc/hardware/peripherals/crc.rst new file mode 100644 index 0000000000000..13525c87861c5 --- /dev/null +++ b/doc/hardware/peripherals/crc.rst @@ -0,0 +1,23 @@ +.. _crc_api: + +Cyclic Redundancy Check (CRC) +############################# + +Overview +******** + +The Cyclic Redundancy Check (CRC) API provides functions for configuring and +computing CRC values on hardware. + +Configuration Options +********************* + +Related configuration options: + +* :kconfig:option:`CRC_HW` +* :kconfig:option:`CRC_INIT_PRIORITY` + +API Reference +************* + +.. doxygengroup:: crc_interface diff --git a/doc/hardware/peripherals/display/index.rst b/doc/hardware/peripherals/display/index.rst index 735241bb466f1..a9b918b200966 100644 --- a/doc/hardware/peripherals/display/index.rst +++ b/doc/hardware/peripherals/display/index.rst @@ -1,11 +1,44 @@ -.. comment - not documenting - .. doxygengroup:: display_interfaces - .. _display_api: -Display Interface -################# +Display +####### + +The Display subsystem in Zephyr provides a unified way to interact with a wide range of display +devices. The Display API is transport-agnostic: it describes what you want the display to do, +without exposing how the data moves over the wire. + +MIPI Display Bus Interface (DBI) +******************************** + +The **MIPI DBI** specification defines several parallel and serial buses for connecting a host to a +display controller. In Zephyr, DBI support provides bus-level primitives for command writes, reads, +pixel transfers, reset, and related operations that a driver uses internally to implement the +generic API. + +Applications do not use DBI functions directly. Instead, they call the generic Display API (e.g., to +write pixels), and the display driver handles the DBI protocol under the hood. + +MIPI-DBI defines 3 interface types: + +* Type A: Motorola 6800 parallel bus +* Type B: Intel 8080 parallel bus +* Type C: SPI Type serial bit bus with 3 options: + + #. 9 write clocks per byte, final bit is command/data selection bit + #. Same as above, but 16 write clocks per byte + #. 8 write clocks per byte. Command/data selected via GPIO pin + +Currently, the API does not support Type C controllers with 16 write clocks (option 2). + +MIPI Display Serial Interface (DSI) +*********************************** + +The **MIPI DSI** standard is a high-speed differential serial bus designed for modern color TFT +panels. Zephyr's DSI support provides the primitives needed by drivers to implement the generic +Display API on top of a DSI link. + +As with DBI, applications never call DSI functions directly. They remain portable by using the +generic Display API, while the driver handles the DSI transactions internally. API Reference ************* @@ -15,6 +48,20 @@ Generic Display Interface .. doxygengroup:: display_interface +.. _mipi_dbi_api: + +MIPI Display Bus Interface (DBI) +================================ + +.. doxygengroup:: mipi_dbi_interface + +.. _mipi_dsi_api: + +MIPI Display Serial Interface (DSI) +=================================== + +.. doxygengroup:: mipi_dsi_interface + Grove LCD Display ================= diff --git a/doc/hardware/peripherals/edac/index.rst b/doc/hardware/peripherals/edac/index.rst index 31f76efe8eaa3..8198daf204633 100644 --- a/doc/hardware/peripherals/edac/index.rst +++ b/doc/hardware/peripherals/edac/index.rst @@ -21,4 +21,4 @@ Related configuration option: API Reference ************* -.. doxygengroup:: edac +.. doxygengroup:: edac_interface diff --git a/doc/hardware/peripherals/eeprom/shell.rst b/doc/hardware/peripherals/eeprom/shell.rst index 2b4d1825732fa..464286722458e 100644 --- a/doc/hardware/peripherals/eeprom/shell.rst +++ b/doc/hardware/peripherals/eeprom/shell.rst @@ -21,7 +21,7 @@ In order to enable the EEPROM shell, the following :ref:`Kconfig ` opti * :kconfig:option:`CONFIG_EEPROM` * :kconfig:option:`CONFIG_EEPROM_SHELL` -For example, building the :zephyr:code-sample:`hello_world` sample for the :ref:`native_sim` with the EEPROM shell: +For example, building the :zephyr:code-sample:`hello_world` sample for the :zephyr:board:`native_sim` with the EEPROM shell: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/doc/hardware/peripherals/index.rst b/doc/hardware/peripherals/index.rst index 1b235d242c33a..88e3ac1fee33a 100644 --- a/doc/hardware/peripherals/index.rst +++ b/doc/hardware/peripherals/index.rst @@ -21,6 +21,7 @@ Peripherals comparator.rst coredump.rst counter.rst + crc.rst dac.rst dma.rst display/index.rst @@ -40,8 +41,6 @@ Peripherals ipm.rst led.rst mdio.rst - mipi_dbi.rst - mipi_dsi.rst mspi.rst mbox.rst pcie.rst diff --git a/doc/hardware/peripherals/mipi_dbi.rst b/doc/hardware/peripherals/mipi_dbi.rst deleted file mode 100644 index 6ca91f4600e97..0000000000000 --- a/doc/hardware/peripherals/mipi_dbi.rst +++ /dev/null @@ -1,29 +0,0 @@ -.. _mipi_dbi_api: - -MIPI Display Bus Interface (DBI) -################################### - -The MIPI DBI driver class implements support for MIPI DBI compliant display -controllers. - -MIPI DBI defines 3 interface types: - -* Type A: Motorola 6800 parallel bus - -* Type B: Intel 8080 parallel bus - -* Type C: SPI Type serial bit bus with 3 options: - - #. 9 write clocks per byte, final bit is command/data selection bit - - #. Same as above, but 16 write clocks per byte - - #. 8 write clocks per byte. Command/data selected via GPIO pin - -Currently, the API does not support Type C controllers with 16 write clocks -(option 2). - -API Reference -************* - -.. doxygengroup:: mipi_dbi_interface diff --git a/doc/hardware/peripherals/mipi_dsi.rst b/doc/hardware/peripherals/mipi_dsi.rst deleted file mode 100644 index 815c772d3b644..0000000000000 --- a/doc/hardware/peripherals/mipi_dsi.rst +++ /dev/null @@ -1,9 +0,0 @@ -.. _mipi_dsi_api: - -MIPI Display Serial Interface (DSI) -################################### - -API Reference -************* - -.. doxygengroup:: mipi_dsi_interface diff --git a/doc/hardware/peripherals/sensor/temp_polling.c b/doc/hardware/peripherals/sensor/temp_polling.c index f6c38cdecc8f3..8c61a41f14690 100644 --- a/doc/hardware/peripherals/sensor/temp_polling.c +++ b/doc/hardware/peripherals/sensor/temp_polling.c @@ -10,14 +10,13 @@ const struct device *const temp0 = DEVICE_DT_GET(DT_ALIAS(temp0)); -SENSOR_DT_READ_IODEV(temp_iodev, DT_ALIAS(temp0), {TEMP_CHANNEL}); +SENSOR_DT_READ_IODEV(temp_iodev, DT_ALIAS(temp0), TEMP_CHANNEL); RTIO_DEFINE(temp_ctx, 1, 1); int main(void) { int rc; uint8_t buf[8]; - uint32_t temp_frame_iter = 0; struct sensor_q31_data temp_data = {0}; struct sensor_decode_context temp_decoder = SENSOR_DECODE_CONTEXT_INIT( SENSOR_DECODER_DT_GET(DT_ALIAS(temp0)), buf, SENSOR_CHAN_AMBIENT_TEMP, 0); diff --git a/doc/introduction/index.rst b/doc/introduction/index.rst index e5635fbfebd0b..173c4a75b645f 100644 --- a/doc/introduction/index.rst +++ b/doc/introduction/index.rst @@ -154,7 +154,7 @@ Zephyr offers a large and ever growing number of features including: **Native Linux, macOS, and Windows Development** A command-line CMake build environment runs on popular developer OS - systems. A native port (:ref:`native_sim `) lets you build and run Zephyr as a native + systems. A native port (:zephyr:board:`native_sim `) lets you build and run Zephyr as a native application on Linux, aiding development and testing. **Virtual File System Interface with ext2, FatFs, and LittleFS Support** @@ -181,7 +181,7 @@ Zephyr offers a large and ever growing number of features including: combination of these. **Native port** - :ref:`Native sim ` allows running Zephyr as a Linux application with support + :zephyr:board:`Native sim ` allows running Zephyr as a Linux application with support for various subsystems and networking. diff --git a/doc/kernel/services/smp/smp.rst b/doc/kernel/services/smp/smp.rst index 9a81609188cac..5cd448e38603c 100644 --- a/doc/kernel/services/smp/smp.rst +++ b/doc/kernel/services/smp/smp.rst @@ -264,6 +264,57 @@ they must be processed. The third is the apparent sputtering of a thread as it "winks in" and then "winks out" due to cascades stemming from the aforementioned first cost. +IPI Work Items +============== + +The kernel allows developers to execute functions on other CPUs at ISR level +using one or more IPI work items. After IPI work items have been added to the +specified CPUs' work queues using :c:func:`k_ipi_work_add`, the targeted CPUs +will process them after receiving an IPI. Signaling an IPI is done by calling +:c:func:`k_ipi_work_signal`. Waiting for an IPI work item to be completed by +the targeted CPUs is done by calling :c:func:`k_ipi_work_wait`. Only a single +waiter is permitted at a time. + +.. note:: + IPI work items will only be added to the IPI work queues of other CPUs. If + adding IPI work items at thread level, the developer must ensure that the + current thread does not change CPUs until after signaling the IPIs. + +Sample Use +---------- + +The following code outlines how to use IPI work items to update status +information across a set of CPUs as a result of one CPU handling an ISR. + +.. code-block:: c + + struct k_ipi_work my_work; + + void remote_cpu_action(struct k_ipi_work *arg) + { + ... + } + + void my_isr(void) + { + /* + * Wait for previous use of to complete. + * It assumes that was initialized elsewhere. + */ + + uint32_t cpu_mask = ; + + while (k_ipi_work_wait(&my_work, K_NO_WAIT) == -EAGAIN) { + } + + /* Add and signal the new work */ + + k_ipi_work_add(&my_work, cpu_mask, remote_cpu_action); + + k_ipi_signal(); + } + + SMP Kernel Internals ******************** diff --git a/doc/kernel/services/synchronization/events.rst b/doc/kernel/services/synchronization/events.rst index cbb86894723c3..bae6063f40e6f 100644 --- a/doc/kernel/services/synchronization/events.rst +++ b/doc/kernel/services/synchronization/events.rst @@ -108,8 +108,8 @@ the event object. ... } -Waiting for Events -================== +Waiting for Events (without removal) +==================================== Threads wait for events by calling :c:func:`k_event_wait`. @@ -152,6 +152,58 @@ before continuing. ... } +Waiting for Events (with removal) +================================= + +Threads wait for events (with atomic removal upon receipt) by calling +:c:func:`k_event_wait_safe`. + +The following code builds on the example above, and waits up to 50 milliseconds +for any of the specified events to be posted. A warning is issued if none +of the events are posted in time. + +If events are received on time, then they will not be present in the event +object until the next time that the events are set or posted. + +.. code-block:: c + + void consumer_thread(void) + { + uint32_t events; + + events = k_event_wait_safe(&my_event, 0xFFF, false, K_MSEC(50)); + if (events == 0) { + printk("No input devices are available!"); + } else { + /* Access the desired input device(s) */ + ... + } + ... + } + +Alternatively, the consumer thread may desire to wait for all the events +(with atomic removal upon receipt) before continuing using +:c:func:`k_event_wait_all_safe`. + +If all events are received on time, then they will not be present in the event +object until the next time that the events are set or posted. + +.. code-block:: c + + void consumer_thread(void) + { + uint32_t events; + + events = k_event_wait_all_safe(&my_event, 0x121, false, K_MSEC(50)); + if (events == 0) { + printk("At least one input device is not available!"); + } else { + /* Access the desired input devices */ + ... + } + ... + } + Suggested Uses ************** diff --git a/doc/releases/migration-guide-3.6.rst b/doc/releases/migration-guide-3.6.rst index 3c0e42b028417..894e76ac20878 100644 --- a/doc/releases/migration-guide-3.6.rst +++ b/doc/releases/migration-guide-3.6.rst @@ -242,7 +242,7 @@ Controller Area Network (CAN) ============================= * The native Linux SocketCAN driver, which can now be used in both ``native_posix`` - and :ref:`native_sim` with or without an embedded C-library, has been renamed to + and :zephyr:board:`native_sim` with or without an embedded C-library, has been renamed to reflect this: * The devicetree compatible was renamed from ``zephyr,native-posix-linux-can`` to diff --git a/doc/releases/migration-guide-4.0.rst b/doc/releases/migration-guide-4.0.rst index 4a7b500c1870e..d3440dcf7c152 100644 --- a/doc/releases/migration-guide-4.0.rst +++ b/doc/releases/migration-guide-4.0.rst @@ -34,7 +34,7 @@ Boards ****** * ``native_posix`` has been deprecated in favour of - :ref:`native_sim` (:github:`76898`). + :zephyr:board:`native_sim` (:github:`76898`). * Nordic nRF53 and nRF91 based boards can use the common devicetree overlays in ``dts/common/nordic`` to define default flash and ram partitioning based on TF-M. diff --git a/doc/releases/migration-guide-4.2.rst b/doc/releases/migration-guide-4.2.rst index 4ec80dfaf8ded..a2c6b825e34a0 100644 --- a/doc/releases/migration-guide-4.2.rst +++ b/doc/releases/migration-guide-4.2.rst @@ -469,8 +469,9 @@ Video size on a per driver basis. Existing applications will not be broken by this change but can be simplified as performed in the sample in the commit ``33dcbe37cfd3593e8c6e9cfd218dd31fdd533598``. -* Samples and projects using the :ref:`native simulator ` now require specifying the - ``--snippet`` :ref:`video-sw-generator ` to build correctly. +* Samples and projects using the :zephyr:board:`native simulator ` now require + specifying the ``--snippet`` :ref:`video-sw-generator ` to build + correctly. * :c:func:`video_query_ctrl` now takes a single argument with the :c:struct:`video_ctrl_query`, which now contains a ``video_ctrl_query.dev`` field to specify and read back which device is diff --git a/doc/releases/migration-guide-4.3.rst b/doc/releases/migration-guide-4.3.rst index b6fb69c1f08f4..e2e6c21b57d75 100644 --- a/doc/releases/migration-guide-4.3.rst +++ b/doc/releases/migration-guide-4.3.rst @@ -26,14 +26,33 @@ Build System Kernel ****** +* :c:func:`device_init` Earlier releases returned a positive +errno value in case + of device init failure due to a bug. This is now fixed to return the correct + negative -errno value. Applications that implemented workarounds for this + issue should now update their code accordingly. + +Base Libraries +************** + +* UTF-8 utils declarations (:c:func:`utf8_trunc`, :c:func:`utf8_lcpy`) have + been moved from ``util.h`` to a separate + :zephyr_file:`include/zephyr/sys/util_utf8.h` file. + Boards ****** +* b_u585i_iot02a/ns: The flash layout was changed to be in sync with the upstream TF-M 2.2.1 board + configurations. The new layout expands the flash partitions, moving the secondary ones to the + external NOR flash. This change currently prevents upgrade from older Zephyr release images to + Zephyr 4.3 release images. More details in the TF-M migration and release notes. + * mimxrt11x0: renamed lpadc1 to lpadc2 and renamed lpadc0 to lpadc1. * NXP ``frdm_mcxa166`` is renamed to ``frdm_mcxa346``. * NXP ``frdm_mcxa276`` is renamed to ``frdm_mcxa266``. +* Panasonic ``panb511evb`` is renamed to ``panb611evb``. + Device Drivers and Devicetree ***************************** @@ -95,6 +114,12 @@ Bluetooth Audio .. zephyr-keep-sorted-stop +Bluetooth HCI +============= + +* The deprecated ``ipm`` value was removed from ``bt-hci-bus`` devicetree property. + ``ipc`` should be used instead. + Ethernet ======== @@ -102,6 +127,17 @@ Ethernet the GPIO_ACTIVE_LOW flag when the reset is being used as active low. Previously the active-low nature was hard-coded into the driver. (:github:`91726`). +* CRC checksum generation offloading to hardware is now explicitly disabled rather then explicitly + enabled in the Xilinx GEM Ethernet driver (:dtcompatible:`xlnx,gem`). By default, offloading is + now enabled by default to improve performance, however, offloading is always disabled for QEMU + targets due to the checksum generation in hardware not being emulated regardless of whether it + is explicitly disabled via the devicetree or not. (:github:`95435`) + + * Replaced devicetree property ``rx-checksum-offload`` which enabled RX checksum offloading + ``disable-rx-checksum-offload`` which now actively disables it. + * Replaced devicetree property ``tx-checksum-offload`` which enabled TX checksum offloading + ``disable-tx-checksum-offload`` which now actively disables it. + Networking ********** @@ -146,6 +182,27 @@ Logging used. The new script supports the same functionality (and more), but requires different command line arguments when invoked. +Secure storage +============== + +* The size of :c:type:`psa_storage_uid_t`, used to identify storage entries, was changed from 64 to + 30 bits. + This change breaks backward compatibility with previously stored entries for which authentication + will start failing. + Enable :kconfig:option:`CONFIG_SECURE_STORAGE_64_BIT_UID` if you are updating an existing + installation from an earlier version of Zephyr and want to keep the pre-existing entries. + (:github:`94171`) + +Shell +===== + +* The MQTT topics related to :kconfig:option:`SHELL_BACKEND_MQTT` have been renamed. Renamed + ``_rx`` to ``/sh/rx`` and ``_tx`` to ``/sh/rx``. The + part after the ```` is now configurable via :kconfig:option:`SHELL_MQTT_TOPIC_RX_ID` + and :kconfig:option:`SHELL_MQTT_TOPIC_TX_ID`. This allows keeping the previous topics for backward + compatibility. + (:github:`92677`). + .. zephyr-keep-sorted-stop Modules diff --git a/doc/releases/release-notes-3.5.rst b/doc/releases/release-notes-3.5.rst index d643d4b5dba45..401181037febb 100644 --- a/doc/releases/release-notes-3.5.rst +++ b/doc/releases/release-notes-3.5.rst @@ -344,7 +344,7 @@ Boards & SoC Support * Added support for these POSIX boards: - * :ref:`native_sim(_64) ` + * :zephyr:board:`native_sim(_64) ` * nrf5340bsim_nrf5340_cpu(net|app). A simulated nrf5340 SOC, which uses Babblesim for its radio traffic. diff --git a/doc/releases/release-notes-3.6.rst b/doc/releases/release-notes-3.6.rst index 06c587298f3fc..95f98ba97e5d5 100644 --- a/doc/releases/release-notes-3.6.rst +++ b/doc/releases/release-notes-3.6.rst @@ -18,8 +18,8 @@ Major enhancements with this release include: * Userspace support extended to Xtensa architecture. * Build system now supports Link Time Optimization (LTO), reducing the size of the final image. * Bluetooth Mesh protocol 1.1 now supported by default. -* Major updates to the documentation of the :ref:`native simulator `, clarifying - supported peripherals and how to use them. +* Major updates to the documentation of the :zephyr:board:`native simulator `, + clarifying supported peripherals and how to use them. * Over 30 new supported boards, spanning all Zephyr-supported architectures. An overview of the changes required or recommended when migrating your application from Zephyr @@ -1301,7 +1301,7 @@ Additionally, the following changes in Zephyr were done: Tests and Samples ***************** -* :ref:`native_sim` has replaced ``native_posix`` as the default +* :zephyr:board:`native_sim` has replaced ``native_posix`` as the default test platform. ``native_posix`` remains supported and used in testing but will be deprecated in a future release. diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index 9f81deebf40ab..2364f7978e7e8 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -30,8 +30,8 @@ Major enhancements with this release include: data flows than the previous fetch/get APIs. * A new :ref:`LLEXT Extension Developer Kit (EDK) ` makes it easier to develop and integrate custom extensions into Zephyr, including outside of the Zephyr tree. -* :ref:`Native simulator ` now supports leveraging the native host networking stack - without having to rely on a complex setup of the host environment. +* :zephyr:board:`Native simulator ` now supports leveraging the native host networking + stack without having to rely on a complex setup of the host environment. * Trusted Firmware-M (TF-M) 2.1.0 and Mbed TLS 3.6.0 have been integrated into Zephyr. Both of these versions are LTS releases. What's more, :ref:`psa_crypto` has been adopted as a replacement for TinyCrypt and provides enhanced security and performance. diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index 99d9a711f485c..7a138429da8ff 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -113,7 +113,7 @@ Deprecated in this release * Deprecated the TinyCrypt shim driver ``CONFIG_CRYPTO_TINYCRYPT_SHIM``. * ``native_posix`` has been deprecated in favour of - :ref:`native_sim`. + :zephyr:board:`native_sim`. * ``include/zephyr/net/buf.h`` is deprecated in favor of ``include/zephyr/net_buf.h>``. The old header will be removed in future releases @@ -1542,7 +1542,7 @@ Tests and Samples ***************** * Together with the deprecation of ``native_posix``, many tests which were - explicitly run in native_posix now run in :ref:`native_sim` instead. + explicitly run in native_posix now run in :zephyr:board:`native_sim` instead. native_posix as a platform remains tested though. * Extended the tests of counter_basic_api with a testcase for counters without alarms * Added support for testing SDMMC devices to the fatfs API test diff --git a/doc/releases/release-notes-4.1.rst b/doc/releases/release-notes-4.1.rst index e23bdb695f3c6..7d850846d3ffb 100644 --- a/doc/releases/release-notes-4.1.rst +++ b/doc/releases/release-notes-4.1.rst @@ -446,7 +446,7 @@ New Boards * Panasonic Corporation - * :zephyr:board:`panb511evb` (``panb511evb``) + * PAN B511 Evaluation Board (``panb511evb``) * Peregrine Consultoria e Servicos diff --git a/doc/releases/release-notes-4.3.rst b/doc/releases/release-notes-4.3.rst index a44210c132135..6dfc304b3ef50 100644 --- a/doc/releases/release-notes-4.3.rst +++ b/doc/releases/release-notes-4.3.rst @@ -60,10 +60,13 @@ Removed APIs and options * The TinyCrypt library was removed as the upstream version is no longer maintained. PSA Crypto API is now the recommended cryptographic library for Zephyr. +* The legacy pipe object API was removed. Use the new pipe API instead. Deprecated APIs and options =========================== +* :dtcompatible:`maxim,ds3231` is deprecated in favor of :dtcompatible:`maxim,ds3231-rtc`. + New APIs and options ==================== @@ -77,7 +80,17 @@ New APIs and options * Architectures + * :kconfig:option:`CONFIG_ARCH_HAS_HW_SHADOW_STACK` * :kconfig:option:`CONFIG_SRAM_SW_ISR_TABLE` + + * x86 Intel CET support + + * :kconfig:option:`CONFIG_X86_CET` + * :kconfig:option:`CONFIG_X86_CET_IBT` + * :kconfig:option:`CONFIG_X86_CET_SHADOW_STACK_ALIGNMENT` + * :kconfig:option:`CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH` + * :kconfig:option:`CONFIG_X86_CET_VERIFY_KERNEL_SHADOW_STACK` + * ARM (Cortex-M) system state save/restore primitives * :c:func:`z_arm_save_scb_context` / :c:func:`z_arm_restore_scb_context` @@ -90,13 +103,23 @@ New APIs and options * :c:struct:`bt_audio_codec_cfg` now contains a target_latency and a target_phy option * :c:func:`bt_bap_broadcast_source_foreach_stream` + * :c:func:`bt_cap_initiator_broadcast_foreach_stream` * :c:struct:`bt_bap_stream` now contains an ``iso`` field as a reference to the ISO channel + * :c:func:`bt_bap_unicast_group_get_info` + * :c:func:`bt_cap_unicast_group_get_info` * Host * :c:struct:`bt_iso_unicast_info` now contains a ``cig_id`` and a ``cis_id`` field * :c:struct:`bt_iso_broadcaster_info` now contains a ``big_handle`` and a ``bis_number`` field * :c:struct:`bt_iso_sync_receiver_info` now contains a ``big_handle`` and a ``bis_number`` field + * :c:struct:`bt_le_ext_adv_info` now contains an ``sid`` field with the Advertising Set ID. + +* CPUFreq + + * Introduced experimental dynamic CPU frequency scaling subsystem + + * :kconfig:option:`CONFIG_CPU_FREQ` * Display @@ -107,6 +130,20 @@ New APIs and options * :kconfig:option:`CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_AL_88` * :kconfig:option:`CONFIG_SDL_DISPLAY_COLOR_TINT` +* Kernel + + * :kconfig:option:`CONFIG_HW_SHADOW_STACK` + * :kconfig:option:`CONFIG_HW_SHADOW_STACK_ALLOW_REUSE` + * :kconfig:option:`CONFIG_HW_SHADOW_STACK_MIN_SIZE` + * :kconfig:option:`CONFIG_HW_SHADOW_STACK_PERCENTAGE_SIZE` + * :c:macro:`K_THREAD_HW_SHADOW_STACK_SIZE` + * :c:macro:`K_KERNEL_HW_SHADOW_STACK_DECLARE` + * :c:macro:`K_KERNEL_HW_SHADOW_STACK_ARRAY_DECLARE` + * :c:macro:`K_THREAD_HW_SHADOW_STACK_DEFINE` + * :c:macro:`K_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE` + * :c:macro:`K_THREAD_HW_SHADOW_STACK_ATTACH` + * :c:macro:`k_thread_hw_shadow_stack_attach` + * Logging: * Added rate-limited logging macros to prevent log flooding when messages are generated frequently. @@ -128,6 +165,12 @@ New APIs and options * :c:macro:`LOG_HEXDUMP_INF_RATELIMIT_RATE` - Rate-limited info hexdump macro (explicit rate) * :c:macro:`LOG_HEXDUMP_DBG_RATELIMIT_RATE` - Rate-limited debug hexdump macro (explicit rate) +* Management + + * hawkBit + + * :kconfig:option:`CONFIG_HAWKBIT_REBOOT_NONE` + * Power management * :c:func:`pm_device_driver_deinit` @@ -136,6 +179,24 @@ New APIs and options * :kconfig:option:`CONFIG_SETTINGS_TFM_ITS` +* Shell + + * MQTT backend + + * :kconfig:option:`CONFIG_SHELL_MQTT_TOPIC_RX_ID` + * :kconfig:option:`CONFIG_SHELL_MQTT_TOPIC_TX_ID` + * :kconfig:option:`CONFIG_SHELL_MQTT_CONNECT_TIMEOUT_MS` + * :kconfig:option:`CONFIG_SHELL_MQTT_WORK_DELAY_MS` + * :kconfig:option:`CONFIG_SHELL_MQTT_LISTEN_TIMEOUT_MS` + +* Storage + + * :kconfig:option:`CONFIG_FILE_SYSTEM_SHELL_LS_SIZE` + +* Sys + + * :c:func:`sys_count_bits` + .. zephyr-keep-sorted-stop New Boards @@ -166,6 +227,9 @@ New Drivers * STM32 RTC driver has been updated to use the new STM32 EXTI interrupt controller API +* Sensors + + * :dtcompatible:`we,wsen-isds-2536030320001` New Samples *********** diff --git a/doc/security/control-flow-integrity.rst b/doc/security/control-flow-integrity.rst new file mode 100644 index 0000000000000..a32ccab79e904 --- /dev/null +++ b/doc/security/control-flow-integrity.rst @@ -0,0 +1,47 @@ +.. _control_flow_integrity: + +Control Flow Integrity +###################### + +Control Flow Integrity (CFI) is a security feature that ensures that the control flow of a program follows a predefined path, preventing attackers from diverting execution to malicious code. CFI is particularly useful in defending against control flow hijacking attacks, such as return-oriented programming (ROP) and jump-oriented programming (JOP). + +CFI works by validating the control flow of a program at runtime, ensuring that function calls and returns are made to legitimate targets. This is typically achieved through instrumentation of the code, which adds checks to verify that the control flow adheres to the expected paths defined by the program's control flow graph. + +Forward and return edges +------------------------ + +In the context of CFI, control flow edges can be categorized into two types: + +1. **Forward edges**: These represent the flow of control from one function to another, such as a function call. Forward edges are typically validated to ensure that the target of a call is a legitimate function within the program. +2. **Return edges**: These represent the return from a function back to the caller. Return edges are validated to ensure that the return address is legitimate and corresponds to a valid call site. + +Forward edges can be supported by compiler instrumentation, which adds checks to verify that the target of a function call is valid. Return edges can be supported by maintaining a shadow stack or using other mechanisms to ensure that return addresses are legitimate. + +Zephyr does support maintaining a shadow stack which can be enabled via :kconfig:option:`CONFIG_HW_SHADOW_STACK`. Then, the kernel will use macros like :c:macro:`K_THREAD_HW_SHADOW_STACK_DEFINE`, in tandem with other thread stack related macros, to provide the area for shadow stacks used by threads. Usually, applications only need to enable :kconfig:option:`CONFIG_HW_SHADOW_STACK` (and related ones, such as :kconfig:option:`CONFIG_HW_SHADOW_STACK_PERCENTAGE_SIZE` and :kconfig:option:`CONFIG_HW_SHADOW_STACK_MIN_SIZE`) to enable shadow stack support. The kernel will then automatically manage the shadow stack for each thread. + +Implementation details +********************** + +The ``K_THREAD_HW_SHADOW_STACK*`` family of macros does a minimal setup of the shadow stack parameters. Then, they invoke arch-specific ``ARCH_THREAD_HW_SHADOW_STACK*`` macros to perform the actual setup. + +Hardware support +---------------- + +While CFI can be implemented in software, hardware support can significantly enhance its effectiveness and performance. Currently, Zephyr supports Intel Control-flow Enforcement Technology (CET), which provides hardware-based support for CFI. + +Intel CET +********* + +Intel Control-flow Enforcement Technology (CET) is a set of hardware features that enhance the security of applications by providing support for CFI. CET includes two main components: + +1. **Shadow Stack**: This feature maintains a separate stack for return addresses, ensuring that return addresses cannot be tampered with. When a function returns, the return address is popped from the shadow stack and compared to that of the regular stack, providing an additional layer of protection against control flow hijacking. +2. **Indirect Branch Tracking (IBT)**: This feature tracks indirect branches (such as function pointers) and ensures that they only target valid locations in the code. It prevents attackers from redirecting execution to arbitrary code through techniques like ROP. + +These two features proved the return and forward edge validation, respectively. To enable shadow stack support in Zephyr, on supported hardware, you can use the :kconfig:option:`CONFIG_HW_SHADOW_STACK` Kconfig option. To enable IBT, use :kconfig:option:`CONFIG_X86_CET_IBT`. + +As IBT is effectively implemented by the compiler, toolchain support is necessary. Currently, Zephyr SDK x86 toolchain can be used to build applications with IBT support. However, their precompiled artifacts, such as ``libc`` and ``libgcc``, do not have IBT enabled. Therefore, for ``libc``, one needs to build it as a module, for example, by using :kconfig:option:`CONFIG_PICOLIBC_USE_MODULE`. For other bits, one would need a custom toolchain. + +Limitations +----------- + +Currently, the shadow stacks that are created behind the scenes live on the global namespace. Thus, one *cannot* reuse thread stack names, even across different compilation units. diff --git a/doc/security/hardening-tool.rst b/doc/security/hardening-tool.rst index 7b69193ce36e7..1b0cd171b2225 100644 --- a/doc/security/hardening-tool.rst +++ b/doc/security/hardening-tool.rst @@ -35,14 +35,20 @@ used instead. .. code-block:: console - name | current | recommended || check result - ================================================================================================ - CONFIG_BOOT_BANNER | y | n || FAIL - CONFIG_BUILD_OUTPUT_STRIPPED | n | y || FAIL - CONFIG_FAULT_DUMP | 2 | 0 || FAIL - CONFIG_HW_STACK_PROTECTION | n | y || FAIL - CONFIG_MPU_STACK_GUARD | n | y || FAIL - CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT | n | y || FAIL - CONFIG_STACK_SENTINEL | n | y || FAIL - CONFIG_EARLY_CONSOLE | y | n || FAIL - CONFIG_PRINTK | y | n || FAIL + +---------------------------------------+-----------+---------------+----------------+ + | Name | Current | Recommended | Check result | + +=======================================+===========+===============+================+ + | CONFIG_BUILD_OUTPUT_STRIPPED | n | y | FAIL | + +---------------------------------------+-----------+---------------+----------------+ + | CONFIG_FAULT_DUMP | 2 | 0 | FAIL | + +---------------------------------------+-----------+---------------+----------------+ + | CONFIG_MPU_STACK_GUARD | n | y | FAIL | + +---------------------------------------+-----------+---------------+----------------+ + | CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT | n | y | FAIL | + +---------------------------------------+-----------+---------------+----------------+ + | CONFIG_STACK_SENTINEL | n | y | FAIL | + +---------------------------------------+-----------+---------------+----------------+ + | CONFIG_EXCEPTION_DEBUG | y | n | FAIL | + +---------------------------------------+-----------+---------------+----------------+ + | CONFIG_PRINTK | y | n | FAIL | + +---------------------------------------+-----------+---------------+----------------+ diff --git a/doc/security/index.rst b/doc/security/index.rst index f05691c014e7e..4514e675e28e1 100644 --- a/doc/security/index.rst +++ b/doc/security/index.rst @@ -15,5 +15,6 @@ for ensuring security is addressed within the Zephyr project. secure-coding.rst sensor-threat.rst hardening-tool.rst + control-flow-integrity.rst vulnerabilities.rst standards/index.rst diff --git a/doc/services/cpu_freq/index.rst b/doc/services/cpu_freq/index.rst new file mode 100644 index 0000000000000..a4b3d6a9e7ec2 --- /dev/null +++ b/doc/services/cpu_freq/index.rst @@ -0,0 +1,71 @@ +.. _cpu_freq: + +CPU Frequency Scaling +##################### + +.. toctree:: + :maxdepth: 1 + + policies/index.rst + +Overview +******** + +The CPU Frequency Scaling subsystem in Zephyr provides a framework for SoC's to dynamically adjust +their processor frequency based on a monitored metric and performance state (p-state) policy +algorithm. + +Design Goals +************ + +The CPU Frequency Scaling subsystem aims to provide a framework that allows for any policy algorithm +to work with any p-state driver and allows for each policy to make use of one, or many, metrics to +determine an optimal CPU frequency. The subsystem should be flexible enough to allow for SoC vendors +to define custom p-states, thresholds and metrics. + +P-state Policies +**************** + +A p-state policy is an algorithm that determines what the optimal p-state is for the CPU based on +the metrics it consumes and the thresholds defined per p-state. A policy can consume one, or many, +metrics to determine the optimal CPU frequency based on the desired statistics of the system. + +See :ref:`policies ` for a list of standard policies. + +Metrics +******* + +A P-state policy should include one or more metrics to base decisions. Examples of metrics could +include percent CPU load, SoC temperature, etc. + +For an example of a metric in use, see the :ref:`on_demand ` policy. + +P-state Drivers +*************** + +A SoC supporting the CPU Freq subsystem must implement a p-state driver that implements +:c:func:`cpu_freq_pstate_set` which applies the passed in ``p_state`` to +the CPU when called. + +A SoC must also provide the available p-states in devicetree by having a +:dtcompatible:`zephyr,pstate` compatible node. The SoC may also define its own p-state binding, +which extends :dtcompatible:`zephyr,pstate` to include additional properties that may be used by +the SoC's p-state driver. + +Usage considerations +******************** + +The CPU Frequency Scaling subsystem assumes that each CPU is clocked independently and that a +p-state transition does not impact an unrelated CPU of the SoC. + +The SoC supporting CPU Freq must uphold Zephyr's requirement that the system timer remains constant +over the lifetime of the program. See :ref:`Kernel Timing ` for more information. + +The CPU Frequency Scaling subsystem runs as a handler function to a ``k_timer``, which means it runs +in interrupt context (IRQ). The SoC p-state driver must ensure that its implementation of +:c:func:`cpu_freq_pstate_set` is IRQ context safe. If a p-state transition +cannot be completed reasonably in an IRQ context, it is recommended that the p-state driver of the +SoC implements its task as a workqueue item. + +CPU Frequency Scaling subsystem is not compatible with SMP as of now since the thread can migrate +between cores during execution, causing per-CPU metrics to be attributed to the wrong CPU. diff --git a/doc/services/cpu_freq/policies/index.rst b/doc/services/cpu_freq/policies/index.rst new file mode 100644 index 0000000000000..72129dd64b5d2 --- /dev/null +++ b/doc/services/cpu_freq/policies/index.rst @@ -0,0 +1,9 @@ +.. _cpu_freq_policies: + +CPU Frequency Scaling Policies +############################## + +.. toctree:: + :maxdepth: 1 + + on_demand.rst diff --git a/doc/services/cpu_freq/policies/on_demand.rst b/doc/services/cpu_freq/policies/on_demand.rst new file mode 100644 index 0000000000000..ea1d3e15b093a --- /dev/null +++ b/doc/services/cpu_freq/policies/on_demand.rst @@ -0,0 +1,17 @@ +.. _on_demand_policy: + +On-Demand CPU Frequency Scaling Policy +###################################### + +The On-Demand policy evaluates the current CPU load using the +:ref:`CPU Load subsystem `, and compares it to the trigger threshold defined by the +SoC P-state definition. + +The On-Demand policy will iterate through the defined P-states and select the first P-state of which +the CPU load exceeds the defined threshold. + +For an example of the on-demand policy refer to the :zephyr:code-sample:`cpu_freq_on_demand` sample. + +This policy is reactive. Frequency adjustments occur only after a change in system load has been +observed, so it cannot anticipate sudden high loads. The policy has no notion of task deadlines and +should not be considered as a real-time policy. diff --git a/doc/services/cpu_load/index.rst b/doc/services/cpu_load/index.rst new file mode 100644 index 0000000000000..68fb257ebba20 --- /dev/null +++ b/doc/services/cpu_load/index.rst @@ -0,0 +1,9 @@ +.. _cpu_load_subsys: + +CPU Load +######## + +The CPU Load subsystem returns the CPU load as a percentage for the current CPU, since the last time +it was called. + +For an example of the CPU Load subsystem refer to :zephyr:code-sample:`cpu_freq_on_demand` sample. diff --git a/doc/services/index.rst b/doc/services/index.rst index 69050cb784fc5..7e8a96d320a35 100644 --- a/doc/services/index.rst +++ b/doc/services/index.rst @@ -8,6 +8,8 @@ OS Services binary_descriptors/index.rst console.rst + cpu_freq/index.rst + cpu_load/index.rst crypto/index debugging/index.rst device_mgmt/index @@ -22,7 +24,6 @@ OS Services resource_management/index.rst mem_mgmt/index.rst net_buf/index.rst - modbus/index.rst modem/index.rst notify.rst pm/index.rst diff --git a/doc/services/pm/device.rst b/doc/services/pm/device.rst index bfd0603e642b6..e068e7d8b07ea 100644 --- a/doc/services/pm/device.rst +++ b/doc/services/pm/device.rst @@ -311,7 +311,7 @@ for brevity, in real drivers they must be handled. * ACTIVE in cases of high throughput or unsolicitet data on the * bus, to avoid inefficient RESUME/SUSPEND cycles of the bus * for every transaction, and allowing reception of unsolicitet - * data on busses like UART. + * data on buses like UART. */ (void)pm_device_runtime_put(config->bus); (void)pm_device_runtime_put(config->enable_pin.port); @@ -511,7 +511,7 @@ used to move the device to the ``ACTIVE`` state through calling state, this results in a call to ``PM_DEVICE_ACTION_TURN_ON`` followed by ``PM_DEVICE_ACTION_RESUME``. -Given power domains and busses are "just devices", every power +Given power domains and buses are "just devices", every power domain and bus will be resumed before its child devices as they are initialized according to the devicetree dependency ordinals. Every device is assumed to be powered, and the devices a device diff --git a/doc/services/sensing/index.rst b/doc/services/sensing/index.rst index 976599826d8fa..db661c31a3c67 100644 --- a/doc/services/sensing/index.rst +++ b/doc/services/sensing/index.rst @@ -246,7 +246,4 @@ See the example :zephyr_file:`samples/subsys/sensing/simple/boards/native_sim.ov API Reference ************* -.. doxygengroup:: sensing_sensor_types -.. doxygengroup:: sensing_datatypes .. doxygengroup:: sensing_api -.. doxygengroup:: sensing_sensor diff --git a/doc/services/smf/index.rst b/doc/services/smf/index.rst index 770717dd0a300..14e68d0470dac 100644 --- a/doc/services/smf/index.rst +++ b/doc/services/smf/index.rst @@ -551,7 +551,7 @@ state. The statechart for this test is below. STATE_B [shape = box]; STATE_C [shape = box]; STATE_D [shape = box]; - DC[shape=point height=0 width=0 label=<>] + DC[shape=point height=0 width=0 label="" style="invis"] subgraph cluster_root { label = "ROOT"; diff --git a/doc/services/storage/secure_storage/index.rst b/doc/services/storage/secure_storage/index.rst index 57f7dc03b27ee..1829b435ea968 100644 --- a/doc/services/storage/secure_storage/index.rst +++ b/doc/services/storage/secure_storage/index.rst @@ -43,9 +43,18 @@ The secure storage subsystem's implementation of the PSA Secure Storage API: Instead, the PS API directly calls into the Internal Trusted Storage (ITS) API (unless a `custom implementation <#whole-api>`_ of the PS API is provided). -Below are some ways the implementation deviates from the specification +Below are some ways the implementation purposefully deviates from the specification and an explanation why. This is not an exhaustive list. +* The UID type is only 30 bits by default. (Against `2.5 UIDs `_.) + + | This is an optimization done to make it more convenient to directly use the UIDs as + storage entry IDs (e.g., with :ref:`ZMS ` when + :kconfig:option:`CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS` is enabled). + | Zephyr defines numerical ranges to be used by different users of the API which guarantees that + there are no collisions and that they all fit within 30 bits. + See the header files in :zephyr_file:`include/zephyr/psa` for more information. + * The data stored in the ITS is by default encrypted and authenticated (Against ``1.`` in `3.2. Internal Trusted Storage requirements `_.) diff --git a/doc/services/tracing/index.rst b/doc/services/tracing/index.rst index 41b03c2652177..41f1fc3161929 100644 --- a/doc/services/tracing/index.rst +++ b/doc/services/tracing/index.rst @@ -499,8 +499,8 @@ Using Tracing The sample :zephyr_file:`samples/subsys/tracing` demonstrates tracing with different formats and backends. -To get started, the simplest way is to use the CTF format with the :ref:`native_sim ` -port, build the sample as follows: +To get started, the simplest way is to use the CTF format with the +:zephyr:board:`native_sim ` port, build the sample as follows: .. zephyr-app-commands:: :tool: all diff --git a/doc/services/zbus/images/zbus_type_of_observers.svg b/doc/services/zbus/images/zbus_type_of_observers.svg index 34b1be733076b..a1f0ad945d3da 100644 --- a/doc/services/zbus/images/zbus_type_of_observers.svg +++ b/doc/services/zbus/images/zbus_type_of_observers.svg @@ -1,14 +1,14 @@ + - - - - - - - - - + + + + + + + + diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index ad12a91316015..ed668b9534230 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -28,6 +28,7 @@ add_subdirectory_ifdef(CONFIG_COMPARATOR comparator) add_subdirectory_ifdef(CONFIG_CONSOLE console) add_subdirectory_ifdef(CONFIG_COREDUMP_DEVICE coredump) add_subdirectory_ifdef(CONFIG_COUNTER counter) +add_subdirectory_ifdef(CONFIG_CRC_DRIVER crc) add_subdirectory_ifdef(CONFIG_CRYPTO crypto) add_subdirectory_ifdef(CONFIG_DAC dac) add_subdirectory_ifdef(CONFIG_DAI dai) diff --git a/drivers/Kconfig b/drivers/Kconfig index d2ebb120032c6..dcb941ee1654a 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -20,6 +20,7 @@ source "drivers/comparator/Kconfig" source "drivers/console/Kconfig" source "drivers/coredump/Kconfig" source "drivers/counter/Kconfig" +source "drivers/crc/Kconfig" source "drivers/crypto/Kconfig" source "drivers/dac/Kconfig" source "drivers/dai/Kconfig" diff --git a/drivers/adc/adc_nrfx_saadc.c b/drivers/adc/adc_nrfx_saadc.c index 614973261746f..06035e2c3c5d4 100644 --- a/drivers/adc/adc_nrfx_saadc.c +++ b/drivers/adc/adc_nrfx_saadc.c @@ -76,6 +76,13 @@ static const uint32_t saadc_psels[NRF_SAADC_AIN7 + 1] = { [NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(11U, 1), [NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), }; +#elif defined(NRF54LS05B_ENGA_XXAA) +static const uint32_t saadc_psels[NRF_SAADC_AIN3 + 1] = { + [NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1), + [NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1), + [NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1), + [NRF_SAADC_AIN3] = NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1), +}; #endif #else diff --git a/drivers/adc/adc_sam.c b/drivers/adc/adc_sam.c index 32b8450ef0fda..58c3ed5f691ba 100644 --- a/drivers/adc/adc_sam.c +++ b/drivers/adc/adc_sam.c @@ -16,6 +16,7 @@ #include #include +#include LOG_MODULE_REGISTER(adc_sam, CONFIG_ADC_LOG_LEVEL); #define SAM_ADC_NUM_CHANNELS 16 @@ -51,18 +52,6 @@ struct adc_sam_data { uint8_t num_active_channels; }; -static uint8_t count_bits(uint32_t val) -{ - uint8_t res = 0; - - while (val) { - res += val & 1U; - val >>= 1; - } - - return res; -} - static int adc_sam_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg) { @@ -156,7 +145,8 @@ static void adc_context_start_sampling(struct adc_context *ctx) const struct adc_sam_config *const cfg = data->dev->config; Adc *const adc = cfg->regs; - data->num_active_channels = count_bits(ctx->sequence.channels); + data->num_active_channels = + sys_count_bits(&ctx->sequence.channels, sizeof(ctx->sequence.channels)); /* Disable all */ adc->ADC_CHDR = 0xffff; @@ -222,7 +212,7 @@ static int start_read(const struct device *dev, return -EINVAL; } - data->num_active_channels = count_bits(channels); + data->num_active_channels = sys_count_bits(&channels, sizeof(channels)); error = check_buffer_size(sequence, data->num_active_channels); if (error) { diff --git a/drivers/adc/iadc_gecko.c b/drivers/adc/iadc_gecko.c index 876da1d7c735f..818183c328dd6 100644 --- a/drivers/adc/iadc_gecko.c +++ b/drivers/adc/iadc_gecko.c @@ -127,7 +127,7 @@ static int start_read(const struct device *dev, const struct adc_sequence *seque if (sequence->oversampling) { LOG_ERR("Oversampling is not supported"); - return -ENOTSUP; + return -EINVAL; } /* Check resolution setting */ @@ -331,7 +331,7 @@ static int adc_gecko_channel_setup(const struct device *dev, break; default: LOG_ERR("unsupported channel gain '%d'", channel_cfg->gain); - return -ENOTSUP; + return -EINVAL; } /* Setup reference */ @@ -353,7 +353,7 @@ static int adc_gecko_channel_setup(const struct device *dev, default: LOG_ERR("unsupported channel reference type '%d'", channel_cfg->reference); - return -ENOTSUP; + return -EINVAL; } channel_config->initialized = true; diff --git a/drivers/audio/dmic_nrfx_pdm.c b/drivers/audio/dmic_nrfx_pdm.c index 1aaeaa65b1500..f0162fc5ef8ba 100644 --- a/drivers/audio/dmic_nrfx_pdm.c +++ b/drivers/audio/dmic_nrfx_pdm.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -15,10 +16,19 @@ #include LOG_MODULE_REGISTER(dmic_nrfx_pdm, CONFIG_AUDIO_DMIC_LOG_LEVEL); +#define NODE_AUDIO_AUXPLL DT_NODELABEL(audio_auxpll) +#define NODE_AUDIOPLL DT_NODELABEL(audiopll) + #if CONFIG_SOC_SERIES_NRF54HX #define DMIC_NRFX_CLOCK_FREQ MHZ(16) #define DMIC_NRFX_CLOCK_FACTOR 8192 -#define DMIC_NRFX_AUDIO_CLOCK_FREQ DT_PROP_OR(DT_NODELABEL(audiopll), frequency, 0) +#define DMIC_NRFX_AUDIO_CLOCK_FREQ DT_PROP_OR(NODE_AUDIOPLL, frequency, 0) +#elif DT_NODE_HAS_STATUS_OKAY(NODE_AUDIO_AUXPLL) +#define DMIC_NRFX_AUDIO_CLOCK_FREQ DT_PROP(NODE_AUDIO_AUXPLL, nordic_frequency) +BUILD_ASSERT((DMIC_NRFX_AUDIO_CLOCK_FREQ == NRF_AUXPLL_FREQ_DIV_AUDIO_48K) || + (DMIC_NRFX_AUDIO_CLOCK_FREQ == NRF_AUXPLL_FREQ_DIV_AUDIO_44K1), + "Unsupported Audio AUXPLL frequency selection for PDM"); +#define DMIC_NRFX_CLOCK_FREQ MHZ(32) #else #define DMIC_NRFX_CLOCK_FREQ MHZ(32) #define DMIC_NRFX_CLOCK_FACTOR 4096 @@ -28,10 +38,10 @@ LOG_MODULE_REGISTER(dmic_nrfx_pdm, CONFIG_AUDIO_DMIC_LOG_LEVEL); struct dmic_nrfx_pdm_drv_data { const nrfx_pdm_t *pdm; -#if CONFIG_CLOCK_CONTROL_NRF - struct onoff_manager *clk_mgr; -#elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL +#if CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL || DT_NODE_HAS_STATUS_OKAY(NODE_AUDIO_AUXPLL) const struct device *audiopll_dev; +#elif CONFIG_CLOCK_CONTROL_NRF + struct onoff_manager *clk_mgr; #endif struct onoff_client clk_cli; struct k_mem_slab *mem_slab; @@ -73,10 +83,10 @@ static int request_clock(struct dmic_nrfx_pdm_drv_data *drv_data) if (!drv_data->request_clock) { return 0; } -#if CONFIG_CLOCK_CONTROL_NRF - return onoff_request(drv_data->clk_mgr, &drv_data->clk_cli); -#elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL +#if CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL || DT_NODE_HAS_STATUS_OKAY(NODE_AUDIO_AUXPLL) return nrf_clock_control_request(drv_data->audiopll_dev, NULL, &drv_data->clk_cli); +#elif CONFIG_CLOCK_CONTROL_NRF + return onoff_request(drv_data->clk_mgr, &drv_data->clk_cli); #else return -ENOTSUP; #endif @@ -87,11 +97,10 @@ static int release_clock(struct dmic_nrfx_pdm_drv_data *drv_data) if (!drv_data->request_clock) { return 0; } - -#if CONFIG_CLOCK_CONTROL_NRF - return onoff_release(drv_data->clk_mgr); -#elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL +#if CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL || DT_NODE_HAS_STATUS_OKAY(NODE_AUDIO_AUXPLL) return nrf_clock_control_release(drv_data->audiopll_dev, NULL); +#elif CONFIG_CLOCK_CONTROL_NRF + return onoff_release(drv_data->clk_mgr); #else return -ENOTSUP; #endif @@ -659,9 +668,11 @@ static int dmic_nrfx_pdm_read(const struct device *dev, static void init_clock_manager(const struct device *dev) { -#if CONFIG_CLOCK_CONTROL_NRF - clock_control_subsys_t subsys; struct dmic_nrfx_pdm_drv_data *drv_data = dev->data; +#if DT_NODE_HAS_STATUS_OKAY(NODE_AUDIO_AUXPLL) + drv_data->audiopll_dev = DEVICE_DT_GET(NODE_AUDIO_AUXPLL); +#elif CONFIG_CLOCK_CONTROL_NRF + clock_control_subsys_t subsys; #if NRF_CLOCK_HAS_HFCLKAUDIO const struct dmic_nrfx_pdm_drv_cfg *drv_cfg = dev->config; @@ -678,7 +689,7 @@ static void init_clock_manager(const struct device *dev) #elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL struct dmic_nrfx_pdm_drv_data *drv_data = dev->data; - drv_data->audiopll_dev = DEVICE_DT_GET(DT_NODELABEL(audiopll)); + drv_data->audiopll_dev = DEVICE_DT_GET(NODE_AUDIOPLL); #endif } @@ -739,12 +750,16 @@ static const struct _dmic_ops dmic_ops = { hfclkaudio_frequency) || \ DT_NODE_HAS_PROP(DT_NODELABEL(aclk), \ clock_frequency) || \ - DT_NODE_HAS_PROP(DT_NODELABEL(audiopll), \ - frequency), \ - "Clock source ACLK requires the hfclkaudio-frequency " \ - "property to be defined in the nordic,nrf-clock node " \ - "or clock-frequency property to be defined in aclk node" \ - "or frequency property to be defined in audiopll node"); \ + DT_NODE_HAS_PROP(NODE_AUDIOPLL, \ + frequency) || \ + DT_NODE_HAS_PROP(NODE_AUDIO_AUXPLL, \ + nordic_frequency), \ + "Clock source ACLK requires one following defined frequency "\ + "properties: " \ + "hfclkaudio-frequency in the nordic,nrf-clock node, " \ + "clock-frequency in the aclk node, " \ + "frequency in the audiopll node, " \ + "nordic-frequency in the audio_auxpll node"); \ DEVICE_DT_DEFINE(PDM(idx), pdm_nrfx_init##idx, NULL, \ &dmic_nrfx_pdm_data##idx, &dmic_nrfx_pdm_cfg##idx, \ POST_KERNEL, CONFIG_AUDIO_DMIC_INIT_PRIORITY, \ diff --git a/drivers/bluetooth/hci/Kconfig b/drivers/bluetooth/hci/Kconfig index a8ee4e531371d..f1d1939259dca 100644 --- a/drivers/bluetooth/hci/Kconfig +++ b/drivers/bluetooth/hci/Kconfig @@ -171,6 +171,9 @@ config BT_SILABS_EFR32 select BT_CTLR_ADV_EXT_SUPPORT select BT_CTLR_PRIVACY_SUPPORT select BT_CTLR_PHY_2M_SUPPORT + select BT_CTLR_SYNC_PERIODIC_SUPPORT + select BT_CTLR_SYNC_TRANSFER_RECEIVER_SUPPORT + select BT_CTLR_SYNC_TRANSFER_SENDER_SUPPORT help Use Silicon Labs binary Bluetooth library to connect to the controller. diff --git a/drivers/bluetooth/hci/apollox_blue.c b/drivers/bluetooth/hci/apollox_blue.c index 9a4bf5440d87d..40283894f8032 100644 --- a/drivers/bluetooth/hci/apollox_blue.c +++ b/drivers/bluetooth/hci/apollox_blue.c @@ -343,9 +343,23 @@ int bt_apollo_controller_init(spi_transmit_fun transmit) int bt_apollo_controller_deinit(void) { - int ret = -ENOTSUP; + int ret = 0; -#if (CONFIG_SOC_SERIES_APOLLO3X) +#if (CONFIG_SOC_SERIES_APOLLO4X) + /* Keep the Controller in resetting state */ + gpio_pin_set_dt(&rst_gpio, 1); + + /* Disable XO32MHz */ + clock_control_off(clk32m_dev, (clock_control_subsys_t)CLOCK_CONTROL_AMBIQ_TYPE_HFXTAL_BLE); + /* Disable XO32kHz */ + clock_control_off(clk32k_dev, (clock_control_subsys_t)CLOCK_CONTROL_AMBIQ_TYPE_LFXTAL); + + /* Disable GPIOs */ + gpio_pin_configure_dt(&irq_gpio, GPIO_DISCONNECTED); + gpio_pin_configure_dt(&clkreq_gpio, GPIO_DISCONNECTED); + gpio_remove_callback(clkreq_gpio.port, &clkreq_gpio_cb); + gpio_remove_callback(irq_gpio.port, &irq_gpio_cb); +#elif (CONFIG_SOC_SERIES_APOLLO3X) irq_disable(DT_IRQN(SPI_DEV_NODE)); ret = am_apollo3_bt_controller_deinit(); @@ -355,7 +369,9 @@ int bt_apollo_controller_deinit(void) ret = -EPERM; LOG_ERR("BT controller deinitialization fails"); } -#endif /* CONFIG_SOC_SERIES_APOLLO3X */ +#else + ret = -ENOTSUP; +#endif /* CONFIG_SOC_SERIES_APOLLO4X */ return ret; } diff --git a/drivers/bluetooth/hci/h4.c b/drivers/bluetooth/hci/h4.c index d3c2ea3511ca5..cfea346a946c6 100644 --- a/drivers/bluetooth/hci/h4.c +++ b/drivers/bluetooth/hci/h4.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -70,6 +71,10 @@ struct h4_config { k_thread_stack_t *rx_thread_stack; size_t rx_thread_stack_size; struct k_thread *rx_thread; +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) + struct gpio_dt_spec reset; + uint16_t reset_ms; +#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */ }; static inline void h4_get_type(const struct device *dev) @@ -523,6 +528,14 @@ static int h4_open(const struct device *dev, bt_hci_recv_t recv) uart_irq_callback_user_data_set(cfg->uart, bt_uart_isr, (void *)dev); +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) + if (cfg->reset.port) { + (void)gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_ACTIVE); + k_sleep(K_MSEC(cfg->reset_ms)); + gpio_pin_set_dt(&cfg->reset, 0); + } +#endif + tid = k_thread_create(cfg->rx_thread, cfg->rx_thread_stack, cfg->rx_thread_stack_size, rx_thread, (void *)dev, NULL, NULL, @@ -601,6 +614,10 @@ static DEVICE_API(bt_hci, h4_driver_api) = { .rx_thread_stack = rx_thread_stack_##inst, \ .rx_thread_stack_size = K_KERNEL_STACK_SIZEOF(rx_thread_stack_##inst), \ .rx_thread = &rx_thread_##inst, \ + COND_CODE_1(DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios), \ + (.reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}), \ + .reset_ms = DT_INST_PROP_OR(0, reset_assert_duration_ms, 0), \ + ), ()) \ }; \ static struct h4_data h4_data_##inst = { \ .rx = { \ diff --git a/drivers/bluetooth/hci/hci_ambiq.c b/drivers/bluetooth/hci/hci_ambiq.c index 3757806b1e53b..b870a50da21ce 100644 --- a/drivers/bluetooth/hci/hci_ambiq.c +++ b/drivers/bluetooth/hci/hci_ambiq.c @@ -395,6 +395,9 @@ static int bt_apollo_close(const struct device *dev) return ret; } + /* Stop RX thread */ + k_thread_abort(&spi_rx_thread_data); + hci->recv = NULL; return ret; diff --git a/drivers/bluetooth/hci/hci_esp32.c b/drivers/bluetooth/hci/hci_esp32.c index c546e33fdb35d..efb4ca0c9b66d 100644 --- a/drivers/bluetooth/hci/hci_esp32.c +++ b/drivers/bluetooth/hci/hci_esp32.c @@ -25,23 +25,27 @@ struct bt_esp32_data { bt_hci_recv_t recv; }; -static K_SEM_DEFINE(hci_send_sem, 1, 1); +/* VHCI notifies when exactly one more HCI packet can be sent */ +static K_SEM_DEFINE(hci_send_sem, 0, 1); -static bool is_hci_event_discardable(const uint8_t *evt_data) +static bool is_hci_event_discardable(uint8_t evt_code, const uint8_t *payload, size_t plen) { - uint8_t evt_type = evt_data[0]; - - switch (evt_type) { + switch (evt_code) { #if defined(CONFIG_BT_CLASSIC) case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI: case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT: return true; #endif case BT_HCI_EVT_LE_META_EVENT: { - uint8_t subevt_type = evt_data[sizeof(struct bt_hci_evt_hdr)]; + /* Need at least 1 byte to read LE subevent safely */ + if (plen < 1U) { + return false; + } + uint8_t subevt_type = payload[0]; switch (subevt_type) { case BT_HCI_EVT_LE_ADVERTISING_REPORT: + case BT_HCI_EVT_LE_EXT_ADVERTISING_REPORT: return true; default: return false; @@ -64,8 +68,6 @@ static struct net_buf *bt_esp_evt_recv(uint8_t *data, size_t remaining) return NULL; } - discardable = is_hci_event_discardable(data); - memcpy((void *)&hdr, data, sizeof(hdr)); data += sizeof(hdr); remaining -= sizeof(hdr); @@ -76,6 +78,8 @@ static struct net_buf *bt_esp_evt_recv(uint8_t *data, size_t remaining) } LOG_DBG("len %u", hdr.len); + discardable = is_hci_event_discardable(hdr.evt, data, remaining); + buf = bt_buf_get_evt(hdr.evt, discardable, K_NO_WAIT); if (!buf) { if (discardable) { @@ -242,22 +246,21 @@ static int bt_esp32_send(const struct device *dev, struct net_buf *buf) LOG_HEXDUMP_DBG(buf->data, buf->len, "Final HCI buffer:"); - if (!esp_vhci_host_check_send_available()) { - LOG_WRN("Controller not ready to receive packets"); - } - - if (k_sem_take(&hci_send_sem, HCI_BT_ESP32_TIMEOUT) == 0) { - esp_vhci_host_send_packet(buf->data, buf->len); - } else { + /* Wait for controller credit (callback gives the semaphore) */ + if (k_sem_take(&hci_send_sem, HCI_BT_ESP32_TIMEOUT) != 0) { LOG_ERR("Send packet timeout error"); err = -ETIMEDOUT; + } else { + if (!esp_vhci_host_check_send_available()) { + LOG_WRN("VHCI not available, sending anyway"); + } + esp_vhci_host_send_packet(buf->data, buf->len); } if (!err) { net_buf_unref(buf); } - k_sem_give(&hci_send_sem); return err; } @@ -291,6 +294,10 @@ static int bt_esp32_ble_init(void) esp_vhci_host_register_callback(&vhci_host_cb); + if (esp_vhci_host_check_send_available()) { + k_sem_give(&hci_send_sem); + } + return 0; } @@ -318,6 +325,8 @@ static int bt_esp32_open(const struct device *dev, bt_hci_recv_t recv) struct bt_esp32_data *hci = dev->data; int err; + k_sem_reset(&hci_send_sem); + err = bt_esp32_ble_init(); if (err) { return err; diff --git a/drivers/bluetooth/hci/hci_stm32wba.c b/drivers/bluetooth/hci/hci_stm32wba.c index 646bdedd8836b..4c18f878b601e 100644 --- a/drivers/bluetooth/hci/hci_stm32wba.c +++ b/drivers/bluetooth/hci/hci_stm32wba.c @@ -13,6 +13,12 @@ #include #include #include +#include +#include +#include +#ifdef CONFIG_PM_DEVICE +#include "linklayer_plat.h" +#endif /* CONFIG_PM_DEVICE */ #include #include @@ -64,13 +70,87 @@ struct aci_set_ble_addr { uint8_t length; uint8_t value[6]; } __packed; -#endif +#endif /* CONFIG_BT_HCI_SETUP */ + +#ifdef CONFIG_PM_DEVICE +/* Proprietary command to enable notification of radio events */ +#define ACI_HAL_WRITE_SET_RADIO_ACTIVITY_MASK BT_OP(BT_OGF_VS, 0xFC18) +#define RADIO_ACTIVITY_MASK_ALL (0x7FFF) +#define ACI_HAL_END_OF_RADIO_ACTIVITY_EVENT (0x0004) + +struct aci_set_radio_activity_mask_params { + uint16_t Radio_Activity_Mask; +} __packed; + +struct bt_hci_end_radio_activity_evt { + uint8_t evt_code; + uint8_t len; + uint16_t vs_code; + uint8_t last_state; + uint8_t next_state; + uint32_t next_state_sys_time; + uint8_t last_state_slot; + uint8_t next_state_slot; +} __packed; +#endif /* CONFIG_PM_DEVICE */ static uint32_t __noinit buffer[DIVC(BLE_DYN_ALLOC_SIZE, 4)]; static uint32_t __noinit gatt_buffer[DIVC(BLE_GATT_BUF_SIZE, 4)]; extern uint8_t ll_state_busy; +#ifdef CONFIG_PM_DEVICE +static int bt_hci_stm32wba_set_radio_activity_mask(void) +{ + struct net_buf *buf; + struct aci_set_radio_activity_mask_params *params; + int err; + + buf = bt_hci_cmd_alloc(K_FOREVER); + if (!buf) { + return -ENOBUFS; + } + + params = net_buf_add(buf, sizeof(*params)); + params->Radio_Activity_Mask = RADIO_ACTIVITY_MASK_ALL; + + err = bt_hci_cmd_send_sync(ACI_HAL_WRITE_SET_RADIO_ACTIVITY_MASK, buf, NULL); + + return err; +} + +void register_radio_event(void) +{ + int64_t value_ticks; + static struct pm_policy_event radio_evt; + static bool first_event = true; + uint32_t cmd_status; + /* Flag indicating that no radio events have been scheduled */ + uint32_t next_radio_event_us = 0; + + /* Getting next radio event time if any */ + cmd_status = ll_intf_le_get_remaining_time_for_next_event(&next_radio_event_us); + UNUSED(cmd_status); + __ASSERT(cmd_staus, "Unable to retrieve next radio event"); + + if (next_radio_event_us == LL_DP_SLP_NO_WAKEUP) { + /* No next radio event scheduled */ + if (!first_event) { + first_event = true; + pm_policy_event_unregister(&radio_evt); + } + } else { + value_ticks = k_us_to_ticks_floor64(next_radio_event_us) + k_uptime_ticks(); + if (first_event) { + pm_policy_event_register(&radio_evt, value_ticks); + first_event = false; + } else { + pm_policy_event_update(&radio_evt, value_ticks); + } + } +} +#endif /* CONFIG_PM_DEVICE */ + static bool is_hci_event_discardable(const uint8_t *evt_data) { uint8_t evt_type = evt_data[0]; @@ -80,7 +160,7 @@ static bool is_hci_event_discardable(const uint8_t *evt_data) case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI: case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT: return true; -#endif +#endif /* CONFIG_BT_CLASSIC */ case BT_HCI_EVT_LE_META_EVENT: { uint8_t subevt_type = evt_data[sizeof(struct bt_hci_evt_hdr)]; @@ -247,6 +327,17 @@ static int receive_data(const struct device *dev, const uint8_t *data, size_t le switch (pkt_indicator) { case BT_HCI_H4_EVT: +#ifdef CONFIG_PM_DEVICE + /* Filtering on next radio events */ + const struct bt_hci_end_radio_activity_evt *evt_pckt = + (const struct bt_hci_end_radio_activity_evt *)(data); + + if ((evt_pckt->evt_code == BT_HCI_EVT_VENDOR) && + (evt_pckt->vs_code == ACI_HAL_END_OF_RADIO_ACTIVITY_EVENT)) { + register_radio_event(); + return err; + } +#endif /* CONFIG_PM_DEVICE */ buf = treat_evt(data, len); break; case BT_HCI_H4_ACL: @@ -450,23 +541,79 @@ static int bt_hci_stm32wba_setup(const struct device *dev, return err; } - return 0; +#ifdef CONFIG_PM_DEVICE + err = bt_hci_stm32wba_set_radio_activity_mask(); + if (err) { + return err; + } +#endif /* CONFIG_PM_DEVICE */ + + return err; } #endif /* CONFIG_BT_HCI_SETUP */ +#ifdef CONFIG_PM_DEVICE +static int radio_pm_action(const struct device *dev, enum pm_device_action action) +{ + switch (action) { + case PM_DEVICE_ACTION_RESUME: + LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_RADIO); +#if defined(CONFIG_PM_S2RAM) + if (LL_PWR_IsActiveFlag_SB() == 1U) { + /* Put the radio in active state */ + link_layer_register_isr(); + } +#endif /* CONFIG_PM_S2RAM */ + LINKLAYER_PLAT_NotifyWFIExit(); + ll_sys_dp_slp_exit(); + break; + case PM_DEVICE_ACTION_SUSPEND: +#if defined(CONFIG_PM_S2RAM) + uint32_t radio_remaining_time = 0; + enum pm_state state = pm_state_next_get(_current_cpu->id)->state; + + if (state == PM_STATE_SUSPEND_TO_RAM) { + /* Checking next radio schedulet event */ + uint32_t cmd_status = + ll_intf_le_get_remaining_time_for_next_event(&radio_remaining_time); + UNUSED(cmd_status); + __ASSERT(cmd_status, "Unable to retrieve next radio event"); + + if (radio_remaining_time == LL_DP_SLP_NO_WAKEUP) { + /* No radio event scheduled */ + (void)ll_sys_dp_slp_enter(LL_DP_SLP_NO_WAKEUP); + } else if (radio_remaining_time > CFG_LPM_STDBY_WAKEUP_TIME) { + /* No event in a "near" future */ + (void)ll_sys_dp_slp_enter(radio_remaining_time - + CFG_LPM_STDBY_WAKEUP_TIME); + } else { + register_radio_event(); + } + } +#endif /* CONFIG_PM_S2RAM */ + LINKLAYER_PLAT_NotifyWFIEnter(); + break; + default: + return -ENOTSUP; + } + + return 0; +} +#endif /* CONFIG_PM_DEVICE */ + static DEVICE_API(bt_hci, drv) = { #if defined(CONFIG_BT_HCI_SETUP) .setup = bt_hci_stm32wba_setup, -#endif +#endif /* CONFIG_BT_HCI_SETUP */ .open = bt_hci_stm32wba_open, .send = bt_hci_stm32wba_send, }; #define HCI_DEVICE_INIT(inst) \ - static struct hci_data hci_data_##inst = { \ - }; \ - DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &hci_data_##inst, NULL, \ - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv) + static struct hci_data hci_data_##inst = {}; \ + PM_DEVICE_DT_INST_DEFINE(inst, radio_pm_action); \ + DEVICE_DT_INST_DEFINE(inst, NULL, PM_DEVICE_DT_INST_GET(inst), &hci_data_##inst, NULL, \ + POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv); /* Only one instance supported */ HCI_DEVICE_INIT(0) diff --git a/drivers/cache/cache_andes.c b/drivers/cache/cache_andes.c index 4b8cd66b87dfa..13e469a20e12d 100644 --- a/drivers/cache/cache_andes.c +++ b/drivers/cache/cache_andes.c @@ -534,9 +534,6 @@ static int andes_cache_init(void) } #elif (CONFIG_ICACHE_LINE_SIZE != 0) cache_cfg.instr_line_size = CONFIG_ICACHE_LINE_SIZE; -#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size) - cache_cfg.instr_line_size = - DT_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size); #else LOG_ERR("Please specific the i-cache-line-size " "CPU0 property of the DT"); @@ -558,9 +555,6 @@ static int andes_cache_init(void) } #elif (CONFIG_DCACHE_LINE_SIZE != 0) cache_cfg.data_line_size = CONFIG_DCACHE_LINE_SIZE; -#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size) - cache_cfg.data_line_size = - DT_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size); #else LOG_ERR("Please specific the d-cache-line-size " "CPU0 property of the DT"); diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index 48a72c9967e77..beb7b794c9743 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -49,6 +49,18 @@ #include #include #include +#elif defined(CONFIG_SOC_SERIES_ESP32H2) +#define DT_CPU_COMPAT espressif_riscv +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #endif #include @@ -85,10 +97,13 @@ static bool reset_reason_is_cpu_reset(void) return false; } -#if defined(CONFIG_SOC_SERIES_ESP32C6) +#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) static void esp32_clock_perip_init(void) { soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + +#if defined(CONFIG_SOC_SERIES_ESP32C6) modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)((rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW @@ -101,19 +116,36 @@ static void esp32_clock_perip_init(void) : MODEM_CLOCK_LPCLK_SRC_RC_SLOW); modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); - - soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); +#elif defined(CONFIG_SOC_SERIES_ESP32H2) + esp_sleep_pd_domain_t pu_domain = + (esp_sleep_pd_domain_t)((rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) + ? ESP_PD_DOMAIN_XTAL32K + : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) + ? ESP_PD_DOMAIN_RC32K + : ESP_PD_DOMAIN_MAX); + esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON); +#endif if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT)) { +#if CONFIG_ESP_CONSOLE_UART_NUM != 0 + periph_ll_disable_clk_set_rst(PERIPH_UART0_MODULE); +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 periph_ll_disable_clk_set_rst(PERIPH_UART1_MODULE); +#endif periph_ll_disable_clk_set_rst(PERIPH_I2C0_MODULE); +#if defined(CONFIG_SOC_SERIES_ESP32H2) + periph_ll_disable_clk_set_rst(PERIPH_I2C1_MODULE); +#endif periph_ll_disable_clk_set_rst(PERIPH_RMT_MODULE); periph_ll_disable_clk_set_rst(PERIPH_LEDC_MODULE); periph_ll_disable_clk_set_rst(PERIPH_TIMG1_MODULE); periph_ll_disable_clk_set_rst(PERIPH_TWAI0_MODULE); +#if defined(CONFIG_SOC_SERIES_ESP32C6) periph_ll_disable_clk_set_rst(PERIPH_TWAI1_MODULE); +#endif periph_ll_disable_clk_set_rst(PERIPH_I2S1_MODULE); periph_ll_disable_clk_set_rst(PERIPH_PCNT_MODULE); periph_ll_disable_clk_set_rst(PERIPH_ETM_MODULE); @@ -124,17 +156,24 @@ static void esp32_clock_perip_init(void) periph_ll_disable_clk_set_rst(PERIPH_TEMPSENSOR_MODULE); periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE); periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE); +#if defined(CONFIG_SOC_SERIES_ESP32C6) periph_ll_disable_clk_set_rst(PERIPH_SDIO_SLAVE_MODULE); +#endif periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE); periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE); periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE); periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE); periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE); periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE); +#if defined(CONFIG_SOC_SERIES_ESP32H2) + periph_ll_disable_clk_set_rst(PERIPH_ECDSA_MODULE); +#endif REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE); REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN); +#if defined(CONFIG_SOC_SERIES_ESP32C6) REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN); +#endif REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN); REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); @@ -150,8 +189,9 @@ static void esp32_clock_perip_init(void) (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) { +#if defined(CONFIG_SOC_SERIES_ESP32C6) periph_ll_disable_clk_set_rst(PERIPH_LP_I2C0_MODULE); - +#endif CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN); CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_UART_CK_EN); CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN); @@ -544,7 +584,7 @@ static int clock_control_esp32_get_rate(const struct device *dev, clock_control_ static int esp32_select_rtc_slow_clk(uint8_t slow_clk) { -#if !defined(CONFIG_SOC_SERIES_ESP32C6) +#if !defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2) soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; #else soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk; @@ -600,7 +640,7 @@ static int esp32_select_rtc_slow_clk(uint8_t slow_clk) return -ENODEV; } } -#if defined(CONFIG_SOC_SERIES_ESP32C6) +#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { rtc_clk_rc32k_enable(true); } @@ -642,11 +682,21 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf #if defined(CONFIG_SOC_SERIES_ESP32C6) rtc_clk_modem_clock_domain_active_state_icg_map_preinit(); - REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, rtc_clk_cfg.clk_8m_dfreq); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap); - REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, rtc_clk_cfg.rc32k_dfreq); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1); +#elif defined(CONFIG_SOC_SERIES_ESP32H2) + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap); + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0); + REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0); +#else + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq); +#endif + +#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) + REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, rtc_clk_cfg.clk_8m_dfreq); + REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, rtc_clk_cfg.rc32k_dfreq); uint32_t hp_cali_dbias = get_act_hp_dbias(); uint32_t lp_cali_dbias = get_act_lp_dbias(); @@ -657,15 +707,11 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S); SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S); - -#else - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap); - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq); #endif #if defined(CONFIG_SOC_SERIES_ESP32) REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1); -#elif defined(CONFIG_SOC_SERIES_ESP32C6) +#elif defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) clk_ll_rc_fast_tick_conf(); esp_rom_uart_tx_wait_idle(0); @@ -678,7 +724,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf rtc_clk_8m_divider_set(rtc_clk_cfg.clk_8m_clk_div); #endif -#if !defined(CONFIG_SOC_SERIES_ESP32C6) +#if !defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2) /* Reset (disable) i2c internal bus for all regi2c registers */ regi2c_ctrl_ll_i2c_reset(); /* Enable the internal bus used to configure BBPLL */ @@ -699,7 +745,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf * to make it run at 80MHz after the switch. PLL = 480MHz, so divider is 6. */ clk_ll_mspi_fast_set_hs_divider(6); -#else +#elif !defined(CONFIG_SOC_SERIES_ESP32H2) rtc_clk_apb_freq_update(rtc_clk_cfg.xtal_freq * MHZ(1)); #endif @@ -719,7 +765,8 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf old_config.freq_mhz); #if defined(CONFIG_ESP_CONSOLE_UART) -#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6) +#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6) && \ + !defined(CONFIG_SOC_SERIES_ESP32H2) #if defined(CONFIG_MCUBOOT) && defined(ESP_ROM_UART_CLK_IS_XTAL) uint32_t uart_clock_src_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1); #else @@ -775,7 +822,9 @@ static int clock_control_esp32_init(const struct device *dev) if (rst_reas == RESET_REASON_CHIP_POWER_ON) { esp_ocode_calib_init(); } -#else /* CONFIG_SOC_SERIES_ESP32C6 */ +#elif defined(CONFIG_SOC_SERIES_ESP32H2) + pmu_init(); +#else /* CONFIG_SOC_SERIES_ESP32C6 || CONFIG_SOC_SERIES_ESP32H2 */ rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT(); #if !defined(CONFIG_SOC_SERIES_ESP32) @@ -788,7 +837,7 @@ static int clock_control_esp32_init(const struct device *dev) } #endif /* !CONFIG_SOC_SERIES_ESP32 */ rtc_init(rtc_cfg); -#endif /* CONFIG_SOC_SERIES_ESP32C6 */ +#endif /* CONFIG_SOC_SERIES_ESP32C6 || CONFIG_SOC_SERIES_ESP32H2 */ ret = esp32_cpu_clock_configure(&cfg->cpu); if (ret) { diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c index 1c2d0363feddf..be7085db8b7bc 100644 --- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c +++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c @@ -299,6 +299,12 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, break; #endif +#ifdef CONFIG_INPUT_MCUX_KPP + case IMX_CCM_KPP_CLK: + clock_root = kCLOCK_CpuClk; + break; +#endif + default: return -EINVAL; } diff --git a/drivers/clock_control/clock_control_mspm0.c b/drivers/clock_control/clock_control_mspm0.c index 8fa07b6761007..a03d10b6d9349 100644 --- a/drivers/clock_control/clock_control_mspm0.c +++ b/drivers/clock_control/clock_control_mspm0.c @@ -177,7 +177,7 @@ static int clock_mspm0_init(const struct device *dev) uint32_t hfxt_freq = DT_PROP(DT_NODELABEL(hfxt), clock_frequency) / MHZ(1); uint32_t xtal_startup_delay = DT_PROP_OR(DT_NODELABEL(hfxt), - ti_xtal_startup_delay_us, 0); + ti_xtal_startup_delay_us, 0); if (hfxt_freq >= 4 && hfxt_freq <= 8) { @@ -197,8 +197,8 @@ static int clock_mspm0_init(const struct device *dev) /* startup time in 64us resolution */ DL_SYSCTL_setHFCLKSourceHFXTParams(hf_range, - mspm0_hfclk_cfg.xtal_startup_delay / 64, - true); + xtal_startup_delay / 64, + true); #else DL_SYSCTL_setHFCLKSourceHFCLKIN(); #endif diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index ce417e7ab2635..67cab58816b39 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -612,7 +612,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, #endif /* STM32_TIMER_PRESCALER && (RCC_DCKCFGR_TIMPRE || RCC_DCKCFGR1_TIMPRE) */ break; #endif /* STM32_SRC_TIMPCLK2 */ -#if defined(STM32_SRC_TIMPLLCLK) +#if defined(STM32_SRC_TIMPLLCLK) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) case STM32_SRC_TIMPLLCLK: *rate = get_pllout_frequency() * 2; if (*rate == 0) { diff --git a/drivers/clock_control/clock_stm32_ll_mp2.c b/drivers/clock_control/clock_stm32_ll_mp2.c index 3917e0db62bd3..ca39af9cff26a 100644 --- a/drivers/clock_control/clock_stm32_ll_mp2.c +++ b/drivers/clock_control/clock_stm32_ll_mp2.c @@ -105,6 +105,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev, case STM32_CLOCK_PERIPH_SPI7: *rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI67_CLKSOURCE); break; + case STM32_CLOCK_PERIPH_WWDG1: + /* The WWDG1 clock is derived from the APB3 clock */ + *rate = SystemCoreClock >> (LL_RCC_Get_LSMCUDIVR() + LL_RCC_GetAPB3Prescaler()); + break; default: return -ENOTSUP; } diff --git a/drivers/comparator/comparator_renesas_ra.c b/drivers/comparator/comparator_renesas_ra.c index c040b645fb546..1ff911eed0b33 100644 --- a/drivers/comparator/comparator_renesas_ra.c +++ b/drivers/comparator/comparator_renesas_ra.c @@ -172,7 +172,7 @@ static int acmphs_renesas_ra_init(const struct device *dev) } /* - * Once the analog comparator is configurate, the program must wait + * Once the analog comparator is configured, the program must wait * for the ACMPHS stabilization time (300ns enabling + 200ns input switching) * before using the comparator. */ diff --git a/drivers/counter/CMakeLists.txt b/drivers/counter/CMakeLists.txt index 0a1c9f8d294dc..dcc13aa58e035 100644 --- a/drivers/counter/CMakeLists.txt +++ b/drivers/counter/CMakeLists.txt @@ -34,6 +34,7 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_TPM counter_mcux_tpm zephyr_library_sources_ifdef(CONFIG_COUNTER_XEC counter_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_LPTMR counter_mcux_lptmr.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_LPIT counter_mcux_lpit.c) +zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_FTM counter_mcux_ftm.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_MAXIM_DS3231 maxim_ds3231.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_NATIVE_SIM counter_native_sim.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE counter_handlers.c) diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 96f03960336c4..b8a8962f0fb83 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -72,6 +72,8 @@ source "drivers/counter/Kconfig.mcux_lptmr" source "drivers/counter/Kconfig.mcux_lpit" +source "drivers/counter/Kconfig.mcux_ftm" + source "drivers/counter/Kconfig.maxim_ds3231" source "drivers/counter/Kconfig.native_sim" diff --git a/drivers/counter/Kconfig.esp32_rtc b/drivers/counter/Kconfig.esp32_rtc index 7670dd0ebaed7..acb48afa00394 100644 --- a/drivers/counter/Kconfig.esp32_rtc +++ b/drivers/counter/Kconfig.esp32_rtc @@ -1,6 +1,6 @@ # ESP32 RTC Timer configuration -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 config COUNTER_RTC_ESP32 diff --git a/drivers/counter/Kconfig.esp32_tmr b/drivers/counter/Kconfig.esp32_tmr index 93f6e2503e2c3..099c1d8206409 100644 --- a/drivers/counter/Kconfig.esp32_tmr +++ b/drivers/counter/Kconfig.esp32_tmr @@ -1,20 +1,12 @@ # ESP32 General Purpose Timer configuration -# Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2020-2025 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 config COUNTER_TMR_ESP32 bool "ESP32 Counter Driver based on GP-Timers" default y - depends on DT_HAS_ESPRESSIF_ESP32_TIMER_ENABLED - help - Enables the Counter driver API based on Espressif's General - Purpose Timers for ESP32 series devices. - -config COUNTER_TMR_RTC_ESP32 - bool "ESP32 Counter Driver based on GP-Timers" - default y - depends on DT_HAS_ESPRESSIF_ESP32_RTC_TIMER_ENABLED + depends on DT_HAS_ESPRESSIF_ESP32_COUNTER_ENABLED help Enables the Counter driver API based on Espressif's General Purpose Timers for ESP32 series devices. diff --git a/drivers/counter/Kconfig.mcux_ftm b/drivers/counter/Kconfig.mcux_ftm new file mode 100644 index 0000000000000..c9480a1eeb67a --- /dev/null +++ b/drivers/counter/Kconfig.mcux_ftm @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# MCUXpresso SDK FlexTimer (FTM) + +config COUNTER_MCUX_FTM + bool "MCUX FTM driver" + default y + depends on DT_HAS_NXP_FTM_ENABLED + help + Enable support for the MCUX FlexTimer (FTM). diff --git a/drivers/counter/counter_ll_stm32_rtc.c b/drivers/counter/counter_ll_stm32_rtc.c index f346de122c828..7434b02377838 100644 --- a/drivers/counter/counter_ll_stm32_rtc.c +++ b/drivers/counter/counter_ll_stm32_rtc.c @@ -590,6 +590,18 @@ static int rtc_stm32_init(const struct device *dev) z_stm32_hsem_unlock(CFG_HW_RCC_SEMID); #if !defined(CONFIG_COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS) + +/* STM32C0 LL driver does not clear the CR register in LL_RTC_DeInit so it will loop forever waiting + * for a flag that will never be set when shadow registers are bypassed (BYPSHAD enabled). + */ +#if defined(RTC_CR_BYPSHAD) && defined(CONFIG_SOC_SERIES_STM32C0X) + if (LL_RTC_IsShadowRegBypassEnabled(RTC)) { + LL_RTC_DisableWriteProtection(RTC); + LL_RTC_DisableShadowRegBypass(RTC); + LL_RTC_EnableWriteProtection(RTC); + } +#endif /* defined(RTC_CR_BYPSHAD) && defined(CONFIG_SOC_SERIES_STM32C0X) */ + if (LL_RTC_DeInit(RTC) != SUCCESS) { goto out_disable_bkup_access; } diff --git a/drivers/counter/counter_mcux_ftm.c b/drivers/counter/counter_mcux_ftm.c new file mode 100644 index 0000000000000..c82b382731349 --- /dev/null +++ b/drivers/counter/counter_mcux_ftm.c @@ -0,0 +1,198 @@ +/* + * Copyright 2023-2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_ftm + +#include +#include +#include +#include + +#include + +LOG_MODULE_REGISTER(mcux_ftm, CONFIG_COUNTER_LOG_LEVEL); + +struct mcux_ftm_config { + struct counter_config_info info; + FTM_Type *base; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + ftm_clock_source_t ftm_clock_source; + ftm_clock_prescale_t prescale; + void (*irq_config_func)(const struct device *dev); +}; + +struct mcux_ftm_data { + uint32_t freq; + counter_top_callback_t top_callback; + void *top_user_data; +}; + +static int mcux_ftm_start(const struct device *dev) +{ + const struct mcux_ftm_config *config = dev->config; + + FTM_StartTimer(config->base, config->ftm_clock_source); + + return 0; +} + +static int mcux_ftm_stop(const struct device *dev) +{ + const struct mcux_ftm_config *config = dev->config; + + FTM_StopTimer(config->base); + + return 0; +} + +static int mcux_ftm_get_value(const struct device *dev, uint32_t *ticks) +{ + const struct mcux_ftm_config *config = dev->config; + + *ticks = FTM_GetCurrentTimerCount(config->base); + + return 0; +} + +static uint32_t mcux_ftm_get_top_value(const struct device *dev) +{ + const struct mcux_ftm_config *config = dev->config; + + return config->base->MOD; +} + +void mcux_ftm_isr(const struct device *dev) +{ + const struct mcux_ftm_config *config = dev->config; + struct mcux_ftm_data *data = dev->data; + uint32_t status = FTM_GetStatusFlags(config->base); + + FTM_ClearStatusFlags(config->base, status); + + if (((status & kFTM_TimeOverflowFlag) != 0) && (data->top_callback != NULL)) { + data->top_callback(dev, data->top_user_data); + } +} + +static uint32_t mcux_ftm_get_pending_int(const struct device *dev) +{ + const struct mcux_ftm_config *config = dev->config; + + return FTM_GetStatusFlags(config->base); +} + +static int mcux_ftm_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) +{ + const struct mcux_ftm_config *config = dev->config; + struct mcux_ftm_data *data = dev->data; + + if (cfg->ticks > config->info.max_top_value) { + return -ENOTSUP; + } + + /* Check if timer already enabled. */ + if ((config->base->SC & FTM_SC_CLKS_MASK) != 0) { + /* Timer already enabled, check flags before resetting */ + if ((cfg->flags & COUNTER_TOP_CFG_DONT_RESET) != 0) { + return -ENOTSUP; + } + + FTM_StopTimer(config->base); + config->base->CNT = 0; + FTM_SetTimerPeriod(config->base, cfg->ticks); + FTM_StartTimer(config->base, config->ftm_clock_source); + } else { + config->base->CNT = 0; + FTM_SetTimerPeriod(config->base, cfg->ticks); + } + + data->top_callback = cfg->callback; + data->top_user_data = cfg->user_data; + + FTM_EnableInterrupts(config->base, kFTM_TimeOverflowInterruptEnable); + + return 0; +} + +static uint32_t mcux_ftm_get_freq(const struct device *dev) +{ + struct mcux_ftm_data *data = dev->data; + + return data->freq; +} + +static int mcux_ftm_init(const struct device *dev) +{ + const struct mcux_ftm_config *config = dev->config; + struct mcux_ftm_data *data = dev->data; + ftm_config_t ftmConfig; + uint32_t clk_freq; + + if (!device_is_ready(config->clock_dev)) { + LOG_ERR("clock control device not ready"); + return -ENODEV; + } + + if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq)) { + LOG_ERR("Could not get clock frequency"); + return -EINVAL; + } + + data->freq = clk_freq / (1U << config->prescale); + + FTM_GetDefaultConfig(&ftmConfig); + ftmConfig.prescale = config->prescale; + FTM_Init(config->base, &ftmConfig); + + config->irq_config_func(dev); + + FTM_SetTimerPeriod(config->base, config->info.max_top_value); + + return 0; +} + +static DEVICE_API(counter, mcux_ftm_driver_api) = { + .start = mcux_ftm_start, + .stop = mcux_ftm_stop, + .get_value = mcux_ftm_get_value, + .set_top_value = mcux_ftm_set_top_value, + .get_pending_int = mcux_ftm_get_pending_int, + .get_top_value = mcux_ftm_get_top_value, + .get_freq = mcux_ftm_get_freq, +}; + +#define TO_FTM_PRESCALE_DIVIDE(val) _DO_CONCAT(kFTM_Prescale_Divide_, val) + +#define COUNTER_MCUX_FTM_DEVICE_INIT(n) \ + static struct mcux_ftm_data mcux_ftm_data_##n; \ + static void mcux_ftm_irq_config_##n(const struct device *dev); \ + \ + static const struct mcux_ftm_config mcux_ftm_config_##n = { \ + .info = \ + { \ + .max_top_value = 0xFFFFU, \ + .flags = COUNTER_CONFIG_INFO_COUNT_UP, \ + }, \ + .base = (FTM_Type *)DT_INST_REG_ADDR(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \ + .ftm_clock_source = (ftm_clock_source_t)(DT_INST_ENUM_IDX(n, clock_source) + 1U), \ + .prescale = TO_FTM_PRESCALE_DIVIDE(DT_INST_PROP(n, prescaler)), \ + .irq_config_func = mcux_ftm_irq_config_##n, \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, mcux_ftm_init, NULL, &mcux_ftm_data_##n, &mcux_ftm_config_##n, \ + POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, &mcux_ftm_driver_api); \ + \ + static void mcux_ftm_irq_config_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mcux_ftm_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(COUNTER_MCUX_FTM_DEVICE_INIT) diff --git a/drivers/counter/counter_mspm0_timer.c b/drivers/counter/counter_mspm0_timer.c index 4cda3df727e97..5a58db4f63cc8 100644 --- a/drivers/counter/counter_mspm0_timer.c +++ b/drivers/counter/counter_mspm0_timer.c @@ -114,6 +114,8 @@ static int counter_mspm0_set_alarm(const struct device *dev, uint32_t top = counter_mspm0_get_top_value(dev); uint32_t ticks = alarm_cfg->ticks; + ARG_UNUSED(chan_id); + if (alarm_cfg->ticks > top) { return -EINVAL; } @@ -146,9 +148,13 @@ static int counter_mspm0_set_alarm(const struct device *dev, static int counter_mspm0_cancel_alarm(const struct device *dev, uint8_t chan_id) { const struct counter_mspm0_config *config = dev->config; + struct counter_mspm0_data *data = dev->data; + + ARG_UNUSED(chan_id); DL_Timer_disableInterrupt(config->base, DL_TIMER_INTERRUPT_CC0_UP_EVENT); + data->alarm_cb = NULL; return 0; } diff --git a/drivers/crc/CMakeLists.txt b/drivers/crc/CMakeLists.txt new file mode 100644 index 0000000000000..86a26f6bcfa2b --- /dev/null +++ b/drivers/crc/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/crc.h) + +zephyr_library() + +zephyr_library_sources_ifdef(CONFIG_CRC_DRIVER_RENESAS_RA crc_renesas_ra.c) diff --git a/drivers/crc/Kconfig b/drivers/crc/Kconfig new file mode 100644 index 0000000000000..c57d376ca26e9 --- /dev/null +++ b/drivers/crc/Kconfig @@ -0,0 +1,100 @@ +# Copyright (c) 2024 Brill Power Ltd. +# SPDX-License-Identifier: Apache-2.0 + +menuconfig CRC_DRIVER + bool "CRC device drivers" + help + Enable support for CRC device driver. + +if CRC_DRIVER + +module = CRC_DRIVER +module-str = CRC_DRIVER + +source "subsys/logging/Kconfig.template.log_config" + +config CRC_DRIVER_INIT_PRIORITY + int "CRC init priority" + default KERNEL_INIT_PRIORITY_DEVICE + help + CRC driver device initialization priority. + +source "drivers/crc/Kconfig.renesas_ra" + +config CRC_DRIVER_HAS_CRC4 + bool + help + CRC driver has CRC4 computation + +config CRC_DRIVER_HAS_CRC4_TI + bool + help + CRC driver has CRC4 TI computation + +config CRC_DRIVER_HAS_CRC7_BE + bool + help + CRC driver has CRC7 BE computation + +config CRC_DRIVER_HAS_CRC8 + bool + help + CRC driver has CRC8 computation + +config CRC_DRIVER_HAS_CRC8_CCITT + bool + help + CRC driver has CRC8 CCITT computation + +config CRC_DRIVER_HAS_CRC8_ROHC + bool + help + CRC driver has CRC8 ROHC computation + +config CRC_DRIVER_HAS_CRC16 + bool + help + CRC driver has CRC16 computation + +config CRC_DRIVER_HAS_CRC16_CCITT + bool + help + CRC driver has CRC16 CCITT computation + +config CRC_DRIVER_HAS_CRC16_ITU_T + bool + help + CRC driver has CRC16 ITU-T computation + +config CRC_DRIVER_HAS_CRC16_ANSI + bool + depends on CRC_DRIVER_HAS_CRC16_REFLECT + help + CRC driver has CRC16 Ansi computation + +config CRC_DRIVER_HAS_CRC16_REFLECT + bool + help + CRC driver has CRC16 reflect computation + +config CRC_DRIVER_HAS_CRC24_PGP + bool + help + CRC driver has CRC24 PGP computation + +config CRC_DRIVER_HAS_CRC32_C + bool + help + CRC driver has CRC32C computation + +config CRC_DRIVER_HAS_CRC32_IEEE + bool + help + CRC driver has CRC32 IEEE computation + +config CRC_DRIVER_HAS_CRC32_K_4_2 + bool + help + CRC driver has CRC32K/4.2 computation + +endif # CRC_DEVICE diff --git a/drivers/crc/Kconfig.renesas_ra b/drivers/crc/Kconfig.renesas_ra new file mode 100644 index 0000000000000..0568b6fb542b1 --- /dev/null +++ b/drivers/crc/Kconfig.renesas_ra @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config CRC_DRIVER_RENESAS_RA + bool + depends on DT_HAS_RENESAS_RA_CRC_ENABLED + default y + select CRC_DRIVER_HAS_CRC8 + select CRC_DRIVER_HAS_CRC8_ROHC + select CRC_DRIVER_HAS_CRC8_CCITT + select CRC_DRIVER_HAS_CRC16 + select CRC_DRIVER_HAS_CRC16_CCITT + select CRC_DRIVER_HAS_CRC16_ANSI + select CRC_DRIVER_HAS_CRC16_ITU_T + select CRC_DRIVER_HAS_CRC16_REFLECT + select CRC_DRIVER_HAS_CRC32_C + select CRC_DRIVER_HAS_CRC32_IEEE + select USE_RA_FSP_CRC + help + Enable the driver implementation for Renesas RA microcontrollers diff --git a/drivers/crc/crc_renesas_ra.c b/drivers/crc/crc_renesas_ra.c new file mode 100644 index 0000000000000..fb5453ab305bc --- /dev/null +++ b/drivers/crc/crc_renesas_ra.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(renesas_ra_crc, CONFIG_CRC_LOG_LEVEL); + +#include +#include + +#include +#include "r_crc.h" +#include "rp_crc.h" + +#define DT_DRV_COMPAT renesas_ra_crc +#define DEFAULT_NUM_BYTES (4U) +#define DEFAULT_SEED_VALUE (0x00000000) + +struct crc_renesas_ra_cfg { + const struct device *clock_dev; + const struct clock_control_ra_subsys_cfg clock_id; +}; + +struct crc_renesas_ra_data { + struct st_crc_instance_ctrl ctrl; + struct st_crc_input_t input_data; + struct st_crc_cfg crc_config; + struct k_sem sem; + bool flag_crc_updated; +}; + +static void crc_lock(const struct device *dev) +{ + struct crc_renesas_ra_data *data = dev->data; + + k_sem_take(&data->sem, K_FOREVER); +} + +static void crc_unlock(const struct device *dev) +{ + struct crc_renesas_ra_data *data = dev->data; + + k_sem_give(&data->sem); +} + +static int crc_set_config(const struct device *dev, struct crc_ctx *ctx) +{ + fsp_err_t err; + struct crc_renesas_ra_data *data = dev->data; + crc_cfg_t const *const crc_cfg = &data->crc_config; + + data->crc_config.bit_order = (ctx->reversed & CRC_FLAG_REVERSE_OUTPUT) + ? CRC_BIT_ORDER_LMS_LSB + : CRC_BIT_ORDER_LMS_MSB; + + switch (ctx->type) { + case CRC8: { + if ((ctx->polynomial != CRC8_POLY) && (ctx->polynomial != CRC8_REFLECT_POLY)) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_8; + break; + } + case CRC16: { + if (ctx->polynomial != CRC16_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_16; + break; + } + case CRC16_CCITT: { + if (ctx->polynomial != CRC16_CCITT_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_CCITT; + break; + } + case CRC32_C: { + if (ctx->polynomial != CRC32C_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_32C; + break; + } + case CRC32_IEEE: { + if (ctx->polynomial != CRC32_IEEE_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_32; + break; + } + default: + return -ENOTSUP; + } + + err = RP_CRC_Reconfigure(&data->ctrl, crc_cfg); + + if (err != FSP_SUCCESS) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -EINVAL; + } + + return 0; +} + +static int crc_renesas_ra_begin(const struct device *dev, struct crc_ctx *ctx) +{ + int ret; + + crc_lock(dev); + + ret = crc_set_config(dev, ctx); + if (ret != 0) { + crc_unlock(dev); + return ret; + } + + ctx->state = CRC_STATE_IN_PROGRESS; + + return 0; +} + +static int crc_renesas_ra_update(const struct device *dev, struct crc_ctx *ctx, const void *buffer, + size_t bufsize) +{ + struct crc_renesas_ra_data *data = dev->data; + fsp_err_t err; + uint32_t init_val; + + /* Ensure CRC calculation has been initialized by crc_begin() */ + if (ctx->state == CRC_STATE_IDLE) { + return -EINVAL; + } + + switch (ctx->type) { + case CRC8: + __fallthrough; + case CRC16: + __fallthrough; + case CRC16_CCITT: { + if (ctx->type == CRC8) { + init_val = (data->flag_crc_updated ? ctx->result : ctx->seed) & 0xFF; + } else { + init_val = (data->flag_crc_updated ? ctx->result : ctx->seed) & 0xFFFF; + } + + data->input_data.num_bytes = bufsize; + data->input_data.crc_seed = init_val; + data->input_data.p_input_buffer = (uint8_t *)buffer; + + err = R_CRC_Calculate(&data->ctrl, &data->input_data, &ctx->result); + if (err != FSP_SUCCESS) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -EINVAL; + } + break; + } + default: { + init_val = (data->flag_crc_updated ? ctx->result : ctx->seed) & 0xFFFFFFFF; + + if ((bufsize % 4) != 0) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -ENOTSUP; + } + + data->input_data.num_bytes = bufsize; + data->input_data.crc_seed = init_val; + data->input_data.p_input_buffer = (uint8_t *)buffer; + + err = R_CRC_Calculate(&data->ctrl, &data->input_data, &ctx->result); + if (err != FSP_SUCCESS) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -EINVAL; + } + + if (ctx->type == CRC32_IEEE) { + ctx->result = (crc_result_t)~ctx->result; + } + break; + } + } + + data->flag_crc_updated = true; + + return 0; +} + +static int crc_renesas_ra_finish(const struct device *dev, struct crc_ctx *ctx) +{ + struct crc_renesas_ra_data *data = dev->data; + + if (ctx->state == CRC_STATE_IDLE) { + return -EINVAL; + } + + ctx->state = CRC_STATE_IDLE; + + data->flag_crc_updated = false; + + crc_unlock(dev); + + return 0; +} + +static int crc_ra_init(const struct device *dev) +{ + int ret; + fsp_err_t err; + const struct crc_renesas_ra_cfg *cfg = dev->config; + struct crc_renesas_ra_data *data = dev->data; + crc_cfg_t const *const crc_cfg = &data->crc_config; + + if (!device_is_ready(cfg->clock_dev)) { + LOG_ERR("CRC: Clock control device not ready"); + return -ENODEV; + } + + ret = clock_control_on(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_id); + if (ret < 0) { + LOG_ERR("CRC: Clock control device could not initialize"); + return -EIO; + } + + err = R_CRC_Open(&data->ctrl, crc_cfg); + if (err != FSP_SUCCESS) { + return -EINVAL; + } + + k_sem_init(&data->sem, 1, 1); + + return 0; +} + +static DEVICE_API(crc, crc_renesas_ra_driver_api) = { + .begin = crc_renesas_ra_begin, + .update = crc_renesas_ra_update, + .finish = crc_renesas_ra_finish, +}; + +#define CRC_RA_INIT_CFG(idx) \ + static const struct crc_renesas_ra_cfg crc_renesas_ra_cfg_##idx = { \ + .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(idx))), \ + .clock_id = \ + { \ + .mstp = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(idx), 0, mstp), \ + .stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(idx), 0, stop_bit), \ + }, \ + }; + +#define CRC_RA_INIT(idx) \ + CRC_RA_INIT_CFG(idx); \ + \ + static struct crc_renesas_ra_data crc_renesas_ra_data_##idx = { \ + .input_data = \ + { \ + .num_bytes = DEFAULT_NUM_BYTES, \ + .crc_seed = DEFAULT_SEED_VALUE, \ + .p_input_buffer = NULL, \ + }, \ + .crc_config = \ + { \ + .bit_order = CRC_BIT_ORDER_LMS_LSB, \ + .polynomial = CRC_POLYNOMIAL_CRC_32, \ + }, \ + .flag_crc_updated = false, \ + }; \ + \ + DEVICE_DT_INST_DEFINE(idx, crc_ra_init, NULL, &crc_renesas_ra_data_##idx, \ + &crc_renesas_ra_cfg_##idx, POST_KERNEL, \ + CONFIG_CRC_DRIVER_INIT_PRIORITY, &crc_renesas_ra_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(CRC_RA_INIT) diff --git a/drivers/crypto/CMakeLists.txt b/drivers/crypto/CMakeLists.txt index f325c7f34a9aa..74c386503a312 100644 --- a/drivers/crypto/CMakeLists.txt +++ b/drivers/crypto/CMakeLists.txt @@ -2,6 +2,7 @@ zephyr_library() zephyr_library_sources_ifdef(CONFIG_CRYPTO_ATAES132A crypto_ataes132a.c) +zephyr_library_sources_ifdef(CONFIG_CRYPTO_MSPM0_AES crypto_mspm0_aes.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_MBEDTLS_SHIM crypto_mtls_shim.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_STM32 crypto_stm32.c) zephyr_library_sources_ifdef(CONFIG_CRYPTO_STM32_HASH crypto_stm32_hash.c) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 5f3c74ee77f14..65495537170a8 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -56,6 +56,7 @@ source "drivers/crypto/Kconfig.xec" source "drivers/crypto/Kconfig.it51xxx" source "drivers/crypto/Kconfig.it8xxx2" source "drivers/crypto/Kconfig.mcux_dcp" +source "drivers/crypto/Kconfig.mspm0" source "drivers/crypto/Kconfig.si32" source "drivers/crypto/Kconfig.smartbond" source "drivers/crypto/Kconfig.cc23x0" diff --git a/drivers/crypto/Kconfig.mspm0 b/drivers/crypto/Kconfig.mspm0 new file mode 100644 index 0000000000000..d645edb07a99f --- /dev/null +++ b/drivers/crypto/Kconfig.mspm0 @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Linumiz GmbH + +# SPDX-License-Identifier: Apache-2.0 + +config CRYPTO_MSPM0_AES + bool "TI MSPM0 AES driver support" + default y + depends on DT_HAS_TI_MSPM0_AES_ENABLED + depends on CRYPTO + select USE_MSPM0_DL_AES + help + Enable TI MSPM0 AES driver support + +config CRYPTO_MSPM0_MAX_SESSION + int "Maximum of sessions the mspm0 aes driver can handle" + default 2 + depends on CRYPTO_MSPM0_AES + help + This can be used to tweak the amount of sessions the driver + can handle in parallel diff --git a/drivers/crypto/crypto_cc23x0.c b/drivers/crypto/crypto_cc23x0.c index 15c8bcb19b550..f6f2d5efbac69 100644 --- a/drivers/crypto/crypto_cc23x0.c +++ b/drivers/crypto/crypto_cc23x0.c @@ -14,6 +14,9 @@ LOG_MODULE_REGISTER(crypto_cc23x0, CONFIG_CRYPTO_LOG_LEVEL); #include #include #include +#include +#include +#include #include #include @@ -80,6 +83,22 @@ struct crypto_cc23x0_data { #endif }; +static inline void crypto_cc23x0_pm_policy_state_lock_get(void) +{ +#ifdef CONFIG_PM_DEVICE + pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); +#endif +} + +static inline void crypto_cc23x0_pm_policy_state_lock_put(void) +{ +#ifdef CONFIG_PM_DEVICE + pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); +#endif +} + static void crypto_cc23x0_isr(const struct device *dev) { struct crypto_cc23x0_data *data = dev->data; @@ -102,17 +121,42 @@ static void crypto_cc23x0_isr(const struct device *dev) AESClearInterrupt(status); } -static void crypto_cc23x0_cleanup(const struct device *dev) -{ #ifdef CONFIG_CRYPTO_CC23X0_DMA + +static int crypto_cc23x0_dma_enable(const struct device *dev, bool *dma_enabled) +{ + const struct crypto_cc23x0_config *cfg = dev->config; + int ret; + + ret = pm_device_runtime_get(cfg->dma_dev); + if (ret) { + LOG_ERR("Failed to resume DMA"); + *dma_enabled = false; + } else { + *dma_enabled = true; + } + + return ret; +} + +static void crypto_cc23x0_dma_cleanup(const struct device *dev, bool dma_enabled) +{ const struct crypto_cc23x0_config *cfg = dev->config; dma_stop(cfg->dma_dev, cfg->dma_channel_b); dma_stop(cfg->dma_dev, cfg->dma_channel_a); + AESDisableDMA(); -#else - ARG_UNUSED(dev); -#endif + + if (dma_enabled) { + pm_device_runtime_put(cfg->dma_dev); + } +} + +#endif /* CONFIG_CRYPTO_CC23X0_DMA */ + +static void crypto_cc23x0_aes_cleanup(void) +{ AESClearAUTOCFGTrigger(); AESClearAUTOCFGBusHalt(); AESClearTXTAndBUF(); @@ -127,6 +171,7 @@ static int crypto_cc23x0_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt * #ifdef CONFIG_CRYPTO_CC23X0_DMA uint32_t int_flags = AES_IMASK_CHBDONE; const struct crypto_cc23x0_config *cfg = dev->config; + bool dma_enabled = false; struct dma_block_config block_cfg_cha = { .source_address = (uint32_t)(pkt->in_buf), @@ -186,6 +231,8 @@ static int crypto_cc23x0_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt * k_mutex_lock(&data->device_mutex, K_FOREVER); + crypto_cc23x0_pm_policy_state_lock_get(); + /* Enable interrupts */ AESSetIMASK(int_flags); @@ -198,6 +245,11 @@ static int crypto_cc23x0_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt * AES_AUTOCFG_TRGAES_WRBUF3S); #ifdef CONFIG_CRYPTO_CC23X0_DMA + ret = crypto_cc23x0_dma_enable(dev, &dma_enabled); + if (ret) { + goto cleanup; + } + /* Setup the DMA for the AES engine */ AESSetupDMA(AES_DMA_ADRCHA_BUF0 | AES_DMA_TRGCHA_AESSTART | @@ -209,11 +261,13 @@ static int crypto_cc23x0_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt * ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha); if (ret) { + LOG_ERR("Failed to configure DMA CHA"); goto cleanup; } ret = dma_config(cfg->dma_dev, cfg->dma_channel_b, &dma_cfg_chb); if (ret) { + LOG_ERR("Failed to configure DMA CHB"); goto cleanup; } @@ -265,7 +319,11 @@ static int crypto_cc23x0_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt * #endif cleanup: - crypto_cc23x0_cleanup(dev); +#ifdef CONFIG_CRYPTO_CC23X0_DMA + crypto_cc23x0_dma_cleanup(dev, dma_enabled); +#endif + crypto_cc23x0_aes_cleanup(); + crypto_cc23x0_pm_policy_state_lock_put(); k_mutex_unlock(&data->device_mutex); pkt->out_len = out_bytes_processed; @@ -284,6 +342,7 @@ static int crypto_cc23x0_ctr(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uin #ifdef CONFIG_CRYPTO_CC23X0_DMA uint32_t int_flags = AES_IMASK_CHBDONE; const struct crypto_cc23x0_config *cfg = dev->config; + bool dma_enabled = false; struct dma_block_config block_cfg_cha = { .source_address = (uint32_t)(pkt->in_buf), @@ -345,6 +404,8 @@ static int crypto_cc23x0_ctr(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uin k_mutex_lock(&data->device_mutex, K_FOREVER); + crypto_cc23x0_pm_policy_state_lock_get(); + /* Enable interrupts */ AESSetIMASK(int_flags); @@ -359,6 +420,11 @@ static int crypto_cc23x0_ctr(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uin AES_AUTOCFG_CTRSIZE_CTR128); #ifdef CONFIG_CRYPTO_CC23X0_DMA + ret = crypto_cc23x0_dma_enable(dev, &dma_enabled); + if (ret) { + goto cleanup; + } + /* Setup the DMA for the AES engine */ AESSetupDMA(AES_DMA_ADRCHA_TXTX0 | AES_DMA_TRGCHA_AESDONE | @@ -367,11 +433,13 @@ static int crypto_cc23x0_ctr(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uin ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha); if (ret) { + LOG_ERR("Failed to configure DMA CHA"); goto cleanup; } ret = dma_config(cfg->dma_dev, cfg->dma_channel_b, &dma_cfg_chb); if (ret) { + LOG_ERR("Failed to configure DMA CHB"); goto cleanup; } @@ -433,7 +501,11 @@ static int crypto_cc23x0_ctr(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uin #endif cleanup: - crypto_cc23x0_cleanup(dev); +#ifdef CONFIG_CRYPTO_CC23X0_DMA + crypto_cc23x0_dma_cleanup(dev, dma_enabled); +#endif + crypto_cc23x0_aes_cleanup(); + crypto_cc23x0_pm_policy_state_lock_put(); k_mutex_unlock(&data->device_mutex); pkt->out_len = bytes_processed; @@ -451,6 +523,7 @@ static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt, #ifdef CONFIG_CRYPTO_CC23X0_DMA uint32_t int_flags = AES_IMASK_CHADONE; const struct crypto_cc23x0_config *cfg = dev->config; + bool dma_enabled = false; struct dma_block_config block_cfg_cha = { .source_address = (uint32_t)b0, @@ -492,6 +565,8 @@ static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt, k_mutex_lock(&data->device_mutex, K_FOREVER); + crypto_cc23x0_pm_policy_state_lock_get(); + /* Enable interrupts */ AESSetIMASK(int_flags); @@ -506,6 +581,13 @@ static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt, /* Write zero'd IV */ AESWriteIV32(iv); +#ifdef CONFIG_CRYPTO_CC23X0_DMA + ret = crypto_cc23x0_dma_enable(dev, &dma_enabled); + if (ret) { + goto out; + } +#endif + if (b0) { #ifdef CONFIG_CRYPTO_CC23X0_DMA /* Setup the DMA for the AES engine */ @@ -514,6 +596,7 @@ static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt, ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha); if (ret) { + LOG_ERR("Failed to configure DMA CHA"); goto out; } @@ -546,6 +629,7 @@ static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt, ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha); if (ret) { + LOG_ERR("Failed to configure DMA CHA"); goto out; } @@ -578,6 +662,7 @@ static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt, ret = dma_config(cfg->dma_dev, cfg->dma_channel_a, &dma_cfg_cha); if (ret) { + LOG_ERR("Failed to configure DMA CHA"); goto out; } @@ -624,7 +709,11 @@ static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt, AESReadTag(pkt->out_buf); out: - crypto_cc23x0_cleanup(dev); +#ifdef CONFIG_CRYPTO_CC23X0_DMA + crypto_cc23x0_dma_cleanup(dev, dma_enabled); +#endif + crypto_cc23x0_aes_cleanup(); + crypto_cc23x0_pm_policy_state_lock_put(); k_mutex_unlock(&data->device_mutex); pkt->out_len = bytes_processed; @@ -979,6 +1068,7 @@ static int crypto_cc23x0_init(const struct device *dev) { #ifdef CONFIG_CRYPTO_CC23X0_DMA const struct crypto_cc23x0_config *cfg = dev->config; + int ret; #endif struct crypto_cc23x0_data *data = dev->data; @@ -1000,6 +1090,12 @@ static int crypto_cc23x0_init(const struct device *dev) if (!device_is_ready(cfg->dma_dev)) { return -ENODEV; } + + ret = pm_device_runtime_enable(cfg->dma_dev); + if (ret) { + LOG_ERR("Failed to enable DMA runtime PM"); + return ret; + } #else k_sem_init(&data->aes_done, 0, 1); #endif @@ -1015,6 +1111,33 @@ static DEVICE_API(crypto, crypto_enc_funcs) = { static struct crypto_cc23x0_data crypto_cc23x0_dev_data; +#ifdef CONFIG_PM_DEVICE + +static int crypto_cc23x0_pm_action(const struct device *dev, enum pm_device_action action) +{ + int ret = 0; + + switch (action) { + case PM_DEVICE_ACTION_SUSPEND: + CLKCTLDisable(CLKCTL_BASE, CLKCTL_LAES); + break; + case PM_DEVICE_ACTION_RESUME: + CLKCTLEnable(CLKCTL_BASE, CLKCTL_LAES); + break; + case PM_DEVICE_ACTION_TURN_ON: + case PM_DEVICE_ACTION_TURN_OFF: + break; + default: + ret = -ENOTSUP; + } + + return ret; +} + +#endif /* CONFIG_PM_DEVICE */ + +PM_DEVICE_DT_INST_DEFINE(0, crypto_cc23x0_pm_action); + #ifdef CONFIG_CRYPTO_CC23X0_DMA static const struct crypto_cc23x0_config crypto_cc23x0_dev_config = { .dma_dev = DEVICE_DT_GET(TI_CC23X0_DT_INST_DMA_CTLR(0, cha)), @@ -1026,7 +1149,7 @@ static const struct crypto_cc23x0_config crypto_cc23x0_dev_config = { DEVICE_DT_INST_DEFINE(0, crypto_cc23x0_init, - NULL, + PM_DEVICE_DT_INST_GET(0), &crypto_cc23x0_dev_data, &crypto_cc23x0_dev_config, POST_KERNEL, @@ -1035,7 +1158,7 @@ DEVICE_DT_INST_DEFINE(0, #else DEVICE_DT_INST_DEFINE(0, crypto_cc23x0_init, - NULL, + PM_DEVICE_DT_INST_GET(0), &crypto_cc23x0_dev_data, NULL, POST_KERNEL, diff --git a/drivers/crypto/crypto_mspm0_aes.c b/drivers/crypto/crypto_mspm0_aes.c new file mode 100644 index 0000000000000..4dd03b7755fcd --- /dev/null +++ b/drivers/crypto/crypto_mspm0_aes.c @@ -0,0 +1,610 @@ +/* + * Copyright 2025 Linumiz GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_mspm0_aes + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define AES_HW_CAPS (CAP_RAW_KEY | CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS | CAP_NO_IV_PREFIX) +#define AES_BLOCK_SIZE 16 + +/* + * The block cycle for aes module max is 300 cycles + * safety margin for this module timeout 300 << 1 cycles + * K_CYC calculates the time period for respective clock freq + * AES_WAIT_TIMEOUT is calculated for worst case time + */ +#define AES_SEM_TIMEOUT K_CYC(AES_BLOCK_TIMEOUT) +#define AES_WAIT_TIMEOUT K_USEC(10) +#define AES_BLOCK_TIMEOUT (MSPM0_AES_BLOCK_CYC << 1) +#define MSPM0_AES_BLOCK_CYC 300 + +LOG_MODULE_REGISTER(aes, CONFIG_CRYPTO_LOG_LEVEL); + +struct crypto_mspm0_aes_config { + AES_Regs *regs; + void (*irq_config_func)(const struct device *dev); +}; + +struct mspm0_aes_session { + DL_AES_KEY_LENGTH keylen; + DL_AES_MODE aesconfig; + enum cipher_op op; + bool in_use; +}; + +struct crypto_mspm0_aes_data { + struct mspm0_aes_session sessions[CONFIG_CRYPTO_MSPM0_MAX_SESSION]; + struct k_mutex device_mutex; + struct k_sem aes_done; +}; + +static int validate_pkt(struct cipher_pkt *pkt) +{ + if (pkt == NULL || pkt->in_buf == NULL || pkt->out_buf == NULL) { + LOG_ERR("Invalid packet or NULL buffers"); + return -EINVAL; + } + + if (pkt->in_len == 0 || (pkt->in_len % AES_BLOCK_SIZE) != 0) { + LOG_ERR("Invalid input length"); + return -EINVAL; + } + + if (pkt->out_buf_max < AES_BLOCK_SIZE || pkt->out_buf_max < pkt->in_len) { + LOG_ERR("Output buffer too small"); + return -EINVAL; + } + + return 0; +} + +static int aes_hw_init(struct cipher_ctx *ctx) +{ + const struct device *dev = ctx->device; + const struct crypto_mspm0_aes_config *config = dev->config; + struct mspm0_aes_session *session = ctx->drv_sessn_state; + int ret; + + DL_AES_softwareReset(config->regs); + + DL_AES_init(config->regs, session->aesconfig, session->keylen); + + ret = DL_AES_setKey(config->regs, ctx->key.bit_stream, session->keylen); + if (ret != DL_AES_STATUS_SUCCESS) { + return ret; + } + + DL_AES_setAllKeyWritten(config->regs); + + return ret; +} + +static int crypto_aes_ecb_op(struct cipher_ctx *ctx, struct cipher_pkt *pkt) +{ + const struct device *dev = ctx->device; + const struct crypto_mspm0_aes_config *config = dev->config; + struct mspm0_aes_session *session = ctx->drv_sessn_state; + struct crypto_mspm0_aes_data *data = dev->data; + int bytes_processed = 0; + int ret; + + if (session == NULL || !session->in_use) { + LOG_ERR("No session data"); + return -EINVAL; + } + + ret = validate_pkt(pkt); + if (ret != 0) { + return ret; + } + + ret = k_mutex_lock(&data->device_mutex, AES_WAIT_TIMEOUT); + if (ret != 0) { + return ret; + } + + ret = aes_hw_init(ctx); + if (ret != 0) { + goto cleanup; + } + + do { + /* load the block */ + ret = DL_AES_loadDataIn(config->regs, &pkt->in_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + + /* wait for AES operation completion */ + ret = k_sem_take(&data->aes_done, AES_SEM_TIMEOUT); + if (ret != 0) { + break; + } + + /* read the dataout */ + ret = DL_AES_getDataOut(config->regs, &pkt->out_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + + bytes_processed += AES_BLOCK_SIZE; + + } while (bytes_processed < pkt->in_len); + +cleanup: + pkt->out_len = bytes_processed; + k_mutex_unlock(&data->device_mutex); + + return ret; +} + +static int crypto_aes_cbc_op(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv) +{ + const struct device *dev = ctx->device; + const struct crypto_mspm0_aes_config *config = dev->config; + struct mspm0_aes_session *session = ctx->drv_sessn_state; + struct crypto_mspm0_aes_data *data = dev->data; + bool pregen_key = false; + int bytes_processed = 0; + int ret; + + if (session == NULL || !session->in_use || iv == NULL) { + LOG_ERR("No session data"); + return -EINVAL; + } + + ret = validate_pkt(pkt); + if (ret != 0) { + return ret; + } + + if (session->op == CRYPTO_CIPHER_OP_DECRYPT) { + pregen_key = true; + } + + ret = k_mutex_lock(&data->device_mutex, AES_WAIT_TIMEOUT); + if (ret != 0) { + return ret; + } + + ret = aes_hw_init(ctx); + if (ret != 0) { + goto cleanup; + } + + /* Enable cipher mode for cbc */ + DL_AES_enableCipherMode(config->regs); + + /* change the mode from pre-gen to use-pre-gen key mode */ + if (pregen_key) { + DL_AES_MODE aesmode; + + ret = k_sem_take(&data->aes_done, AES_SEM_TIMEOUT); + if (ret != 0) { + goto cleanup; + } + + aesmode = DL_AES_MODE_DECRYPT_KEY_IS_FIRST_ROUND_KEY_CBC_MODE; + + DL_AES_init(config->regs, aesmode, session->keylen); + DL_AES_setAllKeyWritten(config->regs); + } + + /* load iv */ + ret = DL_AES_loadXORDataInWithoutTrigger(config->regs, iv); + if (ret != DL_AES_STATUS_SUCCESS) { + goto cleanup; + } + + do { + /* load the next block */ + if (session->op == CRYPTO_CIPHER_OP_DECRYPT) { + ret = DL_AES_loadDataIn(config->regs, + &pkt->in_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + } else { + ret = DL_AES_loadXORDataIn(config->regs, + &pkt->in_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + } + + /* wait for AES operation completion */ + ret = k_sem_take(&data->aes_done, AES_SEM_TIMEOUT); + if (ret != 0) { + break; + } + + /* xor the iv with internal state */ + if (session->op == CRYPTO_CIPHER_OP_DECRYPT) { + ret = DL_AES_loadXORDataInWithoutTrigger(config->regs, iv); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + iv = &pkt->in_buf[bytes_processed]; + } + + /* read the dataout */ + ret = DL_AES_getDataOut(config->regs, &pkt->out_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + bytes_processed += AES_BLOCK_SIZE; + + } while (bytes_processed < pkt->in_len); + +cleanup: + pkt->out_len = bytes_processed; + k_mutex_unlock(&data->device_mutex); + + return ret; +} + +static int crypto_aes_cfb_op(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv) +{ + const struct device *dev = ctx->device; + const struct crypto_mspm0_aes_config *config = dev->config; + struct mspm0_aes_session *session = ctx->drv_sessn_state; + struct crypto_mspm0_aes_data *data = dev->data; + int bytes_processed = 0; + int ret; + + if (session == NULL || !session->in_use || iv == NULL) { + LOG_ERR("No session data"); + return -EINVAL; + } + + ret = validate_pkt(pkt); + if (ret != 0) { + return ret; + } + + ret = k_mutex_lock(&data->device_mutex, AES_WAIT_TIMEOUT); + if (ret != 0) { + return ret; + } + + ret = aes_hw_init(ctx); + if (ret != 0) { + goto cleanup; + } + + /* Enable cipher mode for cfb */ + DL_AES_enableCipherMode(config->regs); + + do { + /* load the next block */ + ret = DL_AES_loadDataIn(config->regs, iv); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + + /* wait for AES operation completion */ + ret = k_sem_take(&data->aes_done, AES_SEM_TIMEOUT); + if (ret != 0) { + break; + } + + /* xor the intput block with internal state */ + ret = DL_AES_loadXORDataInWithoutTrigger(config->regs, + &pkt->in_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + + /* load next block */ + if (session->op == CRYPTO_CIPHER_OP_DECRYPT) { + iv = &pkt->in_buf[bytes_processed]; + } else { + iv = &pkt->out_buf[bytes_processed]; + } + + /* read the dataout */ + ret = DL_AES_getDataOut(config->regs, &pkt->out_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + bytes_processed += AES_BLOCK_SIZE; + + } while (bytes_processed < pkt->in_len); + +cleanup: + pkt->out_len = bytes_processed; + k_mutex_unlock(&data->device_mutex); + + return ret; +} + +static int crypto_aes_ofb_op(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv) +{ + const struct device *dev = ctx->device; + const struct crypto_mspm0_aes_config *config = dev->config; + struct mspm0_aes_session *session = ctx->drv_sessn_state; + struct crypto_mspm0_aes_data *data = dev->data; + uint8_t block[AES_BLOCK_SIZE] __aligned(4); + int bytes_processed = 0; + int ret; + + if (session == NULL || !session->in_use || iv == NULL) { + LOG_ERR("No session data"); + return -EINVAL; + } + + ret = validate_pkt(pkt); + if (ret != 0) { + return ret; + } + + ret = k_mutex_lock(&data->device_mutex, AES_WAIT_TIMEOUT); + if (ret != 0) { + return ret; + } + + ret = aes_hw_init(ctx); + if (ret != 0) { + goto cleanup; + } + + /* Enable cipher mode for ofb */ + DL_AES_enableCipherMode(config->regs); + + do { + /* load the next block */ + ret = DL_AES_loadDataIn(config->regs, iv); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + + /* wait for AES operation completion */ + ret = k_sem_take(&data->aes_done, AES_SEM_TIMEOUT); + if (ret != 0) { + break; + } + + /* read the dataout for next feedback */ + ret = DL_AES_getDataOut(config->regs, (uint8_t *)&block); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + iv = (uint8_t *)█ + + /* xor the input text with internal state */ + ret = DL_AES_loadXORDataInWithoutTrigger(config->regs, + &pkt->in_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + + /* read the dataout */ + ret = DL_AES_getDataOut(config->regs, &pkt->out_buf[bytes_processed]); + if (ret != DL_AES_STATUS_SUCCESS) { + break; + } + bytes_processed += AES_BLOCK_SIZE; + + } while (bytes_processed < pkt->in_len); + +cleanup: + pkt->out_len = bytes_processed; + k_mutex_unlock(&data->device_mutex); + + return ret; +} + +static void crypto_mspm0_aes_isr(const struct device *dev) +{ + const struct crypto_mspm0_aes_config *config = dev->config; + struct crypto_mspm0_aes_data *data = dev->data; + + if (!DL_AES_getPendingInterrupt(config->regs)) { + LOG_ERR("No pending Interrupts"); + return; + } + k_sem_give(&data->aes_done); +} + +static int aes_session_setup(const struct device *dev, struct cipher_ctx *ctx, + enum cipher_algo algo, enum cipher_mode mode, enum cipher_op op) +{ + struct crypto_mspm0_aes_data *data = dev->data; + struct mspm0_aes_session *session = NULL; + DL_AES_KEY_LENGTH keylen; + int ret; + + if (algo != CRYPTO_CIPHER_ALGO_AES || ctx == NULL || ctx->key.bit_stream == NULL) { + return -EINVAL; + } + + if (ctx->flags & ~(AES_HW_CAPS)) { + return -ENOTSUP; + } + + switch (ctx->keylen) { + case 16U: + keylen = DL_AES_KEY_LENGTH_128; + break; + case 32U: + keylen = DL_AES_KEY_LENGTH_256; + break; + default: + LOG_ERR("key size is not supported"); + return -EINVAL; + } + + ret = k_mutex_lock(&data->device_mutex, AES_WAIT_TIMEOUT); + if (ret != 0) { + return ret; + } + + for (uint8_t session_num = 0; session_num < ARRAY_SIZE(data->sessions); session_num++) { + if (!data->sessions[session_num].in_use) { + LOG_INF("Claiming session %d", session_num); + session = &data->sessions[session_num]; + break; + } + } + + if (session == NULL) { + LOG_INF("All %d session(s) in use", CONFIG_CRYPTO_MSPM0_MAX_SESSION); + ret = -EINVAL; + goto out; + } + + switch (mode) { + case CRYPTO_CIPHER_MODE_ECB: + if (op == CRYPTO_CIPHER_OP_ENCRYPT) { + session->aesconfig = DL_AES_MODE_ENCRYPT_ECB_MODE; + } else { + session->aesconfig = DL_AES_MODE_DECRYPT_SAME_KEY_ECB_MODE; + } + ctx->ops.block_crypt_hndlr = crypto_aes_ecb_op; + break; + + case CRYPTO_CIPHER_MODE_CBC: + if (op == CRYPTO_CIPHER_OP_ENCRYPT) { + session->aesconfig = DL_AES_MODE_ENCRYPT_CBC_MODE; + } else { + session->aesconfig = DL_AES_MODE_GEN_FIRST_ROUND_KEY_CBC_MODE; + } + ctx->ops.cbc_crypt_hndlr = crypto_aes_cbc_op; + break; + + case CRYPTO_CIPHER_MODE_CFB: + if (op == CRYPTO_CIPHER_OP_ENCRYPT) { + session->aesconfig = DL_AES_MODE_ENCRYPT_CFB_MODE; + } else { + session->aesconfig = DL_AES_MODE_DECRYPT_SAME_KEY_CFB_MODE; + } + ctx->ops.cfb_crypt_hndlr = crypto_aes_cfb_op; + break; + + case CRYPTO_CIPHER_MODE_OFB: + if (op == CRYPTO_CIPHER_OP_ENCRYPT) { + session->aesconfig = DL_AES_MODE_ENCRYPT_OFB_MODE; + } else { + session->aesconfig = DL_AES_MODE_DECRYPT_SAME_KEY_OFB_MODE; + } + ctx->ops.ofb_crypt_hndlr = crypto_aes_ofb_op; + break; + + default: + ret = -EINVAL; + goto out; + } + + session->keylen = keylen; + session->in_use = true; + ctx->drv_sessn_state = session; + ctx->ops.cipher_mode = mode; + ctx->device = dev; + session->op = op; +out: + k_mutex_unlock(&data->device_mutex); + return ret; +} + +static int aes_session_free(const struct device *dev, struct cipher_ctx *ctx) +{ + struct crypto_mspm0_aes_data *data = dev->data; + struct mspm0_aes_session *session; + int ret; + + if (ctx == NULL) { + return -EINVAL; + } + + session = ctx->drv_sessn_state; + + ret = k_mutex_lock(&data->device_mutex, AES_WAIT_TIMEOUT); + if (ret != 0) { + return ret; + } + + if (session == NULL || !session->in_use) { + LOG_ERR("Session already free!"); + k_mutex_unlock(&data->device_mutex); + return -EINVAL; + } + + session->in_use = false; + ctx->drv_sessn_state = NULL; + ctx->device = NULL; + + k_mutex_unlock(&data->device_mutex); + + return 0; +} + +static int aes_query_caps(const struct device *dev) +{ + ARG_UNUSED(dev); + return AES_HW_CAPS; +} + +int crypto_aes_init(const struct device *dev) +{ + const struct crypto_mspm0_aes_config *config = dev->config; + struct crypto_mspm0_aes_data *data = dev->data; + + DL_AES_enablePower(config->regs); + + k_mutex_init(&data->device_mutex); + + k_sem_init(&data->aes_done, 0, 1); + + /* disable interrupt */ + DL_AES_disableInterrupt(config->regs); + + /* clear interrupt status regs */ + DL_AES_clearInterruptStatus(config->regs); + + config->irq_config_func(dev); + + /* enable interrupt */ + DL_AES_enableInterrupt(config->regs); + + return 0; +} + +static DEVICE_API(crypto, crypto_enc_funcs) = { + .cipher_begin_session = aes_session_setup, + .cipher_free_session = aes_session_free, + .query_hw_caps = aes_query_caps, +}; + +#define MSPM0_AES_DEFINE(n) \ + \ +static void crypto_mspm0_irq_config_##n(const struct device *dev) \ +{ \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), crypto_mspm0_aes_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQN(n)); \ +} \ + \ +static const struct crypto_mspm0_aes_config crypto_aes_config_##n = { \ + .regs = (AES_Regs *)DT_INST_REG_ADDR(n), \ + .irq_config_func = crypto_mspm0_irq_config_##n, \ +}; \ + \ +struct crypto_mspm0_aes_data crypto_aes_data_##n; \ + \ +DEVICE_DT_INST_DEFINE(n, crypto_aes_init, NULL, &crypto_aes_data_##n, \ + &crypto_aes_config_##n, POST_KERNEL, CONFIG_CRYPTO_INIT_PRIORITY, \ + (void *)&crypto_enc_funcs); + +DT_INST_FOREACH_STATUS_OKAY(MSPM0_AES_DEFINE) diff --git a/drivers/crypto/crypto_rts5912_sha.c b/drivers/crypto/crypto_rts5912_sha.c index 3cbdbaf4cc2e3..113c8d8a90b56 100644 --- a/drivers/crypto/crypto_rts5912_sha.c +++ b/drivers/crypto/crypto_rts5912_sha.c @@ -89,14 +89,16 @@ static int rts5912_sha256_process(const struct device *dev, uint8_t *input, size uint32_t _wf_cycle_count = k_us_to_cyc_ceil32(RTS5912_MAXIMUM_CRYPTO_POLLING_TIME_US); uint32_t _wf_start = k_cycle_get_32(); + uint32_t _wf_now = _wf_start; while (!((sha2dma_regs->interrupt_status & INT_COMPLETE_MASK) != 0) && - (_wf_cycle_count > (k_cycle_get_32() - _wf_start))) { + (_wf_cycle_count > (_wf_now - _wf_start))) { k_msleep(1); Z_SPIN_DELAY(10); + _wf_now = k_cycle_get_32(); } - if (_wf_cycle_count < (k_cycle_get_32() - _wf_start)) { + if (_wf_cycle_count < (_wf_now - _wf_start)) { LOG_ERR("SHA2DMA reach timeout and breach"); return -EIO; } diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c index 801aba7d6edf3..f1b9a7d3a40d2 100644 --- a/drivers/dai/intel/dmic/dmic.c +++ b/drivers/dai/intel/dmic/dmic.c @@ -315,7 +315,7 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic) #if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \ defined(CONFIG_SOC_INTEL_ACE40) while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) { - k_sleep(K_USEC(100)); + k_busy_wait(100); } #endif } diff --git a/drivers/disk/Kconfig.sdmmc b/drivers/disk/Kconfig.sdmmc index 50b689891a201..baf6b5592f4f6 100644 --- a/drivers/disk/Kconfig.sdmmc +++ b/drivers/disk/Kconfig.sdmmc @@ -38,7 +38,7 @@ config SDMMC_STM32 select USE_STM32_HAL_MMC_EX if SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X select USE_STM32_LL_SDMMC select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X) - select DMA if $(DT_STM32_SDMMC_HAS_DMA) && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) + select DMA if $(DT_STM32_SDMMC_HAS_DMA) && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X) select PINCTRL select RESET help diff --git a/drivers/disk/sdmmc_stm32.c b/drivers/disk/sdmmc_stm32.c index 39304de569ac1..ff24e5bad036d 100644 --- a/drivers/disk/sdmmc_stm32.c +++ b/drivers/disk/sdmmc_stm32.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include #include @@ -47,6 +47,22 @@ LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL); #define SDMMC_BUS_WIDE_8B SDIO_BUS_WIDE_8B #endif +#ifndef SDMMC_CLOCK_EDGE_RISING +#define SDMMC_CLOCK_EDGE_RISING SDIO_CLOCK_EDGE_RISING +#endif + +#ifndef SDMMC_CLOCK_POWER_SAVE_ENABLE +#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDIO_CLOCK_POWER_SAVE_ENABLE +#endif + +#ifndef SDMMC_CLOCK_POWER_SAVE_DISABLE +#define SDMMC_CLOCK_POWER_SAVE_DISABLE SDIO_CLOCK_POWER_SAVE_DISABLE +#endif + +#ifndef SDMMC_HARDWARE_FLOW_CONTROL_DISABLE +#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE SDIO_HARDWARE_FLOW_CONTROL_DISABLE +#endif + typedef void (*irq_config_func_t)(const struct device *dev); #if STM32_SDMMC_USE_DMA @@ -225,8 +241,8 @@ static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma return ret; } + handle->Instance = STM32_DMA_GET_INSTANCE(dma->reg, dma->channel_nb); #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1) - handle->Instance = __LL_DMA_GET_STREAM_INSTANCE(dma->reg, dma->channel_nb); handle->Init.Channel = dma->cfg.dma_slot * DMA_CHANNEL_1; handle->Init.PeriphInc = DMA_PINC_DISABLE; handle->Init.MemInc = DMA_MINC_ENABLE; @@ -239,14 +255,11 @@ static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma handle->Init.MemBurst = DMA_MBURST_INC4; handle->Init.PeriphBurst = DMA_PBURST_INC4; #else - uint32_t channel_id = dma->channel_nb - STM32_DMA_STREAM_OFFSET; - BUILD_ASSERT(STM32_SDMMC_USE_DMA_SHARED == 1, "Only txrx is supported on this family"); /* handle->Init.Direction is not initialised here on purpose. * Since the channel is reused for both directions, the direction is * configured before each read/write call. */ - handle->Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dma->reg, channel_id); handle->Init.Request = dma->cfg.dma_slot; handle->Init.PeriphInc = DMA_PINC_DISABLE; handle->Init.MemInc = DMA_MINC_ENABLE; @@ -881,7 +894,11 @@ static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = { .hsd = { .Instance = (MMC_TypeDef *)DT_INST_REG_ADDR(0), .Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING, -#ifdef SDMMC_CLOCK_BYPASS_DISABLE +#ifdef SDIO_CLOCK_BYPASS_DISABLE + .Init.ClockBypass = DT_INST_PROP(0, clk_bypass) + ? SDIO_CLOCK_BYPASS_ENABLE + : SDIO_CLOCK_BYPASS_DISABLE, +#elif defined(SDMMC_CLOCK_BYPASS_DISABLE) .Init.ClockBypass = DT_INST_PROP(0, clk_bypass) ? SDMMC_CLOCK_BYPASS_ENABLE : SDMMC_CLOCK_BYPASS_DISABLE, diff --git a/drivers/display/display_ili9xxx.c b/drivers/display/display_ili9xxx.c index fbe4f06aa1a1e..ef258cfed8922 100644 --- a/drivers/display/display_ili9xxx.c +++ b/drivers/display/display_ili9xxx.c @@ -331,7 +331,7 @@ static int ili9xxx_set_orientation(const struct device *dev, } else if (orientation == DISPLAY_ORIENTATION_ROTATED_90) { tx_data |= ILI9XXX_MADCTL_MV; } else if (orientation == DISPLAY_ORIENTATION_ROTATED_180) { - tx_data |= ILI9XXX_MADCTL_MY; + tx_data |= ILI9XXX_MADCTL_MY | ILI9XXX_MADCTL_ML; } else if (orientation == DISPLAY_ORIENTATION_ROTATED_270) { tx_data |= ILI9XXX_MADCTL_MV | ILI9XXX_MADCTL_MX | ILI9XXX_MADCTL_MY; @@ -342,7 +342,8 @@ static int ili9xxx_set_orientation(const struct device *dev, } else if (orientation == DISPLAY_ORIENTATION_ROTATED_90) { tx_data |= ILI9XXX_MADCTL_MV | ILI9XXX_MADCTL_MY; } else if (orientation == DISPLAY_ORIENTATION_ROTATED_180) { - tx_data |= ILI9XXX_MADCTL_MY | ILI9XXX_MADCTL_MX; + tx_data |= ILI9XXX_MADCTL_MY | ILI9XXX_MADCTL_MX | + ILI9XXX_MADCTL_ML; } else if (orientation == DISPLAY_ORIENTATION_ROTATED_270) { tx_data |= ILI9XXX_MADCTL_MV | ILI9XXX_MADCTL_MX; } @@ -425,6 +426,20 @@ static int ili9xxx_configure(const struct device *dev) } } + if (config->te_mode != MIPI_DBI_TE_NO_EDGE) { + /* Attempt to enable TE signal */ + r = mipi_dbi_configure_te(config->mipi_dev, config->te_mode, 0); + if (r == 0) { + /* TE was enabled, send TEON, and enable vblank only */ + const uint8_t tx_data = 0x0; /* Set M bit to 0 */ + + r = ili9xxx_transmit(dev, ILI9XXX_TEON, &tx_data, 1U); + if (r < 0) { + return r; + } + } + } + r = config->regs_init_fn(dev); if (r < 0) { return r; @@ -535,6 +550,7 @@ static const struct ili9xxx_quirks ili9488_quirks = { .x_resolution = ILI##t##_X_RES, \ .y_resolution = ILI##t##_Y_RES, \ .inversion = DT_PROP(INST_DT_ILI9XXX(n, t), display_inversion),\ + .te_mode = MIPI_DBI_TE_MODE_DT(INST_DT_ILI9XXX(n, t), te_mode),\ .regs = &ili##t##_regs_##n, \ .regs_init_fn = ili##t##_regs_init, \ }; \ diff --git a/drivers/display/display_ili9xxx.h b/drivers/display/display_ili9xxx.h index 861b26d436099..cb3774246c72a 100644 --- a/drivers/display/display_ili9xxx.h +++ b/drivers/display/display_ili9xxx.h @@ -24,6 +24,7 @@ #define ILI9XXX_RAMWR 0x2c #define ILI9XXX_RGBSET 0x2d #define ILI9XXX_RAMRD 0x2e +#define ILI9XXX_TEON 0x35 #define ILI9XXX_MADCTL 0x36 #define ILI9XXX_PIXSET 0x3A #define ILI9XXX_RAMRD_CONT 0x3e @@ -74,6 +75,7 @@ struct ili9xxx_config { uint16_t x_resolution; uint16_t y_resolution; bool inversion; + uint8_t te_mode; const void *regs; int (*regs_init_fn)(const struct device *dev); }; diff --git a/drivers/dma/dma_mcux_lpc.c b/drivers/dma/dma_mcux_lpc.c index 5c5f6e27e5d90..2cc7500dfc2a0 100644 --- a/drivers/dma/dma_mcux_lpc.c +++ b/drivers/dma/dma_mcux_lpc.c @@ -33,6 +33,7 @@ struct dma_mcux_lpc_config { uint32_t otrig_base_address; uint32_t itrig_base_address; uint8_t num_of_channels; + uint8_t num_of_allocated_channels; uint8_t num_of_otrigs; void (*irq_config_func)(const struct device *dev); }; @@ -529,6 +530,12 @@ static int dma_mcux_lpc_configure(const struct device *dev, uint32_t channel, /* If needed, allocate a slot to store dma channel data */ if (dma_data->channel_index[channel] == -1) { + /* Not enough items in channel data array */ + if (dma_data->num_channels_used >= dev_config->num_of_allocated_channels) { + LOG_ERR("No free DMA channels available"); + return -ENOMEM; + } + dma_data->channel_index[channel] = dma_data->num_channels_used; dma_data->num_channels_used++; /* Get the slot number that has the dma channel data */ @@ -1016,6 +1023,7 @@ static DEVICE_API(dma, dma_mcux_lpc_api) = { static const struct dma_mcux_lpc_config dma_##n##_config = { \ .base = (DMA_Type *)DT_INST_REG_ADDR(n), \ .num_of_channels = DT_INST_PROP(n, dma_channels), \ + .num_of_allocated_channels = DMA_MCUX_LPC_NUM_USED_CHANNELS(n), \ .num_of_otrigs = DT_INST_PROP_OR(n, nxp_dma_num_of_otrigs, 0), \ .otrig_base_address = DT_INST_PROP_OR(n, nxp_dma_otrig_base_address, 0x0), \ .itrig_base_address = DT_INST_PROP_OR(n, nxp_dma_itrig_base_address, 0x0), \ diff --git a/drivers/dma/dma_sedi.c b/drivers/dma/dma_sedi.c index ec21e57e47408..bda7a63d33ef2 100644 --- a/drivers/dma/dma_sedi.c +++ b/drivers/dma/dma_sedi.c @@ -217,21 +217,21 @@ static int dma_sedi_apply_single_config(sedi_dma_t dev, uint32_t channel, if (ret != 0) { goto INVALID_ARGS; } - /* configurate dma width of source data*/ + /* configure dma width of source data*/ ret = width_index(config->source_data_size, &temp); if (ret != 0) { goto INVALID_ARGS; } sedi_dma_control(dev, channel, SEDI_CONFIG_DMA_SR_TRANS_WIDTH, temp); - /* configurate dma width of destination data*/ + /* configure dma width of destination data*/ ret = width_index(config->dest_data_size, &temp); if (ret != 0) { goto INVALID_ARGS; } sedi_dma_control(dev, channel, SEDI_CONFIG_DMA_DT_TRANS_WIDTH, temp); - /* configurate dma burst size*/ + /* configure dma burst size*/ ret = burst_index(config->source_burst_length, &temp); if (ret != 0) { goto INVALID_ARGS; diff --git a/drivers/dma/dma_si32.c b/drivers/dma/dma_si32.c index 5ceca6a89ab51..6db30ab226430 100644 --- a/drivers/dma/dma_si32.c +++ b/drivers/dma/dma_si32.c @@ -370,7 +370,7 @@ static int dma_si32_start(const struct device *dev, const uint32_t channel) "Address location of the channel transfer descriptors (BASEPTR) must be set."); __ASSERT(SI32_DMACTRL_A_is_primary_selected(SI32_DMACTRL_0, channel), "Primary descriptors must be used for basic and auto-request operations."); - __ASSERT(SI32_SCONFIG_0->CONFIG.FDMAEN, "Fast mode is recommened to be enabled."); + __ASSERT(SI32_SCONFIG_0->CONFIG.FDMAEN, "Fast mode is recommended to be enabled."); __ASSERT(SI32_DMACTRL_0->CHSTATUS.U32 & BIT(channel), "Channel must be waiting for request"); diff --git a/drivers/dma/dma_stm32.c b/drivers/dma/dma_stm32.c index 968e5b9d8d935..1509d536d47d6 100644 --- a/drivers/dma/dma_stm32.c +++ b/drivers/dma/dma_stm32.c @@ -273,10 +273,9 @@ DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev, struct dma_config *config) { const struct dma_stm32_config *dev_config = dev->config; - struct dma_stm32_stream *stream = - &dev_config->streams[id - STM32_DMA_STREAM_OFFSET]; DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base; LL_DMA_InitTypeDef DMA_InitStruct; + struct dma_stm32_stream *stream; int ret; LL_DMA_StructInit(&DMA_InitStruct); @@ -289,6 +288,7 @@ DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev, return -EINVAL; } + stream = &dev_config->streams[id]; if (stream->busy) { LOG_ERR("dma stream %d is busy.", id); return -EBUSY; @@ -594,8 +594,8 @@ DMA_STM32_EXPORT_API int dma_stm32_start(const struct device *dev, uint32_t id) DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id) { const struct dma_stm32_config *config = dev->config; - struct dma_stm32_stream *stream = &config->streams[id - STM32_DMA_STREAM_OFFSET]; DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); + struct dma_stm32_stream *stream; /* Give channel from index 0 */ id = id - STM32_DMA_STREAM_OFFSET; @@ -604,6 +604,8 @@ DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id) return -EINVAL; } + stream = &config->streams[id]; + if (stream->hal_override) { stream->busy = false; return 0; diff --git a/drivers/dma/dma_stm32u5.c b/drivers/dma/dma_stm32u5.c index c7d3225a49ecb..23693fbc5b8f7 100644 --- a/drivers/dma/dma_stm32u5.c +++ b/drivers/dma/dma_stm32u5.c @@ -265,9 +265,9 @@ static void dma_stm32_irq_handler(const struct device *dev, uint32_t id) dma_stm32_clear_stream_irq(dev, id); return; } - callback_arg = id + STM32_DMA_STREAM_OFFSET; + callback_arg = id; - /* The dma stream id is in range from STM32_DMA_STREAM_OFFSET.. */ + /* The dma stream id is in range from 0.. */ if (stm32_dma_is_ht_irq_active(dma, id)) { /* Let HAL DMA handle flags on its own */ if (!stream->hal_override) { @@ -349,16 +349,12 @@ static int dma_stm32_configure(const struct device *dev, struct dma_config *config) { const struct dma_stm32_config *dev_config = dev->config; - struct dma_stm32_stream *stream = - &dev_config->streams[id - STM32_DMA_STREAM_OFFSET]; + struct dma_stm32_stream *stream = &dev_config->streams[id]; DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base; uint32_t ll_priority; uint32_t ll_direction; int ret; - /* Give channel from index 0 */ - id = id - STM32_DMA_STREAM_OFFSET; - if (id >= dev_config->max_streams) { LOG_ERR("cannot configure the dma stream %d.", id); return -EINVAL; @@ -553,9 +549,6 @@ static int dma_stm32_reload(const struct device *dev, uint32_t id, DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); struct dma_stm32_stream *stream; - /* Give channel from index 0 */ - id = id - STM32_DMA_STREAM_OFFSET; - if (id >= config->max_streams) { return -EINVAL; } @@ -570,9 +563,7 @@ static int dma_stm32_reload(const struct device *dev, uint32_t id, return -EINVAL; } - LL_DMA_ConfigAddresses(dma, - dma_stm32_id_to_stream(id), - src, dst); + LL_DMA_ConfigAddresses(dma, dma_stm32_id_to_stream(id), src, dst); LL_DMA_SetBlkDataLength(dma, dma_stm32_id_to_stream(id), size); @@ -590,9 +581,6 @@ static int dma_stm32_start(const struct device *dev, uint32_t id) DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); struct dma_stm32_stream *stream; - /* Give channel from index 0 */ - id = id - STM32_DMA_STREAM_OFFSET; - /* Only M2P or M2M mode can be started manually. */ if (id >= config->max_streams) { return -EINVAL; @@ -619,9 +607,6 @@ static int dma_stm32_suspend(const struct device *dev, uint32_t id) const struct dma_stm32_config *config = dev->config; DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); - /* Give channel from index 0 */ - id = id - STM32_DMA_STREAM_OFFSET; - if (id >= config->max_streams) { return -EINVAL; } @@ -642,9 +627,6 @@ static int dma_stm32_resume(const struct device *dev, uint32_t id) const struct dma_stm32_config *config = dev->config; DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); - /* Give channel from index 0 */ - id = id - STM32_DMA_STREAM_OFFSET; - if (id >= config->max_streams) { return -EINVAL; } @@ -658,12 +640,9 @@ static int dma_stm32_resume(const struct device *dev, uint32_t id) static int dma_stm32_stop(const struct device *dev, uint32_t id) { const struct dma_stm32_config *config = dev->config; - struct dma_stm32_stream *stream = &config->streams[id - STM32_DMA_STREAM_OFFSET]; + struct dma_stm32_stream *stream = &config->streams[id]; DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); - /* Give channel from index 0 */ - id = id - STM32_DMA_STREAM_OFFSET; - if (id >= config->max_streams) { return -EINVAL; } @@ -723,8 +702,6 @@ static int dma_stm32_get_status(const struct device *dev, DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); struct dma_stm32_stream *stream; - /* Give channel from index 0 */ - id = id - STM32_DMA_STREAM_OFFSET; if (id >= config->max_streams) { return -EINVAL; } diff --git a/drivers/dma/dma_wch.c b/drivers/dma/dma_wch.c index 37682ae9d8bcf..68f9719413073 100644 --- a/drivers/dma/dma_wch.c +++ b/drivers/dma/dma_wch.c @@ -89,7 +89,7 @@ static int dma_wch_init(const struct device *dev) return 0; } -/* Coverts a transfer width in bytes to the corresponding bitfield */ +/* Converts a transfer width in bytes to the corresponding bitfield */ static uint16_t dma_wch_width_index(uint32_t bytes) { switch (bytes) { diff --git a/drivers/entropy/entropy_stm32.c b/drivers/entropy/entropy_stm32.c index a4e8cf40f03c1..8b30e1396bcc3 100644 --- a/drivers/entropy/entropy_stm32.c +++ b/drivers/entropy/entropy_stm32.c @@ -205,7 +205,7 @@ static void configure_rng(void) #if DT_INST_NODE_HAS_PROP(0, nist_config) /* * Configure the RNG_CR in compliance with the NIST SP800. - * The nist-config is direclty copied from the DTS. + * The nist-config is directly copied from the DTS. * The RNG clock must be 48MHz else the clock DIV is not adpated. * The RNG_CR_CONDRST is set to 1 at the same time the RNG_CR is written */ diff --git a/drivers/ethernet/Kconfig.adin2111 b/drivers/ethernet/Kconfig.adin2111 index 2e1cbd8a0afdb..518035e74804f 100644 --- a/drivers/ethernet/Kconfig.adin2111 +++ b/drivers/ethernet/Kconfig.adin2111 @@ -6,7 +6,6 @@ menuconfig ETH_ADIN2111 default y depends on DT_HAS_ADI_ADIN2111_ENABLED || DT_HAS_ADI_ADIN1110_ENABLED select SPI - select MDIO imply CRC help The ADIN2111 is a low power, 2-port 10BASE-T1L transceiver diff --git a/drivers/ethernet/Kconfig.esp32 b/drivers/ethernet/Kconfig.esp32 index 35c07860f4ef3..ad2c8bfa0e79c 100644 --- a/drivers/ethernet/Kconfig.esp32 +++ b/drivers/ethernet/Kconfig.esp32 @@ -8,7 +8,6 @@ menuconfig ETH_ESP32 default y depends on SOC_SERIES_ESP32 depends on DT_HAS_ESPRESSIF_ESP32_ETH_ENABLED - select MDIO help Enable ESP32 Ethernet driver. diff --git a/drivers/ethernet/Kconfig.lan865x b/drivers/ethernet/Kconfig.lan865x index 347e73781523b..7f48550e5c4c0 100644 --- a/drivers/ethernet/Kconfig.lan865x +++ b/drivers/ethernet/Kconfig.lan865x @@ -6,7 +6,6 @@ menuconfig ETH_LAN865X default y depends on DT_HAS_MICROCHIP_LAN865X_ENABLED select SPI - select MDIO select NET_L2_ETHERNET_MGMT help The LAN865X is a low power, 10BASE-T1S transceiver compliant with diff --git a/drivers/ethernet/Kconfig.nxp_enet b/drivers/ethernet/Kconfig.nxp_enet index c035fbf686bf0..953ce84d51233 100644 --- a/drivers/ethernet/Kconfig.nxp_enet +++ b/drivers/ethernet/Kconfig.nxp_enet @@ -12,7 +12,6 @@ config ETH_NXP_ENET depends on DT_HAS_NXP_ENET_MAC_ENABLED select NOCACHE_MEMORY if CPU_HAS_DCACHE select ARM_MPU if CPU_CORTEX_M7 - select MDIO if DT_HAS_NXP_ENET_MDIO_ENABLED select NET_POWER_MANAGEMENT if (PM_DEVICE && SOC_FAMILY_KINETIS) select ETH_DSA_SUPPORT_DEPRECATED select PINCTRL diff --git a/drivers/ethernet/Kconfig.nxp_s32_netc b/drivers/ethernet/Kconfig.nxp_s32_netc index bf5a85cb97260..17a0d1f6c56d6 100644 --- a/drivers/ethernet/Kconfig.nxp_s32_netc +++ b/drivers/ethernet/Kconfig.nxp_s32_netc @@ -7,7 +7,6 @@ menuconfig ETH_NXP_S32_NETC depends on (DT_HAS_NXP_S32_NETC_PSI_ENABLED || DT_HAS_NXP_S32_NETC_VSI_ENABLED) select MBOX select PINCTRL - select MDIO if DT_HAS_NXP_S32_NETC_PSI_ENABLED select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT help Enable Ethernet Switch and Controller (NETC) driver for NXP S32 SoCs. diff --git a/drivers/ethernet/Kconfig.renesas_ra b/drivers/ethernet/Kconfig.renesas_ra index a6c04e9392b17..30dd333a575b9 100644 --- a/drivers/ethernet/Kconfig.renesas_ra +++ b/drivers/ethernet/Kconfig.renesas_ra @@ -6,7 +6,6 @@ config ETH_RENESAS_RA default y depends on DT_HAS_RENESAS_RA_ETHERNET_ENABLED select USE_RA_FSP_ETHER - select MDIO help Enable Renesas RA Ethernet Driver. @@ -33,4 +32,10 @@ config ETH_RENESAS_RX_BUF_NUM default 4 range 1 8 +config ETH_RENESAS_RA_USE_NS_BUF + bool "Use non-secure section for buffers" + default y if SOC_SERIES_RA6M5 || SOC_SERIES_RA6M4 + depends on CPU_HAS_TEE + depends on !ARM_SECURE_FIRMWARE && !ARM_NONSECURE_FIRMWARE + endif diff --git a/drivers/ethernet/Kconfig.sam_gmac b/drivers/ethernet/Kconfig.sam_gmac index 60403612bbb52..fed74b1ca40c2 100644 --- a/drivers/ethernet/Kconfig.sam_gmac +++ b/drivers/ethernet/Kconfig.sam_gmac @@ -10,7 +10,6 @@ menuconfig ETH_SAM_GMAC depends on DT_HAS_ATMEL_SAM_GMAC_ENABLED || \ DT_HAS_ATMEL_SAM0_GMAC_ENABLED select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT - select MDIO select ETH_DSA_SUPPORT_DEPRECATED select PINCTRL help diff --git a/drivers/ethernet/Kconfig.stm32_hal b/drivers/ethernet/Kconfig.stm32_hal index fc9beba2d90fb..3fd26ab4adde0 100644 --- a/drivers/ethernet/Kconfig.stm32_hal +++ b/drivers/ethernet/Kconfig.stm32_hal @@ -14,7 +14,6 @@ menuconfig ETH_STM32_HAL select HWINFO select ETH_DSA_SUPPORT_DEPRECATED select PINCTRL - select MDIO if DT_HAS_ST_STM32_MDIO_ENABLED imply CRC help Enable STM32 HAL based Ethernet driver. It is available for diff --git a/drivers/ethernet/Kconfig.sy1xx_mac b/drivers/ethernet/Kconfig.sy1xx_mac index 8493aa5305f54..58adf680e533f 100644 --- a/drivers/ethernet/Kconfig.sy1xx_mac +++ b/drivers/ethernet/Kconfig.sy1xx_mac @@ -5,7 +5,6 @@ config ETH_SY1XX bool "Sensry SY1XX Ethernet driver" default y depends on DT_HAS_SENSRY_SY1XX_MAC_ENABLED - select MDIO select PINCTRL help Enable Sensry SY1XX Ethernet MAC driver. diff --git a/drivers/ethernet/dsa/dsa_nxp_imx_netc.c b/drivers/ethernet/dsa/dsa_nxp_imx_netc.c index 9ba79ec10225f..fc8540f8e9e6e 100644 --- a/drivers/ethernet/dsa/dsa_nxp_imx_netc.c +++ b/drivers/ethernet/dsa/dsa_nxp_imx_netc.c @@ -18,12 +18,22 @@ LOG_MODULE_REGISTER(dsa_netc, CONFIG_ETHERNET_LOG_LEVEL); #define DT_DRV_COMPAT nxp_netc_switch #define PRV_DATA(ctx) ((struct dsa_netc_data *const)(ctx)->prv_data) +#define DEV_CFG(_dev) ((const struct dsa_netc_config *)(_dev)->config) +#define DEV_DATA(_dev) ((struct dsa_netc_data *)(_dev)->data) + struct dsa_netc_port_config { const struct pinctrl_dev_config *pincfg; netc_hw_mii_mode_t phy_mode; }; +struct dsa_netc_config { + DEVICE_MMIO_NAMED_ROM(base); + DEVICE_MMIO_NAMED_ROM(pfconfig); +}; + struct dsa_netc_data { + DEVICE_MMIO_NAMED_RAM(base); + DEVICE_MMIO_NAMED_RAM(pfconfig); swt_config_t swt_config; swt_handle_t swt_handle; netc_cmd_bd_t *cmd_bd; @@ -108,6 +118,14 @@ static void dsa_netc_port_phylink_change(const struct device *phydev, struct phy } } +static int dsa_netc_switch_init(const struct device *dev) +{ + DEVICE_MMIO_NAMED_MAP(dev, base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); + DEVICE_MMIO_NAMED_MAP(dev, pfconfig, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); + + return 0; +} + static struct dsa_api dsa_netc_api = { .port_init = dsa_netc_port_init, .port_generate_random_mac = dsa_netc_port_generate_random_mac, @@ -138,9 +156,21 @@ static struct dsa_api dsa_netc_api = { #define DSA_NETC_DEVICE(n) \ AT_NONCACHEABLE_SECTION_ALIGN(static netc_cmd_bd_t dsa_netc_##n##_cmd_bd[8], \ NETC_BD_ALIGN); \ + static const struct dsa_netc_config netc_switch##n##_config = { \ + DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME(base, DT_DRV_INST(n)), \ + DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME(pfconfig, DT_DRV_INST(n)), \ + }; \ static struct dsa_netc_data dsa_netc_data_##n = { \ .cmd_bd = dsa_netc_##n##_cmd_bd, \ }; \ - DSA_SWITCH_INST_INIT(n, &dsa_netc_api, &dsa_netc_data_##n, DSA_NETC_PORT_INST_INIT); + DEVICE_DT_INST_DEFINE(n, \ + dsa_netc_switch_init, \ + NULL, \ + &dsa_netc_data_##n, \ + &netc_switch##n##_config, \ + POST_KERNEL, \ + CONFIG_ETH_INIT_PRIORITY, \ + NULL); \ + DSA_SWITCH_INST_INIT(n, &dsa_netc_api, &dsa_netc_data_##n, DSA_NETC_PORT_INST_INIT); \ DT_INST_FOREACH_STATUS_OKAY(DSA_NETC_DEVICE); diff --git a/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c b/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c index 6eba5e32632bd..817508a4f7c03 100644 --- a/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c +++ b/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c @@ -420,8 +420,8 @@ static void dwxgmac_set_mac_addr_by_idx(const struct device *dev, uint8_t *addr, /** * 'sa' bit specifies if This MAC address[47:0] is used to compare with the source * address fields of the received packet. MAC Address with index 0 is always enabled - * for recive packet MAC address filtering. And 'sa' bit of MAC address with index 0 - * is reserved hence this step is excluded for index 0. + * for receive packet MAC address filtering. And 'sa' bit of MAC address with index + * 0 is reserved hence this step is excluded for index 0. */ reg_val |= CORE_MAC_ADDRESSx_HIGH_SA_SET(sa); } @@ -488,7 +488,7 @@ static void dwxgmac_mac_init(const struct device *dev, sys_write32(reg_val, ioaddr + CORE_MAC_PACKET_FILTER_OFST); - /* Enable Recive queues for Data Center Bridging/ Generic */ + /* Enable Receive queues for Data Center Bridging/ Generic */ reg_val = 0; for (uint32_t q = 0; q < config->num_rx_Qs; q++) { reg_val |= (XGMAC_RXQxEN_DCB << (q * XGMAC_RXQxEN_SIZE_BITS)); @@ -500,7 +500,7 @@ static void dwxgmac_mac_init(const struct device *dev, sys_write32(reg_val, ioaddr + CORE_MAC_TX_CONFIGURATION_OFST); /** - * Enable Giant Packet Size Limit Control, disable eatchdog timer on reciver and + * Enable Giant Packet Size Limit Control, disable eatchdog timer on receiver and * Configure RX checksum offload, jumbo packet enable, ARP offload, gaint packet size limit * in MAC RX configuration register. */ @@ -1060,7 +1060,7 @@ void eth_dwc_xgmac_prefill_rx_desc(const struct device *dev) * Every RX descriptor in the descriptor ring, needs to be prefilled with 2 RX * buffer addresses and put it to DMA ownership by setting the OWN bit. When new * data is received the DMA will check the OWN bit and moves the data to - * corresponding recive buffers and puts the RX descriptor to application ownership + * corresponding receive buffers and puts the RX descriptor to application ownership * by clearing the OWN bit. If received data size is more than total of 2 buffer * sizes then DMA will use next descriptor in the ring. */ diff --git a/drivers/ethernet/eth_nxp_enet_qos/Kconfig b/drivers/ethernet/eth_nxp_enet_qos/Kconfig index 2f14424499840..a5fab3d617fdd 100644 --- a/drivers/ethernet/eth_nxp_enet_qos/Kconfig +++ b/drivers/ethernet/eth_nxp_enet_qos/Kconfig @@ -6,7 +6,6 @@ menuconfig ETH_NXP_ENET_QOS default y depends on DT_HAS_NXP_ENET_QOS_ENABLED select PINCTRL - select MDIO if DT_HAS_NXP_ENET_QOS_MDIO_ENABLED help Enable NXP ENET Ethernet Module Driver. This driver handles IP module level tasks. diff --git a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c index 93178fb91f293..f01288acd141f 100644 --- a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c +++ b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c @@ -131,12 +131,7 @@ static int eth_nxp_enet_qos_tx(const struct device *dev, struct net_pkt *pkt) k_thread_name_get(k_current_get())); net_pkt_ref(pkt); - data->tx.pkt = pkt; - /* Need to save the header because the ethernet stack - * otherwise discards it from the packet after this call - */ - data->tx.tx_header = pkt->frags; LOG_DBG("Setting up TX descriptors for packet %p", pkt); @@ -197,8 +192,6 @@ static void tx_dma_done(const struct device *dev) net_pkt_frag_unref(fragment); fragment = fragment->frags; } - - net_pkt_frag_unref(data->tx.tx_header); net_pkt_unref(pkt); eth_stats_update_pkts_tx(data->iface); diff --git a/drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h b/drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h index bdc70108e8d2d..0df3736ad5d72 100644 --- a/drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h +++ b/drivers/ethernet/eth_nxp_enet_qos/nxp_enet_qos_priv.h @@ -106,7 +106,6 @@ struct nxp_enet_qos_mac_config { struct nxp_enet_qos_tx_data { struct k_sem tx_sem; struct net_pkt *pkt; - struct net_buf *tx_header; volatile union nxp_enet_qos_tx_desc descriptors[NUM_TX_BUFDESC]; }; diff --git a/drivers/ethernet/eth_renesas_ra.c b/drivers/ethernet/eth_renesas_ra.c index 161deb5f1529e..a0fd19e9d811c 100644 --- a/drivers/ethernet/eth_renesas_ra.c +++ b/drivers/ethernet/eth_renesas_ra.c @@ -12,7 +12,7 @@ #define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL #include -LOG_MODULE_REGISTER(LOG_MODULE_NAME); +LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL); #include #include @@ -66,11 +66,24 @@ struct renesas_ra_eth_config { const struct device *phy_dev; }; +/* + * In some Renesas SoCs, Ethernet peripheral is always a non-secure bus master. + * In that case, placing the Ethernet buffer in non-secure RAM is necessary. + */ +#define ETHER_BUFFER_ALIGN(s) static __aligned(s) +#if defined(CONFIG_ETH_RENESAS_RA_USE_NS_BUF) +#define ETHER_BUFFER_PLACE_IN_SECTION __attribute__((section(".ns_buffer.eth"))) +#else +#define ETHER_BUFFER_PLACE_IN_SECTION +#endif + #define DECLARE_ETHER_RX_BUFFER(idx, _) \ - static __aligned(32) uint8_t g_ether0_ether_rx_buffer##idx[ETHER_BUF_SIZE]; + ETHER_BUFFER_ALIGN(32) \ + uint8_t g_ether0_ether_rx_buffer##idx[ETHER_BUF_SIZE] ETHER_BUFFER_PLACE_IN_SECTION; #define DECLARE_ETHER_TX_BUFFER(idx, _) \ - static __aligned(32) uint8_t g_ether0_ether_tx_buffer##idx[ETHER_BUF_SIZE]; + ETHER_BUFFER_ALIGN(32) \ + uint8_t g_ether0_ether_tx_buffer##idx[ETHER_BUF_SIZE] ETHER_BUFFER_PLACE_IN_SECTION; #define DECLARE_ETHER_RX_BUFFER_PTR(idx, _) (uint8_t *)&g_ether0_ether_rx_buffer##idx[0] @@ -83,10 +96,12 @@ uint8_t *pp_g_ether0_ether_buffers[ETHER_TOTAL_BUF_NUM] = { LISTIFY(CONFIG_ETH_RENESAS_RX_BUF_NUM, DECLARE_ETHER_RX_BUFFER_PTR, (,)), LISTIFY(CONFIG_ETH_RENESAS_TX_BUF_NUM, DECLARE_ETHER_TX_BUFFER_PTR, (,)) }; -static __aligned(16) ether_instance_descriptor_t - g_ether0_tx_descriptors[CONFIG_ETH_RENESAS_TX_BUF_NUM]; -static __aligned(16) ether_instance_descriptor_t - g_ether0_rx_descriptors[CONFIG_ETH_RENESAS_RX_BUF_NUM]; +ETHER_BUFFER_ALIGN(16) +ether_instance_descriptor_t + g_ether0_tx_descriptors[CONFIG_ETH_RENESAS_TX_BUF_NUM] ETHER_BUFFER_PLACE_IN_SECTION; +ETHER_BUFFER_ALIGN(16) +ether_instance_descriptor_t + g_ether0_rx_descriptors[CONFIG_ETH_RENESAS_RX_BUF_NUM] ETHER_BUFFER_PLACE_IN_SECTION; const ether_extended_cfg_t g_ether0_extended_cfg_t = { .p_rx_descriptors = g_ether0_rx_descriptors, diff --git a/drivers/ethernet/eth_sam_gmac.c b/drivers/ethernet/eth_sam_gmac.c index 884f0caf425ce..52a3432418846 100644 --- a/drivers/ethernet/eth_sam_gmac.c +++ b/drivers/ethernet/eth_sam_gmac.c @@ -2155,10 +2155,10 @@ static void eth0_irq_config(void) PINCTRL_DT_INST_DEFINE(0); static const struct eth_sam_dev_cfg eth0_config = { - .regs = (Gmac *)DT_INST_REG_ADDR(0), + .regs = (Gmac *)DT_REG_ADDR(DT_INST_PARENT(0)), .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), #ifdef CONFIG_SOC_FAMILY_ATMEL_SAM - .clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0), + .clock_cfg = SAM_DT_CLOCK_PMC_CFG(0, DT_INST_PARENT(0)), #endif .config_func = eth0_irq_config, .phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, phy_handle)) diff --git a/drivers/ethernet/eth_sensry_sy1xx_mac.c b/drivers/ethernet/eth_sensry_sy1xx_mac.c index ca7f51d3f6d85..d254bb137343d 100644 --- a/drivers/ethernet/eth_sensry_sy1xx_mac.c +++ b/drivers/ethernet/eth_sensry_sy1xx_mac.c @@ -103,7 +103,7 @@ struct sy1xx_mac_dev_data { }; /* prototypes */ -static int sy1xx_mac_set_mac_addr(const struct device *dev, uint8_t *mac_addr); +static int sy1xx_mac_set_mac_addr(const struct device *dev); static int sy1xx_mac_set_promiscuous_mode(const struct device *dev, bool promiscuous_mode); static int sy1xx_mac_set_config(const struct device *dev, enum ethernet_config_type type, const struct ethernet_config *config); @@ -208,7 +208,6 @@ static int sy1xx_mac_start(const struct device *dev) sys_rand_get(&data->mac_addr, 6); /* Set MAC address locally administered, unicast (LAA) */ data->mac_addr[0] |= 0x02; - } sy1xx_mac_set_mac_addr(dev); @@ -312,7 +311,7 @@ static void sy1xx_mac_iface_init(struct net_if *iface) struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config; struct sy1xx_mac_dev_data *const data = dev->data; - LOG_INF("Interface init %s (%.8x)", net_if_get_device(iface)->name, iface); + LOG_INF("Interface init %s (%p)", net_if_get_device(iface)->name, iface); data->iface = iface; @@ -571,7 +570,7 @@ const struct ethernet_api sy1xx_mac_driver_api = { .base_addr = DT_INST_REG_ADDR_BY_NAME(n, data), \ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ .promiscuous_mode = DT_INST_PROP_OR(n, promiscuous_mode, false), \ - .use_zephyr_random_mac = DT_INST_NODE_HAS_PROP(n, zephyr_random_mac_address), \ + .use_zephyr_random_mac = DT_INST_PROP(n, zephyr_random_mac_address), \ .phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, phy_handle))}; \ \ static struct sy1xx_mac_dma_buffers __attribute__((section(".udma_access"))) \ diff --git a/drivers/ethernet/eth_xilinx_axienet.c b/drivers/ethernet/eth_xilinx_axienet.c index 4bf3e96846898..3e61a3216c8e7 100644 --- a/drivers/ethernet/eth_xilinx_axienet.c +++ b/drivers/ethernet/eth_xilinx_axienet.c @@ -388,7 +388,6 @@ static int xilinx_axienet_get_config(const struct device *dev, enum ethernet_con struct ethernet_config *config) { const struct xilinx_axienet_config *dev_config = dev->config; - const struct xilinx_axienet_data *data = dev->data; switch (type) { case ETHERNET_CONFIG_TYPE_RX_CHECKSUM_SUPPORT: diff --git a/drivers/ethernet/eth_xlnx_gem.c b/drivers/ethernet/eth_xlnx_gem.c index ad3a32976e230..b7e64610b7c9e 100644 --- a/drivers/ethernet/eth_xlnx_gem.c +++ b/drivers/ethernet/eth_xlnx_gem.c @@ -37,6 +37,12 @@ #include LOG_MODULE_REGISTER(LOG_MODULE_NAME); +#if CONFIG_QEMU_TARGET ||\ + DT_ANY_INST_HAS_BOOL_STATUS_OKAY(disable_rx_checksum_offload) ||\ + DT_ANY_INST_HAS_BOOL_STATUS_OKAY(disable_tx_checksum_offload) +#warning "xlnx_gem: at least one instance has checksum offloading to hardware disabled" +#endif + static int eth_xlnx_gem_dev_init(const struct device *dev); static void eth_xlnx_gem_iface_init(struct net_if *iface); static void eth_xlnx_gem_isr(const struct device *dev); @@ -181,16 +187,6 @@ static int eth_xlnx_gem_dev_init(const struct device *dev) "must be 16380 bytes maximum.", dev->name, dev_conf->tx_buffer_size); - /* Checksum offloading limitations of the QEMU GEM implementation */ -#ifdef CONFIG_QEMU_TARGET - __ASSERT(!dev_conf->enable_rx_chksum_offload, - "TCP/UDP/IP hardware checksum offloading is not " - "supported by the QEMU GEM implementation"); - __ASSERT(!dev_conf->enable_tx_chksum_offload, - "TCP/UDP/IP hardware checksum offloading is not " - "supported by the QEMU GEM implementation"); -#endif - /* * Initialization procedure as described in the Zynq-7000 TRM, * chapter 16.3.x. @@ -641,11 +637,11 @@ static enum ethernet_hw_caps eth_xlnx_gem_get_capabilities( caps |= ETHERNET_LINK_10BASE; } - if (dev_conf->enable_rx_chksum_offload) { + if (!dev_conf->disable_rx_chksum_offload) { caps |= ETHERNET_HW_RX_CHKSUM_OFFLOAD; } - if (dev_conf->enable_tx_chksum_offload) { + if (!dev_conf->disable_tx_chksum_offload) { caps |= ETHERNET_HW_TX_CHKSUM_OFFLOAD; } @@ -682,7 +678,7 @@ static int eth_xlnx_gem_get_config(const struct device *dev, switch (type) { case ETHERNET_CONFIG_TYPE_RX_CHECKSUM_SUPPORT: - if (dev_conf->enable_rx_chksum_offload) { + if (!dev_conf->disable_rx_chksum_offload) { config->chksum_support = ETHERNET_CHECKSUM_SUPPORT_IPV4_HEADER | ETHERNET_CHECKSUM_SUPPORT_IPV6_HEADER | ETHERNET_CHECKSUM_SUPPORT_TCP | @@ -692,7 +688,7 @@ static int eth_xlnx_gem_get_config(const struct device *dev, } return 0; case ETHERNET_CONFIG_TYPE_TX_CHECKSUM_SUPPORT: - if (dev_conf->enable_tx_chksum_offload) { + if (!dev_conf->disable_tx_chksum_offload) { config->chksum_support = ETHERNET_CHECKSUM_SUPPORT_IPV4_HEADER | ETHERNET_CHECKSUM_SUPPORT_IPV6_HEADER | ETHERNET_CHECKSUM_SUPPORT_TCP | @@ -975,7 +971,7 @@ static void eth_xlnx_gem_set_initial_nwcfg(const struct device *dev) /* [25] RX half duplex while TX enable */ reg_val |= ETH_XLNX_GEM_NWCFG_HDRXEN_BIT; } - if (dev_conf->enable_rx_chksum_offload) { + if (!dev_conf->disable_rx_chksum_offload) { /* [24] enable RX IP/TCP/UDP checksum offload */ reg_val |= ETH_XLNX_GEM_NWCFG_RXCHKSUMEN_BIT; } @@ -1153,7 +1149,7 @@ static void eth_xlnx_gem_set_initial_dmacr(const struct device *dev) reg_val |= (((dev_conf->rx_buffer_size / 64) & ETH_XLNX_GEM_DMACR_RX_BUF_MASK) << ETH_XLNX_GEM_DMACR_RX_BUF_SHIFT); - if (dev_conf->enable_tx_chksum_offload) { + if (!dev_conf->disable_tx_chksum_offload) { /* [11] TX TCP/UDP/IP checksum offload to GEM */ reg_val |= ETH_XLNX_GEM_DMACR_TCP_CHKSUM_BIT; } diff --git a/drivers/ethernet/eth_xlnx_gem_priv.h b/drivers/ethernet/eth_xlnx_gem_priv.h index 74a3058fddcea..d784236e70406 100644 --- a/drivers/ethernet/eth_xlnx_gem_priv.h +++ b/drivers/ethernet/eth_xlnx_gem_priv.h @@ -453,7 +453,8 @@ static const struct eth_xlnx_gem_dev_cfg eth_xlnx_gem##port##_dev_cfg = {\ .enable_sgmii_mode = DT_INST_PROP(port, sgmii_mode),\ .disable_reject_fcs_crc_errors = DT_INST_PROP(port, disable_reject_fcs_crc_errors),\ .enable_rx_halfdup_while_tx = DT_INST_PROP(port, rx_halfdup_while_tx),\ - .enable_rx_chksum_offload = DT_INST_PROP(port, rx_checksum_offload),\ + .disable_rx_chksum_offload = UTIL_OR(IS_ENABLED(CONFIG_QEMU_TARGET),\ + DT_INST_PROP(port, disable_rx_checksum_offload)),\ .disable_pause_copy = DT_INST_PROP(port, disable_pause_copy),\ .discard_rx_fcs = DT_INST_PROP(port, discard_rx_fcs),\ .discard_rx_length_errors = DT_INST_PROP(port, discard_rx_length_errors),\ @@ -467,7 +468,8 @@ static const struct eth_xlnx_gem_dev_cfg eth_xlnx_gem##port##_dev_cfg = {\ .discard_non_vlan = DT_INST_PROP(port, discard_non_vlan),\ .enable_fdx = DT_INST_PROP(port, full_duplex),\ .disc_rx_ahb_unavail = DT_INST_PROP(port, discard_rx_frame_ahb_unavail),\ - .enable_tx_chksum_offload = DT_INST_PROP(port, tx_checksum_offload),\ + .disable_tx_chksum_offload = UTIL_OR(IS_ENABLED(CONFIG_QEMU_TARGET),\ + DT_INST_PROP(port, disable_tx_checksum_offload)),\ .tx_buffer_size_full = DT_INST_PROP(port, hw_tx_buffer_size_full),\ .enable_ahb_packet_endian_swap = DT_INST_PROP(port, ahb_packet_endian_swap),\ .enable_ahb_md_endian_swap = DT_INST_PROP(port, ahb_md_endian_swap)\ @@ -710,7 +712,7 @@ struct eth_xlnx_gem_dev_cfg { bool enable_sgmii_mode : 1; bool disable_reject_fcs_crc_errors : 1; bool enable_rx_halfdup_while_tx : 1; - bool enable_rx_chksum_offload : 1; + bool disable_rx_chksum_offload : 1; bool disable_pause_copy : 1; bool discard_rx_fcs : 1; bool discard_rx_length_errors : 1; @@ -724,7 +726,7 @@ struct eth_xlnx_gem_dev_cfg { bool discard_non_vlan : 1; bool enable_fdx : 1; bool disc_rx_ahb_unavail : 1; - bool enable_tx_chksum_offload : 1; + bool disable_tx_chksum_offload : 1; bool tx_buffer_size_full : 1; bool enable_ahb_packet_endian_swap : 1; bool enable_ahb_md_endian_swap : 1; diff --git a/drivers/ethernet/intel/Kconfig.intel_igc b/drivers/ethernet/intel/Kconfig.intel_igc index a8d37b5adcfd1..c13f874adb0e2 100644 --- a/drivers/ethernet/intel/Kconfig.intel_igc +++ b/drivers/ethernet/intel/Kconfig.intel_igc @@ -5,7 +5,6 @@ menuconfig ETH_INTEL_IGC bool "Intel IGC MAC driver" default y depends on DT_HAS_INTEL_IGC_MAC_ENABLED - select MDIO select PCIE_MSI_MULTI_VECTOR select PCIE_MSI_X help diff --git a/drivers/ethernet/nxp_imx_netc/Kconfig b/drivers/ethernet/nxp_imx_netc/Kconfig index 6c2a3eff29e2b..0769dae16ac09 100644 --- a/drivers/ethernet/nxp_imx_netc/Kconfig +++ b/drivers/ethernet/nxp_imx_netc/Kconfig @@ -5,7 +5,6 @@ menuconfig ETH_NXP_IMX_NETC bool "NXP IMX Ethernet and Network Controller (NETC) driver" default y depends on DT_HAS_NXP_IMX_NETC_PSI_ENABLED - select MDIO select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT help Enable Ethernet and Network Controller (NETC) driver for NXP IMX SoCs. diff --git a/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c index ae2a0a5389af1..1d8d75c1312df 100644 --- a/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c +++ b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c @@ -314,6 +314,7 @@ int netc_eth_init_common(const struct device *dev) ep_config.si = config->si_idx; ep_config.siConfig.txRingUse = 1; ep_config.siConfig.rxRingUse = 1; + ep_config.siConfig.vlanCtrl = kNETC_ENETC_StanCVlan | kNETC_ENETC_StanSVlan; ep_config.userData = data; ep_config.reclaimCallback = NULL; ep_config.msixEntry = &msix_entry[0]; diff --git a/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_blk.c b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_blk.c index 5e6aaa9e87978..84caf5e3795ac 100644 --- a/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_blk.c +++ b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_blk.c @@ -30,6 +30,8 @@ LOG_MODULE_REGISTER(nxp_imx_netc_blk); #define NETCSR_STATE BIT(1) /* NETCMIX CFG Link register */ +#ifdef CONFIG_SOC_MIMX9596 + #define CFG_LINK_MII_PROT 0x10 enum { MII, @@ -44,16 +46,46 @@ enum { #define CFG_LINK_MII_PROT_2_SHIFT 8 #define MII_PROT_N(prot, n) ((prot) << CFG_LINK_MII_PROT_##n##_SHIFT) +#elif defined(CONFIG_SOC_MIMX94398) + +enum { + MII, + RMII, + RGMII, + SGMII, +}; + +#define NETC_LINK_CFG0 0x4c +#define NETC_LINK_CFG1 0x50 +#define NETC_LINK_CFG2 0x54 +#define NETC_LINK_CFG3 0x58 +#define NETC_LINK_CFG4 0x5c +#define NETC_LINK_CFG5 0x60 + +#endif + /* NETCMIX PCS protocol register */ #define CFG_LINK_PCS_PROT_0 0x14 #define CFG_LINK_PCS_PROT_1 0x18 #define CFG_LINK_PCS_PROT_2 0x1c +#if defined(CONFIG_SOC_MIMX94398) +#define CFG_LINK_PCS_PROT_3 0x20 +#define CFG_LINK_PCS_PROT_4 0x24 +#define CFG_LINK_PCS_PROT_5 0x28 +#endif /* PCS Protocols */ #define CFG_LINK_PCS_PROT_1G_SGMII BIT(0) #define CFG_LINK_PCS_PROT_2500M_SGMII BIT(1) #define CFG_LINK_PCS_PROT_XFI BIT(3) #define CFG_LINK_PCS_PROT_10G_SXGMII BIT(6) +#if defined(CONFIG_SOC_MIMX94398) +#define EXT_PIN_CONTROL 0x10 +#define MAC2_MAC3_SEL_SHIFT 1 +#define SET_MAC2(x) ((x) & ~(BIT(MAC2_MAC3_SEL_SHIFT))) +#define SET_MAC3(x) ((x) | BIT(MAC2_MAC3_SEL_SHIFT)) +#endif + struct eth_nxp_imx_netc_blk_config { DEVICE_MMIO_NAMED_ROM(ierb); DEVICE_MMIO_NAMED_ROM(prb); @@ -157,6 +189,39 @@ static int netcmix_init(const struct device *dev) return 0; } +#elif defined(CONFIG_SOC_MIMX94398) +static int ierb_init(const struct device *dev) +{ + return 0; +} + + +static int netcmix_init(const struct device *dev) +{ + uintptr_t base = DEVICE_MMIO_NAMED_GET(dev, netcmix); + uint32_t reg_val; + + /* ToDo: configure PSC protocol and MII protocol according to PHY mode */ + sys_write32(CFG_LINK_PCS_PROT_2500M_SGMII, base + CFG_LINK_PCS_PROT_0); + sys_write32(CFG_LINK_PCS_PROT_2500M_SGMII, base + CFG_LINK_PCS_PROT_1); + sys_write32(CFG_LINK_PCS_PROT_1G_SGMII, base + CFG_LINK_PCS_PROT_2); + sys_write32(CFG_LINK_PCS_PROT_1G_SGMII, base + CFG_LINK_PCS_PROT_3); + sys_write32(CFG_LINK_PCS_PROT_1G_SGMII, base + CFG_LINK_PCS_PROT_4); + sys_write32(CFG_LINK_PCS_PROT_1G_SGMII, base + CFG_LINK_PCS_PROT_5); + + sys_write32(MII, base + NETC_LINK_CFG0); + sys_write32(MII, base + NETC_LINK_CFG1); + sys_write32(RGMII, base + NETC_LINK_CFG2); + sys_write32(RGMII, base + NETC_LINK_CFG3); + sys_write32(RGMII, base + NETC_LINK_CFG4); + sys_write32(RGMII, base + NETC_LINK_CFG5); + + reg_val = sys_read32(base + EXT_PIN_CONTROL); + reg_val = SET_MAC3(reg_val); + sys_write32(reg_val, base + EXT_PIN_CONTROL); + + return 0; +} #endif static int eth_nxp_imx_netc_blk_init(const struct device *dev) diff --git a/drivers/ethernet/phy/Kconfig b/drivers/ethernet/phy/Kconfig index 4caf58d1f5373..5cb3b336499e5 100644 --- a/drivers/ethernet/phy/Kconfig +++ b/drivers/ethernet/phy/Kconfig @@ -30,8 +30,9 @@ config PHY_INIT_PRIORITY config PHY_GENERIC_MII bool "Generic MII PHY Driver" - default y if DT_HAS_ETHERNET_PHY_ENABLED - depends on MDIO + default y + depends on DT_HAS_ETHERNET_PHY_ENABLED + select MDIO help This is a generic MII PHY interface that communicates with the PHY using the MDIO bus. @@ -40,6 +41,7 @@ config PHY_ADIN2111 bool "ADIN2111 PHY driver" default y depends on DT_HAS_ADI_ADIN2111_PHY_ENABLED || DT_HAS_ADI_ADIN1100_PHY_ENABLED + select MDIO help Enable ADIN2111 PHY driver. @@ -47,8 +49,9 @@ config PHY_MICROCHIP_KSZ8081 bool "Microchip KSZ8081 PHY Driver" default y depends on DT_HAS_MICROCHIP_KSZ8081_ENABLED - depends on MDIO - depends on GPIO + select MDIO + select GPIO if ($(dt_compat_any_has_prop,$(DT_COMPAT_MICROCHIP_KSZ8081),reset-gpios) || \ + $(dt_compat_any_has_prop,$(DT_COMPAT_MICROCHIP_KSZ8081),int-gpios)) help Enable Microchip KSZ8081 Ethernet PHY Driver @@ -56,8 +59,9 @@ config PHY_MICROCHIP_VSC8541 bool "Microchip VSC8541 PHY Driver" default y depends on DT_HAS_MICROCHIP_VSC8541_ENABLED - depends on MDIO - depends on GPIO + select MDIO + select GPIO if ($(dt_compat_any_has_prop,$(DT_COMPAT_MICROCHIP_VSC8541),reset-gpios) || \ + $(dt_compat_any_has_prop,$(DT_COMPAT_MICROCHIP_VSC8541),int-gpios)) help Enable Microchip VSC8541 Ethernet PHY Driver @@ -65,8 +69,9 @@ config PHY_TI_DP83825 bool "TI DP83825 PHY Driver" default y depends on DT_HAS_TI_DP83825_ENABLED - depends on MDIO - depends on GPIO + select MDIO + select GPIO if ($(dt_compat_any_has_prop,$(DT_COMPAT_TI_DP83825),reset-gpios) || \ + $(dt_compat_any_has_prop,$(DT_COMPAT_TI_DP83825),int-gpios)) help Enable TI DP83825 Ethernet PHY Driver @@ -74,8 +79,9 @@ config PHY_TI_DP83867 bool "TI DP83867 PHY Driver" default y depends on DT_HAS_TI_DP83867_ENABLED - depends on MDIO - depends on GPIO + select MDIO + select GPIO if ($(dt_compat_any_has_prop,$(DT_COMPAT_TI_DP83867),reset-gpios) || \ + $(dt_compat_any_has_prop,$(DT_COMPAT_TI_DP83867),int-gpios)) help Enable TI DP83867 Ethernet PHY Driver @@ -83,9 +89,9 @@ config PHY_REALTEK_RTL8211F bool "Realtek RTL8211F PHY Driver" default y depends on DT_HAS_REALTEK_RTL8211F_ENABLED - depends on MDIO - depends on GPIO || (!$(dt_compat_any_has_prop,$(DT_COMPAT_REALTEK_RTL8211F),reset-gpios) && \ - !$(dt_compat_any_has_prop,$(DT_COMPAT_REALTEK_RTL8211F),int-gpios)) + select MDIO + select GPIO if ($(dt_compat_any_has_prop,$(DT_COMPAT_REALTEK_RTL8211F),reset-gpios) || \ + $(dt_compat_any_has_prop,$(DT_COMPAT_REALTEK_RTL8211F),int-gpios)) help Enable Realtek RTL8211F Ethernet PHY Driver @@ -93,7 +99,7 @@ config PHY_QUALCOMM_AR8031 bool "Qualcomm Atheros AR8031 Ethernet PHY Driver" default y depends on DT_HAS_QCA_AR8031_ENABLED - depends on MDIO + select MDIO help Enable Qualcomm Atheros AR8031 Ethernet PHY Driver diff --git a/drivers/ethernet/phy/Kconfig.dm8806 b/drivers/ethernet/phy/Kconfig.dm8806 index e952420f7f0c9..a0713a7a28a3a 100644 --- a/drivers/ethernet/phy/Kconfig.dm8806 +++ b/drivers/ethernet/phy/Kconfig.dm8806 @@ -7,7 +7,7 @@ menuconfig PHY_DM8806 bool "Davicom PHY DM8806 driver" default y depends on DT_HAS_DAVICOM_DM8806_PHY_ENABLED - depends on MDIO + select MDIO help Enable driver for Davicom DM8806 PHY. diff --git a/drivers/ethernet/phy/Kconfig.microchip_t1s b/drivers/ethernet/phy/Kconfig.microchip_t1s index ae0b27b076ad9..a5d9e6008e4f1 100644 --- a/drivers/ethernet/phy/Kconfig.microchip_t1s +++ b/drivers/ethernet/phy/Kconfig.microchip_t1s @@ -5,7 +5,7 @@ config PHY_MICROCHIP_T1S bool "Microchip 10BASE-T1S Ethernet PHYs Driver" default y depends on DT_HAS_MICROCHIP_T1S_PHY_ENABLED - depends on MDIO + select MDIO select PHY_OA_TC14_PLCA_LIB help Enable Microchip's LAN8650/1 Rev.B0/B1 Internal PHYs and diff --git a/drivers/ethernet/phy/Kconfig.tja1103 b/drivers/ethernet/phy/Kconfig.tja1103 index e0a00955ce7a2..e7ee267df254c 100644 --- a/drivers/ethernet/phy/Kconfig.tja1103 +++ b/drivers/ethernet/phy/Kconfig.tja1103 @@ -7,7 +7,7 @@ menuconfig PHY_TJA1103 bool "TJA1103 PHY driver" default y depends on DT_HAS_NXP_TJA1103_ENABLED - depends on MDIO + select MDIO help Enable TJA1103 PHY driver. diff --git a/drivers/ethernet/phy/Kconfig.tja11xx b/drivers/ethernet/phy/Kconfig.tja11xx index b4cff9b74851b..995f13f3fd4dd 100644 --- a/drivers/ethernet/phy/Kconfig.tja11xx +++ b/drivers/ethernet/phy/Kconfig.tja11xx @@ -7,6 +7,6 @@ config PHY_TJA11XX bool "TJA11XX PHY driver" default y depends on DT_HAS_NXP_TJA11XX_ENABLED - depends on MDIO + select MDIO help Enable TJA11xx PHY driver. diff --git a/drivers/ethernet/phy/phy_adin2111.c b/drivers/ethernet/phy/phy_adin2111.c index 41d2ec7464767..8ba0023fd2499 100644 --- a/drivers/ethernet/phy/phy_adin2111.c +++ b/drivers/ethernet/phy/phy_adin2111.c @@ -365,7 +365,7 @@ static int phy_adin2111_reset(const struct device *dev) static void invoke_link_cb(const struct device *dev) { struct phy_adin2111_data *const data = dev->data; - struct phy_link_state state; + struct phy_link_state state = data->state; if (data->cb == NULL) { return; diff --git a/drivers/ethernet/phy/phy_microchip_ksz8081.c b/drivers/ethernet/phy/phy_microchip_ksz8081.c index 71c799777bb10..a671dbf57abb7 100644 --- a/drivers/ethernet/phy/phy_microchip_ksz8081.c +++ b/drivers/ethernet/phy/phy_microchip_ksz8081.c @@ -31,6 +31,10 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #define PHY_MC_KSZ8081_OMSO_RMII_OVERRIDE_MASK BIT(1) #define PHY_MC_KSZ8081_OMSO_MII_OVERRIDE_MASK BIT(0) +#define PHY_MC_KSZ8081_ICS_REG 0x1B +#define PHY_MC_KSZ8081_ICS_LINK_DOWN_IE_MASK BIT(10) +#define PHY_MC_KSZ8081_ICS_LINK_UP_IE_MASK BIT(8) + #define PHY_MC_KSZ8081_CTRL2_REG 0x1F #define PHY_MC_KSZ8081_CTRL2_REF_CLK_SEL BIT(7) @@ -53,19 +57,34 @@ struct mc_ksz8081_config { #endif }; +/* arbitrarily defined internal driver flags */ +#define KSZ8081_DO_AUTONEG_FLAG BIT(0) +#define KSZ8081_SILENCE_DEBUG_LOGS BIT(1) +#define KSZ8081_LINK_STATE_VALID BIT(2) + +#define USING_INTERRUPT_GPIO \ + UTIL_OR(DT_ALL_INST_HAS_PROP_STATUS_OKAY(int_gpios), \ + UTIL_AND(DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios), \ + (config->interrupt_gpio.port != NULL))) + struct mc_ksz8081_data { const struct device *dev; struct phy_link_state state; phy_callback_t cb; +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) + struct gpio_callback gpio_callback; +#endif void *cb_data; struct k_mutex mutex; struct k_work_delayable phy_monitor_work; + uint8_t flags; }; static int phy_mc_ksz8081_read(const struct device *dev, uint16_t reg_addr, uint32_t *data) { const struct mc_ksz8081_config *config = dev->config; + struct mc_ksz8081_data *dev_data = dev->data; int ret; /* Make sure excessive bits 16-31 are reset */ @@ -73,9 +92,14 @@ static int phy_mc_ksz8081_read(const struct device *dev, ret = mdio_read(config->mdio_dev, config->addr, reg_addr, (uint16_t *)data); if (ret) { + LOG_WRN("Failed to read from %s reg 0x%x", dev->name, reg_addr); return ret; } + if (!(dev_data->flags & KSZ8081_SILENCE_DEBUG_LOGS)) { + LOG_DBG("Read 0x%x from phy %d reg 0x%x", *data, config->addr, reg_addr); + } + return 0; } @@ -83,70 +107,182 @@ static int phy_mc_ksz8081_write(const struct device *dev, uint16_t reg_addr, uint32_t data) { const struct mc_ksz8081_config *config = dev->config; + struct mc_ksz8081_data *dev_data = dev->data; int ret; ret = mdio_write(config->mdio_dev, config->addr, reg_addr, (uint16_t)data); if (ret) { + LOG_WRN("Failed to write to %s reg 0x%x", dev->name, reg_addr); return ret; } + if (!(dev_data->flags & KSZ8081_SILENCE_DEBUG_LOGS)) { + LOG_DBG("Wrote 0x%x to phy %d reg 0x%x", data, config->addr, reg_addr); + } + return 0; } -static int phy_mc_ksz8081_autonegotiate(const struct device *dev) +#if !DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) +#define phy_mc_ksz8081_clear_interrupt(data) 0 +#else +static int phy_mc_ksz8081_clear_interrupt(struct mc_ksz8081_data *data) { + const struct device *dev = data->dev; const struct mc_ksz8081_config *config = dev->config; + uint32_t ics; int ret; + + /* Lock mutex */ + ret = k_mutex_lock(&data->mutex, K_FOREVER); + if (ret < 0) { + LOG_ERR("PHY mutex lock error"); + return ret; + } + + /* Read/clear PHY interrupt status register */ + ret = phy_mc_ksz8081_read(dev, PHY_MC_KSZ8081_ICS_REG, &ics); + if (ret < 0) { + LOG_ERR("Error reading phy (%d) interrupt status register", config->addr); + } + + /* Unlock mutex */ + k_mutex_unlock(&data->mutex); + return ret; +} + +static int phy_mc_ksz8081_config_interrupt(const struct device *dev) +{ + struct mc_ksz8081_data *data = dev->data; + uint32_t ics; + int ret; + + /* Read Interrupt Control/Status register to write back */ + ret = phy_mc_ksz8081_read(dev, PHY_MC_KSZ8081_ICS_REG, &ics); + if (ret < 0) { + return ret; + } + ics |= PHY_MC_KSZ8081_ICS_LINK_UP_IE_MASK | PHY_MC_KSZ8081_ICS_LINK_DOWN_IE_MASK; + + /* Write settings to Interrupt Control/Status register */ + ret = phy_mc_ksz8081_write(dev, PHY_MC_KSZ8081_ICS_REG, ics); + if (ret < 0) { + return ret; + } + + /* Clear interrupt */ + ret = phy_mc_ksz8081_clear_interrupt(data); + if (ret < 0) { + return ret; + } + + return ret; +} + +static void phy_mc_ksz8081_interrupt_handler(const struct device *port, struct gpio_callback *cb, + gpio_port_pins_t pins) +{ + struct mc_ksz8081_data *data = CONTAINER_OF(cb, struct mc_ksz8081_data, gpio_callback); + int ret = k_work_reschedule(&data->phy_monitor_work, K_NO_WAIT); + + if (ret < 0) { + LOG_ERR("Failed to schedule monitor_work from ISR"); + } +} +#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */ + +static int phy_mc_ksz8081_autonegotiate(const struct device *dev) +{ + const struct mc_ksz8081_config *config = dev->config; + struct mc_ksz8081_data *data = dev->data; + int ret = 0, attempts = 0; uint32_t bmcr = 0; - uint32_t bmsr = 0; + uint32_t bmsr = 0, last_bmsr = 0; uint16_t timeout = CONFIG_PHY_AUTONEG_TIMEOUT_MS / 100; + ret = k_mutex_lock(&data->mutex, K_FOREVER); + if (ret) { + LOG_ERR("PHY mutex lock error"); + goto done; + } + /* Read control register to write back with autonegotiation bit */ ret = phy_mc_ksz8081_read(dev, MII_BMCR, &bmcr); if (ret) { - LOG_ERR("Error reading phy (%d) basic control register", config->addr); - return ret; + goto done; } /* (re)start autonegotiation */ - LOG_DBG("PHY (%d) is entering autonegotiation sequence", config->addr); + LOG_INF("PHY (%d) is entering autonegotiation sequence", config->addr); bmcr |= MII_BMCR_AUTONEG_ENABLE | MII_BMCR_AUTONEG_RESTART; bmcr &= ~MII_BMCR_ISOLATE; ret = phy_mc_ksz8081_write(dev, MII_BMCR, bmcr); if (ret) { - LOG_ERR("Error writing phy (%d) basic control register", config->addr); - return ret; + goto done; } - /* TODO change this to GPIO interrupt driven */ + data->flags |= KSZ8081_SILENCE_DEBUG_LOGS; do { if (timeout-- == 0) { - LOG_DBG("PHY (%d) autonegotiation timed out", config->addr); + LOG_ERR("PHY (%d) autonegotiation timed out", config->addr); /* The value -ETIMEDOUT can be returned by PHY read/write functions, so * return -ENETDOWN instead to distinguish link timeout from PHY timeout. */ - return -ENETDOWN; + ret = -ENETDOWN; + goto done; } k_msleep(100); ret = phy_mc_ksz8081_read(dev, MII_BMSR, &bmsr); if (ret) { - LOG_ERR("Error reading phy (%d) basic status register", config->addr); - return ret; + goto done; + } + + if (last_bmsr != bmsr) { + LOG_DBG("phy %d autoneg BMSR: %x", config->addr, bmsr); } + + last_bmsr = bmsr; + attempts++; } while (!(bmsr & MII_BMSR_AUTONEG_COMPLETE)); + data->flags &= ~KSZ8081_SILENCE_DEBUG_LOGS; - LOG_DBG("PHY (%d) autonegotiation completed", config->addr); + LOG_DBG("PHY (%d) autonegotiation completed after %d checks", config->addr, attempts); - return 0; + data->flags &= ~KSZ8081_DO_AUTONEG_FLAG; + +done: + if (ret && ret != -ENETDOWN) { + LOG_ERR("Failed to configure %s for autonegotiation", dev->name); + } + /* Unlock mutex */ + k_mutex_unlock(&data->mutex); + return ret; } + static int phy_mc_ksz8081_get_link(const struct device *dev, struct phy_link_state *state) +{ + struct mc_ksz8081_data *data = dev->data; + struct phy_link_state *link_state = &data->state; + + if ((data->flags & KSZ8081_LINK_STATE_VALID) != KSZ8081_LINK_STATE_VALID) { + return -EIO; + } + + state->speed = link_state->speed; + state->is_up = link_state->is_up; + + return 0; +} + +static int phy_mc_ksz8081_update_link(const struct device *dev) { const struct mc_ksz8081_config *config = dev->config; struct mc_ksz8081_data *data = dev->data; + struct phy_link_state *state = &data->state; int ret; uint32_t bmsr = 0; uint32_t anar = 0; @@ -156,14 +292,13 @@ static int phy_mc_ksz8081_get_link(const struct device *dev, /* Lock mutex */ ret = k_mutex_lock(&data->mutex, K_FOREVER); if (ret) { - LOG_ERR("PHY mutex lock error"); + LOG_ERR("PHY %d mutex lock error", config->addr); return ret; } /* Read link state */ ret = phy_mc_ksz8081_read(dev, MII_BMSR, &bmsr); if (ret) { - LOG_ERR("Error reading phy (%d) basic status register", config->addr); goto done; } state->is_up = bmsr & MII_BMSR_LINK_STATUS; @@ -175,14 +310,12 @@ static int phy_mc_ksz8081_get_link(const struct device *dev, /* Read currently configured advertising options */ ret = phy_mc_ksz8081_read(dev, MII_ANAR, &anar); if (ret) { - LOG_ERR("Error reading phy (%d) advertising register", config->addr); goto done; } /* Read link partner capability */ ret = phy_mc_ksz8081_read(dev, MII_ANLPAR, &anlpar); if (ret) { - LOG_ERR("Error reading phy (%d) link partner register", config->addr); goto done; } @@ -211,16 +344,14 @@ static int phy_mc_ksz8081_get_link(const struct device *dev, } done: + if (ret) { + LOG_ERR("Failed to get %s state", dev->name); + } k_mutex_unlock(&data->mutex); return ret; } -/* - * Configuration set statically (DT) that should never change - * This function is needed in case the PHY is reset then the next call - * to configure the phy will ensure this configuration will be redone - */ static int phy_mc_ksz8081_static_cfg(const struct device *dev) { const struct mc_ksz8081_config *config = dev->config; @@ -267,7 +398,7 @@ static int phy_mc_ksz8081_static_cfg(const struct device *dev) } #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) -static int phy_ksz8081_reset_gpio(const struct mc_ksz8081_config *config) +static int phy_mc_ksz8081_reset_gpio(const struct mc_ksz8081_config *config) { int ret; @@ -293,7 +424,7 @@ static int phy_ksz8081_reset_gpio(const struct mc_ksz8081_config *config) return ret; } #else -static int phy_ksz8081_reset_gpio(const struct mc_ksz8081_config *config) +static int phy_mc_ksz8081_reset_gpio(const struct mc_ksz8081_config *config) { ARG_UNUSED(config); @@ -314,7 +445,7 @@ static int phy_mc_ksz8081_reset(const struct device *dev) return ret; } - ret = phy_ksz8081_reset_gpio(config); + ret = phy_mc_ksz8081_reset_gpio(config); if (ret != -ENODEV) { /* On -ENODEV, attempt command-based reset */ goto done; } @@ -329,6 +460,11 @@ static int phy_mc_ksz8081_reset(const struct device *dev) */ k_busy_wait(500 * USEC_PER_MSEC); + /* After each reset we will apply the static cfg from DT */ + ret = phy_mc_ksz8081_static_cfg(dev); + if (ret) { + goto done; + } done: /* Unlock mutex */ k_mutex_unlock(&data->mutex); @@ -338,9 +474,8 @@ static int phy_mc_ksz8081_reset(const struct device *dev) static int phy_mc_ksz8081_cfg_link(const struct device *dev, enum phy_link_speed speeds, enum phy_cfg_link_flag flags) { - const struct mc_ksz8081_config *config = dev->config; + __maybe_unused const struct mc_ksz8081_config *config = dev->config; struct mc_ksz8081_data *data = dev->data; - struct phy_link_state state = {}; int ret; if (flags & PHY_FLAG_AUTO_NEGOTIATION_DISABLED) { @@ -352,12 +487,9 @@ static int phy_mc_ksz8081_cfg_link(const struct device *dev, enum phy_link_speed ret = k_mutex_lock(&data->mutex, K_FOREVER); if (ret) { LOG_ERR("PHY mutex lock error"); - goto done; + return ret; } - /* We are going to reconfigure the phy, don't need to monitor until done */ - k_work_cancel_delayable(&data->phy_monitor_work); - /* DT configurations */ ret = phy_mc_ksz8081_static_cfg(dev); if (ret) { @@ -365,40 +497,25 @@ static int phy_mc_ksz8081_cfg_link(const struct device *dev, enum phy_link_speed } ret = phy_mii_set_anar_reg(dev, speeds); - if ((ret < 0) && (ret != -EALREADY)) { - LOG_ERR("Error setting ANAR register for phy (%d)", config->addr); - goto done; + if (ret == -EALREADY) { + ret = 0; } - - /* (re)do autonegotiation */ - ret = phy_mc_ksz8081_autonegotiate(dev); - if (ret && (ret != -ENETDOWN)) { - LOG_ERR("Error in autonegotiation"); + if (ret < 0) { goto done; } - /* Get link status */ - ret = phy_mc_ksz8081_get_link(dev, &state); - - if (ret == 0 && memcmp(&state, &data->state, sizeof(struct phy_link_state)) != 0) { - memcpy(&data->state, &state, sizeof(struct phy_link_state)); - if (data->cb) { - data->cb(dev, &data->state, data->cb_data); - } - } - - /* Log the results of the configuration */ - LOG_INF("PHY %d is %s", config->addr, data->state.is_up ? "up" : "down"); - if (data->state.is_up) { - LOG_INF("PHY (%d) Link speed %s Mb, %s duplex\n", config->addr, - (PHY_LINK_IS_SPEED_100M(data->state.speed) ? "100" : "10"), - PHY_LINK_IS_FULL_DUPLEX(data->state.speed) ? "full" : "half"); - } - + data->flags |= KSZ8081_DO_AUTONEG_FLAG; done: + if (ret) { + LOG_ERR("Failed to configure %s", dev->name); + } /* Unlock mutex */ k_mutex_unlock(&data->mutex); + if (USING_INTERRUPT_GPIO) { + return ret; + } + /* Start monitoring */ k_work_reschedule(&data->phy_monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD)); @@ -427,22 +544,125 @@ static void phy_mc_ksz8081_monitor_work_handler(struct k_work *work) struct mc_ksz8081_data *data = CONTAINER_OF(dwork, struct mc_ksz8081_data, phy_monitor_work); const struct device *dev = data->dev; - struct phy_link_state state = {}; - int rc; + const struct mc_ksz8081_config *config = dev->config; + struct phy_link_state state = data->state; + bool turn_on_logs = false; + int rc = 0; + + if (USING_INTERRUPT_GPIO) { + rc = phy_mc_ksz8081_clear_interrupt(data); + if (rc < 0) { + return; + } + } - rc = phy_mc_ksz8081_get_link(dev, &state); + if (!data->state.is_up) { + /* some overrides might need set on cold reset way late for some reason */ + phy_mc_ksz8081_static_cfg(dev); + } + /* (re)do autonegotiation if needed */ + if (data->flags & KSZ8081_DO_AUTONEG_FLAG) { + rc = phy_mc_ksz8081_autonegotiate(dev); + } + if (rc && (rc != -ENETDOWN)) { + LOG_ERR("Error in %s autonegotiation", dev->name); + data->flags &= ~KSZ8081_SILENCE_DEBUG_LOGS; /* get logs next time */ + turn_on_logs = true; + } + + data->flags &= ~KSZ8081_LINK_STATE_VALID; + rc = phy_mc_ksz8081_update_link(dev); + if (rc == 0) { + data->flags |= KSZ8081_LINK_STATE_VALID; + } + if (!turn_on_logs) { + turn_on_logs = (rc != 0); + } if (rc == 0 && memcmp(&state, &data->state, sizeof(struct phy_link_state)) != 0) { - memcpy(&data->state, &state, sizeof(struct phy_link_state)); if (data->cb) { data->cb(dev, &data->state, data->cb_data); } + LOG_INF("PHY %d is %s", config->addr, data->state.is_up ? "up" : "down"); + if (data->state.is_up) { + LOG_INF("PHY (%d) Link speed %s Mb, %s duplex\n", config->addr, + (PHY_LINK_IS_SPEED_100M(data->state.speed) ? "100" : "10"), + PHY_LINK_IS_FULL_DUPLEX(data->state.speed) ? "full" : "half"); + } + } + + if (turn_on_logs) { + /* something wrong, if it happens again, we'll get logs next time */ + data->flags &= ~KSZ8081_SILENCE_DEBUG_LOGS; + } else { + /* everything is fine, don't need to spam annoying register logs */ + data->flags |= KSZ8081_SILENCE_DEBUG_LOGS; + } + + if (USING_INTERRUPT_GPIO) { + return; } - /* TODO change this to GPIO interrupt driven */ k_work_reschedule(&data->phy_monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD)); } +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) +static int ksz8081_init_int_gpios(const struct device *dev) +{ + const struct mc_ksz8081_config *config = dev->config; + struct mc_ksz8081_data *data = dev->data; + int ret; + + if (config->interrupt_gpio.port == NULL) { + return 0; + } + + /* Configure interrupt pin */ + ret = gpio_pin_configure_dt(&config->interrupt_gpio, GPIO_INPUT); + if (ret < 0) { + goto done; + } + + gpio_init_callback(&data->gpio_callback, phy_mc_ksz8081_interrupt_handler, + BIT(config->interrupt_gpio.pin)); + + ret = gpio_add_callback_dt(&config->interrupt_gpio, &data->gpio_callback); + if (ret < 0) { + goto done; + } + + ret = phy_mc_ksz8081_config_interrupt(dev); + if (ret < 0) { + goto done; + } + + ret = gpio_pin_interrupt_configure_dt(&config->interrupt_gpio, GPIO_INT_EDGE_TO_ACTIVE); +done: + if (ret < 0) { + LOG_ERR("PHY (%d) config interrupt failed", config->addr); + } + + return ret; +} +#else +#define ksz8081_init_int_gpios(dev) 0 +#endif + +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) +static int ksz8081_init_reset_gpios(const struct device *dev) +{ + const struct mc_ksz8081_config *config = dev->config; + + if (config->reset_gpio.port == NULL) { + return 0; + } + + return gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_ACTIVE); +} +#else +#define ksz8081_init_reset_gpios(dev) 0 +#endif + static int phy_mc_ksz8081_init(const struct device *dev) { const struct mc_ksz8081_config *config = dev->config; @@ -451,35 +671,21 @@ static int phy_mc_ksz8081_init(const struct device *dev) data->dev = dev; + k_busy_wait(100000); + ret = k_mutex_init(&data->mutex); if (ret) { return ret; } mdio_bus_enable(config->mdio_dev); + k_busy_wait(100000); -#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) - if (!config->interrupt_gpio.port) { - goto skip_int_gpio; - } - - /* Prevent NAND TREE mode */ - ret = gpio_pin_configure_dt(&config->interrupt_gpio, GPIO_OUTPUT_ACTIVE); + ret = ksz8081_init_reset_gpios(dev); if (ret) { return ret; } - -skip_int_gpio: -#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */ - -#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) - if (config->reset_gpio.port) { - ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_ACTIVE); - if (ret) { - return ret; - } - } -#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */ + k_busy_wait(100000); /* Reset PHY */ ret = phy_mc_ksz8081_reset(dev); @@ -487,10 +693,17 @@ static int phy_mc_ksz8081_init(const struct device *dev) return ret; } + ret = ksz8081_init_int_gpios(dev); + if (ret < 0) { + return ret; + } + + k_busy_wait(100000); k_work_init_delayable(&data->phy_monitor_work, phy_mc_ksz8081_monitor_work_handler); /* Advertise default speeds */ + k_busy_wait(100000); phy_mc_ksz8081_cfg_link(dev, config->default_speeds, 0); return 0; diff --git a/drivers/ethernet/phy/phy_tja1103.c b/drivers/ethernet/phy/phy_tja1103.c index d80331f5512c9..a297debed1714 100644 --- a/drivers/ethernet/phy/phy_tja1103.c +++ b/drivers/ethernet/phy/phy_tja1103.c @@ -375,7 +375,7 @@ static int phy_tja1103_init(const struct device *dev) return ret; } - /* Check always accesible register for handling NMIs */ + /* Check always accessible register for handling NMIs */ ret = phy_tja1103_c45_read(dev, MDIO_MMD_VENDOR_SPECIFIC1, TJA1103_ALWAYS_ACCESSIBLE, &val); if (ret < 0) { return ret; diff --git a/drivers/firmware/scmi/clk.c b/drivers/firmware/scmi/clk.c index bab5f7b92b649..e47e4efdfda29 100644 --- a/drivers/firmware/scmi/clk.c +++ b/drivers/firmware/scmi/clk.c @@ -110,11 +110,7 @@ int scmi_clock_rate_set(struct scmi_protocol *proto, struct scmi_clock_rate_conf return ret; } - if (status != SCMI_SUCCESS) { - return scmi_status_to_errno(status); - } - - return 0; + return scmi_status_to_errno(status); } int scmi_clock_parent_get(struct scmi_protocol *proto, uint32_t clk_id, uint32_t *parent_id) @@ -190,11 +186,7 @@ int scmi_clock_parent_set(struct scmi_protocol *proto, uint32_t clk_id, uint32_t return ret; } - if (status != SCMI_SUCCESS) { - return scmi_status_to_errno(status); - } - - return 0; + return scmi_status_to_errno(status); } int scmi_clock_config_set(struct scmi_protocol *proto, @@ -244,11 +236,7 @@ int scmi_clock_config_set(struct scmi_protocol *proto, return ret; } - if (status != SCMI_SUCCESS) { - return scmi_status_to_errno(status); - } - - return 0; + return scmi_status_to_errno(status); } int scmi_clock_protocol_attributes(struct scmi_protocol *proto, uint32_t *attributes) diff --git a/drivers/firmware/scmi/nxp/cpu.c b/drivers/firmware/scmi/nxp/cpu.c index 41bc3e6da63b9..babd201a4465b 100644 --- a/drivers/firmware/scmi/nxp/cpu.c +++ b/drivers/firmware/scmi/nxp/cpu.c @@ -45,11 +45,7 @@ int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg) return ret; } - if (status != SCMI_SUCCESS) { - return scmi_status_to_errno(status); - } - - return 0; + return scmi_status_to_errno(status); } int scmi_cpu_pd_lpm_set(struct scmi_cpu_pd_lpm_config *cfg) @@ -84,9 +80,37 @@ int scmi_cpu_pd_lpm_set(struct scmi_cpu_pd_lpm_config *cfg) return ret; } - if (status != SCMI_SUCCESS) { - return scmi_status_to_errno(status); + return scmi_status_to_errno(status); +} + +int scmi_cpu_set_irq_mask(struct scmi_cpu_irq_mask_config *cfg) +{ + struct scmi_protocol *proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_CPU_DOMAIN); + struct scmi_message msg, reply; + int status, ret; + + /* sanity checks */ + if (!proto || !cfg) { + return -EINVAL; + } + + if (proto->id != SCMI_PROTOCOL_CPU_DOMAIN) { + return -EINVAL; + } + + msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CPU_DOMAIN_MSG_CPU_IRQ_WAKE_SET, SCMI_COMMAND, + proto->id, 0x0); + msg.len = sizeof(*cfg); + msg.content = cfg; + + reply.hdr = msg.hdr; + reply.len = sizeof(status); + reply.content = &status; + + ret = scmi_send_message(proto, &msg, &reply, true); + if (ret < 0) { + return ret; } - return 0; + return scmi_status_to_errno(status); } diff --git a/drivers/firmware/scmi/pinctrl.c b/drivers/firmware/scmi/pinctrl.c index 080b96521151b..73ed000daa0ef 100644 --- a/drivers/firmware/scmi/pinctrl.c +++ b/drivers/firmware/scmi/pinctrl.c @@ -59,9 +59,5 @@ int scmi_pinctrl_settings_configure(struct scmi_pinctrl_settings *settings) return ret; } - if (status != SCMI_SUCCESS) { - return scmi_status_to_errno(status); - } - - return 0; + return scmi_status_to_errno(status); } diff --git a/drivers/firmware/scmi/power.c b/drivers/firmware/scmi/power.c index 931abe77d1525..b560ce4845713 100644 --- a/drivers/firmware/scmi/power.c +++ b/drivers/firmware/scmi/power.c @@ -94,9 +94,5 @@ int scmi_power_state_set(struct scmi_power_state_config *cfg) return ret; } - if (status != SCMI_SUCCESS) { - return scmi_status_to_errno(status); - } - - return 0; + return scmi_status_to_errno(status); } diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 95493b13e10bd..2ff0f66a59084 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -41,6 +41,7 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_MSPI_NOR flash_mspi_nor.c) zephyr_library_sources_ifdef(CONFIG_FLASH_NPCX_FIU_NOR flash_npcx_fiu_nor.c) zephyr_library_sources_ifdef(CONFIG_FLASH_NPCX_FIU_QSPI flash_npcx_fiu_qspi.c) zephyr_library_sources_ifdef(CONFIG_FLASH_RENESAS_RA_OSPI_B flash_renesas_ra_ospi_b.c) +zephyr_library_sources_ifdef(CONFIG_FLASH_RENESAS_RA_QSPI flash_renesas_ra_qspi.c) zephyr_library_sources_ifdef(CONFIG_FLASH_RPI_PICO flash_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_FLASH_STM32_OSPI flash_stm32_ospi.c) zephyr_library_sources_ifdef(CONFIG_FLASH_STM32_QSPI flash_stm32_qspi.c) @@ -73,6 +74,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SILABS_SIWX91X soc_flash_silabs_si zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SMARTBOND flash_smartbond.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_TELINK_B91 soc_flash_b91.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_XMC4XXX soc_flash_xmc4xxx.c) +zephyr_library_sources_ifdef(CONFIG_SPI_FLASH_AT25XV021A spi_flash_at25xv021a.c) zephyr_library_sources_ifdef(CONFIG_SPI_FLASH_AT45 spi_flash_at45.c) zephyr_library_sources_ifdef(CONFIG_SPI_NOR spi_nor.c) # zephyr-keep-sorted-stop diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index f3eaeade2257e..17db3c45eeb4c 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -167,6 +167,7 @@ config FLASH_INIT_PRIORITY source "drivers/flash/Kconfig.adi_max32_spixf" source "drivers/flash/Kconfig.ambiq" source "drivers/flash/Kconfig.andes" +source "drivers/flash/Kconfig.at25xv021a" source "drivers/flash/Kconfig.at45" source "drivers/flash/Kconfig.b91" source "drivers/flash/Kconfig.cadence_nand" @@ -195,6 +196,7 @@ source "drivers/flash/Kconfig.numaker_rmc" source "drivers/flash/Kconfig.nxp_s32" source "drivers/flash/Kconfig.renesas_ra" source "drivers/flash/Kconfig.renesas_ra_ospi" +source "drivers/flash/Kconfig.renesas_ra_qspi" source "drivers/flash/Kconfig.renesas_rx" source "drivers/flash/Kconfig.rpi_pico" source "drivers/flash/Kconfig.rts5912" diff --git a/drivers/flash/Kconfig.at25xv021a b/drivers/flash/Kconfig.at25xv021a new file mode 100644 index 0000000000000..01b7b1f2fdf31 --- /dev/null +++ b/drivers/flash/Kconfig.at25xv021a @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Cirrus Logic, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SPI_FLASH_AT25XV021A + bool "Atmel AT25 SPI flash variant" + default y + depends on DT_HAS_ATMEL_AT25XV021A_ENABLED + select FLASH_HAS_DRIVER_ENABLED + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_EXPLICIT_ERASE + select SPI + help + Enable support for AT25XV021A SPI flash variants. + + Vendors that have manufactured such variants include: + - Renesas Electronics + - Adesto Technologies diff --git a/drivers/flash/Kconfig.mspi b/drivers/flash/Kconfig.mspi index 62816845175c4..bc04d37299c96 100644 --- a/drivers/flash/Kconfig.mspi +++ b/drivers/flash/Kconfig.mspi @@ -45,10 +45,29 @@ menuconfig FLASH_MSPI_NOR select FLASH_MSPI select FLASH_HAS_EXPLICIT_ERASE select FLASH_JESD216 - select GPIO if $(dt_compat_any_has_prop,$(DT_COMPAT_JEDEC_MSPI_NOR),reset-gpios) + select GPIO if $(dt_compat_any_has_prop,$(DT_COMPAT_JEDEC_MSPI_NOR),reset-gpios) \ + || $(dt_compat_any_has_prop,$(DT_COMPAT_JEDEC_MSPI_NOR),supply-gpios) if FLASH_MSPI_NOR +config FLASH_MSPI_NOR_USE_SFDP + bool "Use Serial Flash Discoverable Parameters (SFDP)" + default $(dt_compat_any_has_prop,$(DT_COMPAT_JEDEC_MSPI_NOR),sfdp-bfp) + help + Use information from SFDP for setting up flash command transfers + and for configuring the flash chip. + + Currently, only build time processing of SFDP structures is supported, + based on dts arrays provided as flash node properties like `sfdp-bfp`, + `sfdp-ff05`, and `sfdp-ff84`. Depending on the IO mode used, some or + all of these properties are required for building the flash driver. + Data for these properties can be obtained with the `drivers/jesd216` + sample. If a given SFDP table is not available in a flash chip, + the related property can be defined as an empty array - this will + prevent a related build assertion from failing and default values + will be assigned to parameters that would otherwise be read from + that SFDP table. + config FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE int "Page size to use for FLASH_LAYOUT feature" depends on FLASH_PAGE_LAYOUT diff --git a/drivers/flash/Kconfig.nordic_qspi_nor b/drivers/flash/Kconfig.nordic_qspi_nor index 82e1e197e3753..ddd3dd1091d3e 100644 --- a/drivers/flash/Kconfig.nordic_qspi_nor +++ b/drivers/flash/Kconfig.nordic_qspi_nor @@ -61,4 +61,15 @@ config NORDIC_QSPI_NOR_TIMEOUT_MS a flash sector erase. The 500 ms default allows for most typical NOR flash chips to erase a sector. +config NORDIC_QSPI_NOR_ACTIVE_DWELL_MS + int "Dwell period (ms) after last use to stay in active mode" + depends on PM_DEVICE_RUNTIME + default 10 + help + Flash accesses commonly occur in bursts, where entering and exiting DPD + mode between each access adds significantly to the total operation time. + This option controls how long to remain in active mode after each API + call, eliminating the active->idle->active transition sequence if another + transaction occurs before the dwell period expires. + endif # NORDIC_QSPI_NOR diff --git a/drivers/flash/Kconfig.renesas_ra_qspi b/drivers/flash/Kconfig.renesas_ra_qspi new file mode 100644 index 0000000000000..bdc78dca98918 --- /dev/null +++ b/drivers/flash/Kconfig.renesas_ra_qspi @@ -0,0 +1,18 @@ +# Renesas RA Family + +# Copyright (c) 2024-2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config FLASH_RENESAS_RA_QSPI + bool "RA Quad-SPI driver" + default y + depends on DT_HAS_RENESAS_RA_QSPI_NOR_ENABLED + select FLASH_HAS_DRIVER_ENABLED + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_EXPLICIT_ERASE + select USE_RA_FSP_QSPI_NOR_FLASH + select FLASH_HAS_EX_OP + select FLASH_JESD216 + select PINCTRL + help + Enable Quad-SPI Nor flash driver for RA series diff --git a/drivers/flash/Kconfig.stm32_xspi b/drivers/flash/Kconfig.stm32_xspi index 53a3f381af548..3374fec6c604d 100644 --- a/drivers/flash/Kconfig.stm32_xspi +++ b/drivers/flash/Kconfig.stm32_xspi @@ -15,6 +15,7 @@ config FLASH_STM32_XSPI select FLASH_JESD216 select FLASH_PAGE_LAYOUT select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_EXPLICIT_ERASE select PINCTRL select DMA if $(DT_STM32_XSPI_HAS_DMA) select USE_STM32_HAL_DMA if $(DT_STM32_XSPI_HAS_DMA) diff --git a/drivers/flash/flash_esp32.c b/drivers/flash/flash_esp32.c index cb123a3349a8d..f638cbc819bf6 100644 --- a/drivers/flash/flash_esp32.c +++ b/drivers/flash/flash_esp32.c @@ -89,6 +89,10 @@ static int flash_esp32_read(const struct device *dev, off_t address, void *buffe { int ret = 0; + if (length == 0U) { + return 0; + } + #ifdef CONFIG_MCUBOOT uint8_t *dest_ptr = (uint8_t *)buffer; size_t remaining = length; diff --git a/drivers/flash/flash_mspi_nor.c b/drivers/flash/flash_mspi_nor.c index ae22202e075d7..f08f8b68a1d0e 100644 --- a/drivers/flash/flash_mspi_nor.c +++ b/drivers/flash/flash_mspi_nor.c @@ -12,14 +12,34 @@ #include #include "flash_mspi_nor.h" -#include "flash_mspi_nor_quirks.h" +#include "flash_mspi_nor_sfdp.h" LOG_MODULE_REGISTER(flash_mspi_nor, CONFIG_FLASH_LOG_LEVEL); -void flash_mspi_command_set(const struct device *dev, const struct flash_mspi_nor_cmd *cmd) +#define XIP_DEV_CFG_MASK (MSPI_DEVICE_CONFIG_CMD_LEN || \ + MSPI_DEVICE_CONFIG_ADDR_LEN || \ + MSPI_DEVICE_CONFIG_READ_CMD || \ + MSPI_DEVICE_CONFIG_WRITE_CMD || \ + MSPI_DEVICE_CONFIG_RX_DUMMY || \ + MSPI_DEVICE_CONFIG_TX_DUMMY) + +#define NON_XIP_DEV_CFG_MASK (MSPI_DEVICE_CONFIG_ALL & ~XIP_DEV_CFG_MASK) + +static void set_up_xfer(const struct device *dev, enum mspi_xfer_direction dir); +static int perform_xfer(const struct device *dev, + uint8_t cmd, bool mem_access); +static int cmd_rdsr(const struct device *dev, uint8_t op_code, uint8_t *sr); +static int wait_until_ready(const struct device *dev, k_timeout_t poll_period); +static int cmd_wren(const struct device *dev); +static int cmd_wrsr(const struct device *dev, uint8_t op_code, + uint8_t sr_cnt, uint8_t *sr); + +#include "flash_mspi_nor_quirks.h" + +static void set_up_xfer(const struct device *dev, enum mspi_xfer_direction dir) { - struct flash_mspi_nor_data *dev_data = dev->data; const struct flash_mspi_nor_config *dev_config = dev->config; + struct flash_mspi_nor_data *dev_data = dev->data; memset(&dev_data->xfer, 0, sizeof(dev_data->xfer)); memset(&dev_data->packet, 0, sizeof(dev_data->packet)); @@ -29,32 +49,186 @@ void flash_mspi_command_set(const struct device *dev, const struct flash_mspi_no dev_data->xfer.num_packet = 1; dev_data->xfer.timeout = dev_config->transfer_timeout; - dev_data->xfer.cmd_length = cmd->cmd_length; - dev_data->xfer.addr_length = cmd->addr_length; - dev_data->xfer.tx_dummy = (cmd->dir == MSPI_TX) ? - cmd->tx_dummy : dev_config->mspi_nor_cfg.tx_dummy; - dev_data->xfer.rx_dummy = (cmd->dir == MSPI_RX) ? - cmd->rx_dummy : dev_config->mspi_nor_cfg.rx_dummy; + dev_data->packet.dir = dir; +} + +static void set_up_xfer_with_addr(const struct device *dev, + enum mspi_xfer_direction dir, + uint32_t addr) +{ + struct flash_mspi_nor_data *dev_data = dev->data; - dev_data->packet.dir = cmd->dir; - dev_data->packet.cmd = cmd->cmd; + set_up_xfer(dev, dir); + dev_data->xfer.addr_length = dev_data->cmd_info.uses_4byte_addr + ? 4 : 3; + dev_data->packet.address = addr; } -static int dev_cfg_apply(const struct device *dev, const struct mspi_dev_cfg *cfg) +static uint16_t get_extended_command(const struct device *dev, + uint8_t cmd) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + uint8_t cmd_extension = cmd; + + if (dev_data->cmd_info.cmd_extension == CMD_EXTENSION_INVERSE) { + cmd_extension = ~cmd_extension; + } + + return ((uint16_t)cmd << 8) | cmd_extension; +} + +static int perform_xfer(const struct device *dev, + uint8_t cmd, bool mem_access) { const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; + const struct mspi_dev_cfg *cfg = NULL; + int rc; - if (dev_data->curr_cfg == cfg) { - return 0; + if (dev_data->cmd_info.cmd_extension != CMD_EXTENSION_NONE && + dev_data->in_target_io_mode) { + dev_data->xfer.cmd_length = 2; + dev_data->packet.cmd = get_extended_command(dev, cmd); + } else { + dev_data->xfer.cmd_length = 1; + dev_data->packet.cmd = cmd; + } + + if (dev_config->multi_io_cmd || + dev_config->mspi_nor_cfg.io_mode == MSPI_IO_MODE_SINGLE) { + /* If multiple IO lines are used in all the transfer phases + * or in none of them, there's no need to switch the IO mode. + */ + } else if (mem_access) { + /* For commands accessing the flash memory (read and program), + * ensure that the target IO mode is active. + */ + if (!dev_data->in_target_io_mode) { + cfg = &dev_config->mspi_nor_cfg; + } + } else { + /* For all other commands, switch to Single IO mode if a given + * command needs the data or address phase and in the target IO + * mode multiple IO lines are used in these phases. + */ + if (dev_data->in_target_io_mode) { + if (dev_data->packet.num_bytes != 0 || + (dev_data->xfer.addr_length != 0 && + !dev_config->single_io_addr)) { + /* Only the IO mode is to be changed, so the + * initial configuration structure can be used + * for this operation. + */ + cfg = &dev_config->mspi_nor_init_cfg; + } + } } - int rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, - MSPI_DEVICE_CONFIG_ALL, cfg); + if (cfg) { + rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, + MSPI_DEVICE_CONFIG_IO_MODE, cfg); + if (rc < 0) { + LOG_ERR("%s: dev_config() failed: %d", __func__, rc); + return rc; + } + + dev_data->in_target_io_mode = mem_access; + } + + rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, + &dev_data->xfer); if (rc < 0) { - LOG_ERR("Failed to set device config: %p error: %d", cfg, rc); + LOG_ERR("%s: transceive() failed: %d", __func__, rc); + return rc; } - return rc; + + return 0; +} + +static int cmd_rdsr(const struct device *dev, uint8_t op_code, uint8_t *sr) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + int rc; + + set_up_xfer(dev, MSPI_RX); + if (dev_data->in_target_io_mode) { + dev_data->xfer.rx_dummy = dev_data->cmd_info.rdsr_dummy; + dev_data->xfer.addr_length = dev_data->cmd_info.rdsr_addr_4 + ? 4 : 0; + } + dev_data->packet.num_bytes = sizeof(uint8_t); + dev_data->packet.data_buf = sr; + rc = perform_xfer(dev, op_code, false); + if (rc < 0) { + LOG_ERR("%s 0x%02x failed: %d", __func__, op_code, rc); + return rc; + } + + return 0; +} + +static int wait_until_ready(const struct device *dev, k_timeout_t poll_period) +{ + int rc; + uint8_t status_reg; + + while (true) { + rc = cmd_rdsr(dev, SPI_NOR_CMD_RDSR, &status_reg); + if (rc < 0) { + LOG_ERR("%s - status xfer failed: %d", __func__, rc); + return rc; + } + + if (!(status_reg & SPI_NOR_WIP_BIT)) { + break; + } + + k_sleep(poll_period); + } + + return 0; +} + +static int cmd_wren(const struct device *dev) +{ + int rc; + + set_up_xfer(dev, MSPI_TX); + rc = perform_xfer(dev, SPI_NOR_CMD_WREN, false); + if (rc < 0) { + LOG_ERR("%s failed: %d", __func__, rc); + return rc; + } + + return 0; +} + +static int cmd_wrsr(const struct device *dev, uint8_t op_code, + uint8_t sr_cnt, uint8_t *sr) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + int rc; + + rc = cmd_wren(dev); + if (rc < 0) { + return rc; + } + + set_up_xfer(dev, MSPI_TX); + dev_data->packet.num_bytes = sr_cnt; + dev_data->packet.data_buf = sr; + rc = perform_xfer(dev, op_code, false); + if (rc < 0) { + LOG_ERR("%s 0x%02x failed: %d", __func__, op_code, rc); + return rc; + } + + rc = wait_until_ready(dev, K_USEC(1)); + if (rc < 0) { + return rc; + } + + return 0; } static int acquire(const struct device *dev) @@ -69,15 +243,26 @@ static int acquire(const struct device *dev) if (rc < 0) { LOG_ERR("pm_device_runtime_get() failed: %d", rc); } else { + enum mspi_dev_cfg_mask mask; + + if (dev_config->multiperipheral_bus) { + mask = NON_XIP_DEV_CFG_MASK; + } else { + mask = MSPI_DEVICE_CONFIG_NONE; + } + /* This acquires the MSPI controller and reconfigures it * if needed for the flash device. */ rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, - dev_config->mspi_nor_cfg_mask, - &dev_config->mspi_nor_cfg); + mask, &dev_config->mspi_nor_cfg); if (rc < 0) { LOG_ERR("mspi_dev_config() failed: %d", rc); } else { + if (dev_config->multiperipheral_bus) { + dev_data->in_target_io_mode = true; + } + return 0; } @@ -110,13 +295,39 @@ static inline uint32_t dev_flash_size(const struct device *dev) static inline uint16_t dev_page_size(const struct device *dev) { - return SPI_NOR_PAGE_SIZE; + const struct flash_mspi_nor_config *dev_config = dev->config; + + return dev_config->page_size; +} + +static inline +const struct jesd216_erase_type *dev_erase_types(const struct device *dev) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + + return dev_data->erase_types; +} + +static uint8_t get_rx_dummy(const struct device *dev) +{ + const struct flash_mspi_nor_config *dev_config = dev->config; + struct flash_mspi_nor_data *dev_data = dev->data; + + /* If the number of RX dummy cycles is specified in dts, use that value. */ + if (dev_config->rx_dummy_specified) { + return dev_config->mspi_nor_cfg.rx_dummy; + } + + /* Since it's not yet possible to specify mode bits with MSPI API, + * treat mode bit cycles as just dummy. + */ + return dev_data->cmd_info.read_mode_bit_cycles + + dev_data->cmd_info.read_dummy_cycles; } static int api_read(const struct device *dev, off_t addr, void *dest, size_t size) { - const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; const uint32_t flash_size = dev_flash_size(dev); int rc; @@ -134,23 +345,11 @@ static int api_read(const struct device *dev, off_t addr, void *dest, return rc; } - if (dev_config->jedec_cmds->read.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); - } - - if (rc < 0) { - return rc; - } - - /* TODO: get rid of all these hard-coded values for MX25Ux chips */ - flash_mspi_command_set(dev, &dev_config->jedec_cmds->read); - dev_data->packet.address = addr; + set_up_xfer_with_addr(dev, MSPI_RX, addr); + dev_data->xfer.rx_dummy = get_rx_dummy(dev); dev_data->packet.data_buf = dest; dev_data->packet.num_bytes = size; - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); + rc = perform_xfer(dev, dev_data->cmd_info.read_cmd, true); release(dev); @@ -162,85 +361,9 @@ static int api_read(const struct device *dev, off_t addr, void *dest, return 0; } -static int status_get(const struct device *dev, uint8_t *status) -{ - const struct flash_mspi_nor_config *dev_config = dev->config; - struct flash_mspi_nor_data *dev_data = dev->data; - int rc; - - /* Enter command mode */ - if (dev_config->jedec_cmds->status.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); - } - - if (rc < 0) { - LOG_ERR("Switching to dev_cfg failed: %d", rc); - return rc; - } - - flash_mspi_command_set(dev, &dev_config->jedec_cmds->status); - dev_data->packet.data_buf = status; - dev_data->packet.num_bytes = sizeof(uint8_t); - - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); - - if (rc < 0) { - LOG_ERR("Status xfer failed: %d", rc); - return rc; - } - - return rc; -} - -static int wait_until_ready(const struct device *dev, k_timeout_t poll_period) -{ - int rc; - uint8_t status_reg; - - while (true) { - rc = status_get(dev, &status_reg); - - if (rc < 0) { - LOG_ERR("Wait until ready - status xfer failed: %d", rc); - return rc; - } - - if (!(status_reg & SPI_NOR_WIP_BIT)) { - break; - } - - k_sleep(poll_period); - } - - return 0; -} - -static int write_enable(const struct device *dev) -{ - const struct flash_mspi_nor_config *dev_config = dev->config; - struct flash_mspi_nor_data *dev_data = dev->data; - int rc; - - if (dev_config->jedec_cmds->write_en.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); - } - - if (rc < 0) { - return rc; - } - - flash_mspi_command_set(dev, &dev_config->jedec_cmds->write_en); - return mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); -} - static int api_write(const struct device *dev, off_t addr, const void *src, size_t size) { - const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; const uint32_t flash_size = dev_flash_size(dev); const uint16_t page_size = dev_page_size(dev); @@ -265,27 +388,14 @@ static int api_write(const struct device *dev, off_t addr, const void *src, uint16_t page_left = page_size - page_offset; uint16_t to_write = (uint16_t)MIN(size, page_left); - if (write_enable(dev) < 0) { - LOG_ERR("Write enable xfer failed: %d", rc); + if (cmd_wren(dev) < 0) { break; } - if (dev_config->jedec_cmds->page_program.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); - } - - if (rc < 0) { - return rc; - } - - flash_mspi_command_set(dev, &dev_config->jedec_cmds->page_program); - dev_data->packet.address = addr; + set_up_xfer_with_addr(dev, MSPI_TX, addr); dev_data->packet.data_buf = (uint8_t *)src; dev_data->packet.num_bytes = to_write; - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); + rc = perform_xfer(dev, dev_data->cmd_info.pp_cmd, true); if (rc < 0) { LOG_ERR("Page program xfer failed: %d", rc); break; @@ -306,9 +416,28 @@ static int api_write(const struct device *dev, off_t addr, const void *src, return rc; } +static const struct jesd216_erase_type *find_best_erase_type( + const struct device *dev, off_t addr, size_t size) +{ + const struct jesd216_erase_type *erase_types = dev_erase_types(dev); + const struct jesd216_erase_type *best_et = NULL; + + for (int i = 0; i < JESD216_NUM_ERASE_TYPES; ++i) { + const struct jesd216_erase_type *et = &erase_types[i]; + + if ((et->exp != 0) + && SPI_NOR_IS_ALIGNED(addr, et->exp) + && (size >= BIT(et->exp)) + && ((best_et == NULL) || (et->exp > best_et->exp))) { + best_et = et; + } + } + + return best_et; +} + static int api_erase(const struct device *dev, off_t addr, size_t size) { - const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; const uint32_t flash_size = dev_flash_size(dev); int rc = 0; @@ -331,45 +460,33 @@ static int api_erase(const struct device *dev, off_t addr, size_t size) } while (size > 0) { - rc = write_enable(dev); - if (rc < 0) { - LOG_ERR("Write enable failed."); + if (cmd_wren(dev) < 0) { break; } if (size == flash_size) { /* Chip erase. */ - if (dev_config->jedec_cmds->chip_erase.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); - } - - if (rc < 0) { - return rc; - } + set_up_xfer(dev, MSPI_TX); + rc = perform_xfer(dev, SPI_NOR_CMD_CE, false); - flash_mspi_command_set(dev, &dev_config->jedec_cmds->chip_erase); size -= flash_size; } else { - /* Sector erase. */ - if (dev_config->jedec_cmds->sector_erase.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); - } + const struct jesd216_erase_type *best_et = + find_best_erase_type(dev, addr, size); - if (rc < 0) { - return rc; - } + if (best_et != NULL) { + set_up_xfer_with_addr(dev, MSPI_TX, addr); + rc = perform_xfer(dev, best_et->cmd, false); - flash_mspi_command_set(dev, &dev_config->jedec_cmds->sector_erase); - dev_data->packet.address = addr; - addr += SPI_NOR_SECTOR_SIZE; - size -= SPI_NOR_SECTOR_SIZE; + addr += BIT(best_et->exp); + size -= BIT(best_et->exp); + } else { + LOG_ERR("Can't erase %zu at 0x%lx", + size, (long)addr); + rc = -EINVAL; + break; + } } - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); if (rc < 0) { LOG_ERR("Erase command 0x%02x xfer failed: %d", dev_data->packet.cmd, rc); @@ -387,6 +504,12 @@ static int api_erase(const struct device *dev, off_t addr, size_t size) return rc; } +static int api_get_size(const struct device *dev, uint64_t *size) +{ + *size = dev_flash_size(dev); + return 0; +} + static const struct flash_parameters *api_get_parameters(const struct device *dev) { @@ -400,30 +523,49 @@ struct flash_parameters *api_get_parameters(const struct device *dev) return ¶meters; } -static int read_jedec_id(const struct device *dev, uint8_t *id) +static int sfdp_read(const struct device *dev, off_t addr, void *dest, + size_t size) { - const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; int rc; - if (dev_config->jedec_cmds->id.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); + set_up_xfer(dev, MSPI_RX); + if (dev_data->in_target_io_mode) { + dev_data->xfer.rx_dummy = dev_data->cmd_info.sfdp_dummy_20 + ? 20 : 8; + dev_data->xfer.addr_length = dev_data->cmd_info.sfdp_addr_4 + ? 4 : 3; } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); + dev_data->xfer.rx_dummy = 8; + dev_data->xfer.addr_length = 3; } - + dev_data->packet.address = addr; + dev_data->packet.data_buf = dest; + dev_data->packet.num_bytes = size; + rc = perform_xfer(dev, JESD216_CMD_READ_SFDP, false); if (rc < 0) { - return rc; + LOG_ERR("Read SFDP xfer failed: %d", rc); } - flash_mspi_command_set(dev, &dev_config->jedec_cmds->id); + return rc; +} + +static int read_jedec_id(const struct device *dev, uint8_t *id) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + int rc; + + set_up_xfer(dev, MSPI_RX); + if (dev_data->in_target_io_mode) { + dev_data->xfer.rx_dummy = dev_data->cmd_info.rdid_dummy; + dev_data->xfer.addr_length = dev_data->cmd_info.rdid_addr_4 + ? 4 : 0; + } dev_data->packet.data_buf = id; dev_data->packet.num_bytes = JESD216_READ_ID_LEN; - - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); + rc = perform_xfer(dev, SPI_NOR_CMD_RDID, false); if (rc < 0) { - LOG_ERR("Read JEDEC ID failed: %d\n", rc); + LOG_ERR("Read JEDEC ID failed: %d", rc); } return rc; @@ -445,8 +587,6 @@ static void api_page_layout(const struct device *dev, static int api_sfdp_read(const struct device *dev, off_t addr, void *dest, size_t size) { - const struct flash_mspi_nor_config *dev_config = dev->config; - struct flash_mspi_nor_data *dev_data = dev->data; int rc; if (size == 0) { @@ -458,26 +598,7 @@ static int api_sfdp_read(const struct device *dev, off_t addr, void *dest, return rc; } - if (dev_config->jedec_cmds->sfdp.force_single) { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - } else { - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); - } - - if (rc < 0) { - return rc; - } - - flash_mspi_command_set(dev, &dev_config->jedec_cmds->sfdp); - dev_data->packet.address = addr; - dev_data->packet.data_buf = dest; - dev_data->packet.num_bytes = size; - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); - if (rc < 0) { - printk("Read SFDP xfer failed: %d\n", rc); - return rc; - } + rc = sfdp_read(dev, addr, dest, size); release(dev); @@ -516,84 +637,238 @@ static int dev_pm_action_cb(const struct device *dev, static int quad_enable_set(const struct device *dev, bool enable) { - const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; + uint8_t op_code; + uint8_t qe_bit; + uint8_t status_reg; + uint8_t payload_len; + uint8_t payload[2]; int rc; - flash_mspi_command_set(dev, &commands_single.write_en); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); + switch (dev_data->switch_info.quad_enable_req) { + case JESD216_DW15_QER_VAL_S1B6: + op_code = SPI_NOR_CMD_RDSR; + qe_bit = BIT(6); + break; + case JESD216_DW15_QER_VAL_S2B7: + /* Use special Read status register 2 instruction. */ + op_code = 0x3F; + qe_bit = BIT(7); + break; + case JESD216_DW15_QER_VAL_S2B1v1: + case JESD216_DW15_QER_VAL_S2B1v4: + case JESD216_DW15_QER_VAL_S2B1v5: + case JESD216_DW15_QER_VAL_S2B1v6: + op_code = SPI_NOR_CMD_RDSR2; + qe_bit = BIT(1); + break; + default: + LOG_ERR("Unknown Quad Enable Requirement: %u", + dev_data->switch_info.quad_enable_req); + return -ENOTSUP; + } + + rc = cmd_rdsr(dev, op_code, &status_reg); if (rc < 0) { - LOG_ERR("Failed to set write enable: %d", rc); return rc; } - if (dev_config->dw15_qer == JESD216_DW15_QER_VAL_S1B6) { - const struct flash_mspi_nor_cmd cmd_status = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_WRSR, - .cmd_length = 1, - }; - uint8_t mode_payload = enable ? BIT(6) : 0; + if (((status_reg & qe_bit) != 0) == enable) { + /* Nothing to do, the QE bit is already set properly. */ + return 0; + } - flash_mspi_command_set(dev, &cmd_status); - dev_data->packet.data_buf = &mode_payload; - dev_data->packet.num_bytes = sizeof(mode_payload); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); + status_reg ^= qe_bit; + + switch (dev_data->switch_info.quad_enable_req) { + default: + case JESD216_DW15_QER_VAL_S1B6: + payload_len = 1; + op_code = SPI_NOR_CMD_WRSR; + break; + case JESD216_DW15_QER_VAL_S2B7: + payload_len = 1; + /* Use special Write status register 2 instruction. */ + op_code = 0x3E; + break; + case JESD216_DW15_QER_VAL_S2B1v1: + case JESD216_DW15_QER_VAL_S2B1v4: + case JESD216_DW15_QER_VAL_S2B1v5: + payload_len = 2; + op_code = SPI_NOR_CMD_WRSR; + break; + case JESD216_DW15_QER_VAL_S2B1v6: + payload_len = 1; + op_code = SPI_NOR_CMD_WRSR2; + break; + } + + if (payload_len == 1) { + payload[0] = status_reg; + } else { + payload[1] = status_reg; + /* When the Write Status command is to be sent with two data + * bytes (this is the case for S2B1v1, S2B1v4, and S2B1v5 QER + * values), the first status register needs to be read and + * sent as the first byte, so that its value is not modified. + */ + rc = cmd_rdsr(dev, SPI_NOR_CMD_RDSR, &payload[0]); if (rc < 0) { - LOG_ERR("Failed to enable/disable quad mode: %d", rc); return rc; } - } else { - /* TODO: handle all DW15 QER values */ + } + + rc = cmd_wrsr(dev, op_code, payload_len, payload); + if (rc < 0) { + return rc; + } + + return 0; +} + +static int octal_enable_set(const struct device *dev, bool enable) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + uint8_t op_code; + uint8_t oe_bit; + uint8_t status_reg; + int rc; + + if (dev_data->switch_info.octal_enable_req != OCTAL_ENABLE_REQ_S2B3) { + LOG_ERR("Unknown Octal Enable Requirement: %u", + dev_data->switch_info.octal_enable_req); return -ENOTSUP; } - rc = wait_until_ready(dev, K_USEC(1)); + oe_bit = BIT(3); + /* Use special Read status register 2 instruction 0x65 with one address + * byte 0x02 and one dummy byte. + */ + op_code = 0x65; + set_up_xfer(dev, MSPI_RX); + dev_data->xfer.rx_dummy = 8; + dev_data->xfer.addr_length = 1; + dev_data->packet.address = 0x02; + dev_data->packet.num_bytes = sizeof(uint8_t); + dev_data->packet.data_buf = &status_reg; + rc = perform_xfer(dev, op_code, false); + if (rc < 0) { + LOG_ERR("cmd_rdsr 0x%02x failed: %d", op_code, rc); + return rc; + } + + if (((status_reg & oe_bit) != 0) == enable) { + /* Nothing to do, the OE bit is already set properly. */ + return 0; + } + + status_reg ^= oe_bit; + + /* Use special Write status register 2 instruction to clear the bit. */ + op_code = (status_reg & oe_bit) ? SPI_NOR_CMD_WRSR2 : 0x3E; + rc = cmd_wrsr(dev, op_code, 1, &status_reg); if (rc < 0) { - LOG_ERR("Failed waiting until device ready after enabling quad: %d", rc); return rc; } return 0; } +static int enter_4byte_addressing_mode(const struct device *dev) +{ + struct flash_mspi_nor_data *dev_data = dev->data; + int rc; + + if (dev_data->switch_info.enter_4byte_addr == ENTER_4BYTE_ADDR_06_B7) { + rc = cmd_wren(dev); + if (rc < 0) { + return rc; + } + } -static int default_io_mode(const struct device *dev) + set_up_xfer(dev, MSPI_TX); + rc = perform_xfer(dev, 0xB7, false); + if (rc < 0) { + LOG_ERR("Command 0xB7 failed: %d", rc); + return rc; + } + + return 0; +} + +static int switch_to_target_io_mode(const struct device *dev) { const struct flash_mspi_nor_config *dev_config = dev->config; + struct flash_mspi_nor_data *dev_data = dev->data; enum mspi_io_mode io_mode = dev_config->mspi_nor_cfg.io_mode; int rc = 0; - if (dev_config->dw15_qer != JESD216_DW15_QER_VAL_NONE) { - /* For Quad 1-1-4 and 1-4-4, entering or leaving mode is defined - * in JEDEC216 BFP DW15 QER - */ - if (io_mode == MSPI_IO_MODE_SINGLE) { - rc = quad_enable_set(dev, false); - } else if (io_mode == MSPI_IO_MODE_QUAD_1_1_4 || - io_mode == MSPI_IO_MODE_QUAD_1_4_4) { - rc = quad_enable_set(dev, true); - } + if (dev_data->switch_info.quad_enable_req != JESD216_DW15_QER_VAL_NONE) { + bool quad_needed = io_mode == MSPI_IO_MODE_QUAD_1_1_4 || + io_mode == MSPI_IO_MODE_QUAD_1_4_4; + rc = quad_enable_set(dev, quad_needed); if (rc < 0) { LOG_ERR("Failed to modify Quad Enable bit: %d", rc); + return rc; + } + } + + if (dev_data->switch_info.octal_enable_req != OCTAL_ENABLE_REQ_NONE) { + bool octal_needed = io_mode == MSPI_IO_MODE_OCTAL_1_1_8 || + io_mode == MSPI_IO_MODE_OCTAL_1_8_8; + + rc = octal_enable_set(dev, octal_needed); + if (rc < 0) { + LOG_ERR("Failed to modify Octal Enable bit: %d", rc); + return rc; } } - if ((dev_config->quirks != NULL) && (dev_config->quirks->post_switch_mode != NULL)) { + if (dev_data->switch_info.enter_4byte_addr != ENTER_4BYTE_ADDR_NONE) { + rc = enter_4byte_addressing_mode(dev); + if (rc < 0) { + LOG_ERR("Failed to enter 4-byte addressing mode: %d", rc); + return rc; + } + } + + if (dev_config->quirks != NULL && + dev_config->quirks->post_switch_mode != NULL) { rc = dev_config->quirks->post_switch_mode(dev); + if (rc < 0) { + return rc; + } } + return mspi_dev_config(dev_config->bus, &dev_config->mspi_id, + NON_XIP_DEV_CFG_MASK, + &dev_config->mspi_nor_cfg); +} + +#if defined(WITH_SUPPLY_GPIO) +static int power_supply(const struct device *dev) +{ + const struct flash_mspi_nor_config *dev_config = dev->config; + int rc; + + if (!gpio_is_ready_dt(&dev_config->supply)) { + LOG_ERR("Device %s is not ready", + dev_config->supply.port->name); + return -ENODEV; + } + + rc = gpio_pin_configure_dt(&dev_config->supply, GPIO_OUTPUT_ACTIVE); if (rc < 0) { - LOG_ERR("Failed to change IO mode: %d\n", rc); - return rc; + LOG_ERR("Failed to activate power supply GPIO: %d", rc); + return -EIO; } - return dev_cfg_apply(dev, &dev_config->mspi_nor_cfg); + return 0; } +#endif #if defined(WITH_RESET_GPIO) static int gpio_reset(const struct device *dev) @@ -601,129 +876,269 @@ static int gpio_reset(const struct device *dev) const struct flash_mspi_nor_config *dev_config = dev->config; int rc; - if (dev_config->reset.port) { - if (!gpio_is_ready_dt(&dev_config->reset)) { - LOG_ERR("Device %s is not ready", - dev_config->reset.port->name); - return -ENODEV; - } + if (!gpio_is_ready_dt(&dev_config->reset)) { + LOG_ERR("Device %s is not ready", + dev_config->reset.port->name); + return -ENODEV; + } + + rc = gpio_pin_configure_dt(&dev_config->reset, GPIO_OUTPUT_ACTIVE); + if (rc < 0) { + LOG_ERR("Failed to activate RESET: %d", rc); + return -EIO; + } + + if (dev_config->reset_pulse_us != 0) { + k_busy_wait(dev_config->reset_pulse_us); + } + + rc = gpio_pin_set_dt(&dev_config->reset, 0); + if (rc < 0) { + LOG_ERR("Failed to deactivate RESET: %d", rc); + return -EIO; + } + + return 0; +} +#endif - rc = gpio_pin_configure_dt(&dev_config->reset, - GPIO_OUTPUT_ACTIVE); +#if defined(WITH_SOFT_RESET) +static int soft_reset_66_99(const struct device *dev) +{ + int rc; + + set_up_xfer(dev, MSPI_TX); + rc = perform_xfer(dev, SPI_NOR_CMD_RESET_EN, false); + if (rc < 0) { + LOG_ERR("CMD_RESET_EN failed: %d", rc); + return rc; + } + + set_up_xfer(dev, MSPI_TX); + rc = perform_xfer(dev, SPI_NOR_CMD_RESET_MEM, false); + if (rc < 0) { + LOG_ERR("CMD_RESET_MEM failed: %d", rc); + return rc; + } + + return 0; +} + +static int soft_reset(const struct device *dev) +{ + const struct flash_mspi_nor_config *dev_config = dev->config; + struct flash_mspi_nor_data *dev_data = dev->data; + int rc; + + /* If the flash may expect commands sent in multi-line mode, + * send additionally the reset sequence this way. + */ + if (dev_config->multi_io_cmd) { + rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, + MSPI_DEVICE_CONFIG_IO_MODE, + &dev_config->mspi_nor_cfg); if (rc < 0) { - LOG_ERR("Failed to activate RESET: %d", rc); - return -EIO; + LOG_ERR("%s: dev_config() failed: %d", __func__, rc); + return rc; } - if (dev_config->reset_pulse_us != 0) { - k_busy_wait(dev_config->reset_pulse_us); - } + dev_data->in_target_io_mode = true; - rc = gpio_pin_set_dt(&dev_config->reset, 0); + rc = soft_reset_66_99(dev); if (rc < 0) { - LOG_ERR("Failed to deactivate RESET: %d", rc); - return -EIO; + return rc; } - if (dev_config->reset_recovery_us != 0) { - k_busy_wait(dev_config->reset_recovery_us); + rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, + MSPI_DEVICE_CONFIG_IO_MODE, + &dev_config->mspi_nor_init_cfg); + if (rc < 0) { + LOG_ERR("%s: dev_config() failed: %d", __func__, rc); + return rc; } + + dev_data->in_target_io_mode = false; + } + + rc = soft_reset_66_99(dev); + if (rc < 0) { + return rc; } return 0; } -#endif +#endif /* WITH_SOFT_RESET */ static int flash_chip_init(const struct device *dev) { const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; - enum mspi_io_mode io_mode = dev_config->mspi_nor_cfg.io_mode; uint8_t id[JESD216_READ_ID_LEN] = {0}; + uint16_t dts_cmd = 0; + uint32_t sfdp_signature; + bool flash_reset = false; int rc; - rc = dev_cfg_apply(dev, &dev_config->mspi_nor_init_cfg); - + rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, + MSPI_DEVICE_CONFIG_ALL, + &dev_config->mspi_nor_init_cfg); if (rc < 0) { + LOG_ERR("%s: dev_config() failed: %d", __func__, rc); return rc; } - /* Some chips reuse RESET pin for data in Quad modes: - * force single line mode before resetting. - */ - if (dev_config->dw15_qer != JESD216_DW15_QER_VAL_NONE && - (io_mode == MSPI_IO_MODE_SINGLE || - io_mode == MSPI_IO_MODE_QUAD_1_1_4 || - io_mode == MSPI_IO_MODE_QUAD_1_4_4)) { - rc = quad_enable_set(dev, false); + dev_data->in_target_io_mode = false; +#if defined(WITH_SUPPLY_GPIO) + if (dev_config->supply.port) { + rc = power_supply(dev); if (rc < 0) { - LOG_ERR("Failed to switch to single line mode: %d", rc); return rc; } - rc = wait_until_ready(dev, K_USEC(1)); + flash_reset = true; + } +#endif +#if defined(WITH_RESET_GPIO) + if (dev_config->reset.port) { + rc = gpio_reset(dev); if (rc < 0) { - LOG_ERR("Failed waiting for device after switch to single line: %d", rc); return rc; } + + flash_reset = true; } +#endif -#if defined(WITH_RESET_GPIO) - rc = gpio_reset(dev); +#if defined(WITH_SOFT_RESET) + if (dev_config->initial_soft_reset) { + rc = soft_reset(dev); + if (rc < 0) { + return rc; + } - if (rc < 0) { - LOG_ERR("Failed to reset with GPIO: %d", rc); - return rc; + flash_reset = true; } #endif - flash_mspi_command_set(dev, &commands_single.id); - dev_data->packet.data_buf = id; - dev_data->packet.num_bytes = sizeof(id); + if (flash_reset && dev_config->reset_recovery_us != 0) { + k_busy_wait(dev_config->reset_recovery_us); + } - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); - if (rc < 0) { - LOG_ERR("Failed to read JEDEC ID in initial line mode: %d", rc); - return rc; + if (dev_config->quirks != NULL && + dev_config->quirks->pre_init != NULL) { + rc = dev_config->quirks->pre_init(dev); + } + + /* Allow users to specify commands for Read and Page Program operations + * through dts to override what was taken from SFDP and perhaps altered + * in the pre_init quirk. Also the number of dummy cycles for the Read + * operation can be overridden this way, see get_rx_dummy(). + */ + if (dev_config->mspi_nor_cfg.read_cmd != 0) { + dts_cmd = (uint16_t)dev_config->mspi_nor_cfg.read_cmd; + if (dev_config->mspi_nor_cfg.cmd_length > 1) { + dev_data->cmd_info.read_cmd = (uint8_t)(dts_cmd >> 8); + } else { + dev_data->cmd_info.read_cmd = (uint8_t)dts_cmd; + } + } + if (dev_config->mspi_nor_cfg.write_cmd != 0) { + dts_cmd = (uint16_t)dev_config->mspi_nor_cfg.write_cmd; + if (dev_config->mspi_nor_cfg.cmd_length > 1) { + dev_data->cmd_info.pp_cmd = (uint8_t)(dts_cmd >> 8); + } else { + dev_data->cmd_info.pp_cmd = (uint8_t)dts_cmd; + } + } + if (dts_cmd != 0) { + if (dev_config->mspi_nor_cfg.cmd_length <= 1) { + dev_data->cmd_info.cmd_extension = CMD_EXTENSION_NONE; + } else if ((dts_cmd & 0xFF) == ((dts_cmd >> 8) & 0xFF)) { + dev_data->cmd_info.cmd_extension = CMD_EXTENSION_SAME; + } else { + dev_data->cmd_info.cmd_extension = CMD_EXTENSION_INVERSE; + } } - rc = default_io_mode(dev); + if (dev_config->jedec_id_specified) { + rc = read_jedec_id(dev, id); + if (rc < 0) { + LOG_ERR("Failed to read JEDEC ID: %d", rc); + return rc; + } + if (memcmp(id, dev_config->jedec_id, sizeof(id)) != 0) { + LOG_ERR("JEDEC ID mismatch, read: %02x %02x %02x, " + "expected: %02x %02x %02x", + id[0], id[1], id[2], + dev_config->jedec_id[0], + dev_config->jedec_id[1], + dev_config->jedec_id[2]); + return -ENODEV; + } + } + + rc = switch_to_target_io_mode(dev); if (rc < 0) { - LOG_ERR("Failed to switch to default io mode: %d", rc); + LOG_ERR("Failed to switch to target io mode: %d", rc); return rc; } - /* Reading JEDEC ID for mode that forces single lane would be redundant, - * since it switches back to single lane mode. Use ID from previous read. - */ - if (!dev_config->jedec_cmds->id.force_single) { - rc = read_jedec_id(dev, id); + dev_data->in_target_io_mode = true; + + if (IS_ENABLED(CONFIG_FLASH_MSPI_NOR_USE_SFDP)) { + /* Read the SFDP signature to test if communication with + * the flash chip can be successfully performed after switching + * to target IO mode. + */ + rc = sfdp_read(dev, 0, &sfdp_signature, sizeof(sfdp_signature)); if (rc < 0) { - LOG_ERR("Failed to read JEDEC ID in final line mode: %d", rc); + LOG_ERR("Failed to read SFDP signature: %d", rc); return rc; } - } - if (memcmp(id, dev_config->jedec_id, sizeof(id)) != 0) { - LOG_ERR("JEDEC ID mismatch, read: %02x %02x %02x, " - "expected: %02x %02x %02x", - id[0], id[1], id[2], - dev_config->jedec_id[0], - dev_config->jedec_id[1], - dev_config->jedec_id[2]); - return -ENODEV; + if (sfdp_signature != JESD216_SFDP_MAGIC) { + LOG_ERR("SFDP signature mismatch: %08x, expected: %08x", + sfdp_signature, JESD216_SFDP_MAGIC); + return -ENODEV; + } } #if defined(CONFIG_MSPI_XIP) /* Enable XIP access for this chip if specified so in DT. */ if (dev_config->xip_cfg.enable) { + struct mspi_dev_cfg mspi_cfg = { + .addr_length = dev_data->cmd_info.uses_4byte_addr + ? 4 : 3, + .rx_dummy = get_rx_dummy(dev), + }; + + if (dev_data->cmd_info.cmd_extension != CMD_EXTENSION_NONE) { + mspi_cfg.cmd_length = 2; + mspi_cfg.read_cmd = get_extended_command(dev, + dev_data->cmd_info.read_cmd); + mspi_cfg.write_cmd = get_extended_command(dev, + dev_data->cmd_info.pp_cmd); + } else { + mspi_cfg.cmd_length = 1; + mspi_cfg.read_cmd = dev_data->cmd_info.read_cmd; + mspi_cfg.write_cmd = dev_data->cmd_info.pp_cmd; + } + + rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id, + XIP_DEV_CFG_MASK, &mspi_cfg); + if (rc < 0) { + LOG_ERR("Failed to configure controller for XIP: %d", + rc); + return rc; + } + rc = mspi_xip_config(dev_config->bus, &dev_config->mspi_id, &dev_config->xip_cfg); if (rc < 0) { + LOG_ERR("Failed to enable XIP: %d", rc); return rc; } } @@ -743,6 +1158,11 @@ static int drv_init(const struct device *dev) return -ENODEV; } + memcpy(dev_data->erase_types, dev_config->default_erase_types, + sizeof(dev_data->erase_types)); + dev_data->cmd_info = dev_config->default_cmd_info; + dev_data->switch_info = dev_config->default_switch_info; + rc = pm_device_runtime_get(dev_config->bus); if (rc < 0) { LOG_ERR("pm_device_runtime_get() failed: %d", rc); @@ -762,6 +1182,39 @@ static int drv_init(const struct device *dev) return rc; } + if (dev_data->cmd_info.read_cmd == 0) { + LOG_ERR("Read command not defined for %s, " + "use \"read-command\" property to specify it.", + dev->name); + return -EINVAL; + } + + if (dev_data->cmd_info.pp_cmd == 0) { + LOG_ERR("Page Program command not defined for %s, " + "use \"write-command\" property to specify it.", + dev->name); + return -EINVAL; + } + + LOG_DBG("%s - size: %u, page %u%s", + dev->name, dev_flash_size(dev), dev_page_size(dev), + dev_data->cmd_info.uses_4byte_addr ? ", 4-byte addressing" : ""); + LOG_DBG("- read command: 0x%02X with %u mode bit and %u dummy cycles", + dev_data->cmd_info.read_cmd, + dev_data->cmd_info.read_mode_bit_cycles, + dev_data->cmd_info.read_dummy_cycles); + LOG_DBG("- page program command: 0x%02X", + dev_data->cmd_info.pp_cmd); + LOG_DBG("- erase types:"); + for (int i = 0; i < JESD216_NUM_ERASE_TYPES; ++i) { + const struct jesd216_erase_type *et = &dev_erase_types(dev)[i]; + + if (et->exp != 0) { + LOG_DBG(" - command: 0x%02X, size: %lu", + et->cmd, BIT(et->exp)); + } + } + k_sem_init(&dev_data->acquired, 1, K_SEM_MAX_LIMIT); return pm_device_driver_init(dev, dev_pm_action_cb); @@ -771,6 +1224,7 @@ static DEVICE_API(flash, drv_api) = { .read = api_read, .write = api_write, .erase = api_erase, + .get_size = api_get_size, .get_parameters = api_get_parameters, #if defined(CONFIG_FLASH_PAGE_LAYOUT) .page_layout = api_page_layout, @@ -793,47 +1247,18 @@ static DEVICE_API(flash, drv_api) = { .dqs_enable = false, \ } -#define FLASH_SIZE_INST(inst) (DT_INST_PROP(inst, size) / 8) - -/* Define copies of mspi_io_mode enum values, so they can be used inside - * the COND_CODE_1 macros. - */ -#define _MSPI_IO_MODE_SINGLE 0 -#define _MSPI_IO_MODE_QUAD_1_4_4 6 -#define _MSPI_IO_MODE_OCTAL 7 -BUILD_ASSERT(_MSPI_IO_MODE_SINGLE == MSPI_IO_MODE_SINGLE, - "Please align _MSPI_IO_MODE_SINGLE macro value"); -BUILD_ASSERT(_MSPI_IO_MODE_QUAD_1_4_4 == MSPI_IO_MODE_QUAD_1_4_4, - "Please align _MSPI_IO_MODE_QUAD_1_4_4 macro value"); -BUILD_ASSERT(_MSPI_IO_MODE_OCTAL == MSPI_IO_MODE_OCTAL, - "Please align _MSPI_IO_MODE_OCTAL macro value"); - -/* Define a non-existing extern symbol to get an understandable compile-time error - * if the IO mode is not supported by the driver. - */ -extern const struct flash_mspi_nor_cmds mspi_io_mode_not_supported; - -#define FLASH_CMDS(inst) COND_CODE_1( \ - IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_SINGLE), \ - (&commands_single), \ - (COND_CODE_1( \ - IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_QUAD_1_4_4), \ - (&commands_quad_1_4_4), \ - (COND_CODE_1( \ - IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_OCTAL), \ - (&commands_octal), \ - (&mspi_io_mode_not_supported) \ - )) \ - )) \ -) - #define FLASH_QUIRKS(inst) FLASH_MSPI_QUIRKS_GET(DT_DRV_INST(inst)) -#define FLASH_DW15_QER_VAL(inst) _CONCAT(JESD216_DW15_QER_VAL_, \ - DT_INST_STRING_TOKEN(inst, quad_enable_requirements)) -#define FLASH_DW15_QER(inst) COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, quad_enable_requirements), \ - (FLASH_DW15_QER_VAL(inst)), (JESD216_DW15_QER_VAL_NONE)) - +#define IO_MODE_FLAGS(io_mode) \ + .multi_io_cmd = (io_mode == MSPI_IO_MODE_DUAL || \ + io_mode == MSPI_IO_MODE_QUAD || \ + io_mode == MSPI_IO_MODE_OCTAL || \ + io_mode == MSPI_IO_MODE_HEX || \ + io_mode == MSPI_IO_MODE_HEX_8_8_16 || \ + io_mode == MSPI_IO_MODE_HEX_8_16_16), \ + .single_io_addr = (io_mode == MSPI_IO_MODE_DUAL_1_1_2 || \ + io_mode == MSPI_IO_MODE_QUAD_1_1_4 || \ + io_mode == MSPI_IO_MODE_OCTAL_1_1_8) #if defined(CONFIG_FLASH_PAGE_LAYOUT) BUILD_ASSERT((CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE % 4096) == 0, @@ -841,11 +1266,11 @@ BUILD_ASSERT((CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE % 4096) == 0, #define FLASH_PAGE_LAYOUT_DEFINE(inst) \ .layout = { \ .pages_size = CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE, \ - .pages_count = FLASH_SIZE_INST(inst) \ + .pages_count = FLASH_SIZE(inst) \ / CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE, \ }, #define FLASH_PAGE_LAYOUT_CHECK(inst) \ -BUILD_ASSERT((FLASH_SIZE_INST(inst) % CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE) == 0, \ +BUILD_ASSERT((FLASH_SIZE(inst) % CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE) == 0, \ "MSPI_NOR_FLASH_LAYOUT_PAGE_SIZE incompatible with flash size, instance " #inst); #else #define FLASH_PAGE_LAYOUT_DEFINE(inst) @@ -860,39 +1285,40 @@ BUILD_ASSERT((FLASH_SIZE_INST(inst) % CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE) == #endif #define FLASH_MSPI_NOR_INST(inst) \ - BUILD_ASSERT((DT_INST_ENUM_IDX(inst, mspi_io_mode) == \ - MSPI_IO_MODE_SINGLE) || \ - (DT_INST_ENUM_IDX(inst, mspi_io_mode) == \ - MSPI_IO_MODE_QUAD_1_4_4) || \ - (DT_INST_ENUM_IDX(inst, mspi_io_mode) == \ - MSPI_IO_MODE_OCTAL), \ - "Only 1x, 1-4-4 and 8x I/O modes are supported for now"); \ + SFDP_BUILD_ASSERTS(inst); \ PM_DEVICE_DT_INST_DEFINE(inst, dev_pm_action_cb); \ + DEFAULT_ERASE_TYPES_DEFINE(inst); \ static struct flash_mspi_nor_data dev##inst##_data; \ static const struct flash_mspi_nor_config dev##inst##_config = { \ .bus = DEVICE_DT_GET(DT_INST_BUS(inst)), \ - .flash_size = FLASH_SIZE_INST(inst), \ + .flash_size = FLASH_SIZE(inst), \ + .page_size = FLASH_PAGE_SIZE(inst), \ .mspi_id = MSPI_DEVICE_ID_DT_INST(inst), \ .mspi_nor_cfg = MSPI_DEVICE_CONFIG_DT_INST(inst), \ .mspi_nor_init_cfg = FLASH_INITIAL_CONFIG(inst), \ - .mspi_nor_cfg_mask = DT_PROP(DT_INST_BUS(inst), \ - software_multiperipheral) \ - ? MSPI_DEVICE_CONFIG_ALL \ - : MSPI_DEVICE_CONFIG_NONE, \ IF_ENABLED(CONFIG_MSPI_XIP, \ (.xip_cfg = MSPI_XIP_CONFIG_DT_INST(inst),)) \ + IF_ENABLED(WITH_SUPPLY_GPIO, \ + (.supply = GPIO_DT_SPEC_INST_GET_OR(inst, supply_gpios, {0}),)) \ IF_ENABLED(WITH_RESET_GPIO, \ (.reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}), \ - .reset_pulse_us = DT_INST_PROP_OR(inst, t_reset_pulse, 0) \ - / 1000, \ + .reset_pulse_us = DT_INST_PROP_OR(inst, t_reset_pulse, 0) \ + / 1000,)) \ .reset_recovery_us = DT_INST_PROP_OR(inst, t_reset_recovery, 0) \ - / 1000,)) \ + / 1000, \ .transfer_timeout = DT_INST_PROP(inst, transfer_timeout), \ FLASH_PAGE_LAYOUT_DEFINE(inst) \ - .jedec_id = DT_INST_PROP(inst, jedec_id), \ - .jedec_cmds = FLASH_CMDS(inst), \ + .jedec_id = DT_INST_PROP_OR(inst, jedec_id, {0}), \ .quirks = FLASH_QUIRKS(inst), \ - .dw15_qer = FLASH_DW15_QER(inst), \ + .default_erase_types = DEFAULT_ERASE_TYPES(inst), \ + .default_cmd_info = DEFAULT_CMD_INFO(inst), \ + .default_switch_info = DEFAULT_SWITCH_INFO(inst), \ + .jedec_id_specified = DT_INST_NODE_HAS_PROP(inst, jedec_id), \ + .rx_dummy_specified = DT_INST_NODE_HAS_PROP(inst, rx_dummy), \ + .multiperipheral_bus = DT_PROP(DT_INST_BUS(inst), \ + software_multiperipheral), \ + IO_MODE_FLAGS(DT_INST_ENUM_IDX(inst, mspi_io_mode)), \ + .initial_soft_reset = DT_INST_PROP(inst, initial_soft_reset), \ }; \ FLASH_PAGE_LAYOUT_CHECK(inst) \ DEVICE_DT_INST_DEFINE(inst, \ diff --git a/drivers/flash/flash_mspi_nor.h b/drivers/flash/flash_mspi_nor.h index ad957f24bc79a..480bccce47291 100644 --- a/drivers/flash/flash_mspi_nor.h +++ b/drivers/flash/flash_mspi_nor.h @@ -16,232 +16,103 @@ extern "C" { #include "jesd216.h" #include "spi_nor.h" +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(supply_gpios) +#define WITH_SUPPLY_GPIO 1 +#endif #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) #define WITH_RESET_GPIO 1 #endif +#if DT_ANY_INST_HAS_BOOL_STATUS_OKAY(initial_soft_reset) +#define WITH_SOFT_RESET 1 +#endif + +#define CMD_EXTENSION_NONE 0 +#define CMD_EXTENSION_SAME 1 +#define CMD_EXTENSION_INVERSE 2 + +#define OCTAL_ENABLE_REQ_NONE 0 +#define OCTAL_ENABLE_REQ_S2B3 1 + +#define ENTER_4BYTE_ADDR_NONE 0 +#define ENTER_4BYTE_ADDR_B7 1 +#define ENTER_4BYTE_ADDR_06_B7 2 + +struct flash_mspi_nor_cmd_info { + uint8_t read_cmd; + uint8_t read_mode_bit_cycles : 3; + uint8_t read_dummy_cycles : 5; + uint8_t pp_cmd; + bool uses_4byte_addr : 1; + /* BFP, 18th DWORD, bits 30-29 */ + uint8_t cmd_extension : 2; + /* xSPI Profile 1.0 (ID FF05), 1st DWORD: */ + /* - Read SFDP command address bytes: 4 (true) or 3 */ + bool sfdp_addr_4 : 1; + /* - Read SDFP command dummy cycles: 20 (true) or 8 */ + bool sfdp_dummy_20 : 1; + /* - Read Status Register command address bytes: 4 (true) or 0 */ + bool rdsr_addr_4 : 1; + /* - Read Status Register command dummy cycles: 0, 4, or 8 */ + uint8_t rdsr_dummy : 4; + /* - Read JEDEC ID command parameters; not sure where to get their + * values from, but since for many flash chips they are the same + * as for RDSR, those are taken as defaults, see DEFAULT_CMD_INFO() + */ + bool rdid_addr_4 : 1; + uint8_t rdid_dummy : 4; +}; + +struct flash_mspi_nor_switch_info { + uint8_t quad_enable_req : 3; + uint8_t octal_enable_req : 3; + uint8_t enter_4byte_addr : 2; +}; struct flash_mspi_nor_config { const struct device *bus; uint32_t flash_size; + uint16_t page_size; struct mspi_dev_id mspi_id; struct mspi_dev_cfg mspi_nor_cfg; struct mspi_dev_cfg mspi_nor_init_cfg; - enum mspi_dev_cfg_mask mspi_nor_cfg_mask; #if defined(CONFIG_MSPI_XIP) struct mspi_xip_cfg xip_cfg; #endif +#if defined(WITH_SUPPLY_GPIO) + struct gpio_dt_spec supply; +#endif #if defined(WITH_RESET_GPIO) struct gpio_dt_spec reset; uint32_t reset_pulse_us; - uint32_t reset_recovery_us; #endif + uint32_t reset_recovery_us; uint32_t transfer_timeout; #if defined(CONFIG_FLASH_PAGE_LAYOUT) struct flash_pages_layout layout; #endif uint8_t jedec_id[SPI_NOR_MAX_ID_LEN]; - const struct flash_mspi_nor_cmds *jedec_cmds; struct flash_mspi_nor_quirks *quirks; - uint8_t dw15_qer; + const struct jesd216_erase_type *default_erase_types; + struct flash_mspi_nor_cmd_info default_cmd_info; + struct flash_mspi_nor_switch_info default_switch_info; + bool jedec_id_specified : 1; + bool rx_dummy_specified : 1; + bool multiperipheral_bus : 1; + bool multi_io_cmd : 1; + bool single_io_addr : 1; + bool initial_soft_reset : 1; }; struct flash_mspi_nor_data { struct k_sem acquired; struct mspi_xfer_packet packet; struct mspi_xfer xfer; - struct mspi_dev_cfg *curr_cfg; + struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES]; + struct flash_mspi_nor_cmd_info cmd_info; + struct flash_mspi_nor_switch_info switch_info; + bool in_target_io_mode; }; -struct flash_mspi_nor_cmd { - enum mspi_xfer_direction dir; - uint32_t cmd; - uint16_t tx_dummy; - uint16_t rx_dummy; - uint8_t cmd_length; - uint8_t addr_length; - bool force_single; -}; - -struct flash_mspi_nor_cmds { - struct flash_mspi_nor_cmd id; - struct flash_mspi_nor_cmd write_en; - struct flash_mspi_nor_cmd read; - struct flash_mspi_nor_cmd status; - struct flash_mspi_nor_cmd config; - struct flash_mspi_nor_cmd page_program; - struct flash_mspi_nor_cmd sector_erase; - struct flash_mspi_nor_cmd chip_erase; - struct flash_mspi_nor_cmd sfdp; -}; - -const struct flash_mspi_nor_cmds commands_single = { - .id = { - .dir = MSPI_RX, - .cmd = JESD216_CMD_READ_ID, - .cmd_length = 1, - }, - .write_en = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_WREN, - .cmd_length = 1, - }, - .read = { - .dir = MSPI_RX, - .cmd = SPI_NOR_CMD_READ_FAST, - .cmd_length = 1, - .addr_length = 3, - .rx_dummy = 8, - }, - .status = { - .dir = MSPI_RX, - .cmd = SPI_NOR_CMD_RDSR, - .cmd_length = 1, - }, - .config = { - .dir = MSPI_RX, - .cmd = SPI_NOR_CMD_RDCR, - .cmd_length = 1, - }, - .page_program = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_PP, - .cmd_length = 1, - .addr_length = 3, - }, - .sector_erase = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_SE, - .cmd_length = 1, - .addr_length = 3, - }, - .chip_erase = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_CE, - .cmd_length = 1, - }, - .sfdp = { - .dir = MSPI_RX, - .cmd = JESD216_CMD_READ_SFDP, - .cmd_length = 1, - .addr_length = 3, - .rx_dummy = 8, - }, -}; - -const struct flash_mspi_nor_cmds commands_quad_1_4_4 = { - .id = { - .dir = MSPI_RX, - .cmd = JESD216_CMD_READ_ID, - .cmd_length = 1, - .force_single = true, - }, - .write_en = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_WREN, - .cmd_length = 1, - }, - .read = { - .dir = MSPI_RX, - .cmd = SPI_NOR_CMD_4READ, - .cmd_length = 1, - .addr_length = 3, - .rx_dummy = 6, - }, - .status = { - .dir = MSPI_RX, - .cmd = SPI_NOR_CMD_RDSR, - .cmd_length = 1, - .force_single = true, - }, - .config = { - .dir = MSPI_RX, - .cmd = SPI_NOR_CMD_RDCR, - .cmd_length = 1, - .force_single = true, - }, - .page_program = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_PP_1_4_4, - .cmd_length = 1, - .addr_length = 3, - }, - .sector_erase = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_SE, - .cmd_length = 1, - .addr_length = 3, - .force_single = true, - }, - .chip_erase = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_CE, - .cmd_length = 1, - }, - .sfdp = { - .dir = MSPI_RX, - .cmd = JESD216_CMD_READ_SFDP, - .cmd_length = 1, - .addr_length = 3, - .rx_dummy = 8, - .force_single = true, - }, -}; - -const struct flash_mspi_nor_cmds commands_octal = { - .id = { - .dir = MSPI_RX, - .cmd = JESD216_OCMD_READ_ID, - .cmd_length = 2, - .addr_length = 4, - .rx_dummy = 4 - }, - .write_en = { - .dir = MSPI_TX, - .cmd = SPI_NOR_OCMD_WREN, - .cmd_length = 2, - }, - .read = { - .dir = MSPI_RX, - .cmd = SPI_NOR_OCMD_RD, - .cmd_length = 2, - .addr_length = 4, - .rx_dummy = 20, - }, - .status = { - .dir = MSPI_RX, - .cmd = SPI_NOR_OCMD_RDSR, - .cmd_length = 2, - .addr_length = 4, - .rx_dummy = 4, - }, - .page_program = { - .dir = MSPI_TX, - .cmd = SPI_NOR_OCMD_PAGE_PRG, - .cmd_length = 2, - .addr_length = 4, - }, - .sector_erase = { - .dir = MSPI_TX, - .cmd = SPI_NOR_OCMD_SE, - .cmd_length = 2, - .addr_length = 4, - }, - .chip_erase = { - .dir = MSPI_TX, - .cmd = SPI_NOR_OCMD_CE, - .cmd_length = 2, - }, - .sfdp = { - .dir = MSPI_RX, - .cmd = JESD216_OCMD_READ_SFDP, - .cmd_length = 2, - .addr_length = 4, - .rx_dummy = 20, - }, -}; - -void flash_mspi_command_set(const struct device *dev, const struct flash_mspi_nor_cmd *cmd); - #ifdef __cplusplus } #endif diff --git a/drivers/flash/flash_mspi_nor_quirks.h b/drivers/flash/flash_mspi_nor_quirks.h index eb40ad1938aa1..d58fbea4ff9b8 100644 --- a/drivers/flash/flash_mspi_nor_quirks.h +++ b/drivers/flash/flash_mspi_nor_quirks.h @@ -9,6 +9,13 @@ /* Flash chip specific quirks */ struct flash_mspi_nor_quirks { + /* Called at the beginning of the flash chip initialization, + * right after reset if any is performed. Can be used to alter + * structures that define communication with the chip, like + * `cmd_info`, `switch_info`, and `erase_types`, which are set + * to default values at this point. + */ + int (*pre_init)(const struct device *dev); /* Called after switching to default IO mode. */ int (*post_switch_mode)(const struct device *dev); }; @@ -63,46 +70,24 @@ static inline int mxicy_mx25r_post_switch_mode(const struct device *dev) return 0; } - /* Wait for previous write to finish */ - do { - flash_mspi_command_set(dev, &dev_config->jedec_cmds->status); - dev_data->packet.data_buf = &status; - dev_data->packet.num_bytes = sizeof(status); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); - if (rc < 0) { - return rc; - } - } while (status & SPI_NOR_WIP_BIT); - /* Write enable */ - flash_mspi_command_set(dev, &commands_single.write_en); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); + rc = cmd_wren(dev); if (rc < 0) { return rc; } /* Write status and config registers */ - const struct flash_mspi_nor_cmd cmd_status = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_WRSR, - .cmd_length = 1, - }; - - flash_mspi_command_set(dev, &cmd_status); + set_up_xfer(dev, MSPI_TX); dev_data->packet.data_buf = mxicy_mx25r_hp_payload; dev_data->packet.num_bytes = sizeof(mxicy_mx25r_hp_payload); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); + rc = perform_xfer(dev, SPI_NOR_CMD_WRSR, false); if (rc < 0) { return rc; } /* Wait for write to end and verify status register */ do { - flash_mspi_command_set(dev, &dev_config->jedec_cmds->status); - dev_data->packet.data_buf = &status; - dev_data->packet.num_bytes = sizeof(status); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); + rc = cmd_rdsr(dev, SPI_NOR_CMD_RDSR, &status); if (rc < 0) { return rc; } @@ -113,10 +98,10 @@ static inline int mxicy_mx25r_post_switch_mode(const struct device *dev) } /* Verify configuration registers */ - flash_mspi_command_set(dev, &dev_config->jedec_cmds->config); - dev_data->packet.data_buf = config; + set_up_xfer(dev, MSPI_RX); dev_data->packet.num_bytes = sizeof(config); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); + dev_data->packet.data_buf = config; + rc = perform_xfer(dev, SPI_NOR_CMD_RDCR, false); if (rc < 0) { return rc; } @@ -138,45 +123,89 @@ struct flash_mspi_nor_quirks flash_quirks_mxicy_mx25r = { #if DT_HAS_COMPAT_STATUS_OKAY(mxicy_mx25u) -#define MXICY_MX25R_OE_MASK BIT(0) - -static uint8_t mxicy_mx25u_oe_payload = MXICY_MX25R_OE_MASK; - static inline int mxicy_mx25u_post_switch_mode(const struct device *dev) { const struct flash_mspi_nor_config *dev_config = dev->config; struct flash_mspi_nor_data *dev_data = dev->data; enum mspi_io_mode io_mode = dev_config->mspi_nor_cfg.io_mode; + uint8_t opi_enable; int rc; if (io_mode != MSPI_IO_MODE_OCTAL) { return 0; } + /* + * TODO - replace this with a generic routine that uses information + * from SFDP header FF87 (Status, Control and Configuration + * Register Map) + */ + + if (dev_config->mspi_nor_cfg.data_rate == MSPI_DATA_RATE_DUAL) { + opi_enable = BIT(1); + } else { + opi_enable = BIT(0); + } + /* Write enable */ - flash_mspi_command_set(dev, &commands_single.write_en); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, - &dev_data->xfer); + rc = cmd_wren(dev); if (rc < 0) { return rc; } /* Write config register 2 */ - const struct flash_mspi_nor_cmd cmd_status = { - .dir = MSPI_TX, - .cmd = SPI_NOR_CMD_WR_CFGREG2, - .cmd_length = 1, - .addr_length = 4, + set_up_xfer(dev, MSPI_TX); + dev_data->xfer.addr_length = 4; + dev_data->packet.address = 0; + dev_data->packet.data_buf = &opi_enable; + dev_data->packet.num_bytes = sizeof(opi_enable); + return perform_xfer(dev, SPI_NOR_CMD_WR_CFGREG2, false); +} + +static int mxicy_mx25u_pre_init(const struct device *dev) +{ + const struct flash_mspi_nor_config *dev_config = dev->config; + struct flash_mspi_nor_data *dev_data = dev->data; + static const uint8_t dummy_cycles[8] = { + 20, 18, 16, 14, 12, 10, 8, 6 }; + uint8_t cfg_reg; + int rc; + + if (dev_config->mspi_nor_cfg.io_mode != MSPI_IO_MODE_OCTAL) { + return 0; + } - flash_mspi_command_set(dev, &cmd_status); - dev_data->packet.data_buf = &mxicy_mx25u_oe_payload; - dev_data->packet.num_bytes = sizeof(mxicy_mx25u_oe_payload); - rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id, &dev_data->xfer); - return rc; + if (dev_config->mspi_nor_cfg.data_rate == MSPI_DATA_RATE_SINGLE) { + dev_data->cmd_info.cmd_extension = CMD_EXTENSION_INVERSE; + } + + /* + * TODO - replace this with a generic routine that uses information + * from SFDP header FF87 (Status, Control and Configuration + * Register Map) + */ + + /* Read configured number of dummy cycles for memory reading commands. */ + set_up_xfer(dev, MSPI_RX); + dev_data->xfer.addr_length = 4; + dev_data->packet.address = 0x300; + dev_data->packet.data_buf = &cfg_reg; + dev_data->packet.num_bytes = sizeof(cfg_reg); + rc = perform_xfer(dev, SPI_NOR_CMD_RD_CFGREG2, false); + if (rc < 0) { + LOG_ERR("Failed to read Dummy Cycle from CFGREG2"); + return rc; + } + + dev_data->cmd_info.read_mode_bit_cycles = 0; + dev_data->cmd_info.read_dummy_cycles = dummy_cycles[cfg_reg & 0x7]; + + return 0; } struct flash_mspi_nor_quirks flash_quirks_mxicy_mx25u = { + .pre_init = mxicy_mx25u_pre_init, .post_switch_mode = mxicy_mx25u_post_switch_mode, }; diff --git a/drivers/flash/flash_mspi_nor_sfdp.h b/drivers/flash/flash_mspi_nor_sfdp.h new file mode 100644 index 0000000000000..8dbecff01e80f --- /dev/null +++ b/drivers/flash/flash_mspi_nor_sfdp.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef CONFIG_FLASH_MSPI_NOR_USE_SFDP + +#define BFP_DW16_SOFT_RESET_66_99 BIT(4) + +#define BFP_DW16_4B_ADDR_ENTER_B7 BIT(0) +#define BFP_DW16_4B_ADDR_ENTER_06_B7 BIT(1) +#define BFP_DW16_4B_ADDR_PER_CMD BIT(5) +#define BFP_DW16_4B_ADDR_ALWAYS BIT(6) + +#define BFP_DW18_CMD_EXT_SAME 0 +#define BFP_DW18_CMD_EXT_INV 1 + +/* 32-bit words in SFDP arrays in devicetree are stored in little-endian byte + * order. See jedec,jesd216.yaml + */ +#define SFDP_DW_BYTE_0_IDX(dw_no) \ + UTIL_DEC(UTIL_DEC(UTIL_DEC(UTIL_DEC(UTIL_X2(UTIL_X2(dw_no)))))) +#define SFDP_DW_BYTE_1_IDX(dw_no) \ + UTIL_DEC(UTIL_DEC(UTIL_DEC(UTIL_X2(UTIL_X2(dw_no))))) +#define SFDP_DW_BYTE_2_IDX(dw_no) \ + UTIL_DEC(UTIL_DEC(UTIL_X2(UTIL_X2(dw_no)))) +#define SFDP_DW_BYTE_3_IDX(dw_no) \ + UTIL_DEC(UTIL_X2(UTIL_X2(dw_no))) +#define SFDP_DW_BYTE(inst, prop, dw_no, byte_idx) \ + DT_INST_PROP_BY_IDX(inst, prop, SFDP_DW_BYTE_##byte_idx##_IDX(dw_no)) +#define SFDP_DW_EXISTS(inst, prop, dw_no) \ + DT_INST_PROP_HAS_IDX(inst, prop, SFDP_DW_BYTE_3_IDX(dw_no)) + +#define SFDP_DW(inst, prop, dw_no) \ + COND_CODE_1(SFDP_DW_EXISTS(inst, prop, dw_no), \ + (((SFDP_DW_BYTE(inst, prop, dw_no, 3) << 24) | \ + (SFDP_DW_BYTE(inst, prop, dw_no, 2) << 16) | \ + (SFDP_DW_BYTE(inst, prop, dw_no, 1) << 8) | \ + (SFDP_DW_BYTE(inst, prop, dw_no, 0) << 0))), \ + (0)) + +#define SFDP_FIELD(inst, prop, dw_no, mask) \ + FIELD_GET(mask, SFDP_DW(inst, prop, dw_no)) + +#define USES_8D_8D_8D(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_OCTAL && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_DUAL) +#define USES_8S_8S_8S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_OCTAL && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_1S_8D_8D(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_OCTAL_1_8_8 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_DUAL) +#define USES_1S_8S_8S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_OCTAL_1_8_8 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_1S_1S_8S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_OCTAL_1_1_8 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_4S_4D_4D(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_QUAD && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_DUAL) +#define USES_4S_4S_4S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_QUAD && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_1S_4D_4D(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_QUAD_1_4_4 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_DUAL) +#define USES_1S_4S_4S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_QUAD_1_4_4 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_1S_1S_4S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_QUAD_1_1_4 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_2S_2S_2S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_DUAL && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_1S_2D_2D(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_DUAL_1_2_2 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_DUAL) +#define USES_1S_2S_2S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_DUAL_1_2_2 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_1S_1S_2S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_DUAL_1_1_2 && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) +#define USES_1S_1D_1D(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_SINGLE && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_DUAL) +#define USES_1S_1S_1S(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_SINGLE && \ + DT_INST_ENUM_IDX(inst, mspi_data_rate) == MSPI_DATA_RATE_SINGLE) + +#define USES_OCTAL_IO(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_OCTAL) + +#define BFP_DW1_ADDRESS_BYTES(inst) \ + SFDP_FIELD(inst, sfdp_bfp, 1, GENMASK(18, 17)) + +#define USES_4BYTE_ADDR(inst) \ + (USES_OCTAL_IO(inst) || \ + DT_INST_PROP(inst, use_4byte_addressing) || \ + BFP_DW1_ADDRESS_BYTES(inst) == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B) + +#define BFP_ENTER_4BYTE_ADDR_METHODS(inst) \ + SFDP_FIELD(inst, sfdp_bfp, 16, GENMASK(31, 24)) + +#define HAS_4BYTE_ADDR_CMDS(inst) \ + (BFP_ENTER_4BYTE_ADDR_METHODS(inst) & BFP_DW16_4B_ADDR_PER_CMD) + +#define BFP_DW18_CMD_EXT(inst) \ + SFDP_FIELD(inst, sfdp_bfp, 18, GENMASK(30, 29)) + +#define CMD_EXTENSION(inst) \ + (!USES_8D_8D_8D(inst) ? CMD_EXTENSION_NONE : \ + (BFP_DW18_CMD_EXT(inst) \ + == BFP_DW18_CMD_EXT_INV) ? CMD_EXTENSION_INVERSE \ + : CMD_EXTENSION_SAME) + +/* 1st DWORD of 4-byte Address Instruction Table (ID FF84) indicates commands + * that are supported by the chip. + */ +#define FF84_DW1_BIT(inst, bit) (SFDP_DW(inst, sfdp_ff84, 1) & BIT(bit)) + +#define SFDP_CMD_PP(inst) \ + USES_1S_4S_4S(inst) ? SPI_NOR_CMD_PP_1_4_4 : \ + USES_1S_1S_4S(inst) ? SPI_NOR_CMD_PP_1_1_4 : \ + SPI_NOR_CMD_PP +#define SFDP_CMD_PP_4B(inst) \ + USES_1S_8S_8S(inst) && FF84_DW1_BIT(inst, 24) ? 0x8E : \ + USES_1S_1S_8S(inst) && FF84_DW1_BIT(inst, 23) ? 0x84 : \ + USES_1S_4S_4S(inst) && FF84_DW1_BIT(inst, 8) ? SPI_NOR_CMD_PP_1_4_4_4B : \ + USES_1S_1S_4S(inst) && FF84_DW1_BIT(inst, 7) ? SPI_NOR_CMD_PP_1_1_4_4B : \ + FF84_DW1_BIT(inst, 6) ? SPI_NOR_CMD_PP_4B \ + : 0 +#define SFDP_CMD_FAST_READ(inst) \ + USES_1S_8D_8D(inst) ? 0 : \ + USES_1S_8S_8S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 17, GENMASK(15, 8)) : \ + USES_1S_1S_8S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 17, GENMASK(31, 24)) : \ + USES_4S_4D_4D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 23, GENMASK(31, 24)) : \ + USES_4S_4S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 7, GENMASK(31, 24)) : \ + USES_1S_4D_4D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 23, GENMASK(15, 8)) : \ + USES_1S_4S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 3, GENMASK(15, 8)) : \ + USES_1S_1S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 3, GENMASK(31, 24)) : \ + USES_2S_2S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 6, GENMASK(31, 24)) : \ + USES_1S_2D_2D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 22, GENMASK(31, 24)) : \ + USES_1S_2S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 4, GENMASK(31, 24)) : \ + USES_1S_1S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 4, GENMASK(15, 8)) : \ + USES_1S_1D_1D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 22, GENMASK(15, 8)) : \ + SPI_NOR_CMD_READ_FAST +#define SFDP_CMD_FAST_READ_4B(inst) \ + USES_8D_8D_8D(inst) ? 0xEE : \ + USES_8S_8S_8S(inst) ? 0xEC : \ + USES_1S_8D_8D(inst) && FF84_DW1_BIT(inst, 22) ? 0xFD : \ + USES_1S_8S_8S(inst) && FF84_DW1_BIT(inst, 21) ? 0xCC : \ + USES_1S_1S_8S(inst) && FF84_DW1_BIT(inst, 20) ? 0x7C : \ + USES_4S_4D_4D(inst) ? 0 : \ + USES_4S_4S_4S(inst) ? 0 : \ + USES_1S_4D_4D(inst) && FF84_DW1_BIT(inst, 15) ? 0xEE : \ + USES_1S_4S_4S(inst) && FF84_DW1_BIT(inst, 5) ? 0xEC : \ + USES_1S_1S_4S(inst) && FF84_DW1_BIT(inst, 4) ? 0x6C : \ + USES_2S_2S_2S(inst) ? 0 : \ + USES_1S_2D_2D(inst) && FF84_DW1_BIT(inst, 14) ? 0xBE : \ + USES_1S_2S_2S(inst) && FF84_DW1_BIT(inst, 3) ? 0xBC : \ + USES_1S_1S_2S(inst) && FF84_DW1_BIT(inst, 2) ? 0x3C : \ + USES_1S_1D_1D(inst) && FF84_DW1_BIT(inst, 13) ? 0x0E : \ + FF84_DW1_BIT(inst, 1) ? SPI_NOR_CMD_READ_FAST_4B : \ + 0 + +#define DEFAULT_CMD_INFO(inst) { \ + .pp_cmd = USES_4BYTE_ADDR(inst) && HAS_4BYTE_ADDR_CMDS(inst) \ + ? SFDP_CMD_PP_4B(inst) \ + : SFDP_CMD_PP(inst), \ + .read_cmd = USES_4BYTE_ADDR(inst) && HAS_4BYTE_ADDR_CMDS(inst) \ + ? SFDP_CMD_FAST_READ_4B(inst) \ + : SFDP_CMD_FAST_READ(inst), \ + .read_mode_bit_cycles = \ + USES_1S_8S_8S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 17, GENMASK(7, 5)) : \ + USES_1S_1S_8S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 17, GENMASK(23, 21)) : \ + USES_4S_4D_4D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 23, GENMASK(23, 21)) : \ + USES_4S_4S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 7, GENMASK(23, 21)) : \ + USES_1S_4D_4D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 23, GENMASK(7, 5)) : \ + USES_1S_4S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 3, GENMASK(7, 5)) : \ + USES_1S_1S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 3, GENMASK(23, 21)) : \ + USES_2S_2S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 6, GENMASK(23, 21)) : \ + USES_1S_2D_2D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 22, GENMASK(23, 21)) : \ + USES_1S_2S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 4, GENMASK(23, 21)) : \ + USES_1S_1S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 4, GENMASK(7, 5)) : \ + USES_1S_1D_1D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 22, GENMASK(7, 5)) : \ + USES_1S_1S_1S(inst) ? 0 : \ + 0, \ + .read_dummy_cycles = DT_INST_PROP_OR(inst, rx_dummy, \ + USES_8D_8D_8D(inst) ? SFDP_FIELD(inst, sfdp_ff05, 6, GENMASK(4, 0)) : \ + USES_8S_8S_8S(inst) ? SFDP_FIELD(inst, sfdp_ff05, 6, GENMASK(9, 5)) : \ + USES_1S_8S_8S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 17, GENMASK(4, 0)) : \ + USES_1S_1S_8S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 17, GENMASK(20, 16)) : \ + USES_4S_4D_4D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 23, GENMASK(20, 16)) : \ + USES_4S_4S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 7, GENMASK(20, 16)) : \ + USES_1S_4D_4D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 23, GENMASK(4, 0)) : \ + USES_1S_4S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 3, GENMASK(4, 0)) : \ + USES_1S_1S_4S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 3, GENMASK(20, 16)) : \ + USES_2S_2S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 6, GENMASK(20, 16)) : \ + USES_1S_2D_2D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 22, GENMASK(20, 16)) : \ + USES_1S_2S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 4, GENMASK(20, 16)) : \ + USES_1S_1S_2S(inst) ? SFDP_FIELD(inst, sfdp_bfp, 4, GENMASK(4, 0)) : \ + USES_1S_1D_1D(inst) ? SFDP_FIELD(inst, sfdp_bfp, 22, GENMASK(4, 0)) : \ + USES_1S_1S_1S(inst) ? 8 : \ + 0), \ + .uses_4byte_addr = USES_4BYTE_ADDR(inst), \ + .cmd_extension = CMD_EXTENSION(inst), \ + .sfdp_addr_4 = USES_OCTAL_IO(inst) \ + ? (SFDP_FIELD(inst, sfdp_ff05, 1, BIT(31)) == 0) \ + : false, \ + .sfdp_dummy_20 = USES_OCTAL_IO(inst) \ + ? (SFDP_FIELD(inst, sfdp_ff05, 1, BIT(30)) == 1) \ + : false, \ + .rdsr_addr_4 = USES_OCTAL_IO(inst) \ + ? (SFDP_FIELD(inst, sfdp_ff05, 1, BIT(29)) == 1) \ + : false, \ + .rdsr_dummy = USES_OCTAL_IO(inst) \ + ? (SFDP_FIELD(inst, sfdp_ff05, 1, BIT(28)) ? 8 : 4) \ + : 0, \ + .rdid_addr_4 = USES_OCTAL_IO(inst) \ + ? (SFDP_FIELD(inst, sfdp_ff05, 1, BIT(29)) == 1) \ + : false, \ + .rdid_dummy = USES_OCTAL_IO(inst) \ + ? (SFDP_FIELD(inst, sfdp_ff05, 1, BIT(28)) ? 8 : 4) \ + : 0, } + +/* Erase Types, 8th and 9th DWORD of BSP */ +#define BFP_DW8_CMD_ET_1(inst) SFDP_FIELD(inst, sfdp_bfp, 8, GENMASK(15, 8)) +#define BFP_DW8_EXP_ET_1(inst) SFDP_FIELD(inst, sfdp_bfp, 8, GENMASK(7, 0)) +#define BFP_DW8_CMD_ET_2(inst) SFDP_FIELD(inst, sfdp_bfp, 8, GENMASK(31, 24)) +#define BFP_DW8_EXP_ET_2(inst) SFDP_FIELD(inst, sfdp_bfp, 8, GENMASK(23, 16)) +#define BFP_DW9_CMD_ET_3(inst) SFDP_FIELD(inst, sfdp_bfp, 9, GENMASK(15, 8)) +#define BFP_DW9_EXP_ET_3(inst) SFDP_FIELD(inst, sfdp_bfp, 9, GENMASK(7, 0)) +#define BFP_DW9_CMD_ET_4(inst) SFDP_FIELD(inst, sfdp_bfp, 9, GENMASK(31, 24)) +#define BFP_DW9_EXP_ET_4(inst) SFDP_FIELD(inst, sfdp_bfp, 9, GENMASK(23, 16)) + +/* 4-byte Address instructions for Erase Types defined in 8th and 9th DWORD + * of BFP; 2nd DWORD of 4-byte Address Instruction Table (ID FF84) + */ +#define FF84_DW2_CMD_ET_1(inst) SFDP_FIELD(inst, sfdp_ff84, 2, GENMASK(7, 0)) +#define FF84_DW2_CMD_ET_2(inst) SFDP_FIELD(inst, sfdp_ff84, 2, GENMASK(15, 8)) +#define FF84_DW2_CMD_ET_3(inst) SFDP_FIELD(inst, sfdp_ff84, 2, GENMASK(23, 16)) +#define FF84_DW2_CMD_ET_4(inst) SFDP_FIELD(inst, sfdp_ff84, 2, GENMASK(31, 24)) +/* Support for Erase Types in 4-byte Address mode; table FF84, 1st DWORD */ +#define FF84_DW1_SUP_ET_1(inst) SFDP_FIELD(inst, sfdp_ff84, 1, BIT(9)) +#define FF84_DW1_SUP_ET_2(inst) SFDP_FIELD(inst, sfdp_ff84, 1, BIT(10)) +#define FF84_DW1_SUP_ET_3(inst) SFDP_FIELD(inst, sfdp_ff84, 1, BIT(11)) +#define FF84_DW1_SUP_ET_4(inst) SFDP_FIELD(inst, sfdp_ff84, 1, BIT(12)) + +#define DEFAULT_ERASE_TYPES_DEFINE(inst) \ + static const struct jesd216_erase_type \ + dev##inst##_erase_types[JESD216_NUM_ERASE_TYPES] = \ + COND_CODE_1(SFDP_DW_EXISTS(inst, sfdp_bfp, 8), \ + ({{ .cmd = BFP_DW8_CMD_ET_1(inst), \ + .exp = BFP_DW8_EXP_ET_1(inst), }, \ + { .cmd = BFP_DW8_CMD_ET_2(inst), \ + .exp = BFP_DW8_EXP_ET_2(inst), }, \ + { .cmd = BFP_DW9_CMD_ET_3(inst), \ + .exp = BFP_DW9_EXP_ET_3(inst), }, \ + { .cmd = BFP_DW9_CMD_ET_4(inst), \ + .exp = BFP_DW9_EXP_ET_4(inst), }}), \ + ({{ .cmd = SPI_NOR_CMD_SE, \ + .exp = 0x0C }})); \ + static const struct jesd216_erase_type \ + dev##inst##_erase_types_4b[JESD216_NUM_ERASE_TYPES] = \ + COND_CODE_1(UTIL_AND(SFDP_DW_EXISTS(inst, sfdp_ff84, 2), \ + SFDP_DW_EXISTS(inst, sfdp_bfp, 9)), \ + ({{ .cmd = FF84_DW2_CMD_ET_1(inst), \ + .exp = FF84_DW1_SUP_ET_1(inst) \ + ? BFP_DW8_EXP_ET_1(inst) \ + : 0, }, \ + { .cmd = FF84_DW2_CMD_ET_2(inst), \ + .exp = FF84_DW1_SUP_ET_2(inst) \ + ? BFP_DW8_EXP_ET_2(inst) \ + : 0, }, \ + { .cmd = FF84_DW2_CMD_ET_3(inst), \ + .exp = FF84_DW1_SUP_ET_3(inst) \ + ? BFP_DW9_EXP_ET_3(inst) \ + : 0, }, \ + { .cmd = FF84_DW2_CMD_ET_4(inst), \ + .exp = FF84_DW1_SUP_ET_4(inst) \ + ? BFP_DW9_EXP_ET_4(inst) \ + : 0, }}), \ + ({{ .cmd = SPI_NOR_CMD_SE_4B, \ + .exp = 0x0C }})) + +#define DEFAULT_ERASE_TYPES(inst) \ + USES_4BYTE_ADDR(inst) && HAS_4BYTE_ADDR_CMDS(inst) \ + ? dev##inst##_erase_types_4b \ + : dev##inst##_erase_types + +#define BFP_DW15_QER(inst) \ + SFDP_FIELD(inst, sfdp_bfp, 15, GENMASK(22, 20)) + +#define BFP_DW19_OER(inst) \ + SFDP_FIELD(inst, sfdp_bfp, 19, GENMASK(22, 20)) + +#define ENTER_4BYTE_ADDR(inst) \ + (!USES_4BYTE_ADDR(inst) ? ENTER_4BYTE_ADDR_NONE : \ + (BFP_ENTER_4BYTE_ADDR_METHODS(inst) \ + & (BFP_DW16_4B_ADDR_PER_CMD | \ + BFP_DW16_4B_ADDR_ALWAYS)) ? ENTER_4BYTE_ADDR_NONE : \ + (BFP_ENTER_4BYTE_ADDR_METHODS(inst) \ + & BFP_DW16_4B_ADDR_ENTER_B7) ? ENTER_4BYTE_ADDR_B7 : \ + (BFP_ENTER_4BYTE_ADDR_METHODS(inst) \ + & BFP_DW16_4B_ADDR_ENTER_06_B7) ? ENTER_4BYTE_ADDR_06_B7 : \ + ENTER_4BYTE_ADDR_NONE) + +#define DEFAULT_SWITCH_INFO(inst) { \ + .quad_enable_req = BFP_DW15_QER(inst), \ + .octal_enable_req = BFP_DW19_OER(inst), \ + .enter_4byte_addr = ENTER_4BYTE_ADDR(inst) } + +#define BFP_FLASH_SIZE(dw2) \ + ((dw2 & BIT(31)) \ + ? BIT(MIN(31, (dw2 & BIT_MASK(31)) - 3)) \ + : dw2 / 8) + +#define FLASH_SIZE(inst) \ + (DT_INST_NODE_HAS_PROP(inst, size) \ + ? DT_INST_PROP(inst, size) / 8 \ + : BFP_FLASH_SIZE(SFDP_DW(inst, sfdp_bfp, 2))) + +#define BFP_FLASH_PAGE_EXP(inst) SFDP_FIELD(inst, sfdp_bfp, 11, GENMASK(7, 4)) + +#define FLASH_PAGE_SIZE(inst) \ + (BFP_FLASH_PAGE_EXP(inst) \ + ? BIT(BFP_FLASH_PAGE_EXP(inst)) \ + : SPI_NOR_PAGE_SIZE) + +#define SFDP_BUILD_ASSERTS(inst) \ + BUILD_ASSERT(DT_INST_NODE_HAS_PROP(inst, sfdp_bfp), \ + "sfdp-bfp property needed in " \ + DT_NODE_FULL_NAME(DT_DRV_INST(inst))); \ + BUILD_ASSERT((DT_INST_ENUM_IDX(inst, mspi_io_mode) \ + != MSPI_IO_MODE_OCTAL) || \ + DT_INST_NODE_HAS_PROP(inst, sfdp_ff05), \ + "sfdp-ff05 property needed in " \ + DT_NODE_FULL_NAME(DT_DRV_INST(inst))); \ + BUILD_ASSERT(!USES_4BYTE_ADDR(inst) || \ + DT_INST_NODE_HAS_PROP(inst, sfdp_ff84), \ + "sfdp-ff84 property needed in " \ + DT_NODE_FULL_NAME(DT_DRV_INST(inst))); \ + BUILD_ASSERT(!USES_8D_8D_8D(inst) || \ + BFP_DW18_CMD_EXT(inst) <= BFP_DW18_CMD_EXT_INV, \ + "Unsupported Octal Command Extension mode in " \ + DT_NODE_FULL_NAME(DT_DRV_INST(inst))); \ + BUILD_ASSERT(!DT_INST_PROP(inst, use_4byte_addressing) || \ + (BFP_DW1_ADDRESS_BYTES(inst) \ + != JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_3B), \ + "Cannot use 4-byte addressing for " \ + DT_NODE_FULL_NAME(DT_DRV_INST(inst))); \ + BUILD_ASSERT(!DT_INST_PROP(inst, use_4byte_addressing) || \ + (BFP_ENTER_4BYTE_ADDR_METHODS(inst) \ + & (BFP_DW16_4B_ADDR_ENTER_B7 | \ + BFP_DW16_4B_ADDR_ENTER_06_B7 | \ + BFP_DW16_4B_ADDR_PER_CMD | \ + BFP_DW16_4B_ADDR_ALWAYS)), \ + "No supported method of entering 4-byte addressing mode for " \ + DT_NODE_FULL_NAME(DT_DRV_INST(inst))); \ + BUILD_ASSERT(!DT_INST_PROP(inst, initial_soft_reset) || \ + (SFDP_FIELD(inst, sfdp_bfp, 16, GENMASK(13, 8)) \ + & BFP_DW16_SOFT_RESET_66_99), \ + "Cannot use 66h/99h soft reset sequence for " \ + DT_NODE_FULL_NAME(DT_DRV_INST(inst))) + +#else + +#define USES_4BYTE_ADDR(inst) \ + (DT_INST_ENUM_IDX(inst, mspi_io_mode) == MSPI_IO_MODE_OCTAL || \ + DT_INST_PROP(inst, use_4byte_addressing)) + +#define DEFAULT_CMD_INFO(inst) { \ + .pp_cmd = USES_4BYTE_ADDR(inst) \ + ? SPI_NOR_CMD_PP_4B \ + : SPI_NOR_CMD_PP, \ + .read_cmd = USES_4BYTE_ADDR(inst) \ + ? SPI_NOR_CMD_READ_FAST_4B \ + : SPI_NOR_CMD_READ_FAST, \ + .read_mode_bit_cycles = 0, \ + .read_dummy_cycles = 8, \ + .uses_4byte_addr = USES_4BYTE_ADDR(inst), \ + .cmd_extension = CMD_EXTENSION_NONE, \ + .sfdp_addr_4 = false, \ + .sfdp_dummy_20 = false, \ + .rdsr_addr_4 = false, \ + .rdsr_dummy = 0, \ + .rdid_addr_4 = false, \ + .rdid_dummy = 0, } + +#define DEFAULT_ERASE_TYPES_DEFINE(inst) \ + static const struct jesd216_erase_type \ + dev##inst##_erase_types[JESD216_NUM_ERASE_TYPES] = \ + {{ .cmd = SPI_NOR_CMD_SE, \ + .exp = 0x0C }}; \ + static const struct jesd216_erase_type \ + dev##inst##_erase_types_4b[JESD216_NUM_ERASE_TYPES] = \ + {{ .cmd = SPI_NOR_CMD_SE_4B, \ + .exp = 0x0C }} + +#define DEFAULT_ERASE_TYPES(inst) \ + USES_4BYTE_ADDR(inst) ? dev##inst##_erase_types_4b \ + : dev##inst##_erase_types + +#define DEFAULT_SWITCH_INFO(inst) { \ + .quad_enable_req = DT_INST_ENUM_IDX_OR(inst, quad_enable_requirements, \ + JESD216_DW15_QER_VAL_NONE), \ + .octal_enable_req = OCTAL_ENABLE_REQ_NONE, \ + .enter_4byte_addr = ENTER_4BYTE_ADDR_NONE } + +#define FLASH_SIZE(inst) (DT_INST_PROP(inst, size) / 8) + +#define FLASH_PAGE_SIZE(inst) SPI_NOR_PAGE_SIZE + +#define SFDP_BUILD_ASSERTS(inst) + +#endif /* CONFIG_FLASH_MSPI_NOR_USE_SFDP */ diff --git a/drivers/flash/flash_renesas_ra_qspi.c b/drivers/flash/flash_renesas_ra_qspi.c new file mode 100644 index 0000000000000..aa3b56c164879 --- /dev/null +++ b/drivers/flash/flash_renesas_ra_qspi.c @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2024-2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define DT_DRV_COMPAT renesas_ra_qspi_nor + +#include +#include +#include +#include +#include +#include +#include "spi_nor.h" +#include "r_spi_flash_api.h" +#include "r_qspi.h" + +/* Flash QPI (4-4-4) opcodes */ +#define QSPI_QPI_CMD_QPIID (0xAF) /* QPI ID Read */ +#define QSPI_QPI_CMD_RDSFDP (0x5A) /* Read SFDP */ +#define QSPI_QPI_CMD_RSTQIO (0xF5) /* Reset QPI */ +#define QSPI_QPI_CMD_EQIO (0x35) /* Enable QPI */ + +/* XIP (Execute In Place) mode */ +#define QSPI_CMD_XIP_ENTER (0x20) /* XIP Enter command */ +#define QSPI_CMD_XIP_EXIT (0xFF) /* XIP Exit command */ + +#define WRITE_STATUS_BIT 0 + +#if defined(CONFIG_SOC_SERIES_RA6E2) +#define STATUS_REG_PAYLOAD {0x01, 0x00} +#define SET_SREG_VALUE (0x00) +#else +#define STATUS_REG_PAYLOAD {0x01, 0x40, 0x00} +#define SET_SREG_VALUE (0x40) +#endif +/* one byte data transfer */ +#define ONE_BYTE (1) +#define THREE_BYTE (3) +#define FOUR_BYTE (4) +#define RESET_VALUE (0x00) +/* default memory value */ +#define QSPI_DEFAULT_MEM_VAL (0xFF) +#define QSPI0_NODE DT_INST_PARENT(0) +#define RA_QSPI_NOR_NODE DT_INST(0, renesas_ra_qspi_nor) +#define QSPI_WRITE_BLK_SZ DT_PROP(RA_QSPI_NOR_NODE, write_block_size) +#define QSPI_ERASE_BLK_SZ DT_PROP(RA_QSPI_NOR_NODE, erase_block_size) +/* QSPI flash page Size */ +#define PAGE_SIZE_BYTE SPI_NOR_PAGE_SIZE +/* sector size of QSPI flash device */ +#define BLOCK_SIZE_4K (4096U) +#define BLOCK_SIZE_32K (32768U) +#define BLOCK_SIZE_64K (65536U) + +/* Flash Size*/ +#define QSPI_NOR_FLASH_SIZE DT_REG_SIZE(RA_QSPI_NOR_NODE) + +#define ERASE_COMMAND_LENGTH(arr) (sizeof(arr) / sizeof((arr)[0])) + +#define QSPI_ENABLE_QUAD_MODE DT_PROP(RA_QSPI_NOR_NODE, qpi_enable) + +PINCTRL_DT_DEFINE(QSPI0_NODE); +LOG_MODULE_REGISTER(flash_qspi_renesas_ra, CONFIG_FLASH_LOG_LEVEL); + +struct qspi_flash_ra_data { + struct st_qspi_instance_ctrl qspi_ctrl; + struct st_spi_flash_cfg qspi_cfg; + struct k_sem sem; +}; + +struct ra_qspi_nor_flash_config { + const struct pinctrl_dev_config *pcfg; +}; + +static const spi_flash_erase_command_t g_qspi_erase_command_list[4] = { + {.command = 0x20, .size = 4096}, + {.command = 0x52, .size = 32768}, + {.command = 0xD8, .size = 65536}, + {.command = 0xC7, .size = SPI_FLASH_ERASE_SIZE_CHIP_ERASE}, +}; + +static const struct ra_qspi_nor_flash_config qspi_nor_dev_config = { + .pcfg = PINCTRL_DT_DEV_CONFIG_GET(QSPI0_NODE), +}; + +static const struct flash_parameters qspi_flash_ra_config_para = { + .write_block_size = QSPI_WRITE_BLK_SZ, + .erase_value = 0xff, +}; + +static const qspi_extended_cfg_t g_qspi_extended_cfg = { + .min_qssl_deselect_cycles = QSPI_QSSL_MIN_HIGH_LEVEL_8_QSPCLK, + .qspclk_div = QSPI_QSPCLK_DIV_2, +}; + +static struct qspi_flash_ra_data qspi_flash_data = { + .qspi_cfg = { + .spi_protocol = SPI_FLASH_PROTOCOL_EXTENDED_SPI, + .read_mode = SPI_FLASH_READ_MODE_FAST_READ_QUAD_IO, + .address_bytes = SPI_FLASH_ADDRESS_BYTES_3, + .dummy_clocks = SPI_FLASH_DUMMY_CLOCKS_DEFAULT, + .page_program_address_lines = SPI_FLASH_DATA_LINES_1, + .page_size_bytes = PAGE_SIZE_BYTE, + .page_program_command = (SPI_NOR_CMD_PP), + .write_enable_command = (SPI_NOR_CMD_WREN), + .status_command = (SPI_NOR_CMD_RDSR), + .write_status_bit = WRITE_STATUS_BIT, + .xip_enter_command = QSPI_CMD_XIP_ENTER, + .xip_exit_command = QSPI_CMD_XIP_EXIT, + .p_erase_command_list = &g_qspi_erase_command_list[0], + .erase_command_list_length = ERASE_COMMAND_LENGTH(g_qspi_erase_command_list), + .p_extend = &g_qspi_extended_cfg, + }}; + +static void acquire_device(const struct device *dev) +{ + struct qspi_flash_ra_data *dev_data = dev->data; + + k_sem_take(&dev_data->sem, K_FOREVER); +} + +static void release_device(const struct device *dev) +{ + struct qspi_flash_ra_data *dev_data = dev->data; + + k_sem_give(&dev_data->sem); +} +static int get_flash_status(const struct device *dev) +{ + struct qspi_flash_ra_data *qspi_data = dev->data; + spi_flash_status_t status = {.write_in_progress = true}; + int32_t time_out = (INT32_MAX); + int err; + + do { + err = R_QSPI_StatusGet(&qspi_data->qspi_ctrl, &status); + if (err != FSP_SUCCESS) { + LOG_ERR("Status get failed"); + return -EIO; + } + --time_out; + if (RESET_VALUE >= time_out) { + return -EIO; + } + } while (false != status.write_in_progress); + + return 0; +} + +#if defined(CONFIG_FLASH_EX_OP_ENABLED) +static int qspi_flash_ra_ex_op(const struct device *dev, uint16_t code, const uintptr_t in, + void *out) +{ + int err = 0; + uint8_t cmd; + struct qspi_flash_ra_data *qspi_data = dev->data; + + ARG_UNUSED(in); + ARG_UNUSED(out); + acquire_device(dev); + + switch (code) { + case QSPI_FLASH_EX_OP_EXIT_QPI: + if (SPI_FLASH_PROTOCOL_QPI != qspi_data->qspi_cfg.spi_protocol) { + err = 0; + break; + } + cmd = QSPI_QPI_CMD_RSTQIO; + err = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &cmd, ONE_BYTE, false); + if (err != FSP_SUCCESS) { + LOG_ERR("Direct write for EXIT QPI failed"); + err = -EIO; + } + break; + + case FLASH_EX_OP_RESET: + cmd = SPI_NOR_CMD_RESET_EN; + err = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &cmd, ONE_BYTE, false); + if (err == FSP_SUCCESS) { + cmd = SPI_NOR_CMD_RESET_MEM; + err = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &cmd, ONE_BYTE, false); + if (err != FSP_SUCCESS) { + LOG_ERR("Direct write for RESET MEM failed"); + err = -EIO; + } + } else { + if (err != FSP_SUCCESS) { + LOG_ERR("Direct write for RESET Flash failed"); + err = -EIO; + } + } + break; + default: + break; + } + release_device(dev); + + return err; +} +#endif + +#if CONFIG_FLASH_PAGE_LAYOUT +static const struct flash_pages_layout qspi_flash_ra_layout = { + .pages_count = QSPI_NOR_FLASH_SIZE / QSPI_ERASE_BLK_SZ, + .pages_size = QSPI_ERASE_BLK_SZ, +}; + +void qspi_flash_ra_page_layout(const struct device *dev, const struct flash_pages_layout **layout, + size_t *layout_size) +{ + ARG_UNUSED(dev); + *layout = &qspi_flash_ra_layout; + *layout_size = 1; +} +#endif /* CONFIG_FLASH_PAGE_LAYOUT */ + +#if defined(CONFIG_FLASH_JESD216_API) +static int qspi_flash_ra_read_jedec_id(const struct device *dev, uint8_t *id) +{ + struct qspi_flash_ra_data *qspi_data = dev->data; + int err = 0; + uint8_t cmd; + + if (id == NULL) { + return -EINVAL; + } + acquire_device(dev); + + if (SPI_FLASH_PROTOCOL_QPI == qspi_data->qspi_cfg.spi_protocol) { + cmd = QSPI_QPI_CMD_QPIID; + } else { + cmd = SPI_NOR_CMD_RDID; + } + err = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &cmd, ONE_BYTE, true); + if (err != FSP_SUCCESS) { + LOG_ERR("Direct write for READ ID failed"); + err = -EIO; + goto out; + } + + err = R_QSPI_DirectRead(&qspi_data->qspi_ctrl, id, THREE_BYTE); + if (err != FSP_SUCCESS) { + LOG_ERR("Direct read failed"); + err = -EIO; + goto out; + } + + err = get_flash_status(dev); + if (err != FSP_SUCCESS) { + LOG_ERR("Failed to get status for QSPI operation"); + err = -EIO; + } +out: + release_device(dev); + + return err; +} + +static int qspi_flash_ra_sfdp_read(const struct device *dev, off_t addr, void *data, size_t size) +{ + struct qspi_flash_ra_data *qspi_data = dev->data; + int err = 0; + uint8_t offset; + + SPI_FLASH_PROTOCOL_QPI == qspi_data->qspi_cfg.spi_protocol ? (offset = 4) : (offset = 1); + uint8_t *buffer = k_malloc((size + offset) > 4 ? (size + offset) : 4); + + if (!buffer) { + LOG_ERR("Failed to allocate buffer for SFDP read"); + return -ENOMEM; + } + + acquire_device(dev); + memset(&buffer[0], 0, sizeof(buffer)); + buffer[0] = QSPI_QPI_CMD_RDSFDP; + buffer[1] = addr; + buffer[2] = addr >> 8; + buffer[3] = addr >> 16; + + err = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &buffer[0], FOUR_BYTE, true); + if (err != FSP_SUCCESS) { + LOG_ERR("Direct write for READ SFDP failed"); + err = -EIO; + goto out; + } + + err = R_QSPI_DirectRead(&qspi_data->qspi_ctrl, &buffer[0], size + offset); + if (err != FSP_SUCCESS) { + LOG_ERR("Direct read failed"); + err = -EIO; + goto out; + } + + err = get_flash_status(dev); + if (err != FSP_SUCCESS) { + LOG_ERR("Failed to get status for QSPI operation"); + err = -EIO; + goto out; + } + + if (SPI_FLASH_PROTOCOL_QPI == qspi_data->qspi_cfg.spi_protocol) { + /* 3 dummy byte */ + memcpy(data, &buffer[4], size); + } else { + /* 1 dummy byte */ + memcpy(data, &buffer[1], size); + } +out: + release_device(dev); + return err; +} +#endif + +static bool qspi_flash_ra_valid(off_t area_size, off_t offset, size_t len) +{ + if ((offset < 0) || (offset >= area_size) || ((area_size - offset) < len)) { + return false; + } + + return true; +} + +static int qspi_flash_ra_erase(const struct device *dev, off_t offset, size_t len) +{ + struct qspi_flash_ra_data *qspi_data = dev->data; + int err = 0; + struct flash_pages_info page_info_start, page_info_end; + uint32_t erase_size; + int rc; + + if (!len) { + return 0; + } + + if (!qspi_flash_ra_valid(QSPI_NOR_FLASH_SIZE, offset, len)) { + LOG_ERR("The offset 0x%lx is invalid", (long)offset); + return -EINVAL; + } + + if (len % QSPI_ERASE_BLK_SZ != 0) { + LOG_ERR("The size %u is not align with block size (%u)", len, QSPI_ERASE_BLK_SZ); + return -EINVAL; + } + + rc = flash_get_page_info_by_offs(dev, offset, &page_info_start); + if ((rc != 0) || (offset != page_info_start.start_offset)) { + LOG_ERR("The offset 0x%lx is not aligned with the starting sector", (long)offset); + return -EINVAL; + } + + rc = flash_get_page_info_by_offs(dev, (offset + len), &page_info_end); + if ((rc != 0) || ((offset + len) != page_info_end.start_offset)) { + LOG_ERR("The size %u is not aligned with the ending sector", len); + return -EINVAL; + } + + acquire_device(dev); + while (len > 0) { + + if (len < BLOCK_SIZE_32K) { + erase_size = BLOCK_SIZE_4K; + } else if (len < BLOCK_SIZE_64K) { + erase_size = BLOCK_SIZE_32K; + } else { + erase_size = BLOCK_SIZE_64K; + } + err = R_QSPI_Erase(&qspi_data->qspi_ctrl, + (uint8_t *)(QSPI_DEVICE_START_ADDRESS + offset), erase_size); + if (err) { + LOG_ERR("Erase failed"); + err = -EIO; + break; + } + + err = get_flash_status(dev); + if (err) { + LOG_ERR("failed to get status for QSPI operation"); + err = -EIO; + break; + } + + offset += erase_size; + len -= erase_size; + } + release_device(dev); + + return err; +} + +static int qspi_flash_ra_read(const struct device *dev, off_t offset, void *data, size_t len) +{ + if (!len) { + return 0; + } + + if (!qspi_flash_ra_valid(QSPI_NOR_FLASH_SIZE, offset, len)) { + return -EINVAL; + } + + acquire_device(dev); + + memcpy(data, (uint8_t *)(QSPI_DEVICE_START_ADDRESS + offset), len); + release_device(dev); + + return 0; +} + +static int qspi_flash_ra_write(const struct device *dev, off_t offset, const void *data, size_t len) +{ + struct qspi_flash_ra_data *qspi_data = dev->data; + int err = 0; + uint32_t remaining_bytes = len; + const uint8_t *p_data = data; + uint32_t size = len; + + if (!len) { + return 0; + } + + if (!qspi_flash_ra_valid(QSPI_NOR_FLASH_SIZE, offset, len)) { + return -EINVAL; + } + + acquire_device(dev); + while (remaining_bytes > 0) { + size = remaining_bytes > PAGE_SIZE_BYTE ? PAGE_SIZE_BYTE : remaining_bytes; + err = R_QSPI_Write(&qspi_data->qspi_ctrl, p_data, + (uint8_t *)(QSPI_DEVICE_START_ADDRESS + offset), size); + if (err) { + LOG_ERR("Direct write failed"); + err = -EIO; + break; + } + + err = get_flash_status(dev); + if (err) { + LOG_ERR("Failed to get status for QSPI operation"); + err = -EIO; + break; + } + + remaining_bytes -= size; + offset += size; + p_data += size; + } + release_device(dev); + return err; +} + +static int qspi_flash_ra_get_size(const struct device *dev, uint64_t *size) +{ + *size = (uint64_t)QSPI_NOR_FLASH_SIZE; + + return 0; +} + +static const struct flash_parameters *qspi_flash_ra_get_parameters(const struct device *dev) +{ + ARG_UNUSED(dev); + + return &qspi_flash_ra_config_para; +} +static const struct flash_driver_api qspi_flash_ra_api = { + .erase = qspi_flash_ra_erase, + .write = qspi_flash_ra_write, + .read = qspi_flash_ra_read, + .get_parameters = qspi_flash_ra_get_parameters, + .get_size = qspi_flash_ra_get_size, +#ifdef CONFIG_FLASH_PAGE_LAYOUT + .page_layout = qspi_flash_ra_page_layout, +#endif +#if defined(CONFIG_FLASH_JESD216_API) + .sfdp_read = qspi_flash_ra_sfdp_read, + .read_jedec_id = qspi_flash_ra_read_jedec_id, +#endif +#if defined(CONFIG_FLASH_EX_OP_ENABLED) + .ex_op = qspi_flash_ra_ex_op, +#endif /* CONFIG_FLASH_EX_OP_ENABLED */ +}; + +static int set_qspi_flash_status(const struct device *dev) +{ + struct qspi_flash_ra_data *qspi_data = dev->data; + uint8_t data_sreg[] = STATUS_REG_PAYLOAD; + uint8_t sreg_data = 0; + int ret; + + ret = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, data_sreg, sizeof(data_sreg), false); + if (ret) { + LOG_ERR("Direct write for STATUS_REG_PAYLOAD fail"); + return -EIO; + } + + ret = get_flash_status(dev); + if (ret) { + LOG_ERR("Failed to get status for QSPI operation"); + return -EIO; + } + ret = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &(qspi_data->qspi_cfg.status_command), + ONE_BYTE, true); + if (ret) { + LOG_ERR("Direct write for status command fail "); + return -EIO; + } + + ret = R_QSPI_DirectRead(&qspi_data->qspi_ctrl, &sreg_data, ONE_BYTE); + if (ret) { + LOG_ERR("Direct read fail"); + return -EIO; + } + + if (SET_SREG_VALUE != sreg_data) { + LOG_ERR("Verify status register data failed"); + return -EIO; + } + return ret; +} + +static int qspi_flash_ra_init(const struct device *dev) +{ + const struct ra_qspi_nor_flash_config *config = dev->config; + struct qspi_flash_ra_data *qspi_data = dev->data; + int ret; + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret) { + LOG_ERR("Failed to configure pins for QSPI"); + return -EIO; + } + k_sem_init(&qspi_data->sem, 1, 1); + + ret = R_QSPI_Open(&qspi_data->qspi_ctrl, &qspi_data->qspi_cfg); + if (ret) { + LOG_ERR("Open failed"); + return -EIO; + } + + ret = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &(qspi_data->qspi_cfg.write_enable_command), + ONE_BYTE, false); + if (ret) { + LOG_ERR("Direct write enable command failed"); + return -EIO; + } + + ret = get_flash_status(dev); + if (ret) { + LOG_ERR("Failed to get status for QSPI operation"); + return -EIO; + } + + ret = set_qspi_flash_status(dev); + if (ret) { + LOG_ERR("Set qspi flash status failed"); + return -EIO; + } +#if QSPI_ENABLE_QUAD_MODE + uint8_t data_qpi_en = QSPI_QPI_CMD_EQIO; + + qspi_data->qspi_cfg.spi_protocol = SPI_FLASH_PROTOCOL_QPI; + ret = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &data_qpi_en, ONE_BYTE, false); + if (ret) { + LOG_ERR("Direct write SPI_FLASH_PROTOCOL_QPI failed"); + return -EIO; + } + + ret = R_QSPI_SpiProtocolSet(&qspi_data->qspi_ctrl, SPI_FLASH_PROTOCOL_QPI); + if (ret) { + LOG_ERR("Set SpiProtocol failed"); + return -EIO; + } +#endif + + return 0; +} + +DEVICE_DT_INST_DEFINE(0, qspi_flash_ra_init, NULL, &qspi_flash_data, &qspi_nor_dev_config, + POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, &qspi_flash_ra_api); diff --git a/drivers/flash/flash_sam0.c b/drivers/flash/flash_sam0.c index b393249646056..12718435f9ee2 100644 --- a/drivers/flash/flash_sam0.c +++ b/drivers/flash/flash_sam0.c @@ -224,7 +224,7 @@ static int flash_sam0_commit(const struct device *dev, off_t base) for (page = 0; page < PAGES_PER_ROW; page++) { err = flash_sam0_write_page( dev, base + page * FLASH_PAGE_SIZE, - &ctx->buf[page * FLASH_PAGE_SIZE], ROW_SIZE); + &ctx->buf[page * FLASH_PAGE_SIZE], FLASH_PAGE_SIZE); if (err != 0) { return err; } diff --git a/drivers/flash/flash_shell.c b/drivers/flash/flash_shell.c index 068a108fc9124..3ec97cd02090e 100644 --- a/drivers/flash/flash_shell.c +++ b/drivers/flash/flash_shell.c @@ -732,6 +732,19 @@ static int cmd_page_info(const struct shell *sh, size_t argc, char *argv[]) return 0; } +#if DT_HAS_COMPAT_STATUS_OKAY(fixed_partitions) +#define PRINT_PARTITION_INFO(part) \ + shell_print(sh, "%-32s %-15s 0x%08x %d KiB", DT_NODE_FULL_NAME(part), \ + DT_PROP_OR(part, label, ""), DT_REG_ADDR(part), DT_REG_SIZE(part) / 1024); + +static int cmd_partitions(const struct shell *sh, size_t argc, char *argv[]) +{ + DT_FOREACH_CHILD(DT_COMPAT_GET_ANY_STATUS_OKAY(fixed_partitions), PRINT_PARTITION_INFO); + + return 0; +} +#endif + static void device_name_get(size_t idx, struct shell_static_entry *entry); SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get); @@ -774,6 +787,12 @@ SHELL_STATIC_SUBCMD_SET_CREATE(flash_cmds, "[]
", cmd_page_info, 2, 1), +#if DT_HAS_COMPAT_STATUS_OKAY(fixed_partitions) + SHELL_CMD_ARG(partitions, &dsub_device_name, + "", + cmd_partitions, 0, 0), +#endif + #ifdef CONFIG_FLASH_SHELL_TEST_COMMANDS SHELL_CMD_ARG(read_test, &dsub_device_name, "[]
", diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index 7c0eee1234ad4..ddcdc1390388a 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -1702,11 +1702,21 @@ static void flash_stm32_ospi_pages_layout(const struct device *dev, } #endif +static int flash_stm32_ospi_get_size(const struct device *dev, uint64_t *size) +{ + const struct flash_stm32_ospi_config *dev_cfg = dev->config; + + *size = (uint64_t)dev_cfg->flash_size; + + return 0; +} + static DEVICE_API(flash, flash_stm32_ospi_driver_api) = { .read = flash_stm32_ospi_read, .write = flash_stm32_ospi_write, .erase = flash_stm32_ospi_erase, .get_parameters = flash_stm32_ospi_get_parameters, + .get_size = flash_stm32_ospi_get_size, #if defined(CONFIG_FLASH_PAGE_LAYOUT) .page_layout = flash_stm32_ospi_pages_layout, #endif @@ -2219,12 +2229,9 @@ static int flash_stm32_ospi_init(const struct device *dev) dma_cfg.user_data = &hdma; /* HACK: This field is used to inform driver that it is overridden */ dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE; - /* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */ - ret = dma_config(dev_data->dma.dev, - (dev_data->dma.channel + STM32_DMA_STREAM_OFFSET), &dma_cfg); + ret = dma_config(dev_data->dma.dev, dev_data->dma.channel, &dma_cfg); if (ret != 0) { - LOG_ERR("Failed to configure DMA channel %d", - dev_data->dma.channel + STM32_DMA_STREAM_OFFSET); + LOG_ERR("Failed to configure DMA channel %d", dev_data->dma.channel); return ret; } @@ -2256,27 +2263,12 @@ static int flash_stm32_ospi_init(const struct device *dev) hdma.Init.Mode = DMA_NORMAL; hdma.Init.Priority = table_priority[dma_cfg.channel_priority]; hdma.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma.Instance = STM32_DMA_GET_INSTANCE(dev_data->dma.reg, dev_data->dma.channel); #ifdef CONFIG_DMA_STM32_V1 /* TODO: Not tested in this configuration */ hdma.Init.Channel = dma_cfg.dma_slot; - hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(dev_data->dma.reg, - dev_data->dma.channel); #else hdma.Init.Request = dma_cfg.dma_slot; -#if CONFIG_DMA_STM32U5 - hdma.Instance = LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg, - dev_data->dma.channel); -#elif defined(CONFIG_DMAMUX_STM32) - /* - * HAL expects a valid DMA channel (not DMAMUX). - * The channel is from 0 to 7 because of the STM32_DMA_STREAM_OFFSET in the dma_stm32 driver - */ - hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg, - dev_data->dma.channel); -#else - hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg, - dev_data->dma.channel-1); -#endif /* CONFIG_DMA_STM32U5 */ #endif /* CONFIG_DMA_STM32_V1 */ /* Initialize DMA HAL */ diff --git a/drivers/flash/flash_stm32_qspi.c b/drivers/flash/flash_stm32_qspi.c index fca6f0d8cb7f8..cf348d5cfb355 100644 --- a/drivers/flash/flash_stm32_qspi.c +++ b/drivers/flash/flash_stm32_qspi.c @@ -1592,21 +1592,12 @@ static int flash_stm32_qspi_init(const struct device *dev) hdma.Init.MemInc = DMA_MINC_ENABLE; hdma.Init.Mode = DMA_NORMAL; hdma.Init.Priority = table_priority[dma_cfg.channel_priority]; + hdma.Instance = STM32_DMA_GET_INSTANCE(dev_data->dma.reg, dev_data->dma.channel); #ifdef CONFIG_DMA_STM32_V1 /* TODO: Not tested in this configuration */ hdma.Init.Channel = dma_cfg.dma_slot; - hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(dev_data->dma.reg, - dev_data->dma.channel); #else hdma.Init.Request = dma_cfg.dma_slot; -#ifdef CONFIG_DMAMUX_STM32 - /* HAL expects a valid DMA channel (not a DMAMUX channel) */ - hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg, - dev_data->dma.channel); -#else - hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg, - dev_data->dma.channel-1); -#endif #endif /* CONFIG_DMA_STM32_V1 */ /* Initialize DMA HAL */ diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c index 6ff3262598502..043b2dc138757 100644 --- a/drivers/flash/flash_stm32_xspi.c +++ b/drivers/flash/flash_stm32_xspi.c @@ -568,11 +568,20 @@ static int stm32_xspi_write_enable(const struct device *dev, } /* Write Flash configuration register 2 with new dummy cycles */ -static int stm32_xspi_write_cfg2reg_dummy(XSPI_HandleTypeDef *hxspi, +static int stm32_xspi_write_cfg2reg_dummy(const struct device *dev, uint8_t nor_mode, uint8_t nor_rate) { - uint8_t transmit_data = SPI_NOR_CR2_DUMMY_CYCLES_66MHZ; XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate); + const struct flash_stm32_xspi_config *dev_cfg = dev->config; + struct flash_stm32_xspi_data *dev_data = dev->data; + uint8_t transmit_data; + + if (dev_cfg->max_frequency == MHZ(200)) { + /* Use memory default value */ + return 0; + } + + transmit_data = SPI_NOR_CR2_DUMMY_CYCLES_66MHZ; /* Initialize the writing of configuration register 2 */ s_command.Instruction = (nor_mode == XSPI_SPI_MODE) @@ -583,13 +592,13 @@ static int stm32_xspi_write_cfg2reg_dummy(XSPI_HandleTypeDef *hxspi, s_command.DataLength = (nor_mode == XSPI_SPI_MODE) ? 1U : ((nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U); - if (HAL_XSPI_Command(hxspi, &s_command, + if (HAL_XSPI_Command(&dev_data->hxspi, &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { LOG_ERR("XSPI transmit cmd"); return -EIO; } - if (HAL_XSPI_Transmit(hxspi, &transmit_data, + if (HAL_XSPI_Transmit(&dev_data->hxspi, &transmit_data, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { LOG_ERR("XSPI transmit "); return -EIO; @@ -683,7 +692,7 @@ static int stm32_xspi_config_mem(const struct device *dev) } /* Write Configuration register 2 (with new dummy cycles) */ - if (stm32_xspi_write_cfg2reg_dummy(&dev_data->hxspi, + if (stm32_xspi_write_cfg2reg_dummy(dev, XSPI_SPI_MODE, XSPI_STR_TRANSFER) != 0) { LOG_ERR("XSPI write CFGR2 failed"); return -EIO; @@ -1035,7 +1044,7 @@ static int flash_stm32_xspi_erase(const struct device *dev, off_t addr, goto erase_end; } } -#endif +#endif /* CONFIG_STM32_MEMMAP */ XSPI_RegularCmdTypeDef cmd_erase = { .OperationType = HAL_XSPI_OPTYPE_COMMON_CFG, @@ -1173,7 +1182,7 @@ static int flash_stm32_xspi_read(const struct device *dev, off_t addr, { const struct flash_stm32_xspi_config *dev_cfg = dev->config; struct flash_stm32_xspi_data *dev_data = dev->data; - int ret; + int ret = 0; if (!xspi_address_is_valid(dev, addr, size)) { LOG_ERR("Error: address or size exceeds expected values: " @@ -1186,29 +1195,31 @@ static int flash_stm32_xspi_read(const struct device *dev, off_t addr, return 0; } -#ifdef CONFIG_STM32_MEMMAP +#if defined(CONFIG_STM32_MEMMAP) || defined(CONFIG_STM32_APP_IN_EXT_FLASH) ARG_UNUSED(dev_cfg); ARG_UNUSED(dev_data); - - xspi_lock_thread(dev); + /* + * When the call is made by an app executing in external flash, + * skip the memory-mapped mode check + */ +#ifdef CONFIG_STM32_MEMMAP /* Do reads through memory-mapping instead of indirect */ if (!stm32_xspi_is_memorymap(dev)) { ret = stm32_xspi_set_memorymap(dev); if (ret != 0) { LOG_ERR("READ: failed to set memory mapped"); - goto read_end; + return ret; } } __ASSERT_NO_MSG(stm32_xspi_is_memorymap(dev)); - +#endif /* CONFIG_STM32_MEMMAP */ uintptr_t mmap_addr = STM32_XSPI_BASE_ADDRESS + addr; LOG_DBG("Memory-mapped read from 0x%08lx, len %zu", mmap_addr, size); memcpy(data, (void *)mmap_addr, size); - ret = 0; - goto read_end; + return ret; #else XSPI_RegularCmdTypeDef cmd = xspi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate); @@ -1274,13 +1285,10 @@ static int flash_stm32_xspi_read(const struct device *dev, off_t addr, xspi_lock_thread(dev); ret = xspi_read_access(dev, &cmd, data, size); - goto read_end; -#endif - -read_end: xspi_unlock_thread(dev); return ret; +#endif /* CONFIG_STM32_MEMMAP || CONFIG_STM32_APP_IN_EXT_FLASH */ } /* Function to write the flash (page program) : with possible OCTO/SPI and STR/DTR */ @@ -1563,11 +1571,21 @@ static void flash_stm32_xspi_pages_layout(const struct device *dev, } #endif +static int flash_stm32_xspi_get_size(const struct device *dev, uint64_t *size) +{ + const struct flash_stm32_xspi_config *dev_cfg = dev->config; + + *size = (uint64_t)dev_cfg->flash_size; + + return 0; +} + static DEVICE_API(flash, flash_stm32_xspi_driver_api) = { .read = flash_stm32_xspi_read, .write = flash_stm32_xspi_write, .erase = flash_stm32_xspi_erase, .get_parameters = flash_stm32_xspi_get_parameters, + .get_size = flash_stm32_xspi_get_size, #if defined(CONFIG_FLASH_PAGE_LAYOUT) .page_layout = flash_stm32_xspi_pages_layout, #endif @@ -1977,12 +1995,9 @@ static int flash_stm32_xspi_dma_init(DMA_HandleTypeDef *hdma, struct stream *dma dma_stream->cfg.user_data = hdma; /* HACK: This field is used to inform driver that it is overridden */ dma_stream->cfg.linked_channel = STM32_DMA_HAL_OVERRIDE; - /* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */ - ret = dma_config(dma_stream->dev, - (dma_stream->channel + STM32_DMA_STREAM_OFFSET), &dma_stream->cfg); + ret = dma_config(dma_stream->dev, dma_stream->channel, &dma_stream->cfg); if (ret != 0) { - LOG_ERR("Failed to configure DMA channel %d", - dma_stream->channel + STM32_DMA_STREAM_OFFSET); + LOG_ERR("Failed to configure DMA channel %d", dma_stream->channel); return ret; } diff --git a/drivers/flash/nrf_qspi_nor.c b/drivers/flash/nrf_qspi_nor.c index 730a220a9892b..e9eb5a17302ba 100644 --- a/drivers/flash/nrf_qspi_nor.c +++ b/drivers/flash/nrf_qspi_nor.c @@ -59,6 +59,12 @@ struct qspi_nor_config { const struct pinctrl_dev_config *pcfg; }; +#ifdef CONFIG_NORDIC_QSPI_NOR_ACTIVE_DWELL_MS +#define ACTIVE_DWELL_MS CONFIG_NORDIC_QSPI_NOR_ACTIVE_DWELL_MS +#else +#define ACTIVE_DWELL_MS 0 +#endif + /* Status register bits */ #define QSPI_SECTOR_SIZE SPI_NOR_SECTOR_SIZE #define QSPI_BLOCK_SIZE SPI_NOR_BLOCK_SIZE @@ -363,7 +369,7 @@ static void qspi_release(const struct device *dev) qspi_unlock(dev); - rc = pm_device_runtime_put(dev); + rc = pm_device_runtime_put_async(dev, K_MSEC(ACTIVE_DWELL_MS)); if (rc < 0) { LOG_ERR("pm_device_runtime_put failed: %d", rc); } diff --git a/drivers/flash/spi_flash_at25xv021a.c b/drivers/flash/spi_flash_at25xv021a.c new file mode 100644 index 0000000000000..07b6da95e90b0 --- /dev/null +++ b/drivers/flash/spi_flash_at25xv021a.c @@ -0,0 +1,993 @@ +/* + * Copyright (c) 2025 Cirrus Logic, Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Driver for AT25XV021A SPI flash devices, a variant of Atmel's AT25 family + */ + +#define DT_DRV_COMPAT atmel_at25xv021a + +#include +#include +#include +#include +#include +#include + +#include +LOG_MODULE_REGISTER(spi_flash_at25xv021a, CONFIG_FLASH_LOG_LEVEL); + +/* AT25XV021A opcodes */ +#define DEV_READ (0x0b) +#define DEV_PAGE_ERASE (0x81) +#define DEV_CHIP_ERASE (0x60) +#define DEV_WRITE (0x02) +#define DEV_WRITE_ENABLE (0x06) +#define DEV_PROTECT (0x36) +#define DEV_UNPROTECT (0x39) +#define DEV_READ_SR (0x05) +#define DEV_WRITE_SR (0x01) +#define DEV_READ_DEVICE_INFO (0x9f) +#define DEV_DEEP_SLEEP (0xb9) +#define DEV_ULTRA_DEEP_SLEEP (0x79) +#define DEV_RESUME (0xab) + +/* AT25XV021A driver instruction set */ +#define DEV_DUMMY_BYTE (0x00) +#define DEV_HW_LOCK (0xf8) +#define DEV_HW_UNLOCK (0x00) +#define DEV_GLOBAL_PROTECT (0x7f) +#define DEV_GLOBAL_UNPROTECT (0x00) + +/* AT25XV021A status register masks */ +#define DEV_SR_BUSY (1U << 0) +#define DEV_SR_WEL (1U << 1) +#define DEV_SR_SWP (3U << 2) +#define DEV_SR_WPP (1U << 4) +#define DEV_SR_EPE (1U << 5) +#define DEV_SR_SPRL (1U << 7) + +#define ANY_DEV_WRITEABLE !DT_ALL_INST_HAS_BOOL_STATUS_OKAY(read_only) +#define ANY_DEV_HAS_WP_GPIO DT_ANY_INST_HAS_PROP_STATUS_OKAY(wp_gpios) + +struct flash_at25xv021a_config { + struct spi_dt_spec spi; +#if ANY_DEV_HAS_WP_GPIO + struct gpio_dt_spec wp_gpio; +#endif /* ANY_DEV_HAS_WP_GPIO */ +#if defined(CONFIG_FLASH_PAGE_LAYOUT) + struct flash_pages_layout pages_layout; +#endif /* defined(CONFIG_FLASH_PAGE_LAYOUT) */ + struct flash_parameters parameters; + uint8_t jedec_id[3]; + size_t size; + k_timeout_t timeout; + bool read_only; + bool ultra_deep_sleep; +#if ANY_DEV_WRITEABLE + size_t page_size; + k_timeout_t timeout_erase; +#endif /* ANY_DEV_WRITEABLE */ +}; + +struct flash_at25xv021a_data { + struct k_mutex lock; +}; + +static int flash_at25xv021a_read_status(const struct device *dev, uint8_t *status) +{ + int err; + uint8_t sr[2]; + uint8_t cmd[2] = {DEV_READ_SR, DEV_DUMMY_BYTE}; + const struct flash_at25xv021a_config *config = dev->config; + const struct spi_buf tx_buf = {.buf = cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + const struct spi_buf rx_buf = {.buf = sr, .len = ARRAY_SIZE(sr)}; + const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1}; + + err = spi_transceive_dt(&config->spi, &tx, &rx); + if (err < 0) { + LOG_ERR("unable to read status register from %s", dev->name); + return err; + } + + *status = sr[1]; + + return err; +} + +static int flash_at25xv021a_wait_for_idle(const struct device *dev, k_timeout_t timeout) +{ + int err; + uint8_t status; + k_timepoint_t end = sys_timepoint_calc(timeout); + + while (!sys_timepoint_expired(end)) { + err = flash_at25xv021a_read_status(dev, &status); + if (err != 0) { + return err; + } + + if ((status & DEV_SR_BUSY) == 0) { + return 0; + } + + k_msleep(1); + } + + LOG_ERR("timed out waiting for %s to idle", dev->name); + return -EBUSY; +} + +static int flash_at25xv021a_spi_transceive(const struct device *dev, const struct spi_dt_spec *spi, + const struct spi_buf_set *tx, + const struct spi_buf_set *rx) +{ + int err; + const struct flash_at25xv021a_config *config = dev->config; + + err = flash_at25xv021a_wait_for_idle(dev, config->timeout); + if (err != 0) { + return err; + } + + err = spi_transceive_dt(spi, tx, rx); + if (err < 0) { + LOG_ERR("unable to read from %s", dev->name); + } + + return err; +} + +static int flash_at25xv021a_verify_device(const struct device *dev) +{ + int err; + uint8_t info[3]; + uint8_t cmd[1] = {DEV_READ_DEVICE_INFO}; + const struct flash_at25xv021a_config *config = dev->config; + const struct spi_buf tx_buf = {.buf = cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + const struct spi_buf rx_bufs[2] = { + {.buf = NULL, .len = ARRAY_SIZE(cmd)}, + {.buf = info, .len = ARRAY_SIZE(info)}, + }; + const struct spi_buf_set rx = {.buffers = rx_bufs, .count = ARRAY_SIZE(rx_bufs)}; + + err = flash_at25xv021a_spi_transceive(dev, &config->spi, &tx, &rx); + if (err != 0) { + return err; + } + + if ((info[0] != config->jedec_id[0]) || (info[1] != config->jedec_id[1]) || + (info[2] != config->jedec_id[2])) { + return -ENODEV; + } + + return err; +} + +static int flash_at25xv021a_read_internal(const struct device *dev, off_t offset, void *buf, + size_t len) +{ + const struct flash_at25xv021a_config *config = dev->config; + uint8_t cmd[5] = { + DEV_READ, + FIELD_GET(GENMASK(23, 16), offset), + FIELD_GET(GENMASK(15, 8), offset), + FIELD_GET(GENMASK(7, 0), offset), + DEV_DUMMY_BYTE, + }; + const struct spi_buf tx_buf = {.buf = cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = { + .buffers = &tx_buf, + .count = 1, + }; + const struct spi_buf rx_bufs[2] = { + {.buf = NULL, .len = ARRAY_SIZE(cmd)}, + {.buf = buf, .len = len}, + }; + const struct spi_buf_set rx = {.buffers = rx_bufs, .count = ARRAY_SIZE(rx_bufs)}; + + return flash_at25xv021a_spi_transceive(dev, &config->spi, &tx, &rx); +} + +static int flash_at25xv021a_read(const struct device *dev, off_t offset, void *buf, size_t len) +{ + int err; + struct flash_at25xv021a_data *data = dev->data; + const struct flash_at25xv021a_config *config = dev->config; + + if (len == 0) { + LOG_DBG("attempted to read 0 bytes from %s", dev->name); + return 0; + } + + if (len > config->size) { + LOG_ERR("attempted to read more than device %s size: %u", dev->name, config->size); + return -EINVAL; + } + + k_mutex_lock(&data->lock, K_FOREVER); + + err = flash_at25xv021a_read_internal(dev, offset, buf, len); + + k_mutex_unlock(&data->lock); + + return err; +} + +#if ANY_DEV_WRITEABLE +static int flash_at25xv021a_check_status(const struct device *dev, uint8_t mask, uint8_t *status) +{ + int err; + uint8_t temp_status; + const struct flash_at25xv021a_config *config = dev->config; + + err = flash_at25xv021a_wait_for_idle(dev, config->timeout); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_read_status(dev, &temp_status); + if (err != 0) { + return err; + } + + *status = (temp_status & mask); + + return err; +} + +static int flash_at25xv021a_spi_write(const struct device *dev, const struct spi_dt_spec *spi, + const struct spi_buf_set *tx) +{ + int err; + const struct flash_at25xv021a_config *config = dev->config; + + err = flash_at25xv021a_wait_for_idle(dev, config->timeout); + if (err != 0) { + return err; + } + + err = spi_write_dt(spi, tx); + if (err < 0) { + LOG_ERR("unable to write to %s", dev->name); + } + + return err; +} + +static int flash_at25xv021a_write_enable(const struct device *dev) +{ + int err; + uint8_t status; + uint8_t cmd[1] = {DEV_WRITE_ENABLE}; + const struct flash_at25xv021a_config *config = dev->config; + const struct spi_buf tx_buf = {.buf = &cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, DEV_SR_WEL, &status); + if (err != 0) { + return err; + } + + if (status != DEV_SR_WEL) { + LOG_ERR("unable to enable writes on %s", dev->name); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_hardware_lock(const struct device *dev) +{ + int err; + uint8_t status; + uint8_t cmd[2] = {DEV_WRITE_SR, DEV_HW_LOCK}; + const struct flash_at25xv021a_config *config = dev->config; + const struct spi_buf tx_buf = {.buf = &cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + err = flash_at25xv021a_write_enable(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + /* Ensure device is idle before configuring WP pin. */ + err = flash_at25xv021a_wait_for_idle(dev, config->timeout); + if (err != 0) { + return err; + } + +#if ANY_DEV_HAS_WP_GPIO + err = gpio_pin_configure_dt(&config->wp_gpio, GPIO_OUTPUT_ACTIVE); + if (err < 0) { + LOG_ERR("unable to set WP GPIO"); + return err; + } +#endif /* ANY_DEV_HAS_WP_GPIOS */ + + err = flash_at25xv021a_check_status(dev, DEV_SR_SPRL, &status); + if (err != 0) { + return err; + } + + if (status != DEV_SR_SPRL) { + LOG_ERR("unable to lock hardware"); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_hardware_unlock(const struct device *dev) +{ + int err; + uint8_t status; + uint8_t cmd[2] = {DEV_WRITE_SR, DEV_HW_UNLOCK}; + const struct flash_at25xv021a_config *config = dev->config; + const struct spi_buf tx_buf = {.buf = &cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + /* Ensure device is idle before configuring WP pin. */ + err = flash_at25xv021a_wait_for_idle(dev, config->timeout); + if (err != 0) { + return err; + } + +#if ANY_DEV_HAS_WP_GPIO + err = gpio_pin_configure_dt(&config->wp_gpio, GPIO_OUTPUT_INACTIVE); + if (err < 0) { + LOG_ERR("unable to set WP GPIO"); + return err; + } +#endif /* ANY_DEV_HAS_WP_GPIO */ + + err = flash_at25xv021a_write_enable(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, DEV_SR_SPRL, &status); + if (err != 0) { + return err; + } + + if (status == DEV_SR_SPRL) { + LOG_ERR("unable to unlock hardware"); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_global_protection(const struct device *dev, uint8_t protection_cmd) +{ + int err; + uint8_t expected_status, status; + const struct flash_at25xv021a_config *config = dev->config; + uint8_t cmd[2] = {DEV_WRITE_SR, protection_cmd}; + const struct spi_buf tx_buf = {.buf = &cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + err = flash_at25xv021a_hardware_unlock(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_write_enable(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_hardware_lock(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, DEV_SR_SWP, &status); + if (err != 0) { + return err; + } + + expected_status = (protection_cmd == DEV_GLOBAL_PROTECT) ? DEV_SR_SWP : 0; + if (status != expected_status) { + LOG_ERR("unable to update global protection"); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_software_protection(const struct device *dev, off_t page, + uint8_t protection_cmd) +{ + int err; + uint8_t status; + uint8_t unexpected_status; + const struct flash_at25xv021a_config *config = dev->config; + uint8_t cmd[4] = { + protection_cmd, + FIELD_GET(GENMASK(23, 16), page), + FIELD_GET(GENMASK(15, 8), page), + FIELD_GET(GENMASK(7, 0), page), + }; + const struct spi_buf tx_buf = {.buf = &cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + err = flash_at25xv021a_hardware_unlock(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_write_enable(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_hardware_lock(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, DEV_SR_SWP, &status); + if (err != 0) { + return err; + } + + unexpected_status = (protection_cmd == DEV_PROTECT) ? 0 : DEV_SR_SWP; + if (status == unexpected_status) { + LOG_ERR("failed to update software protection for %s", dev->name); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_hardware_init(const struct device *dev) +{ + int err; + uint8_t status; + + err = flash_at25xv021a_hardware_unlock(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_global_protection(dev, DEV_GLOBAL_PROTECT); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_hardware_lock(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, (DEV_SR_SPRL | DEV_SR_SWP), &status); + if (err != 0) { + return err; + } + + if (status != (DEV_SR_SPRL | DEV_SR_SWP)) { + LOG_ERR("unable to initialize hardware"); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_write_internal(const struct device *dev, off_t offset, const void *buf, + size_t len) +{ + int err; + uint8_t status; + const struct flash_at25xv021a_config *config = dev->config; + uint8_t cmd[4] = { + DEV_WRITE, + FIELD_GET(GENMASK(23, 16), offset), + FIELD_GET(GENMASK(15, 8), offset), + FIELD_GET(GENMASK(7, 0), offset), + }; + const struct spi_buf tx_bufs[2] = { + {.buf = cmd, .len = ARRAY_SIZE(cmd)}, + {.buf = (void *)buf, .len = len}, + }; + const struct spi_buf_set tx = {.buffers = tx_bufs, .count = ARRAY_SIZE(tx_bufs)}; + + err = flash_at25xv021a_write_enable(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, DEV_SR_EPE, &status); + if (err != 0) { + return err; + } + + if (status != 0) { + LOG_ERR("failed to program %s", dev->name); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_process_write(const struct device *dev, off_t offset, const void *buf, + size_t len) +{ + int err; + const struct flash_at25xv021a_config *config = dev->config; + off_t page_start = ROUND_DOWN(offset, config->page_size); + + err = flash_at25xv021a_software_protection(dev, page_start, DEV_UNPROTECT); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_write_internal(dev, offset, buf, len); + if (err != 0) { + return err; + } + + return flash_at25xv021a_software_protection(dev, page_start, DEV_PROTECT); +} + +static int flash_at25xv021a_chip_erase(const struct device *dev) +{ + int err; + uint8_t status; + uint8_t cmd[1] = {DEV_CHIP_ERASE}; + const struct flash_at25xv021a_config *config = dev->config; + const struct spi_buf tx_buf = {.buf = &cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + err = flash_at25xv021a_global_protection(dev, DEV_GLOBAL_UNPROTECT); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_write_enable(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + /* Need to wait extra time for chip erase. */ + err = flash_at25xv021a_wait_for_idle(dev, config->timeout_erase); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_global_protection(dev, DEV_GLOBAL_PROTECT); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, DEV_SR_EPE, &status); + if (err != 0) { + return err; + } + + if (status != 0) { + LOG_ERR("failed to erase %s", dev->name); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_erase_internal(const struct device *dev, uint32_t addr) +{ + int err; + uint8_t status; + const struct flash_at25xv021a_config *config = dev->config; + uint8_t cmd[4] = { + DEV_PAGE_ERASE, + FIELD_GET(GENMASK(9, 8), addr), + FIELD_GET(GENMASK(7, 0), addr), + DEV_DUMMY_BYTE, + }; + const struct spi_buf tx_buf = {.buf = &cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + err = flash_at25xv021a_write_enable(dev); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_spi_write(dev, &config->spi, &tx); + if (err != 0) { + return err; + } + + /* Page erase operations can take up to 20 milliseconds. */ + err = flash_at25xv021a_wait_for_idle(dev, config->timeout_erase); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_check_status(dev, DEV_SR_EPE, &status); + if (err != 0) { + return err; + } + + if (status != 0) { + LOG_ERR("unable to erase from %s", dev->name); + return -EIO; + } + + return err; +} + +static int flash_at25xv021a_process_erase(const struct device *dev, off_t *offset) +{ + int err; + const struct flash_at25xv021a_config *config = dev->config; + uint32_t page_addr = *offset / config->page_size; + + err = flash_at25xv021a_software_protection(dev, *offset, DEV_UNPROTECT); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_erase_internal(dev, page_addr); + if (err != 0) { + return err; + } + + err = flash_at25xv021a_software_protection(dev, *offset, DEV_PROTECT); + if (err != 0) { + return err; + } + + *offset += config->page_size; + + return err; +} + +static int flash_at25xv021a_write(const struct device *dev, off_t offset, const void *buf, + size_t len) +{ + int err; + struct flash_at25xv021a_data *data = dev->data; + const struct flash_at25xv021a_config *config = dev->config; + + if (config->read_only) { + LOG_ERR("attempted to write to read-only device %s", dev->name); + return -EINVAL; + } + + if (len == 0) { + LOG_DBG("attempted to write 0 bytes to %s", dev->name); + return 0; + } + + if (len > config->page_size) { + LOG_ERR("attempted to write more than page size in one write operation"); + return -EINVAL; + } + + k_mutex_lock(&data->lock, K_FOREVER); + + err = flash_at25xv021a_process_write(dev, offset, buf, len); + if (err != 0) { + LOG_ERR("unable to complete write operation for %s", dev->name); + } + + k_mutex_unlock(&data->lock); + + return err; +} + +static int flash_at25xv021a_erase(const struct device *dev, off_t offset, size_t size) +{ + int err = 0; + struct flash_at25xv021a_data *data = dev->data; + const struct flash_at25xv021a_config *config = dev->config; + + if (config->read_only) { + LOG_ERR("attempted to erase from read-only device %s", dev->name); + return -EINVAL; + } + + if (size == 0) { + LOG_DBG("attempted to erase 0 bytes from %s", dev->name); + return 0; + } + + if (offset % config->page_size != 0 || size % config->page_size != 0) { + LOG_ERR("offset and/or size is not aligned to page size in %s erase", dev->name); + return -EINVAL; + } + + if (offset + size > config->size) { + LOG_ERR("attempted to erase beyond %s size boundary: %u", dev->name, config->size); + return -EINVAL; + } + + k_mutex_lock(&data->lock, K_FOREVER); + + if (offset == 0 && size == config->size) { + err = flash_at25xv021a_chip_erase(dev); + k_mutex_unlock(&data->lock); + return err; + } + + while (size != 0) { + + err = flash_at25xv021a_process_erase(dev, &offset); + if (err != 0) { + LOG_ERR("unable to complete erase operation for %s", dev->name); + break; + } + + size -= config->page_size; + } + + k_mutex_unlock(&data->lock); + + return err; +} +#else +static int flash_at25xv021a_write(const struct device *dev, off_t offset, const void *buf, + size_t len) +{ + LOG_ERR("attempted to write to read-only device %s", dev->name); + + return -EINVAL; +} + +static int flash_at25xv021a_erase(const struct device *dev, off_t offset, size_t size) +{ + LOG_ERR("attempted to erase from read-only device %s", dev->name); + + return -EINVAL; +} +#endif /* ANY_DEV_WRITEABLE */ + +static int flash_at25xv021a_get_size(const struct device *dev, uint64_t *size) +{ + const struct flash_at25xv021a_config *config = dev->config; + + *size = (uint64_t)config->size; + + return 0; +} + +static const struct flash_parameters *flash_at25xv021a_get_parameters(const struct device *dev) +{ + const struct flash_at25xv021a_config *config = dev->config; + + return &config->parameters; +} + +#if defined(CONFIG_FLASH_PAGE_LAYOUT) +static void flash_at25xv021a_pages_layout(const struct device *dev, + const struct flash_pages_layout **layout, + size_t *layout_size) +{ + const struct flash_at25xv021a_config *config = dev->config; + + *layout = &config->pages_layout; + *layout_size = 1; +} +#endif /* defined(CONFIG_FLASH_PAGE_LAYOUT) */ + +#ifdef CONFIG_PM_DEVICE +static int flash_at25xv021a_resume(const struct device *dev) +{ + int err; + uint8_t cmd[1] = {DEV_RESUME}; + const struct flash_at25xv021a_config *config = dev->config; + const struct spi_buf tx_bufs = {.buf = cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_bufs, .count = 1}; + + /* If in ultra deep sleep mode, we can send any command. Don't check return status. */ + (void)spi_write_dt(&config->spi, &tx); + + /* Device takes a minimum of 70 microseconds to exit ultra deep sleep mode. */ + k_msleep(1); + + err = flash_at25xv021a_verify_device(dev); + if (err != 0) { + LOG_ERR("failed to resume %s", dev->name); + } + + return err; +} + +static int flash_at25xv021a_suspend(const struct device *dev) +{ + int err; + const struct flash_at25xv021a_config *config = dev->config; + uint8_t cmd[1] = {config->ultra_deep_sleep ? DEV_ULTRA_DEEP_SLEEP : DEV_DEEP_SLEEP}; + const struct spi_buf tx_bufs = {.buf = cmd, .len = ARRAY_SIZE(cmd)}; + const struct spi_buf_set tx = {.buffers = &tx_bufs, .count = 1}; + + /* Longer timeout in case suspend is called during a chip erase operation. */ + err = flash_at25xv021a_wait_for_idle(dev, config->timeout_erase); + if (err != 0) { + return err; + } + + return flash_at25xv021a_spi_write(dev, &config->spi, &tx); +} + +static int flash_at25xv021a_pm_action(const struct device *dev, enum pm_device_action action) +{ + switch (action) { + case PM_DEVICE_ACTION_RESUME: + return flash_at25xv021a_resume(dev); + case PM_DEVICE_ACTION_SUSPEND: + return flash_at25xv021a_suspend(dev); + case PM_DEVICE_ACTION_TURN_OFF: + __fallthrough; + case PM_DEVICE_ACTION_TURN_ON: + __fallthrough; + default: + break; + } + + return -ENOTSUP; +} +#endif /* CONFIG_PM_DEVICE */ + +static int flash_at25xv021a_init(const struct device *dev) +{ + int err; + struct flash_at25xv021a_data *data = dev->data; + const struct flash_at25xv021a_config *config = dev->config; + + err = k_mutex_init(&data->lock); + if (err != 0) { + LOG_ERR("unable to initialize mutex"); + return err; + } + + if (!device_is_ready(config->spi.bus)) { + LOG_ERR("spi bus is not ready"); + return -ENODEV; + } + +#ifdef CONFIG_PM_DEVICE + /* Resume if device was previously suspended. */ + err = flash_at25xv021a_resume(dev); + if (err != 0) { + return err; + } +#endif /* CONFIG_PM_DEVICE */ + + err = flash_at25xv021a_verify_device(dev); + if (err != 0) { + LOG_ERR("unable to verify device information"); + return err; + } + +#if ANY_DEV_WRITEABLE && ANY_DEV_HAS_WP_GPIO + if (!device_is_ready(config->wp_gpio.port)) { + LOG_ERR("device controlling WP GPIO is not ready"); + return -ENODEV; + } + + if (!gpio_is_ready_dt(&config->wp_gpio)) { + LOG_ERR("WP GPIO is not ready"); + return -ENODEV; + } +#endif /* ANY_DEV_WRITEABLE && ANY_DEV_HAS_WP_GPIO */ + +#if ANY_DEV_WRITEABLE + return flash_at25xv021a_hardware_init(dev); +#else + return 0; +#endif /* ANY_DEV_WRITEABLE */ +} + +static DEVICE_API(flash, spi_flash_at25xv021a_api) = { + .read = flash_at25xv021a_read, + .write = flash_at25xv021a_write, + .erase = flash_at25xv021a_erase, + .get_size = flash_at25xv021a_get_size, + .get_parameters = flash_at25xv021a_get_parameters, +#if defined(CONFIG_FLASH_PAGE_LAYOUT) + .page_layout = flash_at25xv021a_pages_layout, +#endif +}; + +#define ASSERT_SIZE(sz) BUILD_ASSERT(sz > 0, "Size must be positive") + +#define ASSERT_PAGE_SIZE(pg) \ + BUILD_ASSERT(IS_POWER_OF_TWO(pg), "Page size must be positive and a power of 2") + +#define ASSERT_TIMEOUTS(timeout, timeout_erase) \ + BUILD_ASSERT((timeout > 0) && (timeout_erase > 0), "Timeouts must be positive") + +#define SPI_OP (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8)) + +#define PAGE_SIZE_IF_WRITEABLE(inst) \ + COND_CODE_0(DT_INST_NODE_PROP_OR(inst, read_only, false), \ + (.page_size = DT_INST_PROP(inst, page_size),), \ + (EMPTY)) + +#define TIMEOUT_ERASE_IF_WRITEABLE(inst) \ + COND_CODE_0(DT_INST_NODE_PROP_OR(inst, read_only, false), \ + (.timeout_erase = K_MSEC(DT_INST_PROP(inst, timeout_erase)),), \ + (EMPTY)) + +#define WP_GPIO_IF_PROVIDED(inst) \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, wp_gpios), \ + (.wp_gpio = GPIO_DT_SPEC_INST_GET(inst, wp_gpios),)) + +#define PAGES_LAYOUT_IF_ENABLED(inst) \ + IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, (.pages_layout = { \ + .pages_count = DT_INST_PROP(inst, size) / DT_INST_PROP(inst, page_size),\ + .pages_size = DT_INST_PROP(inst, page_size), \ + },)) + +#define SPI_FLASH_AT25XV021A_DEFINE(inst) \ + \ + ASSERT_SIZE(DT_INST_PROP(inst, size)); \ + ASSERT_PAGE_SIZE(DT_INST_PROP(inst, page_size)); \ + ASSERT_TIMEOUTS(DT_INST_PROP(inst, timeout), DT_INST_PROP(inst, timeout_erase)); \ + \ + static const struct flash_at25xv021a_config flash_at25xv021a_config_##inst = { \ + .spi = SPI_DT_SPEC_INST_GET(inst, SPI_OP, 0), \ + .jedec_id = DT_INST_PROP(inst, jedec_id), \ + .size = DT_INST_PROP(inst, size), \ + .timeout = K_MSEC(DT_INST_PROP(inst, timeout)), \ + .read_only = DT_INST_PROP(inst, read_only), \ + .ultra_deep_sleep = DT_INST_PROP(inst, ultra_deep_sleep), \ + .parameters = \ + { \ + .write_block_size = DT_INST_PROP(inst, page_size), \ + .erase_value = 0xff, \ + }, \ + WP_GPIO_IF_PROVIDED(inst) PAGES_LAYOUT_IF_ENABLED(inst) \ + PAGE_SIZE_IF_WRITEABLE(inst) TIMEOUT_ERASE_IF_WRITEABLE(inst)}; \ + \ + static struct flash_at25xv021a_data flash_at25xv021a_data_##inst; \ + \ + PM_DEVICE_DT_INST_DEFINE(inst, flash_at25xv021a_pm_action); \ + \ + DEVICE_DT_INST_DEFINE(inst, flash_at25xv021a_init, PM_DEVICE_DT_INST_GET(inst), \ + &flash_at25xv021a_data_##inst, &flash_at25xv021a_config_##inst, \ + POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, &spi_flash_at25xv021a_api); + +DT_INST_FOREACH_STATUS_OKAY(SPI_FLASH_AT25XV021A_DEFINE) diff --git a/drivers/flash/spi_nor.c b/drivers/flash/spi_nor.c index 383a6065394bc..b235c166f374e 100644 --- a/drivers/flash/spi_nor.c +++ b/drivers/flash/spi_nor.c @@ -1376,7 +1376,7 @@ static int spi_nor_process_sfdp(const struct device *dev) if (id == JESD216_SFDP_PARAM_ID_BFP) { union { - uint32_t dw[MIN(php->len_dw, 20)]; + uint32_t dw[20]; struct jesd216_bfp bfp; } u_param; const struct jesd216_bfp *bfp = &u_param.bfp; diff --git a/drivers/fuel_gauge/CMakeLists.txt b/drivers/fuel_gauge/CMakeLists.txt index 643ff5f6e81eb..afd417040cf89 100644 --- a/drivers/fuel_gauge/CMakeLists.txt +++ b/drivers/fuel_gauge/CMakeLists.txt @@ -11,6 +11,7 @@ add_subdirectory_ifdef(CONFIG_BQ27Z746 bq27z746) add_subdirectory_ifdef(CONFIG_FUEL_GAUGE_AXP2101 axp2101) add_subdirectory_ifdef(CONFIG_LC709203F lc709203f) add_subdirectory_ifdef(CONFIG_SY24561 sy24561) +add_subdirectory_ifdef(CONFIG_BQ40Z50 bq40z50) zephyr_library_sources_ifdef(CONFIG_USERSPACE fuel_gauge_syscall_handlers.c) diff --git a/drivers/fuel_gauge/Kconfig b/drivers/fuel_gauge/Kconfig index ab34a07a5a3e1..c7168036e3eac 100644 --- a/drivers/fuel_gauge/Kconfig +++ b/drivers/fuel_gauge/Kconfig @@ -22,6 +22,7 @@ config FUEL_GAUGE_INIT_PRIORITY source "drivers/fuel_gauge/max17048/Kconfig" source "drivers/fuel_gauge/sbs_gauge/Kconfig" source "drivers/fuel_gauge/bq27z746/Kconfig" +source "drivers/fuel_gauge/bq40z50/Kconfig" source "drivers/fuel_gauge/composite/Kconfig" source "drivers/fuel_gauge/axp2101/Kconfig" source "drivers/fuel_gauge/lc709203f/Kconfig" diff --git a/drivers/fuel_gauge/bq27z746/bq27z746.c b/drivers/fuel_gauge/bq27z746/bq27z746.c index 0cbc3b5fb2372..0605b762d2963 100644 --- a/drivers/fuel_gauge/bq27z746/bq27z746.c +++ b/drivers/fuel_gauge/bq27z746/bq27z746.c @@ -22,6 +22,10 @@ LOG_MODULE_REGISTER(BQ27Z746); #define BQ27Z746_MAC_OVERHEAD_LEN 4 /* 2 cmd bytes, 1 length byte, 1 checksum byte */ #define BQ27Z746_MAC_COMPLETE_LEN (BQ27Z746_MAC_DATA_LEN + BQ27Z746_MAC_OVERHEAD_LEN) +struct bq27z746_config { + struct i2c_dt_spec i2c; +}; + static int bq27z746_read16(const struct device *dev, uint8_t reg, uint16_t *value) { uint8_t i2c_data[2]; @@ -196,9 +200,8 @@ static int bq27z746_get_prop(const struct device *dev, fuel_gauge_prop_t prop, return rc; } -static int bq27z746_get_buffer_prop(const struct device *dev, - fuel_gauge_prop_t property_type, void *dst, - size_t dst_len) +static int bq27z746_get_buffer_prop(const struct device *dev, fuel_gauge_prop_t property_type, + void *dst, size_t dst_len) { int rc = 0; diff --git a/drivers/fuel_gauge/bq27z746/bq27z746.h b/drivers/fuel_gauge/bq27z746/bq27z746.h index 6d9f821b90d80..a28452f83cb26 100644 --- a/drivers/fuel_gauge/bq27z746/bq27z746.h +++ b/drivers/fuel_gauge/bq27z746/bq27z746.h @@ -11,132 +11,133 @@ #include /* Registers */ -#define BQ27Z746_MANUFACTURERACCESS 0x00 /* R/W */ -#define BQ27Z746_ATRATE 0x02 /* R/W, Unit: mA, Range: -32768..32767 */ -#define BQ27Z746_ATRATETIMETOEMPTY 0x04 /* R/O, Unit: minutes, Range: 0..65535 */ -#define BQ27Z746_TEMPERATURE 0x06 /* R/O, Unit: 0.1 K, Range: 0..32767 */ -#define BQ27Z746_VOLTAGE 0x08 /* R/O, Unit: mV, Range: 0..32767 */ -#define BQ27Z746_BATTERYSTATUS 0x0A /* R/O, Unit: status bits */ -#define BQ27Z746_CURRENT 0x0C /* R/O, Unit: mA, Range: -32768..32767 */ -#define BQ27Z746_REMAININGCAPACITY 0x10 /* R/O, Unit: mAh, Range: 0..32767 */ -#define BQ27Z746_FULLCHARGECAPACITY 0x12 /* R/O, Unit: mAh, Range: 0..32767 */ -#define BQ27Z746_AVERAGECURRENT 0x14 /* R/O, Unit: mA, Range: -32768..32767 */ -#define BQ27Z746_AVERAGETIMETOEMPTY 0x16 /* R/O, Unit: minutes, Range: 0..65535 */ -#define BQ27Z746_AVERAGETIMETOFULL 0x18 /* R/O, Unit: minutes, Range: 0..65535 */ -#define BQ27Z746_MAXLOADCURRENT 0x1E /* R/O, Unit: mA, Range: 0..65535 */ -#define BQ27Z746_MAXLOADTIMETOEMPTY 0x20 /* R/O, Unit: minutes, Range: 0..65535 */ -#define BQ27Z746_AVERAGEPOWER 0x22 /* R/O, Unit: mW, Range: -32768..32767 */ -#define BQ27Z746_BTPDISCHARGESET 0x24 /* Datasheet unclear */ -#define BQ27Z746_BTPCHARGESET 0x26 /* Datasheet unclear */ -#define BQ27Z746_INTERNALTEMPERATURE 0x28 /* R/O, Unit: 0.1 K, Range: 0..32767 */ -#define BQ27Z746_CYCLECOUNT 0x2A /* R/O, Unit: none, Range: 0..65535 */ -#define BQ27Z746_RELATIVESTATEOFCHARGE 0x2C /* R/O, Unit: percent, Range: 0..100 */ -#define BQ27Z746_STATEOFHEALTH 0x2E /* R/O, Unit: percent, Range: 0..100 */ -#define BQ27Z746_CHARGINGVOLTAGE 0x30 /* R/O, Unit: mV, Range: 0..32767 */ -#define BQ27Z746_CHARGINGCURRENT 0x32 /* R/O, Unit: mA, Range: 0..32767 */ -#define BQ27Z746_TERMINATEVOLTAGE 0x34 /* R/W, Unit: mC, Range: 0..32767 */ -#define BQ27Z746_TIMESTAMPUPPER 0x36 /* R/O, Unit: seconds, Range: 0..65535 */ -#define BQ27Z746_TIMESTAMPLOWER 0x38 /* R/O, Unit: seconds, Range: 0..65535 */ -#define BQ27Z746_QMAXCYCLES 0x3A /* R/O, Unit: none, Range: 0..65535 */ -#define BQ27Z746_DESIGNCAPACITY \ - 0x3C /* R/O (sealed), R/W (unsealed or factory access), Unit: mAh, Range: 0..32767 */ -#define BQ27Z746_ALTMANUFACTURERACCESS 0x3E /* R/W */ -#define BQ27Z746_MACDATA 0x40 /* R/O, MAC data */ -#define BQ27Z746_MACDATASUM 0x60 /* R/O, Checksum over MAC command and data */ -#define BQ27Z746_MACDATALEN 0x61 /* R/O, Length of the MAC data */ -#define BQ27Z746_VOLTHISETTHRESHOLD 0x62 /* R/W, Unit: mV, Range: 0..5000 */ -#define BQ27Z746_VOLTHICLEARTHRESHOLD 0x64 /* R/W, Unit: mV, Range: 0..5000 */ -#define BQ27Z746_VOLTLOSETTHRESHOLD 0x66 /* R/W, Unit: mV, Range: 0..5000 */ -#define BQ27Z746_VOLTLOCLEARTHRESHOLD 0x68 /* R/W, Unit: mV, Range: 0..5000 */ -#define BQ27Z746_TEMPHISETTHRESHOLD 0x6A /* R/W, Unit: degree celsius, Range: -128..127 */ -#define BQ27Z746_TEMPHICLEARTHRESHOLD 0x6B /* R/W, Unit: degree celsius, Range: -128..127 */ -#define BQ27Z746_TEMPLOSETTHRESHOLD 0x6C /* R/W, Unit: degree celsius, Range: -128..127 */ -#define BQ27Z746_TEMPLOCLEARTHRESHOLD 0x6D /* R/W, Unit: degree celsius, Range: -128..127 */ -#define BQ27Z746_INTERRUPTSTATUS 0x6E /* R/O, Unit: status bits */ -#define BQ27Z746_SOCDELTASETTHRESHOLD 0x6F /* R/W, Unit: percent, Range: 0..100 */ +enum bq27z746_regs { + BQ27Z746_MANUFACTURERACCESS = 0x00, /* R/W */ + BQ27Z746_ATRATE = 0x02, /* R/W, Unit: mA, Range: -32768..32767 */ + BQ27Z746_ATRATETIMETOEMPTY = 0x04, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ27Z746_TEMPERATURE = 0x06, /* R/O, Unit: 0.1 K, Range: 0..32767 */ + BQ27Z746_VOLTAGE = 0x08, /* R/O, Unit: mV, Range: 0..32767 */ + BQ27Z746_BATTERYSTATUS = 0x0A, /* R/O, Unit: status bits */ + BQ27Z746_CURRENT = 0x0C, /* R/O, Unit: mA, Range: -32768..32767 */ + BQ27Z746_REMAININGCAPACITY = 0x10, /* R/O, Unit: mAh, Range: 0..32767 */ + BQ27Z746_FULLCHARGECAPACITY = 0x12, /* R/O, Unit: mAh, Range: 0..32767 */ + BQ27Z746_AVERAGECURRENT = 0x14, /* R/O, Unit: mA, Range: -32768..32767 */ + BQ27Z746_AVERAGETIMETOEMPTY = 0x16, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ27Z746_AVERAGETIMETOFULL = 0x18, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ27Z746_MAXLOADCURRENT = 0x1E, /* R/O, Unit: mA, Range: 0..65535 */ + BQ27Z746_MAXLOADTIMETOEMPTY = 0x20, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ27Z746_AVERAGEPOWER = 0x22, /* R/O, Unit: mW, Range: -32768..32767 */ + BQ27Z746_BTPDISCHARGESET = 0x24, /* Datasheet unclear */ + BQ27Z746_BTPCHARGESET = 0x26, /* Datasheet unclear */ + BQ27Z746_INTERNALTEMPERATURE = 0x28, /* R/O, Unit: 0.1 K, Range: 0..32767 */ + BQ27Z746_CYCLECOUNT = 0x2A, /* R/O, Unit: none, Range: 0..65535 */ + BQ27Z746_RELATIVESTATEOFCHARGE = 0x2C, /* R/O, Unit: percent, Range: 0..100 */ + BQ27Z746_STATEOFHEALTH = 0x2E, /* R/O, Unit: percent, Range: 0..100 */ + BQ27Z746_CHARGINGVOLTAGE = 0x30, /* R/O, Unit: mV, Range: 0..32767 */ + BQ27Z746_CHARGINGCURRENT = 0x32, /* R/O, Unit: mA, Range: 0..32767 */ + BQ27Z746_TERMINATEVOLTAGE = 0x34, /* R/W, Unit: mC, Range: 0..32767 */ + BQ27Z746_TIMESTAMPUPPER = 0x36, /* R/O, Unit: seconds, Range: 0..65535 */ + BQ27Z746_TIMESTAMPLOWER = 0x38, /* R/O, Unit: seconds, Range: 0..65535 */ + BQ27Z746_QMAXCYCLES = 0x3A, /* R/O, Unit: none, Range: 0..65535 */ + BQ27Z746_DESIGNCAPACITY = 0x3C, /* R/O (sealed), R/W (unsealed or factory access), + * Unit: mAh, Range: 0..32767 + */ + BQ27Z746_ALTMANUFACTURERACCESS = 0x3E, /* R/W */ + BQ27Z746_MACDATA = 0x40, /* R/O, MAC data */ + BQ27Z746_MACDATASUM = 0x60, /* R/O, Checksum over MAC command and data */ + BQ27Z746_MACDATALEN = 0x61, /* R/O, Length of the MAC data */ + BQ27Z746_VOLTHISETTHRESHOLD = 0x62, /* R/W, Unit: mV, Range: 0..5000 */ + BQ27Z746_VOLTHICLEARTHRESHOLD = 0x64, /* R/W, Unit: mV, Range: 0..5000 */ + BQ27Z746_VOLTLOSETTHRESHOLD = 0x66, /* R/W, Unit: mV, Range: 0..5000 */ + BQ27Z746_VOLTLOCLEARTHRESHOLD = 0x68, /* R/W, Unit: mV, Range: 0..5000 */ + BQ27Z746_TEMPHISETTHRESHOLD = 0x6A, /* R/W, Unit: degree celsius, Range: -128..127 */ + BQ27Z746_TEMPHICLEARTHRESHOLD = 0x6B, /* R/W, Unit: degree celsius, Range: -128..127 */ + BQ27Z746_TEMPLOSETTHRESHOLD = 0x6C, /* R/W, Unit: degree celsius, Range: -128..127 */ + BQ27Z746_TEMPLOCLEARTHRESHOLD = 0x6D, /* R/W, Unit: degree celsius, Range: -128..127 */ + BQ27Z746_INTERRUPTSTATUS = 0x6E, /* R/O, Unit: status bits */ + BQ27Z746_SOCDELTASETTHRESHOLD = 0x6F, /* R/W, Unit: percent, Range: 0..100 */ +}; /* MAC commands */ -#define BQ27Z746_MAC_CMD_DEVICETYPE 0x0001 -#define BQ27Z746_MAC_CMD_FIRMWAREVERSION 0x0002 -#define BQ27Z746_MAC_CMD_HARDWAREVERSION 0x0003 -#define BQ27Z746_MAC_CMD_IFCHECKSUM 0x0004 -#define BQ27Z746_MAC_CMD_STATICDFSIGNATURE 0x0005 -#define BQ27Z746_MAC_CMD_CHEMID 0x0006 -#define BQ27Z746_MAC_CMD_PREV_MACWRITE 0x0007 -#define BQ27Z746_MAC_CMD_STATICCHEMDFSIGNATURE 0x0008 -#define BQ27Z746_MAC_CMD_ALLDFSIGNATURE 0x0009 -#define BQ27Z746_MAC_CMD_SHELFENABLE 0x000B -#define BQ27Z746_MAC_CMD_SHELFDISABLE 0x000C -#define BQ27Z746_MAC_CMD_SHUTDOWNMODE 0x0010 -#define BQ27Z746_MAC_CMD_RESET1 0x0012 -#define BQ27Z746_MAC_CMD_SHIPMODEENABLE 0x0015 -#define BQ27Z746_MAC_CMD_SHIPMODEDISABLE 0x0016 -#define BQ27Z746_MAC_CMD_QMAX_DAY 0x0017 -#define BQ27Z746_MAC_CMD_CHARGEFETTOGGLE 0x001F -#define BQ27Z746_MAC_CMD_DISCHARGEFETTOGGLE 0x0020 -#define BQ27Z746_MAC_CMD_GAUGING_IT_ENABLE 0x0021 -#define BQ27Z746_MAC_CMD_FET_ENABLE 0x0022 -#define BQ27Z746_MAC_CMD_LIFETIMEDATACOLLECTION 0x0023 -#define BQ27Z746_MAC_CMD_LIFETIMEDATARESET 0x0028 -#define BQ27Z746_MAC_CMD_CALIBRATIONMODE 0x002D -#define BQ27Z746_MAC_CMD_LIFETIMEDATAFLUSH 0x002E -#define BQ27Z746_MAC_CMD_LIFETIMEDATASPEEDUPMODE 0x002F -#define BQ27Z746_MAC_CMD_SEALDEVICE 0x0030 -#define BQ27Z746_MAC_CMD_SECURITYKEYS 0x0035 -#define BQ27Z746_MAC_CMD_RESET2 0x0041 -#define BQ27Z746_MAC_CMD_TAMBIENTSYNC 0x0047 -#define BQ27Z746_MAC_CMD_DEVICE_NAME 0x004A -#define BQ27Z746_MAC_CMD_DEVICE_CHEM 0x004B -#define BQ27Z746_MAC_CMD_MANUFACTURER_NAME 0x004C -#define BQ27Z746_MAC_CMD_MANUFACTURE_DATE 0x004D -#define BQ27Z746_MAC_CMD_SERIAL_NUMBER 0x004E -#define BQ27Z746_MAC_CMD_SAFETYALERT 0x0050 -#define BQ27Z746_MAC_CMD_SAFETYSTATUS 0x0051 -#define BQ27Z746_MAC_CMD_OPERATIONSTATUS 0x0054 -#define BQ27Z746_MAC_CMD_CHARGINGSTATUS 0x0055 -#define BQ27Z746_MAC_CMD_GAUGINGSTATUS 0x0056 -#define BQ27Z746_MAC_CMD_MANUFACTURINGSTATUS 0x0057 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK1 0x0060 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK2 0x0061 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK3 0x0062 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK4 0x0063 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK6 0x0065 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK7 0x0065 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK8 0x0067 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK9 0x0068 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK10 0x0069 -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK11 0x006A -#define BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK12 0x006B -#define BQ27Z746_MAC_CMD_MANUFACTURERINFO 0x0070 -#define BQ27Z746_MAC_CMD_DASTATUS1 0x0071 -#define BQ27Z746_MAC_CMD_DASTATUS2 0x0072 -#define BQ27Z746_MAC_CMD_ITSTATUS1 0x0073 -#define BQ27Z746_MAC_CMD_ITSTATUS2 0x0074 -#define BQ27Z746_MAC_CMD_ITSTATUS3 0x0075 -#define BQ27Z746_MAC_CMD_FCC_SOH 0x0077 -#define BQ27Z746_MAC_CMD_FILTERED_CAPACITY 0x0078 -#define BQ27Z746_MAC_CMD_MANUFACTURERINFOB 0x007A -#define BQ27Z746_MAC_CMD_MANUFACTURERINFOC 0x007B -#define BQ27Z746_MAC_CMD_FET_CONTROL_OVERRIDE 0x0097 -#define BQ27Z746_MAC_CMD_SYSTEM_RESET_ENABLE 0x00A3 -#define BQ27Z746_MAC_CMD_SYSTEM_RESET 0x00A4 -#define BQ27Z746_MAC_CMD_BATTSENSEOUTPUT 0x00B1 -#define BQ27Z746_MAC_CMD_RATABLECELL0 0x00E0 -#define BQ27Z746_MAC_CMD_ROMMODE 0x0F00 -#define BQ27Z746_MAC_CMD_DATAFLASHACCESS 0x4000 -#define BQ27Z746_MAC_CMD_SWITCHTOHDQ 0x7C40 -#define BQ27Z746_MAC_CMD_EXITCALIBRATIONOUTPUT 0xF080 -#define BQ27Z746_MAC_CMD_OUTPUTCCANDADCFORCALIBRATIO 0xF081 -#define BQ27Z746_MAC_CMD_OUTPUTTEMPERATURECAL 0xF083 -#define BQ27Z746_MAC_CMD_PROTECTORCALIBRATION 0xF0A0 -#define BQ27Z746_MAC_CMD_PROTECTORIMAGE1 0xF0A1 -#define BQ27Z746_MAC_CMD_PROTECTORIMAGE2 0xF0A2 -#define BQ27Z746_MAC_CMD_PROTECTORIMAGESAVE 0xF0A3 -#define BQ27Z746_MAC_CMD_PROTECTORIMAGELOCK 0xF0A4 -#define BQ27Z746_MAC_CMD_PROTECTORFACTORYCONFIG 0xF0A5 - -struct bq27z746_config { - struct i2c_dt_spec i2c; +enum bq27z746_mac_cmds { + BQ27Z746_MAC_CMD_DEVICETYPE = 0x0001, + BQ27Z746_MAC_CMD_FIRMWAREVERSION = 0x0002, + BQ27Z746_MAC_CMD_HARDWAREVERSION = 0x0003, + BQ27Z746_MAC_CMD_IFCHECKSUM = 0x0004, + BQ27Z746_MAC_CMD_STATICDFSIGNATURE = 0x0005, + BQ27Z746_MAC_CMD_CHEMID = 0x0006, + BQ27Z746_MAC_CMD_PREV_MACWRITE = 0x0007, + BQ27Z746_MAC_CMD_STATICCHEMDFSIGNATURE = 0x0008, + BQ27Z746_MAC_CMD_ALLDFSIGNATURE = 0x0009, + BQ27Z746_MAC_CMD_SHELFENABLE = 0x000B, + BQ27Z746_MAC_CMD_SHELFDISABLE = 0x000C, + BQ27Z746_MAC_CMD_SHUTDOWNMODE = 0x0010, + BQ27Z746_MAC_CMD_RESET1 = 0x0012, + BQ27Z746_MAC_CMD_SHIPMODEENABLE = 0x0015, + BQ27Z746_MAC_CMD_SHIPMODEDISABLE = 0x0016, + BQ27Z746_MAC_CMD_QMAX_DAY = 0x0017, + BQ27Z746_MAC_CMD_CHARGEFETTOGGLE = 0x001F, + BQ27Z746_MAC_CMD_DISCHARGEFETTOGGLE = 0x0020, + BQ27Z746_MAC_CMD_GAUGING_IT_ENABLE = 0x0021, + BQ27Z746_MAC_CMD_FET_ENABLE = 0x0022, + BQ27Z746_MAC_CMD_LIFETIMEDATACOLLECTION = 0x0023, + BQ27Z746_MAC_CMD_LIFETIMEDATARESET = 0x0028, + BQ27Z746_MAC_CMD_CALIBRATIONMODE = 0x002D, + BQ27Z746_MAC_CMD_LIFETIMEDATAFLUSH = 0x002E, + BQ27Z746_MAC_CMD_LIFETIMEDATASPEEDUPMODE = 0x002F, + BQ27Z746_MAC_CMD_SEALDEVICE = 0x0030, + BQ27Z746_MAC_CMD_SECURITYKEYS = 0x0035, + BQ27Z746_MAC_CMD_RESET2 = 0x0041, + BQ27Z746_MAC_CMD_TAMBIENTSYNC = 0x0047, + BQ27Z746_MAC_CMD_DEVICE_NAME = 0x004A, + BQ27Z746_MAC_CMD_DEVICE_CHEM = 0x004B, + BQ27Z746_MAC_CMD_MANUFACTURER_NAME = 0x004C, + BQ27Z746_MAC_CMD_MANUFACTURE_DATE = 0x004D, + BQ27Z746_MAC_CMD_SERIAL_NUMBER = 0x004E, + BQ27Z746_MAC_CMD_SAFETYALERT = 0x0050, + BQ27Z746_MAC_CMD_SAFETYSTATUS = 0x0051, + BQ27Z746_MAC_CMD_OPERATIONSTATUS = 0x0054, + BQ27Z746_MAC_CMD_CHARGINGSTATUS = 0x0055, + BQ27Z746_MAC_CMD_GAUGINGSTATUS = 0x0056, + BQ27Z746_MAC_CMD_MANUFACTURINGSTATUS = 0x0057, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK1 = 0x0060, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK2 = 0x0061, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK3 = 0x0062, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK4 = 0x0063, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK6 = 0x0065, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK7 = 0x0065, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK8 = 0x0067, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK9 = 0x0068, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK10 = 0x0069, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK11 = 0x006A, + BQ27Z746_MAC_CMD_LIFETIMEDATABLOCK12 = 0x006B, + BQ27Z746_MAC_CMD_MANUFACTURERINFO = 0x0070, + BQ27Z746_MAC_CMD_DASTATUS1 = 0x0071, + BQ27Z746_MAC_CMD_DASTATUS2 = 0x0072, + BQ27Z746_MAC_CMD_ITSTATUS1 = 0x0073, + BQ27Z746_MAC_CMD_ITSTATUS2 = 0x0074, + BQ27Z746_MAC_CMD_ITSTATUS3 = 0x0075, + BQ27Z746_MAC_CMD_FCC_SOH = 0x0077, + BQ27Z746_MAC_CMD_FILTERED_CAPACITY = 0x0078, + BQ27Z746_MAC_CMD_MANUFACTURERINFOB = 0x007A, + BQ27Z746_MAC_CMD_MANUFACTURERINFOC = 0x007B, + BQ27Z746_MAC_CMD_FET_CONTROL_OVERRIDE = 0x0097, + BQ27Z746_MAC_CMD_SYSTEM_RESET_ENABLE = 0x00A3, + BQ27Z746_MAC_CMD_SYSTEM_RESET = 0x00A4, + BQ27Z746_MAC_CMD_BATTSENSEOUTPUT = 0x00B1, + BQ27Z746_MAC_CMD_RATABLECELL0 = 0x00E0, + BQ27Z746_MAC_CMD_ROMMODE = 0x0F00, + BQ27Z746_MAC_CMD_DATAFLASHACCESS = 0x4000, + BQ27Z746_MAC_CMD_SWITCHTOHDQ = 0x7C40, + BQ27Z746_MAC_CMD_EXITCALIBRATIONOUTPUT = 0xF080, + BQ27Z746_MAC_CMD_OUTPUTCCANDADCFORCALIBRATIO = 0xF081, + BQ27Z746_MAC_CMD_OUTPUTTEMPERATURECAL = 0xF083, + BQ27Z746_MAC_CMD_PROTECTORCALIBRATION = 0xF0A0, + BQ27Z746_MAC_CMD_PROTECTORIMAGE1 = 0xF0A1, + BQ27Z746_MAC_CMD_PROTECTORIMAGE2 = 0xF0A2, + BQ27Z746_MAC_CMD_PROTECTORIMAGESAVE = 0xF0A3, + BQ27Z746_MAC_CMD_PROTECTORIMAGELOCK = 0xF0A4, + BQ27Z746_MAC_CMD_PROTECTORFACTORYCONFIG = 0xF0A5, }; #endif diff --git a/drivers/fuel_gauge/bq40z50/CMakeLists.txt b/drivers/fuel_gauge/bq40z50/CMakeLists.txt new file mode 100644 index 0000000000000..19dff956c75c5 --- /dev/null +++ b/drivers/fuel_gauge/bq40z50/CMakeLists.txt @@ -0,0 +1,6 @@ +zephyr_library() + +zephyr_library_sources(bq40z50.c) + +zephyr_include_directories_ifdef(CONFIG_EMUL_BQ40Z50 .) +zephyr_library_sources_ifdef(CONFIG_EMUL_BQ40Z50 ./emul_bq40z50.c) diff --git a/drivers/fuel_gauge/bq40z50/Kconfig b/drivers/fuel_gauge/bq40z50/Kconfig new file mode 100644 index 0000000000000..0ba36c137334c --- /dev/null +++ b/drivers/fuel_gauge/bq40z50/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: Apache-2.0 + +config BQ40Z50 + bool "BQ40Z50 Fuel Gauge" + default y + depends on DT_HAS_TI_BQ40Z50_ENABLED + select I2C + help + Enable I2C-based driver for BQ40Z50 Fuel Gauge. + +config EMUL_BQ40Z50 + bool "Emulate a BQ40Z50 fuel gauge" + default y + depends on EMUL + depends on BQ40Z50 + help + It provides readings which follow a simple sequence, thus allowing + test code to check that things are working as expected. diff --git a/drivers/fuel_gauge/bq40z50/bq40z50.c b/drivers/fuel_gauge/bq40z50/bq40z50.c new file mode 100644 index 0000000000000..410a5ceacd8e4 --- /dev/null +++ b/drivers/fuel_gauge/bq40z50/bq40z50.c @@ -0,0 +1,414 @@ +/** + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ti_bq40z50 + +#include "bq40z50.h" + +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(BQ40Z50); + +/* MAC commands */ +#define BQ40Z50_MAC_CMD_DEVICE_TYPE 0X0001 +#define BQ40Z50_MAC_CMD_FIRMWARE_VER 0X0002 +#define BQ40Z50_MAC_CMD_SHUTDOWNMODE 0X0010 +#define BQ40Z50_MAC_CMD_SLEEPMODE 0X0011 +#define BQ40Z50_MAC_CMD_GAUGING 0X0021 + +/* first byte is the length of the data received from the block access and the next two bytes are + * the cmd. + */ +#define BQ40Z50_MAC_META_DATA_LEN 3 +#define BQ40Z50_FIRMWARE_VERSION_LEN 11 + +#define BQ40Z50_LEN_BYTE 1 +#define BQ40Z50_LEN_HALF_WORD 2 +#define BQ40Z50_LEN_WORD 4 + +/* Bit 14 of Operational status (0x54) is XCHG (charging disabled) */ +#define BQ40Z50_OPERATION_STATUS_XCHG_BIT 14 + +struct bq40z50_config { + struct i2c_dt_spec i2c; +}; + +struct bq40z50_data { + uint8_t major_version; + uint8_t minor_version; +}; + +static int bq40z50_i2c_read(const struct device *dev, uint8_t reg_addr, uint8_t *value, size_t len) +{ + const struct bq40z50_config *cfg = dev->config; + int ret = i2c_burst_read_dt(&cfg->i2c, reg_addr, value, len); + + if (ret) { + LOG_ERR("i2c_burst_read_dt failed for address %d: %d", reg_addr, ret); + } + return ret; +} + +static int bq40z50_i2c_write(const struct device *dev, uint8_t reg_addr, uint8_t *value, size_t len) +{ + const struct bq40z50_config *cfg = dev->config; + int ret = i2c_burst_write_dt(&cfg->i2c, reg_addr, value, len); + + if (ret) { + LOG_ERR("i2c_burst_write_dt failed for address %d: %d", reg_addr, ret); + } + return ret; +} + +static int bq40z50_i2c_write_mfr_blk_access(const struct device *dev, uint16_t cmd, uint8_t *value, + size_t len) +{ + const struct bq40z50_config *cfg = dev->config; + /* Manufacturer Block Access (0x44) is standard for bq40zxy family.*/ + uint8_t mac_cmd = BQ40Z50_MANUFACTURERBLOCKACCESS; + struct i2c_msg msg[4]; + uint8_t total_len = sizeof(cmd) + len; + + /* As per Datasheet, use SMBus block protocol to write/read using + * Manufacturer Block Access (0x44). + * SMBus block write requires writing command followed by number of + * bytes that will follow and then actual bytes to write. + */ + msg[0].buf = &mac_cmd; + msg[0].len = 1U; + msg[0].flags = I2C_MSG_WRITE; + + msg[1].buf = &total_len; + msg[1].len = 1U; + msg[1].flags = I2C_MSG_WRITE; + + msg[2].buf = (uint8_t *)&cmd; + msg[2].len = sizeof(cmd); + msg[2].flags = I2C_MSG_WRITE; + + msg[3].buf = value; + msg[3].len = len; + msg[3].flags = I2C_MSG_WRITE | I2C_MSG_STOP; + + /* For battery cutoff, we only need to send the command. */ + int ret = i2c_transfer_dt(&cfg->i2c, msg, ((value == NULL) ? 3 : 4)); + + if (ret) { + LOG_ERR("i2c_burst_write_dt returned %d", ret); + } + return ret; +} + +static int bq40z50_battery_cutoff(const struct device *dev) +{ + int ret = 0; + + /* + * As per TRM (RevB.) (section 14.1.10), in order to enter shutdown mode + * we need to send BQ40Z50_MAC_CMD_SHUTDOWNMODE command twice irrespective of access mode. + * The first command will arm the shutdown sequence and second command will confirm it. + */ + + ret = bq40z50_i2c_write_mfr_blk_access(dev, (uint16_t)BQ40Z50_MAC_CMD_SHUTDOWNMODE, NULL, + 0); + + ret |= bq40z50_i2c_write_mfr_blk_access(dev, (uint16_t)BQ40Z50_MAC_CMD_SHUTDOWNMODE, NULL, + 0); + return ret; +} + +static int bq40z50_get_buffer_prop(const struct device *dev, fuel_gauge_prop_t prop_type, void *dst, + size_t dst_len) +{ + int ret = 0; + + if (dst == NULL) { + return -EINVAL; + } + + switch (prop_type) { + case FUEL_GAUGE_MANUFACTURER_NAME: + if (dst_len == sizeof(struct sbs_gauge_manufacturer_name)) { + ret = bq40z50_i2c_read(dev, BQ40Z50_MANUFACTURERNAME, dst, dst_len); + struct sbs_gauge_manufacturer_name *mfgname = + (struct sbs_gauge_manufacturer_name *)dst; + + mfgname->manufacturer_name[mfgname->manufacturer_name_length] = '\0'; + } else { + ret = -EINVAL; + } + break; + + case FUEL_GAUGE_DEVICE_NAME: + if (dst_len == sizeof(struct sbs_gauge_device_name)) { + ret = bq40z50_i2c_read(dev, BQ40Z50_DEVICENAME, dst, dst_len); + struct sbs_gauge_device_name *devname = (struct sbs_gauge_device_name *)dst; + + devname->device_name[devname->device_name_length] = '\0'; + } else { + ret = -EINVAL; + } + break; + + case FUEL_GAUGE_DEVICE_CHEMISTRY: + if (dst_len == sizeof(struct sbs_gauge_device_chemistry)) { + ret = bq40z50_i2c_read(dev, BQ40Z50_DEVICECHEMISTRY, dst, dst_len); + struct sbs_gauge_device_chemistry *devchem = + (struct sbs_gauge_device_chemistry *)dst; + + devchem->device_chemistry[devchem->device_chemistry_length] = '\0'; + } else { + ret = -EINVAL; + } + break; + + default: + ret = -ENOTSUP; + break; + } + return ret; +} + +static int bq40z50_set_prop(const struct device *dev, fuel_gauge_prop_t prop, + union fuel_gauge_prop_val val) +{ + int ret = 0; + + switch (prop) { + case FUEL_GAUGE_SBS_REMAINING_CAPACITY_ALARM: + ret = bq40z50_i2c_write(dev, BQ40Z50_REMAININGCAPACITYALARM, + (uint8_t *)&val.sbs_remaining_capacity_alarm, + sizeof(val.sbs_remaining_capacity_alarm)); + break; + + case FUEL_GAUGE_SBS_REMAINING_TIME_ALARM: + ret = bq40z50_i2c_write(dev, BQ40Z50_REMAININGTIMEALARM, + (uint8_t *)&val.sbs_remaining_time_alarm, + sizeof(val.sbs_remaining_time_alarm)); + break; + + case FUEL_GAUGE_SBS_MODE: + ret = bq40z50_i2c_write(dev, BQ40Z50_BATTERYMODE, (uint8_t *)&val.sbs_mode, + sizeof(val.sbs_mode)); + break; + + case FUEL_GAUGE_SBS_ATRATE: + ret = bq40z50_i2c_write(dev, BQ40Z50_ATRATE, (uint8_t *)&val.sbs_at_rate, + sizeof(val.sbs_at_rate)); + break; + + case FUEL_GAUGE_SBS_MFR_ACCESS: + ret = bq40z50_i2c_write(dev, BQ40Z50_MANUFACTURERACCESS, + (uint8_t *)&val.sbs_mfr_access_word, + sizeof(val.sbs_mfr_access_word)); + break; + default: + ret = -ENOTSUP; + break; + } + + return ret; +} + +static int bq40z50_get_prop(const struct device *dev, fuel_gauge_prop_t prop, + union fuel_gauge_prop_val *val) +{ + int ret = 0; + uint16_t tmp_val = 0; + + switch (prop) { + case FUEL_GAUGE_AVG_CURRENT: + ret = bq40z50_i2c_read(dev, BQ40Z50_AVERAGECURRENT, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* convert mA to uA */ + val->avg_current = (int16_t)tmp_val * 1000; + break; + + case FUEL_GAUGE_CURRENT: + ret = bq40z50_i2c_read(dev, BQ40Z50_CURRENT, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* convert mA to uA */ + val->current = (int16_t)tmp_val * 1000; + break; + + case FUEL_GAUGE_CHARGE_CUTOFF: + ret = bq40z50_i2c_read(dev, BQ40Z50_MANUFACTURERACCESS, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->cutoff = IS_BIT_SET(tmp_val, BQ40Z50_OPERATION_STATUS_XCHG_BIT); + break; + + case FUEL_GAUGE_CYCLE_COUNT: + ret = bq40z50_i2c_read(dev, BQ40Z50_CYCLECOUNT, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->cycle_count = tmp_val; + break; + + case FUEL_GAUGE_FULL_CHARGE_CAPACITY: + ret = bq40z50_i2c_read(dev, BQ40Z50_FULLCHARGECAPACITY, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* convert mAh to uAh */ + val->full_charge_capacity = tmp_val * 1000; + break; + + case FUEL_GAUGE_REMAINING_CAPACITY: + ret = bq40z50_i2c_read(dev, BQ40Z50_REMAININGCAPACITY, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* convert mAh to uAh */ + val->remaining_capacity = tmp_val * 1000; + break; + + case FUEL_GAUGE_RUNTIME_TO_EMPTY: + ret = bq40z50_i2c_read(dev, BQ40Z50_RUNTIMETOEMPTY, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->runtime_to_empty = tmp_val; + break; + + case FUEL_GAUGE_SBS_MFR_ACCESS: + ret = bq40z50_i2c_read(dev, BQ40Z50_MANUFACTURERACCESS, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_mfr_access_word = tmp_val; + break; + + case FUEL_GAUGE_ABSOLUTE_STATE_OF_CHARGE: + ret = bq40z50_i2c_read(dev, BQ40Z50_ABSOLUTESTATEOFCHARGE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_BYTE); + val->absolute_state_of_charge = tmp_val; + break; + + case FUEL_GAUGE_RELATIVE_STATE_OF_CHARGE: + ret = bq40z50_i2c_read(dev, BQ40Z50_RELATIVESTATEOFCHARGE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_BYTE); + val->relative_state_of_charge = tmp_val; + break; + + case FUEL_GAUGE_TEMPERATURE: + ret = bq40z50_i2c_read(dev, BQ40Z50_TEMPERATURE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->temperature = tmp_val; + break; + + case FUEL_GAUGE_VOLTAGE: + ret = bq40z50_i2c_read(dev, BQ40Z50_VOLTAGE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* change mV to uV */ + val->voltage = tmp_val * 1000; + break; + + case FUEL_GAUGE_SBS_MODE: + ret = bq40z50_i2c_read(dev, BQ40Z50_BATTERYMODE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_mode = tmp_val; + break; + + case FUEL_GAUGE_CHARGE_CURRENT: + ret = bq40z50_i2c_read(dev, BQ40Z50_CHARGINGCURRENT, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* change mA to uA */ + val->chg_current = (int16_t)tmp_val * 1000; + break; + + case FUEL_GAUGE_CHARGE_VOLTAGE: + ret = bq40z50_i2c_read(dev, BQ40Z50_CHARGINGVOLTAGE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* change mV to uV */ + val->chg_voltage = tmp_val * 1000; + break; + + case FUEL_GAUGE_STATUS: + ret = bq40z50_i2c_read(dev, BQ40Z50_BATTERYSTATUS, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->fg_status = tmp_val; + break; + + case FUEL_GAUGE_DESIGN_CAPACITY: + ret = bq40z50_i2c_read(dev, BQ40Z50_DESIGNCAPACITY, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + /* return in mAh unit */ + val->design_cap = tmp_val; + break; + + case FUEL_GAUGE_DESIGN_VOLTAGE: + ret = bq40z50_i2c_read(dev, BQ40Z50_DESIGNVOLTAGE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->design_volt = tmp_val; + break; + + case FUEL_GAUGE_SBS_ATRATE: + ret = bq40z50_i2c_read(dev, BQ40Z50_ATRATE, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_at_rate = (int16_t)tmp_val; + break; + + case FUEL_GAUGE_SBS_ATRATE_TIME_TO_FULL: + ret = bq40z50_i2c_read(dev, BQ40Z50_ATRATETIMETOFULL, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_at_rate_time_to_full = tmp_val; + break; + + case FUEL_GAUGE_SBS_ATRATE_TIME_TO_EMPTY: + ret = bq40z50_i2c_read(dev, BQ40Z50_ATRATETIMETOEMPTY, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_at_rate_time_to_empty = tmp_val; + break; + + case FUEL_GAUGE_SBS_ATRATE_OK: + ret = bq40z50_i2c_read(dev, BQ40Z50_ATRATEOK, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_at_rate_ok = tmp_val; + break; + + case FUEL_GAUGE_SBS_REMAINING_CAPACITY_ALARM: + ret = bq40z50_i2c_read(dev, BQ40Z50_REMAININGCAPACITYALARM, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_remaining_capacity_alarm = tmp_val; + break; + + case FUEL_GAUGE_SBS_REMAINING_TIME_ALARM: + ret = bq40z50_i2c_read(dev, BQ40Z50_REMAININGTIMEALARM, (uint8_t *)&tmp_val, + BQ40Z50_LEN_HALF_WORD); + val->sbs_remaining_time_alarm = tmp_val; + break; + + default: + ret = -ENOTSUP; + break; + } + + return ret; +} + +static int bq40z50_init(const struct device *dev) +{ + const struct bq40z50_config *cfg = (const struct bq40z50_config *)dev->config; + + if (!device_is_ready(cfg->i2c.bus)) { + LOG_ERR("Bus device is not ready"); + return -ENODEV; + } + + return 0; +} + +static DEVICE_API(fuel_gauge, + bq40z50_driver_api) = {.get_property = &bq40z50_get_prop, + .get_buffer_property = &bq40z50_get_buffer_prop, + .set_property = &bq40z50_set_prop, + .battery_cutoff = &bq40z50_battery_cutoff}; + +#define BQ40Z50_INIT(inst) \ + struct bq40z50_config bq40z50_config_##inst = {.i2c = I2C_DT_SPEC_INST_GET(inst)}; \ + struct bq40z50_data bq40z50_data_##inst = {.major_version = 0x00, .minor_version = 0x00}; \ + \ + DEVICE_DT_INST_DEFINE(inst, &bq40z50_init, NULL, &bq40z50_data_##inst, \ + &bq40z50_config_##inst, POST_KERNEL, \ + CONFIG_FUEL_GAUGE_INIT_PRIORITY, &bq40z50_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(BQ40Z50_INIT) diff --git a/drivers/fuel_gauge/bq40z50/bq40z50.h b/drivers/fuel_gauge/bq40z50/bq40z50.h new file mode 100644 index 0000000000000..88b0dc5f68427 --- /dev/null +++ b/drivers/fuel_gauge/bq40z50/bq40z50.h @@ -0,0 +1,58 @@ +/** + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_FUELGAUGE_BQ40Z50_GAUGE_H_ +#define ZEPHYR_DRIVERS_FUELGAUGE_BQ40Z50_GAUGE_H_ + +#include + +enum bq40z50_regs { + BQ40Z50_MANUFACTURERACCESS = 0x00, /* R/W */ + BQ40Z50_REMAININGCAPACITYALARM = 0x01, /* R/W, Unit: mAh/cWh, Range: 0..700 */ + BQ40Z50_REMAININGTIMEALARM = 0x02, /* R/W, Unit: minutes, Range: 0..30 */ + BQ40Z50_BATTERYMODE = 0x03, /* R/W, Unit: ---, Range: 0x0000..0xFFFF */ + BQ40Z50_ATRATE = 0x04, /* R/W, Unit: mA, Range: -32768..32767 */ + BQ40Z50_ATRATETIMETOFULL = 0x05, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ40Z50_ATRATETIMETOEMPTY = 0x06, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ40Z50_ATRATEOK = 0x07, /* R/O, Unit: ---, Range: 0..65535 */ + BQ40Z50_TEMPERATURE = 0x08, /* R/O, Unit: 0.1 K, Range: 0..65535 */ + BQ40Z50_VOLTAGE = 0x09, /* R/O, Unit: mV, Range: 0..65535 */ + BQ40Z50_CURRENT = 0x0A, /* R/O, Unit: mA, Range: -32768..32767 */ + BQ40Z50_AVERAGECURRENT = 0x0B, /* R/O, Unit: mA, Range: -32768..32767 */ + BQ40Z50_RELATIVESTATEOFCHARGE = 0x0D, /* R/O, Unit: percent, Range: 0..100 */ + BQ40Z50_ABSOLUTESTATEOFCHARGE = 0x0E, /* R/O, Unit: percent, Range: 0..100 */ + BQ40Z50_REMAININGCAPACITY = 0x0F, /* R/O, Unit: mAh, Range: 0..65535 */ + BQ40Z50_FULLCHARGECAPACITY = 0x10, /* R/O, Unit: mAh, Range: 0..65535 */ + BQ40Z50_RUNTIMETOEMPTY = 0x11, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ40Z50_AVERAGETIMETOEMPTY = 0x12, /* R/O, Unit: minutes, Range: 0..65535 */ + BQ40Z50_CHARGINGCURRENT = 0x14, /* R/O, Unit: mA, Range: 0..65535 */ + BQ40Z50_CHARGINGVOLTAGE = 0x15, /* R/O, Unit: mV, Range: 0..65535 */ + BQ40Z50_BATTERYSTATUS = 0x16, /* R/O, Unit: ---, Range: --- */ + BQ40Z50_CYCLECOUNT = 0x17, /* R/O, Unit: cycles, Range: 0..65535 */ + BQ40Z50_DESIGNCAPACITY = 0x18, /* R/O, Unit: mAh, Range: 0..65535 */ + BQ40Z50_DESIGNVOLTAGE = 0x19, /* R/O, Unit: mV, Range: 7000..18000 */ + BQ40Z50_MANUFACTURERDATE = 0x1B, /* R/O, Unit: ---, Range: 0..65535 */ + BQ40Z50_SERIALNUMBER = 0x1C, /* R/O, Unit: ---, Range: 0..65535 */ + BQ40Z50_MANUFACTURERNAME = 0x20, /* R/O, Unit: ASCII, Range: --- */ + BQ40Z50_DEVICENAME = 0x21, /* R/O, Unit: ASCII, Range: --- */ + BQ40Z50_DEVICECHEMISTRY = 0x22, /* R/O, Unit: ASCII, Range: --- */ + BQ40Z50_MANUFACTURERDATA = 0x23, /* R/O, Unit: ---, Range: --- */ + BQ40Z50_AUTHENTICATE = 0x2F, /* R/W, Unit: ---, Range: --- */ + BQ40Z50_MANUFACTURERBLOCKACCESS = 0x44, /* R/W */ + BQ40Z50_BTPDISCHARGE = 0x4A, /* R/W, Unit: mAh, Range: 150..65535 */ + BQ40Z50_BTPCHARGE = 0x4B, /* R/W, Unit: mAh, Range: 175..65535 */ + BQ40Z50_PFSTATUS = 0x53, /* Cannot read in Sealed Mode */ + BQ40Z50_OPERATIONSTATUS = 0x54, /* Cannot read in Sealed Mode */ + BQ40Z50_CHARGINGSTATUS = 0x55, /* Cannot read in Sealed Mode */ + BQ40Z50_GAUGINGSSTATUS = + 0x56, /* Cannot read in Sealed Mode (same address as CHARGINGSTATUS) */ + BQ40Z50_MAXTURBOPWR = 0x59, /* R/W, Unit: cW, Range: --- */ + BQ40Z50_SUSTURBOPWR = 0x5A, /* R/W, Unit: cW, Range: --- */ + BQ40Z50_MAXTURBOCURR = 0x5E, /* R/W, Unit: mA, Range: --- */ + BQ40Z50_SUSTURBOCURR = 0x5F /* R/W, Unit: mA, Range: --- */ +}; + +#endif diff --git a/drivers/fuel_gauge/bq40z50/emul_bq40z50.c b/drivers/fuel_gauge/bq40z50/emul_bq40z50.c new file mode 100644 index 0000000000000..0d861359060f8 --- /dev/null +++ b/drivers/fuel_gauge/bq40z50/emul_bq40z50.c @@ -0,0 +1,275 @@ +/** + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Emulator for bq40z50 fuel gauge + */ +#include +#define DT_DRV_COMPAT ti_bq40z50 + +#include +LOG_MODULE_REGISTER(EMUL_BQ40Z50); + +#include +#include +#include +#include +#include + +#include "bq40z50.h" + +/** Static configuration for the emulator */ +struct bq40z50_emul_cfg { + uint16_t i2c_addr; +}; + +static int emul_bq40z70_buffer_read(int reg, uint8_t *buf, size_t len) +{ + static const char manufacturer_name[] = "Texas Inst."; + static const char device_name[] = "bq40z50"; + static const char device_chemistry[] = "LION"; + + switch (reg) { + case BQ40Z50_MANUFACTURERNAME: + if (len < sizeof(manufacturer_name)) { + return -EIO; + } + buf[0] = strlen(manufacturer_name); + memcpy(&buf[1], manufacturer_name, strlen(manufacturer_name)); + break; + + case BQ40Z50_DEVICENAME: + if (len < sizeof(device_name)) { + return -EIO; + } + buf[0] = strlen(device_name); + memcpy(&buf[1], device_name, strlen(device_name)); + break; + + case BQ40Z50_DEVICECHEMISTRY: + if (len < sizeof(device_chemistry)) { + return -EIO; + } + buf[0] = strlen(device_chemistry); + memcpy(&buf[1], device_chemistry, strlen(device_chemistry)); + break; + + default: + LOG_ERR("Buffer Read for reg 0x%x is not supported", reg); + return -EIO; + } + + return 0; +} + +static int emul_bq40z50_write(const struct emul *target, uint8_t *buf, size_t len) +{ + LOG_ERR("Write operation is not currently supported"); + return -EIO; +} + +static int emul_bq40z50_reg_read(const struct emul *target, int reg, uint16_t *val) +{ + switch (reg) { + case BQ40Z50_MANUFACTURERACCESS: + *val = 1; + break; + case BQ40Z50_ATRATE: + *val = 0; + break; + case BQ40Z50_ATRATETIMETOEMPTY: + *val = 0xFFFF; + break; + case BQ40Z50_TEMPERATURE: + *val = 2980; + break; + case BQ40Z50_VOLTAGE: + *val = 1; + break; + case BQ40Z50_BATTERYSTATUS: + *val = 1; + break; + case BQ40Z50_CURRENT: + *val = 1; + break; + case BQ40Z50_REMAININGCAPACITY: + *val = 1; + break; + case BQ40Z50_FULLCHARGECAPACITY: + *val = 1; + break; + case BQ40Z50_AVERAGECURRENT: + *val = 1; + break; + case BQ40Z50_AVERAGETIMETOEMPTY: + *val = 0xFFFF; + break; + case BQ40Z50_ATRATETIMETOFULL: + *val = 0xFFFF; + break; + case BQ40Z50_BTPDISCHARGE: + *val = 150; + break; + case BQ40Z50_BTPCHARGE: + *val = 175; + break; + case BQ40Z50_CYCLECOUNT: + *val = 1; + break; + case BQ40Z50_RELATIVESTATEOFCHARGE: + case BQ40Z50_ABSOLUTESTATEOFCHARGE: + *val = 100; + break; + case BQ40Z50_CHARGINGVOLTAGE: + case BQ40Z50_CHARGINGCURRENT: + *val = 1; + break; + case BQ40Z50_DESIGNCAPACITY: + *val = 1; + break; + + case BQ40Z50_DESIGNVOLTAGE: + *val = 14400; + break; + + case BQ40Z50_RUNTIMETOEMPTY: + *val = 0xFFFF; + break; + + case BQ40Z50_BATTERYMODE: + *val = 0; + break; + + case BQ40Z50_ATRATEOK: + *val = 0; + break; + + case BQ40Z50_REMAININGCAPACITYALARM: + *val = 300; + break; + + case BQ40Z50_REMAININGTIMEALARM: + *val = 10; + break; + + default: + LOG_ERR("Unknown register 0x%x read", reg); + return -EIO; + } + + return 0; +} + +static int emul_bq40z50_read(const struct emul *target, int reg, uint8_t *buf, size_t len) +{ + if (len <= 2) { + /* Normal reads are maximum 1 or 2 bytes wide. */ + uint16_t val; + int rc = emul_bq40z50_reg_read(target, reg, &val); + + if (rc) { + return rc; + } + + sys_put_le16(val, buf); + } else { + switch (reg) { + case BQ40Z50_MANUFACTURERNAME: + case BQ40Z50_DEVICECHEMISTRY: + case BQ40Z50_DEVICENAME: + return emul_bq40z70_buffer_read(reg, buf, len); + default: + LOG_ERR(" Buffer read only supported for string registers (i.e. " + "manufacturer_name, device_chemistry, and device name)"); + return -EIO; + } + } + + return 0; +} + +static int bq40z50_emul_transfer_i2c(const struct emul *target, struct i2c_msg *msgs, int num_msgs, + int addr) +{ + int reg; + int rc; + const struct bq40z50_emul_cfg *cfg = (const struct bq40z50_emul_cfg *)(target->cfg); + + __ASSERT_NO_MSG(msgs && num_msgs); + + if (addr != cfg->i2c_addr) { + LOG_ERR("I2C address (0x%2x) is not supported.", addr); + return -EIO; + } + + i2c_dump_msgs_rw(target->dev, msgs, num_msgs, addr, false); + switch (num_msgs) { + case 1: + if (msgs->flags & I2C_MSG_READ) { + LOG_ERR("Unexpected read"); + return -EIO; + } + + return emul_bq40z50_write(target, msgs->buf, msgs->len); + case 2: + if (msgs->flags & I2C_MSG_READ) { + LOG_ERR("Unexpected read"); + return -EIO; + } + if (msgs->len != 1) { + LOG_ERR("Unexpected addr length %d", msgs->len); + return -EIO; + } + reg = msgs->buf[0]; + + /* Now process the 'read' part of the message */ + msgs++; + if (msgs->flags & I2C_MSG_READ) { + rc = emul_bq40z50_read(target, reg, msgs->buf, msgs->len); + if (rc) { + return rc; + } + } else { + LOG_ERR("Second message must be an I2C read"); + return -EIO; + } + return rc; + default: + LOG_ERR("Invalid number of messages: %d", num_msgs); + return -EIO; + } + + return 0; +} + +static const struct i2c_emul_api bq40z50_emul_api_i2c = { + .transfer = bq40z50_emul_transfer_i2c, +}; + +/** + * Set up a new emulator (I2C) + * + * @param target Emulation information + * @param parent Device to emulate + * @return 0 indicating success (always) + */ +static int emul_bq40z50_init(const struct emul *target, const struct device *parent) +{ + ARG_UNUSED(target); + ARG_UNUSED(parent); + + return 0; +} + +/* + * Main instantiation macro. + */ +#define BQ40Z50_EMUL(n) \ + static const struct bq40z50_emul_cfg bq40z50_emul_cfg_##n = { \ + .i2c_addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DT_INST_DEFINE(n, emul_bq40z50_init, NULL, &bq40z50_emul_cfg_##n, \ + &bq40z50_emul_api_i2c, NULL) + +DT_INST_FOREACH_STATUS_OKAY(BQ40Z50_EMUL) diff --git a/drivers/fuel_gauge/max17048/max17048.c b/drivers/fuel_gauge/max17048/max17048.c index 5a597c4dc5dd3..5f4227f39a92e 100644 --- a/drivers/fuel_gauge/max17048/max17048.c +++ b/drivers/fuel_gauge/max17048/max17048.c @@ -25,6 +25,13 @@ LOG_MODULE_REGISTER(MAX17048); #warning "MAX17048 driver enabled without any devices" #endif +#define RESET_COMMAND 0x5400 +#define QUICKSTART_MODE 0x4000 + +struct max17048_config { + struct i2c_dt_spec i2c; +}; + /** * Storage for the fuel gauge basic information */ @@ -52,7 +59,7 @@ int max17048_read_register(const struct device *dev, uint8_t registerId, uint16_ const struct max17048_config *cfg = dev->config; int rc = i2c_write_read_dt(&cfg->i2c, ®isterId, sizeof(registerId), max17048_buffer, sizeof(max17048_buffer)); - if (rc != 0) { + if (rc) { LOG_ERR("Unable to read register, error %d", rc); return rc; } @@ -77,7 +84,7 @@ int max17048_voltage(const struct device *i2c_dev, uint32_t *response) uint16_t raw_voltage; int rc = max17048_adc(i2c_dev, &raw_voltage); - if (rc < 0) { + if (rc) { return rc; } /** @@ -89,7 +96,7 @@ int max17048_voltage(const struct device *i2c_dev, uint32_t *response) * obtain µV */ - *response = (uint32_t)raw_voltage * 78.125; + *response = ((uint32_t)raw_voltage * 78125) / 1000; return 0; } @@ -101,7 +108,7 @@ int max17048_percent(const struct device *i2c_dev, uint8_t *response) uint16_t data; int rc = max17048_read_register(i2c_dev, REGISTER_SOC, &data); - if (rc < 0) { + if (rc) { return rc; } /** @@ -109,7 +116,7 @@ int max17048_percent(const struct device *i2c_dev, uint8_t *response) * https://www.analog.com/media/en/technical-documentation/data-she4ets/ * MAX17048-MAX17049.pdf * Page 10, Table 2. Register Summary: 1%/256 - * So to obtain the total percentaje we just divide the read value by 256 + * So to obtain the total percentage we just divide the read value by 256 */ *response = data / 256; return 0; @@ -123,7 +130,7 @@ int max17048_crate(const struct device *i2c_dev, int16_t *response) { int rc = max17048_read_register(i2c_dev, REGISTER_CRATE, response); - if (rc < 0) { + if (rc) { return rc; } @@ -135,7 +142,7 @@ int max17048_crate(const struct device *i2c_dev, int16_t *response) * To avoid floats, the value will be multiplied by 208 instead of 0.208, taking into * account that the value will be 1000 times higher */ - *response = *response * 208; + *response *= 208; return 0; } @@ -147,14 +154,15 @@ static int max17048_init(const struct device *dev) { const struct max17048_config *cfg = dev->config; uint16_t version; - int rc = max17048_read_register(dev, REGISTER_VERSION, &version); if (!device_is_ready(cfg->i2c.bus)) { LOG_ERR("Bus device is not ready"); return -ENODEV; } - if (rc < 0) { + int rc = max17048_read_register(dev, REGISTER_VERSION, &version); + + if (rc) { LOG_ERR("Cannot read from I2C"); return rc; } @@ -211,13 +219,13 @@ static int max17048_get_prop(const struct device *dev, fuel_gauge_prop_t prop, int16_t crate; int ret; - if (rc < 0) { + if (rc) { LOG_ERR("Error while reading battery percentage"); return rc; } rc = max17048_voltage(dev, &data->voltage); - if (rc < 0) { + if (rc) { LOG_ERR("Error while reading battery voltage"); return rc; } @@ -227,7 +235,7 @@ static int max17048_get_prop(const struct device *dev, fuel_gauge_prop_t prop, * per hour */ rc = max17048_crate(dev, &crate); - if (rc < 0) { + if (rc) { LOG_ERR("Error while reading battery current rate"); return rc; } @@ -290,7 +298,7 @@ static DEVICE_API(fuel_gauge, max17048_driver_api) = { .i2c = I2C_DT_SPEC_INST_GET(inst)}; \ \ DEVICE_DT_INST_DEFINE(inst, &max17048_init, NULL, &max17048_data_##inst, \ - &max17048_config_##inst, POST_KERNEL, \ - CONFIG_FUEL_GAUGE_INIT_PRIORITY, &max17048_driver_api); + &max17048_config_##inst, POST_KERNEL, \ + CONFIG_FUEL_GAUGE_INIT_PRIORITY, &max17048_driver_api); DT_INST_FOREACH_STATUS_OKAY(MAX17048_DEFINE) diff --git a/drivers/fuel_gauge/max17048/max17048.h b/drivers/fuel_gauge/max17048/max17048.h index 8dc388e2ec929..ae6d1a0856f89 100644 --- a/drivers/fuel_gauge/max17048/max17048.h +++ b/drivers/fuel_gauge/max17048/max17048.h @@ -4,31 +4,25 @@ * SPDX-License-Identifier: Apache-2.0 */ - #ifndef ZEPHYR_DRIVERS_SENSOR_MAX17048_MAX17048_H_ #define ZEPHYR_DRIVERS_SENSOR_MAX17048_MAX17048_H_ #include -#define REGISTER_VCELL 0x02 -#define REGISTER_SOC 0x04 -#define REGISTER_MODE 0x06 -#define REGISTER_VERSION 0x08 -#define REGISTER_HIBRT 0x0A -#define REGISTER_CONFIG 0x0C -#define REGISTER_VALRT 0x14 -#define REGISTER_CRATE 0x16 -#define REGISTER_VRESET 0x18 -#define REGISTER_CHIP_ID 0x19 -#define REGISTER_STATUS 0x1A -#define REGISTER_TABLE 0x40 -#define REGISTER_COMMAND 0xFE - -#define RESET_COMMAND 0x5400 -#define QUICKSTART_MODE 0x4000 - -struct max17048_config { - struct i2c_dt_spec i2c; +enum max17048_regs { + REGISTER_VCELL = 0x02, + REGISTER_SOC = 0x04, + REGISTER_MODE = 0x06, + REGISTER_VERSION = 0x08, + REGISTER_HIBRT = 0x0A, + REGISTER_CONFIG = 0x0C, + REGISTER_VALRT = 0x14, + REGISTER_CRATE = 0x16, + REGISTER_VRESET = 0x18, + REGISTER_CHIP_ID = 0x19, + REGISTER_STATUS = 0x1A, + REGISTER_TABLE = 0x40, + REGISTER_COMMAND = 0xFE, }; #endif /* ZEPHYR_DRIVERS_SENSOR_MAX17048_MAX17048_H_ */ diff --git a/drivers/fuel_gauge/sbs_gauge/sbs_gauge.c b/drivers/fuel_gauge/sbs_gauge/sbs_gauge.c index 64d7c7ed087db..23b3fd57f5f10 100644 --- a/drivers/fuel_gauge/sbs_gauge/sbs_gauge.c +++ b/drivers/fuel_gauge/sbs_gauge/sbs_gauge.c @@ -22,6 +22,22 @@ LOG_MODULE_REGISTER(sbs_gauge); +#define SBS_GAUGE_DELAY 1000 + +struct sbs_gauge_battery_cutoff_config { + /* Size of the payload array */ + size_t payload_size; + /* Array SMBus word values to write to cut off the battery */ + uint32_t payload[SBS_GAUGE_CUTOFF_PAYLOAD_MAX_SIZE]; + /* Register to write cutoff payload */ + uint8_t reg; +}; + +struct sbs_gauge_config { + struct i2c_dt_spec i2c; + const struct sbs_gauge_battery_cutoff_config *cutoff_cfg; +}; + static int sbs_cmd_reg_read(const struct device *dev, uint8_t reg_addr, uint16_t *val) { const struct sbs_gauge_config *cfg; @@ -51,7 +67,7 @@ static int sbs_cmd_reg_write(const struct device *dev, uint8_t reg_addr, uint16_ } static int sbs_cmd_buffer_read(const struct device *dev, uint8_t reg_addr, char *buffer, - const uint8_t buffer_size) + const uint8_t buffer_size) { const struct sbs_gauge_config *cfg; int status; @@ -233,9 +249,8 @@ static int sbs_gauge_set_prop(const struct device *dev, fuel_gauge_prop_t prop, return rc; } -static int sbs_gauge_get_buffer_prop(const struct device *dev, - fuel_gauge_prop_t prop_type, void *dst, - size_t dst_len) +static int sbs_gauge_get_buffer_prop(const struct device *dev, fuel_gauge_prop_t prop_type, + void *dst, size_t dst_len) { int rc = 0; @@ -243,7 +258,7 @@ static int sbs_gauge_get_buffer_prop(const struct device *dev, case FUEL_GAUGE_MANUFACTURER_NAME: if (dst_len == sizeof(struct sbs_gauge_manufacturer_name)) { rc = sbs_cmd_buffer_read(dev, SBS_GAUGE_CMD_MANUFACTURER_NAME, (char *)dst, - dst_len); + dst_len); } else { rc = -EINVAL; } @@ -251,7 +266,7 @@ static int sbs_gauge_get_buffer_prop(const struct device *dev, case FUEL_GAUGE_DEVICE_NAME: if (dst_len == sizeof(struct sbs_gauge_device_name)) { rc = sbs_cmd_buffer_read(dev, SBS_GAUGE_CMD_DEVICE_NAME, (char *)dst, - dst_len); + dst_len); } else { rc = -EINVAL; } @@ -259,7 +274,7 @@ static int sbs_gauge_get_buffer_prop(const struct device *dev, case FUEL_GAUGE_DEVICE_CHEMISTRY: if (dst_len == sizeof(struct sbs_gauge_device_chemistry)) { rc = sbs_cmd_buffer_read(dev, SBS_GAUGE_CMD_DEVICE_CHEMISTRY, (char *)dst, - dst_len); + dst_len); } else { rc = -EINVAL; } diff --git a/drivers/fuel_gauge/sbs_gauge/sbs_gauge.h b/drivers/fuel_gauge/sbs_gauge/sbs_gauge.h index 2ae8007125c5b..c2b312df242d8 100644 --- a/drivers/fuel_gauge/sbs_gauge/sbs_gauge.h +++ b/drivers/fuel_gauge/sbs_gauge/sbs_gauge.h @@ -11,41 +11,41 @@ #include /** Standard Commands */ -#define SBS_GAUGE_CMD_MANUFACTURER_ACCESS 0x00 /* ManufacturerAccess */ -#define SBS_GAUGE_CMD_REM_CAPACITY_ALARM 0x01 /* LowCapacityAlarmThreshold */ -#define SBS_GAUGE_CMD_REM_TIME_ALARM 0x02 /* RemainingTimeToEmptyThreshold */ -#define SBS_GAUGE_CMD_BATTERY_MODE 0x03 /* BatteryOperatingMode */ -#define SBS_GAUGE_CMD_AR 0x04 /* AtRate */ -#define SBS_GAUGE_CMD_ARTTF 0x05 /* AtRateTimeToFull */ -#define SBS_GAUGE_CMD_ARTTE 0x06 /* AtRateTimeToEmpty */ -#define SBS_GAUGE_CMD_AROK 0x07 /* AtRateOK */ -#define SBS_GAUGE_CMD_TEMP 0x08 /* Temperature */ -#define SBS_GAUGE_CMD_VOLTAGE 0x09 /* Voltage */ -#define SBS_GAUGE_CMD_CURRENT 0x0A /* Current */ -#define SBS_GAUGE_CMD_AVG_CURRENT 0x0B /* AverageCurrent */ -#define SBS_GAUGE_CMD_MAX_ERROR 0x0C /* MaxError */ -#define SBS_GAUGE_CMD_RSOC 0x0D /* RelativeStateOfCharge */ -#define SBS_GAUGE_CMD_ASOC 0x0E /* AbsoluteStateOfCharge */ -#define SBS_GAUGE_CMD_REM_CAPACITY 0x0F /* RemainingCapacity */ -#define SBS_GAUGE_CMD_FULL_CAPACITY 0x10 /* FullChargeCapacity */ -#define SBS_GAUGE_CMD_RUNTIME2EMPTY 0x11 /* RunTimeToEmpty */ -#define SBS_GAUGE_CMD_AVG_TIME2EMPTY 0x12 /* AverageTimeToEmpty */ -#define SBS_GAUGE_CMD_AVG_TIME2FULL 0x13 /* AverageTimeToFull */ -#define SBS_GAUGE_CMD_CHG_CURRENT 0x14 /* ChargeCurrent */ -#define SBS_GAUGE_CMD_CHG_VOLTAGE 0x15 /* ChargeVoltage */ -#define SBS_GAUGE_CMD_FLAGS 0x16 /* BatteryStatus */ -#define SBS_GAUGE_CMD_CYCLE_COUNT 0x17 /* CycleCount */ -#define SBS_GAUGE_CMD_NOM_CAPACITY 0x18 /* DesignCapacity */ -#define SBS_GAUGE_CMD_DESIGN_VOLTAGE 0x19 /* DesignVoltage */ -#define SBS_GAUGE_CMD_SPECS_INFO 0x1A /* SpecificationInfo */ -#define SBS_GAUGE_CMD_MANUFACTURER_DATE 0x1B /* ManufacturerDate */ -#define SBS_GAUGE_CMD_SN 0x1C /* SerialNumber */ -#define SBS_GAUGE_CMD_MANUFACTURER_NAME 0x20 /* ManufacturerName */ -#define SBS_GAUGE_CMD_DEVICE_NAME 0x21 /* DeviceName */ -#define SBS_GAUGE_CMD_DEVICE_CHEMISTRY 0x22 /* DeviceChemistry */ -#define SBS_GAUGE_CMD_MANUFACTURER_DATA 0x23 /* ManufacturerData */ - -#define SBS_GAUGE_DELAY 1000 +enum sbs_gauge_cmds { + SBS_GAUGE_CMD_MANUFACTURER_ACCESS = 0x00, /* ManufacturerAccess */ + SBS_GAUGE_CMD_REM_CAPACITY_ALARM = 0x01, /* LowCapacityAlarmThreshold */ + SBS_GAUGE_CMD_REM_TIME_ALARM = 0x02, /* RemainingTimeToEmptyThreshold */ + SBS_GAUGE_CMD_BATTERY_MODE = 0x03, /* BatteryOperatingMode */ + SBS_GAUGE_CMD_AR = 0x04, /* AtRate */ + SBS_GAUGE_CMD_ARTTF = 0x05, /* AtRateTimeToFull */ + SBS_GAUGE_CMD_ARTTE = 0x06, /* AtRateTimeToEmpty */ + SBS_GAUGE_CMD_AROK = 0x07, /* AtRateOK */ + SBS_GAUGE_CMD_TEMP = 0x08, /* Temperature */ + SBS_GAUGE_CMD_VOLTAGE = 0x09, /* Voltage */ + SBS_GAUGE_CMD_CURRENT = 0x0A, /* Current */ + SBS_GAUGE_CMD_AVG_CURRENT = 0x0B, /* AverageCurrent */ + SBS_GAUGE_CMD_MAX_ERROR = 0x0C, /* MaxError */ + SBS_GAUGE_CMD_RSOC = 0x0D, /* RelativeStateOfCharge */ + SBS_GAUGE_CMD_ASOC = 0x0E, /* AbsoluteStateOfCharge */ + SBS_GAUGE_CMD_REM_CAPACITY = 0x0F, /* RemainingCapacity */ + SBS_GAUGE_CMD_FULL_CAPACITY = 0x10, /* FullChargeCapacity */ + SBS_GAUGE_CMD_RUNTIME2EMPTY = 0x11, /* RunTimeToEmpty */ + SBS_GAUGE_CMD_AVG_TIME2EMPTY = 0x12, /* AverageTimeToEmpty */ + SBS_GAUGE_CMD_AVG_TIME2FULL = 0x13, /* AverageTimeToFull */ + SBS_GAUGE_CMD_CHG_CURRENT = 0x14, /* ChargeCurrent */ + SBS_GAUGE_CMD_CHG_VOLTAGE = 0x15, /* ChargeVoltage */ + SBS_GAUGE_CMD_FLAGS = 0x16, /* BatteryStatus */ + SBS_GAUGE_CMD_CYCLE_COUNT = 0x17, /* CycleCount */ + SBS_GAUGE_CMD_NOM_CAPACITY = 0x18, /* DesignCapacity */ + SBS_GAUGE_CMD_DESIGN_VOLTAGE = 0x19, /* DesignVoltage */ + SBS_GAUGE_CMD_SPECS_INFO = 0x1A, /* SpecificationInfo */ + SBS_GAUGE_CMD_MANUFACTURER_DATE = 0x1B, /* ManufacturerDate */ + SBS_GAUGE_CMD_SN = 0x1C, /* SerialNumber */ + SBS_GAUGE_CMD_MANUFACTURER_NAME = 0x20, /* ManufacturerName */ + SBS_GAUGE_CMD_DEVICE_NAME = 0x21, /* DeviceName */ + SBS_GAUGE_CMD_DEVICE_CHEMISTRY = 0x22, /* DeviceChemistry */ + SBS_GAUGE_CMD_MANUFACTURER_DATA = 0x23, /* ManufacturerData */ +}; /* * Nearly all cutoff payloads are actually a singular value that must be written twice to the fuel @@ -62,18 +62,4 @@ */ #define SBS_GAUGE_CUTOFF_PAYLOAD_MAX_SIZE 2 -struct sbs_gauge_battery_cutoff_config { - /* Size of the payload array */ - size_t payload_size; - /* Array SMBus word values to write to cut off the battery */ - uint32_t payload[SBS_GAUGE_CUTOFF_PAYLOAD_MAX_SIZE]; - /* Register to write cutoff payload */ - uint8_t reg; -}; - -struct sbs_gauge_config { - struct i2c_dt_spec i2c; - const struct sbs_gauge_battery_cutoff_config *cutoff_cfg; -}; - #endif diff --git a/drivers/gnss/gnss_ubx_common.c b/drivers/gnss/gnss_ubx_common.c index 73998442562e1..35d0769098cbf 100644 --- a/drivers/gnss/gnss_ubx_common.c +++ b/drivers/gnss/gnss_ubx_common.c @@ -136,8 +136,8 @@ void gnss_ubx_common_satellite_callback(struct modem_ubx *ubx, const struct ubx_ .elevation = ubx_sat->sat[i].elevation, .azimuth = ubx_sat->sat[i].azimuth, .system = gnss_system, - .is_tracked = (ubx_sat->sat[i].flags & UBX_NAV_SAT_FLAGS_SV_USED), - .is_corrected = (ubx_sat->sat[i].flags & UBX_NAV_SAT_FLAGS_RTCM_CORR_USED) + .is_tracked = !!(ubx_sat->sat[i].flags & UBX_NAV_SAT_FLAGS_SV_USED), + .is_corrected = !!(ubx_sat->sat[i].flags & UBX_NAV_SAT_FLAGS_RTCM_CORR_USED) }; data->satellites.data[i] = sat; diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 0e1cf4155ed9a..7947c44318b4f 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_AW9523B gpio_aw9523b.c) zephyr_library_sources_ifdef(CONFIG_GPIO_AXP192 gpio_axp192.c) zephyr_library_sources_ifdef(CONFIG_GPIO_BCM2711 gpio_bcm2711.c) zephyr_library_sources_ifdef(CONFIG_GPIO_BD8LB600FS gpio_bd8lb600fs.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_BFLB_BL61X gpio_bflb_bl61x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_BRCMSTB gpio_brcmstb.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CC13XX_CC26XX gpio_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_CC23X0 gpio_cc23x0.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 87271f0ff9411..61139e04d3b66 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -105,6 +105,7 @@ source "drivers/gpio/Kconfig.axp192" source "drivers/gpio/Kconfig.b91" source "drivers/gpio/Kconfig.bcm2711" source "drivers/gpio/Kconfig.bd8lb600fs" +source "drivers/gpio/Kconfig.bflb" source "drivers/gpio/Kconfig.brcmstb" source "drivers/gpio/Kconfig.cc13xx_cc26xx" source "drivers/gpio/Kconfig.cc23x0" diff --git a/drivers/gpio/Kconfig.bflb b/drivers/gpio/Kconfig.bflb new file mode 100644 index 0000000000000..0d78d8bbd1c63 --- /dev/null +++ b/drivers/gpio/Kconfig.bflb @@ -0,0 +1,9 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_BFLB_BL61X + bool "Bouffalo Lab BL61X GPIO driver" + depends on DT_HAS_BFLB_BL61X_GPIO_ENABLED + default y + help + Bouffalo Lab BL61X GPIO driver diff --git a/drivers/gpio/Kconfig.renesas_ra_ioport b/drivers/gpio/Kconfig.renesas_ra_ioport index 0aff2565c5acf..6d2db6ba24665 100644 --- a/drivers/gpio/Kconfig.renesas_ra_ioport +++ b/drivers/gpio/Kconfig.renesas_ra_ioport @@ -5,6 +5,7 @@ config GPIO_RA_IOPORT bool "Renesas RA GPIO IO port driver" default y depends on DT_HAS_RENESAS_RA_GPIO_IOPORT_ENABLED + select PINCTRL help Enable the Renesas RA GPIO IO port driver. diff --git a/drivers/gpio/gpio_bflb_bl61x.c b/drivers/gpio/gpio_bflb_bl61x.c new file mode 100644 index 0000000000000..b75acf2faf7c9 --- /dev/null +++ b/drivers/gpio/gpio_bflb_bl61x.c @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT bflb_bl61x_gpio + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +LOG_MODULE_REGISTER(gpio_bflb_bl61x); + +#define GPIO_BFLB_FUNCTION_GPIO 11 +/* Medium drive strength, 0 to 3 */ +#define GPIO_BFLB_DRIVE_STRENGTH 1 + +#define GPIO_BFLB_TRIG_MODE_SYNC_LOW 0 +#define GPIO_BFLB_TRIG_MODE_SYNC_HIGH 1 +#define GPIO_BFLB_TRIG_MODE_SYNC_LEVEL 2 +#define GPIO_BFLB_TRIG_MODE_SYNC_EDGE_BOTH 4 + +#define GPIO_BFLB_PIN_REG_SIZE_SHIFT 2 + +/* This driver is limited by zephyr masks and supports only 32 pins for simplicity. + * BL61x serie supports up to 35 pins. + */ + +struct gpio_bflb_config { + /* gpio_driver_config needs to be first */ + struct gpio_driver_config common; + uint32_t base_reg; + void (*irq_config_func)(const struct device *dev); + void (*irq_enable_func)(const struct device *dev); +}; + +struct gpio_bflb_data { + /* gpio_driver_data needs to be first */ + struct gpio_driver_data common; + sys_slist_t callbacks; +}; + +static int gpio_bflb_port_get_raw(const struct device *dev, uint32_t *value) +{ + const struct gpio_bflb_config * const cfg = dev->config; + + *value = sys_read32(cfg->base_reg + GLB_GPIO_CFG128_OFFSET); + + return 0; +} + +static int gpio_bflb_port_set_masked_raw(const struct device *dev, + uint32_t mask, + uint32_t value) +{ + const struct gpio_bflb_config * const cfg = dev->config; + uint32_t tmp; + + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + tmp = (tmp & ~mask) | (mask & value); + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + + return 0; +} + +static int gpio_bflb_port_set_bits_raw(const struct device *dev, uint32_t mask) +{ + const struct gpio_bflb_config * const cfg = dev->config; + uint32_t tmp; + + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + tmp = tmp | mask; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + + return 0; +} + +static int gpio_bflb_port_clear_bits_raw(const struct device *dev, uint32_t mask) +{ + const struct gpio_bflb_config * const cfg = dev->config; + uint32_t tmp; + + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + tmp = tmp & ~mask; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + + return 0; +} + +static int gpio_bflb_port_toggle_bits(const struct device *dev, uint32_t mask) +{ + const struct gpio_bflb_config * const cfg = dev->config; + uint32_t tmp; + + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + tmp ^= mask; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG136_OFFSET); + + return 0; +} + +static void gpio_bflb_port_interrupt_configure_mode(const struct device *dev, uint32_t pin, + enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + const struct gpio_bflb_config * const cfg = dev->config; + uint32_t tmp; + uint8_t trig_mode = GPIO_BFLB_TRIG_MODE_SYNC_LOW; + + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + /* clear modes */ + tmp &= GLB_REG_GPIO_0_INT_MODE_SET_UMSK; + + if ((trig & GPIO_INT_HIGH_1) != 0 + && (trig & GPIO_INT_LOW_0) != 0 + && (mode & GPIO_INT_EDGE)) { + trig_mode |= GPIO_BFLB_TRIG_MODE_SYNC_EDGE_BOTH; + } else if ((trig & GPIO_INT_HIGH_1) != 0) { + trig_mode |= GPIO_BFLB_TRIG_MODE_SYNC_HIGH; + } + + if ((mode & GPIO_INT_EDGE) == 0) { + trig_mode |= GPIO_BFLB_TRIG_MODE_SYNC_LEVEL; + } + tmp |= (trig_mode << GLB_REG_GPIO_0_INT_MODE_SET_POS); + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); +} + + +static void gpio_bflb_pin_interrupt_clear(const struct device *dev, gpio_pin_t pin) +{ + const struct gpio_bflb_config * const cfg = dev->config; + uint32_t tmp; + + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + tmp |= GLB_REG_GPIO_0_INT_CLR_MSK; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + tmp &= GLB_REG_GPIO_0_INT_CLR_UMSK; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); +} + +static void gpio_bflb_pins_interrupt_clear(const struct device *dev, uint32_t mask) +{ + for (int i = 0; i < 32; i++) { + if (((mask >> i) & 0x1) != 0) { + gpio_bflb_pin_interrupt_clear(dev, i); + } + } +} + +static int gpio_bflb_pin_interrupt_configure(const struct device *dev, + gpio_pin_t pin, + enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + const struct gpio_bflb_config * const cfg = dev->config; + uint32_t tmp; + + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + tmp |= GLB_REG_GPIO_0_INT_MASK_MSK; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + + gpio_bflb_port_interrupt_configure_mode(dev, pin, mode, trig); + + if (mode != GPIO_INT_MODE_DISABLED) { + gpio_bflb_pin_interrupt_clear(dev, pin); + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + tmp &= GLB_REG_GPIO_0_INT_MASK_UMSK; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + } else { + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + tmp |= GLB_REG_GPIO_0_INT_MASK_MSK; + sys_write32(tmp, cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + } + cfg->irq_enable_func(dev); + + return 0; +} + +#ifdef CONFIG_GPIO_GET_CONFIG +static int gpio_bflb_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags) +{ + const struct gpio_bflb_config * const conf = dev->config; + uint32_t cfg, out; + + *flags = 0; + + cfg = sys_read32(conf->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + out = sys_read32(conf->base_reg + GLB_GPIO_CFG136_OFFSET); + + if ((cfg & GLB_REG_GPIO_0_IE_MSK) != 0) { + *flags |= GPIO_INPUT; + } else if ((cfg & GLB_REG_GPIO_0_OE_MSK) != 0) { + *flags |= GPIO_OUTPUT; + *flags |= (out & (1U << pin)) != 0 ? GPIO_OUTPUT_HIGH : GPIO_OUTPUT_LOW; + } + if ((cfg & GLB_REG_GPIO_0_PU_MSK) != 0) { + *flags |= GPIO_PULL_UP; + } else if ((cfg & GLB_REG_GPIO_0_PD_MSK) != 0) { + *flags |= GPIO_PULL_DOWN; + } + + return 0; +} +#endif + +static int gpio_bflb_config(const struct device *dev, gpio_pin_t pin, + gpio_flags_t flags) +{ + const struct gpio_bflb_config * const conf = dev->config; + uint32_t cfg; + uint32_t tmp; + + /* disable RC32K muxing */ + if (pin == 16) { + *(volatile uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) + &= ~(1 << HBN_REG_EN_AON_CTRL_GPIO_POS); + } else if (pin == 17) { + *(volatile uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) + &= ~(1 << (HBN_REG_EN_AON_CTRL_GPIO_POS + 1)); + } + + cfg = sys_read32(conf->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + + if ((flags & GPIO_INPUT) != 0) { + cfg |= GLB_REG_GPIO_0_IE_MSK; + cfg &= GLB_REG_GPIO_0_OE_UMSK; + } else if ((flags & GPIO_OUTPUT) != 0) { + cfg &= GLB_REG_GPIO_0_IE_UMSK; + cfg |= GLB_REG_GPIO_0_OE_MSK; + if (flags & GPIO_OUTPUT_INIT_HIGH) { + tmp = sys_read32(conf->base_reg + GLB_GPIO_CFG136_OFFSET); + tmp |= 1U << pin; + sys_write32(tmp, conf->base_reg + GLB_GPIO_CFG136_OFFSET); + } + if (flags & GPIO_OUTPUT_INIT_LOW) { + tmp = sys_read32(conf->base_reg + GLB_GPIO_CFG136_OFFSET); + tmp &= ~(1U << pin); + sys_write32(tmp, conf->base_reg + GLB_GPIO_CFG136_OFFSET); + } + } + + if ((flags & GPIO_PULL_UP) != 0) { + cfg &= GLB_REG_GPIO_0_PD_UMSK; + cfg |= GLB_REG_GPIO_0_PU_MSK; + } else if ((flags & GPIO_PULL_DOWN) != 0) { + cfg |= GLB_REG_GPIO_0_PD_MSK; + cfg &= GLB_REG_GPIO_0_PU_UMSK; + } else { + cfg &= GLB_REG_GPIO_0_PD_UMSK; + cfg &= GLB_REG_GPIO_0_PU_UMSK; + } + + /* Schmitt trigger is enabled for GPIO */ + cfg |= GLB_REG_GPIO_0_SMT_MSK; + + cfg &= GLB_REG_GPIO_0_DRV_UMSK; + cfg |= (GPIO_BFLB_DRIVE_STRENGTH << GLB_REG_GPIO_0_DRV_POS); + + cfg &= GLB_REG_GPIO_0_FUNC_SEL_UMSK; + cfg |= (GPIO_BFLB_FUNCTION_GPIO << GLB_REG_GPIO_0_FUNC_SEL_POS); + + /* output is controlled by value of _o*/ + cfg &= GLB_REG_GPIO_0_MODE_UMSK; + + sys_write32(cfg, conf->base_reg + GLB_GPIO_CFG0_OFFSET + + (pin << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + + return 0; +} + +int gpio_bflb_init(const struct device *dev) +{ + const struct gpio_bflb_config * const cfg = dev->config; + + cfg->irq_config_func(dev); + + return 0; +} + +static void gpio_bflb_isr(const struct device *dev) +{ + const struct gpio_bflb_config * const cfg = dev->config; + struct gpio_bflb_data *data = dev->data; + uint32_t int_stat = 0; + uint32_t tmp; + + for (int i = 0; i < 32; i++) { + tmp = sys_read32(cfg->base_reg + GLB_GPIO_CFG0_OFFSET + + (i << GPIO_BFLB_PIN_REG_SIZE_SHIFT)); + int_stat |= ((tmp & GLB_GPIO_0_INT_STAT_MSK) != 0 ? 1 : 0) << i; + } + + gpio_fire_callbacks(&data->callbacks, dev, int_stat); + gpio_bflb_pins_interrupt_clear(dev, int_stat); +} + +static int gpio_bflb_manage_callback(const struct device *port, + struct gpio_callback *callback, + bool set) +{ + struct gpio_bflb_data *data = port->data; + + return gpio_manage_callback(&(data->callbacks), callback, set); +} + +static const struct gpio_driver_api gpio_bflb_api = { + .pin_configure = gpio_bflb_config, +#ifdef CONFIG_GPIO_GET_CONFIG + .pin_get_config = gpio_bflb_get_config, +#endif + .port_get_raw = gpio_bflb_port_get_raw, + .port_set_masked_raw = gpio_bflb_port_set_masked_raw, + .port_set_bits_raw = gpio_bflb_port_set_bits_raw, + .port_clear_bits_raw = gpio_bflb_port_clear_bits_raw, + .port_toggle_bits = gpio_bflb_port_toggle_bits, + .pin_interrupt_configure = gpio_bflb_pin_interrupt_configure, + .manage_callback = gpio_bflb_manage_callback, +}; + +#define GPIO_BFLB_INIT(n) \ + static void port_##n##_bflb_irq_config_func(const struct device *dev); \ + static void port_##n##_bflb_irq_enable_func(const struct device *dev); \ + \ + static const struct gpio_bflb_config port_##n##_bflb_config = { \ + .common = { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \ + }, \ + .base_reg = DT_INST_REG_ADDR(n), \ + .irq_config_func = port_##n##_bflb_irq_config_func, \ + .irq_enable_func = port_##n##_bflb_irq_enable_func, \ + }; \ + \ + static struct gpio_bflb_data port_##n##_bflb_data; \ + \ + DEVICE_DT_INST_DEFINE(n, gpio_bflb_init, NULL, \ + &port_##n##_bflb_data, \ + &port_##n##_bflb_config, PRE_KERNEL_1, \ + CONFIG_GPIO_INIT_PRIORITY, \ + &gpio_bflb_api); \ + \ + static void port_##n##_bflb_irq_config_func(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ + gpio_bflb_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + } \ + static void port_##n##_bflb_irq_enable_func(const struct device *dev) \ + { \ + irq_enable(DT_INST_IRQN(n)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(GPIO_BFLB_INIT) diff --git a/drivers/gpio/gpio_esp32.c b/drivers/gpio/gpio_esp32.c index 289565302bffd..33d7396997520 100644 --- a/drivers/gpio/gpio_esp32.c +++ b/drivers/gpio/gpio_esp32.c @@ -44,8 +44,8 @@ LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL); #define out_w1tc out_w1tc.val /* arch_curr_cpu() is not available for riscv based chips */ #define ESP32_CPU_ID() 0 -#elif defined(CONFIG_SOC_SERIES_ESP32C6) -/* gpio structs in esp32c6 are also different */ +#elif defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) +/* gpio structs in esp32c6/h2 are also different */ #define out out.out_data_orig #define in in.in_data_next #define out_w1ts out_w1ts.val diff --git a/drivers/gpio/gpio_silabs.c b/drivers/gpio/gpio_silabs.c index b2935c9555185..a3b1f2fd7c636 100644 --- a/drivers/gpio/gpio_silabs.c +++ b/drivers/gpio/gpio_silabs.c @@ -22,8 +22,11 @@ LOG_MODULE_REGISTER(gpio_silabs, CONFIG_GPIO_LOG_LEVEL); #define GET_SILABS_GPIO_INDEX(node_id) \ (DT_REG_ADDR(node_id) - DT_REG_ADDR(DT_NODELABEL(gpioa))) / SILABS_GPIO_PORT_ADDR_SPACE_SIZE -#define NUMBER_OF_PORTS (SIZEOF_FIELD(GPIO_TypeDef, P) / SIZEOF_FIELD(GPIO_TypeDef, P[0])) -#define NUM_IRQ_LINES 16 +#define NUMBER_OF_PORTS (SIZEOF_FIELD(GPIO_TypeDef, P) / SIZEOF_FIELD(GPIO_TypeDef, P[0])) +#define NUM_IRQ_LINES 16 +#define MAX_EM4_IRQ_PER_PORT 3 +#define EM4WU_TO_INT(wu) ((wu) + NUM_IRQ_LINES) +#define INT_TO_EM4WU(int_no) ((int_no) - NUM_IRQ_LINES) struct gpio_silabs_common_config { /* IRQ configuration function */ @@ -39,6 +42,11 @@ struct gpio_silabs_common_data { const struct device *ports[NUMBER_OF_PORTS]; }; +struct gpio_silabs_em4wu_mapping { + uint8_t wu_no; + uint8_t pin; +}; + struct gpio_silabs_port_config { /* gpio_driver_config must be first */ struct gpio_driver_config common; @@ -46,6 +54,10 @@ struct gpio_silabs_port_config { sl_gpio_port_t gpio_index; /* pointer to common device */ const struct device *common_dev; + /* Number of valid EM4 wakeup interrupt mappings */ + int em4wu_pin_count; + /* EM4 wakeup interrupt mapping for GPIO pins */ + struct gpio_silabs_em4wu_mapping em4wu_pins[MAX_EM4_IRQ_PER_PORT]; }; struct gpio_silabs_port_data { @@ -253,6 +265,38 @@ static int interrupt_to_pin(int int_no) return ROUND_DOWN(int_no, 4) + FIELD_GET(0xF << (offset * 4), reg); } +static int gpio_silabs_pin_interrupt_configure_em4wu(sl_gpio_t *gpio, enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + int32_t em4wu_no = sl_hal_gpio_get_em4_interrupt_number(gpio); + int32_t int_no = EM4WU_TO_INT(em4wu_no); + + if (em4wu_no == SL_GPIO_INTERRUPT_UNAVAILABLE) { + LOG_ERR("Pin %u is not EM4 wakeup capable", gpio->pin); + return -EINVAL; + } + + if (mode != GPIO_INT_MODE_DISABLED) { + if (trig == GPIO_INT_TRIG_BOTH) { + LOG_ERR("EM4 wakeup interrupt on pin %u can only trigger on one edge", + gpio->pin); + return -ENOTSUP; + } + + sl_hal_gpio_configure_wakeup_em4_external_interrupt(gpio, em4wu_no, + trig == GPIO_INT_TRIG_HIGH); + } + + if (mode == GPIO_INT_MODE_DISABLED) { + sl_hal_gpio_disable_interrupts(BIT(int_no)); + sl_hal_gpio_disable_pin_em4_wakeup(BIT(int_no)); + } else { + sl_hal_gpio_enable_interrupts(BIT(int_no)); + } + + return 0; +} + static int gpio_silabs_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, enum gpio_int_mode mode, enum gpio_int_trig trig) { @@ -264,12 +308,20 @@ static int gpio_silabs_pin_interrupt_configure(const struct device *dev, gpio_pi sl_gpio_interrupt_flag_t flag = SL_GPIO_INTERRUPT_RISING_FALLING_EDGE; uint32_t enabled_interrupts; int32_t int_no = SL_GPIO_INTERRUPT_UNAVAILABLE; + bool em4_wakeup; + + em4_wakeup = ((trig & GPIO_INT_WAKEUP) == GPIO_INT_WAKEUP); + trig &= ~GPIO_INT_WAKEUP; if (mode == GPIO_INT_MODE_LEVEL) { LOG_ERR("Level interrupt not supported on pin %u", pin); return -ENOTSUP; } + if (em4_wakeup) { + return gpio_silabs_pin_interrupt_configure_em4wu(&gpio, mode, trig); + } + enabled_interrupts = sl_hal_gpio_get_enabled_interrupts(); for (int i = 0; i < NUM_IRQ_LINES; ++i) { @@ -315,6 +367,25 @@ static int gpio_silabs_port_manage_callback(const struct device *dev, struct gpi return gpio_manage_callback(&data->callbacks, cb, set); } +static void gpio_silabs_em4wu_interrupt_to_port_pin(struct gpio_silabs_common_data *data, + int int_no, int *port, int *pin) +{ + ARRAY_FOR_EACH(data->ports, p) { + const struct device *dev = data->ports[p]; + const struct gpio_silabs_port_config *config = dev->config; + + for (int i = 0; i < config->em4wu_pin_count; i++) { + const struct gpio_silabs_em4wu_mapping *em4wu = &config->em4wu_pins[i]; + + if (em4wu->wu_no == INT_TO_EM4WU(int_no)) { + *port = config->gpio_index; + *pin = em4wu->pin; + return; + } + } + } +} + static void gpio_silabs_common_isr(const struct device *dev) { struct gpio_silabs_common_data *data = dev->data; @@ -323,8 +394,15 @@ static void gpio_silabs_common_isr(const struct device *dev) while (pending) { int int_no = find_lsb_set(pending) - 1; - int port = interrupt_to_port(int_no); - int pin = interrupt_to_pin(int_no); + int port = -1; + int pin = -1; + + if (int_no >= NUM_IRQ_LINES) { + gpio_silabs_em4wu_interrupt_to_port_pin(data, int_no, &port, &pin); + } else { + port = interrupt_to_port(int_no); + pin = interrupt_to_pin(int_no); + } port_pin_masks[port] |= BIT(pin); sl_hal_gpio_clear_interrupts(BIT(int_no)); @@ -385,11 +463,19 @@ static int gpio_silabs_common_init(const struct device *dev) return 0; } +#define EM4_WAKEUP_PIN(node, prop, idx) \ + { \ + .wu_no = DT_PROP_BY_IDX(node, prop, idx), \ + .pin = DT_PROP_BY_IDX(node, silabs_wakeup_pins, idx), \ + }, + #define GPIO_PORT_INIT(n) \ static const struct gpio_silabs_port_config gpio_silabs_port_config_##n = { \ .common.port_pin_mask = (gpio_port_pins_t)(-1), \ .gpio_index = GET_SILABS_GPIO_INDEX(n), \ .common_dev = DEVICE_DT_GET(DT_PARENT(n)), \ + .em4wu_pin_count = DT_PROP_LEN(n, silabs_wakeup_ints), \ + .em4wu_pins = {DT_FOREACH_PROP_ELEM(n, silabs_wakeup_ints, EM4_WAKEUP_PIN)}, \ }; \ static struct gpio_silabs_port_data gpio_silabs_port_data_##n; \ DEVICE_DT_DEFINE(n, gpio_silabs_port_init, NULL, &gpio_silabs_port_data_##n, \ diff --git a/drivers/hwinfo/CMakeLists.txt b/drivers/hwinfo/CMakeLists.txt index 85fb6b8eba5b1..f1dcc284eb01c 100644 --- a/drivers/hwinfo/CMakeLists.txt +++ b/drivers/hwinfo/CMakeLists.txt @@ -40,3 +40,13 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_SILABS_S2 hwinfo_silabs_series2.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_SMARTBOND hwinfo_smartbond.c) zephyr_library_sources_ifdef(CONFIG_HWINFO_STM32 hwinfo_stm32.c) # zephyr-keep-sorted-stop + +if(CONFIG_HWINFO_NATIVE) + if(${CMAKE_HOST_SYSTEM_NAME} STREQUAL Linux) + zephyr_library_sources(hwinfo_native.c) + + target_sources(native_simulator INTERFACE hwinfo_native_bottom.c) + else() + message(FATAL_ERROR "CONFIG_HWINFO_NATIVE is only available on Linux") + endif() +endif() diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 89e47925773c8..86d52152e64bd 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -43,6 +43,7 @@ rsource "Kconfig.mcux_src" rsource "Kconfig.mcux_src_rev2" rsource "Kconfig.mcux_syscon" rsource "Kconfig.mspm0" +rsource "Kconfig.native" rsource "Kconfig.nrf" rsource "Kconfig.numaker" rsource "Kconfig.numaker_rmc" diff --git a/drivers/hwinfo/Kconfig.mcux_mcx_cmc b/drivers/hwinfo/Kconfig.mcux_mcx_cmc index e53acc24b84e6..1efe328ef99a8 100644 --- a/drivers/hwinfo/Kconfig.mcux_mcx_cmc +++ b/drivers/hwinfo/Kconfig.mcux_mcx_cmc @@ -4,7 +4,7 @@ config HWINFO_MCUX_MCX_CMC bool "NXP MCX CMC reset cause" default y - depends on HAS_MCUX_MCX_CMC + depends on DT_HAS_NXP_CMC_RESET_CAUSE_ENABLED select HWINFO_HAS_DRIVER help Enable NXP kinetis mcux CMC hwinfo driver. diff --git a/drivers/hwinfo/Kconfig.native b/drivers/hwinfo/Kconfig.native new file mode 100644 index 0000000000000..9ff5b3695c27a --- /dev/null +++ b/drivers/hwinfo/Kconfig.native @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config HWINFO_NATIVE + bool "HWINFO driver for native_sim" + default y + depends on ARCH_POSIX + select HWINFO_HAS_DRIVER + help + Enable native_sim HWINFO driver. diff --git a/drivers/hwinfo/hwinfo_esp32.c b/drivers/hwinfo/hwinfo_esp32.c index 5a453a000518d..39fbc5b18691b 100644 --- a/drivers/hwinfo/hwinfo_esp32.c +++ b/drivers/hwinfo/hwinfo_esp32.c @@ -18,6 +18,9 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) #if defined(CONFIG_SOC_SERIES_ESP32C2) uint32_t rdata1 = sys_read32(EFUSE_RD_BLK2_DATA0_REG); uint32_t rdata2 = sys_read32(EFUSE_RD_BLK2_DATA1_REG); +#elif defined(CONFIG_SOC_SERIES_ESP32H2) + uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SYS_0_REG); + uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SYS_1_REG); #elif !defined(CONFIG_SOC_SERIES_ESP32) uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG); uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG); diff --git a/drivers/hwinfo/hwinfo_native.c b/drivers/hwinfo/hwinfo_native.c new file mode 100644 index 0000000000000..2e02c9cceb7ee --- /dev/null +++ b/drivers/hwinfo/hwinfo_native.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2025 Henrik Brix Andersen + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include "hwinfo_native_bottom.h" + +static uint32_t native_hwinfo_device_id; +static bool native_hwinfo_device_id_set; + +ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) +{ + + if (length > sizeof(native_hwinfo_device_id)) { + length = sizeof(native_hwinfo_device_id); + } + + sys_put_be(buffer, &native_hwinfo_device_id, length); + + return length; +} + +static void native_hwinfo_gethostid(void) +{ + if (!native_hwinfo_device_id_set) { + native_hwinfo_device_id = native_hwinfo_gethostid_bottom(); + } +} + +static void native_hwinfo_device_id_was_set(char *argv, int offset) +{ + ARG_UNUSED(argv); + ARG_UNUSED(offset); + + native_hwinfo_device_id_set = true; +} + +static void native_hwinfo_add_options(void) +{ + static struct args_struct_t native_hwinfo_options[] = { + { + .option = "device_id", + .name = "id", + .type = 'u', + .dest = (void *)&native_hwinfo_device_id, + .call_when_found = native_hwinfo_device_id_was_set, + .descript = "A 32-bit integer value to use as HWINFO device ID. " + "If not set, the host gethostid() output will be used.", + }, + ARG_TABLE_ENDMARKER, + }; + + native_add_command_line_opts(native_hwinfo_options); +} + +NATIVE_TASK(native_hwinfo_add_options, PRE_BOOT_1, 10); +NATIVE_TASK(native_hwinfo_gethostid, PRE_BOOT_2, 10); diff --git a/drivers/hwinfo/hwinfo_native_bottom.c b/drivers/hwinfo/hwinfo_native_bottom.c new file mode 100644 index 0000000000000..a3401f4607824 --- /dev/null +++ b/drivers/hwinfo/hwinfo_native_bottom.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Henrik Brix Andersen + * SPDX-License-Identifier: Apache-2.0 + */ + +#undef _XOPEN_SOURCE +#define _XOPEN_SOURCE 500 + +#include + +#include "hwinfo_native_bottom.h" + +long native_hwinfo_gethostid_bottom(void) +{ + return gethostid(); +} diff --git a/drivers/hwinfo/hwinfo_native_bottom.h b/drivers/hwinfo/hwinfo_native_bottom.h new file mode 100644 index 0000000000000..8d09e8418a91a --- /dev/null +++ b/drivers/hwinfo/hwinfo_native_bottom.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Henrik Brix Andersen + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef DRIVERS_HWINFO_NATIVE_BOTTOM_H +#define DRIVERS_HWINFO_NATIVE_BOTTOM_H + +long native_hwinfo_gethostid_bottom(void); + +#endif /* DRIVERS_HWINFO_NATIVE_BOTTOM_H */ diff --git a/drivers/i2c/CMakeLists.txt b/drivers/i2c/CMakeLists.txt index f8c1c31d7167d..df5652a379517 100644 --- a/drivers/i2c/CMakeLists.txt +++ b/drivers/i2c/CMakeLists.txt @@ -57,6 +57,7 @@ zephyr_library_sources_ifdef(CONFIG_I2C_RCAR i2c_rcar.c) zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RA_IIC i2c_renesas_ra_iic.c) zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RA_SCI_B i2c_renesas_ra_sci_b.c) zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RX_RIIC i2c_renesas_rx_riic.c) +zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RZ_IIC i2c_renesas_rz_riic.c) zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RZ_RIIC i2c_renesas_rz_riic.c) zephyr_library_sources_ifdef(CONFIG_I2C_RTS5912 i2c_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_I2C_RV32M1_LPI2C i2c_rv32m1_lpi2c.c) @@ -67,6 +68,7 @@ zephyr_library_sources_ifdef(CONFIG_I2C_SBCON i2c_sbcon.c) zephyr_library_sources_ifdef(CONFIG_I2C_SC18IM704 i2c_sc18im704.c) zephyr_library_sources_ifdef(CONFIG_I2C_SEDI i2c_sedi.c) zephyr_library_sources_ifdef(CONFIG_I2C_SIFIVE i2c_sifive.c) +zephyr_library_sources_ifdef(CONFIG_I2C_SILABS i2c_silabs.c) zephyr_library_sources_ifdef(CONFIG_I2C_SMARTBOND i2c_smartbond.c) zephyr_library_sources_ifdef(CONFIG_I2C_SY1XX i2c_sy1xx.c) zephyr_library_sources_ifdef(CONFIG_I2C_TCA954X i2c_tca954x.c) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index c25954fc7d6b1..5e276ca235dfe 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -154,6 +154,7 @@ source "drivers/i2c/Kconfig.sbcon" source "drivers/i2c/Kconfig.sc18im704" source "drivers/i2c/Kconfig.sedi" source "drivers/i2c/Kconfig.sifive" +source "drivers/i2c/Kconfig.silabs" source "drivers/i2c/Kconfig.smartbond" source "drivers/i2c/Kconfig.stm32" source "drivers/i2c/Kconfig.sy1xx" diff --git a/drivers/i2c/Kconfig.renesas_rz b/drivers/i2c/Kconfig.renesas_rz index 16ebd19c54ece..5d82311c9a6c2 100644 --- a/drivers/i2c/Kconfig.renesas_rz +++ b/drivers/i2c/Kconfig.renesas_rz @@ -1,4 +1,4 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 config I2C_RENESAS_RZ_RIIC @@ -6,5 +6,15 @@ config I2C_RENESAS_RZ_RIIC default y depends on DT_HAS_RENESAS_RZ_RIIC_ENABLED select USE_RZ_FSP_RIIC_MASTER + select PINCTRL help Enable Renesas RZ I2C RIIC Driver. + +config I2C_RENESAS_RZ_IIC + bool "Renesas RZ I2C IIC Master" + default y + depends on DT_HAS_RENESAS_RZ_IIC_ENABLED + select USE_RZ_FSP_IIC_MASTER + select PINCTRL + help + Enable Renesas RZ I2C IIC Driver. diff --git a/drivers/i2c/Kconfig.silabs b/drivers/i2c/Kconfig.silabs new file mode 100644 index 0000000000000..4504456ee5fda --- /dev/null +++ b/drivers/i2c/Kconfig.silabs @@ -0,0 +1,26 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +menuconfig I2C_SILABS + bool "Silabs I2C_S2 driver" + default y + depends on DT_HAS_SILABS_I2C_ENABLED + select SILABS_SISDK_I2C + help + Enable I2C series 2 driver for the Silabs gecko SoC series. +if I2C_SILABS + +config I2C_SILABS_DMA + bool "DMA support for I2C operations" + depends on DMA + default y if $(dt_compat_any_has_prop,$(DT_COMPAT_SILABS_I2C),dmas) + help + Enable DMA mode for I2C DMA transfer. + +config I2C_SILABS_TIMEOUT + int "I2C operation timeout (milliseconds)" + default 1000 + help + Specify the timeout value in milliseconds for I2C transfer. + +endif # I2C_SILABS diff --git a/drivers/i2c/i2c_ll_stm32_rtio.c b/drivers/i2c/i2c_ll_stm32_rtio.c index 6b150c1d5619b..d42c20fc9ded7 100644 --- a/drivers/i2c/i2c_ll_stm32_rtio.c +++ b/drivers/i2c/i2c_ll_stm32_rtio.c @@ -269,9 +269,7 @@ static int i2c_stm32_init(const struct device *dev) return ret; } -#ifdef CONFIG_PM_DEVICE_RUNTIME (void)pm_device_runtime_enable(dev); -#endif return 0; } diff --git a/drivers/i2c/i2c_ll_stm32_v2_rtio.c b/drivers/i2c/i2c_ll_stm32_v2_rtio.c index 3bb4614b56d3c..269288055ece8 100644 --- a/drivers/i2c/i2c_ll_stm32_v2_rtio.c +++ b/drivers/i2c/i2c_ll_stm32_v2_rtio.c @@ -209,15 +209,16 @@ int i2c_stm32_target_register(const struct device *dev, return ret; } -#if defined(CONFIG_PM_DEVICE_RUNTIME) + /* Mark device as active */ + (void)pm_device_runtime_get(dev); + +#if !defined(CONFIG_SOC_SERIES_STM32F7X) if (pm_device_wakeup_is_capable(dev)) { - /* Mark device as active */ - (void)pm_device_runtime_get(dev); /* Enable wake-up from stop */ LOG_DBG("i2c: enabling wakeup from stop"); LL_I2C_EnableWakeUpFromStop(cfg->i2c); } -#endif /* defined(CONFIG_PM_DEVICE_RUNTIME) */ +#endif /* !CONFIG_SOC_SERIES_STM32F7X */ LL_I2C_Enable(i2c); @@ -298,15 +299,16 @@ int i2c_stm32_target_unregister(const struct device *dev, LL_I2C_Disable(i2c); -#if defined(CONFIG_PM_DEVICE_RUNTIME) +#if !defined(CONFIG_SOC_SERIES_STM32F7X) if (pm_device_wakeup_is_capable(dev)) { /* Disable wake-up from STOP */ LOG_DBG("i2c: disabling wakeup from stop"); LL_I2C_DisableWakeUpFromStop(i2c); - /* Release the device */ - (void)pm_device_runtime_put(dev); } -#endif /* defined(CONFIG_PM_DEVICE_RUNTIME) */ +#endif /* !CONFIG_SOC_SERIES_STM32F7X */ + + /* Release the device */ + (void)pm_device_runtime_put(dev); data->slave_attached = false; diff --git a/drivers/i2c/i2c_renesas_rz_riic.c b/drivers/i2c/i2c_renesas_rz_riic.c index 951a552e2d503..3669e06768ab2 100644 --- a/drivers/i2c/i2c_renesas_rz_riic.c +++ b/drivers/i2c/i2c_renesas_rz_riic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,25 +9,33 @@ #include #include #include -#include + +#if defined(CONFIG_I2C_RENESAS_RZ_RIIC) +#include "r_riic_master.h" +#else /* CONFIG_I2C_RENESAS_RZ_IIC */ +#include "r_iic_master.h" +typedef iic_master_extended_cfg_t riic_master_extended_cfg_t; +#define FSP_PRIV_CLOCK_P0CLK FSP_PRIV_CLOCK_PCLKL +#endif #include LOG_MODULE_REGISTER(renesas_rz_riic); -typedef void (*init_func_t)(const struct device *dev); +#define RZ_RIIC_MASTER_DIV_TIME_NS (1000000000.0) struct i2c_rz_riic_config { const struct pinctrl_dev_config *pin_config; - i2c_master_cfg_t *fsp_cfg; - riic_master_extended_cfg_t *riic_master_ext_cfg; const i2c_master_api_t *fsp_api; double rise_time_s; double fall_time_s; double duty_cycle_percent; + uint32_t noise_filter_stage; }; struct i2c_rz_riic_data { i2c_master_ctrl_t *fsp_ctrl; + i2c_master_cfg_t *fsp_cfg; + riic_master_extended_cfg_t *riic_master_ext_cfg; struct k_mutex bus_mutex; struct k_sem complete_sem; i2c_master_event_t event; @@ -38,15 +46,79 @@ struct i2c_rz_riic_data { static void calc_riic_master_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate, iic_master_clock_settings_t *clk_cfg); +#if defined(CONFIG_I2C_RENESAS_RZ_RIIC) /* FSP interruption handlers. */ -void riic_master_rxi_isr(void); -void riic_master_txi_isr(void); -void riic_master_tei_isr(void); -void riic_master_naki_isr(void); -void riic_master_sti_isr(void); -void riic_master_spi_isr(void); -void riic_master_ali_isr(void); -void riic_master_tmoi_isr(void); +void riic_master_rxi_isr(void *irq); +void riic_master_txi_isr(void *irq); +void riic_master_tei_isr(void *irq); +void riic_master_naki_isr(void *irq); +void riic_master_sti_isr(void *irq); +void riic_master_spi_isr(void *irq); +void riic_master_ali_isr(void *irq); +void riic_master_tmoi_isr(void *irq); + +static void i2c_rz_riic_master_rxi_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_rxi_isr((void *)data->fsp_cfg->rxi_irq); +} + +static void i2c_rz_riic_master_txi_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_txi_isr((void *)data->fsp_cfg->txi_irq); +} + +static void i2c_rz_riic_master_tei_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_tei_isr((void *)data->fsp_cfg->tei_irq); +} + +static void i2c_rz_riic_master_naki_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_naki_isr((void *)data->riic_master_ext_cfg->naki_irq); +} + +static void i2c_rz_riic_master_sti_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_sti_isr((void *)data->riic_master_ext_cfg->sti_irq); +} + +static void i2c_rz_riic_master_spi_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_spi_isr((void *)data->riic_master_ext_cfg->spi_irq); +} + +static void i2c_rz_riic_master_ali_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_ali_isr((void *)data->riic_master_ext_cfg->ali_irq); +} + +static void i2c_rz_riic_master_tmoi_isr(const struct device *dev) +{ + struct i2c_rz_riic_data *data = dev->data; + + riic_master_tmoi_isr((void *)data->riic_master_ext_cfg->tmoi_irq); +} + +#elif defined(CONFIG_I2C_RENESAS_RZ_IIC) +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); +#endif struct rz_riic_master_bitrate { uint32_t bitrate; @@ -61,6 +133,7 @@ static int i2c_rz_riic_configure(const struct device *dev, uint32_t dev_config) { const struct i2c_rz_riic_config *config = dev->config; struct i2c_rz_riic_data *data = dev->data; + fsp_err_t err; if (!(dev_config & I2C_MODE_CONTROLLER)) { LOG_ERR("Only I2C Master mode supported."); @@ -69,13 +142,13 @@ static int i2c_rz_riic_configure(const struct device *dev, uint32_t dev_config) switch (I2C_SPEED_GET(dev_config)) { case I2C_SPEED_STANDARD: - config->fsp_cfg->rate = I2C_MASTER_RATE_STANDARD; + data->fsp_cfg->rate = I2C_MASTER_RATE_STANDARD; break; case I2C_SPEED_FAST: - config->fsp_cfg->rate = I2C_MASTER_RATE_FAST; + data->fsp_cfg->rate = I2C_MASTER_RATE_FAST; break; case I2C_SPEED_FAST_PLUS: - config->fsp_cfg->rate = I2C_MASTER_RATE_FASTPLUS; + data->fsp_cfg->rate = I2C_MASTER_RATE_FASTPLUS; break; default: LOG_ERR("%s: Invalid I2C speed rate flag: %d", __func__, I2C_SPEED_GET(dev_config)); @@ -83,11 +156,20 @@ static int i2c_rz_riic_configure(const struct device *dev, uint32_t dev_config) } /* Recalc clock setting after updating config. */ - calc_riic_master_clock_setting(dev, config->fsp_cfg->rate, - &config->riic_master_ext_cfg->clock_settings); + calc_riic_master_clock_setting(dev, data->fsp_cfg->rate, + &data->riic_master_ext_cfg->clock_settings); - config->fsp_api->close(data->fsp_ctrl); - config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg); + err = config->fsp_api->close(data->fsp_ctrl); + if (err != FSP_SUCCESS) { + LOG_ERR("Failed to configure I2C device"); + return -EIO; + } + + err = config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg); + if (err != FSP_SUCCESS) { + LOG_ERR("Failed to configure I2C device"); + return -EIO; + } /* save current devconfig. */ data->dev_config = dev_config; @@ -111,7 +193,7 @@ static int i2c_rz_riic_transfer(const struct device *dev, struct i2c_msg *msgs, const struct i2c_rz_riic_config *config = dev->config; struct i2c_rz_riic_data *data = (struct i2c_rz_riic_data *const)dev->data; struct i2c_msg *current, *next; - fsp_err_t err = FSP_SUCCESS; + fsp_err_t err; int ret = 0; if (!num_msgs) { @@ -178,7 +260,11 @@ static int i2c_rz_riic_transfer(const struct device *dev, struct i2c_msg *msgs, addr_mode = I2C_MASTER_ADDR_MODE_7BIT; } - config->fsp_api->slaveAddressSet(data->fsp_ctrl, addr, addr_mode); + err = config->fsp_api->slaveAddressSet(data->fsp_ctrl, addr, addr_mode); + if (err != FSP_SUCCESS) { + LOG_ERR("Failed to set slave address"); + return -EIO; + } /* Process input `msgs`. */ @@ -259,7 +345,7 @@ static int i2c_rz_riic_init(const struct device *dev) { const struct i2c_rz_riic_config *config = dev->config; struct i2c_rz_riic_data *data = dev->data; - fsp_err_t err = FSP_SUCCESS; + fsp_err_t err; int ret = 0; /* Configure dt provided device signals when available */ @@ -275,21 +361,21 @@ static int i2c_rz_riic_init(const struct device *dev) k_mutex_init(&data->bus_mutex); k_sem_init(&data->complete_sem, 0, 1); - switch (config->fsp_cfg->rate) { + switch (data->fsp_cfg->rate) { case I2C_MASTER_RATE_STANDARD: case I2C_MASTER_RATE_FAST: case I2C_MASTER_RATE_FASTPLUS: - calc_riic_master_clock_setting(dev, config->fsp_cfg->rate, - &config->riic_master_ext_cfg->clock_settings); - config->riic_master_ext_cfg->timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT; - config->riic_master_ext_cfg->timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED; + calc_riic_master_clock_setting(dev, data->fsp_cfg->rate, + &data->riic_master_ext_cfg->clock_settings); + data->riic_master_ext_cfg->timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT; + data->riic_master_ext_cfg->timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED; break; default: - LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, config->fsp_cfg->rate); + LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, data->fsp_cfg->rate); return -ENOTSUP; } - err = config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg); + err = config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg); if (err != FSP_SUCCESS) { LOG_ERR("I2C initialization failed"); @@ -303,7 +389,7 @@ static void calc_riic_master_bitrate(const struct i2c_rz_riic_config *config, uint32_t total_brl_brh, uint32_t brh, uint32_t divider, struct rz_riic_master_bitrate *result) { - const uint32_t noise_filter_stages = config->riic_master_ext_cfg->noise_filter_stage; + const uint32_t noise_filter_stages = config->noise_filter_stage; const double rise_time_s = config->rise_time_s; const double fall_time_s = config->fall_time_s; const double requested_duty = config->duty_cycle_percent; @@ -342,7 +428,7 @@ static void calc_riic_master_clock_setting(const struct device *dev, const uint3 iic_master_clock_settings_t *clk_cfg) { const struct i2c_rz_riic_config *config = dev->config; - const uint32_t noise_filter_stages = config->riic_master_ext_cfg->noise_filter_stage; + const uint32_t noise_filter_stages = config->noise_filter_stage; const double rise_time_s = config->rise_time_s; const double fall_time_s = config->fall_time_s; const uint32_t requested_duty = config->duty_cycle_percent; @@ -461,27 +547,32 @@ static DEVICE_API(i2c, i2c_rz_riic_driver_api) = { .transfer = i2c_rz_riic_transfer, }; -#define I2C_RZG_IRQ_CONNECT(index, irq_name, isr) \ +#ifdef CONFIG_CPU_CORTEX_M +#define GET_IRQ_FLAGS(index, irq_name) 0 +#else /* Cortex-A/R */ +#define GET_IRQ_FLAGS(index, irq_name) DT_INST_IRQ_BY_NAME(index, irq_name, flags) +#endif + +#define I2C_RZ_IRQ_CONNECT(index, irq_name, isr) \ do { \ IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, irq_name, irq), \ DT_INST_IRQ_BY_NAME(index, irq_name, priority), isr, \ - DEVICE_DT_INST_GET(index), 0); \ + DEVICE_DT_INST_GET(index), GET_IRQ_FLAGS(index, irq_name)); \ irq_enable(DT_INST_IRQ_BY_NAME(index, irq_name, irq)); \ } while (0) -#define I2C_RZG_CONFIG_FUNC(index) \ - I2C_RZG_IRQ_CONNECT(index, rxi, riic_master_rxi_isr); \ - I2C_RZG_IRQ_CONNECT(index, txi, riic_master_txi_isr); \ - I2C_RZG_IRQ_CONNECT(index, tei, riic_master_tei_isr); \ - I2C_RZG_IRQ_CONNECT(index, naki, riic_master_naki_isr); \ - I2C_RZG_IRQ_CONNECT(index, sti, riic_master_sti_isr); \ - I2C_RZG_IRQ_CONNECT(index, spi, riic_master_spi_isr); \ - I2C_RZG_IRQ_CONNECT(index, ali, riic_master_ali_isr); \ - I2C_RZG_IRQ_CONNECT(index, tmoi, riic_master_tmoi_isr); - -#define I2C_RZG_RIIC_INIT(index) \ - static const double RZG_RIIC_MASTER_DIV_TIME_NS = 1000000000; \ - \ +#if defined(CONFIG_I2C_RENESAS_RZ_RIIC) +#define I2C_RZ_CONFIG_FUNC(index) \ + I2C_RZ_IRQ_CONNECT(index, rxi, i2c_rz_riic_master_rxi_isr); \ + I2C_RZ_IRQ_CONNECT(index, txi, i2c_rz_riic_master_txi_isr); \ + I2C_RZ_IRQ_CONNECT(index, tei, i2c_rz_riic_master_tei_isr); \ + I2C_RZ_IRQ_CONNECT(index, naki, i2c_rz_riic_master_naki_isr); \ + I2C_RZ_IRQ_CONNECT(index, sti, i2c_rz_riic_master_sti_isr); \ + I2C_RZ_IRQ_CONNECT(index, spi, i2c_rz_riic_master_spi_isr); \ + I2C_RZ_IRQ_CONNECT(index, ali, i2c_rz_riic_master_ali_isr); \ + I2C_RZ_IRQ_CONNECT(index, tmoi, i2c_rz_riic_master_tmoi_isr); + +#define I2C_RZ_EXTENDED_CFG(index) \ static riic_master_extended_cfg_t g_i2c_master##index##_extend = { \ .noise_filter_stage = DT_INST_PROP(index, noise_filter_stages), \ .naki_irq = DT_INST_IRQ_BY_NAME(index, naki, irq), \ @@ -489,7 +580,23 @@ static DEVICE_API(i2c, i2c_rz_riic_driver_api) = { .spi_irq = DT_INST_IRQ_BY_NAME(index, spi, irq), \ .ali_irq = DT_INST_IRQ_BY_NAME(index, ali, irq), \ .tmoi_irq = DT_INST_IRQ_BY_NAME(index, tmoi, irq), \ - }; \ + }; +#endif /* CONFIG_I2C_RENESAS_RZ_RIIC */ + +#if defined(CONFIG_I2C_RENESAS_RZ_IIC) +#define I2C_RZ_CONFIG_FUNC(index) \ + I2C_RZ_IRQ_CONNECT(index, eri, iic_master_eri_isr); \ + I2C_RZ_IRQ_CONNECT(index, rxi, iic_master_rxi_isr); \ + I2C_RZ_IRQ_CONNECT(index, txi, iic_master_txi_isr); \ + I2C_RZ_IRQ_CONNECT(index, tei, iic_master_tei_isr); + +#define I2C_RZ_EXTENDED_CFG(index) \ + static riic_master_extended_cfg_t g_i2c_master##index##_extend = {}; +#endif /* CONFIG_I2C_RENESAS_RZ_IIC */ + +#define I2C_RZ_RIIC_INIT(index) \ + \ + I2C_RZ_EXTENDED_CFG(index) \ \ static i2c_master_cfg_t g_i2c_master##index##_cfg = { \ .channel = DT_INST_PROP(index, channel), \ @@ -505,29 +612,31 @@ static DEVICE_API(i2c, i2c_rz_riic_driver_api) = { .tei_irq = DT_INST_IRQ_BY_NAME(index, tei, irq), \ .ipl = DT_INST_IRQ_BY_NAME(index, rxi, priority), \ .p_extend = &g_i2c_master##index##_extend, \ - }; \ + IF_ENABLED(CONFIG_I2C_RENESAS_RZ_IIC, \ + (.eri_irq = DT_INST_IRQ_BY_NAME(index, eri, irq),))}; \ \ PINCTRL_DT_INST_DEFINE(index); \ \ - static struct i2c_rz_riic_config i2c_rz_riic_config_##index = { \ + static const struct i2c_rz_riic_config i2c_rz_riic_config_##index = { \ .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ - .fsp_cfg = &g_i2c_master##index##_cfg, \ - .riic_master_ext_cfg = &g_i2c_master##index##_extend, \ .fsp_api = &g_i2c_master_on_iic, \ - .rise_time_s = DT_INST_PROP(index, rise_time_ns) / RZG_RIIC_MASTER_DIV_TIME_NS, \ - .fall_time_s = DT_INST_PROP(index, fall_time_ns) / RZG_RIIC_MASTER_DIV_TIME_NS, \ + .rise_time_s = DT_INST_PROP(index, rise_time_ns) / RZ_RIIC_MASTER_DIV_TIME_NS, \ + .fall_time_s = DT_INST_PROP(index, fall_time_ns) / RZ_RIIC_MASTER_DIV_TIME_NS, \ .duty_cycle_percent = DT_INST_PROP(index, duty_cycle_percent), \ + .noise_filter_stage = DT_INST_PROP(index, noise_filter_stages), \ }; \ \ static iic_master_instance_ctrl_t g_i2c_master##index##_ctrl; \ \ static struct i2c_rz_riic_data i2c_rz_riic_data_##index = { \ .fsp_ctrl = (i2c_master_ctrl_t *)&g_i2c_master##index##_ctrl, \ + .fsp_cfg = &g_i2c_master##index##_cfg, \ + .riic_master_ext_cfg = &g_i2c_master##index##_extend, \ }; \ \ static int i2c_rz_riic_init_##index(const struct device *dev) \ { \ - I2C_RZG_CONFIG_FUNC(index) \ + I2C_RZ_CONFIG_FUNC(index) \ return i2c_rz_riic_init(dev); \ }; \ \ @@ -536,4 +645,9 @@ static DEVICE_API(i2c, i2c_rz_riic_driver_api) = { PRE_KERNEL_2, CONFIG_I2C_INIT_PRIORITY, \ &i2c_rz_riic_driver_api); -DT_INST_FOREACH_STATUS_OKAY(I2C_RZG_RIIC_INIT) +DT_INST_FOREACH_STATUS_OKAY(I2C_RZ_RIIC_INIT) + +#undef DT_DRV_COMPAT +#define DT_DRV_COMPAT renesas_rz_iic + +DT_INST_FOREACH_STATUS_OKAY(I2C_RZ_RIIC_INIT) diff --git a/drivers/i2c/i2c_silabs.c b/drivers/i2c/i2c_silabs.c new file mode 100644 index 0000000000000..eb302310d3d26 --- /dev/null +++ b/drivers/i2c/i2c_silabs.c @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT silabs_i2c + +#include +#include +#include +#include +#if defined(CONFIG_I2C_SILABS_DMA) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL +LOG_MODULE_REGISTER(silabs); +#include "i2c-priv.h" + +/* Structure for DMA configuration */ +struct i2c_silabs_dma_config { + const struct device *dma_dev; /* Pointer to the DMA device structure */ + int dma_channel; /* DMA channel number */ +}; + +/* Structure for I2C device configuration */ +struct i2c_silabs_dev_config { + const struct pinctrl_dev_config *pcfg; /* Pin configuration for the I2C instance */ + I2C_TypeDef *base; /* I2C peripheral base address */ + uint32_t bitrate; /* I2C bitrate (clock frequency) */ + void (*irq_config_func)(void); /* IRQ configuration function */ + const struct device *clock; /* Clock device */ + const struct silabs_clock_control_cmu_config clock_cfg; /* Clock control subsystem */ +}; + +/* Structure for I2C device data */ +struct i2c_silabs_dev_data { + struct k_sem bus_lock; /* Semaphore to lock the I2C bus */ + struct k_sem transfer_sem; /* Semaphore to manage transfer */ + sli_i2c_instance_t i2c_instance; /* I2C instance structure */ + struct i2c_silabs_dma_config dma_rx; /* DMA configuration for RX */ + struct i2c_silabs_dma_config dma_tx; /* DMA configuration for TX */ + bool asynchronous; /* Indicates if transfer is asynchronous */ + bool last_transfer; /* Transfer is the last in the sequence */ +#if defined CONFIG_I2C_CALLBACK + i2c_callback_t callback; /* I2C callback function pointer */ + void *callback_context; /* Context for I2C callback */ + bool callback_invoked; /* Tracks if callback has been invoked */ +#endif + bool pm_lock_done; /* Tracks if PM lock release has occurred */ +}; + +static int i2c_silabs_pm_action(const struct device *dev, enum pm_device_action action); + +static bool i2c_silabs_is_dma_enabled_instance(const struct device *dev) +{ +#ifdef CONFIG_I2C_SILABS_DMA + struct i2c_silabs_dev_data *data = dev->data; + + __ASSERT_NO_MSG(!!data->dma_tx.dma_dev == !!data->dma_rx.dma_dev); + + return data->dma_rx.dma_dev != NULL; +#else + return false; +#endif +} + +static void i2c_silabs_pm_policy_state_lock_get(const struct device *dev) +{ + pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); + pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); +} + +static void i2c_silabs_pm_policy_state_lock_put(const struct device *dev) +{ + pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); + pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); +} + +/* Function to configure I2C peripheral */ +static int i2c_silabs_dev_configure(const struct device *dev, uint32_t dev_config) +{ + const struct i2c_silabs_dev_config *config = dev->config; + struct i2c_silabs_dev_data *data = dev->data; + sl_i2c_init_params_t init_params; + + /* Determine the I2C speed and corresponding baudrate */ + switch (I2C_SPEED_GET(dev_config)) { + case I2C_SPEED_STANDARD: + init_params.freq_mode = SL_I2C_FREQ_STANDARD_MODE; + break; + case I2C_SPEED_FAST: + init_params.freq_mode = SL_I2C_FREQ_FAST_MODE; + break; + case I2C_SPEED_FAST_PLUS: + init_params.freq_mode = SL_I2C_FREQ_FASTPLUS_MODE; + break; + default: + return -EINVAL; + } + + /* Take the bus lock semaphore to ensure exclusive access */ + k_sem_take(&data->bus_lock, K_FOREVER); + /* Initialize I2C parameters */ + init_params.i2c_base_addr = config->base; + data->i2c_instance.i2c_base_addr = init_params.i2c_base_addr; + + /* Set the operating mode (leader or follower) */ +#if defined(CONFIG_I2C_TARGET) + init_params.operating_mode = SL_I2C_FOLLOWER_MODE; +#else + init_params.operating_mode = SL_I2C_LEADER_MODE; +#endif /* CONFIG_I2C_TARGET */ + data->i2c_instance.operating_mode = init_params.operating_mode; + + /* Configure the I2C instance */ + sli_i2c_instance_configuration(&init_params); + + /* Release the bus lock semaphore */ + k_sem_give(&data->bus_lock); + + return 0; +} + +/* Function to handle DMA transfer */ +static int i2c_silabs_transfer_dma(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs, + uint16_t addr, i2c_callback_t cb, void *userdata, + bool asynchronous) +{ +#if defined(CONFIG_I2C_SILABS_DMA) + struct i2c_silabs_dev_data *data = dev->data; + __maybe_unused const struct i2c_silabs_dev_config *config = dev->config; + sl_i2c_handle_t *i2c_handle = (sl_i2c_handle_t *)&data->i2c_instance; +#if defined(CONFIG_I2C_CALLBACK) + data->callback_invoked = false; +#endif + data->pm_lock_done = false; + uint8_t i = 0; + int err = 0; + + /* Get the power management policy state lock */ + i2c_silabs_pm_policy_state_lock_get(dev); + +#if defined(CONFIG_I2C_TARGET) + /* Set follower address in target mode */ + sli_i2c_set_follower_address(config->base, addr, data->i2c_instance.is_10bit_addr); +#endif /* CONFIG_I2C_TARGET */ + + while (i < num_msgs) { + uint8_t msgs_in_transfer = 1; + + /* Combined DMA write-read (repeated start) */ + if ((msgs[i].flags & I2C_MSG_WRITE) == 0 && (i + 1 < num_msgs) && + (msgs[i + 1].flags & I2C_MSG_READ)) { + msgs_in_transfer = 2; + } + data->last_transfer = (i + msgs_in_transfer) == num_msgs; + + if (msgs_in_transfer == 2) { + if (sl_i2c_transfer_non_blocking(i2c_handle, msgs[i].buf, msgs[i].len, + msgs[i + 1].buf, msgs[i + 1].len, NULL, + NULL) != 0) { + k_sem_give(&data->bus_lock); + return -EIO; + } + } else if (msgs[i].flags & I2C_MSG_READ) { + /* Start DMA receive */ + if (sl_i2c_receive_non_blocking(i2c_handle, msgs[i].buf, msgs[i].len, NULL, + NULL) != 0) { + k_sem_give(&data->bus_lock); + return -EIO; + } + } else { + /* Start DMA send */ + if (sl_i2c_send_non_blocking(i2c_handle, msgs[i].buf, msgs[i].len, NULL, + NULL) != 0) { + k_sem_give(&data->bus_lock); + return -EIO; + } + } + if (!asynchronous) { + /* Wait for DMA transfer to complete */ + if (k_sem_take(&data->transfer_sem, K_MSEC(CONFIG_I2C_SILABS_TIMEOUT))) { + err = -ETIMEDOUT; + } + if (data->i2c_instance.state == SLI_I2C_STATE_ERROR) { + err = -EIO; + } + k_sem_reset(&data->transfer_sem); + if (err < 0) { + break; + } + } + i += msgs_in_transfer; + } + + return err; +#else + return -ENOTSUP; +#endif /* CONFIG_I2C_SILABS_DMA */ +} + +/* Function to handle synchronous transfer */ +static int i2c_silabs_transfer_sync(const struct device *dev, struct i2c_msg *msgs, + uint8_t num_msgs, uint16_t addr) +{ + struct i2c_silabs_dev_data *data = dev->data; + sl_i2c_handle_t *i2c_handle = (sl_i2c_handle_t *)&data->i2c_instance; + uint8_t i = 0; + + /* Get the power management policy state lock */ + i2c_silabs_pm_policy_state_lock_get(dev); + + while (i < num_msgs) { + uint8_t msgs_in_transfer = 1; + + if ((msgs[i].flags & I2C_MSG_WRITE) == 0 && (i + 1 < num_msgs) && + (msgs[i + 1].flags & I2C_MSG_READ)) { + msgs_in_transfer = 2; + if (sl_i2c_transfer(i2c_handle, msgs[i].buf, msgs[i].len, msgs[i + 1].buf, + msgs[i + 1].len) != 0) { + k_sem_give(&data->bus_lock); + return -EIO; + } + i++; + } else if (msgs[i].flags & I2C_MSG_READ) { + if (sl_i2c_receive_blocking(i2c_handle, msgs[i].buf, msgs[i].len, + CONFIG_I2C_SILABS_TIMEOUT) != 0) { + k_sem_give(&data->bus_lock); + return -ETIMEDOUT; + } + } else { + if (sl_i2c_send_blocking(i2c_handle, msgs[i].buf, msgs[i].len, + CONFIG_I2C_SILABS_TIMEOUT) != 0) { + k_sem_give(&data->bus_lock); + return -ETIMEDOUT; + } + } + i += msgs_in_transfer; + } + + /* Release the bus lock semaphore */ + k_sem_give(&data->bus_lock); + + /* Release the power management policy state lock */ + i2c_silabs_pm_policy_state_lock_put(dev); + + return 0; +} + +/* Function to perform I2C transfer */ +static int i2c_silabs_transfer_impl(const struct device *dev, struct i2c_msg *msgs, + uint8_t num_msgs, uint16_t addr, i2c_callback_t cb, + void *userdata) +{ + struct i2c_silabs_dev_data *data = dev->data; + __maybe_unused const struct i2c_silabs_dev_config *config = dev->config; + sl_i2c_handle_t *i2c_handle = (sl_i2c_handle_t *)&data->i2c_instance; + int ret = -EINVAL; /* Initialize ret to a default error value */ + + /* Check for invalid number of messages */ + if (!num_msgs) { + return -EINVAL; + } + + /* Check and set the address mode (7-bit or 10-bit) based on */ + /* the provided address */ + if (addr <= 0x7F) { + data->i2c_instance.is_10bit_addr = false; /* 7-bit address */ + } else if (addr <= 0x3FF) { + data->i2c_instance.is_10bit_addr = true; /* 10-bit address */ + } else { + return -EINVAL; + } + + /* Take the bus lock semaphore to ensure exclusive access */ + ret = k_sem_take(&data->bus_lock, data->asynchronous ? K_NO_WAIT : K_FOREVER); + if (ret != 0) { + if (data->asynchronous && ret == -EBUSY) { + return -EWOULDBLOCK; + } + return ret; + } + + /* Set the follower address */ + if (sl_i2c_set_follower_address(i2c_handle, addr) != 0) { + k_sem_give(&data->bus_lock); + return -EINVAL; + } + + if (i2c_silabs_is_dma_enabled_instance(dev)) { + /* DMA transfer handle a/synchronous transfers */ + ret = i2c_silabs_transfer_dma(dev, msgs, num_msgs, addr, cb, userdata, + data->asynchronous); + + } else if (!data->asynchronous) { + /* Polling transfer for synchronous transfers */ + ret = i2c_silabs_transfer_sync(dev, msgs, num_msgs, addr); + + } else { + /* Asynchronous transfers without DMA is not implemented, + * please configure the device tree instance with the proper DMA configuration. + */ + ret = -ENOTSUP; + /* Release the bus lock semaphore */ + k_sem_give(&data->bus_lock); + } + + return ret; +} + +/* Blocking I2C transfer function */ +static int i2c_silabs_dev_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs, + uint16_t addr) +{ + struct i2c_silabs_dev_data *data = dev->data; + + data->asynchronous = false; + return i2c_silabs_transfer_impl(dev, msgs, num_msgs, addr, NULL, NULL); +} + +#if defined(CONFIG_I2C_CALLBACK) +/* Non-blocking I2C transfer function with callback */ +static int i2c_silabs_dev_transfer_cb(const struct device *dev, struct i2c_msg *msgs, + uint8_t num_msgs, uint16_t addr, i2c_callback_t cb, + void *userdata) +{ + struct i2c_silabs_dev_data *data = dev->data; + + data->asynchronous = true; + /* Store the callback and context in the data structure */ + data->callback = cb; + data->callback_context = userdata; + return i2c_silabs_transfer_impl(dev, msgs, num_msgs, addr, cb, userdata); +} +#endif /* CONFIG_I2C_CALLBACK */ + +/* Function to initialize the I2C peripheral */ +static int i2c_silabs_dev_init(const struct device *dev) +{ + __maybe_unused struct i2c_silabs_dev_data *data = dev->data; + const struct i2c_silabs_dev_config *config = dev->config; + uint32_t bitrate_cfg; + int ret; + + /* Enable clock */ + ret = clock_control_on(config->clock, (clock_control_subsys_t)&config->clock_cfg); + if (ret < 0) { + return ret; + } + + /* Apply default pin configuration */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + /* Map the bitrate configuration from device tree */ + bitrate_cfg = i2c_map_dt_bitrate(config->bitrate); + + /* Configure the I2C device with the mapped bitrate configuration */ + if (i2c_silabs_dev_configure(dev, bitrate_cfg) != 0) { + return -EINVAL; + } + +#if defined(CONFIG_I2C_SILABS_DMA) + if (i2c_silabs_is_dma_enabled_instance(dev)) { + if (!device_is_ready(data->dma_rx.dma_dev) || + !device_is_ready(data->dma_tx.dma_dev)) { + return -ENODEV; + } + data->dma_rx.dma_channel = dma_request_channel(data->dma_rx.dma_dev, NULL); + data->i2c_instance.dma_channel.dma_rx_channel = data->dma_rx.dma_channel; + + data->dma_tx.dma_channel = dma_request_channel(data->dma_tx.dma_dev, NULL); + data->i2c_instance.dma_channel.dma_tx_channel = data->dma_tx.dma_channel; + + if (data->dma_rx.dma_channel < 0 || data->dma_tx.dma_channel < 0) { + dma_release_channel(data->dma_rx.dma_dev, data->dma_rx.dma_channel); + dma_release_channel(data->dma_tx.dma_dev, data->dma_tx.dma_channel); + return -EAGAIN; + } + } +#endif /* CONFIG_I2C_SILABS_DMA */ + + /* Configure IRQ */ + config->irq_config_func(); + + return pm_device_driver_init(dev, i2c_silabs_pm_action); +} + +static int i2c_silabs_pm_action(const struct device *dev, enum pm_device_action action) +{ + const struct i2c_silabs_dev_config *config = dev->config; + int ret; + + switch (action) { + case PM_DEVICE_ACTION_RESUME: + + /* Enable clock */ + ret = clock_control_on(config->clock, (clock_control_subsys_t)&config->clock_cfg); + if (ret < 0 && ret != -EALREADY) { + return ret; + } + /* Apply default pin configuration to resume normal operation */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + break; + case PM_DEVICE_ACTION_SUSPEND: + + /* Apply low-power pin configuration */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); + if (ret < 0 && ret != -ENOENT) { + return ret; + } + + /* Disable clock */ + ret = clock_control_off(config->clock, (clock_control_subsys_t)&config->clock_cfg); + if (ret < 0) { + return ret; + } + + break; + default: + return -ENOTSUP; + } + + return 0; +} + +/* ISR to dispatch DMA interrupts */ +void i2c_silabs_isr_handler(const struct device *dev) +{ + struct i2c_silabs_dev_data *data = dev->data; + sli_i2c_instance_t *sl_i2c_instance = &data->i2c_instance; + +#if defined(CONFIG_I2C_TARGET) + sli_i2c_follower_dispatch_interrupt(sl_i2c_instance); +#else + sli_i2c_leader_dispatch_interrupt(sl_i2c_instance); +#endif + if (sl_i2c_instance->transfer_event != SL_I2C_EVENT_IN_PROGRESS && + sl_i2c_instance->rstart == 0) { + if (!data->asynchronous) { + k_sem_give(&data->transfer_sem); + } +#if defined(CONFIG_I2C_CALLBACK) + if (data->callback && !data->callback_invoked) { + int err = 0; + + data->callback_invoked = true; + if (sl_i2c_instance->transfer_event == SL_I2C_EVENT_ARBITRATION_LOST || + sl_i2c_instance->transfer_event == SL_I2C_EVENT_BUS_ERROR || + sl_i2c_instance->transfer_event == SL_I2C_EVENT_INVALID_ADDR) { + err = -EIO; + } + data->callback(dev, err, data->callback_context); + } +#endif + if (data->last_transfer) { + /* Release the bus lock semaphore */ + k_sem_give(&data->bus_lock); + + if (!data->pm_lock_done) { + /* Release the power management policy state lock */ + i2c_silabs_pm_policy_state_lock_put(dev); + data->pm_lock_done = true; + } + } + } +} + +/* Store the I2C Driver APIs */ +static DEVICE_API(i2c, i2c_silabs_dev_driver_api) = { + .configure = i2c_silabs_dev_configure, + .transfer = i2c_silabs_dev_transfer, +#if defined(CONFIG_I2C_CALLBACK) + .transfer_cb = i2c_silabs_dev_transfer_cb, +#endif /* CONFIG_I2C_CALLBACK */ +}; + +#define I2C_INIT(idx) \ + PINCTRL_DT_INST_DEFINE(idx); \ + \ + static void i2c_silabs_irq_config_##idx(void) \ + { \ + COND_CODE_1(CONFIG_I2C_SILABS_DMA, \ + (IRQ_CONNECT(DT_INST_IRQ(idx, irq), DT_INST_IRQ(idx, priority), \ + i2c_silabs_isr_handler, DEVICE_DT_INST_GET(idx), 0); \ + irq_enable(DT_INST_IRQ(idx, irq));), \ + ()) \ + } \ + \ + static const struct i2c_silabs_dev_config i2c_silabs_dev_config_##idx = { \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \ + .base = (I2C_TypeDef *)DT_INST_REG_ADDR(idx), \ + .bitrate = DT_INST_PROP(idx, clock_frequency), \ + .irq_config_func = i2c_silabs_irq_config_##idx, \ + .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \ + .clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx), \ + }; \ + \ + static struct i2c_silabs_dev_data i2c_silabs_dev_data_##idx = { \ + .bus_lock = Z_SEM_INITIALIZER(i2c_silabs_dev_data_##idx.bus_lock, 1, 1), \ + .transfer_sem = Z_SEM_INITIALIZER(i2c_silabs_dev_data_##idx.transfer_sem, 0, 1), \ + .dma_rx.dma_dev = COND_CODE_1( \ + CONFIG_I2C_SILABS_DMA, \ + (DEVICE_DT_GET_OR_NULL(DT_INST_DMAS_CTLR_BY_NAME(idx, rx))), (NULL)), \ + .dma_tx.dma_dev = COND_CODE_1( \ + CONFIG_I2C_SILABS_DMA, \ + (DEVICE_DT_GET_OR_NULL(DT_INST_DMAS_CTLR_BY_NAME(idx, tx))), (NULL)), \ + }; \ + PM_DEVICE_DT_INST_DEFINE(idx, i2c_silabs_pm_action); \ + I2C_DEVICE_DT_INST_DEFINE(idx, i2c_silabs_dev_init, PM_DEVICE_DT_INST_GET(idx), \ + &i2c_silabs_dev_data_##idx, &i2c_silabs_dev_config_##idx, \ + POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \ + &i2c_silabs_dev_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(I2C_INIT) diff --git a/drivers/i2s/i2s_nrf_tdm.c b/drivers/i2s/i2s_nrf_tdm.c index c65edb2717bc4..45e5b3d18049d 100644 --- a/drivers/i2s/i2s_nrf_tdm.c +++ b/drivers/i2s/i2s_nrf_tdm.c @@ -30,6 +30,10 @@ LOG_MODULE_REGISTER(tdm_nrf, CONFIG_I2S_LOG_LEVEL); */ #define NRFX_TDM_STATUS_TRANSFER_STOPPED BIT(1) +/* Maximum clock divider value. Corresponds to CKDIV2. */ +#define NRFX_TDM_MAX_SCK_DIV_VALUE TDM_CONFIG_SCK_DIV_SCKDIV_Max +#define NRFX_TDM_MAX_MCK_DIV_VALUE TDM_CONFIG_MCK_DIV_DIV_Max + #define NRFX_TDM_NUM_OF_CHANNELS (TDM_CONFIG_CHANNEL_NUM_NUM_Max + 1) #define NRFX_TDM_TX_CHANNELS_MASK \ @@ -814,11 +818,11 @@ static int trigger_start(const struct device *dev) nrf_tdm_sck_configure(drv_cfg->p_reg, drv_cfg->sck_src == ACLK ? NRF_TDM_SRC_ACLK : NRF_TDM_SRC_PCLK32M, - false); + nrfx_cfg->sck_setup > NRFX_TDM_MAX_SCK_DIV_VALUE); nrf_tdm_mck_configure(drv_cfg->p_reg, drv_cfg->mck_src == ACLK ? NRF_TDM_SRC_ACLK : NRF_TDM_SRC_PCLK32M, - false); + nrfx_cfg->mck_setup > NRFX_TDM_MAX_MCK_DIV_VALUE); /* If it is required to use certain HF clock, request it to be running * first. If not, start the transfer directly. */ diff --git a/drivers/i2s/i2s_stm32_sai.c b/drivers/i2s/i2s_stm32_sai.c index dade7f2bc0041..f692af120c9d3 100644 --- a/drivers/i2s/i2s_stm32_sai.c +++ b/drivers/i2s/i2s_stm32_sai.c @@ -17,8 +17,6 @@ #include #include -#include -#include #include #include @@ -133,6 +131,7 @@ void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) { struct i2s_stm32_sai_data *dev_data = CONTAINER_OF(hsai, struct i2s_stm32_sai_data, hsai); struct stream *stream = &dev_data->stream; + void *mem_block_tmp = stream->mem_block; struct queue_item item; int ret; @@ -154,6 +153,7 @@ void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) if (stream->last_block) { LOG_DBG("TX Stopped ..."); stream->state = I2S_STATE_READY; + stream->mem_block = NULL; goto exit; } @@ -162,6 +162,7 @@ void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) if (k_msgq_num_used_get(&stream->queue) == 0) { LOG_DBG("Exit TX callback, no more data in the queue"); stream->state = I2S_STATE_READY; + stream->mem_block = NULL; goto exit; } @@ -183,7 +184,7 @@ void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) exit: /* Free memory slab & exit */ - k_mem_slab_free(stream->i2s_cfg.mem_slab, stream->mem_block); + k_mem_slab_free(stream->i2s_cfg.mem_slab, mem_block_tmp); } void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) @@ -274,23 +275,24 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) /* HACK: This field is used to inform driver that it is overridden */ dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE; - /* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */ - ret = dma_config(stream->dma_dev, stream->dma_channel + STM32_DMA_STREAM_OFFSET, &dma_cfg); + ret = dma_config(stream->dma_dev, stream->dma_channel, &dma_cfg); if (ret != 0) { - LOG_ERR("Failed to configure DMA channel %d", - stream->dma_channel + STM32_DMA_STREAM_OFFSET); + LOG_ERR("Failed to configure DMA channel %d", stream->dma_channel); return ret; } -#if defined(CONFIG_SOC_SERIES_STM32H7X) - hdma->Instance = __LL_DMA_GET_STREAM_INSTANCE(stream->reg, stream->dma_channel); + hdma->Instance = STM32_DMA_GET_INSTANCE(stream->reg, stream->dma_channel); + hdma->Init.Request = dma_cfg.dma_slot; + hdma->Init.Mode = DMA_NORMAL; + +#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32L4X) hdma->Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - hdma->Init.MemDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma->Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma->Init.Priority = DMA_PRIORITY_HIGH; - hdma->Init.FIFOMode = DMA_FIFOMODE_DISABLE; + hdma->Init.PeriphInc = DMA_PINC_DISABLE; + hdma->Init.MemInc = DMA_MINC_ENABLE; #else - hdma->Instance = LL_DMA_GET_CHANNEL_INSTANCE(stream->reg, stream->dma_channel); hdma->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST; hdma->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_HALFWORD; hdma->Init.DestDataWidth = DMA_DEST_DATAWIDTH_HALFWORD; @@ -301,16 +303,14 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) hdma->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER; #endif - hdma->Init.Request = dma_cfg.dma_slot; - hdma->Init.Mode = DMA_NORMAL; +#if defined(CONFIG_SOC_SERIES_STM32H7X) + hdma->Init.FIFOMode = DMA_FIFOMODE_DISABLE; +#endif if (stream->dma_cfg.channel_direction == (enum dma_channel_direction)MEMORY_TO_PERIPHERAL) { hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; -#if defined(CONFIG_SOC_SERIES_STM32H7X) - hdma->Init.PeriphInc = DMA_PINC_DISABLE; - hdma->Init.MemInc = DMA_MINC_ENABLE; -#else +#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) hdma->Init.SrcInc = DMA_SINC_INCREMENTED; hdma->Init.DestInc = DMA_DINC_FIXED; #endif @@ -319,10 +319,7 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) } else { hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; -#if defined(CONFIG_SOC_SERIES_STM32H7X) - hdma->Init.PeriphInc = DMA_PINC_ENABLE; - hdma->Init.MemInc = DMA_MINC_DISABLE; -#else +#if !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) hdma->Init.SrcInc = DMA_SINC_FIXED; hdma->Init.DestInc = DMA_DINC_INCREMENTED; #endif @@ -341,7 +338,7 @@ static int i2s_stm32_sai_dma_init(const struct device *dev) LOG_ERR("HAL_DMA_ConfigChannelAttributes: "); return -EIO; } -#elif !defined(CONFIG_SOC_SERIES_STM32H7X) +#elif !defined(CONFIG_SOC_SERIES_STM32H7X) && !defined(CONFIG_SOC_SERIES_STM32L4X) if (HAL_DMA_ConfigChannelAttributes(&dev_data->hdma, DMA_CHANNEL_NPRIV) != HAL_OK) { LOG_ERR("HAL_DMA_ConfigChannelAttributes: "); return -EIO; @@ -456,21 +453,28 @@ static int i2s_stm32_sai_configure(const struct device *dev, enum i2s_dir dir, return -EINVAL; } + /* Control of MCLK output from SAI configuration is not possible on STM32L4xx MCUs */ +#if !defined(CONFIG_SOC_SERIES_STM32L4X) if (cfg->mclk_enable && stream->master) { hsai->Init.MckOutput = SAI_MCK_OUTPUT_ENABLE; } else { hsai->Init.MckOutput = SAI_MCK_OUTPUT_DISABLE; } +#endif if (cfg->mclk_div == (enum mclk_divider)MCLK_NO_DIV) { hsai->Init.NoDivider = SAI_MASTERDIVIDER_DISABLED; } else { hsai->Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + + /* MckOverSampling is not supported by all STM32L4xx MCUs */ +#if !defined(CONFIG_SOC_SERIES_STM32L4X) if (cfg->mclk_div == (enum mclk_divider)MCLK_DIV_256) { hsai->Init.MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE; } else { hsai->Init.MckOverSampling = SAI_MCK_OVERSAMPLING_ENABLE; } +#endif } /* AudioFrequency */ diff --git a/drivers/i3c/i3c_dw.c b/drivers/i3c/i3c_dw.c index cd90b16b26499..0657a37c74a92 100644 --- a/drivers/i3c/i3c_dw.c +++ b/drivers/i3c/i3c_dw.c @@ -2373,14 +2373,17 @@ static int dw_i3c_init(const struct device *dev) if (ret != 0) { return ret; } -#endif /* CONFIG_I3C_CONTROLLER */ - dw_i3c_enable_controller(config, true); -#ifdef CONFIG_I3C_CONTROLLER + if (!(ctrl_config->is_secondary)) { ret = set_controller_info(dev); if (ret) { return ret; } + } +#endif /* CONFIG_I3C_CONTROLLER */ + dw_i3c_enable_controller(config, true); +#ifdef CONFIG_I3C_CONTROLLER + if (!(ctrl_config->is_secondary)) { /* Perform bus initialization - skip if no I3C devices are known. */ if (config->common.dev_list.num_i3c > 0) { ret = i3c_bus_init(dev, &config->common.dev_list); diff --git a/drivers/i3c/i3c_max32.c b/drivers/i3c/i3c_max32.c index f82838ca2df69..3a562f4e51ac9 100644 --- a/drivers/i3c/i3c_max32.c +++ b/drivers/i3c/i3c_max32.c @@ -1127,15 +1127,6 @@ static int max32_i3c_do_ccc(const struct device *dev, struct i3c_ccc_payload *pa return -EINVAL; } - if (config->common.dev_list.num_i3c == 0) { - /* - * No i3c devices in dev tree. Just return so - * we don't get errors doing cmds when there - * are no devices listening/responding. - */ - return 0; - } - k_mutex_lock(&data->lock, K_FOREVER); max32_i3c_xfer_reset(regs); diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt index 1677514593cc1..5007123095602 100644 --- a/drivers/input/CMakeLists.txt +++ b/drivers/input/CMakeLists.txt @@ -24,6 +24,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT51XXX_KBD input_ite_it51xxx_kbd. zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8801_KBD input_ite_it8801_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8XXX2_KBD input_ite_it8xxx2_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_KBD_MATRIX input_kbd_matrix.c) +zephyr_library_sources_ifdef(CONFIG_INPUT_MCUX_KPP input_mcux_kpp.c) zephyr_library_sources_ifdef(CONFIG_INPUT_MODULINO_BUTTONS input_modulino_buttons.c) zephyr_library_sources_ifdef(CONFIG_INPUT_NPCX_KBD input_npcx_kbd.c) zephyr_library_sources_ifdef(CONFIG_INPUT_NUNCHUK input_nunchuk.c) diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index e4c83af5350bc..be547866a417e 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -26,6 +26,7 @@ source "drivers/input/Kconfig.it51xxx" source "drivers/input/Kconfig.it8801" source "drivers/input/Kconfig.it8xxx2" source "drivers/input/Kconfig.kbd_matrix" +source "drivers/input/Kconfig.mcux_kpp" source "drivers/input/Kconfig.modulino" source "drivers/input/Kconfig.npcx" source "drivers/input/Kconfig.nunchuk" diff --git a/drivers/input/Kconfig.mcux_kpp b/drivers/input/Kconfig.mcux_kpp new file mode 100644 index 0000000000000..00cf2998bf9f0 --- /dev/null +++ b/drivers/input/Kconfig.mcux_kpp @@ -0,0 +1,16 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config INPUT_MCUX_KPP + bool "KPP driver" + default y + depends on DT_HAS_NXP_MCUX_KPP_ENABLED + help + Enable the driver of keypad port. + +config INPUT_KPP_PERIOD_MS + int "Sample period" + default 10 + depends on INPUT_MCUX_KPP + help + Sample period in milliseconds when the key is pressed. diff --git a/drivers/input/input_mcux_kpp.c b/drivers/input/input_mcux_kpp.c new file mode 100644 index 0000000000000..df206a8ee2d73 --- /dev/null +++ b/drivers/input/input_mcux_kpp.c @@ -0,0 +1,191 @@ +/* + * Copyright 2025, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(kpp, CONFIG_INPUT_LOG_LEVEL); + +#define DT_DRV_COMPAT nxp_mcux_kpp + +#define INPUT_KPP_COLUMNNUM_MAX KPP_KEYPAD_COLUMNNUM_MAX +#define INPUT_KPP_ROWNUM_MAX KPP_KEYPAD_ROWNUM_MAX +#define INPUT_KPP_ROWNUM_MAX KPP_KEYPAD_ROWNUM_MAX + +struct kpp_config { + KPP_Type *base; + const struct device *ccm_dev; + clock_control_subsys_t clk_sub_sys; + const struct pinctrl_dev_config *pcfg; +}; + +struct kpp_data { + uint32_t clock_rate; + struct k_work_delayable work; + uint8_t read_keys_old[KPP_KEYPAD_COLUMNNUM_MAX]; + uint8_t read_keys_new[KPP_KEYPAD_COLUMNNUM_MAX]; + uint8_t key_pressed_number; + const struct device *dev; +}; + +static void get_source_clk_rate(const struct device *dev, uint32_t *clk_rate) +{ + const struct kpp_config *dev_cfg = dev->config; + const struct device *ccm_dev = dev_cfg->ccm_dev; + clock_control_subsys_t clk_sub_sys = dev_cfg->clk_sub_sys; + + if (!device_is_ready(ccm_dev)) { + LOG_ERR("CCM driver is not installed"); + *clk_rate = 0; + return; + } + + clock_control_get_rate(ccm_dev, clk_sub_sys, clk_rate); +} + +static void kpp_work_handler(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct kpp_data *drv_data = CONTAINER_OF(dwork, struct kpp_data, work); + const struct device *dev = drv_data->dev; + const struct kpp_config *config = dev->config; + + uint8_t read_keys_new[KPP_KEYPAD_COLUMNNUM_MAX]; + + /* Read the key press data */ + KPP_keyPressScanning(config->base, read_keys_new, drv_data->clock_rate); + + /* Analyze the keypad data */ + for (int col = 0; col < INPUT_KPP_COLUMNNUM_MAX; col++) { + if (drv_data->read_keys_old[col] == read_keys_new[col]) { + continue; + } + for (int row = 0; row < INPUT_KPP_ROWNUM_MAX; row++) { + if (((drv_data->read_keys_old[col] ^ read_keys_new[col]) + & BIT(row)) == 0) { + continue; + } + if ((read_keys_new[col] & BIT(row)) != 0) { + /* Key press event */ + KPP_SetSynchronizeChain(config->base, + kKPP_ClearKeyDepressSyncChain); + input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER); + input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER); + drv_data->key_pressed_number++; + } else { + /* Key release event */ + KPP_SetSynchronizeChain(config->base, + kKPP_SetKeyReleasesSyncChain); + input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER); + input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER); + input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER); + drv_data->key_pressed_number--; + } + drv_data->read_keys_old[col] = read_keys_new[col]; + } + } + + if (drv_data->key_pressed_number == 0U) { + KPP_ClearStatusFlag(config->base, kKPP_keyDepressInterrupt | + kKPP_keyReleaseInterrupt); + KPP_EnableInterrupts(config->base, kKPP_keyDepressInterrupt); + } else { + k_work_schedule(&drv_data->work, K_MSEC(CONFIG_INPUT_KPP_PERIOD_MS)); + } +} + +static void kpp_isr(const struct device *dev) +{ + const struct kpp_config *config = dev->config; + struct kpp_data *drv_data = dev->data; + + uint16_t status = KPP_GetStatusFlag(config->base); + + if ((status & kKPP_keyDepressInterrupt) == 0) { + LOG_ERR("No key press or release detected"); + return; + } + + drv_data->key_pressed_number = 0; + /* Disable interrupts. */ + KPP_DisableInterrupts(config->base, kKPP_keyDepressInterrupt | + kKPP_keyReleaseInterrupt); + /* Clear status. */ + KPP_ClearStatusFlag(config->base, kKPP_keyDepressInterrupt | + kKPP_keyReleaseInterrupt); + /* Key depress report */ + k_work_schedule(&drv_data->work, K_MSEC(0)); +} + +static int input_kpp_init(const struct device *dev) +{ + const struct kpp_config *config = dev->config; + struct kpp_data *drv_data = dev->data; + kpp_config_t kppConfig; + + if (!device_is_ready(config->ccm_dev)) { + LOG_ERR("CCM driver is not installed"); + return -ENODEV; + } + + int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + + if (ret < 0) { + LOG_ERR("Failed to configure pin"); + return ret; + } + + kppConfig.activeRow = 0xFF; + kppConfig.activeColumn = 0xFF; + kppConfig.interrupt = kKPP_keyDepressInterrupt; + + KPP_Init(config->base, &kppConfig); + + get_source_clk_rate(dev, &drv_data->clock_rate); + + drv_data->dev = dev; + + /* Read the key press data */ + KPP_keyPressScanning(config->base, drv_data->read_keys_old, drv_data->clock_rate); + + k_work_init_delayable(&drv_data->work, kpp_work_handler); + + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), + kpp_isr, DEVICE_DT_INST_GET(0), 0); + return 0; +} + +#define INPUT_KPP_INIT(n) \ + static struct kpp_data kpp_data_##n; \ + \ + PINCTRL_DT_INST_DEFINE(n); \ + \ + static const struct kpp_config kpp_config_##n = { \ + .base = (KPP_Type *)DT_INST_REG_ADDR(n), \ + .clk_sub_sys = \ + (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(n, 0, name), \ + .ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, \ + input_kpp_init, \ + NULL, \ + &kpp_data_##n, \ + &kpp_config_##n, \ + POST_KERNEL, \ + CONFIG_INPUT_INIT_PRIORITY, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(INPUT_KPP_INIT) diff --git a/drivers/interrupt_controller/Kconfig.gic b/drivers/interrupt_controller/Kconfig.gic index c0c348750b293..c2bb011ba9f07 100644 --- a/drivers/interrupt_controller/Kconfig.gic +++ b/drivers/interrupt_controller/Kconfig.gic @@ -78,9 +78,9 @@ config GIC_V3_RDIST_DMA_NONCOHERENT depends on GIC_V3 default n help - GIC redistributor on Some platform are connected to a non-coherent - downstream interconnect, it need to use Non-cahable and Non-shareable - access atttributes to access external memory. + GIC redistributor on some platforms is connected to a non-coherent + downstream interconnect, it needs to use Non-cacheable and Non-shareable + access attributes to access external memory. config GIC_V3_ITS_DMA_NONCOHERENT bool "GIC ITS is DMA noncoherent" @@ -88,7 +88,7 @@ config GIC_V3_ITS_DMA_NONCOHERENT default n help GIC ITS on Some platform are connected to a non-coherent downstream - interconnect, it need to use Non-cahable and Non-shareable access - atttributes to access external memory. + interconnect, it need to use Non-cacheable and Non-shareable access + attributes to access external memory. endif # CPU_CORTEX diff --git a/drivers/interrupt_controller/intc_gpio_stm32.c b/drivers/interrupt_controller/intc_gpio_stm32.c index 6f049c3b224af..6f55cf7750f49 100644 --- a/drivers/interrupt_controller/intc_gpio_stm32.c +++ b/drivers/interrupt_controller/intc_gpio_stm32.c @@ -102,7 +102,7 @@ static void stm32_intc_gpio_isr(const void *exti_range) uint32_t line_num; /* see which bits are set */ - for (uint8_t i = 0; i <= range->len; i++) { + for (uint8_t i = 0; i < range->len; i++) { line_num = range->start + i; /* check if interrupt is pending */ diff --git a/drivers/lora/CMakeLists.txt b/drivers/lora/CMakeLists.txt index 85a37f0d55948..f1bbba12c0257 100644 --- a/drivers/lora/CMakeLists.txt +++ b/drivers/lora/CMakeLists.txt @@ -1,23 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -# LoRa drivers depend on the include directories exposed by the loramac-node -# library. Hence, if it exists then the source files are added to that otherwise -# a library with same name is created. -if(TARGET loramac-node) - set(ZEPHYR_CURRENT_LIBRARY loramac-node) -else() - zephyr_library_named(loramac-node) -endif() +zephyr_sources_ifdef(CONFIG_LORA_SHELL shell.c) -zephyr_library_sources_ifdef(CONFIG_LORA_SHELL shell.c) -zephyr_library_sources_ifdef(CONFIG_HAS_SEMTECH_RADIO_DRIVERS hal_common.c) -zephyr_library_sources_ifdef(CONFIG_HAS_SEMTECH_RADIO_DRIVERS sx12xx_common.c) -zephyr_library_sources_ifdef(CONFIG_LORA_SX127X sx127x.c) - -if (CONFIG_LORA_SX126X OR CONFIG_LORA_STM32WL_SUBGHZ_RADIO) - zephyr_library_sources(sx126x.c) -endif() - -zephyr_library_sources_ifdef(CONFIG_LORA_SX126X sx126x_standalone.c) -zephyr_library_sources_ifdef(CONFIG_LORA_STM32WL_SUBGHZ_RADIO sx126x_stm32wl.c) -zephyr_library_sources_ifdef(CONFIG_LORA_RYLRXXX rylrxxx.c) +add_subdirectory_ifdef(CONFIG_LORA_MODULE_BACKEND_LORAMAC_NODE loramac_node) +add_subdirectory_ifdef(CONFIG_LORA_MODULE_BACKEND_LORA_BASICS_MODEM lora_basics_modem) diff --git a/drivers/lora/Kconfig b/drivers/lora/Kconfig index 6319ccf6be9e2..124f4619d07eb 100644 --- a/drivers/lora/Kconfig +++ b/drivers/lora/Kconfig @@ -15,6 +15,23 @@ menuconfig LORA if LORA +choice LORA_MODULE_BACKEND + prompt "Low-level LoRa modem integration to use" + +config LORA_MODULE_BACKEND_LORAMAC_NODE + bool "loramac-node backend" + depends on ZEPHYR_LORAMAC_NODE_MODULE + +config LORA_MODULE_BACKEND_LORA_BASICS_MODEM + bool "LoRa Basic modem backend [EXPERIMENTAL]" + depends on ZEPHYR_LORA_BASICS_MODEM_MODULE + depends on DT_HAS_SEMTECH_SX1262_ENABLED || DT_HAS_SEMTECH_SX1261_ENABLED || DT_HAS_SEMTECH_SX1272_ENABLED || DT_HAS_SEMTECH_SX1276_ENABLED + select USE_LORA_BASICS_MODEM_DRIVERS + help + Experimental support for implementing the LoRa API using the LoRa Basics Modem module. + +endchoice + module = LORA module-str = lora source "subsys/logging/Kconfig.template.log_config" @@ -31,8 +48,8 @@ config LORA_INIT_PRIORITY help System initialization priority for LoRa drivers. -source "drivers/lora/Kconfig.sx12xx" - -source "drivers/lora/Kconfig.rylrxxx" +rsource "Kconfig.sx12xx" +rsource "Kconfig.rylrxxx" +rsource "lora_basics_modem/Kconfig" endif # LORA diff --git a/drivers/lora/lora_basics_modem/CMakeLists.txt b/drivers/lora/lora_basics_modem/CMakeLists.txt new file mode 100644 index 0000000000000..fa96b05064172 --- /dev/null +++ b/drivers/lora/lora_basics_modem/CMakeLists.txt @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# LoRa drivers depend on the include directories exposed by the lora_basics_modem +# library. Hence, if it exists then the source files are added to that otherwise +# a library with same name is created. +if(TARGET lora_basics_modem) + set(ZEPHYR_CURRENT_LIBRARY lora_basics_modem) +else() + zephyr_library_named(lora_basics_modem) +endif() + +zephyr_library_sources(lbm_common.c) +zephyr_library_sources_ifdef(CONFIG_LORA_SX126X lbm_sx126x.c) +zephyr_library_sources_ifdef(CONFIG_LORA_SX127X lbm_sx127x.c) +zephyr_library_sources_ifdef(CONFIG_LORA_RYLRXXX ../rylrxxx.c) diff --git a/drivers/lora/lora_basics_modem/Kconfig b/drivers/lora/lora_basics_modem/Kconfig new file mode 100644 index 0000000000000..561984468e371 --- /dev/null +++ b/drivers/lora/lora_basics_modem/Kconfig @@ -0,0 +1,37 @@ +# +# Copyright (c) 2025 Embeint Inc +# +# SPDX-License-Identifier: Apache-2.0 +# + +if LORA_MODULE_BACKEND_LORA_BASICS_MODEM + +config LORA_BASICS_MODEM_ASYNC_RX_MAX_PAYLOAD + int "Maximum size payload that can be received by async RX" + default 256 + help + A buffer of this size is allocated on the system workqueue stack when + running the async RX handler. + +choice LORA_BASICS_MODEM_RSSI_REPORT_TYPE + prompt "Type of RSSI to report to the application layer" + default LORA_BASICS_MODEM_RSSI_REPORT_TYPE_SIGNAL + +config LORA_BASICS_MODEM_RSSI_REPORT_TYPE_PACKET + bool "Report the packet RSSI (rssi_pkt_in_dbm)" + help + The packet RSSI is the strength of the signal in the configured band. + Once the LoRa signal goes below the noise floor, this value with stay + at the signal strength of the noise floor. + +config LORA_BASICS_MODEM_RSSI_REPORT_TYPE_SIGNAL + bool "Report the signal RSSI (signal_rssi_pkt_in_dbm)" + help + The signal RSSI is an estimate of the strength of the received LoRa + signal. In contrast to the packet RSSI, this value will continue to + decrease below the noise floor as the signal approaches the sensitivity + limits of the receiver. + +endchoice + +endif diff --git a/drivers/lora/lora_basics_modem/lbm_common.c b/drivers/lora/lora_basics_modem/lbm_common.c new file mode 100644 index 0000000000000..42bea84267abb --- /dev/null +++ b/drivers/lora/lora_basics_modem/lbm_common.c @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2025 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "lbm_common.h" + +/* LoRa interrupts from the RAL library */ +#define RAL_IRQ_LORA \ + RAL_IRQ_TX_DONE | RAL_IRQ_RX_DONE | RAL_IRQ_RX_HDR_ERROR | RAL_IRQ_RX_CRC_ERROR | \ + RAL_IRQ_CAD_DONE | RAL_IRQ_CAD_OK + +LOG_MODULE_REGISTER(lbm_driver, CONFIG_LORA_LOG_LEVEL); + +/** + * @brief Attempt to acquire the modem for operations + * + * @param dev modem to acquire + * + * @retval true if modem was acquired + * @retval false otherwise + */ +static inline bool modem_acquire(const struct device *dev) +{ + struct lbm_lora_data_common *data = dev->data; + + return atomic_cas(&data->modem_state, STATE_FREE, STATE_BUSY); +} + +/** + * @brief Safely release the modem from any context + * + * This function can be called from any context and guarantees that the + * release operations will only be run once. + * + * @param dev modem to release + * + * @retval true if modem was released by this function + * @retval false otherwise + */ +static bool modem_release(const struct device *dev) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + + /* Move to cleanup state so both acquire and release will fail */ + if (!atomic_cas(&data->modem_state, STATE_BUSY, STATE_CLEANUP)) { + return false; + } + + /* Configure modem for sleep */ + lbm_driver_antenna_configure(dev, MODE_SLEEP); + data->modem_mode = MODE_SLEEP; + + /* Put radio back into sleep mode */ + (void)ral_set_sleep(&config->ralf.ral, true); + + /* Completely release modem */ + data->operation_done = NULL; + atomic_set(&data->modem_state, STATE_FREE); + return true; +} + +int lbm_lora_config(const struct device *dev, struct lora_modem_config *lora_config) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + ralf_params_lora_t params = { + .mod_params = { + .sf = lora_config->datarate, + .cr = lora_config->coding_rate, + .ldro = 0, + }, + .pkt_params = { + .preamble_len_in_symb = lora_config->preamble_len, + .header_type = RAL_LORA_PKT_EXPLICIT, + .pld_len_in_bytes = UINT8_MAX, + .crc_is_on = true, + .invert_iq_is_on = lora_config->iq_inverted, + }, + .rf_freq_in_hz = lora_config->frequency, + .output_pwr_in_dbm = lora_config->tx_power, + .sync_word = lora_config->public_network ? LBM_LORA_SYNC_WORD_PUBLIC + : LBM_LORA_SYNC_WORD_PRIVATE, + }; + ral_status_t status; + int ret; + + /* Ensure available, decremented after configuration */ + if (!modem_acquire(dev)) { + return -EBUSY; + } + + switch (lora_config->bandwidth) { + case BW_125_KHZ: + params.mod_params.bw = RAL_LORA_BW_125_KHZ; + break; + case BW_250_KHZ: + params.mod_params.bw = RAL_LORA_BW_250_KHZ; + break; + case BW_500_KHZ: + params.mod_params.bw = RAL_LORA_BW_500_KHZ; + break; + default: + ret = -EINVAL; + goto release; + } + + /* Store TX parameters for use in the TX functions */ + data->mod_params = params.mod_params; + data->pkt_params = params.pkt_params; + + status = ralf_setup_lora(&config->ralf, ¶ms); + ret = status == RAL_STATUS_OK ? 0 : -EIO; + +release: + modem_release(dev); + return ret; +} + +int lbm_lora_send_async(const struct device *dev, uint8_t *msg, uint32_t msg_len, + struct k_poll_signal *async) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + ral_status_t status; + int ret = 0; + + /* Ensure available, freed by TX done callback */ + if (!modem_acquire(dev)) { + return -EBUSY; + } + + /* Configure modem for TX */ + lbm_driver_antenna_configure(dev, MODE_TX); + data->modem_mode = MODE_TX; + + /* Validate that we have a TX configuration */ + if (data->mod_params.sf == 0) { + ret = -EINVAL; + goto release; + } + + /* Store signal */ + data->operation_done = async; + + /* Update packet params to override the internal packet length variable. + * This has a huge overhead since it performs many register writes, but is the only + * generic way to update the variable. Why this isn't just done in ral_set_pkt_payload + * is anyones guess. + */ + data->pkt_params.pld_len_in_bytes = msg_len; + status = ral_set_lora_pkt_params(&config->ralf.ral, &data->pkt_params); + if (status != RAL_STATUS_OK) { + ret = -EINVAL; + goto release; + } + + /* Set the packet payload */ + status = ral_set_pkt_payload(&config->ralf.ral, msg, msg_len); + if (status != RAL_STATUS_OK) { + ret = -EINVAL; + goto release; + } + + /* Start the transmission */ + status = ral_set_tx(&config->ralf.ral); + if (status != RAL_STATUS_OK) { + ret = -EINVAL; + goto release; + } + return 0; + +release: + modem_release(dev); + return ret; +} + +int lbm_lora_send(const struct device *dev, uint8_t *msg, uint32_t msg_len) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + struct k_poll_signal done = K_POLL_SIGNAL_INITIALIZER(done); + struct k_poll_event evt = + K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &done); + uint32_t air_time; + int ret; + + /* Trigger the asynchronous send */ + ret = lbm_lora_send_async(dev, msg, msg_len, &done); + if (ret < 0) { + return ret; + } + + /* Calculate expected airtime of the packet */ + air_time = ral_get_lora_time_on_air_in_ms(&config->ralf.ral, &data->pkt_params, + &data->mod_params); + LOG_DBG("Expected airtime: %d ms", air_time); + + /* Wait for the packet to finish transmitting. + * Setting up the transaction takes some minimal time, take it into + * account to ensure extremely short packets don't incorrectly timeout. + * Use twice the tx duration to ensure that we are actually detecting + * a failed transmission, and not some minor timing variation between + * modem and driver. + */ + ret = k_poll(&evt, 1, K_MSEC(10 + (2 * air_time))); + if (ret < 0) { + if (modem_release(dev)) { + LOG_ERR("Packet transmission failed!"); + } else { + /* TX done interrupt is currently running */ + k_poll(&evt, 1, K_FOREVER); + } + } + return ret; +} + +int lbm_lora_recv(const struct device *dev, uint8_t *msg, uint8_t msg_len, k_timeout_t timeout, + int16_t *rssi, int8_t *snr) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + struct k_poll_signal done = K_POLL_SIGNAL_INITIALIZER(done); + struct k_poll_event evt = + K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &done); + ral_status_t status; + int ret; + + /* Ensure available, decremented by op_done_work_handler or on timeout */ + if (!modem_acquire(dev)) { + return -EBUSY; + } + + /* Store signal */ + data->operation_done = &done; + data->rx_state.sync.msg = msg; + data->rx_state.sync.msg_len = msg_len; + + /* Configure modem for RX */ + lbm_driver_antenna_configure(dev, MODE_RX); + data->modem_mode = MODE_RX; + + /* Start the reception in continuous mode. + * Receive timeouts are handled by the k_poll timeout. + * In theory we should be able to use the one-shot mode here and transition + * back to IDLE slightly faster, but the SX127x driver does not appear to + * receive packets reliably in the single-shot mode. + */ + status = ral_set_rx(&config->ralf.ral, RAL_RX_TIMEOUT_CONTINUOUS_MODE); + if (status != RAL_STATUS_OK) { + ret = -EINVAL; + goto release; + } + + /* Wait for the packet to be received */ + ret = k_poll(&evt, 1, timeout); + if (ret < 0) { + if (modem_release(dev)) { + LOG_INF("Receive timeout"); + return -EAGAIN; + } + /* Releasing the modem failed, which means that + * the RX callback is currently running. Wait until + * the RX callback finishes and we get our packet. + */ + k_poll(&evt, 1, K_FOREVER); + + /* We did receive a packet, continue processing */ + } + + if (done.result != 0) { + LOG_ERR("Receive error"); + ret = done.result; + goto release; + } + + /* Retrieve cached RSSI and SNR */ + *rssi = data->rx_state.sync.rssi_dbm; + *snr = data->rx_state.sync.snr_db; + ret = data->rx_state.sync.msg_len; + +release: + modem_release(dev); + return ret; +} + +int lbm_lora_recv_async(const struct device *dev, lora_recv_cb cb, void *user_data) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + ral_status_t status; + + /* Cancel ongoing reception */ + if (cb == NULL) { + if (!modem_release(dev)) { + /* Not receiving or already being stopped */ + return -EINVAL; + } + return 0; + } + + /* Ensure available */ + if (!modem_acquire(dev)) { + return -EBUSY; + } + + /* Configure modem for asynchronous RX */ + lbm_driver_antenna_configure(dev, MODE_RX_ASYNC); + data->modem_mode = MODE_RX_ASYNC; + + /* Store user state */ + data->rx_state.async.rx_cb = cb; + data->rx_state.async.user_data = user_data; + + /* Start the reception in continuous mode */ + status = ral_set_rx(&config->ralf.ral, RAL_RX_TIMEOUT_CONTINUOUS_MODE); + if (status != RAL_STATUS_OK) { + modem_release(dev); + return -EIO; + } + return 0; +} + +int lbm_lora_test_cw(const struct device *dev, uint32_t frequency, int8_t tx_power, + uint16_t duration) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + ral_status_t status; + int ret = 0; + + /* Ensure available, freed by op_done_work */ + if (!modem_acquire(dev)) { + return -EBUSY; + } + + /* Configure modem for CW */ + lbm_driver_antenna_configure(dev, MODE_CW); + data->modem_mode = MODE_CW; + + /* Invalidate stored config */ + data->mod_params.sf = 0; + + /* Configure continuous wave */ + status = ral_set_pkt_type(&config->ralf.ral, RAL_PKT_TYPE_LORA); + if (status != RAL_STATUS_OK) { + return status; + } + status = ral_set_rf_freq(&config->ralf.ral, frequency); + if (status != RAL_STATUS_OK) { + return status; + } + status = ral_set_tx_cfg(&config->ralf.ral, tx_power, frequency); + if (status != RAL_STATUS_OK) { + return status; + } + + /* Start the continuous wave transmission */ + status = ral_set_tx_cw(&config->ralf.ral); + if (status != RAL_STATUS_OK) { + ret = -EIO; + goto release; + } + + /* Schedule the end of the transmission */ + k_work_reschedule(&data->op_done_work, K_MSEC(duration)); + return 0; +release: + modem_release(dev); + return ret; +} + +static int op_done_sync_rx(const struct device *dev) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + ral_lora_rx_pkt_status_t pkt_status; + ral_status_t status; + int ret; + + /* Retrieve packet information before putting modem into sleep mode */ + status = ral_get_pkt_payload(&config->ralf.ral, data->rx_state.sync.msg_len, + data->rx_state.sync.msg, &data->rx_state.sync.msg_len); + if (status == RAL_STATUS_OK) { + LOG_HEXDUMP_DBG(data->rx_state.sync.msg, data->rx_state.sync.msg_len, "RX"); + ret = 0; + } else { + LOG_ERR("Failed to retrieve packet payload"); + ret = -EIO; + } + + status = ral_get_lora_rx_pkt_status(&config->ralf.ral, &pkt_status); + if (status == RAL_STATUS_OK) { + data->rx_state.sync.rssi_dbm = pkt_status.signal_rssi_pkt_in_dbm; + data->rx_state.sync.snr_db = pkt_status.snr_pkt_in_db; + } else { + LOG_WRN("Failed to query packet signal stats"); + data->rx_state.sync.rssi_dbm = INT16_MIN; + data->rx_state.sync.snr_db = INT8_MIN; + } + + return ret; +} + +static void op_done_async_rx(const struct device *dev) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + ral_lora_rx_pkt_status_t pkt_status; + uint8_t rx_buffer[CONFIG_LORA_BASICS_MODEM_ASYNC_RX_MAX_PAYLOAD]; + ral_status_t status; + uint16_t size; + int16_t rssi; + + /* Retrieve the packet payload */ + status = ral_get_pkt_payload(&config->ralf.ral, sizeof(rx_buffer), rx_buffer, &size); + if (status != RAL_STATUS_OK) { + LOG_ERR("Failed to retrieve packet payload"); + return; + } + LOG_HEXDUMP_DBG(rx_buffer, size, "RX"); + + /* Retrieve packet parameters */ + status = ral_get_lora_rx_pkt_status(&config->ralf.ral, &pkt_status); + if (status != RAL_STATUS_OK) { + LOG_WRN("Failed to query packet signal stats"); + } + + rssi = IS_ENABLED(CONFIG_LORA_BASICS_MODEM_RSSI_REPORT_TYPE_PACKET) + ? pkt_status.rssi_pkt_in_dbm + : pkt_status.signal_rssi_pkt_in_dbm; + + /* Run the user callback */ + data->rx_state.async.rx_cb(dev, rx_buffer, size, rssi, pkt_status.snr_pkt_in_db, + data->rx_state.async.user_data); +} + +static void op_done_work_handler(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct lbm_lora_data_common *data = + CONTAINER_OF(dwork, struct lbm_lora_data_common, op_done_work); + const struct device *dev = data->dev; + const struct lbm_lora_config_common *config = dev->config; + struct k_poll_signal *sig_done; + ral_irq_t irq_state; + ral_status_t status; + bool release = false; + bool error_irq; + int ret = 0; + + LOG_DBG("%d", data->modem_mode); + + switch (data->modem_mode) { + case MODE_SLEEP: + LOG_WRN("Unexpected modem mode (%d)", data->modem_mode); + return; + case MODE_TX: + case MODE_CW: + status = ral_handle_tx_done(&config->ralf.ral); + if (status != RAL_STATUS_OK) { + LOG_WRN("RAL handle TX done failed (%d)", status); + } + release = true; + break; + case MODE_RX: + status = ral_handle_rx_done(&config->ralf.ral); + if (status != RAL_STATUS_OK) { + LOG_WRN("RAL handle RX done failed (%d)", status); + } + ret = op_done_sync_rx(dev); + release = true; + break; + case MODE_RX_ASYNC: + status = ral_handle_rx_done(&config->ralf.ral); + if (status != RAL_STATUS_OK) { + LOG_WRN("RAL handle RX done failed (%d)", status); + } + op_done_async_rx(dev); + /* Don't release the modem here, RX continues */ + break; + case MODE_CAD: + LOG_DBG("CAD complete (TBC)"); + break; + } + + /* Get and reset the current IRQ state */ + (void)ral_get_irq_status(&config->ralf.ral, &irq_state); + (void)ral_clear_irq_status(&config->ralf.ral, RAL_IRQ_ALL); + error_irq = irq_state & (RAL_IRQ_RX_TIMEOUT | RAL_IRQ_RX_HDR_ERROR | RAL_IRQ_RX_CRC_ERROR); + + /* Release the modem before running the user callback so that the notified thread can + * immediately start another operation before the work item terminates. This requires + * preserving the operation_done pointer, since modem_release clears it. + */ + sig_done = data->operation_done; + + /* Modem should return to idle */ + if (release) { + /* Return to sleep mode */ + modem_release(dev); + } + + /* Notify user that operation has completed */ + if (sig_done) { + k_poll_signal_raise(sig_done, error_irq ? -EAGAIN : ret); + } +} + +int lbm_lora_common_init(const struct device *dev) +{ + const struct lbm_lora_config_common *config = dev->config; + struct lbm_lora_data_common *data = dev->data; + ral_status_t status; + + data->dev = dev; + k_work_init_delayable(&data->op_done_work, op_done_work_handler); + atomic_clear(&data->modem_state); + + /* Initialise the radio abstraction layer */ + status = ral_init(&config->ralf.ral); + if (status != RAL_STATUS_OK) { + LOG_ERR("RAL init failure (%d)", status); + return -EIO; + } + + /* Enable all relevant interrupts */ + status = ral_set_dio_irq_params(&config->ralf.ral, RAL_IRQ_LORA); + if (status != RAL_STATUS_OK) { + LOG_ERR("RAL DIO init failure (%d)", status); + return -EIO; + } + + /* Idle in sleep mode */ + status = ral_set_sleep(&config->ralf.ral, true); + if (status != RAL_STATUS_OK) { + LOG_ERR("Sleep failure (%d)", status); + return -EIO; + } + return 0; +} + +DEVICE_API(lora, lbm_lora_api) = { + .config = lbm_lora_config, + .send = lbm_lora_send, + .send_async = lbm_lora_send_async, + .recv = lbm_lora_recv, + .recv_async = lbm_lora_recv_async, + .test_cw = lbm_lora_test_cw, +}; diff --git a/drivers/lora/lora_basics_modem/lbm_common.h b/drivers/lora/lora_basics_modem/lbm_common.h new file mode 100644 index 0000000000000..8ce24e780d5ff --- /dev/null +++ b/drivers/lora/lora_basics_modem/lbm_common.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2025 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include "ralf.h" + +#define STATE_FREE 0 +#define STATE_BUSY 1 +#define STATE_CLEANUP 2 + +/* LoRa sync words, taken from the legacy loramac-node sx1272.h/sx1276.h */ +enum lbm_modem_lora_sync_word { + LBM_LORA_SYNC_WORD_PRIVATE = 0x12, + LBM_LORA_SYNC_WORD_PUBLIC = 0x34, +}; + +/* Current operation mode of the LBM modem */ +enum lbm_modem_mode { + MODE_SLEEP = 0, + MODE_TX = 1, + MODE_CW = 2, + MODE_RX = 3, + MODE_RX_ASYNC = 4, + MODE_CAD = 5, +}; + +/* Common LBM modem configuration, must be first element of device config */ +struct lbm_lora_config_common { + /* LBM radio abstration layer structure */ + ralf_t ralf; +}; + +/* Common LBM modem data, must be first element of device data */ +struct lbm_lora_data_common { + /* Reference back to parent device */ + const struct device *dev; + /* Current LoRa parameters */ + ral_lora_mod_params_t mod_params; + ral_lora_pkt_params_t pkt_params; + /* Operation complete worker */ + struct k_work_delayable op_done_work; + /* RX state storage */ + union { + struct { + /* Sync RX params */ + uint8_t *msg; + uint16_t msg_len; + int16_t rssi_dbm; + int8_t snr_db; + } sync; + struct { + /* Async RX params */ + lora_recv_cb rx_cb; + void *user_data; + } async; + } rx_state; + /* User signal */ + struct k_poll_signal *operation_done; + /* Current modem state */ + atomic_t modem_state; + enum lbm_modem_mode modem_mode; +}; + +/** + * @brief Initialise common LBM data structures + * + * @param dev Modem to initialise + * + * @retval 0 On success + * @retval -errno On failure + */ +int lbm_lora_common_init(const struct device *dev); + +/** + * @brief Configure modem for a given mode + * + * Expected to be implemented by individual drivers + * + * @param dev Modem to configure + * @param mode Mode to configure for + */ +void lbm_driver_antenna_configure(const struct device *dev, enum lbm_modem_mode mode); + +/** + * @brief Control a GPIO pin if it has been configured + * + * @param spec GPIO specification from devicetree + * @param value Value assigned to the pin. + * + * @return a value from gpio_pin_set_dt() + */ +static inline int lbm_optional_gpio_set_dt(const struct gpio_dt_spec *spec, int value) +{ + if (spec->port != NULL) { + return gpio_pin_set_dt(spec, value); + } + return 0; +} + +/* Common LBM implementation of the LoRa API */ +extern const struct lora_driver_api lbm_lora_api; diff --git a/drivers/lora/lora_basics_modem/lbm_sx126x.c b/drivers/lora/lora_basics_modem/lbm_sx126x.c new file mode 100644 index 0000000000000..10d9b425750e3 --- /dev/null +++ b/drivers/lora/lora_basics_modem/lbm_sx126x.c @@ -0,0 +1,519 @@ +/* + * Copyright (c) 2025 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ral.h" + +#include "ralf_sx126x.h" +#include "ral_sx126x_bsp.h" +#include "sx126x_hal.h" +#include "sx126x.h" + +#include "lbm_common.h" + +#define SX1261_TX_PWR_MAX 15 +#define SX1261_TX_PWR_MIN -17 +#define SX1262_TX_PWR_MAX 22 +#define SX1262_TX_PWR_MIN -9 + +enum sx126x_variant { + VARIANT_SX1261, + VARIANT_SX1262, +}; + +/* Copied from LBM sx126x.c */ +enum sx126x_commands { + /* Operational Modes Functions */ + SX126X_SET_SLEEP = 0x84, + SX126X_SET_STANDBY = 0x80, + SX126X_SET_FS = 0xC1, + SX126X_SET_TX = 0x83, + SX126X_SET_RX = 0x82, + SX126X_SET_STOP_TIMER_ON_PREAMBLE = 0x9F, + SX126X_SET_RX_DUTY_CYCLE = 0x94, + SX126X_SET_CAD = 0xC5, + SX126X_SET_TX_CONTINUOUS_WAVE = 0xD1, + SX126X_SET_TX_INFINITE_PREAMBLE = 0xD2, + SX126X_SET_REGULATOR_MODE = 0x96, + SX126X_CALIBRATE = 0x89, + SX126X_CALIBRATE_IMAGE = 0x98, + SX126X_SET_PA_CFG = 0x95, + SX126X_SET_RX_TX_FALLBACK_MODE = 0x93, + /* Registers and buffer Access */ + SX126X_WRITE_REGISTER = 0x0D, + SX126X_READ_REGISTER = 0x1D, + SX126X_WRITE_BUFFER = 0x0E, + SX126X_READ_BUFFER = 0x1E, + /* DIO and IRQ Control Functions */ + SX126X_SET_DIO_IRQ_PARAMS = 0x08, + SX126X_GET_IRQ_STATUS = 0x12, + SX126X_CLR_IRQ_STATUS = 0x02, + SX126X_SET_DIO2_AS_RF_SWITCH_CTRL = 0x9D, + SX126X_SET_DIO3_AS_TCXO_CTRL = 0x97, + /* RF Modulation and Packet-Related Functions */ + SX126X_SET_RF_FREQUENCY = 0x86, + SX126X_SET_PKT_TYPE = 0x8A, + SX126X_GET_PKT_TYPE = 0x11, + SX126X_SET_TX_PARAMS = 0x8E, + SX126X_SET_MODULATION_PARAMS = 0x8B, + SX126X_SET_PKT_PARAMS = 0x8C, + SX126X_SET_CAD_PARAMS = 0x88, + SX126X_SET_BUFFER_BASE_ADDRESS = 0x8F, + SX126X_SET_LORA_SYMB_NUM_TIMEOUT = 0xA0, + /* Communication Status Information */ + SX126X_GET_STATUS = 0xC0, + SX126X_GET_RX_BUFFER_STATUS = 0x13, + SX126X_GET_PKT_STATUS = 0x14, + SX126X_GET_RSSI_INST = 0x15, + SX126X_GET_STATS = 0x10, + SX126X_RESET_STATS = 0x00, + /* Miscellaneous */ + SX126X_GET_DEVICE_ERRORS = 0x17, + SX126X_CLR_DEVICE_ERRORS = 0x07, +}; + +struct lbm_sx126x_config { + struct lbm_lora_config_common lbm_common; + struct spi_dt_spec spi; + struct gpio_dt_spec reset; + struct gpio_dt_spec busy; + struct gpio_dt_spec dio1; + struct gpio_dt_spec ant_enable; + struct gpio_dt_spec tx_enable; + struct gpio_dt_spec rx_enable; + int dio3_tcxo_startup_delay_ms; + uint8_t dio3_tcxo_voltage; + bool dio2_rf_switch; + bool rx_boosted; + enum sx126x_variant variant; +}; + +struct lbm_sx126x_data { + struct lbm_lora_data_common lbm_common; + const struct device *dev; + struct gpio_callback dio1_callback; + bool asleep; +}; + +LOG_MODULE_DECLARE(lbm_driver, CONFIG_LORA_LOG_LEVEL); + +static bool sx126x_is_busy(const struct device *dev) +{ + const struct lbm_sx126x_config *config = dev->config; + + return gpio_pin_get_dt(&config->busy); +} + +static int sx126x_wait_device_ready(const struct device *dev, k_timeout_t timeout) +{ + k_timepoint_t expiry = sys_timepoint_calc(timeout); + + do { + if (!sx126x_is_busy(dev)) { + return 0; + } + k_sleep(K_MSEC(1)); + } while (!sys_timepoint_expired(expiry)); + return -EAGAIN; +} + +static int sx126x_ensure_device_ready(const struct device *dev, k_timeout_t timeout) +{ + const struct lbm_sx126x_config *config = dev->config; + struct lbm_sx126x_data *data = dev->data; + uint8_t get_status_cmd[2] = {SX126X_GET_STATUS, 0xFF}; + const struct spi_buf tx_bufs[] = { + { + .buf = (void *)get_status_cmd, + .len = sizeof(get_status_cmd), + }, + }; + const struct spi_buf_set tx_buf_set = {tx_bufs, .count = ARRAY_SIZE(tx_bufs)}; + int ret; + + if (data->asleep) { + LOG_DBG("SLEEP -> ACTIVE"); + /* Re-enable the DIO1 interrupt */ + gpio_pin_interrupt_configure_dt(&config->dio1, GPIO_INT_EDGE_TO_ACTIVE); + /* DO NOT USE sx126x_get_status as this will result in recursion */ + ret = spi_write_dt(&config->spi, &tx_buf_set); + if (ret) { + return ret; + } + } + ret = sx126x_wait_device_ready(dev, timeout); + data->asleep = false; + return ret; +} + +sx126x_hal_status_t sx126x_hal_write(const void *context, const uint8_t *command, + const uint16_t command_length, const uint8_t *data, + const uint16_t data_length) +{ + const struct device *dev = context; + const struct lbm_sx126x_config *config = dev->config; + struct lbm_sx126x_data *dev_data = dev->data; + const struct spi_buf tx_bufs[] = { + { + .buf = (void *)command, + .len = command_length, + }, + { + .buf = (void *)data, + .len = data_length, + }, + }; + const struct spi_buf_set tx_buf_set = {tx_bufs, .count = ARRAY_SIZE(tx_bufs)}; + int ret; + + LOG_DBG("CMD[0]=0x%02x CMD_LEN=%d DATA_LEN=%d", command[0], command_length, data_length); + + ret = sx126x_ensure_device_ready(dev, K_SECONDS(1)); + if (ret) { + return SX126X_HAL_STATUS_ERROR; + } + + ret = spi_write_dt(&config->spi, &tx_buf_set); + if (ret) { + return SX126X_HAL_STATUS_ERROR; + } + + if (command[0] == SX126X_SET_SLEEP) { + LOG_DBG("ACTIVE -> SLEEP"); + /* Disable the DIO1 interrupt to save power */ + (void)gpio_pin_interrupt_configure_dt(&config->dio1, GPIO_INT_DISABLE); + dev_data->asleep = true; + /* Wait for sleep to take effect */ + k_sleep(K_MSEC(1)); + } + + return SX126X_HAL_STATUS_OK; +} + +sx126x_hal_status_t sx126x_hal_read(const void *context, const uint8_t *command, + const uint16_t command_length, uint8_t *data, + const uint16_t data_length) +{ + const struct device *dev = context; + const struct lbm_sx126x_config *config = dev->config; + const struct spi_buf tx_bufs[] = { + { + .buf = (uint8_t *)command, + .len = command_length, + }, + { + .buf = NULL, + .len = data_length, + }, + }; + const struct spi_buf rx_bufs[] = { + { + .buf = NULL, + .len = command_length, + }, + { + .buf = data, + .len = data_length, + }, + }; + const struct spi_buf_set tx_buf_set = {.buffers = tx_bufs, .count = ARRAY_SIZE(tx_bufs)}; + const struct spi_buf_set rx_buf_set = {.buffers = rx_bufs, .count = ARRAY_SIZE(rx_bufs)}; + int ret; + + LOG_DBG("CMD[0]=0x%02x DATA_LEN=%d", command[0], data_length); + + ret = sx126x_ensure_device_ready(dev, K_SECONDS(1)); + if (ret) { + return SX126X_HAL_STATUS_ERROR; + } + + ret = spi_transceive_dt(&config->spi, &tx_buf_set, &rx_buf_set); + if (ret) { + return SX126X_HAL_STATUS_ERROR; + } + return SX126X_HAL_STATUS_OK; +} + +sx126x_hal_status_t sx126x_hal_reset(const void *context) +{ + const struct device *dev = context; + const struct lbm_sx126x_config *config = dev->config; + + LOG_DBG(""); + + gpio_pin_set_dt(&config->reset, 1); + k_sleep(K_MSEC(20)); + gpio_pin_set_dt(&config->reset, 0); + k_sleep(K_MSEC(10)); + + return SX126X_HAL_STATUS_OK; +} + +sx126x_hal_status_t sx126x_hal_wakeup(const void *context) +{ + const struct device *dev = context; + int ret; + + LOG_DBG(""); + + ret = sx126x_ensure_device_ready(dev, K_SECONDS(1)); + if (ret) { + return SX126X_HAL_STATUS_ERROR; + } + return SX126X_HAL_STATUS_OK; +} + +void ral_sx126x_bsp_get_reg_mode(const void *context, sx126x_reg_mod_t *reg_mode) +{ + /* Not currently described in devicetree */ + *reg_mode = SX126X_REG_MODE_DCDC; +} + +void ral_sx126x_bsp_get_rf_switch_cfg(const void *context, bool *dio2_is_set_as_rf_switch) +{ + const struct device *dev = context; + const struct lbm_sx126x_config *config = dev->config; + + *dio2_is_set_as_rf_switch = config->dio2_rf_switch; +} + +void ral_sx126x_bsp_get_tx_cfg(const void *context, + const ral_sx126x_bsp_tx_cfg_input_params_t *input_params, + ral_sx126x_bsp_tx_cfg_output_params_t *output_params) + +{ + const struct device *dev = context; + const struct lbm_sx126x_config *config = dev->config; + int16_t power = input_params->system_output_pwr_in_dbm; + + output_params->pa_ramp_time = SX126X_RAMP_40_US; + output_params->pa_cfg.pa_lut = 0x01; + + if (config->variant == VARIANT_SX1261) { + power = CLAMP(power, SX1261_TX_PWR_MIN, SX1261_TX_PWR_MAX); + output_params->pa_cfg.device_sel = 0x01; + output_params->chip_output_pwr_in_dbm_configured = power; + output_params->chip_output_pwr_in_dbm_expected = power; + if (power == 15) { + output_params->chip_output_pwr_in_dbm_configured = 14; + output_params->pa_cfg.pa_duty_cycle = 0x06; + } else { + output_params->pa_cfg.pa_duty_cycle = 0x04; + } + } else { + power = CLAMP(power, SX1262_TX_PWR_MIN, SX1262_TX_PWR_MAX); + output_params->pa_cfg.device_sel = 0x00; + output_params->pa_cfg.hp_max = 0x07; + output_params->pa_cfg.pa_duty_cycle = 0x04; + output_params->chip_output_pwr_in_dbm_configured = power; + output_params->chip_output_pwr_in_dbm_expected = power; + } +} + +void ral_sx126x_bsp_get_xosc_cfg(const void *context, ral_xosc_cfg_t *xosc_cfg, + sx126x_tcxo_ctrl_voltages_t *supply_voltage, + uint32_t *startup_time_in_tick) +{ + const struct device *dev = context; + const struct lbm_sx126x_config *config = dev->config; + + if (config->dio3_tcxo_voltage == UINT8_MAX) { + *xosc_cfg = RAL_XOSC_CFG_XTAL; + } else { + *xosc_cfg = RAL_XOSC_CFG_TCXO_RADIO_CTRL; + *supply_voltage = config->dio3_tcxo_voltage; + /* From datasheet: 1 tick = 15.625 us = 65536 Hz */ + *startup_time_in_tick = z_tmcvt_32(config->dio3_tcxo_startup_delay_ms, Z_HZ_ms, + 65536, true, true, false); + } +} + +void ral_sx126x_bsp_get_trim_cap(const void *context, uint8_t *trimming_cap_xta, + uint8_t *trimming_cap_xtb) +{ + /* Do nothing, let the driver choose the default values */ +} + +void ral_sx126x_bsp_get_rx_boost_cfg(const void *context, bool *rx_boost_is_activated) +{ + const struct device *dev = context; + const struct lbm_sx126x_config *config = dev->config; + + *rx_boost_is_activated = config->rx_boosted; +} + +void ral_sx126x_bsp_get_ocp_value(const void *context, uint8_t *ocp_in_step_of_2_5_ma) +{ + /* Do nothing, let the driver choose the default values */ +} + +void ral_sx126x_bsp_get_lora_cad_det_peak(const void *context, ral_lora_sf_t sf, ral_lora_bw_t bw, + ral_lora_cad_symbs_t nb_symbol, + uint8_t *in_out_cad_det_peak) +{ + /* The DetPeak value set in the sx126x Radio Abstraction Layer is too close to the + * sensitivity for BW500 and SF>=9 + */ + if (bw >= RAL_LORA_BW_500_KHZ) { + if (sf >= RAL_LORA_SF9) { + *in_out_cad_det_peak += 11; + } + } +} + +ral_status_t ral_sx126x_bsp_get_instantaneous_tx_power_consumption( + const void *context, const ral_sx126x_bsp_tx_cfg_output_params_t *tx_cfg_output_params, + sx126x_reg_mod_t radio_reg_mode, uint32_t *pwr_consumption_in_ua) +{ + /* Not yet implemented, not relevant for LoRa */ + return RAL_STATUS_UNSUPPORTED_FEATURE; +} + +ral_status_t ral_sx126x_bsp_get_instantaneous_gfsk_rx_power_consumption( + const void *context, sx126x_reg_mod_t radio_reg_mode, bool rx_boosted, + uint32_t *pwr_consumption_in_ua) +{ + /* Not yet implemented, not relevant for LoRa */ + return RAL_STATUS_UNSUPPORTED_FEATURE; +} + +ral_status_t ral_sx126x_bsp_get_instantaneous_lora_rx_power_consumption( + const void *context, sx126x_reg_mod_t radio_reg_mode, bool rx_boosted, + uint32_t *pwr_consumption_in_ua) +{ + /* Not yet implemented, not relevant for LoRa */ + return RAL_STATUS_UNSUPPORTED_FEATURE; +} + +void lbm_driver_antenna_configure(const struct device *dev, enum lbm_modem_mode mode) +{ + const struct lbm_sx126x_config *config = dev->config; + + /* Antenna / RF switch control */ + switch (mode) { + case MODE_SLEEP: + lbm_optional_gpio_set_dt(&config->ant_enable, 0); + lbm_optional_gpio_set_dt(&config->rx_enable, 0); + lbm_optional_gpio_set_dt(&config->tx_enable, 0); + break; + case MODE_TX: + case MODE_CW: + lbm_optional_gpio_set_dt(&config->rx_enable, 0); + lbm_optional_gpio_set_dt(&config->tx_enable, 1); + lbm_optional_gpio_set_dt(&config->ant_enable, 1); + break; + case MODE_RX: + case MODE_RX_ASYNC: + case MODE_CAD: + lbm_optional_gpio_set_dt(&config->tx_enable, 0); + lbm_optional_gpio_set_dt(&config->rx_enable, 1); + lbm_optional_gpio_set_dt(&config->ant_enable, 1); + break; + } +} + +static void sx126x_dio1_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins) +{ + struct lbm_sx126x_data *data = CONTAINER_OF(cb, struct lbm_sx126x_data, dio1_callback); + + LOG_DBG(""); + /* Submit work to process the interrupt immediately */ + k_work_schedule(&data->lbm_common.op_done_work, K_NO_WAIT); +} + +static int sx126x_init(const struct device *dev) +{ + const struct lbm_sx126x_config *config = dev->config; + struct lbm_sx126x_data *data = dev->data; + ral_status_t status; + int ret; + + /* Validate hardware is ready */ + if (!spi_is_ready_dt(&config->spi)) { + LOG_ERR("SPI bus %s not ready", config->spi.bus->name); + return -ENODEV; + } + + /* Setup GPIOs */ + if (gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_INACTIVE) || + gpio_pin_configure_dt(&config->busy, GPIO_INPUT) || + gpio_pin_configure_dt(&config->dio1, GPIO_INPUT)) { + LOG_ERR("GPIO configuration failed."); + return -EIO; + } + if (config->ant_enable.port) { + gpio_pin_configure_dt(&config->ant_enable, GPIO_OUTPUT_INACTIVE); + } + if (config->tx_enable.port) { + gpio_pin_configure_dt(&config->tx_enable, GPIO_OUTPUT_INACTIVE); + } + if (config->rx_enable.port) { + gpio_pin_configure_dt(&config->rx_enable, GPIO_OUTPUT_INACTIVE); + } + + /* Configure interrupts */ + gpio_init_callback(&data->dio1_callback, sx126x_dio1_callback, BIT(config->dio1.pin)); + if (gpio_add_callback(config->dio1.port, &data->dio1_callback) < 0) { + LOG_ERR("Could not set GPIO callback for DIO1 interrupt."); + return -EIO; + } + + /* Reset chip on boot */ + status = ral_reset(&config->lbm_common.ralf.ral); + if (status != RAL_STATUS_OK) { + LOG_ERR("Reset failure (%d)", status); + return -EIO; + } + + /* Wait for chip to be ready */ + ret = sx126x_ensure_device_ready(dev, K_MSEC(100)); + if (ret) { + LOG_ERR("Failed to return to ready after reset"); + return -EIO; + } + + /* Enable interrupts */ + gpio_pin_interrupt_configure_dt(&config->dio1, GPIO_INT_EDGE_TO_ACTIVE); + + /* Common structure init */ + return lbm_lora_common_init(dev); +} + +#define SX126X_DEFINE(node_id, sx_variant) \ + static const struct lbm_sx126x_config config_##node_id = { \ + .lbm_common.ralf = RALF_SX126X_INSTANTIATE(DEVICE_DT_GET(node_id)), \ + .spi = SPI_DT_SPEC_GET( \ + node_id, SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB, 0), \ + .reset = GPIO_DT_SPEC_GET(node_id, reset_gpios), \ + .busy = GPIO_DT_SPEC_GET(node_id, busy_gpios), \ + .dio1 = GPIO_DT_SPEC_GET(node_id, dio1_gpios), \ + .ant_enable = GPIO_DT_SPEC_GET_OR(node_id, antenna_enable_gpios, {0}), \ + .tx_enable = GPIO_DT_SPEC_GET_OR(node_id, tx_enable_gpios, {0}), \ + .rx_enable = GPIO_DT_SPEC_GET_OR(node_id, rx_enable_gpios, {0}), \ + .dio3_tcxo_startup_delay_ms = DT_PROP_OR(node_id, tcxo_power_startup_delay_ms, 0), \ + .dio3_tcxo_voltage = DT_PROP_OR(node_id, dio3_tcxo_voltage, UINT8_MAX), \ + .dio2_rf_switch = DT_PROP(node_id, dio2_tx_enable), \ + .rx_boosted = DT_PROP(node_id, rx_boosted), \ + .variant = sx_variant, \ + }; \ + static struct lbm_sx126x_data data_##node_id; \ + DEVICE_DT_DEFINE(node_id, sx126x_init, NULL, &data_##node_id, &config_##node_id, \ + POST_KERNEL, CONFIG_LORA_INIT_PRIORITY, &lbm_lora_api) + +#define SX1261_DEFINE(node_id) SX126X_DEFINE(node_id, VARIANT_SX1261) +#define SX1262_DEFINE(node_id) SX126X_DEFINE(node_id, VARIANT_SX1262) + +DT_FOREACH_STATUS_OKAY(semtech_sx1261, SX1261_DEFINE); +DT_FOREACH_STATUS_OKAY(semtech_sx1262, SX1262_DEFINE); diff --git a/drivers/lora/lora_basics_modem/lbm_sx127x.c b/drivers/lora/lora_basics_modem/lbm_sx127x.c new file mode 100644 index 0000000000000..434761502a560 --- /dev/null +++ b/drivers/lora/lora_basics_modem/lbm_sx127x.c @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2025 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ral.h" + +#include "ralf_sx127x.h" +#include "ral_sx127x_bsp.h" +#include "sx127x_hal.h" +#include "sx127x.h" + +#include "lbm_common.h" + +struct lbm_sx127x_config { + struct lbm_lora_config_common lbm_common; + struct spi_dt_spec spi; + struct gpio_dt_spec reset; + struct gpio_dt_spec ant_enable; + struct gpio_dt_spec rfi_enable; + struct gpio_dt_spec rfo_enable; + struct gpio_dt_spec pa_boost_enable; + struct gpio_dt_spec tcxo_power; + const struct gpio_dt_spec *dios; + uint8_t num_dios; +}; + +struct lbm_sx127x_dio_package { + uint8_t idx; + struct gpio_callback callback; + struct k_work worker; +}; + +struct lbm_sx127x_data { + struct lbm_lora_data_common lbm_common; + sx127x_t radio; + const struct device *dev; + struct lbm_sx127x_dio_package dio_packages[3]; + struct k_timer timer; + void (*timer_cb)(void *context); + bool asleep; +}; + +LOG_MODULE_DECLARE(lbm_driver, CONFIG_LORA_LOG_LEVEL); + +static int sx127x_transceive(const struct device *dev, uint8_t reg, bool write, void *data, + size_t length) +{ + const struct lbm_sx127x_config *config = dev->config; + const struct spi_buf buf[2] = { + { + .buf = ®, + .len = sizeof(reg), + }, + { + .buf = data, + .len = length, + }, + }; + struct spi_buf_set tx = { + .buffers = buf, + .count = ARRAY_SIZE(buf), + }; + + if (!write) { + const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)}; + + return spi_transceive_dt(&config->spi, &tx, &rx); + } + + return spi_write_dt(&config->spi, &tx); +} + +static int sx127x_write(const struct device *dev, uint8_t reg_addr, uint8_t *data, uint8_t len) +{ + return sx127x_transceive(dev, reg_addr | BIT(7), true, data, len); +} + +static int sx127x_read(const struct device *dev, uint8_t reg_addr, uint8_t *data, uint8_t len) +{ + return sx127x_transceive(dev, reg_addr, false, data, len); +} + +sx127x_radio_id_t sx127x_hal_get_radio_id(const sx127x_t *radio) +{ +#if defined(SX1272) + return SX127X_RADIO_ID_SX1272; +#elif defined(SX1276) + return SX127X_RADIO_ID_SX1276; +#else +#error "Please define the radio to be used" +#endif +} + +sx127x_hal_status_t sx127x_hal_write(const sx127x_t *radio, const uint16_t address, + const uint8_t *data, const uint16_t data_len) +{ + const struct device *dev = radio->hal_context; + int ret; + + LOG_DBG("ADDR=0x%02x DATA_LEN=%d", address, data_len); + + /* Only 7 bit addresses make any sense */ + __ASSERT_NO_MSG(address < BIT(7)); + + ret = sx127x_write(dev, address, (uint8_t *)data, data_len); + return ret == 0 ? SX127X_HAL_STATUS_OK : SX127X_HAL_STATUS_ERROR; +} + +sx127x_hal_status_t sx127x_hal_read(const sx127x_t *radio, const uint16_t address, uint8_t *data, + const uint16_t data_len) +{ + const struct device *dev = radio->hal_context; + int ret; + + LOG_DBG("ADDR=0x%02x DATA_LEN=%d", address, data_len); + + /* Only 7 bit addresses make any sense */ + __ASSERT_NO_MSG(address < BIT(7)); + + ret = sx127x_read(dev, address, data, data_len); + return ret == 0 ? SX127X_HAL_STATUS_OK : SX127X_HAL_STATUS_ERROR; +} + +void sx127x_hal_reset(const sx127x_t *radio) +{ + const struct device *dev = radio->hal_context; + const struct lbm_sx127x_config *config = dev->config; + + LOG_DBG(""); + + /* Assert reset pin for >= 100 us */ + gpio_pin_set_dt(&config->reset, 1); + k_sleep(K_MSEC(1)); + gpio_pin_set_dt(&config->reset, 0); + + /* Wait >= 5ms for modem to be ready again */ + k_sleep(K_MSEC(50)); +} + +uint32_t sx127x_hal_get_dio_1_pin_state(const sx127x_t *radio) +{ + const struct device *dev = radio->hal_context; + const struct lbm_sx127x_config *config = dev->config; + + return gpio_pin_get_dt(&config->dios[0]); +} + +static void sx127x_timer_expiry(struct k_timer *timer) +{ + struct lbm_sx127x_data *data = CONTAINER_OF(timer, struct lbm_sx127x_data, timer); + + LOG_DBG(""); + + /* Run the provided callback */ + data->timer_cb((void *)&data->radio); +} + +sx127x_hal_status_t sx127x_hal_timer_start(const sx127x_t *radio, const uint32_t time_in_ms, + void (*callback)(void *context)) +{ + const struct device *dev = radio->hal_context; + struct lbm_sx127x_data *data = dev->data; + + if (callback == NULL) { + return SX127X_HAL_STATUS_ERROR; + } + + LOG_DBG("Starting %d ms timer", time_in_ms); + + /* Update internal state */ + data->timer_cb = callback; + + /* Start the timer */ + k_timer_start(&data->timer, K_MSEC(time_in_ms), K_FOREVER); + return SX127X_HAL_STATUS_OK; +} + +sx127x_hal_status_t sx127x_hal_timer_stop(const sx127x_t *radio) +{ + const struct device *dev = radio->hal_context; + struct lbm_sx127x_data *data = dev->data; + + LOG_DBG(""); + + k_timer_stop(&data->timer); + return SX127X_HAL_STATUS_OK; +} + +bool sx127x_hal_timer_is_started(const sx127x_t *radio) +{ + const struct device *dev = radio->hal_context; + struct lbm_sx127x_data *data = dev->data; + + return k_timer_remaining_get(&data->timer) > 0; +} + +void ral_sx127x_bsp_get_tx_cfg(const void *context, + const ral_sx127x_bsp_tx_cfg_input_params_t *input_params, + ral_sx127x_bsp_tx_cfg_output_params_t *output_params) + +{ + int16_t power = input_params->system_output_pwr_in_dbm; +#if defined(SX1272) + output_params->pa_cfg.pa_select = SX127X_PA_SELECT_RFO; + output_params->pa_cfg.is_20_dbm_output_on = false; +#elif defined(SX1276) + if (input_params->freq_in_hz > RF_FREQUENCY_MID_BAND_THRESHOLD) { + output_params->pa_cfg.pa_select = SX127X_PA_SELECT_BOOST; + output_params->pa_cfg.is_20_dbm_output_on = true; + } else { + output_params->pa_cfg.pa_select = SX127X_PA_SELECT_RFO; + output_params->pa_cfg.is_20_dbm_output_on = false; + } +#endif + + if (output_params->pa_cfg.pa_select == SX127X_PA_SELECT_BOOST) { + if (output_params->pa_cfg.is_20_dbm_output_on == true) { + power = MAX(power, 5); + power = MIN(power, 20); + } else { + power = MAX(power, 2); + power = MIN(power, 17); + } + } else { +#if defined(SX1272) + power = MAX(power, -1); + power = MIN(power, 14); +#elif defined(SX1276) + power = MAX(power, -4); + power = MIN(power, 15); +#endif + } + + output_params->chip_output_pwr_in_dbm_configured = power; + output_params->chip_output_pwr_in_dbm_expected = power; + output_params->pa_ramp_time = SX127X_RAMP_40_US; +} + +void ral_sx127x_bsp_get_ocp_value(const void *context, uint8_t *ocp_trim_value) +{ + /* Do nothing, let the driver choose the default values */ +} + +ral_status_t ral_sx127x_bsp_get_instantaneous_tx_power_consumption( + const void *context, + const ral_sx127x_bsp_tx_cfg_output_params_t *tx_cfg_output_params_local, + uint32_t *pwr_consumption_in_ua) +{ + /* Not yet implemented, not relevant for LoRa */ + return RAL_STATUS_UNSUPPORTED_FEATURE; +} + +ral_status_t +ral_sx127x_bsp_get_instantaneous_gfsk_rx_power_consumption(const void *context, bool rx_boosted, + uint32_t *pwr_consumption_in_ua) +{ + /* Not yet implemented, not relevant for LoRa */ + return RAL_STATUS_UNSUPPORTED_FEATURE; +} + +ral_status_t +ral_sx127x_bsp_get_instantaneous_lora_rx_power_consumption(const void *context, bool rx_boosted, + uint32_t *pwr_consumption_in_ua) + +{ + /* Not yet implemented, not relevant for LoRa */ + return RAL_STATUS_UNSUPPORTED_FEATURE; +} + +void lbm_driver_antenna_configure(const struct device *dev, enum lbm_modem_mode mode) +{ + const struct lbm_sx127x_config *config = dev->config; + + /* Antenna / RF switch control */ + switch (mode) { + case MODE_SLEEP: + lbm_optional_gpio_set_dt(&config->pa_boost_enable, 0); + lbm_optional_gpio_set_dt(&config->ant_enable, 0); + lbm_optional_gpio_set_dt(&config->rfi_enable, 0); + lbm_optional_gpio_set_dt(&config->rfo_enable, 0); + break; + case MODE_TX: + case MODE_CW: + lbm_optional_gpio_set_dt(&config->rfi_enable, 0); + lbm_optional_gpio_set_dt(&config->pa_boost_enable, 1); + lbm_optional_gpio_set_dt(&config->rfo_enable, 1); + lbm_optional_gpio_set_dt(&config->ant_enable, 1); + break; + case MODE_RX: + case MODE_RX_ASYNC: + case MODE_CAD: + lbm_optional_gpio_set_dt(&config->pa_boost_enable, 0); + lbm_optional_gpio_set_dt(&config->rfo_enable, 0); + lbm_optional_gpio_set_dt(&config->rfi_enable, 1); + lbm_optional_gpio_set_dt(&config->ant_enable, 1); + break; + } +} + +static void sx127x_dio_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins) +{ + /* Get DIO container to find the DIO index */ + struct lbm_sx127x_dio_package *dio_package = + CONTAINER_OF(cb, struct lbm_sx127x_dio_package, callback); + uint8_t dio = dio_package->idx; + /* Get the parent data structure */ + struct lbm_sx127x_data *data = + CONTAINER_OF(dio_package, struct lbm_sx127x_data, dio_packages[dio]); + + LOG_DBG("%d", dio); + + __ASSERT_NO_MSG(dio <= 3); + /* Submit work to process the interrupt immediately */ + k_work_submit(&data->dio_packages[dio].worker); +} + +static void dio_work_function(struct k_work *work) +{ + /* Get DIO container to find the DIO index */ + struct lbm_sx127x_dio_package *dio_package = + CONTAINER_OF(work, struct lbm_sx127x_dio_package, worker); + uint8_t dio = dio_package->idx; + /* Get the parent data structure */ + struct lbm_sx127x_data *data = + CONTAINER_OF(dio_package, struct lbm_sx127x_data, dio_packages[dio]); + + switch (dio) { + case 0: + data->radio.dio_0_irq_handler(&data->radio); + break; + case 1: + data->radio.dio_1_irq_handler(&data->radio); + break; + case 2: + data->radio.dio_2_irq_handler(&data->radio); + break; + default: + LOG_WRN("Unknown DIO %d", dio); + } +} + +void sx127x_hal_dio_irq_attach(const sx127x_t *radio) +{ + /* Nothing to do here */ +} + +static void sx127x_irq_handler(void *irq_context) +{ + const struct device *dev = irq_context; + struct lbm_sx127x_data *data = dev->data; + + /* Finish the current task from the common worker */ + k_work_reschedule(&data->lbm_common.op_done_work, K_NO_WAIT); +} + +static int sx127x_driver_init(const struct device *dev) +{ + const struct lbm_sx127x_config *config = dev->config; + struct lbm_sx127x_data *data = dev->data; + ral_status_t status; + + data->radio.hal_context = dev; + data->radio.irq_handler_context = (void *)dev; + data->radio.irq_handler = sx127x_irq_handler; + k_timer_init(&data->timer, sx127x_timer_expiry, NULL); + + /* Validate hardware is ready */ + if (!spi_is_ready_dt(&config->spi)) { + LOG_ERR("SPI bus %s not ready", config->spi.bus->name); + return -ENODEV; + } + + /* Setup GPIOs */ + if (gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_INACTIVE)) { + LOG_ERR("GPIO configuration failed."); + return -EIO; + } + if (config->ant_enable.port) { + gpio_pin_configure_dt(&config->ant_enable, GPIO_OUTPUT_INACTIVE); + } + if (config->rfi_enable.port) { + gpio_pin_configure_dt(&config->rfi_enable, GPIO_OUTPUT_INACTIVE); + } + if (config->rfo_enable.port) { + gpio_pin_configure_dt(&config->rfo_enable, GPIO_OUTPUT_INACTIVE); + } + if (config->pa_boost_enable.port) { + gpio_pin_configure_dt(&config->pa_boost_enable, GPIO_OUTPUT_INACTIVE); + } + if (config->tcxo_power.port) { + gpio_pin_configure_dt(&config->tcxo_power, GPIO_OUTPUT_INACTIVE); + } + + /* Configure interrupts */ + for (int i = 0; i < MIN(config->num_dios, 3); i++) { + data->dio_packages[i].idx = i; + k_work_init(&data->dio_packages[i].worker, dio_work_function); + + gpio_pin_configure_dt(&config->dios[i], GPIO_INPUT); + gpio_init_callback(&data->dio_packages[i].callback, sx127x_dio_callback, + BIT(config->dios[i].pin)); + if (gpio_add_callback(config->dios[i].port, &data->dio_packages[i].callback) < 0) { + LOG_ERR("Could not set GPIO callback for DIO%d interrupt.", i); + return -EIO; + } + gpio_pin_interrupt_configure_dt(&config->dios[i], GPIO_INT_EDGE_RISING); + } + + /* Reset chip on boot */ + status = ral_reset(&config->lbm_common.ralf.ral); + if (status != RAL_STATUS_OK) { + LOG_ERR("Reset failure (%d)", status); + return -EIO; + } + + /* Common structure init */ + return lbm_lora_common_init(dev); +} + +#define SX127X_DIO_GPIO_ELEM(idx, node_id) GPIO_DT_SPEC_GET_BY_IDX(node_id, dio_gpios, idx) + +#define SX127X_DIO_GPIO_INIT(node_id) \ + LISTIFY(DT_PROP_LEN(node_id, dio_gpios), SX127X_DIO_GPIO_ELEM, (,), node_id) + +#define SX127X_DEFINE(node_id) \ + static const struct gpio_dt_spec sx127x_dios_##node_id[] = { \ + SX127X_DIO_GPIO_INIT(node_id)}; \ + BUILD_ASSERT(ARRAY_SIZE(sx127x_dios_##node_id) >= 1); \ + static struct lbm_sx127x_data data_##node_id; \ + static const struct lbm_sx127x_config config_##node_id = { \ + .lbm_common.ralf = RALF_SX127X_INSTANTIATE(&data_##node_id.radio), \ + .spi = SPI_DT_SPEC_GET( \ + node_id, SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB, 0), \ + .reset = GPIO_DT_SPEC_GET(node_id, reset_gpios), \ + .ant_enable = GPIO_DT_SPEC_GET_OR(node_id, antenna_enable_gpios, {0}), \ + .rfi_enable = GPIO_DT_SPEC_GET_OR(node_id, rfi_enable_gpios, {0}), \ + .rfo_enable = GPIO_DT_SPEC_GET_OR(node_id, rfo_enable_gpios, {0}), \ + .pa_boost_enable = GPIO_DT_SPEC_GET_OR(node_id, pa_boost_enable_gpios, {0}), \ + .tcxo_power = GPIO_DT_SPEC_GET_OR(node_id, tcxo_power_gpios, {0}), \ + .dios = sx127x_dios_##node_id, \ + .num_dios = ARRAY_SIZE(sx127x_dios_##node_id), \ + }; \ + DEVICE_DT_DEFINE(node_id, sx127x_driver_init, NULL, &data_##node_id, &config_##node_id, \ + POST_KERNEL, CONFIG_LORA_INIT_PRIORITY, &lbm_lora_api) + +DT_FOREACH_STATUS_OKAY(semtech_sx1272, SX127X_DEFINE); +DT_FOREACH_STATUS_OKAY(semtech_sx1276, SX127X_DEFINE); diff --git a/drivers/lora/loramac_node/CMakeLists.txt b/drivers/lora/loramac_node/CMakeLists.txt new file mode 100644 index 0000000000000..f37aa80dc1214 --- /dev/null +++ b/drivers/lora/loramac_node/CMakeLists.txt @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# LoRa drivers depend on the include directories exposed by the loramac-node +# library. Hence, if it exists then the source files are added to that otherwise +# a library with same name is created. +if(TARGET loramac-node) + set(ZEPHYR_CURRENT_LIBRARY loramac-node) +else() + zephyr_library_named(loramac-node) +endif() + +zephyr_library_sources_ifdef(CONFIG_HAS_SEMTECH_RADIO_DRIVERS hal_common.c) +zephyr_library_sources_ifdef(CONFIG_HAS_SEMTECH_RADIO_DRIVERS sx12xx_common.c) +zephyr_library_sources_ifdef(CONFIG_LORA_SX127X sx127x.c) + +if(CONFIG_LORA_SX126X OR CONFIG_LORA_STM32WL_SUBGHZ_RADIO) + zephyr_library_sources(sx126x.c) +endif() + +zephyr_library_sources_ifdef(CONFIG_LORA_SX126X sx126x_standalone.c) +zephyr_library_sources_ifdef(CONFIG_LORA_STM32WL_SUBGHZ_RADIO sx126x_stm32wl.c) +zephyr_library_sources_ifdef(CONFIG_LORA_RYLRXXX ../rylrxxx.c) diff --git a/drivers/lora/hal_common.c b/drivers/lora/loramac_node/hal_common.c similarity index 100% rename from drivers/lora/hal_common.c rename to drivers/lora/loramac_node/hal_common.c diff --git a/drivers/lora/sx126x.c b/drivers/lora/loramac_node/sx126x.c similarity index 100% rename from drivers/lora/sx126x.c rename to drivers/lora/loramac_node/sx126x.c diff --git a/drivers/lora/sx126x_common.h b/drivers/lora/loramac_node/sx126x_common.h similarity index 100% rename from drivers/lora/sx126x_common.h rename to drivers/lora/loramac_node/sx126x_common.h diff --git a/drivers/lora/sx126x_standalone.c b/drivers/lora/loramac_node/sx126x_standalone.c similarity index 100% rename from drivers/lora/sx126x_standalone.c rename to drivers/lora/loramac_node/sx126x_standalone.c diff --git a/drivers/lora/sx126x_stm32wl.c b/drivers/lora/loramac_node/sx126x_stm32wl.c similarity index 100% rename from drivers/lora/sx126x_stm32wl.c rename to drivers/lora/loramac_node/sx126x_stm32wl.c diff --git a/drivers/lora/sx127x.c b/drivers/lora/loramac_node/sx127x.c similarity index 100% rename from drivers/lora/sx127x.c rename to drivers/lora/loramac_node/sx127x.c diff --git a/drivers/lora/sx12xx_common.c b/drivers/lora/loramac_node/sx12xx_common.c similarity index 100% rename from drivers/lora/sx12xx_common.c rename to drivers/lora/loramac_node/sx12xx_common.c diff --git a/drivers/lora/sx12xx_common.h b/drivers/lora/loramac_node/sx12xx_common.h similarity index 100% rename from drivers/lora/sx12xx_common.h rename to drivers/lora/loramac_node/sx12xx_common.h diff --git a/drivers/mdio/mdio_nxp_enet.c b/drivers/mdio/mdio_nxp_enet.c index d71e3640cd434..b79e3e1502b86 100644 --- a/drivers/mdio/mdio_nxp_enet.c +++ b/drivers/mdio/mdio_nxp_enet.c @@ -216,6 +216,7 @@ static int nxp_enet_mdio_init(const struct device *dev) data->base = (ENET_Type *)DEVICE_MMIO_GET(config->module_dev); + k_busy_wait(100000); ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); if (ret) { return ret; diff --git a/drivers/mdio/mdio_sam.c b/drivers/mdio/mdio_sam.c index 54dd321e5507d..3fdf692ad53b6 100644 --- a/drivers/mdio/mdio_sam.c +++ b/drivers/mdio/mdio_sam.c @@ -169,12 +169,14 @@ static DEVICE_API(mdio, mdio_sam_driver_api) = { #define MDIO_SAM_CLOCK(n) \ COND_CODE_1(CONFIG_SOC_FAMILY_ATMEL_SAM, \ - (.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n),), () \ + (.clock_cfg = \ + SAM_DT_CLOCK_PMC_CFG(0, DT_INST_PARENT(n)),), \ + () \ ) #define MDIO_SAM_CONFIG(n) \ static const struct mdio_sam_dev_config mdio_sam_dev_config_##n = { \ - .regs = (Gmac *)DT_INST_REG_ADDR(n), \ + .regs = (Gmac *)DT_REG_ADDR(DT_INST_PARENT(n)), \ .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ MDIO_SAM_CLOCK(n) \ }; diff --git a/drivers/memc/Kconfig.max32_hpb b/drivers/memc/Kconfig.max32_hpb index b1976eb2439be..78b7fbc206bd1 100644 --- a/drivers/memc/Kconfig.max32_hpb +++ b/drivers/memc/Kconfig.max32_hpb @@ -8,3 +8,10 @@ config MEMC_MAX32_HPB select PINCTRL help Enable ADI MAX32 HyperBus controller. + + If you want to rely on the linker to place symbols in this memory + (using`zephyr_code_relocate() or Z_GENERIC_SECTION()), you have to + ensure this driver in initialized before KERNEL_INIT_PRIORITY_OBJECTS + (=30). In addition, this driver depends on a clock, so you have to + ensure the clock will be started before this driver as well (see + CLOCK_CONTROL_INIT_PRIORITY) diff --git a/drivers/memc/memc_max32_hpb.c b/drivers/memc/memc_max32_hpb.c index 5afc9e35e9a03..eeb3f57c4feac 100644 --- a/drivers/memc/memc_max32_hpb.c +++ b/drivers/memc/memc_max32_hpb.c @@ -136,5 +136,5 @@ static const struct memc_max32_hpb_config config = { .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), }; -DEVICE_DT_INST_DEFINE(0, memc_max32_hpb_init, NULL, NULL, &config, POST_KERNEL, +DEVICE_DT_INST_DEFINE(0, memc_max32_hpb_init, NULL, NULL, &config, PRE_KERNEL_1, CONFIG_MEMC_INIT_PRIORITY, NULL); diff --git a/drivers/mipi_dbi/mipi_dbi_spi.c b/drivers/mipi_dbi/mipi_dbi_spi.c index 85cba935dff3b..a62bb416c5f34 100644 --- a/drivers/mipi_dbi/mipi_dbi_spi.c +++ b/drivers/mipi_dbi/mipi_dbi_spi.c @@ -15,23 +15,6 @@ #include LOG_MODULE_REGISTER(mipi_dbi_spi, CONFIG_MIPI_DBI_LOG_LEVEL); -struct mipi_dbi_spi_config { - /* SPI hardware used to send data */ - const struct device *spi_dev; - /* Command/Data gpio */ - const struct gpio_dt_spec cmd_data; - /* Reset GPIO */ - const struct gpio_dt_spec reset; - /* Minimum transfer bits */ - const uint8_t xfr_min_bits; -}; - -struct mipi_dbi_spi_data { - struct k_mutex lock; - /* Used for 3 wire mode */ - uint16_t spi_byte; -}; - /* Expands to 1 if the node does not have the `write-only` property */ #define MIPI_DBI_SPI_WRITE_ONLY_ABSENT(n) (!DT_INST_PROP(n, write_only)) | @@ -42,6 +25,16 @@ struct mipi_dbi_spi_data { #define MIPI_DBI_SPI_READ_REQUIRED DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_SPI_WRITE_ONLY_ABSENT) 0 uint32_t var = MIPI_DBI_SPI_READ_REQUIRED; +/* Expands to 1 if the node configures a gpio in the `te-gpios` property */ +#define MIPI_DBI_SPI_TE_GPIOS_PRESENT(n) DT_INST_NODE_HAS_PROP(n, te_gpios) | + +/* This macro will evaluate to 1 if any of the nodes with zephyr,mipi-dbi-spi + * has a `te-gpios` property. The intention here is to allow the entire + * configure_te and mipi_dbi_spi_te_cb functions to be optimized out when it + * is not needed. + */ +#define MIPI_DBI_SPI_TE_REQUIRED DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_SPI_TE_GPIOS_PRESENT) 0 + /* Expands to 1 if the node does reflect the enum in `xfr-min-bits` property */ #define MIPI_DBI_SPI_XFR_8BITS(n) (DT_INST_STRING_UPPER_TOKEN(n, xfr_min_bits) \ == MIPI_DBI_SPI_XFR_8BIT) | @@ -64,6 +57,53 @@ uint32_t var = MIPI_DBI_SPI_READ_REQUIRED; */ #define MIPI_DBI_DC_BIT BIT(8) +struct mipi_dbi_spi_config { + /* SPI hardware used to send data */ + const struct device *spi_dev; + /* Command/Data gpio */ + const struct gpio_dt_spec cmd_data; + /* Tearing Effect GPIO */ + const struct gpio_dt_spec tearing_effect; + /* Reset GPIO */ + const struct gpio_dt_spec reset; + /* Minimum transfer bits */ + const uint8_t xfr_min_bits; +}; + +struct mipi_dbi_spi_data { + struct k_mutex lock; +#if MIPI_DBI_SPI_TE_REQUIRED + struct k_sem te_signal; + k_timeout_t te_delay; + atomic_t in_active_area; + struct gpio_callback te_cb_data; +#endif + /* Used for 3 wire mode */ + uint16_t spi_byte; +}; + +#if MIPI_DBI_SPI_TE_REQUIRED + +static void mipi_dbi_spi_te_cb(const struct device *dev, + struct gpio_callback *cb, + uint32_t pins) +{ + ARG_UNUSED(dev); + ARG_UNUSED(pins); + + struct mipi_dbi_spi_data *data = CONTAINER_OF(cb, + struct mipi_dbi_spi_data, te_cb_data); + + /* Open frame window */ + if (!atomic_cas(&data->in_active_area, 0, 1)) { + return; + } + + k_sem_give(&data->te_signal); +} + +#endif /* MIPI_DBI_SPI_TE_REQUIRED */ + static inline int mipi_dbi_spi_write_helper_3wire(const struct device *dev, const struct mipi_dbi_config *dbi_config, @@ -323,8 +363,32 @@ static int mipi_dbi_spi_write_display(const struct device *dev, { ARG_UNUSED(pixfmt); - return mipi_dbi_spi_write_helper(dev, dbi_config, false, 0x0, - framebuf, desc->buf_size); + int ret = 0; + +#if MIPI_DBI_SPI_TE_REQUIRED + struct mipi_dbi_spi_data *data = dev->data; + + /* Wait for TE signal, otherwise transferring can begin */ + if (!atomic_get(&data->in_active_area)) { + ret = k_sem_take(&data->te_signal, K_FOREVER); + if (ret < 0) { + return ret; + } + k_sleep(data->te_delay); + } +#endif + + ret = mipi_dbi_spi_write_helper(dev, dbi_config, false, 0x0, + framebuf, desc->buf_size); + +#if MIPI_DBI_SPI_TE_REQUIRED + /* End of frame reset */ + if (!desc->frame_incomplete) { + atomic_set(&data->in_active_area, 0); + } +#endif + + return ret; } #if MIPI_DBI_SPI_READ_REQUIRED @@ -507,6 +571,66 @@ static int mipi_dbi_spi_release(const struct device *dev, return spi_release(config->spi_dev, &dbi_config->config); } +#if MIPI_DBI_SPI_TE_REQUIRED + +static int mipi_dbi_spi_configure_te(const struct device *dev, + uint8_t edge, + k_timeout_t delay_us) +{ + const struct mipi_dbi_spi_config *config = dev->config; + struct mipi_dbi_spi_data *data = dev->data; + int ret = 0; + + if (edge == MIPI_DBI_TE_NO_EDGE) { + /* No configuration */ + return 0; + } + + if (!mipi_dbi_has_pin(&config->tearing_effect)) { + return -ENOTSUP; + } + + if (!gpio_is_ready_dt(&config->tearing_effect)) { + return -ENODEV; + } + + ret = gpio_pin_configure_dt(&config->tearing_effect, GPIO_INPUT); + if (ret < 0) { + LOG_ERR("Could not configure Tearing Effect GPIO (%d)", ret); + return ret; + } + + if (edge == MIPI_DBI_TE_RISING_EDGE) { + ret = gpio_pin_interrupt_configure_dt(&config->tearing_effect, + GPIO_INT_EDGE_RISING); + } else if (edge == MIPI_DBI_TE_FALLING_EDGE) { + ret = gpio_pin_interrupt_configure_dt(&config->tearing_effect, + GPIO_INT_EDGE_FALLING); + } + if (ret < 0) { + LOG_ERR("Could not configure Tearing Effect GPIO EXT interrupt (%d)", ret); + return ret; + } + + gpio_init_callback(&data->te_cb_data, mipi_dbi_spi_te_cb, + BIT(config->tearing_effect.pin)); + + ret = gpio_add_callback(config->tearing_effect.port, + &data->te_cb_data); + if (ret < 0) { + LOG_ERR("Could not add Tearing Effect GPIO callback (%d)", ret); + return ret; + } + + data->te_delay = delay_us; + atomic_set(&data->in_active_area, 0); + k_sem_init(&data->te_signal, 0, 1); + + return ret; +} + +#endif /* MIPI_DBI_SPI_TE_REQUIRED */ + static int mipi_dbi_spi_init(const struct device *dev) { const struct mipi_dbi_spi_config *config = dev->config; @@ -553,6 +677,9 @@ static DEVICE_API(mipi_dbi, mipi_dbi_spi_driver_api) = { #if MIPI_DBI_SPI_READ_REQUIRED .command_read = mipi_dbi_spi_command_read, #endif +#if MIPI_DBI_SPI_TE_REQUIRED + .configure_te = mipi_dbi_spi_configure_te, +#endif }; #define MIPI_DBI_SPI_INIT(n) \ @@ -561,6 +688,7 @@ static DEVICE_API(mipi_dbi, mipi_dbi_spi_driver_api) = { .spi_dev = DEVICE_DT_GET( \ DT_INST_PHANDLE(n, spi_dev)), \ .cmd_data = GPIO_DT_SPEC_INST_GET_OR(n, dc_gpios, {}), \ + .tearing_effect = GPIO_DT_SPEC_INST_GET_OR(n, te_gpios, {}), \ .reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \ .xfr_min_bits = DT_INST_STRING_UPPER_TOKEN(n, xfr_min_bits) \ }; \ diff --git a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c index aaf3f0d447480..bf7462c5e05cb 100644 --- a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c +++ b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c @@ -15,7 +15,9 @@ #include #include -#if DT_ANY_INST_HAS_BOOL_STATUS_OKAY(enable_secure) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) +#if (DT_ANY_INST_HAS_BOOL_STATUS_OKAY(enable_secure) || \ + DT_ANY_INST_HAS_BOOL_STATUS_OKAY(enable_dma_secure)) && \ + !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) #include #endif @@ -25,6 +27,7 @@ struct nordic_vpr_launcher_config { NRF_VPR_Type *vpr; uintptr_t exec_addr; bool enable_secure; + bool enable_dma_secure; #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory) uintptr_t src_addr; size_t size; @@ -53,12 +56,21 @@ static int nordic_vpr_launcher_init(const struct device *dev) } #endif -#if DT_ANY_INST_HAS_BOOL_STATUS_OKAY(enable_secure) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) +#if DT_ANY_INST_HAS_BOOL_STATUS_OKAY(enable_secure) if (config->enable_secure) { nrf_spu_periph_perm_secattr_set(NRF_SPU00, nrf_address_slave_get((uint32_t)config->vpr), true); } +#endif +#if DT_ANY_INST_HAS_BOOL_STATUS_OKAY(enable_dma_secure) + if (config->enable_dma_secure) { + nrf_spu_periph_perm_dmasec_set(NRF_SPU00, + nrf_address_slave_get((uint32_t)config->vpr), + true); + } +#endif #endif LOG_DBG("Launching VPR (%p) from %p", config->vpr, (void *)config->exec_addr); nrf_vpr_initpc_set(config->vpr, config->exec_addr); @@ -86,6 +98,7 @@ static int nordic_vpr_launcher_init(const struct device *dev) IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, execution_memory), \ (.exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)),)) \ .enable_secure = DT_INST_PROP(inst, enable_secure), \ + .enable_dma_secure = DT_INST_PROP(inst, enable_dma_secure), \ IF_ENABLED(NEEDS_COPYING(inst), \ (.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \ .size = DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)),))}; \ diff --git a/drivers/misc/pio_rpi_pico/pio_rpi_pico.c b/drivers/misc/pio_rpi_pico/pio_rpi_pico.c index 5182cdf32b0ea..1dd3ec0e690ce 100644 --- a/drivers/misc/pio_rpi_pico/pio_rpi_pico.c +++ b/drivers/misc/pio_rpi_pico/pio_rpi_pico.c @@ -34,13 +34,6 @@ int pio_rpi_pico_allocate_sm(const struct device *dev, size_t *sm) return 0; } -PIO pio_rpi_pico_get_pio(const struct device *dev) -{ - const struct pio_rpi_pico_config *config = dev->config; - - return config->pio; -} - static int pio_rpi_pico_init(const struct device *dev) { const struct pio_rpi_pico_config *config = dev->config; diff --git a/drivers/misc/stm32n6_axisram/Kconfig b/drivers/misc/stm32n6_axisram/Kconfig index b6c2493ac6e1d..7d583aec7ce44 100644 --- a/drivers/misc/stm32n6_axisram/Kconfig +++ b/drivers/misc/stm32n6_axisram/Kconfig @@ -4,4 +4,7 @@ config STM32N6_AXISRAM bool select USE_STM32_HAL_RAMCFG - default y if DT_HAS_ST_STM32N6_RAMCFG_ENABLED + default y if $(dt_nodelabel_enabled,axisram3) || \ + $(dt_nodelabel_enabled,axisram4) || \ + $(dt_nodelabel_enabled,axisram5) || \ + $(dt_nodelabel_enabled,axisram6) diff --git a/drivers/mspi/Kconfig.dw b/drivers/mspi/Kconfig.dw index d429cff044c01..06d2e09c8af19 100644 --- a/drivers/mspi/Kconfig.dw +++ b/drivers/mspi/Kconfig.dw @@ -8,6 +8,7 @@ config MSPI_DW depends on DT_HAS_SNPS_DESIGNWARE_SSI_ENABLED select PINCTRL if $(dt_compat_any_has_prop,$(DT_COMPAT_SNPS_DESIGNWARE_SSI),pinctrl-0) imply MSPI_XIP + imply MSPI_TIMING if MSPI_DW diff --git a/drivers/mspi/mspi_dw.c b/drivers/mspi/mspi_dw.c index 0c6d8d1516617..66f257839aa46 100644 --- a/drivers/mspi/mspi_dw.c +++ b/drivers/mspi/mspi_dw.c @@ -691,7 +691,6 @@ static int _api_dev_config(const struct device *dev, } if (param_mask & MSPI_DEVICE_CONFIG_DATA_RATE) { - /* TODO: add support for DDR */ dev_data->spi_ctrlr0 &= ~(SPI_CTRLR0_SPI_DDR_EN_BIT | SPI_CTRLR0_INST_DDR_EN_BIT); switch (cfg->data_rate) { @@ -712,10 +711,10 @@ static int _api_dev_config(const struct device *dev, } if (param_mask & MSPI_DEVICE_CONFIG_DQS) { - /* TODO: add support for DQS */ + dev_data->spi_ctrlr0 &= ~SPI_CTRLR0_SPI_RXDS_EN_BIT; + if (cfg->dqs_enable) { - LOG_ERR("DQS line is not supported."); - return -ENOTSUP; + dev_data->spi_ctrlr0 |= SPI_CTRLR0_SPI_RXDS_EN_BIT; } } @@ -1193,6 +1192,22 @@ static int api_transceive(const struct device *dev, return rc; } +#if defined(CONFIG_MSPI_TIMING) +static int api_timing_config(const struct device *dev, + const struct mspi_dev_id *dev_id, + const uint32_t param_mask, void *cfg) +{ + struct mspi_dw_data *dev_data = dev->data; + struct mspi_dw_timing_cfg *config = cfg; + + if (param_mask & MSPI_DW_RX_TIMING_CFG) { + dev_data->rx_sample_dly = config->rx_sample_dly; + return 0; + } + return -ENOTSUP; +} +#endif /* defined(CONFIG_MSPI_TIMING) */ + #if defined(CONFIG_MSPI_XIP) static int _api_xip_config(const struct device *dev, const struct mspi_dev_id *dev_id, @@ -1299,20 +1314,6 @@ static int _api_xip_config(const struct device *dev, return 0; } -static int api_timing_config(const struct device *dev, - const struct mspi_dev_id *dev_id, - const uint32_t param_mask, void *cfg) -{ - struct mspi_dw_data *dev_data = dev->data; - struct mspi_dw_timing_cfg *config = cfg; - - if (param_mask & MSPI_DW_RX_TIMING_CFG) { - dev_data->rx_sample_dly = config->rx_sample_dly; - return 0; - } - return -ENOTSUP; -} - static int api_xip_config(const struct device *dev, const struct mspi_dev_id *dev_id, const struct mspi_xip_cfg *cfg) @@ -1461,7 +1462,9 @@ static DEVICE_API(mspi, drv_api) = { .dev_config = api_dev_config, .get_channel_status = api_get_channel_status, .transceive = api_transceive, +#if defined(CONFIG_MSPI_TIMING) .timing_config = api_timing_config, +#endif #if defined(CONFIG_MSPI_XIP) .xip_config = api_xip_config, #endif diff --git a/drivers/pinctrl/pinctrl_esp32.c b/drivers/pinctrl/pinctrl_esp32.c index 4ed39229d5625..eacf62a668135 100644 --- a/drivers/pinctrl/pinctrl_esp32.c +++ b/drivers/pinctrl/pinctrl_esp32.c @@ -23,8 +23,8 @@ #define in in.data #define out_w1ts out_w1ts.val #define out_w1tc out_w1tc.val -#elif CONFIG_SOC_SERIES_ESP32C6 -/* gpio structs in esp32c6 are also different */ +#elif defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) +/* gpio structs in esp32c6/h2 are also different */ #define out out.out_data_orig #define in in.in_data_next #define out_w1ts out_w1ts.val diff --git a/drivers/power_domain/power_domain_nrfs_gdpwr.c b/drivers/power_domain/power_domain_nrfs_gdpwr.c index 64e83f5774bc1..16343293be583 100644 --- a/drivers/power_domain/power_domain_nrfs_gdpwr.c +++ b/drivers/power_domain/power_domain_nrfs_gdpwr.c @@ -26,7 +26,7 @@ static const struct device *const domains[] = { }; struct domain_data { - bool off; + bool on; bool synced; }; @@ -104,7 +104,7 @@ static int manager_set_domain(const struct device *dev, bool on) * is ready. */ ret = 0; - dev_data->off = !on; + dev_data->on = on; } if (ret == 0) { @@ -134,9 +134,9 @@ static int manager_sync_domain_locked(const struct device *dev) /* * Power domains initialize ON so we only need to send a request - * if the expected state of the power domain is OFF. + * if the expected state of the power domain is not ON. */ - if (dev_data->off) { + if (!dev_data->on) { return manager_set_domain_locked(dev_config->domain, false); } @@ -261,7 +261,7 @@ static int domain_init(const struct device *dev) _CONCAT(GDPWR_GD_, DT_NODE_FULL_NAME_UPPER_TOKEN(node)) #define DOMAIN_DEFINE(node) \ - static struct domain_config DOMAIN_NODE_SYMNAME(node, data); \ + static struct domain_data DOMAIN_NODE_SYMNAME(node, data); \ static const struct domain_config DOMAIN_NODE_SYMNAME(node, config) = { \ .domain = DOMAIN_NODE_TO_GDPWR_ENUM(node), \ }; \ diff --git a/drivers/pwm/CMakeLists.txt b/drivers/pwm/CMakeLists.txt index b94be264f714d..c976a24b44c44 100644 --- a/drivers/pwm/CMakeLists.txt +++ b/drivers/pwm/CMakeLists.txt @@ -55,7 +55,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB106X pwm_ene_kb106x.c) zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB1200 pwm_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RA pwm_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RX_MTU pwm_renesas_rx_mtu.c) -zephyr_library_sources_ifdef(CONFIG_PWM_INFINEON_CAT1 pwm_ifx_cat1.c) +zephyr_library_sources_ifdef(CONFIG_PWM_INFINEON_TCPWM pwm_ifx_tcpwm.c) zephyr_library_sources_ifdef(CONFIG_PWM_FAKE pwm_fake.c) zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RZ_GPT pwm_renesas_rz_gpt.c) zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RZ_MTU pwm_renesas_rz_mtu.c) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 6b8298a46b3c3..f0db0f8b10c16 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -126,7 +126,7 @@ source "drivers/pwm/Kconfig.renesas_ra" source "drivers/pwm/Kconfig.renesas_rx_mtu" -source "drivers/pwm/Kconfig.ifx_cat1" +source "drivers/pwm/Kconfig.ifx_tcpwm" source "drivers/pwm/Kconfig.fake" diff --git a/drivers/pwm/Kconfig.ifx_cat1 b/drivers/pwm/Kconfig.ifx_cat1 deleted file mode 100644 index d8c12ac411f85..0000000000000 --- a/drivers/pwm/Kconfig.ifx_cat1 +++ /dev/null @@ -1,16 +0,0 @@ -# Infineon CAT1 PWM configuration options - -# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config PWM_INFINEON_CAT1 - bool "Infineon CAT1 PWM driver" - default y - depends on DT_HAS_INFINEON_CAT1_PWM_ENABLED - depends on SOC_FAMILY_INFINEON_CAT1B - select USE_INFINEON_PWM - select PINCTRL - help - This option enables the PWM driver for Infineon CAT1 family. diff --git a/drivers/pwm/Kconfig.ifx_tcpwm b/drivers/pwm/Kconfig.ifx_tcpwm new file mode 100644 index 0000000000000..f8cf2b4829abe --- /dev/null +++ b/drivers/pwm/Kconfig.ifx_tcpwm @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Infineon TCPWM PWM configuration options + +config PWM_INFINEON_TCPWM + bool "Infineon TCPWM driver" + default y + depends on DT_HAS_INFINEON_TCPWM_PWM_ENABLED + select USE_INFINEON_PWM + select PINCTRL + help + This option enables the PWM driver in the Infineon TCPWM peripheral. diff --git a/drivers/pwm/pwm_ifx_cat1.c b/drivers/pwm/pwm_ifx_cat1.c deleted file mode 100644 index 25c9395d0e560..0000000000000 --- a/drivers/pwm/pwm_ifx_cat1.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief ADC driver for Infineon CAT1 MCU family. - */ - -#define DT_DRV_COMPAT infineon_cat1_pwm - -#include -#include - -#include -#include -#include -#include -#include - -#include -LOG_MODULE_REGISTER(pwm_ifx_cat1, CONFIG_PWM_LOG_LEVEL); - -#define PWM_REG_BASE TCPWM0 - -struct ifx_cat1_pwm_data { - uint32_t pwm_num; -}; - -struct ifx_cat1_pwm_config { - TCPWM_GRP_CNT_Type *reg_addr; - const struct pinctrl_dev_config *pcfg; - bool resolution_32_bits; - cy_en_divider_types_t divider_type; - uint32_t divider_sel; - uint32_t divider_val; -}; - -static int ifx_cat1_pwm_init(const struct device *dev) -{ - struct ifx_cat1_pwm_data *data = dev->data; - const struct ifx_cat1_pwm_config *config = dev->config; - cy_en_tcpwm_status_t status; - int ret; - uint32_t addr_offset = (uint32_t)config->reg_addr - TCPWM0_BASE; - uint32_t clk_connection; - - const cy_stc_tcpwm_pwm_config_t pwm_config = { - .pwmMode = CY_TCPWM_PWM_MODE_PWM, - .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, - .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, - .runMode = CY_TCPWM_PWM_CONTINUOUS, - .countInputMode = CY_TCPWM_INPUT_LEVEL, - .countInput = CY_TCPWM_INPUT_1, - .enableCompareSwap = true, - .enablePeriodSwap = true, - }; - - /* Configure PWM clock */ - Cy_SysClk_PeriphDisableDivider(config->divider_type, config->divider_sel); - Cy_SysClk_PeriphSetDivider(config->divider_type, config->divider_sel, config->divider_val); - Cy_SysClk_PeriphEnableDivider(config->divider_type, config->divider_sel); - - /* This is very specific to the cyw920829m2evk_02 and may need to be modified - * for other boards. - */ - if (addr_offset < sizeof(TCPWM_GRP_Type)) { - clk_connection = - PCLK_TCPWM0_CLOCK_COUNTER_EN0 + (addr_offset / sizeof(TCPWM_GRP_CNT_Type)); - } else { - addr_offset -= sizeof(TCPWM_GRP_Type); - clk_connection = PCLK_TCPWM0_CLOCK_COUNTER_EN256 + - (addr_offset / sizeof(TCPWM_GRP_CNT_Type)); - } - Cy_SysClk_PeriphAssignDivider(clk_connection, config->divider_type, config->divider_sel); - - ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (ret < 0) { - return ret; - } - - /* Configure the TCPWM to be a PWM */ - data->pwm_num += addr_offset / sizeof(TCPWM_GRP_CNT_Type); - status = Cy_TCPWM_PWM_Init(PWM_REG_BASE, data->pwm_num, &pwm_config); - if (status != CY_TCPWM_SUCCESS) { - return -ENOTSUP; - } - - return 0; -} - -static int ifx_cat1_pwm_set_cycles(const struct device *dev, uint32_t channel, - uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags) -{ - struct ifx_cat1_pwm_data *data = dev->data; - const struct ifx_cat1_pwm_config *config = dev->config; - - if (!config->resolution_32_bits && - ((period_cycles > UINT16_MAX) || (pulse_cycles > UINT16_MAX))) { - /* 16-bit resolution */ - if (period_cycles > UINT16_MAX) { - LOG_ERR("Period cycles more than 16-bits (%u)", period_cycles); - } - if (pulse_cycles > UINT16_MAX) { - LOG_ERR("Pulse cycles more than 16-bits (%u)", pulse_cycles); - } - return -EINVAL; - } - - if ((period_cycles == 0) || (pulse_cycles == 0)) { - Cy_TCPWM_PWM_Disable(PWM_REG_BASE, data->pwm_num); - } else { - /* Update period and compare values using buffer registers so the new values - * take effect on the next TC event - */ - Cy_TCPWM_PWM_SetPeriod1(PWM_REG_BASE, data->pwm_num, period_cycles); - Cy_TCPWM_PWM_SetCompare0BufVal(PWM_REG_BASE, data->pwm_num, pulse_cycles); - - /* Trigger the swap by writing to the SW trigger command register. */ - Cy_TCPWM_TriggerCaptureOrSwap_Single(PWM_REG_BASE, data->pwm_num); - - if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_INVERTED) { - config->reg_addr->CTRL &= ~TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk; - config->reg_addr->CTRL |= _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE, - CY_TCPWM_PWM_INVERT_ENABLE); - } - - /* TODO: Add 2-bit field to top 8 bits of pwm_flags_t to set this. - * #define CY_TCPWM_PWM_OUTPUT_HIGHZ (0U) - * #define CY_TCPWM_PWM_OUTPUT_RETAIN (1U) - * #define CY_TCPWM_PWM_OUTPUT_LOW (2U) - * #define CY_TCPWM_PWM_OUTPUT_HIGH (3U) - * if ((flags & __) == __) { - * config->reg_addr->CTRL &= ~TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk; - * config->reg_addr->CTRL |= _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE, - * __); - * } - */ - - /* Enable the TCPWM for PWM mode of operation */ - Cy_TCPWM_PWM_Enable(PWM_REG_BASE, data->pwm_num); - - /* Start the TCPWM block */ - Cy_TCPWM_TriggerStart_Single(PWM_REG_BASE, data->pwm_num); - } - - return 0; -} - -static int ifx_cat1_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel, - uint64_t *cycles) -{ - const struct ifx_cat1_pwm_config *config = dev->config; - - *cycles = Cy_SysClk_PeriphGetFrequency(config->divider_type, config->divider_sel); - - return 0; -} - -static DEVICE_API(pwm, ifx_cat1_pwm_api) = { - .set_cycles = ifx_cat1_pwm_set_cycles, - .get_cycles_per_sec = ifx_cat1_pwm_get_cycles_per_sec, -}; - -#define INFINEON_CAT1_PWM_INIT(n) \ - PINCTRL_DT_INST_DEFINE(n); \ - \ - static struct ifx_cat1_pwm_data pwm_cat1_data_##n; \ - \ - static struct ifx_cat1_pwm_config pwm_cat1_config_##n = { \ - .reg_addr = (TCPWM_GRP_CNT_Type *)DT_INST_REG_ADDR(n), \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ - .resolution_32_bits = (DT_INST_PROP(n, resolution) == 32) ? true : false, \ - .divider_type = DT_INST_PROP(n, divider_type), \ - .divider_sel = DT_INST_PROP(n, divider_sel), \ - .divider_val = DT_INST_PROP(n, divider_val), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, ifx_cat1_pwm_init, NULL, &pwm_cat1_data_##n, \ - &pwm_cat1_config_##n, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \ - &ifx_cat1_pwm_api); - -DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_PWM_INIT) diff --git a/drivers/pwm/pwm_ifx_tcpwm.c b/drivers/pwm/pwm_ifx_tcpwm.c new file mode 100644 index 0000000000000..c4214ddc890cc --- /dev/null +++ b/drivers/pwm/pwm_ifx_tcpwm.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * PWM driver for Infineon MCUs using the TCPWM block. + */ + +#define DT_DRV_COMPAT infineon_tcpwm_pwm + +#include +#include +#include +#include + +#include +#include +#include + +#include +LOG_MODULE_REGISTER(pwm_ifx_tcpwm, CONFIG_PWM_LOG_LEVEL); + +struct ifx_tcpwm_pwm_config { + TCPWM_GRP_CNT_Type *reg_base; + const struct pinctrl_dev_config *pcfg; + bool resolution_32_bits; + cy_en_divider_types_t divider_type; + uint32_t divider_sel; + uint32_t divider_val; + uint32_t tcpwm_index; +}; + +static int ifx_tcpwm_pwm_init(const struct device *dev) +{ + const struct ifx_tcpwm_pwm_config *config = dev->config; + cy_en_tcpwm_status_t status; + int ret; + uint32_t clk_connection; + + const cy_stc_tcpwm_pwm_config_t pwm_config = { + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .countInputMode = CY_TCPWM_INPUT_LEVEL, + .countInput = CY_TCPWM_INPUT_1, + .enableCompareSwap = true, + .enablePeriodSwap = true, + }; + + /* Configure PWM clock */ + Cy_SysClk_PeriphDisableDivider(config->divider_type, config->divider_sel); + Cy_SysClk_PeriphSetDivider(config->divider_type, config->divider_sel, config->divider_val); + Cy_SysClk_PeriphEnableDivider(config->divider_type, config->divider_sel); + + /* Calculate clock connection based on TCPWM index */ + if (config->resolution_32_bits) { + clk_connection = PCLK_TCPWM0_CLOCK_COUNTER_EN0 + config->tcpwm_index; + } else { + clk_connection = PCLK_TCPWM0_CLOCK_COUNTER_EN256 + config->tcpwm_index; + } + + Cy_SysClk_PeriphAssignDivider(clk_connection, config->divider_type, config->divider_sel); + + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + /* Configure the TCPWM to be a PWM */ + status = IFX_TCPWM_PWM_Init(config->reg_base, &pwm_config); + if (status != CY_TCPWM_SUCCESS) { + return -ENOTSUP; + } + + return 0; +} + +static int ifx_tcpwm_pwm_set_cycles(const struct device *dev, uint32_t channel, + uint32_t period_cycles, uint32_t pulse_cycles, + pwm_flags_t flags) +{ + const struct ifx_tcpwm_pwm_config *config = dev->config; + uint32_t pwm_status; + uint32_t ctrl_temp; + + if (!config->resolution_32_bits && + ((period_cycles > UINT16_MAX) || (pulse_cycles > UINT16_MAX))) { + /* 16-bit resolution */ + if (period_cycles > UINT16_MAX) { + LOG_ERR("Period cycles more than 16-bits (%u)", period_cycles); + } + if (pulse_cycles > UINT16_MAX) { + LOG_ERR("Pulse cycles more than 16-bits (%u)", pulse_cycles); + } + return -EINVAL; + } + if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_INVERTED) { + config->reg_base->CTRL |= TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk; + } else { + config->reg_base->CTRL &= ~TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk; + } + + ctrl_temp = config->reg_base->CTRL & ~TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk; + + config->reg_base->CTRL = ctrl_temp | _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE, + (flags & PWM_IFX_TCPWM_OUTPUT_MASK) >> + PWM_IFX_TCPWM_OUTPUT_POS); + + /* If the PWM is not yet running, write the period and compare directly pwm won't start + * correctly. + */ + pwm_status = IFX_TCPWM_PWM_GetStatus(config->reg_base); + if ((pwm_status & TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk) == 0) { + if ((period_cycles != 0) && (pulse_cycles != 0)) { + IFX_TCPWM_PWM_SetPeriod0(config->reg_base, period_cycles - 1); + IFX_TCPWM_PWM_SetCompare0Val(config->reg_base, pulse_cycles); + } + } + + /* Special case, if period_cycles is 0, set the period and compare to zero. If we were to + * disable the PWM, the output would be set to High-Z, wheras this will set the output to + * the zero duty cycle state instead. + */ + if (period_cycles == 0) { + IFX_TCPWM_PWM_SetPeriod1(config->reg_base, 0); + IFX_TCPWM_PWM_SetCompare0BufVal(config->reg_base, 0); + IFX_TCPWM_TriggerCaptureOrSwap_Single(config->reg_base); + } else { + /* Update period and compare values using buffer registers so the new values take + * effect on the next TC event. This prevents glitches in PWM output depending on + * where in the PWM cycle the update occurs. + */ + IFX_TCPWM_PWM_SetPeriod1(config->reg_base, period_cycles - 1); + IFX_TCPWM_PWM_SetCompare0BufVal(config->reg_base, pulse_cycles); + + /* Trigger the swap by writing to the SW trigger command register. + */ + IFX_TCPWM_TriggerCaptureOrSwap_Single(config->reg_base); + } + /* Enable the TCPWM for PWM mode of operation */ + IFX_TCPWM_PWM_Enable(config->reg_base); + + /* Start the TCPWM block */ + IFX_TCPWM_TriggerStart_Single(config->reg_base); + + return 0; +} + +static int ifx_tcpwm_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel, + uint64_t *cycles) +{ + const struct ifx_tcpwm_pwm_config *config = dev->config; + + *cycles = Cy_SysClk_PeriphGetFrequency(config->divider_type, config->divider_sel); + + return 0; +} + +static DEVICE_API(pwm, ifx_tcpwm_pwm_api) = { + .set_cycles = ifx_tcpwm_pwm_set_cycles, + .get_cycles_per_sec = ifx_tcpwm_pwm_get_cycles_per_sec, +}; + +#define INFINEON_TCPWM_PWM_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + \ + static const struct ifx_tcpwm_pwm_config pwm_tcpwm_config_##n = { \ + .reg_base = (TCPWM_GRP_CNT_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \ + .tcpwm_index = (DT_REG_ADDR(DT_INST_PARENT(n)) - \ + DT_REG_ADDR(DT_PARENT(DT_INST_PARENT(n)))) / \ + DT_REG_SIZE(DT_INST_PARENT(n)), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .resolution_32_bits = \ + (DT_PROP(DT_INST_PARENT(n), resolution) == 32) ? true : false, \ + .divider_type = DT_PROP(DT_INST_PARENT(n), divider_type), \ + .divider_sel = DT_PROP(DT_INST_PARENT(n), divider_sel), \ + .divider_val = DT_PROP(DT_INST_PARENT(n), divider_val), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, ifx_tcpwm_pwm_init, NULL, NULL, &pwm_tcpwm_config_##n, \ + POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, &ifx_tcpwm_pwm_api); + +DT_INST_FOREACH_STATUS_OKAY(INFINEON_TCPWM_PWM_INIT) diff --git a/drivers/pwm/pwm_intel_blinky.c b/drivers/pwm/pwm_intel_blinky.c index 2396ae2246a6c..ef70b59f5179b 100644 --- a/drivers/pwm/pwm_intel_blinky.c +++ b/drivers/pwm/pwm_intel_blinky.c @@ -27,6 +27,7 @@ struct bk_intel_config { uint32_t reg_offset; uint32_t clock_freq; uint32_t max_pins; + uint32_t reg_upper_32; /* Stores higher 32 bits of 64 bit reg address */ }; struct bk_intel_runtime { @@ -103,9 +104,13 @@ static int bk_intel_init(const struct device *dev) { struct bk_intel_runtime *runtime = dev->data; const struct bk_intel_config *config = dev->config; + uintptr_t physical_addr; + + physical_addr = (config->reg_base.phys_addr & ~0xFFU) + | ((uintptr_t)config->reg_upper_32 << 32); device_map(&runtime->reg_base, - config->reg_base.phys_addr & ~0xFFU, + physical_addr, config->reg_base.size, K_MEM_CACHE_NONE); @@ -118,6 +123,7 @@ static int bk_intel_init(const struct device *dev) .reg_offset = DT_INST_PROP(n, reg_offset), \ .max_pins = DT_INST_PROP(n, max_pins), \ .clock_freq = DT_INST_PROP(n, clock_frequency), \ + .reg_upper_32 = DT_INST_PROP(n, reg_upper32), \ }; \ \ static struct bk_intel_runtime bk_rt_##n; \ diff --git a/drivers/pwm/pwm_max32.c b/drivers/pwm/pwm_max32.c index 85b734de600eb..6145e5b74ef2a 100644 --- a/drivers/pwm/pwm_max32.c +++ b/drivers/pwm/pwm_max32.c @@ -40,14 +40,14 @@ static int api_set_cycles(const struct device *dev, uint32_t channel, uint32_t p mxc_tmr_regs_t *regs = cfg->regs; wrap_mxc_tmr_cfg_t pwm_cfg; int prescaler_index; + mxc_tmr_pres_t tmr_prescaler_lut[] = { + TMR_PRES_1, TMR_PRES_2, TMR_PRES_4, TMR_PRES_8, TMR_PRES_16, + TMR_PRES_32, TMR_PRES_64, TMR_PRES_128, TMR_PRES_256, TMR_PRES_512, + TMR_PRES_1024, TMR_PRES_2048, TMR_PRES_4096}; prescaler_index = LOG2(cfg->prescaler); - if (prescaler_index == 0) { - pwm_cfg.pres = TMR_PRES_1; /* TMR_PRES_1 is 0 */ - } else { - /* TMR_PRES_2 is 1<duty = (uint32_t)duty_cycle; + channel->duty = DIV_ROUND_CLOSEST((uint64_t)pulse_cycles * 100ULL, period_cycles); channel->inverted = (flags & PWM_POLARITY_INVERTED); diff --git a/drivers/pwm/pwm_mchp_xec.c b/drivers/pwm/pwm_mchp_xec.c index c0d87a0da2dec..339ce72ea9d45 100644 --- a/drivers/pwm/pwm_mchp_xec.c +++ b/drivers/pwm/pwm_mchp_xec.c @@ -40,7 +40,7 @@ LOG_MODULE_REGISTER(pwm_mchp_xec, CONFIG_PWM_LOG_LEVEL); #define XEC_PWM_MAX_LOW_CLK_FREQ \ (MCHP_PWM_INPUT_FREQ_LO / XEC_PWM_LOWEST_ON_OFF) /* Precision factor for frequency calculation - * To mitigate frequency comparision up to the first digit after 0. + * To mitigate frequency comparison up to the first digit after 0. */ #define XEC_PWM_FREQ_PF 10U /* Precision factor for DC calculation diff --git a/drivers/pwm/pwm_silabs_siwx91x.c b/drivers/pwm/pwm_silabs_siwx91x.c index 520776a371744..49fff3bb750db 100644 --- a/drivers/pwm/pwm_silabs_siwx91x.c +++ b/drivers/pwm/pwm_silabs_siwx91x.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "sl_si91x_pwm.h" @@ -179,7 +180,7 @@ static int pwm_siwx91x_get_cycles_per_sec(const struct device *dev, uint32_t cha return 0; } -static int pwm_siwx91x_init(const struct device *dev) +static int pwm_siwx91x_pm_action(const struct device *dev, enum pm_device_action action) { const struct pwm_siwx91x_config *config = dev->config; struct pwm_siwx91x_data *data = dev->data; @@ -187,33 +188,46 @@ static int pwm_siwx91x_init(const struct device *dev) uint32_t pwm_frequency; int ret; - ret = clock_control_on(config->clock_dev, config->clock_subsys); - if (ret) { - return ret; - } + if (action == PM_DEVICE_ACTION_RESUME) { + ret = clock_control_on(config->clock_dev, config->clock_subsys); + if (ret) { + return ret; + } - ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &pwm_frequency); - if (ret) { - return ret; - } + ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, + &pwm_frequency); + if (ret) { + return ret; + } - ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (ret) { - return ret; - } + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret) { + return ret; + } - ARRAY_FOR_EACH(data->pwm_channel_cfg, i) { - data->pwm_channel_cfg[i].frequency = pwm_frequency / config->ch_prescaler[i]; - } + ARRAY_FOR_EACH(data->pwm_channel_cfg, i) { + data->pwm_channel_cfg[i].frequency = + pwm_frequency / config->ch_prescaler[i]; + } - ret = sl_si91x_pwm_set_output_polarity(polarity_inverted, !polarity_inverted); - if (ret) { - return -EINVAL; + ret = sl_si91x_pwm_set_output_polarity(polarity_inverted, !polarity_inverted); + if (ret) { + return -EINVAL; + } + } else if (IS_ENABLED(CONFIG_PM_DEVICE) && (action == PM_DEVICE_ACTION_SUSPEND)) { + return 0; + } else { + return -ENOTSUP; } return 0; } +static int pwm_siwx91x_init(const struct device *dev) +{ + return pm_device_driver_init(dev, pwm_siwx91x_pm_action); +} + static DEVICE_API(pwm, pwm_siwx91x_driver_api) = { .set_cycles = pwm_siwx91x_set_cycles, .get_cycles_per_sec = pwm_siwx91x_get_cycles_per_sec, @@ -229,8 +243,9 @@ static DEVICE_API(pwm, pwm_siwx91x_driver_api) = { .ch_prescaler = DT_INST_PROP(inst, silabs_ch_prescaler), \ .pwm_polarity = DT_INST_PROP(inst, silabs_pwm_polarity), \ }; \ - DEVICE_DT_INST_DEFINE(inst, &pwm_siwx91x_init, NULL, &pwm_siwx91x_data_##inst, \ - &pwm_config_##inst, PRE_KERNEL_1, CONFIG_PWM_INIT_PRIORITY, \ - &pwm_siwx91x_driver_api); + PM_DEVICE_DT_INST_DEFINE(inst, pwm_siwx91x_pm_action); \ + DEVICE_DT_INST_DEFINE(inst, &pwm_siwx91x_init, PM_DEVICE_DT_INST_GET(inst), \ + &pwm_siwx91x_data_##inst, &pwm_config_##inst, PRE_KERNEL_1, \ + CONFIG_PWM_INIT_PRIORITY, &pwm_siwx91x_driver_api); DT_INST_FOREACH_STATUS_OKAY(SIWX91X_PWM_INIT) diff --git a/drivers/rtc/rtc_ds3231.c b/drivers/rtc/rtc_ds3231.c index 3d149fec00714..45beac1fbab21 100644 --- a/drivers/rtc/rtc_ds3231.c +++ b/drivers/rtc/rtc_ds3231.c @@ -9,7 +9,7 @@ /* TODO: handle century bit, external storage? */ #include -#include +#include "rtc_ds3231.h" #include #include @@ -74,9 +74,6 @@ static int rtc_ds3231_modify_register(const struct device *dev, uint8_t reg, uin og_buf |= *buf; *buf = og_buf; } - if (err != 0) { - return err; - } err = mfd_ds3231_i2c_set_registers(config->mfd, reg, buf, 1); return err; } diff --git a/include/zephyr/drivers/rtc/rtc_ds3231.h b/drivers/rtc/rtc_ds3231.h similarity index 100% rename from include/zephyr/drivers/rtc/rtc_ds3231.h rename to drivers/rtc/rtc_ds3231.h diff --git a/drivers/rtc/rtc_ll_stm32.h b/drivers/rtc/rtc_ll_stm32.h index 0ce272d8fdd54..921a8c3f9bccd 100644 --- a/drivers/rtc/rtc_ll_stm32.h +++ b/drivers/rtc/rtc_ll_stm32.h @@ -12,7 +12,7 @@ * ES0584 / ES0631 §2.5.2; ES0632 §2.6.2 (both Rev. 2) * """ * RTC interrupts cannot be reliably used for real-time - * control functions, since some occurences of RTC + * control functions, since some occurrences of RTC * interrupts may be missed. * """ * Since alarm IRQs are unreliable, don't allow RTC alarm diff --git a/drivers/sdhc/imx_usdhc.c b/drivers/sdhc/imx_usdhc.c index 0c4dbac14fccd..f0b3e5a299f3e 100644 --- a/drivers/sdhc/imx_usdhc.c +++ b/drivers/sdhc/imx_usdhc.c @@ -216,12 +216,16 @@ static void imx_usdhc_error_recovery(const struct device *dev) if (status & kUSDHC_CommandInhibitFlag) { /* Reset command line */ - USDHC_Reset(base, kUSDHC_ResetCommand, 100U); + if (!USDHC_Reset(base, kUSDHC_ResetCommand, 100U)) { + LOG_ERR("Failed to reset command line"); + } } if (((status & (uint32_t)kUSDHC_DataInhibitFlag) != 0U) || (USDHC_GetAdmaErrorStatusFlags(base) != 0U)) { /* Reset data line */ - USDHC_Reset(base, kUSDHC_DataInhibitFlag, 100U); + if (!USDHC_Reset(base, kUSDHC_ResetData, 100U)) { + LOG_ERR("Failed to reset data line"); + } } } diff --git a/drivers/sdhc/sdhc_spi.c b/drivers/sdhc/sdhc_spi.c index aaf75ebf10007..950f511ade094 100644 --- a/drivers/sdhc/sdhc_spi.c +++ b/drivers/sdhc/sdhc_spi.c @@ -369,7 +369,7 @@ static int sdhc_spi_send_cmd(const struct device *dev, struct sdhc_command *cmd, * the maximum spi response length is 5 bytes, so we provide an * additional 5 bytes of data, leaving us with 13 bytes of 0xff. * Finally, we send a padding byte of all 0xff, to ensure that - * the card recives at least one 0xff byte before next command. + * the card receives at least one 0xff byte before next command. */ /* Note: we can discard CMD data as we send it, @@ -704,7 +704,7 @@ static int sdhc_spi_set_io(const struct device *dev, struct sdhc_io *ios) if (ios->clock > cfg->spi_max_freq) { return -ENOTSUP; } - /* Because pointer comparision is used, we have to + /* Because pointer comparison is used, we have to * swap to a new configuration structure to reconfigure SPI. */ if (ios->clock != 0) { diff --git a/drivers/sensor/a01nyub/a01nyub.c b/drivers/sensor/a01nyub/a01nyub.c index 07241140d446d..64d3a7eb99483 100644 --- a/drivers/sensor/a01nyub/a01nyub.c +++ b/drivers/sensor/a01nyub/a01nyub.c @@ -142,7 +142,7 @@ static void a01nyub_uart_isr(const struct device *uart_dev, void *user_data) * If we do not read A01NYUB_HEADER on what we think is the * first byte, then reset the number of bytes read until we do */ - if ((data->rd_data[0] != A01NYUB_HEADER) & (data->xfer_bytes == 1)) { + if ((data->rd_data[0] != A01NYUB_HEADER) && (data->xfer_bytes == 1)) { LOG_DBG("First byte not header! Resetting # of bytes read."); data->xfer_bytes = 0; } diff --git a/drivers/sensor/adi/adxl367/adxl367.c b/drivers/sensor/adi/adxl367/adxl367.c index 06c69ad81e866..476514cea776e 100644 --- a/drivers/sensor/adi/adxl367/adxl367.c +++ b/drivers/sensor/adi/adxl367/adxl367.c @@ -743,29 +743,38 @@ int adxl367_get_accel_data(const struct device *dev, } /** - * @brief Reads the raw temperature of the device. If ADXL367_TEMP_EN is not - * set, use adxl367_temp_read_en() first to enable temperature reading. + * @brief Reads the raw temperature of the device. * - * @param dev - The device structure. - * @param raw_temp - Raw value of temperature. + * If ADXL367_TEMP_EN is not set, use adxl367_temp_read_en() first to enable temperature reading. + * Optionally checks the data ready status before reading temperature. + * + * @param dev - The device structure. + * @param raw_temp - Raw value of temperature. + * @param check_data_rdy - If true, waits for data ready status before reading temperature. + * If false, reads temperature directly. Note: The DATA_READY bit is + * cleared when data is read; set this flag to false if temperature from + * the same sample frame is needed after performing an axis(x,y,z) read. * * @return 0 in case of success, negative error code otherwise. */ -int adxl367_get_temp_data(const struct device *dev, int16_t *raw_temp) +int adxl367_get_temp_data(const struct device *dev, int16_t *raw_temp, bool check_data_rdy) { int ret; uint8_t temp[2] = { 0 }; - uint8_t reg_data, nready = 1U; struct adxl367_data *data = dev->data; - while (nready != 0) { - ret = data->hw_tf->read_reg(dev, ADXL367_STATUS, ®_data); - if (ret != 0) { - return ret; - } + if (check_data_rdy) { + uint8_t reg_data, nready = 1U; - if ((reg_data & ADXL367_STATUS_DATA_RDY) != 0) { - nready = 0U; + while (nready != 0) { + ret = data->hw_tf->read_reg(dev, ADXL367_STATUS, ®_data); + if (ret != 0) { + return ret; + } + + if ((reg_data & ADXL367_STATUS_DATA_RDY) != 0) { + nready = 0U; + } } } @@ -879,8 +888,14 @@ static int adxl367_sample_fetch(const struct device *dev, if (ret != 0) { return ret; } + const struct adxl367_dev_config *cfg = dev->config; + bool check_temp_data_ready = false; - return adxl367_get_temp_data(dev, &data->temp_val); + if (cfg->temp_en) { + ret = adxl367_get_temp_data(dev, &data->temp_val, check_temp_data_ready); + } + + return ret; } #ifdef CONFIG_SENSOR_ASYNC_API void adxl367_accel_convert(struct sensor_value *val, int16_t value, diff --git a/drivers/sensor/adi/adxl367/adxl367.h b/drivers/sensor/adi/adxl367/adxl367.h index a1ff9d3b25059..bc6ddd0f32a79 100644 --- a/drivers/sensor/adi/adxl367/adxl367.h +++ b/drivers/sensor/adi/adxl367/adxl367.h @@ -442,7 +442,7 @@ void adxl367_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); int adxl367_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); int adxl367_get_accel_data(const struct device *dev, struct adxl367_xyz_accel_data *accel_data); -int adxl367_get_temp_data(const struct device *dev, int16_t *raw_temp); +int adxl367_get_temp_data(const struct device *dev, int16_t *raw_temp, bool check_data_rdy); void adxl367_accel_convert(struct sensor_value *val, int16_t value, enum adxl367_range range); void adxl367_temp_convert(struct sensor_value *val, int16_t value); diff --git a/drivers/sensor/adi/adxl367/adxl367_rtio.c b/drivers/sensor/adi/adxl367/adxl367_rtio.c index b19ec800ca9a5..ec9580c06192a 100644 --- a/drivers/sensor/adi/adxl367/adxl367_rtio.c +++ b/drivers/sensor/adi/adxl367/adxl367_rtio.c @@ -44,8 +44,9 @@ static void adxl367_submit_fetch(struct rtio_iodev_sqe *iodev_sqe) } enc_data->xyz.range = data->range; + bool check_temp_data_ready = false; - rc = adxl367_get_temp_data(dev, &enc_data->raw_temp); + rc = adxl367_get_temp_data(dev, &enc_data->raw_temp, check_temp_data_ready); if (rc != 0) { LOG_ERR("Failed to fetch temp samples"); rtio_iodev_sqe_err(iodev_sqe, rc); diff --git a/drivers/sensor/bosch/bmi08x/bmi08x_accel.c b/drivers/sensor/bosch/bmi08x/bmi08x_accel.c index 2ea2dacdecd2f..7de8c6ed68204 100644 --- a/drivers/sensor/bosch/bmi08x/bmi08x_accel.c +++ b/drivers/sensor/bosch/bmi08x/bmi08x_accel.c @@ -744,7 +744,7 @@ int bmi08x_accel_init(const struct device *dev) */ #define BMI08X_GYRO_ODR(inst) DT_ENUM_IDX(DT_INST_PHANDLE(inst, data_sync), gyro_hz) #define BMI08X_ACCEL_ODR(inst) DT_INST_ENUM_IDX(inst, accel_hz) -/* As the dts uses strings to define the definition, ints must be used for comparision */ +/* As the dts uses strings to define the definition, ints must be used for comparison */ #define BMI08X_VERIFY_DATA_SYNC_ODR(inst) \ BUILD_ASSERT((BMI08X_GYRO_ODR(inst) == 3 && BMI08X_ACCEL_ODR(inst) == 5) || \ (BMI08X_GYRO_ODR(inst) == 2 && BMI08X_ACCEL_ODR(inst) == 6) || \ diff --git a/drivers/sensor/bosch/bmi270/bmi270.c b/drivers/sensor/bosch/bmi270/bmi270.c index d94d0e39d00bd..fc8652a7d1d9c 100644 --- a/drivers/sensor/bosch/bmi270/bmi270.c +++ b/drivers/sensor/bosch/bmi270/bmi270.c @@ -747,7 +747,7 @@ static int bmi270_init(const struct device *dev) k_usleep(BMI270_CONFIG_FILE_POLL_PERIOD_US); } - if (tries == BMI270_CONFIG_FILE_RETRIES) { + if (tries > BMI270_CONFIG_FILE_RETRIES) { return -EIO; } diff --git a/drivers/sensor/explorir_m/explorir_m.c b/drivers/sensor/explorir_m/explorir_m.c index dc0306fb7ef0b..5ce6e180eaea1 100644 --- a/drivers/sensor/explorir_m/explorir_m.c +++ b/drivers/sensor/explorir_m/explorir_m.c @@ -405,8 +405,17 @@ static int explorir_m_init(const struct device *dev) uart_irq_rx_enable(cfg->uart_dev); val.val1 = EXPLORIR_M_MODE_POLL; - explorir_m_uart_transceive(dev, EXPLORIR_M_MODE_CHAR, &val, EXPLORIR_M_SET_VAL_ONE); - explorir_m_uart_transceive(dev, EXPLORIR_M_SCALING_CHAR, NULL, EXPLORIR_M_SET_NONE); + rc = explorir_m_uart_transceive(dev, EXPLORIR_M_MODE_CHAR, &val, EXPLORIR_M_SET_VAL_ONE); + if (rc != 0) { + LOG_ERR("Set mode failed: %d", rc); + return rc; + } + + rc = explorir_m_uart_transceive(dev, EXPLORIR_M_SCALING_CHAR, NULL, EXPLORIR_M_SET_NONE); + if (rc != 0) { + LOG_ERR("Set scaling failed: %d", rc); + return rc; + } return rc; } diff --git a/drivers/sensor/pixart/paj7620/paj7620.c b/drivers/sensor/pixart/paj7620/paj7620.c index 27f35fa997658..8f4eb1defbe17 100644 --- a/drivers/sensor/pixart/paj7620/paj7620.c +++ b/drivers/sensor/pixart/paj7620/paj7620.c @@ -107,7 +107,7 @@ static int paj7620_set_sampling_rate(const struct device *dev, const struct sens int ret; int fps; const struct paj7620_config *config = dev->config; - int64_t uval = val->val1 * 1000000 + val->val2; + int64_t uval = ((int64_t)val->val1 * (int64_t)1000000) + val->val2; if (uval <= 120000000) { fps = PAJ7620_NORMAL_SPEED; diff --git a/drivers/sensor/shell_battery.c b/drivers/sensor/shell_battery.c index babdd7315ce19..4d7e34ea62865 100644 --- a/drivers/sensor/shell_battery.c +++ b/drivers/sensor/shell_battery.c @@ -94,7 +94,8 @@ static int cmd_battery(const struct shell *sh, size_t argc, char **argv) volt.val1, volt.val2 / 10000); shell_print(sh, "V-desired: %d.%02d V", v_desired.val1, v_desired.val2 / 10000); - shell_fprintf_normal(sh, "I: %d mA", current.val1); + shell_fprintf_normal(sh, "I: %lld mA", + sensor_value_to_milli(¤t)); if (current.val1 > 0) { shell_fprintf_normal(sh, " (CHG)"); } else if (current.val1 < 0) { @@ -109,10 +110,10 @@ static int cmd_battery(const struct shell *sh, size_t argc, char **argv) shell_print(sh, "Charge: %d %%", charge.val1); shell_print(sh, "V-design: %d.%02d V", v_design.val1, v_design.val2 / 10000); - shell_print(sh, "Remaining: %d mA", + shell_print(sh, "Remaining: %d mAh", charge_remain.val1); - shell_print(sh, "Cap-full: %d mA", cap.val1); - shell_print(sh, "Design: %d mA", nom_cap.val1); + shell_print(sh, "Cap-full: %d mAh", cap.val1); + shell_print(sh, "Design: %d mAh", nom_cap.val1); shell_print(sh, "Time full: %dh:%02d", full.val1 / 60, full.val1 % 60); shell_print(sh, "Time empty: %dh:%02d", diff --git a/drivers/sensor/st/lsm9ds1/lsm9ds1.c b/drivers/sensor/st/lsm9ds1/lsm9ds1.c index 22918c9e19fa6..4f46427a81dbc 100644 --- a/drivers/sensor/st/lsm9ds1/lsm9ds1.c +++ b/drivers/sensor/st/lsm9ds1/lsm9ds1.c @@ -8,6 +8,7 @@ #include #include +#include #include "lsm9ds1.h" #include @@ -570,11 +571,48 @@ static DEVICE_API(sensor, lsm9ds1_api_funcs) = { .attr_set = lsm9ds1_attr_set, }; +#ifdef CONFIG_PM_DEVICE +static int lsm9ds1_pm_action(const struct device *dev, enum pm_device_action action) +{ + const struct lsm9ds1_config *cfg = dev->config; + stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; + struct lsm9ds1_data *data = dev->data; + int ret; + + switch (action) { + case PM_DEVICE_ACTION_RESUME: + ret = lsm9ds1_accel_set_odr_raw(dev, data->accel_odr); + if (ret < 0) { + LOG_ERR("Failed to resume accelerometer"); + return ret; + } + ret = lsm9ds1_gyro_set_odr_raw(dev, data->gyro_odr); + if (ret < 0) { + LOG_ERR("Failed to resume gyroscope"); + return ret; + } + break; + case PM_DEVICE_ACTION_SUSPEND: + ret = lsm9ds1_imu_data_rate_set(ctx, LSM9DS1_IMU_OFF); + if (ret < 0) { + LOG_ERR("Failed to suspend accelerometer and gyroscope"); + return ret; + } + + break; + default: + return -ENOTSUP; + } + + return 0; +} +#endif + static int lsm9ds1_init(const struct device *dev) { const struct lsm9ds1_config *cfg = dev->config; stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; - struct lsm9ds1_data *lsm9ds1 = dev->data; + struct lsm9ds1_data *data = dev->data; uint8_t chip_id, fs; int ret; @@ -611,7 +649,7 @@ static int lsm9ds1_init(const struct device *dev) return ret; } - lsm9ds1->acc_gain = lsm9ds1_accel_fs_val_to_gain(fs); + data->acc_gain = lsm9ds1_accel_fs_val_to_gain(fs); fs = cfg->gyro_range; LOG_DBG("gyro range is %d", fs); @@ -620,7 +658,7 @@ static int lsm9ds1_init(const struct device *dev) LOG_ERR("failed to set gyroscope range %d\n", fs); return ret; } - lsm9ds1->gyro_gain = (lsm9ds1_gyro_fs_sens[fs] * GAIN_UNIT_G); + data->gyro_gain = (lsm9ds1_gyro_fs_sens[fs] * GAIN_UNIT_G); return 0; } @@ -651,8 +689,10 @@ static int lsm9ds1_init(const struct device *dev) \ static struct lsm9ds1_config lsm9ds1_config_##inst = LSM9DS1_CONFIG_I2C(inst); \ \ - SENSOR_DEVICE_DT_INST_DEFINE(inst, lsm9ds1_init, NULL, &lsm9ds1_data_##inst, \ - &lsm9ds1_config_##inst, POST_KERNEL, \ + PM_DEVICE_DT_INST_DEFINE(inst, lsm9ds1_pm_action); \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, lsm9ds1_init, PM_DEVICE_DT_INST_GET(inst), \ + &lsm9ds1_data_##inst, &lsm9ds1_config_##inst, POST_KERNEL, \ CONFIG_SENSOR_INIT_PRIORITY, &lsm9ds1_api_funcs); DT_INST_FOREACH_STATUS_OKAY(LSM9DS1_DEFINE); diff --git a/drivers/sensor/st/lsm9ds1_mag/lsm9ds1_mag.c b/drivers/sensor/st/lsm9ds1_mag/lsm9ds1_mag.c index 2e90084b2725c..261e24b19b287 100644 --- a/drivers/sensor/st/lsm9ds1_mag/lsm9ds1_mag.c +++ b/drivers/sensor/st/lsm9ds1_mag/lsm9ds1_mag.c @@ -337,7 +337,7 @@ static int lsm9ds1_mag_init(const struct device *dev) { const struct lsm9ds1_mag_config *cfg = dev->config; stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; - struct lsm9ds1_mag_data *lsm9ds1_mag = dev->data; + struct lsm9ds1_mag_data *data = dev->data; uint8_t chip_id, fs; int ret; @@ -366,7 +366,7 @@ static int lsm9ds1_mag_init(const struct device *dev) } if (cfg->mag_odr == LSM9DS1_MAG_POWER_DOWN) { - lsm9ds1_mag->powered_down = 1; + data->powered_down = 1; } fs = cfg->mag_range; @@ -376,7 +376,7 @@ static int lsm9ds1_mag_init(const struct device *dev) return ret; } - lsm9ds1_mag->mag_gain = lsm9ds1_mag_fs_sens[fs]; + data->mag_gain = lsm9ds1_mag_fs_sens[fs]; return 0; } diff --git a/drivers/sensor/voltage_divider/voltage.c b/drivers/sensor/voltage_divider/voltage.c index 1827e752359c0..bc27ea4f16ad1 100644 --- a/drivers/sensor/voltage_divider/voltage.c +++ b/drivers/sensor/voltage_divider/voltage.c @@ -191,6 +191,7 @@ static int voltage_init(const struct device *dev) data->sequence.buffer = &data->raw; data->sequence.buffer_size = sizeof(data->raw); + data->sequence.calibrate = true; return pm_device_driver_init(dev, pm_action); } diff --git a/drivers/sensor/wsen/CMakeLists.txt b/drivers/sensor/wsen/CMakeLists.txt index 9069a6d4c439f..856e5ff496479 100644 --- a/drivers/sensor/wsen/CMakeLists.txt +++ b/drivers/sensor/wsen/CMakeLists.txt @@ -4,6 +4,7 @@ # zephyr-keep-sorted-start add_subdirectory_ifdef(CONFIG_WSEN_HIDS_2525020210002 wsen_hids_2525020210002) +add_subdirectory_ifdef(CONFIG_WSEN_ISDS_2536030320001 wsen_isds_2536030320001) add_subdirectory_ifdef(CONFIG_WSEN_ITDS_2533020201601 wsen_itds_2533020201601) add_subdirectory_ifdef(CONFIG_WSEN_PADS_2511020213301 wsen_pads_2511020213301) add_subdirectory_ifdef(CONFIG_WSEN_PDUS_25131308XXXXX wsen_pdus_25131308XXXXX) diff --git a/drivers/sensor/wsen/Kconfig b/drivers/sensor/wsen/Kconfig index b4c9c0523fc79..5b01259aa7443 100644 --- a/drivers/sensor/wsen/Kconfig +++ b/drivers/sensor/wsen/Kconfig @@ -4,6 +4,7 @@ # zephyr-keep-sorted-start source "drivers/sensor/wsen/wsen_hids_2525020210002/Kconfig" +source "drivers/sensor/wsen/wsen_isds_2536030320001/Kconfig" source "drivers/sensor/wsen/wsen_itds_2533020201601/Kconfig" source "drivers/sensor/wsen/wsen_pads_2511020213301/Kconfig" source "drivers/sensor/wsen/wsen_pdus_25131308XXXXX/Kconfig" diff --git a/drivers/sensor/wsen/wsen_isds_2536030320001/CMakeLists.txt b/drivers/sensor/wsen/wsen_isds_2536030320001/CMakeLists.txt new file mode 100644 index 0000000000000..430238b2508b8 --- /dev/null +++ b/drivers/sensor/wsen/wsen_isds_2536030320001/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(wsen_isds_2536030320001.c) +zephyr_library_sources_ifdef(CONFIG_WSEN_ISDS_2536030320001_TRIGGER wsen_isds_2536030320001_trigger.c) + +zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/..) diff --git a/drivers/sensor/wsen/wsen_isds_2536030320001/Kconfig b/drivers/sensor/wsen/wsen_isds_2536030320001/Kconfig new file mode 100644 index 0000000000000..d009210caa6b7 --- /dev/null +++ b/drivers/sensor/wsen/wsen_isds_2536030320001/Kconfig @@ -0,0 +1,98 @@ +# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +menuconfig WSEN_ISDS_2536030320001 + bool "WSEN-ISDS 3D accelerometer and 3D gyroscope sensor" + default y + depends on DT_HAS_WE_WSEN_ISDS_2536030320001_ENABLED + select I2C if $(dt_compat_on_bus,$(DT_COMPAT_WE_WSEN_ISDS_2536030320001),i2c) + select SPI if $(dt_compat_on_bus,$(DT_COMPAT_WE_WSEN_ISDS_2536030320001),spi) + select HAS_WESENSORS + help + Enable driver for the WSEN-ISDS I2C/SPI-based 3D accelerometer and 3D gyroscope sensor + with integrated temperature sensor. + +if WSEN_ISDS_2536030320001 + +config WSEN_ISDS_2536030320001_DISABLE_ACCEL_HIGH_PERFORMANCE_MODE + bool "Disable accelerometer high performance mode" + help + Disables accelerometer high performance mode. If high performance mode is disabled, + the ODR is used to switch between power modes as follows: + - 1.6 Hz - 52 Hz Low power mode + - 104 Hz - 208 Hz Normal power mode + - 416 Hz - 6.66 kHz High performance mode + +config WSEN_ISDS_2536030320001_DISABLE_GYRO_HIGH_PERFORMANCE_MODE + bool "Disable gyroscope high performance mode" + help + Disables gyroscope high performance mode. If high performance mode is disabled, + the ODR is used to switch between power modes as follows: + - 12.5 Hz - 52 Hz Low power mode + - 104 Hz - 208 Hz Normal power mode + - 416 Hz - 6.66 kHz High performance mode + +choice WSEN_ISDS_2536030320001_TRIGGER_MODE + prompt "Trigger mode" + default WSEN_ISDS_2536030320001_TRIGGER_NONE + help + Specify the type of triggering to be used by the driver. + +config WSEN_ISDS_2536030320001_TRIGGER_NONE + bool "No trigger" + +config WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD + bool "Use global thread" + depends on GPIO + select WSEN_ISDS_2536030320001_TRIGGER + +config WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD + bool "Use own thread" + depends on GPIO + select WSEN_ISDS_2536030320001_TRIGGER + +endchoice # WSEN_ISDS_2536030320001_TRIGGER_MODE + +config WSEN_ISDS_2536030320001_TRIGGER + bool + +config WSEN_ISDS_2536030320001_EVENTS + bool + +config WSEN_ISDS_2536030320001_THREAD_PRIORITY + int "Thread priority" + depends on WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD + default 10 + help + Priority of thread used by the driver to handle interrupts. + +config WSEN_ISDS_2536030320001_THREAD_STACK_SIZE + int "Thread stack size" + depends on WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD + default 1024 + help + Stack size of thread used by the driver to handle interrupts. + +config WSEN_ISDS_2536030320001_TAP + bool "Tap and double tap detection" + depends on WSEN_ISDS_2536030320001_TRIGGER + select WSEN_ISDS_2536030320001_EVENTS + help + Enable tap (single/double) detection + Note that the recommended ODRs for tap recognition are 416 Hz and 833 Hz. + +config WSEN_ISDS_2536030320001_FREEFALL + bool "Free-fall detection" + depends on WSEN_ISDS_2536030320001_TRIGGER + select WSEN_ISDS_2536030320001_EVENTS + help + Enable free-fall detection + +config WSEN_ISDS_2536030320001_DELTA + bool "Wake-up detection (SENSOR_TRIG_DELTA)" + depends on WSEN_ISDS_2536030320001_TRIGGER + select WSEN_ISDS_2536030320001_EVENTS + help + Enable wake-up detection (SENSOR_TRIG_DELTA) + +endif # WSEN_ISDS_2536030320001 diff --git a/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001.c b/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001.c new file mode 100644 index 0000000000000..8d54ed33bc8bf --- /dev/null +++ b/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001.c @@ -0,0 +1,946 @@ +/* + * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT we_wsen_isds_2536030320001 + +#include + +#include +#include +#include + +#include +#include "wsen_isds_2536030320001.h" + +LOG_MODULE_REGISTER(WSEN_ISDS_2536030320001, CONFIG_SENSOR_LOG_LEVEL); + +/* + * List of supported accelerometer output data rates (sensor_value struct, input to + * sensor_attr_set()). Index into this list is used as argument for + * ISDS_setAccOutputDataRate(). + */ +static const struct sensor_value isds_2536030320001_accel_odr_list[] = { + {.val1 = 0, .val2 = 0}, {.val1 = 12, .val2 = 5 * 100000}, + {.val1 = 26, .val2 = 0}, {.val1 = 52, .val2 = 0}, + {.val1 = 104, .val2 = 0}, {.val1 = 208, .val2 = 0}, + {.val1 = 416, .val2 = 0}, {.val1 = 833, .val2 = 0}, + {.val1 = 1660, .val2 = 0}, {.val1 = 3330, .val2 = 0}, + {.val1 = 6660, .val2 = 0}, {.val1 = 1, .val2 = 6 * 100000}, +}; + +/* + * List of supported gyroscope output data rates (sensor_value struct, input to + * sensor_attr_set()). Index into this list is used as argument for + * ISDS_setGyroOutputDataRate(). + */ +static const struct sensor_value isds_2536030320001_gyro_odr_list[] = { + {.val1 = 0, .val2 = 0}, {.val1 = 12, .val2 = 5 * 100000}, {.val1 = 26, .val2 = 0}, + {.val1 = 52, .val2 = 0}, {.val1 = 104, .val2 = 0}, {.val1 = 208, .val2 = 0}, + {.val1 = 416, .val2 = 0}, {.val1 = 833, .val2 = 0}, {.val1 = 1660, .val2 = 0}, + {.val1 = 3330, .val2 = 0}, {.val1 = 6660, .val2 = 0}, +}; + +/* + * List of supported accelerometer full scale values (i.e. measurement ranges, in g). + * Index into this list is used as input for ISDS_setAccFullScale(). + */ +static const uint8_t isds_2536030320001_accel_full_scale_list[] = { + 2, + 16, + 4, + 8, +}; + +/* + * List of supported gyroscope full scale values (i.e. measurement ranges, in dps). + * Index into this list is used as input for ISDS_setGyroFullScale(). + */ +static const uint16_t isds_2536030320001_gyro_full_scale_list[] = { + 250, 125, 500, 0, 1000, 0, 2000, +}; + +static int isds_2536030320001_sample_fetch(const struct device *dev, enum sensor_channel channel) +{ + struct isds_2536030320001_data *data = dev->data; + + uint32_t accel_step_sleep_duration, gyro_step_sleep_duration, step_sleep_duration; + + switch (channel) { + case SENSOR_CHAN_ALL: + case SENSOR_CHAN_AMBIENT_TEMP: { + if (!wsen_sensor_step_sleep_duration_milli_from_odr_hz( + &isds_2536030320001_accel_odr_list[data->accel_odr], + &accel_step_sleep_duration)) { + LOG_ERR("Accelerometer is disabled."); + return -ENOTSUP; + } + + if (!wsen_sensor_step_sleep_duration_milli_from_odr_hz( + &isds_2536030320001_gyro_odr_list[data->gyro_odr], + &gyro_step_sleep_duration)) { + LOG_ERR("Gyroscope is disabled."); + return -ENOTSUP; + } + + step_sleep_duration = accel_step_sleep_duration < gyro_step_sleep_duration + ? gyro_step_sleep_duration + : accel_step_sleep_duration; + break; + } + case SENSOR_CHAN_ACCEL_X: + case SENSOR_CHAN_ACCEL_Y: + case SENSOR_CHAN_ACCEL_Z: + case SENSOR_CHAN_ACCEL_XYZ: { + if (!wsen_sensor_step_sleep_duration_milli_from_odr_hz( + &isds_2536030320001_accel_odr_list[data->accel_odr], + &step_sleep_duration)) { + LOG_ERR("Accelerometer is disabled."); + return -ENOTSUP; + } + break; + } + case SENSOR_CHAN_GYRO_X: + case SENSOR_CHAN_GYRO_Y: + case SENSOR_CHAN_GYRO_Z: + case SENSOR_CHAN_GYRO_XYZ: { + if (!wsen_sensor_step_sleep_duration_milli_from_odr_hz( + &isds_2536030320001_gyro_odr_list[data->gyro_odr], + &step_sleep_duration)) { + LOG_ERR("Gyroscope is disabled."); + return -ENOTSUP; + } + break; + } + default: + LOG_ERR("Fetching is not supported on channel %d.", channel); + return -ENOTSUP; + } + + ISDS_state_t acceleration_data_ready, gyro_data_ready, temp_data_ready; + + acceleration_data_ready = gyro_data_ready = temp_data_ready = ISDS_disable; + + bool data_ready = false; + int step_count = 0; + + while (1) { + switch (channel) { + case SENSOR_CHAN_ALL: { + if (ISDS_isAccelerationDataReady(&data->sensor_interface, + &acceleration_data_ready) != WE_SUCCESS) { + LOG_ERR("Failed to check if acceleration data is ready."); + return -EIO; + } + + if (ISDS_isGyroscopeDataReady(&data->sensor_interface, &gyro_data_ready) != + WE_SUCCESS) { + LOG_ERR("Failed to check if gyroscope data is ready."); + return -EIO; + } + + if (ISDS_isTemperatureDataReady(&data->sensor_interface, + &temp_data_ready) != WE_SUCCESS) { + LOG_ERR("Failed to check if temperature data is ready."); + return -EIO; + } + + data_ready = + (acceleration_data_ready == ISDS_enable && + gyro_data_ready == ISDS_enable && temp_data_ready == ISDS_enable); + break; + } + case SENSOR_CHAN_AMBIENT_TEMP: { + if (ISDS_isTemperatureDataReady(&data->sensor_interface, + &temp_data_ready) != WE_SUCCESS) { + LOG_ERR("Failed to check if temperature data is ready."); + return -EIO; + } + data_ready = (temp_data_ready == ISDS_enable); + break; + } + case SENSOR_CHAN_ACCEL_X: + case SENSOR_CHAN_ACCEL_Y: + case SENSOR_CHAN_ACCEL_Z: + case SENSOR_CHAN_ACCEL_XYZ: { + if (ISDS_isAccelerationDataReady(&data->sensor_interface, + &acceleration_data_ready) != WE_SUCCESS) { + LOG_ERR("Failed to check if acceleration data is ready."); + return -EIO; + } + + data_ready = (acceleration_data_ready == ISDS_enable); + break; + } + case SENSOR_CHAN_GYRO_X: + case SENSOR_CHAN_GYRO_Y: + case SENSOR_CHAN_GYRO_Z: + case SENSOR_CHAN_GYRO_XYZ: { + if (ISDS_isGyroscopeDataReady(&data->sensor_interface, &gyro_data_ready) != + WE_SUCCESS) { + LOG_ERR("Failed to check if gyroscope data is ready."); + return -EIO; + } + + data_ready = (gyro_data_ready == ISDS_enable); + break; + } + default: + break; + } + + if (data_ready) { + break; + } else if (step_count >= MAX_POLL_STEP_COUNT) { + return -EIO; + } + + step_count++; + k_sleep(K_USEC(step_sleep_duration)); + } + + int16_t temperature, acceleration_x, acceleration_y, acceleration_z, gyro_x, gyro_y, gyro_z; + + switch (channel) { + case SENSOR_CHAN_ALL: { + + if (ISDS_getRawAccelerations(&data->sensor_interface, &acceleration_x, + &acceleration_y, &acceleration_z) != WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "acceleration"); + return -EIO; + } + + if (ISDS_getRawAngularRates(&data->sensor_interface, &gyro_x, &gyro_y, &gyro_z) != + WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "gyro"); + return -EIO; + } + + if (ISDS_getRawTemperature(&data->sensor_interface, &temperature) != WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "temperature"); + return -EIO; + } + + data->acceleration_x = + ISDS_convertAcceleration_int(acceleration_x, data->accel_range); + data->acceleration_y = + ISDS_convertAcceleration_int(acceleration_y, data->accel_range); + data->acceleration_z = + ISDS_convertAcceleration_int(acceleration_z, data->accel_range); + + data->rate_x = ISDS_convertAngularRate_int(gyro_x, data->gyro_range); + data->rate_y = ISDS_convertAngularRate_int(gyro_y, data->gyro_range); + data->rate_z = ISDS_convertAngularRate_int(gyro_z, data->gyro_range); + + data->temperature = ISDS_convertTemperature_int(temperature); + break; + } + case SENSOR_CHAN_AMBIENT_TEMP: { + if (ISDS_getRawTemperature(&data->sensor_interface, &temperature) != WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "temperature"); + return -EIO; + } + data->temperature = ISDS_convertTemperature_int(temperature); + break; + } + case SENSOR_CHAN_ACCEL_X: { + if (ISDS_getRawAccelerationX(&data->sensor_interface, &acceleration_x) != + WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "acceleration"); + return -EIO; + } + data->acceleration_x = + ISDS_convertAcceleration_int(acceleration_x, data->accel_range); + break; + } + case SENSOR_CHAN_ACCEL_Y: { + if (ISDS_getRawAccelerationY(&data->sensor_interface, &acceleration_y) != + WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "acceleration"); + return -EIO; + } + data->acceleration_y = + ISDS_convertAcceleration_int(acceleration_y, data->accel_range); + break; + } + case SENSOR_CHAN_ACCEL_Z: { + if (ISDS_getRawAccelerationZ(&data->sensor_interface, &acceleration_z) != + WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "acceleration"); + return -EIO; + } + data->acceleration_z = + ISDS_convertAcceleration_int(acceleration_z, data->accel_range); + break; + } + case SENSOR_CHAN_ACCEL_XYZ: { + if (ISDS_getRawAccelerations(&data->sensor_interface, &acceleration_x, + &acceleration_y, &acceleration_z) != WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "acceleration"); + return -EIO; + } + + data->acceleration_x = + ISDS_convertAcceleration_int(acceleration_x, data->accel_range); + data->acceleration_y = + ISDS_convertAcceleration_int(acceleration_y, data->accel_range); + data->acceleration_z = + ISDS_convertAcceleration_int(acceleration_z, data->accel_range); + break; + } + case SENSOR_CHAN_GYRO_X: { + if (ISDS_getRawAngularRateX(&data->sensor_interface, &gyro_x) != WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "gyro"); + return -EIO; + } + data->rate_x = ISDS_convertAngularRate_int(gyro_x, data->gyro_range); + break; + } + case SENSOR_CHAN_GYRO_Y: { + if (ISDS_getRawAngularRateY(&data->sensor_interface, &gyro_y) != WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "gyro"); + return -EIO; + } + data->rate_y = ISDS_convertAngularRate_int(gyro_y, data->gyro_range); + break; + } + case SENSOR_CHAN_GYRO_Z: { + if (ISDS_getRawAngularRateZ(&data->sensor_interface, &gyro_z) != WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "gyro"); + return -EIO; + } + data->rate_z = ISDS_convertAngularRate_int(gyro_z, data->gyro_range); + break; + } + case SENSOR_CHAN_GYRO_XYZ: { + if (ISDS_getRawAngularRates(&data->sensor_interface, &gyro_x, &gyro_y, &gyro_z) != + WE_SUCCESS) { + LOG_ERR("Failed to fetch %s sample.", "gyro"); + return -EIO; + } + + data->rate_x = ISDS_convertAngularRate_int(gyro_x, data->gyro_range); + data->rate_y = ISDS_convertAngularRate_int(gyro_y, data->gyro_range); + data->rate_z = ISDS_convertAngularRate_int(gyro_z, data->gyro_range); + break; + } + default: + break; + } + + return 0; +} + +/* Convert acceleration value from mg (int16) to m/s^2 (sensor_value). */ +static inline void isds_2536030320001_convert_acceleration(struct sensor_value *val, + int16_t raw_val) +{ + int64_t dval; + + /* Convert to m/s^2 */ + dval = (((int64_t)raw_val) * SENSOR_G) / 1000000LL; + val->val1 = dval / 1000LL; + val->val2 = (dval % 1000LL) * 1000; +} + +/* Convert angular rate value from mdps (int32) to radians/s (sensor_value). */ +static inline void isds_2536030320001_convert_angular_rate(struct sensor_value *val, + int32_t raw_val) +{ + int64_t dval; + + /* Convert to radians/s */ + dval = ((((int64_t)raw_val) * SENSOR_PI) / 180000000LL); + val->val1 = dval / 1000LL; + val->val2 = (dval % 1000LL) * 1000; +} + +static int isds_2536030320001_channel_get(const struct device *dev, enum sensor_channel channel, + struct sensor_value *value) +{ + struct isds_2536030320001_data *data = dev->data; + + switch (channel) { + case SENSOR_CHAN_AMBIENT_TEMP: + /* Convert temperature from 0.01 degrees Celsius to degrees Celsius */ + value->val1 = (int32_t)data->temperature / 100; + value->val2 = ((int32_t)data->temperature % 100) * (1000000 / 100); + break; + case SENSOR_CHAN_ACCEL_X: + case SENSOR_CHAN_ACCEL_Y: + case SENSOR_CHAN_ACCEL_Z: + case SENSOR_CHAN_ACCEL_XYZ: + /* Convert requested acceleration(s) */ + if (channel == SENSOR_CHAN_ACCEL_X || channel == SENSOR_CHAN_ACCEL_XYZ) { + isds_2536030320001_convert_acceleration(value, data->acceleration_x); + value++; + } + if (channel == SENSOR_CHAN_ACCEL_Y || channel == SENSOR_CHAN_ACCEL_XYZ) { + isds_2536030320001_convert_acceleration(value, data->acceleration_y); + value++; + } + if (channel == SENSOR_CHAN_ACCEL_Z || channel == SENSOR_CHAN_ACCEL_XYZ) { + isds_2536030320001_convert_acceleration(value, data->acceleration_z); + value++; + } + break; + case SENSOR_CHAN_GYRO_X: + case SENSOR_CHAN_GYRO_Y: + case SENSOR_CHAN_GYRO_Z: + case SENSOR_CHAN_GYRO_XYZ: + if (channel == SENSOR_CHAN_GYRO_X || channel == SENSOR_CHAN_GYRO_XYZ) { + isds_2536030320001_convert_angular_rate(value, data->rate_x); + value++; + } + if (channel == SENSOR_CHAN_GYRO_Y || channel == SENSOR_CHAN_GYRO_XYZ) { + isds_2536030320001_convert_angular_rate(value, data->rate_y); + value++; + } + if (channel == SENSOR_CHAN_GYRO_Z || channel == SENSOR_CHAN_GYRO_XYZ) { + isds_2536030320001_convert_angular_rate(value, data->rate_z); + value++; + } + break; + default: + LOG_ERR("Channel not supported %d", channel); + return -ENOTSUP; + } + + return 0; +} + +/* Set accelerometer output data rate. See isds_2536030320001_accel_odr_list for allowed values. */ +static int isds_2536030320001_accel_odr_set(const struct device *dev, + const struct sensor_value *odr) +{ + struct isds_2536030320001_data *data = dev->data; + int odr_index; + + for (odr_index = 0; odr_index < ARRAY_SIZE(isds_2536030320001_accel_odr_list); + odr_index++) { + if (odr->val1 == isds_2536030320001_accel_odr_list[odr_index].val1 && + odr->val2 == isds_2536030320001_accel_odr_list[odr_index].val2) { + break; + } + } + + if (odr_index == ARRAY_SIZE(isds_2536030320001_accel_odr_list)) { + /* ODR not allowed (was not found in isds_2536030320001_accel_odr_list) */ + LOG_ERR("Bad sampling frequency %d.%d", odr->val1, odr->val2); + return -EINVAL; + } + + if (ISDS_setAccOutputDataRate(&data->sensor_interface, + (ISDS_accOutputDataRate_t)odr_index) != WE_SUCCESS) { + LOG_ERR("Failed to set accelerometer output data rate"); + return -EIO; + } + + data->accel_odr = (ISDS_accOutputDataRate_t)odr_index; + + return 0; +} + +/* Get accelerometer output data rate. See isds_2536030320001_accel_odr_list for allowed values. */ +static int isds_2536030320001_accel_odr_get(const struct device *dev, struct sensor_value *odr) +{ + struct isds_2536030320001_data *data = dev->data; + ISDS_accOutputDataRate_t odr_index; + + if (ISDS_getAccOutputDataRate(&data->sensor_interface, &odr_index) != WE_SUCCESS) { + LOG_ERR("Failed to get output data rate"); + return -EIO; + } + + data->accel_odr = odr_index; + + odr->val1 = isds_2536030320001_accel_odr_list[odr_index].val1; + odr->val2 = isds_2536030320001_accel_odr_list[odr_index].val2; + + return 0; +} + +/* Set gyroscope output data rate. See isds_2536030320001_gyro_odr_list for allowed values. */ +static int isds_2536030320001_gyro_odr_set(const struct device *dev, const struct sensor_value *odr) +{ + struct isds_2536030320001_data *data = dev->data; + int odr_index; + + for (odr_index = 0; odr_index < ARRAY_SIZE(isds_2536030320001_gyro_odr_list); odr_index++) { + if (odr->val1 == isds_2536030320001_gyro_odr_list[odr_index].val1 && + odr->val2 == isds_2536030320001_gyro_odr_list[odr_index].val2) { + break; + } + } + + if (odr_index == ARRAY_SIZE(isds_2536030320001_gyro_odr_list)) { + /* ODR not allowed (was not found in isds_2536030320001_gyro_odr_list) */ + LOG_ERR("Bad sampling frequency %d.%d", odr->val1, odr->val2); + return -EINVAL; + } + + if (ISDS_setGyroOutputDataRate(&data->sensor_interface, + (ISDS_gyroOutputDataRate_t)odr_index) != WE_SUCCESS) { + LOG_ERR("Failed to set gyroscope output data rate"); + return -EIO; + } + + data->gyro_odr = (ISDS_gyroOutputDataRate_t)odr_index; + + return 0; +} + +/* Get gyroscope output data rate. See isds_2536030320001_gyro_odr_list for allowed values. */ +static int isds_2536030320001_gyro_odr_get(const struct device *dev, struct sensor_value *odr) +{ + struct isds_2536030320001_data *data = dev->data; + ISDS_gyroOutputDataRate_t odr_index; + + if (ISDS_getGyroOutputDataRate(&data->sensor_interface, &odr_index) != WE_SUCCESS) { + LOG_ERR("Failed to get output data rate"); + return -EIO; + } + + data->gyro_odr = odr_index; + + odr->val1 = isds_2536030320001_gyro_odr_list[odr_index].val1; + odr->val2 = isds_2536030320001_gyro_odr_list[odr_index].val2; + + return 0; +} + +/* + * Set accelerometer full scale (measurement range). See isds_2536030320001_accel_full_scale_list + * for allowed values. + */ +static int isds_2536030320001_accel_full_scale_set(const struct device *dev, + const struct sensor_value *fs) +{ + struct isds_2536030320001_data *data = dev->data; + + uint8_t scaleg = (uint8_t)sensor_ms2_to_g(fs); + + uint8_t idx; + + for (idx = 0; idx < ARRAY_SIZE(isds_2536030320001_accel_full_scale_list); idx++) { + if (isds_2536030320001_accel_full_scale_list[idx] == scaleg) { + break; + } + } + + if (idx == ARRAY_SIZE(isds_2536030320001_accel_full_scale_list)) { + /* fullscale not allowed (was not found in isds_2536030320001_accel_full_scale_list) + */ + LOG_ERR("Bad scale %d", scaleg); + return -EINVAL; + } + + if (ISDS_setAccFullScale(&data->sensor_interface, (ISDS_accFullScale_t)idx) != WE_SUCCESS) { + LOG_ERR("Failed to set accelerometer full scale."); + return -EIO; + } + + data->accel_range = (ISDS_accFullScale_t)idx; + + return 0; +} + +/* + * Get accelerometer full scale (measurement range). See isds_2536030320001_accel_full_scale_list + * for allowed values. + */ +static int isds_2536030320001_accel_full_scale_get(const struct device *dev, + struct sensor_value *fs) +{ + struct isds_2536030320001_data *data = dev->data; + + ISDS_accFullScale_t accel_fs; + + if (ISDS_getAccFullScale(&data->sensor_interface, &accel_fs) != WE_SUCCESS) { + LOG_ERR("Failed to get full scale"); + return -EIO; + } + + data->accel_range = accel_fs; + + fs->val1 = isds_2536030320001_accel_full_scale_list[accel_fs]; + fs->val2 = 0; + + return 0; +} + +/* + * Set gyroscope full scale (measurement range). See isds_2536030320001_gyro_full_scale_list for + * allowed values. + */ +static int isds_2536030320001_gyro_full_scale_set(const struct device *dev, + const struct sensor_value *fs) +{ + struct isds_2536030320001_data *data = dev->data; + + uint16_t scale_dps = (uint16_t)sensor_rad_to_degrees(fs); + + uint8_t idx; + + for (idx = 0; idx < ARRAY_SIZE(isds_2536030320001_gyro_full_scale_list); idx++) { + if (isds_2536030320001_gyro_full_scale_list[idx] == scale_dps) { + break; + } + } + + if (idx == ARRAY_SIZE(isds_2536030320001_gyro_full_scale_list)) { + /* fullscale not allowed (was not found in isds_2536030320001_gyro_full_scale_list) + */ + LOG_ERR("Bad scale %d", scale_dps); + return -EINVAL; + } + + if (ISDS_setGyroFullScale(&data->sensor_interface, (ISDS_gyroFullScale_t)idx) != + WE_SUCCESS) { + LOG_ERR("Failed to set gyroscope full scale."); + return -EIO; + } + + data->gyro_range = (ISDS_gyroFullScale_t)idx; + + return 0; +} + +/* + * Get gyroscope full scale (measurement range). See isds_2536030320001_gyro_full_scale_list for + * allowed values. + */ +static int isds_2536030320001_gyro_full_scale_get(const struct device *dev, struct sensor_value *fs) +{ + struct isds_2536030320001_data *data = dev->data; + + ISDS_gyroFullScale_t gyro_fs; + + if (ISDS_getGyroFullScale(&data->sensor_interface, &gyro_fs) != WE_SUCCESS) { + LOG_ERR("Failed to get full scale"); + return -EIO; + } + + data->gyro_range = gyro_fs; + + fs->val1 = isds_2536030320001_gyro_full_scale_list[gyro_fs]; + fs->val2 = 0; + + return 0; +} + +static int isds_2536030320001_attr_set(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, const struct sensor_value *val) +{ + switch (attr) { + case SENSOR_ATTR_SAMPLING_FREQUENCY: + switch (chan) { + case SENSOR_CHAN_ACCEL_XYZ: + return isds_2536030320001_accel_odr_set(dev, val); + case SENSOR_CHAN_GYRO_XYZ: + return isds_2536030320001_gyro_odr_set(dev, val); + default: + break; + } + break; + case SENSOR_ATTR_FULL_SCALE: + switch (chan) { + case SENSOR_CHAN_ACCEL_XYZ: + return isds_2536030320001_accel_full_scale_set(dev, val); + case SENSOR_CHAN_GYRO_XYZ: + return isds_2536030320001_gyro_full_scale_set(dev, val); + default: + break; + } + break; + default: + break; + } + + LOG_ERR("attr_set() is not supported on channel %d.", chan); + return -ENOTSUP; +} + +static int isds_2536030320001_attr_get(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, struct sensor_value *val) +{ + + if (val == NULL) { + LOG_WRN("address of passed value is NULL."); + return -EFAULT; + } + + switch (attr) { + case SENSOR_ATTR_SAMPLING_FREQUENCY: + switch (chan) { + case SENSOR_CHAN_ACCEL_XYZ: + return isds_2536030320001_accel_odr_get(dev, val); + case SENSOR_CHAN_GYRO_XYZ: + return isds_2536030320001_gyro_odr_get(dev, val); + default: + break; + } + break; + case SENSOR_ATTR_FULL_SCALE: + switch (chan) { + case SENSOR_CHAN_ACCEL_XYZ: + return isds_2536030320001_accel_full_scale_get(dev, val); + case SENSOR_CHAN_GYRO_XYZ: + return isds_2536030320001_gyro_full_scale_get(dev, val); + default: + break; + } + break; + default: + break; + } + + LOG_ERR("attr_get() is not supported on channel %d.", chan); + return -ENOTSUP; +} + +static DEVICE_API(sensor, isds_2536030320001_driver_api) = { + .attr_set = isds_2536030320001_attr_set, + .attr_get = isds_2536030320001_attr_get, +#if CONFIG_WSEN_ISDS_2536030320001_TRIGGER + .trigger_set = isds_2536030320001_trigger_set, +#endif + .sample_fetch = isds_2536030320001_sample_fetch, + .channel_get = isds_2536030320001_channel_get, +}; + +static int isds_2536030320001_init(const struct device *dev) +{ + const struct isds_2536030320001_config *config = dev->config; + struct isds_2536030320001_data *data = dev->data; + struct sensor_value accel_range, gyro_range; + uint8_t device_id; + ISDS_state_t sw_reset; + + /* Initialize WE sensor interface */ + WE_sensorInterfaceType_t interface_type = data->sensor_interface.interfaceType; + + ISDS_getDefaultInterface(&data->sensor_interface); + data->sensor_interface.interfaceType = interface_type; + + switch (data->sensor_interface.interfaceType) { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + case WE_i2c: + if (!i2c_is_ready_dt(&config->bus_cfg.i2c)) { + LOG_ERR("I2C bus device not ready"); + return -ENODEV; + } + data->sensor_interface.handle = (void *)&config->bus_cfg.i2c; + break; +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + case WE_spi: + if (!spi_is_ready_dt(&config->bus_cfg.spi)) { + LOG_ERR("SPI bus device not ready"); + return -ENODEV; + } + data->sensor_interface.handle = (void *)&config->bus_cfg.spi; + break; +#endif + default: + LOG_ERR("Invalid interface type"); + return -EINVAL; + } + + /* First communication test - check device ID */ + if (ISDS_getDeviceID(&data->sensor_interface, &device_id) != WE_SUCCESS) { + LOG_ERR("Failed to read device ID."); + return -EIO; + } + + if (device_id != ISDS_DEVICE_ID_VALUE) { + LOG_ERR("Invalid device ID 0x%x.", device_id); + return -EINVAL; + } + + /* Perform soft reset of the sensor */ + ISDS_softReset(&data->sensor_interface, ISDS_enable); + + k_sleep(K_USEC(5)); + + do { + if (ISDS_getSoftResetState(&data->sensor_interface, &sw_reset) != WE_SUCCESS) { + LOG_ERR("Failed to get sensor reset state."); + return -EIO; + } + } while (sw_reset); + + if (isds_2536030320001_accel_odr_set( + dev, &isds_2536030320001_accel_odr_list[config->accel_odr]) < 0) { + LOG_ERR("Failed to set odr"); + return -EIO; + } + + if (isds_2536030320001_gyro_odr_set( + dev, &isds_2536030320001_gyro_odr_list[config->gyro_odr]) < 0) { + LOG_ERR("Failed to set odr"); + return -EIO; + } + + if (ISDS_enableAutoIncrement(&data->sensor_interface, ISDS_enable) != WE_SUCCESS) { + LOG_ERR("Failed to enable auto increment."); + return -EIO; + } + + if (ISDS_enableBlockDataUpdate(&data->sensor_interface, ISDS_enable) != WE_SUCCESS) { + LOG_ERR("Failed to enable block data update."); + return -EIO; + } + + sensor_g_to_ms2((int32_t)config->accel_range, &accel_range); + + if (isds_2536030320001_accel_full_scale_set(dev, &accel_range) < 0) { + LOG_ERR("Failed to set full scale"); + return -EIO; + } + + sensor_degrees_to_rad((int32_t)config->gyro_range, &gyro_range); + + if (isds_2536030320001_gyro_full_scale_set(dev, &gyro_range) < 0) { + LOG_ERR("Failed to set full scale"); + return -EIO; + } + +#if CONFIG_WSEN_ISDS_2536030320001_DISABLE_ACCEL_HIGH_PERFORMANCE_MODE + if (ISDS_disableAccHighPerformanceMode(&data->sensor_interface, ISDS_enable) != + WE_SUCCESS) { + LOG_ERR("Failed to disable accelerometer high performance mode."); + return -EIO; + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_DISABLE_ACCEL_HIGH_PERFORMANCE_MODE */ + +#if CONFIG_WSEN_ISDS_2536030320001_DISABLE_GYRO_HIGH_PERFORMANCE_MODE + if (ISDS_disableGyroHighPerformanceMode(&data->sensor_interface, ISDS_enable) != + WE_SUCCESS) { + LOG_ERR("Failed to disable gyroscope high performance mode."); + return -EIO; + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_DISABLE_GYRO_HIGH_PERFORMANCE_MODE */ + +#if CONFIG_WSEN_ISDS_2536030320001_TRIGGER + if (isds_2536030320001_init_interrupt(dev) < 0) { + LOG_ERR("Failed to initialize interrupt(s)."); + return -EIO; + } +#endif + + return 0; +} + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TRIGGER +#define ISDS_2536030320001_CFG_EVENTS_IRQ(inst) \ + .events_interrupt_gpio = GPIO_DT_SPEC_INST_GET(inst, events_interrupt_gpios), +#define ISDS_2536030320001_CFG_DRDY_IRQ(inst) \ + .drdy_interrupt_gpio = GPIO_DT_SPEC_INST_GET(inst, drdy_interrupt_gpios), +#else +#define ISDS_2536030320001_CFG_EVENTS_IRQ(inst) +#define ISDS_2536030320001_CFG_DRDY_IRQ(inst) +#endif /* CONFIG_WSEN_ISDS_2536030320001_TRIGGER */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TAP +#define ISDS_2536030320001_CONFIG_TAP(inst) \ + .tap_mode = DT_INST_PROP(inst, tap_mode), \ + .tap_threshold = DT_INST_PROP(inst, tap_threshold), \ + .tap_axis_enable = DT_INST_PROP(inst, tap_axis_enable), \ + .tap_shock = DT_INST_PROP(inst, tap_shock), \ + .tap_latency = DT_INST_PROP(inst, tap_latency), \ + .tap_quiet = DT_INST_PROP(inst, tap_quiet), +#else +#define ISDS_2536030320001_CONFIG_TAP(inst) +#endif /* CONFIG_WSEN_ISDS_2536030320001_TAP */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_FREEFALL +#define ISDS_2536030320001_CONFIG_FREEFALL(inst) \ + .freefall_duration = DT_INST_PROP(inst, freefall_duration), \ + .freefall_threshold = \ + (ISDS_freeFallThreshold_t)DT_INST_ENUM_IDX(inst, freefall_threshold), +#else +#define ISDS_2536030320001_CONFIG_FREEFALL(inst) +#endif /* CONFIG_WSEN_ISDS_2536030320001_FREEFALL */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_DELTA +#define ISDS_2536030320001_CONFIG_DELTA(inst) \ + .delta_threshold = DT_INST_PROP(inst, delta_threshold), \ + .delta_duration = DT_INST_PROP(inst, delta_duration), +#else +#define ISDS_2536030320001_CONFIG_DELTA(inst) +#endif /* CONFIG_WSEN_ISDS_2536030320001_DELTA */ + +/* clang-format off */ + +#define ISDS_2536030320001_CONFIG_COMMON(inst) \ + .accel_odr = (ISDS_accOutputDataRate_t)(DT_INST_ENUM_IDX(inst, accel_odr)), \ + .gyro_odr = (ISDS_gyroOutputDataRate_t)(DT_INST_ENUM_IDX(inst, gyro_odr)), \ + .accel_range = DT_INST_PROP(inst, accel_range), \ + .gyro_range = DT_INST_PROP(inst, gyro_range), \ + ISDS_2536030320001_CONFIG_TAP(inst) \ + ISDS_2536030320001_CONFIG_FREEFALL(inst) \ + ISDS_2536030320001_CONFIG_DELTA(inst) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, events_interrupt_gpios), \ + (ISDS_2536030320001_CFG_EVENTS_IRQ(inst)), ()) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, drdy_interrupt_gpios), \ + (ISDS_2536030320001_CFG_DRDY_IRQ(inst)), ()) + +/* clang-format on */ + +/* + * Instantiation macros used when device is on SPI bus. + */ + +#define ISDS_2536030320001_SPI_OPERATION \ + (SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA) + +#define ISDS_2536030320001_CONFIG_SPI(inst) \ + {.bus_cfg = \ + { \ + .spi = SPI_DT_SPEC_INST_GET(inst, ISDS_2536030320001_SPI_OPERATION, 0), \ + }, \ + ISDS_2536030320001_CONFIG_COMMON(inst)} + +/* + * Instantiation macros used when device is on I2C bus. + */ + +#define ISDS_2536030320001_CONFIG_I2C(inst) \ + {.bus_cfg = \ + { \ + .i2c = I2C_DT_SPEC_INST_GET(inst), \ + }, \ + ISDS_2536030320001_CONFIG_COMMON(inst)} + +/* clang-format off */ + +/* + * Main instantiation macro. Use of COND_CODE_1() selects the right + * bus-specific macro at preprocessor time. + */ +#define ISDS_2536030320001_DEFINE(inst) \ + static struct isds_2536030320001_data isds_2536030320001_data_##inst = \ + COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \ + ({ .sensor_interface = { .interfaceType = WE_i2c } }), ()) \ + COND_CODE_1(DT_INST_ON_BUS(inst, spi), \ + ({ .sensor_interface = { .interfaceType = WE_spi } }), ()); \ + static const struct isds_2536030320001_config isds_2536030320001_config_##inst = \ + COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \ + (ISDS_2536030320001_CONFIG_I2C(inst)), ()) \ + COND_CODE_1(DT_INST_ON_BUS(inst, spi), \ + (ISDS_2536030320001_CONFIG_SPI(inst)), ()); \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, \ + isds_2536030320001_init, \ + NULL, \ + &isds_2536030320001_data_##inst, \ + &isds_2536030320001_config_##inst, \ + POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, \ + &isds_2536030320001_driver_api) + +/* clang-format on */ + +DT_INST_FOREACH_STATUS_OKAY(ISDS_2536030320001_DEFINE) diff --git a/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001.h b/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001.h new file mode 100644 index 0000000000000..baf3fd131f28f --- /dev/null +++ b/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_WSEN_ISDS_2536030320001_WSEN_ISDS_2536030320001_H_ +#define ZEPHYR_DRIVERS_SENSOR_WSEN_ISDS_2536030320001_WSEN_ISDS_2536030320001_H_ + +#include +#include + +#include + +#include "WSEN_ISDS_2536030320001_hal.h" + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ + +struct isds_2536030320001_data { + /* WE sensor interface configuration */ + WE_sensorInterface_t sensor_interface; + + /* Last acceleration samples */ + int16_t acceleration_x; + int16_t acceleration_y; + int16_t acceleration_z; + + /* Last angular rate samples */ + int32_t rate_x; + int32_t rate_y; + int32_t rate_z; + + /* Last temperature sample */ + int16_t temperature; + + ISDS_accOutputDataRate_t accel_odr; + ISDS_gyroOutputDataRate_t gyro_odr; + + ISDS_accFullScale_t accel_range; + ISDS_gyroFullScale_t gyro_range; + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TRIGGER + const struct device *dev; + + /* Callback for interrupts */ + struct gpio_callback drdy_interrupt_cb; + +#ifdef CONFIG_WSEN_ISDS_2536030320001_EVENTS + struct gpio_callback events_interrupt_cb; +#endif + + /* Registered trigger handlers */ + sensor_trigger_handler_t accel_data_ready_handler; + sensor_trigger_handler_t gyro_data_ready_handler; + sensor_trigger_handler_t temp_data_ready_handler; + sensor_trigger_handler_t single_tap_handler; + sensor_trigger_handler_t double_tap_handler; + sensor_trigger_handler_t freefall_handler; + sensor_trigger_handler_t delta_handler; + + const struct sensor_trigger *accel_data_ready_trigger; + const struct sensor_trigger *gyro_data_ready_trigger; + const struct sensor_trigger *temp_data_ready_trigger; + const struct sensor_trigger *single_tap_trigger; + const struct sensor_trigger *double_tap_trigger; + const struct sensor_trigger *freefall_trigger; + const struct sensor_trigger *delta_trigger; + +#if defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(drdy_thread_stack, CONFIG_WSEN_ISDS_2536030320001_THREAD_STACK_SIZE); + struct k_thread drdy_thread; + struct k_sem drdy_sem; +#ifdef CONFIG_WSEN_ISDS_2536030320001_EVENTS + K_KERNEL_STACK_MEMBER(events_thread_stack, + CONFIG_WSEN_ISDS_2536030320001_THREAD_STACK_SIZE); + struct k_thread events_thread; + struct k_sem events_sem; +#endif +#elif defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD) + struct k_work drdy_work; +#ifdef CONFIG_WSEN_ISDS_2536030320001_EVENTS + struct k_work events_work; +#endif +#endif +#endif /* CONFIG_WSEN_ISDS_2536030320001_TRIGGER */ +}; + +struct isds_2536030320001_config { + union { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + const struct i2c_dt_spec i2c; +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + const struct spi_dt_spec spi; +#endif + } bus_cfg; + + /* Output data rates */ + ISDS_accOutputDataRate_t accel_odr; + ISDS_gyroOutputDataRate_t gyro_odr; + + /* Measurement ranges (full scale) */ + uint8_t accel_range; + uint16_t gyro_range; + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TRIGGER + /* Interrupt pin (used for data-ready, tap, free-fall, delta/wake-up) */ + const struct gpio_dt_spec events_interrupt_gpio; + const struct gpio_dt_spec drdy_interrupt_gpio; + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TAP + uint8_t tap_mode; + uint8_t tap_threshold; + uint8_t tap_axis_enable[3]; + uint8_t tap_shock; + uint8_t tap_latency; + uint8_t tap_quiet; +#endif /* CONFIG_WSEN_ISDS_2536030320001_TAP */ +#ifdef CONFIG_WSEN_ISDS_2536030320001_FREEFALL + uint8_t freefall_duration; + ISDS_freeFallThreshold_t freefall_threshold; +#endif /* CONFIG_WSEN_ISDS_2536030320001_FREEFALL */ +#ifdef CONFIG_WSEN_ISDS_2536030320001_DELTA + uint8_t delta_threshold; + uint8_t delta_duration; +#endif /* CONFIG_WSEN_ISDS_2536030320001_DELTA */ +#endif /* CONFIG_WSEN_ISDS_2536030320001_TRIGGER */ +}; + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TRIGGER +int isds_2536030320001_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); + +int isds_2536030320001_init_interrupt(const struct device *dev); +#endif /* CONFIG_WSEN_ISDS_2536030320001_TRIGGER */ + +#endif /* ZEPHYR_DRIVERS_SENSOR_WSEN_ISDS_2536030320001_WSEN_ISDS_2536030320001_H_ */ diff --git a/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001_trigger.c b/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001_trigger.c new file mode 100644 index 0000000000000..da51d40862a34 --- /dev/null +++ b/drivers/sensor/wsen/wsen_isds_2536030320001/wsen_isds_2536030320001_trigger.c @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT we_wsen_isds_2536030320001 + +#include + +#include "wsen_isds_2536030320001.h" + +LOG_MODULE_DECLARE(WSEN_ISDS_2536030320001, CONFIG_SENSOR_LOG_LEVEL); + +/* Enable/disable interrupt handling for data-ready, tap, free-fall, delta/wake-up */ +static inline int isds_2536030320001_setup_interrupt(const struct device *dev, + const struct gpio_dt_spec *pin, bool enable) +{ + unsigned int flags = enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE; + + return gpio_pin_interrupt_configure_dt(pin, flags); +} + +static inline void isds_2536030320001_handle_interrupt_1(const struct device *dev) +{ + struct isds_2536030320001_data *data = dev->data; + const struct isds_2536030320001_config *cfg = dev->config; + + /* Disable interrupt handling until the interrupt has been processed */ + isds_2536030320001_setup_interrupt(data->dev, &cfg->drdy_interrupt_gpio, false); + +#if defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD) + k_sem_give(&data->drdy_sem); +#elif defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD) + k_work_submit(&data->drdy_work); +#endif +} + +static void isds_2536030320001_process_interrupt_1(const struct device *dev) +{ + struct isds_2536030320001_data *data = dev->data; + const struct isds_2536030320001_config *cfg = dev->config; + ISDS_status_t status_reg; + + if (ISDS_getStatusRegister(&data->sensor_interface, &status_reg) != WE_SUCCESS) { + LOG_ERR("Failed to read status register"); + return; + } + + if (data->accel_data_ready_handler && status_reg.accDataReady) { + data->accel_data_ready_handler(dev, data->accel_data_ready_trigger); + } + + if (data->gyro_data_ready_handler && status_reg.gyroDataReady) { + data->gyro_data_ready_handler(dev, data->gyro_data_ready_trigger); + } + + if (data->temp_data_ready_handler && status_reg.tempDataReady) { + data->temp_data_ready_handler(dev, data->temp_data_ready_trigger); + } + + /* Re-enable interrupt handling */ + isds_2536030320001_setup_interrupt(dev, &cfg->drdy_interrupt_gpio, true); +} + +/* + * Is called when interrupt on INT1. + * Triggers asynchronous handling of interrupt in isds_2536030320001_process_interrupt(). + */ +static void isds_2536030320001_interrupt_1_gpio_callback(const struct device *dev, + struct gpio_callback *cb, uint32_t pins) +{ + struct isds_2536030320001_data *data = + CONTAINER_OF(cb, struct isds_2536030320001_data, drdy_interrupt_cb); + + ARG_UNUSED(pins); + + isds_2536030320001_handle_interrupt_1(data->dev); +} + +#ifdef CONFIG_WSEN_ISDS_2536030320001_EVENTS +static inline void isds_2536030320001_handle_interrupt_0(const struct device *dev) +{ + struct isds_2536030320001_data *data = dev->data; + const struct isds_2536030320001_config *cfg = dev->config; + + /* Disable interrupt handling until the interrupt has been processed */ + isds_2536030320001_setup_interrupt(data->dev, &cfg->events_interrupt_gpio, false); + +#if defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD) + k_sem_give(&data->events_sem); +#elif defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD) + k_work_submit(&data->events_work); +#endif +} + +/* Asynchronous handling of interrupt triggered in isds_2536030320001_gpio_callback() */ +static void isds_2536030320001_process_interrupt_0(const struct device *dev) +{ + struct isds_2536030320001_data *data = dev->data; + const struct isds_2536030320001_config *cfg = dev->config; + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TAP + ISDS_tapEvent_t tap_event; + /* Read tap event register to find out if a tap event interrupt occurred. */ + if (ISDS_getTapEventRegister(&data->sensor_interface, &tap_event) != WE_SUCCESS) { + LOG_ERR("Failed to read tap event register"); + return; + } + + if (data->single_tap_handler && tap_event.singleState) { + data->single_tap_handler(dev, data->single_tap_trigger); + } + + if (data->double_tap_handler && tap_event.doubleState) { + data->double_tap_handler(dev, data->double_tap_trigger); + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_TAP */ + +#if defined(CONFIG_WSEN_ISDS_2536030320001_FREEFALL) || \ + defined(CONFIG_WSEN_ISDS_2536030320001_DELTA) + + ISDS_wakeUpEvent_t wake_up_event; + /* Read wake-up event register to find out if freefall or wake-up interrupt occurred. */ + if (ISDS_getWakeUpEventRegister(&data->sensor_interface, &wake_up_event) != WE_SUCCESS) { + LOG_ERR("Failed to read wake-up event register"); + return; + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_FREEFALL || CONFIG_WSEN_ISDS_2536030320001_DELTA */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_FREEFALL + if (data->freefall_handler && wake_up_event.freeFallState) { + data->freefall_handler(dev, data->freefall_trigger); + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_FREEFALL */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_DELTA + if (data->delta_handler && wake_up_event.wakeUpState) { + data->delta_handler(dev, data->delta_trigger); + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_DELTA */ + + /* Re-enable interrupt handling */ + isds_2536030320001_setup_interrupt(dev, &cfg->events_interrupt_gpio, true); +} + +/* + * Is called when interrupt on INT0. + * Triggers asynchronous handling of interrupt in isds_2536030320001_process_interrupt(). + */ +static void isds_2536030320001_interrupt_0_gpio_callback(const struct device *dev, + struct gpio_callback *cb, uint32_t pins) +{ + struct isds_2536030320001_data *data = + CONTAINER_OF(cb, struct isds_2536030320001_data, events_interrupt_cb); + + ARG_UNUSED(pins); + + isds_2536030320001_handle_interrupt_0(data->dev); +} + +#endif /* CONFIG_WSEN_ISDS_2536030320001_EVENTS */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD +static void isds_2536030320001_drdy_thread(void *p1, void *p2, void *p3) +{ + ARG_UNUSED(p2); + ARG_UNUSED(p3); + + struct isds_2536030320001_data *data = p1; + + while (true) { + k_sem_take(&data->drdy_sem, K_FOREVER); + isds_2536030320001_process_interrupt_1(data->dev); + } +} +#ifdef CONFIG_WSEN_ISDS_2536030320001_EVENTS +static void isds_2536030320001_events_thread(void *p1, void *p2, void *p3) +{ + ARG_UNUSED(p2); + ARG_UNUSED(p3); + + struct isds_2536030320001_data *data = p1; + + while (true) { + k_sem_take(&data->events_sem, K_FOREVER); + isds_2536030320001_process_interrupt_0(data->dev); + } +} +#endif /* CONFIG_WSEN_ISDS_2536030320001_EVENTS */ +#endif /* CONFIG_WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD +static void isds_2536030320001_drdy_work_cb(struct k_work *work) +{ + struct isds_2536030320001_data *isds_2536030320001 = + CONTAINER_OF(work, struct isds_2536030320001_data, drdy_work); + + isds_2536030320001_process_interrupt_1(isds_2536030320001->dev); +} + +#ifdef CONFIG_WSEN_ISDS_2536030320001_EVENTS +static void isds_2536030320001_events_work_cb(struct k_work *work) +{ + struct isds_2536030320001_data *isds_2536030320001 = + CONTAINER_OF(work, struct isds_2536030320001_data, events_work); + + isds_2536030320001_process_interrupt_0(isds_2536030320001->dev); +} +#endif /* CONFIG_WSEN_ISDS_2536030320001_EVENTS */ +#endif /* CONFIG_WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD */ + +/* (Un)register trigger handler and enable/disable the corresponding sensor interrupt */ +int isds_2536030320001_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler) +{ + struct isds_2536030320001_data *data = dev->data; + const struct isds_2536030320001_config *cfg = dev->config; + + ISDS_state_t state = (handler != NULL) ? ISDS_enable : ISDS_disable; + + switch (trig->type) { + case SENSOR_TRIG_DATA_READY: { + int16_t x, y, z; + + switch (trig->chan) { + case SENSOR_CHAN_ACCEL_X: + case SENSOR_CHAN_ACCEL_Y: + case SENSOR_CHAN_ACCEL_Z: + case SENSOR_CHAN_ACCEL_XYZ: { + data->accel_data_ready_handler = handler; + data->accel_data_ready_trigger = trig; + isds_2536030320001_setup_interrupt(dev, &cfg->drdy_interrupt_gpio, + data->accel_data_ready_handler || + data->gyro_data_ready_handler || + data->temp_data_ready_handler); + if (state) { + /* Dummy read: re-trigger interrupt */ + ISDS_getRawAccelerations(&data->sensor_interface, &x, &y, &z); + } + if (ISDS_enableAccDataReadyINT1(&data->sensor_interface, state) != + WE_SUCCESS) { + return -EIO; + } + break; + } + case SENSOR_CHAN_GYRO_X: + case SENSOR_CHAN_GYRO_Y: + case SENSOR_CHAN_GYRO_Z: + case SENSOR_CHAN_GYRO_XYZ: { + data->gyro_data_ready_handler = handler; + data->gyro_data_ready_trigger = trig; + isds_2536030320001_setup_interrupt(dev, &cfg->drdy_interrupt_gpio, + data->accel_data_ready_handler || + data->gyro_data_ready_handler || + data->temp_data_ready_handler); + if (state) { + /* Dummy read: re-trigger interrupt */ + ISDS_getRawAngularRates(&data->sensor_interface, &x, &y, &z); + } + if (ISDS_enableGyroDataReadyINT1(&data->sensor_interface, state) != + WE_SUCCESS) { + return -EIO; + } + break; + } + case SENSOR_CHAN_AMBIENT_TEMP: { + data->temp_data_ready_handler = handler; + data->temp_data_ready_trigger = trig; + isds_2536030320001_setup_interrupt(dev, &cfg->drdy_interrupt_gpio, + data->accel_data_ready_handler || + data->gyro_data_ready_handler || + data->temp_data_ready_handler); + if (state) { + /* Dummy read: re-trigger interrupt */ + ISDS_getRawTemperature(&data->sensor_interface, &x); + } + if (ISDS_enableTemperatureDataReadyINT1(&data->sensor_interface, state) != + WE_SUCCESS) { + return -EIO; + } + break; + } + default: + goto error; + } + return 0; + } +#ifdef CONFIG_WSEN_ISDS_2536030320001_TAP + case SENSOR_TRIG_TAP: + if (trig->chan != SENSOR_CHAN_ALL) { + break; + } + data->single_tap_handler = handler; + data->single_tap_trigger = trig; + isds_2536030320001_setup_interrupt( + dev, &cfg->events_interrupt_gpio, + data->single_tap_handler || data->double_tap_handler || + data->freefall_handler || data->delta_handler); + if (ISDS_enableSingleTapINT0(&data->sensor_interface, state) != WE_SUCCESS) { + return -EIO; + } + return 0; + case SENSOR_TRIG_DOUBLE_TAP: + if (trig->chan != SENSOR_CHAN_ALL) { + break; + } + data->double_tap_handler = handler; + data->double_tap_trigger = trig; + isds_2536030320001_setup_interrupt( + dev, &cfg->events_interrupt_gpio, + data->single_tap_handler || data->double_tap_handler || + data->freefall_handler || data->delta_handler); + if (ISDS_enableDoubleTapINT0(&data->sensor_interface, state) != WE_SUCCESS) { + return -EIO; + } + return 0; +#endif /* CONFIG_WSEN_ISDS_2536030320001_TAP */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_FREEFALL + case SENSOR_TRIG_FREEFALL: + if (trig->chan != SENSOR_CHAN_ALL) { + break; + } + data->freefall_handler = handler; + data->freefall_trigger = trig; + isds_2536030320001_setup_interrupt( + dev, &cfg->events_interrupt_gpio, + data->single_tap_handler || data->double_tap_handler || + data->freefall_handler || data->delta_handler); + if (ISDS_enableFreeFallINT0(&data->sensor_interface, state) != WE_SUCCESS) { + return -EIO; + } + return 0; +#endif /* CONFIG_WSEN_ISDS_2536030320001_FREEFALL */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_DELTA + case SENSOR_TRIG_DELTA: + if (trig->chan != SENSOR_CHAN_ALL) { + break; + } + data->delta_handler = handler; + data->delta_trigger = trig; + isds_2536030320001_setup_interrupt( + dev, &cfg->events_interrupt_gpio, + data->single_tap_handler || data->double_tap_handler || + data->freefall_handler || data->delta_handler); + if (ISDS_enableWakeUpINT0(&data->sensor_interface, state) != WE_SUCCESS) { + return -EIO; + } + return 0; +#endif /* CONFIG_WSEN_ISDS_2536030320001_DELTA */ + default: + break; + } + +error: + LOG_ERR("Unsupported sensor trigger"); + return -ENOTSUP; +} + +int isds_2536030320001_init_interrupt(const struct device *dev) +{ + struct isds_2536030320001_data *data = dev->data; + const struct isds_2536030320001_config *cfg = dev->config; + + data->dev = dev; + + if (cfg->drdy_interrupt_gpio.port == NULL) { + LOG_ERR("drdy-interrupt-gpios is not defined in the device tree."); + return -EINVAL; + } + + if (!gpio_is_ready_dt(&cfg->drdy_interrupt_gpio)) { + LOG_ERR("Device %s is not ready", cfg->drdy_interrupt_gpio.port->name); + return -ENODEV; + } + + /* Setup interrupt gpio */ + if (gpio_pin_configure_dt(&cfg->drdy_interrupt_gpio, GPIO_INPUT) < 0) { + LOG_ERR("Failed to configure %s.%02u", cfg->drdy_interrupt_gpio.port->name, + cfg->drdy_interrupt_gpio.pin); + return -EIO; + } + + gpio_init_callback(&data->drdy_interrupt_cb, isds_2536030320001_interrupt_1_gpio_callback, + BIT(cfg->drdy_interrupt_gpio.pin)); + + if (gpio_add_callback(cfg->drdy_interrupt_gpio.port, &data->drdy_interrupt_cb) < 0) { + LOG_ERR("Failed to set gpio callback"); + return -EIO; + } + +#if defined(CONFIG_WSEN_ISDS_2536030320001_EVENTS) + + if (cfg->events_interrupt_gpio.port == NULL) { + LOG_DBG("events-interrupt-gpios is not defined in the device tree."); + return -EINVAL; + } + + if (!gpio_is_ready_dt(&cfg->events_interrupt_gpio)) { + LOG_ERR("Device %s is not ready", cfg->events_interrupt_gpio.port->name); + return -ENODEV; + } + + /* Setup interrupt gpio */ + if (gpio_pin_configure_dt(&cfg->events_interrupt_gpio, GPIO_INPUT) < 0) { + LOG_ERR("Failed to configure %s.%02u", cfg->events_interrupt_gpio.port->name, + cfg->events_interrupt_gpio.pin); + return -EIO; + } + + gpio_init_callback(&data->events_interrupt_cb, isds_2536030320001_interrupt_0_gpio_callback, + BIT(cfg->events_interrupt_gpio.pin)); + + if (gpio_add_callback(cfg->events_interrupt_gpio.port, &data->events_interrupt_cb) < 0) { + LOG_ERR("Failed to set gpio callback"); + return -EIO; + } + +#endif + +#if defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD) + k_sem_init(&data->drdy_sem, 0, K_SEM_MAX_LIMIT); + + k_thread_create(&data->drdy_thread, data->drdy_thread_stack, + CONFIG_WSEN_ISDS_2536030320001_THREAD_STACK_SIZE, + isds_2536030320001_drdy_thread, data, NULL, NULL, + K_PRIO_COOP(CONFIG_WSEN_ISDS_2536030320001_THREAD_PRIORITY), 0, K_NO_WAIT); +#if defined(CONFIG_WSEN_ISDS_2536030320001_EVENTS) + k_sem_init(&data->events_sem, 0, K_SEM_MAX_LIMIT); + + k_thread_create(&data->events_thread, data->events_thread_stack, + CONFIG_WSEN_ISDS_2536030320001_THREAD_STACK_SIZE, + isds_2536030320001_events_thread, data, NULL, NULL, + K_PRIO_COOP(CONFIG_WSEN_ISDS_2536030320001_THREAD_PRIORITY), 0, K_NO_WAIT); +#endif +#elif defined(CONFIG_WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD) + data->drdy_work.handler = isds_2536030320001_drdy_work_cb; +#if defined(CONFIG_WSEN_ISDS_2536030320001_EVENTS) + data->events_work.handler = isds_2536030320001_events_work_cb; +#endif +#endif + + /* Enable interrupt on INT_0/INT_1 in pulsed mode */ + if (ISDS_enableLatchedInterrupt(&data->sensor_interface, ISDS_disable) != WE_SUCCESS) { + LOG_ERR("Failed to disable latched mode"); + return -EIO; + } + + /* Enable data-ready interrupt on INT_0/INT_1 in pulsed mode */ + if (ISDS_enableDataReadyPulsed(&data->sensor_interface, ISDS_enable) != WE_SUCCESS) { + LOG_ERR("Failed to enable data-ready pulsed mode"); + return -EIO; + } + + if (ISDS_enableInterrupts(&data->sensor_interface, ISDS_enable) != WE_SUCCESS) { + LOG_ERR("Failed to enable interrupts"); + return -EIO; + } + +#ifdef CONFIG_WSEN_ISDS_2536030320001_TAP + if (cfg->accel_odr < ISDS_accOdr416Hz || cfg->accel_odr >= ISDS_accOdr1Hz6) { + LOG_WRN("The tap recognition feature requires a minimum output data rate " + "of 416 Hz"); + } + + if (ISDS_enableDoubleTapEvent(&data->sensor_interface, + (cfg->tap_mode == 1) ? ISDS_enable : ISDS_disable) != + WE_SUCCESS) { + LOG_ERR("Failed to enable/disable double tap event"); + return -EIO; + } + + if (ISDS_setTapThreshold(&data->sensor_interface, cfg->tap_threshold) != WE_SUCCESS) { + LOG_ERR("Failed to set tap threshold"); + return -EIO; + } + + if (cfg->tap_axis_enable[0] != 0) { + if (ISDS_enableTapX(&data->sensor_interface, ISDS_enable) != WE_SUCCESS) { + LOG_ERR("Failed to enable tap recognition in X direction"); + return -EIO; + } + } + + if (cfg->tap_axis_enable[1] != 0) { + if (ISDS_enableTapY(&data->sensor_interface, ISDS_enable) != WE_SUCCESS) { + LOG_ERR("Failed to enable tap recognition in Y direction"); + return -EIO; + } + } + + if (cfg->tap_axis_enable[2] != 0) { + if (ISDS_enableTapZ(&data->sensor_interface, ISDS_enable) != WE_SUCCESS) { + LOG_ERR("Failed to enable tap recognition in Z direction"); + return -EIO; + } + } + + if (ISDS_setTapShockTime(&data->sensor_interface, cfg->tap_shock) != WE_SUCCESS) { + LOG_ERR("Failed to set tap shock duration"); + return -EIO; + } + + if (ISDS_setTapLatencyTime(&data->sensor_interface, cfg->tap_latency) != WE_SUCCESS) { + LOG_ERR("Failed to set tap latency"); + return -EIO; + } + + if (ISDS_setTapQuietTime(&data->sensor_interface, cfg->tap_quiet) != WE_SUCCESS) { + LOG_ERR("Failed to set tap quiet time"); + return -EIO; + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_TAP */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_FREEFALL + if (ISDS_setFreeFallDuration(&data->sensor_interface, cfg->freefall_duration) != + WE_SUCCESS) { + LOG_ERR("Failed to set free-fall duration"); + return -EIO; + } + + if (ISDS_setFreeFallThreshold(&data->sensor_interface, cfg->freefall_threshold) != + WE_SUCCESS) { + LOG_ERR("Failed to set free-fall threshold"); + return -EIO; + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_FREEFALL */ + +#ifdef CONFIG_WSEN_ISDS_2536030320001_DELTA + if (ISDS_setWakeUpDuration(&data->sensor_interface, cfg->delta_duration) != WE_SUCCESS) { + LOG_ERR("Failed to set wake-up duration"); + return -EIO; + } + + if (ISDS_setWakeUpThreshold(&data->sensor_interface, cfg->delta_threshold) != WE_SUCCESS) { + LOG_ERR("Failed to set wake-up threshold"); + return -EIO; + } +#endif /* CONFIG_WSEN_ISDS_2536030320001_DELTA */ + + return 0; +} diff --git a/drivers/sensor/wsen/wsen_sensors_common.h b/drivers/sensor/wsen/wsen_sensors_common.h new file mode 100644 index 0000000000000..ee4d5d8cb2b41 --- /dev/null +++ b/drivers/sensor/wsen/wsen_sensors_common.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_WSEN_COMMON_H_ +#define ZEPHYR_DRIVERS_SENSOR_WSEN_COMMON_H_ + +#include +#include +#include + +#define MAX_POLL_STEP_COUNT 10 + +static inline bool +wsen_sensor_step_sleep_duration_milli_from_odr_hz(const struct sensor_value *odr_hz, + uint32_t *step_sleep_duation_milli) +{ + if ((odr_hz == NULL) || (step_sleep_duation_milli == NULL)) { + return false; + } + + uint32_t odr_milli = (uint32_t)sensor_value_to_milli(odr_hz); + + if (odr_milli == 0) { + return false; + } + + uint32_t poll_cycle_duration = 1000000000 / odr_milli; + + *step_sleep_duation_milli = poll_cycle_duration / MAX_POLL_STEP_COUNT; + + return true; +} + +#endif /* ZEPHYR_DRIVERS_SENSOR_WSEN_COMMON_H_ */ diff --git a/drivers/serial/uart_bt.c b/drivers/serial/uart_bt.c index f3e3398b35a9d..3ae70465a2eec 100644 --- a/drivers/serial/uart_bt.c +++ b/drivers/serial/uart_bt.c @@ -316,7 +316,7 @@ static int uart_bt_workqueue_init(void) return 0; } -/** The work-queue is shared across all instances, hence we initialize it separatedly */ +/** The work-queue is shared across all instances, hence we initialize it separately */ SYS_INIT(uart_bt_workqueue_init, POST_KERNEL, CONFIG_SERIAL_INIT_PRIORITY); static int uart_bt_init(const struct device *dev) diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c index bf519b041943e..32505a4750cf5 100644 --- a/drivers/serial/uart_esp32.c +++ b/drivers/serial/uart_esp32.c @@ -33,6 +33,10 @@ #include #include #include +#elif defined(CONFIG_SOC_SERIES_ESP32H2) +#include +#include +#include #endif #ifdef CONFIG_UART_ASYNC_API #include diff --git a/drivers/serial/uart_sam0.c b/drivers/serial/uart_sam0.c index 459d7bd633fa2..242076b55d26c 100644 --- a/drivers/serial/uart_sam0.c +++ b/drivers/serial/uart_sam0.c @@ -847,7 +847,7 @@ static int uart_sam0_irq_rx_ready(const struct device *dev) const struct uart_sam0_dev_cfg *config = dev->config; SercomUsart * const regs = config->regs; - return regs->INTFLAG.bit.RXC != 0; + return (regs->INTFLAG.bit.RXC != 0) && (regs->INTENSET.bit.RXC != 0); } static int uart_sam0_fifo_read(const struct device *dev, uint8_t *rx_data, diff --git a/drivers/serial/uart_silabs_usart.c b/drivers/serial/uart_silabs_usart.c index 739628cf78837..1ae9caa48ba08 100644 --- a/drivers/serial/uart_silabs_usart.c +++ b/drivers/serial/uart_silabs_usart.c @@ -982,11 +982,19 @@ static int uart_silabs_configure(const struct device *dev, return -ENOSYS; } + if (cfg->parity > UART_CFG_PARITY_SPACE) { + return -EINVAL; + } + if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_DTR_DSR || cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485) { return -ENOSYS; } + if (cfg->flow_ctrl > UART_CFG_FLOW_CTRL_RS485) { + return -EINVAL; + } + *data->uart_cfg = *cfg; USART_Enable(base, usartDisable); diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c index f81a5f04df0e8..2436d2ca56b35 100644 --- a/drivers/serial/uart_stm32.c +++ b/drivers/serial/uart_stm32.c @@ -1359,6 +1359,16 @@ static void uart_stm32_isr(const struct device *dev) #endif #ifdef CONFIG_UART_ASYNC_API +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + /* If both ASYNC and INTERRUPT modes are supported in this build, + * check whether this instance is currently being used via the + * interrupt-driven API. If it is, do not process interrupt flags + * as the user callback invoked earlier is responsible for that. + */ + if (data->user_cb) { + return; + } +#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ if (LL_USART_IsEnabledIT_IDLE(usart) && LL_USART_IsActiveFlag_IDLE(usart)) { @@ -2214,13 +2224,13 @@ static int uart_stm32_registers_configure(const struct device *dev) /* Wait until TEACK flag is set */ while (!(LL_USART_IsActiveFlag_TEACK(usart))) { } -#endif /* !USART_ISR_TEACK */ +#endif /* USART_ISR_TEACK */ #ifdef USART_ISR_REACK /* Wait until REACK flag is set */ while (!(LL_USART_IsActiveFlag_REACK(usart))) { } -#endif /* !USART_ISR_REACK */ +#endif /* USART_ISR_REACK */ return 0; } @@ -2291,14 +2301,12 @@ static void uart_stm32_suspend_setup(const struct device *dev) LL_USART_ClearFlag_ORE(usart); } -static int uart_stm32_pm_action(const struct device *dev, - enum pm_device_action action) +static int uart_stm32_pm_action(const struct device *dev, enum pm_device_action action) { const struct uart_stm32_config *config = dev->config; struct uart_stm32_data *data = dev->data; int err; - switch (action) { case PM_DEVICE_ACTION_RESUME: /* Set pins to active state */ @@ -2307,21 +2315,34 @@ static int uart_stm32_pm_action(const struct device *dev, return err; } - /* Enable clock */ - err = clock_control_on(data->clock, - (clock_control_subsys_t)&config->pclken[0]); + /* Enable bus clock */ + err = clock_control_on(data->clock, (clock_control_subsys_t)&config->pclken[0]); if (err < 0) { LOG_ERR("Could not enable (LP)UART clock"); return err; } - if ((IS_ENABLED(CONFIG_PM_S2RAM)) && - (!LL_USART_IsEnabled(config->usart))) { + if (!LL_USART_IsEnabled(config->usart)) { /* When exiting low power mode, check whether UART is enabled. - * If not, it means we are exiting Suspend to RAM mode (STM32 - * Standby), and the driver needs to be reinitialized. + * If not, it means the peripheral has been powered down + * by the low-power mode. If suspend-to-RAM is enabled, + * assume the entire SoC has been powered down and do a + * full re-initialization. Otherwise, assume that the + * low-power mode shut down power to the UART but not + * critical peripherals (CPU, GPIO, RCC), which means + * we only have to reconfigure this UART instance. + * + * STOP2 on STM32WLE5 is an example of such low-power mode. */ - uart_stm32_init(dev); + if (IS_ENABLED(CONFIG_PM_S2RAM)) { + err = uart_stm32_init(dev); + } else { + err = uart_stm32_registers_configure(dev); + } + + if (err < 0) { + return err; + } } break; case PM_DEVICE_ACTION_SUSPEND: diff --git a/drivers/spi/spi_esp32_spim.c b/drivers/spi/spi_esp32_spim.c index e214657dccee5..ea4895899ef4d 100644 --- a/drivers/spi/spi_esp32_spim.c +++ b/drivers/spi/spi_esp32_spim.c @@ -163,7 +163,7 @@ static int IRAM_ATTR spi_esp32_transfer(const struct device *dev) /* clean up and prepare SPI hal */ for (size_t i = 0; i < ARRAY_SIZE(hal->hw->data_buf); ++i) { -#ifdef CONFIG_SOC_SERIES_ESP32C6 +#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) hal->hw->data_buf[i].val = 0; #else hal->hw->data_buf[i] = 0; diff --git a/drivers/spi/spi_litex_litespi.c b/drivers/spi/spi_litex_litespi.c index 34608a948ef07..ad78a424adc52 100644 --- a/drivers/spi/spi_litex_litespi.c +++ b/drivers/spi/spi_litex_litespi.c @@ -215,8 +215,8 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con #if SPI_LITEX_ANY_HAS_IRQ if (SPI_LITEX_HAS_IRQ) { - litex_write8(BIT(0), dev_config->master_ev_enable_addr); litex_write8(BIT(0), dev_config->master_ev_pending_addr); + litex_write8(BIT(0), dev_config->master_ev_enable_addr); spi_litex_spi_do_tx(dev); diff --git a/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c index dd954a956ed98..ff7431f0a4c65 100644 --- a/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c +++ b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c @@ -11,6 +11,15 @@ * the driver is going to achieve the zephyr API. */ + /* + * The other spi_nxp_lpspi driver source files also use DT_DRV_COMPAT and it is used by the + * spi_context.h file to determine if the gpio cs code can be removed. + * If DT_DRV_COMPAT is not defined in this file, the gpio cs code may not be removed for this file + * but in the other spi_nxp_lpspi driver source files it may be removed and result in breakage of + * this driver. Do not remove DT_DRV_COMPAT from this file. + */ +#define DT_DRV_COMPAT nxp_lpspi + #include LOG_MODULE_REGISTER(spi_lpspi, CONFIG_SPI_LOG_LEVEL); diff --git a/drivers/spi/spi_renesas_ra.c b/drivers/spi/spi_renesas_ra.c index 182bebd1ee0c1..28dac5d9a9e13 100644 --- a/drivers/spi/spi_renesas_ra.c +++ b/drivers/spi/spi_renesas_ra.c @@ -153,7 +153,23 @@ static int ra_spi_configure(const struct device *dev, const struct spi_config *c data->fsp_config_extend.spi_clksyn = SPI_SSL_MODE_CLK_SYN; } else { data->fsp_config_extend.spi_clksyn = SPI_SSL_MODE_SPI; - data->fsp_config_extend.ssl_select = SPI_SSL_SELECT_SSL0; + switch (config->slave) { + case 0: + data->fsp_config_extend.ssl_select = SPI_SSL_SELECT_SSL0; + break; + case 1: + data->fsp_config_extend.ssl_select = SPI_SSL_SELECT_SSL1; + break; + case 2: + data->fsp_config_extend.ssl_select = SPI_SSL_SELECT_SSL2; + break; + case 3: + data->fsp_config_extend.ssl_select = SPI_SSL_SELECT_SSL3; + break; + default: + LOG_ERR("Invalid SSL"); + return -EINVAL; + } } data->fsp_config.p_extend = &data->fsp_config_extend; @@ -172,15 +188,7 @@ static int ra_spi_configure(const struct device *dev, const struct spi_config *c static bool ra_spi_transfer_ongoing(struct ra_spi_data *data) { -#if defined(CONFIG_SPI_INTERRUPT) return (spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx)); -#else - if (spi_context_total_tx_len(&data->ctx) < spi_context_total_rx_len(&data->ctx)) { - return (spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx)); - } else { - return (spi_context_tx_on(&data->ctx) && spi_context_rx_on(&data->ctx)); - } -#endif } #ifndef CONFIG_SPI_INTERRUPT @@ -826,7 +834,7 @@ static void ra_spi_eri_isr(const struct device *dev) return 0; \ } \ \ - DEVICE_DT_INST_DEFINE(index, spi_ra_init##index, PM_DEVICE_DT_INST_GET(index), \ + DEVICE_DT_INST_DEFINE(index, spi_ra_init##index, NULL, \ &ra_spi_data_##index, &ra_spi_config_##index, PRE_KERNEL_1, \ CONFIG_SPI_INIT_PRIORITY, &ra_spi_driver_api); diff --git a/drivers/spi/spi_renesas_rz_rspi.c b/drivers/spi/spi_renesas_rz_rspi.c index 4b505df50dccb..f5290ce95692b 100644 --- a/drivers/spi/spi_renesas_rz_rspi.c +++ b/drivers/spi/spi_renesas_rz_rspi.c @@ -41,7 +41,6 @@ struct spi_rz_rspi_data { rspi_extended_cfg_t fsp_extend_config; #ifdef CONFIG_SPI_RTIO struct spi_rtio *rtio_ctx; - int rtio_buf_remain; int rtio_tiny_buf_idx; #endif /* CONFIG_SPI_RTIO */ }; @@ -71,6 +70,31 @@ static bool spi_rz_rspi_transfer_ongoing(struct spi_rz_rspi_data *data) } #endif } + +static void spi_rz_rspi_retransmit(const struct device *dev) +{ + struct spi_rz_rspi_data *data = dev->data; + const struct spi_rz_rspi_config *config = dev->config; + + if (data->ctx.rx_len == 0) { + data->data_len = data->ctx.tx_len; + } else if (data->ctx.tx_len == 0) { + data->data_len = data->ctx.rx_len; + } else { + data->data_len = MIN(data->ctx.tx_len, data->ctx.rx_len); + } + + if (data->ctx.tx_buf == NULL) { /* If there is only the rx buffer */ + config->fsp_api->read(data->fsp_ctrl, data->ctx.rx_buf, data->data_len, + data->fsp_ctrl->bit_width); + } else if (data->ctx.rx_buf == NULL) { /* If there is only the tx buffer */ + config->fsp_api->write(data->fsp_ctrl, data->ctx.tx_buf, data->data_len, + data->fsp_ctrl->bit_width); + } else { + config->fsp_api->writeRead(data->fsp_ctrl, data->ctx.tx_buf, data->ctx.rx_buf, + data->data_len, data->fsp_ctrl->bit_width); + } +} #endif /* CONFIG_SPI_RTIO */ #ifdef CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT @@ -93,48 +117,6 @@ static void spi_rz_rspi_eri_isr(const struct device *dev) } #endif /* CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT */ -static void spi_rz_rspi_retransmit(struct spi_rz_rspi_data *data) -{ - const uint8_t *tx = NULL; - uint8_t *rx = NULL; - -#ifdef CONFIG_SPI_RTIO - struct spi_rtio *rtio_ctx = data->rtio_ctx; - struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe; - - switch (sqe->op) { - case RTIO_OP_RX: - rx = sqe->rx.buf++; - break; - case RTIO_OP_TX: - tx = sqe->tx.buf++; - break; - case RTIO_OP_TINY_TX: - data->rtio_tiny_buf_idx++; - tx = &sqe->tiny_tx.buf[data->rtio_tiny_buf_idx]; - break; - case RTIO_OP_TXRX: - rx = sqe->txrx.rx_buf++; - tx = sqe->txrx.tx_buf++; - break; - default: - LOG_ERR("Invalid op %d for sqe %p\n", sqe->op, (void *)sqe); - return; - } -#else - tx = data->ctx.tx_buf; - rx = data->ctx.rx_buf; -#endif - - if (tx == NULL) { /* If there is only the rx buffer */ - R_RSPI_Read(data->fsp_ctrl, rx, 1, data->fsp_ctrl->bit_width); - } else if (rx == NULL) { /* If there is only the tx buffer */ - R_RSPI_Write(data->fsp_ctrl, tx, 1, data->fsp_ctrl->bit_width); - } else { - R_RSPI_WriteRead(data->fsp_ctrl, tx, rx, 1, data->fsp_ctrl->bit_width); - } -} - static void spi_callbacks(spi_callback_args_t *p_args) { struct device *dev = (struct device *)p_args->p_context; @@ -144,23 +126,17 @@ static void spi_callbacks(spi_callback_args_t *p_args) case SPI_EVENT_TRANSFER_COMPLETE: #ifndef CONFIG_SPI_RTIO - spi_context_update_tx(&data->ctx, data->dfs, 1); - spi_context_update_rx(&data->ctx, data->dfs, 1); + spi_context_update_tx(&data->ctx, data->dfs, data->data_len); + spi_context_update_rx(&data->ctx, data->dfs, data->data_len); if (spi_rz_rspi_transfer_ongoing(data)) { - spi_rz_rspi_retransmit(data); - } else { - spi_context_complete(&data->ctx, dev, 0); + spi_rz_rspi_retransmit(dev); return; } #else - if (data->rtio_buf_remain-- > 0) { - spi_rz_rspi_retransmit(data); - } else { - struct spi_rtio *rtio_ctx = data->rtio_ctx; + struct spi_rtio *rtio_ctx = data->rtio_ctx; - if (rtio_ctx->txn_head != NULL) { - spi_rz_rspi_iodev_complete(dev, 0); - } + if (rtio_ctx->txn_head != NULL) { + spi_rz_rspi_iodev_complete(dev, 0); } #endif /* CONFIG_SPI_RTIO */ spi_context_complete(&data->ctx, dev, 0); @@ -178,62 +154,63 @@ static void spi_callbacks(spi_callback_args_t *p_args) } } -static int spi_rz_rspi_configure(const struct device *dev, const struct spi_config *config) +static int spi_rz_rspi_configure(const struct device *dev, const struct spi_config *spi_cfg) { struct spi_rz_rspi_data *data = dev->data; + const struct spi_rz_rspi_config *config = dev->config; spi_bit_width_t spi_width; fsp_err_t err; - if (spi_context_configured(&data->ctx, config)) { + if (spi_context_configured(&data->ctx, spi_cfg)) { /* This configuration is already in use */ return 0; } if (data->fsp_ctrl->open != 0) { - R_RSPI_Close(data->fsp_ctrl); + config->fsp_api->close(data->fsp_ctrl); } - if (config->operation & SPI_FRAME_FORMAT_TI) { + if (spi_cfg->operation & SPI_FRAME_FORMAT_TI) { LOG_ERR("TI frame not supported"); return -ENOTSUP; } if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) && - (config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) { + (spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) { LOG_DEV_ERR(dev, "Only single line mode is supported"); return -ENOTSUP; } /* SPI mode */ - if (config->operation & SPI_OP_MODE_SLAVE) { + if (spi_cfg->operation & SPI_OP_MODE_SLAVE) { data->fsp_config->operating_mode = SPI_MODE_SLAVE; } else { data->fsp_config->operating_mode = SPI_MODE_MASTER; } /* SPI POLARITY */ - if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) { + if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) { data->fsp_config->clk_polarity = SPI_CLK_POLARITY_HIGH; } else { data->fsp_config->clk_polarity = SPI_CLK_POLARITY_LOW; } /* SPI PHASE */ - if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) { + if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) { data->fsp_config->clk_phase = SPI_CLK_PHASE_EDGE_EVEN; } else { data->fsp_config->clk_phase = SPI_CLK_PHASE_EDGE_ODD; } /* SPI bit order */ - if (config->operation & SPI_TRANSFER_LSB) { + if (spi_cfg->operation & SPI_TRANSFER_LSB) { data->fsp_config->bit_order = SPI_BIT_ORDER_LSB_FIRST; } else { data->fsp_config->bit_order = SPI_BIT_ORDER_MSB_FIRST; } /* SPI bit width */ - spi_width = (spi_bit_width_t)(SPI_WORD_SIZE_GET(config->operation) - 1); + spi_width = (spi_bit_width_t)(SPI_WORD_SIZE_GET(spi_cfg->operation) - 1); if (spi_width > SPI_BIT_WIDTH_16_BITS) { data->dfs = 4; data->fsp_ctrl->bit_width = SPI_BIT_WIDTH_32_BITS; @@ -246,15 +223,16 @@ static int spi_rz_rspi_configure(const struct device *dev, const struct spi_conf } /* SPI slave select polarity */ - if (config->operation & SPI_CS_ACTIVE_HIGH) { + if (spi_cfg->operation & SPI_CS_ACTIVE_HIGH) { data->fsp_extend_config.ssl_polarity = RSPI_SSLP_HIGH; } else { data->fsp_extend_config.ssl_polarity = RSPI_SSLP_LOW; } /* Calculate bitrate */ - if (config->frequency > 0) { - err = R_RSPI_CalculateBitrate(config->frequency, &data->fsp_extend_config.spck_div); + if (spi_cfg->frequency > 0) { + err = R_RSPI_CalculateBitrate(spi_cfg->frequency, + &data->fsp_extend_config.spck_div); if (err != FSP_SUCCESS) { LOG_DEV_ERR(dev, "rspi: bitrate calculate error: %d", err); return -ENOSYS; @@ -269,13 +247,13 @@ static int spi_rz_rspi_configure(const struct device *dev, const struct spi_conf /* Data is passed into spi_callbacks. */ data->fsp_config->p_context = dev; /* Open module RSPI. */ - err = R_RSPI_Open(data->fsp_ctrl, data->fsp_config); + err = config->fsp_api->open(data->fsp_ctrl, data->fsp_config); if (err != FSP_SUCCESS) { LOG_ERR("R_RSPI_Open error: %d", err); return -EINVAL; } - data->ctx.config = config; + data->ctx.config = spi_cfg; return 0; } @@ -295,9 +273,9 @@ static int spi_rz_rspi_transceive_data(struct spi_rz_rspi_data *data) if (data_count) { if (data->dfs > 2) { if (spi_context_tx_buf_on(&data->ctx)) { - p_spi_reg->SPDR = *(uint32_t *)(data->ctx.tx_buf); + p_spi_reg->SPDR_b.SPD = *(uint32_t *)(data->ctx.tx_buf); } else { - p_spi_reg->SPDR = 0; + p_spi_reg->SPDR_b.SPD = 0; } } else if (data->dfs > 1) { if (spi_context_tx_buf_on(&data->ctx)) { @@ -314,8 +292,6 @@ static int spi_rz_rspi_transceive_data(struct spi_rz_rspi_data *data) } } - /* Clear Transmit Buffer Empty Flags */ - p_spi_reg->SPBFCR = R_RSPI0_SPBFCR_TXRST_Msk; spi_context_update_tx(&data->ctx, data->dfs, 1); /* RX transfer */ @@ -326,14 +302,12 @@ static int spi_rz_rspi_transceive_data(struct spi_rz_rspi_data *data) /* Read data from Data Register */ if (data->dfs > 2) { - UNALIGNED_PUT(p_spi_reg->SPDR, (uint32_t *)data->ctx.rx_buf); + UNALIGNED_PUT(p_spi_reg->SPDR_b.SPD, (uint32_t *)data->ctx.rx_buf); } else if (data->dfs > 1) { UNALIGNED_PUT(p_spi_reg->SPDR_hword.L, (uint16_t *)data->ctx.rx_buf); } else { UNALIGNED_PUT(p_spi_reg->SPDR_byte.LL, (uint8_t *)data->ctx.rx_buf); } - /* Clear Receive Buffer Full Flag */ - p_spi_reg->SPBFCR = R_RSPI0_SPBFCR_RXRST_Msk; spi_context_update_rx(&data->ctx, data->dfs, 1); } return 0; @@ -341,7 +315,7 @@ static int spi_rz_rspi_transceive_data(struct spi_rz_rspi_data *data) #endif /* #if !defined(CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT) */ /* && !defined(CONFIG_SPI_RENESAS_RZ_RSPI_DMAC) */ -static int transceive(const struct device *dev, const struct spi_config *config, +static int transceive(const struct device *dev, const struct spi_config *spi_cfg, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs, bool asynchronous, spi_callback_t cb, void *userdata) { @@ -358,51 +332,73 @@ static int transceive(const struct device *dev, const struct spi_config *config, return -ENOTSUP; } #endif - spi_context_lock(spi_ctx, asynchronous, cb, userdata, config); + spi_context_lock(spi_ctx, asynchronous, cb, userdata, spi_cfg); -#ifndef CONFIG_SPI_RTIO /* Configure module RSPI. */ - ret = spi_rz_rspi_configure(dev, config); + ret = spi_rz_rspi_configure(dev, spi_cfg); if (ret) { spi_context_release(spi_ctx, ret); return -EIO; } +#ifndef CONFIG_SPI_RTIO /* Setup tx buffer and rx buffer info. */ spi_context_buffers_setup(spi_ctx, tx_bufs, rx_bufs, data->dfs); spi_context_cs_control(spi_ctx, true); #if (defined(CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT) || defined(CONFIG_SPI_RENESAS_RZ_RSPI_DMAC)) + const struct spi_rz_rspi_config *config = dev->config; + + if (!spi_context_total_tx_len(&data->ctx) && !spi_context_total_rx_len(&data->ctx)) { + goto end_transceive; + } + if (data->ctx.rx_len == 0) { + data->data_len = spi_context_is_slave(&data->ctx) + ? spi_context_total_tx_len(&data->ctx) + : data->ctx.tx_len; + } else if (data->ctx.tx_len == 0) { + data->data_len = spi_context_is_slave(&data->ctx) + ? spi_context_total_rx_len(&data->ctx) + : data->ctx.rx_len; + } else { + data->data_len = spi_context_is_slave(&data->ctx) + ? MAX(spi_context_total_tx_len(&data->ctx), + spi_context_total_rx_len(&data->ctx)) + : MIN(data->ctx.tx_len, data->ctx.rx_len); + } if (data->ctx.tx_buf == NULL) { /* If there is only the rx buffer */ - ret = R_RSPI_Read(data->fsp_ctrl, data->ctx.rx_buf, 1, data->fsp_ctrl->bit_width); + ret = config->fsp_api->read(data->fsp_ctrl, data->ctx.rx_buf, data->data_len, + data->fsp_ctrl->bit_width); } else if (data->ctx.rx_buf == NULL) { /* If there is only the tx buffer */ - ret = R_RSPI_Write(data->fsp_ctrl, data->ctx.tx_buf, 1, data->fsp_ctrl->bit_width); + ret = config->fsp_api->write(data->fsp_ctrl, data->ctx.tx_buf, data->data_len, + data->fsp_ctrl->bit_width); } else { - ret = R_RSPI_WriteRead(data->fsp_ctrl, data->ctx.tx_buf, data->ctx.rx_buf, 1, - data->fsp_ctrl->bit_width); + ret = config->fsp_api->writeRead(data->fsp_ctrl, data->ctx.tx_buf, data->ctx.rx_buf, + data->data_len, data->fsp_ctrl->bit_width); } if (ret) { LOG_ERR("Async transmit fail: %d", ret); return -EIO; } ret = spi_context_wait_for_completion(spi_ctx); +end_transceive: #else - spi_bit_width_t spi_width = - (spi_bit_width_t)(SPI_WORD_SIZE_GET(data->ctx.config->operation) - 1); - /* Enable the SPI transfer */ - data->fsp_ctrl->p_regs->SPCR_b.SPE = 1; - data->fsp_ctrl->p_regs->SPBFCR = (3 << R_RSPI0_SPBFCR_TXTRG_Pos); - data->fsp_ctrl->p_regs->SPBFCR |= R_RSPI0_SPBFCR_TXRST_Msk | R_RSPI0_SPBFCR_RXRST_Msk; - if (spi_width > SPI_BIT_WIDTH_16_BITS) { - data->fsp_ctrl->p_regs->SPDCR |= (3 << R_RSPI0_SPDCR_SPLW_Pos); - data->fsp_ctrl->p_regs->SPCMD0 |= (3 << R_RSPI0_SPCMD0_SPB_Pos); - } else if (spi_width > SPI_BIT_WIDTH_8_BITS) { - data->fsp_ctrl->p_regs->SPDCR |= (2 << R_RSPI0_SPDCR_SPLW_Pos); - data->fsp_ctrl->p_regs->SPCMD0 |= (15 << R_RSPI0_SPCMD0_SPB_Pos); + data->fsp_ctrl->p_regs->SPBFCR_b.TXTRG = 0x3; /* Trigger when TX FIFO is empty */ + data->fsp_ctrl->p_regs->SPBFCR_b.RXRST = 0x1; /* Reset the receive buffer to empty state */ + data->fsp_ctrl->p_regs->SPCMD0 &= ~R_RSPI0_SPCMD0_SPB_Msk; /* Reset data length setting */ + if (data->fsp_ctrl->bit_width > SPI_BIT_WIDTH_16_BITS) { + data->fsp_ctrl->p_regs->SPDCR_b.SPLW = 0x3; /* Set access width 32 bit */ + data->fsp_ctrl->p_regs->SPCMD0_b.SPB = 0x3; /* Set data length 32 bit */ + } else if (data->fsp_ctrl->bit_width > SPI_BIT_WIDTH_8_BITS) { + data->fsp_ctrl->p_regs->SPDCR_b.SPLW = 0x2; /* Set access width 16 bit */ + data->fsp_ctrl->p_regs->SPCMD0_b.SPB = 0xF; /* Set data length 16 bit */ } else { - data->fsp_ctrl->p_regs->SPDCR |= (1 << R_RSPI0_SPDCR_SPLW_Pos); - data->fsp_ctrl->p_regs->SPCMD0 |= (7 << R_RSPI0_SPCMD0_SPB_Pos); + data->fsp_ctrl->p_regs->SPDCR_b.SPLW = 0x1; /* Set access width 8 bit */ + data->fsp_ctrl->p_regs->SPCMD0_b.SPB = 0x7; /* Set data length 8 bit */ } + data->fsp_ctrl->p_regs->SPBFCR &= ~(R_RSPI0_SPBFCR_RXRST_Msk | R_RSPI0_SPBFCR_TXRST_Msk); + /* Enable the SPI Transfer */ + data->fsp_ctrl->p_regs->SPCR_b.SPE = 0x1; do { spi_rz_rspi_transceive_data(data); @@ -412,8 +408,8 @@ static int transceive(const struct device *dev, const struct spi_config *config, while (!data->fsp_ctrl->p_regs->SPSR_b.TEND) { } - /* Disable the SPI Transfer. */ - data->fsp_ctrl->p_regs->SPCR_b.SPE = 0; + /* Disable the SPI Transfer */ + data->fsp_ctrl->p_regs->SPCR_b.SPE = 0x0; #endif /* #if (defined(CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT) */ /* || defined(CONFIG_SPI_RENESAS_RZ_RSPI_DMAC)) */ @@ -428,7 +424,7 @@ static int transceive(const struct device *dev, const struct spi_config *config, #else struct spi_rtio *rtio_ctx = data->rtio_ctx; - ret = spi_rtio_transceive(rtio_ctx, config, tx_bufs, rx_bufs); + ret = spi_rtio_transceive(rtio_ctx, spi_cfg, tx_bufs, rx_bufs); #endif /* CONFIG_SPI_RTIO */ spi_context_release(spi_ctx, ret); @@ -436,14 +432,14 @@ static int transceive(const struct device *dev, const struct spi_config *config, return ret; } -static int spi_rz_rspi_transceive_sync(const struct device *dev, const struct spi_config *config, +static int spi_rz_rspi_transceive_sync(const struct device *dev, const struct spi_config *spi_cfg, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs) { - return transceive(dev, config, tx_bufs, rx_bufs, false, NULL, NULL); + return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL); } -static int spi_rz_rspi_release(const struct device *dev, const struct spi_config *config) +static int spi_rz_rspi_release(const struct device *dev, const struct spi_config *spi_cfg) { struct spi_rz_rspi_data *data = dev->data; @@ -453,12 +449,12 @@ static int spi_rz_rspi_release(const struct device *dev, const struct spi_config } #ifdef CONFIG_SPI_ASYNC -static int spi_rz_rspi_transceive_async(const struct device *dev, const struct spi_config *config, +static int spi_rz_rspi_transceive_async(const struct device *dev, const struct spi_config *spi_cfg, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs, spi_callback_t cb, void *userdata) { - return transceive(dev, config, tx_bufs, rx_bufs, true, cb, userdata); + return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata); } #endif /* CONFIG_SPI_ASYNC */ @@ -469,10 +465,10 @@ static inline void spi_rz_rspi_iodev_prepare_start(const struct device *dev) struct spi_rz_rspi_data *data = dev->data; struct spi_rtio *rtio_ctx = data->rtio_ctx; struct spi_dt_spec *spi_dt_spec = rtio_ctx->txn_curr->sqe.iodev->data; - struct spi_config *config = &spi_dt_spec->config; + struct spi_config *spi_config = &spi_dt_spec->config; int err; - err = spi_rz_rspi_configure(dev, config); + err = spi_rz_rspi_configure(dev, spi_config); if (err != 0) { LOG_ERR("RTIO config spi error: %d", err); } @@ -482,28 +478,31 @@ static inline void spi_rz_rspi_iodev_prepare_start(const struct device *dev) static void spi_rz_rspi_iodev_start(const struct device *dev) { struct spi_rz_rspi_data *data = dev->data; + const struct spi_rz_rspi_config *config = dev->config; struct spi_rtio *rtio_ctx = data->rtio_ctx; struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe; int ret = 0; switch (sqe->op) { case RTIO_OP_RX: - data->rtio_buf_remain = sqe->rx.buf_len; - ret = R_RSPI_Read(data->fsp_ctrl, sqe->rx.buf, 1, data->fsp_ctrl->bit_width); + data->data_len = sqe->rx.buf_len / data->dfs; + ret = config->fsp_api->read(data->fsp_ctrl, sqe->rx.buf, data->data_len, + data->fsp_ctrl->bit_width); break; case RTIO_OP_TX: - data->rtio_buf_remain = sqe->tx.buf_len; - ret = R_RSPI_Write(data->fsp_ctrl, sqe->tx.buf, 1, data->fsp_ctrl->bit_width); + data->data_len = sqe->tx.buf_len / data->dfs; + ret = config->fsp_api->write(data->fsp_ctrl, sqe->tx.buf, data->data_len, + data->fsp_ctrl->bit_width); break; case RTIO_OP_TINY_TX: - data->rtio_buf_remain = sqe->tiny_tx.buf_len; - data->rtio_tiny_buf_idx = 0; - ret = R_RSPI_Write(data->fsp_ctrl, sqe->tiny_tx.buf, 1, data->fsp_ctrl->bit_width); + data->data_len = sqe->tiny_tx.buf_len / data->dfs; + ret = config->fsp_api->write(data->fsp_ctrl, sqe->tiny_tx.buf, data->data_len, + data->fsp_ctrl->bit_width); break; case RTIO_OP_TXRX: - data->rtio_buf_remain = sqe->txrx.buf_len; - ret = R_RSPI_WriteRead(data->fsp_ctrl, sqe->txrx.tx_buf, sqe->txrx.rx_buf, 1, - data->fsp_ctrl->bit_width); + data->data_len = sqe->txrx.buf_len / data->dfs; + ret = config->fsp_api->writeRead(data->fsp_ctrl, sqe->txrx.tx_buf, sqe->txrx.rx_buf, + data->data_len, data->fsp_ctrl->bit_width); break; default: spi_rz_rspi_iodev_complete(dev, -EINVAL); diff --git a/drivers/spi/spi_rpi_pico_pio.c b/drivers/spi/spi_rpi_pico_pio.c index 6421ec6d16ec6..62f6cfcb4bb2f 100644 --- a/drivers/spi/spi_rpi_pico_pio.c +++ b/drivers/spi/spi_rpi_pico_pio.c @@ -66,7 +66,6 @@ struct spi_pico_pio_data { struct spi_context spi_ctx; uint32_t tx_count; uint32_t rx_count; - PIO pio; size_t pio_sm; uint32_t pio_tx_offset; uint32_t pio_rx_offset; @@ -241,10 +240,11 @@ static inline uint32_t spi_pico_pio_sm_get32(PIO pio, uint sm) return *rxfifo; } -static inline int spi_pico_pio_sm_complete(struct spi_pico_pio_data *data) +static inline int spi_pico_pio_sm_complete(PIO pio, + struct spi_pico_pio_data *data) { - return ((data->pio->sm[data->pio_sm].addr == data->pio_tx_offset) && - pio_sm_is_tx_fifo_empty(data->pio, data->pio_sm)); + return ((pio->sm[data->pio_sm].addr == data->pio_tx_offset) && + pio_sm_is_tx_fifo_empty(pio, data->pio_sm)); } static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, @@ -257,6 +257,7 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, uint32_t cpha = 0; uint32_t rc = 0; uint32_t clock_freq; + PIO pio = pio_rpi_pico_get_pio(dev_cfg->piodev); rc = clock_control_on(dev_cfg->clk_dev, dev_cfg->clk_id); if (rc < 0) { @@ -320,10 +321,12 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, #if SPI_RPI_PICO_PIO_HALF_DUPLEX_ENABLED if (spi_cfg->operation & SPI_HALF_DUPLEX) { +#if defined(CONFIG_SPI_RPI_PICO_PIO_DMA) if (dev_cfg->dma_config.dev) { LOG_ERR("DMA not supported in 3-wire operation"); return -ENOTSUP; } +#endif if ((cpol != 0) || (cpha != 0)) { LOG_ERR("Only mode (0, 0) supported in 3-wire SIO"); @@ -349,7 +352,6 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, #endif /* SPI_RPI_PICO_PIO_HALF_DUPLEX_ENABLED */ clk = &dev_cfg->clk_gpio; - data->pio = pio_rpi_pico_get_pio(dev_cfg->piodev); rc = pio_rpi_pico_allocate_sm(dev_cfg->piodev, &data->pio_sm); if (rc < 0) { return rc; @@ -362,11 +364,11 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, float clock_div = spi_pico_pio_clock_divisor(clock_freq, SPI_SIO_MODE_0_0_TX_CYCLES, spi_cfg->frequency); - data->pio_tx_offset = - pio_add_program(data->pio, RPI_PICO_PIO_GET_PROGRAM(spi_sio_mode_0_0_tx)); + data->pio_tx_offset = pio_add_program( + pio, RPI_PICO_PIO_GET_PROGRAM(spi_sio_mode_0_0_tx)); - data->pio_rx_offset = - pio_add_program(data->pio, RPI_PICO_PIO_GET_PROGRAM(spi_sio_mode_0_0_rx)); + data->pio_rx_offset = pio_add_program( + pio, RPI_PICO_PIO_GET_PROGRAM(spi_sio_mode_0_0_rx)); data->pio_rx_wrap_target = data->pio_rx_offset + RPI_PICO_PIO_GET_WRAP_TARGET(spi_sio_mode_0_0_rx); data->pio_rx_wrap = @@ -379,7 +381,7 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, sm_config_set_in_shift(&sm_config, lsb, true, data->bits); sm_config_set_out_pins(&sm_config, sio->pin, 1); sm_config_set_out_shift(&sm_config, lsb, false, data->bits); - hw_set_bits(&data->pio->input_sync_bypass, 1u << sio->pin); + hw_set_bits(&pio->input_sync_bypass, 1u << sio->pin); sm_config_set_sideset_pins(&sm_config, clk->pin); sm_config_set_sideset(&sm_config, 1, false, false); @@ -388,16 +390,16 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, data->pio_tx_offset + RPI_PICO_PIO_GET_WRAP_TARGET(spi_sio_mode_0_0_tx), data->pio_tx_offset + RPI_PICO_PIO_GET_WRAP(spi_sio_mode_0_0_tx)); - pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, + pio_sm_set_pindirs_with_mask(pio, data->pio_sm, (BIT(clk->pin) | BIT(sio->pin)), (BIT(clk->pin) | BIT(sio->pin))); - pio_sm_set_pins_with_mask(data->pio, data->pio_sm, 0, + pio_sm_set_pins_with_mask(pio, data->pio_sm, 0, BIT(clk->pin) | BIT(sio->pin)); - pio_gpio_init(data->pio, sio->pin); - pio_gpio_init(data->pio, clk->pin); + pio_gpio_init(pio, sio->pin); + pio_gpio_init(pio, clk->pin); - pio_sm_init(data->pio, data->pio_sm, data->pio_tx_offset, &sm_config); - pio_sm_set_enabled(data->pio, data->pio_sm, true); + pio_sm_init(pio, data->pio_sm, data->pio_tx_offset, &sm_config); + pio_sm_set_enabled(pio, data->pio_sm, true); #else LOG_ERR("SIO pin requires half-duplex support"); return -EINVAL; @@ -442,11 +444,11 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, float clock_div = spi_pico_pio_clock_divisor(clock_freq, cycles, spi_cfg->frequency); - if (!pio_can_add_program(data->pio, program)) { + if (!pio_can_add_program(pio, program)) { return -EBUSY; } - data->pio_tx_offset = pio_add_program(data->pio, program); + data->pio_tx_offset = pio_add_program(pio, program); sm_config = pio_get_default_sm_config(); sm_config_set_clkdiv(&sm_config, clock_div); @@ -459,18 +461,18 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg, sm_config_set_wrap(&sm_config, data->pio_tx_offset + wrap_target, data->pio_tx_offset + wrap); - pio_sm_set_consecutive_pindirs(data->pio, data->pio_sm, miso->pin, 1, false); - pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, + pio_sm_set_consecutive_pindirs(pio, data->pio_sm, miso->pin, 1, false); + pio_sm_set_pindirs_with_mask(pio, data->pio_sm, (BIT(clk->pin) | BIT(mosi->pin)), (BIT(clk->pin) | BIT(mosi->pin))); - pio_sm_set_pins_with_mask(data->pio, data->pio_sm, (cpol << clk->pin), + pio_sm_set_pins_with_mask(pio, data->pio_sm, (cpol << clk->pin), BIT(clk->pin) | BIT(mosi->pin)); - pio_gpio_init(data->pio, mosi->pin); - pio_gpio_init(data->pio, miso->pin); - pio_gpio_init(data->pio, clk->pin); + pio_gpio_init(pio, mosi->pin); + pio_gpio_init(pio, miso->pin); + pio_gpio_init(pio, clk->pin); - pio_sm_init(data->pio, data->pio_sm, data->pio_tx_offset, &sm_config); - pio_sm_set_enabled(data->pio, data->pio_sm, true); + pio_sm_init(pio, data->pio_sm, data->pio_tx_offset, &sm_config); + pio_sm_set_enabled(pio, data->pio_sm, true); } data->spi_ctx.config = spi_cfg; @@ -596,6 +598,7 @@ static int spi_pico_pio_dma_setup(const struct device *dev, bool dir) struct dma_block_config *block_cfg = &data->dma_block; uint32_t dma_channel = dir ? dev_cfg->dma_config.tx_channel : dev_cfg->dma_config.rx_channel; + PIO pio = pio_rpi_pico_get_pio(dev_cfg->piodev); int ret; memset(dma_cfg, 0, sizeof(struct dma_config)); @@ -606,7 +609,7 @@ static int spi_pico_pio_dma_setup(const struct device *dev, bool dir) dma_cfg->user_data = (void *)dev; dma_cfg->block_count = 1U; dma_cfg->head_block = block_cfg; - dma_cfg->dma_slot = RPI_PICO_DMA_DREQ_TO_SLOT(pio_get_dreq(data->pio, data->pio_sm, dir)); + dma_cfg->dma_slot = RPI_PICO_DMA_DREQ_TO_SLOT(pio_get_dreq(pio, data->pio_sm, dir)); dma_cfg->channel_direction = dir ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY; dma_cfg->source_data_size = data->dfs; dma_cfg->dest_data_size = data->dfs; @@ -616,7 +619,7 @@ static int spi_pico_pio_dma_setup(const struct device *dev, bool dir) if (dir) { /* TX, in pio convention */ - block_cfg->dest_address = (uint32_t)&data->pio->txf[data->pio_sm]; + block_cfg->dest_address = (uint32_t)&pio->txf[data->pio_sm]; block_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; if (spi_context_tx_buf_on(&data->spi_ctx)) { block_cfg->source_address = (uint32_t)data->spi_ctx.tx_buf; @@ -629,7 +632,7 @@ static int spi_pico_pio_dma_setup(const struct device *dev, bool dir) data->tx_callbacked = false; } else { /* RX, in pio convention */ - block_cfg->source_address = (uint32_t)&data->pio->rxf[data->pio_sm]; + block_cfg->source_address = (uint32_t)&pio->rxf[data->pio_sm]; block_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; if (spi_context_rx_buf_on(&data->spi_ctx)) { @@ -662,15 +665,17 @@ static int spi_pico_pio_dma_setup(const struct device *dev, bool dir) static void spi_pico_pio_txrx_4_wire(const struct device *dev) { struct spi_pico_pio_data *data = dev->data; + const struct spi_pico_pio_config *dev_cfg = dev->config; const size_t chunk_len = spi_context_max_continuous_chunk(&data->spi_ctx); const uint8_t *txbuf = data->spi_ctx.tx_buf; uint8_t *rxbuf = data->spi_ctx.rx_buf; uint32_t txrx; size_t fifo_cnt = 0; + PIO pio = pio_rpi_pico_get_pio(dev_cfg->piodev); - while ((data->rx_count < chunk_len) || (data->tx_count < chunk_len)) { + while (data->rx_count < chunk_len || data->tx_count < chunk_len) { /* Fill up fifo with available TX data */ - while ((!pio_sm_is_tx_fifo_full(data->pio, data->pio_sm)) && + while ((!pio_sm_is_tx_fifo_full(pio, data->pio_sm)) && data->tx_count < chunk_len && fifo_cnt < PIO_FIFO_DEPTH) { /* Send 0 in the case of read only operation */ txrx = 0; @@ -680,21 +685,21 @@ static void spi_pico_pio_txrx_4_wire(const struct device *dev) if (txbuf) { txrx = sys_get_be32(txbuf + (data->tx_count * 4)); } - spi_pico_pio_sm_put32(data->pio, data->pio_sm, txrx); + spi_pico_pio_sm_put32(pio, data->pio_sm, txrx); } break; case 2: { if (txbuf) { txrx = sys_get_be16(txbuf + (data->tx_count * 2)); } - spi_pico_pio_sm_put16(data->pio, data->pio_sm, txrx); + spi_pico_pio_sm_put16(pio, data->pio_sm, txrx); } break; case 1: { if (txbuf) { txrx = ((uint8_t *)txbuf)[data->tx_count]; } - spi_pico_pio_sm_put8(data->pio, data->pio_sm, txrx); + spi_pico_pio_sm_put8(pio, data->pio_sm, txrx); } break; default: @@ -705,11 +710,11 @@ static void spi_pico_pio_txrx_4_wire(const struct device *dev) fifo_cnt++; } - while ((!pio_sm_is_rx_fifo_empty(data->pio, data->pio_sm)) && + while ((!pio_sm_is_rx_fifo_empty(pio, data->pio_sm)) && data->rx_count < chunk_len && fifo_cnt > 0) { switch (data->dfs) { case 4: { - txrx = spi_pico_pio_sm_get32(data->pio, data->pio_sm); + txrx = spi_pico_pio_sm_get32(pio, data->pio_sm); /* Discard received data if rx buffer not assigned */ if (rxbuf) { @@ -718,7 +723,7 @@ static void spi_pico_pio_txrx_4_wire(const struct device *dev) } break; case 2: { - txrx = spi_pico_pio_sm_get16(data->pio, data->pio_sm); + txrx = spi_pico_pio_sm_get16(pio, data->pio_sm); /* Discard received data if rx buffer not assigned */ if (rxbuf) { @@ -727,7 +732,7 @@ static void spi_pico_pio_txrx_4_wire(const struct device *dev) } break; case 1: { - txrx = spi_pico_pio_sm_get8(data->pio, data->pio_sm); + txrx = spi_pico_pio_sm_get8(pio, data->pio_sm); /* Discard received data if rx buffer not assigned */ if (rxbuf) { @@ -756,39 +761,41 @@ static void spi_pico_pio_txrx_3_wire(const struct device *dev) int sio_pin = dev_cfg->sio_gpio.pin; uint32_t tx_size = data->spi_ctx.tx_len; /* Number of WORDS to send */ uint32_t rx_size = data->spi_ctx.rx_len; /* Number of WORDS to receive */ + PIO pio = pio_rpi_pico_get_pio(dev_cfg->piodev); if (txbuf) { - pio_sm_set_enabled(data->pio, data->pio_sm, false); - pio_sm_set_wrap(data->pio, data->pio_sm, + pio_sm_set_enabled(pio, data->pio_sm, false); + pio_sm_set_wrap(pio, data->pio_sm, data->pio_tx_offset + RPI_PICO_PIO_GET_WRAP_TARGET(spi_sio_mode_0_0_tx), data->pio_tx_offset + RPI_PICO_PIO_GET_WRAP(spi_sio_mode_0_0_tx)); - pio_sm_clear_fifos(data->pio, data->pio_sm); - pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, BIT(sio_pin), BIT(sio_pin)); - pio_sm_restart(data->pio, data->pio_sm); - pio_sm_clkdiv_restart(data->pio, data->pio_sm); - pio_sm_exec(data->pio, data->pio_sm, pio_encode_jmp(data->pio_tx_offset)); - pio_sm_set_enabled(data->pio, data->pio_sm, true); + pio_sm_clear_fifos(pio, data->pio_sm); + pio_sm_set_pindirs_with_mask(pio, data->pio_sm, BIT(sio_pin), + BIT(sio_pin)); + pio_sm_restart(pio, data->pio_sm); + pio_sm_clkdiv_restart(pio, data->pio_sm); + pio_sm_exec(pio, data->pio_sm, pio_encode_jmp(data->pio_tx_offset)); + pio_sm_set_enabled(pio, data->pio_sm, true); while (data->tx_count < tx_size) { /* Fill up fifo with available TX data */ - while ((!pio_sm_is_tx_fifo_full(data->pio, data->pio_sm)) && + while ((!pio_sm_is_tx_fifo_full(pio, data->pio_sm)) && data->tx_count < tx_size) { switch (data->dfs) { case 4: { txrx = sys_get_be32(txbuf + (data->tx_count * 4)); - spi_pico_pio_sm_put32(data->pio, data->pio_sm, txrx); + spi_pico_pio_sm_put32(pio, data->pio_sm, txrx); } break; case 2: { txrx = sys_get_be16(txbuf + (data->tx_count * 2)); - spi_pico_pio_sm_put16(data->pio, data->pio_sm, txrx); + spi_pico_pio_sm_put16(pio, data->pio_sm, txrx); } break; case 1: { txrx = ((uint8_t *)txbuf)[data->tx_count]; - spi_pico_pio_sm_put8(data->pio, data->pio_sm, txrx); + spi_pico_pio_sm_put8(pio, data->pio_sm, txrx); } break; default: @@ -800,40 +807,41 @@ static void spi_pico_pio_txrx_3_wire(const struct device *dev) } /* Wait for the state machine to complete the cycle */ /* before resetting the PIO for reading. */ - while ((!pio_sm_is_tx_fifo_empty(data->pio, data->pio_sm)) || - (!spi_pico_pio_sm_complete(data))) + while ((!pio_sm_is_tx_fifo_empty(pio, data->pio_sm)) || + (!spi_pico_pio_sm_complete(pio, data))) { ; + } } if (rxbuf) { - pio_sm_set_enabled(data->pio, data->pio_sm, false); - pio_sm_set_wrap(data->pio, data->pio_sm, data->pio_rx_wrap_target, + pio_sm_set_enabled(pio, data->pio_sm, false); + pio_sm_set_wrap(pio, data->pio_sm, data->pio_rx_wrap_target, data->pio_rx_wrap); - pio_sm_clear_fifos(data->pio, data->pio_sm); - pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, 0, BIT(sio_pin)); - pio_sm_restart(data->pio, data->pio_sm); - pio_sm_clkdiv_restart(data->pio, data->pio_sm); - pio_sm_put(data->pio, data->pio_sm, (rx_size * data->bits) - 1); - pio_sm_exec(data->pio, data->pio_sm, pio_encode_jmp(data->pio_rx_offset)); - pio_sm_set_enabled(data->pio, data->pio_sm, true); + pio_sm_clear_fifos(pio, data->pio_sm); + pio_sm_set_pindirs_with_mask(pio, data->pio_sm, 0, BIT(sio_pin)); + pio_sm_restart(pio, data->pio_sm); + pio_sm_clkdiv_restart(pio, data->pio_sm); + pio_sm_put(pio, data->pio_sm, (rx_size * data->bits) - 1); + pio_sm_exec(pio, data->pio_sm, pio_encode_jmp(data->pio_rx_offset)); + pio_sm_set_enabled(pio, data->pio_sm, true); while (data->rx_count < rx_size) { - while ((!pio_sm_is_rx_fifo_empty(data->pio, data->pio_sm)) && + while ((!pio_sm_is_rx_fifo_empty(pio, data->pio_sm)) && data->rx_count < rx_size) { switch (data->dfs) { case 4: { - txrx = spi_pico_pio_sm_get32(data->pio, data->pio_sm); + txrx = spi_pico_pio_sm_get32(pio, data->pio_sm); sys_put_be32(txrx, rxbuf + (data->rx_count * 4)); } break; case 2: { - txrx = spi_pico_pio_sm_get16(data->pio, data->pio_sm); + txrx = spi_pico_pio_sm_get16(pio, data->pio_sm); sys_put_be16(txrx, rxbuf + (data->rx_count * 2)); } break; case 1: { - txrx = spi_pico_pio_sm_get8(data->pio, data->pio_sm); + txrx = spi_pico_pio_sm_get8(pio, data->pio_sm); rxbuf[data->rx_count] = (uint8_t)txrx; } break; @@ -870,6 +878,7 @@ static int spi_pico_pio_transceive_impl(const struct device *dev, const struct s const struct spi_pico_pio_config *dev_cfg = dev->config; struct spi_pico_pio_data *data = dev->data; struct spi_context *spi_ctx = &data->spi_ctx; + PIO pio = pio_rpi_pico_get_pio(dev_cfg->piodev); int rc = 0; spi_context_lock(spi_ctx, asynchronous, cb, userdata, spi_cfg); @@ -886,7 +895,7 @@ static int spi_pico_pio_transceive_impl(const struct device *dev, const struct s data->tx_count = 0; data->rx_count = 0; - pio_sm_clear_fifos(data->pio, data->pio_sm); + pio_sm_clear_fifos(pio, data->pio_sm); #if defined(CONFIG_SPI_RPI_PICO_PIO_DMA) if (dev_cfg->dma_config.dev) { diff --git a/drivers/spi/spi_rtio.c b/drivers/spi/spi_rtio.c index 7a26727e66f8a..a671b817ec068 100644 --- a/drivers/spi/spi_rtio.c +++ b/drivers/spi/spi_rtio.c @@ -255,8 +255,8 @@ int spi_rtio_copy(struct rtio *r, NULL); tx++; if (tx < tx_count) { - tx_buf = rx_bufs->buffers[rx].buf; - tx_len = rx_bufs->buffers[rx].len; + tx_buf = tx_bufs->buffers[tx].buf; + tx_len = tx_bufs->buffers[tx].len; } else { tx_buf = NULL; tx_len = 0; diff --git a/drivers/spi/spi_silabs_eusart.c b/drivers/spi/spi_silabs_eusart.c index 71fedef029230..49963776247f6 100644 --- a/drivers/spi/spi_silabs_eusart.c +++ b/drivers/spi/spi_silabs_eusart.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -728,6 +729,9 @@ static DEVICE_API(spi, spi_silabs_eusart_api) = { .transceive = spi_silabs_eusart_transceive_sync, #ifdef CONFIG_SPI_ASYNC .transceive_async = spi_silabs_eusart_transceive_async, +#endif +#ifdef CONFIG_SPI_RTIO + .iodev_submit = spi_rtio_iodev_default_submit, #endif .release = spi_silabs_eusart_release, }; diff --git a/drivers/spi/spi_silabs_siwx91x_gspi.c b/drivers/spi/spi_silabs_siwx91x_gspi.c index 79d5f7b81bd6e..2fb7e06dd549f 100644 --- a/drivers/spi/spi_silabs_siwx91x_gspi.c +++ b/drivers/spi/spi_silabs_siwx91x_gspi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -624,6 +625,9 @@ static DEVICE_API(spi, gspi_siwx91x_driver_api) = { .transceive = gspi_siwx91x_transceive_sync, #ifdef CONFIG_SPI_ASYNC .transceive_async = gspi_siwx91x_transceive_async, +#endif +#ifdef CONFIG_SPI_RTIO + .iodev_submit = spi_rtio_iodev_default_submit, #endif .release = gspi_siwx91x_release, }; diff --git a/drivers/timer/Kconfig.esp32 b/drivers/timer/Kconfig.esp32 index ff10f017866d7..1a61d02d46966 100644 --- a/drivers/timer/Kconfig.esp32 +++ b/drivers/timer/Kconfig.esp32 @@ -1,11 +1,13 @@ # Copyright (c) 2014-2015 Wind River Systems, Inc. # Copyright (c) 2016 Cadence Design Systems, Inc. # Copyright (c) 2019 Intel Corp. +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 config ESP32_SYS_TIMER bool "ESP32 sys-timer support (ESP32Cx series)" - depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || (SOC_SERIES_ESP32C6 && !SOC_ESP32C6_LPCORE) + depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || \ + (SOC_SERIES_ESP32C6 && !SOC_ESP32C6_LPCORE) || SOC_SERIES_ESP32H2 default y select TICKLESS_CAPABLE select TIMER_HAS_64BIT_CYCLE_COUNTER diff --git a/drivers/timer/Kconfig.stm32_lptim b/drivers/timer/Kconfig.stm32_lptim index f8f89740bee36..bdd732467559d 100644 --- a/drivers/timer/Kconfig.stm32_lptim +++ b/drivers/timer/Kconfig.stm32_lptim @@ -53,7 +53,7 @@ config STM32_LPTIM_TICK_FREQ_RATIO_OVERRIDE For LPTIM configuration, a specific tick freq is advised depending on LPTIM input clock: - LSI(32KHz): 4000 ticks/sec - - LSE(32678): 4096 ticks/sec + - LSE(32768): 4096 ticks/sec To prevent misconfigurations, a dedicated check is implemented in the driver. This options allows to override this check diff --git a/drivers/timer/mcux_os_timer.c b/drivers/timer/mcux_os_timer.c index 40719f9b907a0..0fb6128789ed1 100644 --- a/drivers/timer/mcux_os_timer.c +++ b/drivers/timer/mcux_os_timer.c @@ -43,12 +43,12 @@ static const struct device *counter_dev = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(0, deep_sleep_counter)); /* Indicates if the counter is running. */ static bool counter_running; +static uint32_t counter_max_val; +#endif /* Indicates we received a call with ticks set to wait forever */ static bool wait_forever; /* Incase of counter overflow, track the remaining ticks left */ static uint32_t counter_remaining_ticks; -static uint32_t counter_max_val; -#endif static uint64_t mcux_lpc_ostick_get_compensated_timer_value(void) { @@ -191,11 +191,6 @@ static uint32_t mcux_lpc_ostick_compensate_system_timer(void) return 0; } -bool z_nxp_os_timer_ignore_timer_wakeup(void) -{ - return (wait_forever || counter_remaining_ticks); -} - static uint32_t mcux_os_timer_set_lp_counter_timeout(void) { uint64_t timeout; @@ -233,6 +228,11 @@ static uint32_t mcux_os_timer_set_lp_counter_timeout(void) #define mcux_os_timer_set_lp_counter_timeout(...) do { } while (0) #endif +bool z_nxp_os_timer_ignore_timer_wakeup(void) +{ + return (wait_forever || counter_remaining_ticks); +} + void sys_clock_set_timeout(int32_t ticks, bool idle) { if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) { diff --git a/drivers/timer/renesas_rx_cmt.c b/drivers/timer/renesas_rx_cmt.c index ff44000edeb2d..b013e05a610e9 100644 --- a/drivers/timer/renesas_rx_cmt.c +++ b/drivers/timer/renesas_rx_cmt.c @@ -19,13 +19,12 @@ #define CMT0_NODE DT_NODELABEL(cmt0) #define CMT1_NODE DT_NODELABEL(cmt1) +#define CMT1_IRQN DT_IRQN(CMT1_NODE) + #define ICU_NODE DT_NODELABEL(icu) -#define ICU_IR_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, IR) -#define ICU_IER_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, IER) -#define ICU_IPR_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, IPR) -#define ICU_FIR_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, FIR) -#define ICU_IR ((volatile uint8_t *)ICU_IR_ADDR) +#define ICU_IR_ADDR DT_REG_ADDR_BY_NAME(ICU_NODE, IR) +#define ICU_IR ((volatile uint8_t *)ICU_IR_ADDR) #define CMT0_IRQ_NUM DT_IRQ_BY_NAME(CMT0_NODE, cmi, irq) #define CMT1_IRQ_NUM DT_IRQ_BY_NAME(CMT1_NODE, cmi, irq) @@ -35,10 +34,9 @@ #define CYCLES_PER_SEC (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) #define TICKS_PER_SEC (CONFIG_SYS_CLOCK_TICKS_PER_SEC) #define CYCLES_PER_TICK (CYCLES_PER_SEC / TICKS_PER_SEC) +#define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYCLES_PER_TICK) - 1) #define CYCLES_CYCLE_TIMER (COUNTER_MAX + 1) -#define MSTPCR_ADDR ((volatile uint32_t *)0x00080010) /* MSTPCR register address */ -#define MSTP_CMT0_BIT (1 << 15) /* Bit 15 controls MSTPA15 (CMT0) */ static const struct clock_control_rx_subsys_cfg cmt_clk_cfg = { .mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(0), 0, mstp), @@ -86,13 +84,13 @@ const int32_t z_sys_timer_irq_for_test = CMT0_IRQ_NUM; static cycle_t cmt1_elapsed(void) { uint32_t val1 = (uint32_t)(*cycle_timer_cfg.cmcnt); - uint8_t cmt_ir = ICU_IR[29]; + uint8_t cmt_ir = ICU_IR[CMT1_IRQN]; uint32_t val2 = (uint32_t)(*cycle_timer_cfg.cmcnt); if ((1 == cmt_ir) || (val1 > val2)) { cycle_count += CYCLES_CYCLE_TIMER; - ICU_IR[29] = 0; + ICU_IR[CMT1_IRQN] = 0; } return (val2 + cycle_count); @@ -211,17 +209,40 @@ static int sys_clock_driver_init(void) void sys_clock_set_timeout(int32_t ticks, bool idle) { - if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && idle && ticks == K_TICKS_FOREVER) { - *tick_timer_cfg.cmstr = 0x0000; /* stop cmt0,1 */ + if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) { + return; + } + + if (ticks == K_TICKS_FOREVER || ticks == INT32_MAX) { return; } -#if defined(CONFIG_TICKLESS_KERNEL) - /* - * By default, it is implemented as a no operation. - * Implement the processing as needed. - */ -#endif /* CONFIG_TICKLESS_KERNEL */ + ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS); + + k_spinlock_key_t key = k_spin_lock(&lock); + + cycle_t now = cmt1_elapsed(); + cycle_t elapsed; + + if (now < announced_cycle_count) { + /* cycle_count overflowed */ + elapsed = (cycle_t)(now + (CYCLE_COUNT_MAX - announced_cycle_count + 1)); + } else { + elapsed = (now - announced_cycle_count); + } + + cycle_t delay = (cycle_t)ticks * CYCLES_PER_TICK; + + delay += elapsed; + delay = DIV_ROUND_UP(delay, CYCLES_PER_TICK) * CYCLES_PER_TICK; + delay -= elapsed; + + uint16_t current = *tick_timer_cfg.cmcnt; + uint16_t new_cmcor = (uint16_t)(current + delay - 1U); + + *tick_timer_cfg.cmcor = new_cmcor; + + k_spin_unlock(&lock, key); } SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY); diff --git a/drivers/usb/udc/udc_common.c b/drivers/usb/udc/udc_common.c index 3612cd23b5f61..e46ff96776504 100644 --- a/drivers/usb/udc/udc_common.c +++ b/drivers/usb/udc/udc_common.c @@ -355,7 +355,6 @@ int udc_ep_enable_internal(const struct device *dev, cfg->mps = mps; cfg->interval = interval; - cfg->stat.odd = 0; cfg->stat.halted = 0; cfg->stat.data1 = false; ret = api->ep_enable(dev, cfg); @@ -631,13 +630,13 @@ struct net_buf *udc_ep_buf_alloc(const struct device *dev, buf = net_buf_alloc_len(&udc_ep_pool, size, K_NO_WAIT); if (!buf) { - LOG_ERR("Failed to allocate net_buf %zd", size); + LOG_ERR("Failed to allocate net_buf %zd, ep 0x%02x", size, ep); goto ep_alloc_error; } bi = udc_get_buf_info(buf); bi->ep = ep; - LOG_DBG("Allocate net_buf, ep 0x%02x, size %zd", ep, size); + LOG_DBG("Allocate net_buf %p, ep 0x%02x, size %zd", buf, ep, size); ep_alloc_error: api->unlock(dev); diff --git a/drivers/usb/udc/udc_kinetis.c b/drivers/usb/udc/udc_kinetis.c index 7d22730160396..cb44857871aba 100644 --- a/drivers/usb/udc/udc_kinetis.c +++ b/drivers/usb/udc/udc_kinetis.c @@ -326,10 +326,11 @@ static inline int work_handler_setup(const struct device *dev) udc_ctrl_update_stage(dev, buf); if (udc_ctrl_stage_is_data_out(dev)) { + size_t length = ROUND_UP(udc_data_stage_length(buf), USBFSOTG_EP0_SIZE); + /* Allocate and feed buffer for data OUT stage */ LOG_DBG("s:%p|feed for -out-", buf); - err = usbfsotg_ctrl_feed_dout(dev, udc_data_stage_length(buf), - false, true); + err = usbfsotg_ctrl_feed_dout(dev, length, false, true); if (err == -ENOMEM) { err = udc_submit_ep_event(dev, buf, err); } @@ -539,7 +540,7 @@ static ALWAYS_INLINE void isr_handle_xfer_done(const struct device *dev, struct usbfsotg_data *priv = udc_get_private(dev); uint8_t ep = stat_reg_get_ep(status); bool odd = stat_reg_is_odd(status); - struct usbfsotg_bd *bd, *bd_op; + struct usbfsotg_bd *bd; struct udc_ep_config *ep_cfg; struct net_buf *buf; uint8_t token_pid; @@ -548,7 +549,6 @@ static ALWAYS_INLINE void isr_handle_xfer_done(const struct device *dev, ep_cfg = udc_get_ep_cfg(dev, ep); bd = usbfsotg_get_ebd(dev, ep_cfg, false); - bd_op = usbfsotg_get_ebd(dev, ep_cfg, true); token_pid = bd->get.tok_pid; len = bd->get.bc; data1 = bd->get.data1 ? true : false; @@ -885,8 +885,12 @@ static int usbfsotg_ep_enable(const struct device *dev, priv->busy[0] = false; priv->busy[1] = false; buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, USBFSOTG_EP0_SIZE); - usbfsotg_bd_set_ctrl(bd_even, buf->size, buf->data, false); + if (buf == NULL) { + return -ENOMEM; + } + priv->out_buf[0] = buf; + usbfsotg_bd_set_ctrl(bd_even, USBFSOTG_EP0_SIZE, buf->data, false); } return 0; @@ -954,8 +958,7 @@ static int usbfsotg_disable(const struct device *dev) const struct usbfsotg_config *config = dev->config; USB_Type *base = config->base; - /* disable USB and DP Pullup */ - base->CTL &= ~USB_CTL_USBENSOFEN_MASK; + /* Disable DP Pullup */ base->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK; return 0; @@ -1189,8 +1192,8 @@ static const struct udc_api usbfsotg_api = { .irq_enable_func = udc_irq_enable_func##n, \ .irq_disable_func = udc_irq_disable_func##n, \ .num_of_eps = DT_INST_PROP(n, num_bidir_endpoints), \ - .ep_cfg_in = ep_cfg_out, \ - .ep_cfg_out = ep_cfg_in, \ + .ep_cfg_in = ep_cfg_in, \ + .ep_cfg_out = ep_cfg_out, \ }; \ \ static struct usbfsotg_data priv_data_##n = { \ diff --git a/drivers/usb/udc/udc_numaker.c b/drivers/usb/udc/udc_numaker.c index 43630010caa28..e14640219cf4b 100644 --- a/drivers/usb/udc/udc_numaker.c +++ b/drivers/usb/udc/udc_numaker.c @@ -172,10 +172,11 @@ static inline void numaker_usbd_sw_connect(const struct device *dev) /* Enable relevant interrupts */ base->INTEN = USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | - IF_ENABLED(CONFIG_UDC_ENABLE_SOF, (USBD_INT_SOF |)) + IF_ENABLED(CONFIG_UDC_ENABLE_SOF, (USBD_INT_SOF |)) /* CPU load concern */ USBD_INT_WAKEUP; /* Clear SE0 for connect */ + base->ATTR |= USBD_ATTR_DPPUEN_Msk; base->SE0 &= ~USBD_DRVSE0; } @@ -345,8 +346,8 @@ static int numaker_usbd_hw_setup(const struct device *dev) /* Initialize USBD engine */ /* NOTE: BSP USBD driver: ATTR = 0x7D0 */ - base->ATTR = USBD_ATTR_BYTEM_Msk | BIT(9) | USBD_ATTR_DPPUEN_Msk | USBD_ATTR_USBEN_Msk | - BIT(6) | USBD_ATTR_PHYEN_Msk; + base->ATTR = USBD_ATTR_BYTEM_Msk | BIT(9) | USBD_ATTR_USBEN_Msk | BIT(6) | + USBD_ATTR_PHYEN_Msk; /* Set SE0 for S/W disconnect */ numaker_usbd_sw_disconnect(dev); @@ -395,12 +396,53 @@ static void numaker_usbd_hw_shutdown(const struct device *dev) SYS_LockReg(); } +/* Interrupt top half processing for vbus plug */ +static void numaker_usbd_vbus_plug_th(const struct device *dev) +{ + const struct udc_numaker_config *config = dev->config; + USBD_T *base = config->base; + + /* Enable back USB/PHY */ + base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk; + + /* UDC stack would handle bottom-half processing */ + udc_submit_event(dev, UDC_EVT_VBUS_READY, 0); + + LOG_DBG("USB plug-in"); +} + +/* Interrupt top half processing for vbus unplug */ +static void numaker_usbd_vbus_unplug_th(const struct device *dev) +{ + const struct udc_numaker_config *config = dev->config; + USBD_T *base = config->base; + + /* Disable USB */ + base->ATTR &= ~USBD_USB_EN; + + /* UDC stack would handle bottom-half processing */ + udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0); + + LOG_DBG("USB unplug"); +} + +/* Interrupt top half processing for bus wakeup */ +static void numaker_usbd_bus_wakeup_th(const struct device *dev) +{ + LOG_DBG("USB wake-up"); +} + /* Interrupt top half processing for bus reset */ static void numaker_usbd_bus_reset_th(const struct device *dev) { + const struct udc_numaker_config *config = dev->config; + USBD_T *base = config->base; struct udc_numaker_data *priv = udc_get_private(dev); USBD_EP_T *ep_base; + /* Enable back USB/PHY */ + base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk; + for (uint32_t i = 0ul; i < priv->ep_pool_size; i++) { ep_base = numaker_usbd_ep_base(dev, EP0 + i); @@ -420,6 +462,128 @@ static void numaker_usbd_bus_reset_th(const struct device *dev) } numaker_usbd_reset_addr(dev); + + /* UDC stack would handle bottom-half processing, + * including reset device address (udc_set_address), + * un-configure device (udc_ep_disable), etc. + */ + udc_submit_event(dev, UDC_EVT_RESET, 0); + + LOG_DBG("USB reset"); +} + +/* Interrupt top half processing for bus suspend */ +static void numaker_usbd_bus_suspend_th(const struct device *dev) +{ + const struct udc_numaker_config *config = dev->config; + USBD_T *base = config->base; + + /* Enable USB but disable PHY */ + base->ATTR &= ~USBD_PHY_EN; + + /* UDC stack would handle bottom-half processing */ + udc_submit_event(dev, UDC_EVT_SUSPEND, 0); + + LOG_DBG("USB suspend"); +} + +/* Interrupt top half processing for bus resume */ +static void numaker_usbd_bus_resume_th(const struct device *dev) +{ + const struct udc_numaker_config *config = dev->config; + USBD_T *base = config->base; + + /* Enable back USB/PHY */ + base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk; + + /* UDC stack would handle bottom-half processing */ + udc_submit_event(dev, UDC_EVT_RESUME, 0); + + LOG_DBG("USB resume"); +} + +/* Interrupt top half processing for SOF */ +static void numaker_usbd_sof_th(const struct device *dev) +{ + /* UDC stack would handle bottom-half processing */ + udc_submit_sof_event(dev); +} + +static void numaker_usbd_setup_copy_to_user(const struct device *dev, uint8_t *usrbuf); + +/* Interrupt top half processing for Setup packet */ +static void numaker_usbd_setup_th(const struct device *dev) +{ + USBD_EP_T *ep0_base = numaker_usbd_ep_base(dev, EP0); + USBD_EP_T *ep1_base = numaker_usbd_ep_base(dev, EP1); + struct numaker_usbd_msg msg = {0}; + + /* Clear the data IN/OUT ready flag of control endpoints */ + ep0_base->CFGP |= USBD_CFGP_CLRRDY_Msk; + ep1_base->CFGP |= USBD_CFGP_CLRRDY_Msk; + + /* By USB spec, following transactions, regardless of Data/Status stage, + * will always be DATA1 + */ + ep0_base->CFG |= USBD_CFG_DSQSYNC_Msk; + ep1_base->CFG |= USBD_CFG_DSQSYNC_Msk; + + /* Message for bottom-half processing */ + /* NOTE: In Zephyr USB device stack, Setup packet is passed via + * CTRL OUT EP + */ + msg.type = NUMAKER_USBD_MSG_TYPE_SETUP; + numaker_usbd_setup_copy_to_user(dev, msg.setup.packet); + numaker_usbd_send_msg(dev, &msg); +} + +/* Interrupt top half processing for EP (excluding Setup) */ +static void numaker_usbd_ep_th(const struct device *dev, uint32_t ep_hw_idx) +{ + struct udc_numaker_data *priv = udc_get_private(dev); + USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_hw_idx); + uint8_t ep_dir; + uint8_t ep_idx; + uint8_t ep; + struct numaker_usbd_msg msg = {0}; + + /* We don't enable INNAKEN interrupt, so as long as EP event occurs, + * we can just regard one data transaction has completed (ACK for + * CTRL/BULK/INT or no-ACK for Iso), that is, no need to check EPSTS0, + * EPSTS1, etc. + */ + + /* EP direction, number, and address */ + ep_dir = ((ep_base->CFG & USBD_CFG_STATE_Msk) == USBD_CFG_EPMODE_IN) ? USB_EP_DIR_IN + : USB_EP_DIR_OUT; + ep_idx = (ep_base->CFG & USBD_CFG_EPNUM_Msk) >> USBD_CFG_EPNUM_Pos; + ep = USB_EP_GET_ADDR(ep_idx, ep_dir); + + /* NOTE: See comment in udc_numaker_set_address()'s implementation + * for safe place to change USB device address + */ + if (ep == USB_EP_GET_ADDR(0, USB_EP_DIR_IN)) { + numaker_usbd_set_addr(dev); + } + + /* NOTE: See comment on mxpld_ctrlout for why make one copy of + * CTRL OUT's MXPLD + */ + if (ep == USB_EP_GET_ADDR(0, USB_EP_DIR_OUT)) { + struct numaker_usbd_ep *ep_ctrlout = priv->ep_pool + 0; + + ep_ctrlout->mxpld_ctrlout = ep_base->MXPLD; + } + + /* Message for bottom-half processing */ + if (USB_EP_DIR_IS_OUT(ep)) { + msg.type = NUMAKER_USBD_MSG_TYPE_OUT; + msg.out.ep = ep; + } else { + msg.type = NUMAKER_USBD_MSG_TYPE_IN; + msg.in.ep = ep; + } + numaker_usbd_send_msg(dev, &msg); } /* USBD SRAM base for DMA */ @@ -558,8 +722,8 @@ static void numaker_usbd_ep_config_major(struct numaker_usbd_ep *ep_cur, } /* Endpoint index */ - ep_cur->ep_hw_cfg |= - (USB_EP_GET_IDX(ep_cfg->addr) << USBD_CFG_EPNUM_Pos) & USBD_CFG_EPNUM_Msk; + ep_cur->ep_hw_cfg |= (USB_EP_GET_IDX(ep_cfg->addr) << USBD_CFG_EPNUM_Pos) & + USBD_CFG_EPNUM_Msk; ep_base->CFG = ep_cur->ep_hw_cfg; } @@ -1205,102 +1369,61 @@ static void numaker_usbd_msg_handler(const struct device *dev) } } -static void numaker_udbd_isr(const struct device *dev) +static void numaker_usbd_isr(const struct device *dev) { const struct udc_numaker_config *config = dev->config; - struct udc_numaker_data *priv = udc_get_private(dev); USBD_T *const base = config->base; + uint32_t usbd_intsts = base->INTSTS; + uint32_t usbd_bus_state = base->ATTR; - struct numaker_usbd_msg msg = {0}; + /* Focus on enabled + * + * NOTE: INTSTS has more interrupt bits than INTEN: SETUP and EPEVTx. + * For SETUP, it is added back for not missing. + * For EPEVTx, they are caught by EPINTSTS. + */ + usbd_intsts &= base->INTEN | USBD_INTSTS_SETUP; - uint32_t volatile usbd_intsts = base->INTSTS; - uint32_t volatile usbd_bus_state = base->ATTR; + /* Clear event flag */ + base->INTSTS = usbd_intsts; /* USB plug-in/unplug */ if (usbd_intsts & USBD_INTSTS_FLDET) { - /* Floating detect */ - base->INTSTS = USBD_INTSTS_FLDET; - if (base->VBUSDET & USBD_VBUSDET_VBUSDET_Msk) { /* USB plug-in */ - - /* Enable back USB/PHY */ - base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk; - - /* UDC stack would handle bottom-half processing */ - udc_submit_event(dev, UDC_EVT_VBUS_READY, 0); - - LOG_DBG("USB plug-in"); + numaker_usbd_vbus_plug_th(dev); } else { /* USB unplug */ - - /* Disable USB */ - base->ATTR &= ~USBD_USB_EN; - - /* UDC stack would handle bottom-half processing */ - udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0); - - LOG_DBG("USB unplug"); + numaker_usbd_vbus_unplug_th(dev); } } /* USB wake-up */ if (usbd_intsts & USBD_INTSTS_WAKEUP) { - /* Clear event flag */ - base->INTSTS = USBD_INTSTS_WAKEUP; - - LOG_DBG("USB wake-up"); + numaker_usbd_bus_wakeup_th(dev); } /* USB reset/suspend/resume */ if (usbd_intsts & USBD_INTSTS_BUS) { - /* Clear event flag */ - base->INTSTS = USBD_INTSTS_BUS; - + /* Bus reset */ if (usbd_bus_state & USBD_STATE_USBRST) { - /* Bus reset */ - - /* Enable back USB/PHY */ - base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk; - - /* Bus reset top half */ numaker_usbd_bus_reset_th(dev); - - /* UDC stack would handle bottom-half processing, - * including reset device address (udc_set_address), - * un-configure device (udc_ep_disable), etc. - */ - udc_submit_event(dev, UDC_EVT_RESET, 0); - - LOG_DBG("USB reset"); } - if (usbd_bus_state & USBD_STATE_SUSPEND) { - /* Enable USB but disable PHY */ - base->ATTR &= ~USBD_PHY_EN; - /* UDC stack would handle bottom-half processing */ - udc_submit_event(dev, UDC_EVT_SUSPEND, 0); - - LOG_DBG("USB suspend"); + /* Bus suspend */ + if (usbd_bus_state & USBD_STATE_SUSPEND) { + numaker_usbd_bus_suspend_th(dev); } - if (usbd_bus_state & USBD_STATE_RESUME) { - /* Enable back USB/PHY */ - base->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk; - - /* UDC stack would handle bottom-half processing */ - udc_submit_event(dev, UDC_EVT_RESUME, 0); - LOG_DBG("USB resume"); + /* Bus resume */ + if (usbd_bus_state & USBD_STATE_RESUME) { + numaker_usbd_bus_resume_th(dev); } } /* USB SOF */ if (usbd_intsts & USBD_INTSTS_SOFIF_Msk) { - /* Clear event flag */ - base->INTSTS = USBD_INTSTS_SOFIF_Msk; - - /* UDC stack would handle bottom-half processing */ - udc_submit_sof_event(dev); + numaker_usbd_sof_th(dev); } /* USB Setup/EP */ @@ -1309,83 +1432,19 @@ static void numaker_udbd_isr(const struct device *dev) /* Setup event */ if (usbd_intsts & USBD_INTSTS_SETUP) { - USBD_EP_T *ep0_base = numaker_usbd_ep_base(dev, EP0); - USBD_EP_T *ep1_base = numaker_usbd_ep_base(dev, EP1); - - /* Clear event flag */ - base->INTSTS = USBD_INTSTS_SETUP; - - /* Clear the data IN/OUT ready flag of control endpoints */ - ep0_base->CFGP |= USBD_CFGP_CLRRDY_Msk; - ep1_base->CFGP |= USBD_CFGP_CLRRDY_Msk; - - /* By USB spec, following transactions, regardless of Data/Status stage, - * will always be DATA1 - */ - ep0_base->CFG |= USBD_CFG_DSQSYNC_Msk; - ep1_base->CFG |= USBD_CFG_DSQSYNC_Msk; - - /* Message for bottom-half processing */ - /* NOTE: In Zephyr USB device stack, Setup packet is passed via - * CTRL OUT EP - */ - msg.type = NUMAKER_USBD_MSG_TYPE_SETUP; - numaker_usbd_setup_copy_to_user(dev, msg.setup.packet); - numaker_usbd_send_msg(dev, &msg); + numaker_usbd_setup_th(dev); } /* EP events */ epintsts = base->EPINTSTS; + /* Clear event flag */ base->EPINTSTS = epintsts; while (epintsts) { uint32_t ep_hw_idx = u32_count_trailing_zeros(epintsts); - USBD_EP_T *ep_base = numaker_usbd_ep_base(dev, ep_hw_idx); - uint8_t ep_dir; - uint8_t ep_idx; - uint8_t ep; - - /* We don't enable INNAKEN interrupt, so as long as EP event occurs, - * we can just regard one data transaction has completed (ACK for - * CTRL/BULK/INT or no-ACK for Iso), that is, no need to check EPSTS0, - * EPSTS1, etc. - */ - - /* EP direction, number, and address */ - ep_dir = ((ep_base->CFG & USBD_CFG_STATE_Msk) == USBD_CFG_EPMODE_IN) - ? USB_EP_DIR_IN - : USB_EP_DIR_OUT; - ep_idx = (ep_base->CFG & USBD_CFG_EPNUM_Msk) >> USBD_CFG_EPNUM_Pos; - ep = USB_EP_GET_ADDR(ep_idx, ep_dir); - - /* NOTE: See comment in udc_numaker_set_address()'s implementation - * for safe place to change USB device address - */ - if (ep == USB_EP_GET_ADDR(0, USB_EP_DIR_IN)) { - numaker_usbd_set_addr(dev); - } - - /* NOTE: See comment on mxpld_ctrlout for why make one copy of - * CTRL OUT's MXPLD - */ - if (ep == USB_EP_GET_ADDR(0, USB_EP_DIR_OUT)) { - struct numaker_usbd_ep *ep_ctrlout = priv->ep_pool + 0; - USBD_EP_T *ep_ctrlout_base = - numaker_usbd_ep_base(dev, ep_ctrlout->ep_hw_idx); - ep_ctrlout->mxpld_ctrlout = ep_ctrlout_base->MXPLD; - } - - /* Message for bottom-half processing */ - if (USB_EP_DIR_IS_OUT(ep)) { - msg.type = NUMAKER_USBD_MSG_TYPE_OUT; - msg.out.ep = ep; - } else { - msg.type = NUMAKER_USBD_MSG_TYPE_IN; - msg.in.ep = ep; - } - numaker_usbd_send_msg(dev, &msg); + numaker_usbd_ep_th(dev, ep_hw_idx); /* Have handled this EP and go next */ epintsts &= ~BIT(ep_hw_idx); @@ -1593,6 +1652,9 @@ static int udc_numaker_disable(const struct device *dev) static int udc_numaker_init(const struct device *dev) { + const struct udc_numaker_config *config = dev->config; + struct udc_data *data = dev->data; + USBD_T *base = config->base; int err; /* Initialize USBD H/W */ @@ -1618,6 +1680,11 @@ static int udc_numaker_init(const struct device *dev) return -EIO; } + /* Enable VBUS detect early */ + if (data->caps.can_detect_vbus) { + base->INTEN = USBD_INT_FLDET; + } + return 0; } @@ -1662,6 +1729,7 @@ static int udc_numaker_driver_preinit(const struct device *dev) data->caps.rwup = true; data->caps.addr_before_status = true; + data->caps.can_detect_vbus = true; data->caps.mps0 = UDC_MPS0_64; /* Some soc series don't allow ISO IN/OUT to be assigned the same EP number. @@ -1747,7 +1815,7 @@ static const struct udc_api udc_numaker_api = { \ static void udc_numaker_irq_config_func_##inst(const struct device *dev) \ { \ - IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), numaker_udbd_isr, \ + IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), numaker_usbd_isr, \ DEVICE_DT_INST_GET(inst), 0); \ \ irq_enable(DT_INST_IRQN(inst)); \ diff --git a/drivers/usb/udc/udc_rpi_pico.c b/drivers/usb/udc/udc_rpi_pico.c index 0aa3cc7e44a5f..b0fb2fcf44f10 100644 --- a/drivers/usb/udc/udc_rpi_pico.c +++ b/drivers/usb/udc/udc_rpi_pico.c @@ -12,13 +12,13 @@ #include #include -#include #include #include #include #include #include +#include #include LOG_MODULE_REGISTER(udc_rpi_pico, CONFIG_UDC_DRIVER_LOG_LEVEL); @@ -36,6 +36,7 @@ struct rpi_pico_config { const struct device *clk_dev; struct pinctrl_dev_config *const pcfg; clock_control_subsys_t clk_sys; + const struct reset_dt_spec reset; }; struct rpi_pico_ep_data { @@ -1025,10 +1026,13 @@ static int udc_rpi_pico_enable(const struct device *dev) const struct pinctrl_dev_config *const pcfg = config->pcfg; usb_device_dpram_t *dpram = config->dpram; usb_hw_t *base = config->base; + int ret; /* Reset USB controller */ - reset_block(RESETS_RESET_USBCTRL_BITS); - unreset_block_wait(RESETS_RESET_USBCTRL_BITS); + ret = reset_line_toggle_dt(&config->reset); + if (ret) { + return ret; + } /* Clear registers and DPRAM */ memset(base, 0, sizeof(usb_hw_t)); @@ -1296,6 +1300,7 @@ static const struct udc_api udc_rpi_pico_api = { .pcfg = UDC_RPI_PICO_PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ .clk_sys = (void *)DT_INST_PHA_BY_IDX(n, clocks, 0, clk_id), \ + .reset = RESET_DT_SPEC_INST_GET(n), \ }; \ \ static struct rpi_pico_data udc_priv_##n = { \ diff --git a/drivers/video/video_stm32_dcmi.c b/drivers/video/video_stm32_dcmi.c index 363de09717b8f..440b2c359ecd8 100644 --- a/drivers/video/video_stm32_dcmi.c +++ b/drivers/video/video_stm32_dcmi.c @@ -136,12 +136,9 @@ static int stm32_dma_init(const struct device *dev) dma_cfg.user_data = &hdma; /* HACK: This field is used to inform driver that it is overridden */ dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE; - /* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */ - ret = dma_config(config->dma.dma_dev, - config->dma.channel + STM32_DMA_STREAM_OFFSET, &dma_cfg); + ret = dma_config(config->dma.dma_dev, config->dma.channel, &dma_cfg); if (ret != 0) { - LOG_ERR("Failed to configure DMA channel %d", - config->dma.channel + STM32_DMA_STREAM_OFFSET); + LOG_ERR("Failed to configure DMA channel %d", config->dma.channel); return ret; } @@ -155,17 +152,12 @@ static int stm32_dma_init(const struct device *dev) hdma.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; hdma.Init.Mode = DMA_CIRCULAR; hdma.Init.Priority = DMA_PRIORITY_HIGH; + hdma.Instance = STM32_DMA_GET_INSTANCE(config->dma.reg, + config->dma.channel); #if defined(CONFIG_SOC_SERIES_STM32F7X) || defined(CONFIG_SOC_SERIES_STM32H7X) hdma.Init.FIFOMode = DMA_FIFOMODE_DISABLE; #endif -#if defined(CONFIG_SOC_SERIES_STM32F7X) || defined(CONFIG_SOC_SERIES_STM32H7X) - hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(config->dma.reg, - config->dma.channel); -#elif defined(CONFIG_SOC_SERIES_STM32L4X) - hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(config->dma.reg, config->dma.channel); -#endif - /* Initialize DMA HAL */ __HAL_LINKDMA(&data->hdcmi, DMA_Handle, hdma); diff --git a/drivers/video/video_stm32_dcmipp.c b/drivers/video/video_stm32_dcmipp.c index a7c182a89e22d..2cd5da210321f 100644 --- a/drivers/video/video_stm32_dcmipp.c +++ b/drivers/video/video_stm32_dcmipp.c @@ -1588,6 +1588,8 @@ static void stm32_dcmipp_isr(const struct device *dev) HAL_DCMIPP_IRQHandler(&dcmipp->hdcmipp); } +#define SOURCE_DEV(inst) DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(inst, 0, 0))) + #define DCMIPP_PIPE_INIT_DEFINE(node_id, inst) \ static struct stm32_dcmipp_pipe_data stm32_dcmipp_pipe_##node_id = { \ .id = DT_NODE_CHILD_IDX(node_id), \ @@ -1598,9 +1600,9 @@ static void stm32_dcmipp_isr(const struct device *dev) &stm32_dcmipp_pipe_##node_id, \ &stm32_dcmipp_config_##inst, \ POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, \ - &stm32_dcmipp_driver_api); - -#define SOURCE_DEV(inst) DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(inst, 0, 0))) + &stm32_dcmipp_driver_api); \ + \ + VIDEO_DEVICE_DEFINE(dcmipp_##inst_pipe_##node_id, DEVICE_DT_GET(node_id), SOURCE_DEV(inst)); #if defined(STM32_DCMIPP_HAS_CSI) #define STM32_DCMIPP_CSI_DT_PARAMS(inst) \ @@ -1620,6 +1622,14 @@ static void stm32_dcmipp_isr(const struct device *dev) #define STM32_DCMIPP_CSI_DT_PARAMS(inst) #endif +#if defined(STM32_DCMIPP_HAS_PIXEL_PIPES) +#define STM32_DCMIPP_PIPES(inst) \ + DT_FOREACH_CHILD_VARGS(DT_INST_CHILD(inst, pipes), DCMIPP_PIPE_INIT_DEFINE, inst) +#else +#define STM32_DCMIPP_PIPE_INIT(node_id, inst) DCMIPP_PIPE_INIT_DEFINE(node_id, inst) +#define STM32_DCMIPP_PIPES(inst) STM32_DCMIPP_PIPE_INIT(DT_INST_CHILD(inst, pipe), inst) +#endif + #define STM32_DCMIPP_INIT(inst) \ static void stm32_dcmipp_irq_config_##inst(const struct device *dev) \ { \ @@ -1661,7 +1671,7 @@ static void stm32_dcmipp_isr(const struct device *dev) vsync_active, 0) ? \ DCMIPP_VSPOLARITY_HIGH : \ DCMIPP_VSPOLARITY_LOW, \ - .parallel.hs_polarity = DT_PROP_OR(DT_INST_ENDPOINT_BY_ID(n, 0, 0), \ + .parallel.hs_polarity = DT_PROP_OR(DT_INST_ENDPOINT_BY_ID(inst, 0, 0), \ hsync_active, 0) ? \ DCMIPP_HSPOLARITY_HIGH : \ DCMIPP_HSPOLARITY_LOW, \ @@ -1677,8 +1687,6 @@ static void stm32_dcmipp_isr(const struct device *dev) POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, \ NULL); \ \ - DT_FOREACH_CHILD_VARGS(DT_INST_PORT_BY_ID(inst, 1), DCMIPP_PIPE_INIT_DEFINE, inst); \ - \ - VIDEO_DEVICE_DEFINE(dcmipp_##inst, DEVICE_DT_INST_GET(inst), SOURCE_DEV(inst)); + STM32_DCMIPP_PIPES(inst) DT_INST_FOREACH_STATUS_OKAY(STM32_DCMIPP_INIT) diff --git a/drivers/w1/w1_zephyr_serial.c b/drivers/w1/w1_zephyr_serial.c index 1bdf461b3d702..a1bb74d7c1a9a 100644 --- a/drivers/w1/w1_zephyr_serial.c +++ b/drivers/w1/w1_zephyr_serial.c @@ -131,8 +131,9 @@ static int w1_serial_reset_bus(const struct device *dev) { const struct w1_serial_config *cfg = dev->config; struct w1_serial_data *data = dev->data; - uint8_t reset_byte = data->overdrive_active ? - W1_SERIAL_OD_RESET_BYTE : W1_SERIAL_STD_RESET_BYTE; + const uint8_t reset_byte_tx = + data->overdrive_active ? W1_SERIAL_OD_RESET_BYTE : W1_SERIAL_STD_RESET_BYTE; + uint8_t reset_byte_rx = 0; /* reset uses 115200/9600=12 slower baudrate, * adjust timeout accordingly, also valid for overdrive speed. */ @@ -145,7 +146,7 @@ static int w1_serial_reset_bus(const struct device *dev) return -EIO; } - if (serial_tx_rx(dev, &reset_byte, &reset_byte, 1, reset_timeout) < 0) { + if (serial_tx_rx(dev, &reset_byte_tx, &reset_byte_rx, 1, reset_timeout) < 0) { LOG_ERR("tx_rx_error reset_present"); return -EIO; } @@ -157,10 +158,11 @@ static int w1_serial_reset_bus(const struct device *dev) return -EIO; } - /* At least 1 device is present on bus, if reset_byte is different - * from 0xF0. But Bus probably shorted if reset_byte is 0x00. + /* At least 1 device is present on bus if reset_byte_rx is different + * from reset_byte_tx (which varies depending on standard or overdrive mode). + * Bus is probably shorted if reset_byte_rx is 0x00. */ - return (reset_byte != W1_SERIAL_STD_RESET_BYTE) && (reset_byte != 0x00); + return (reset_byte_rx != reset_byte_tx) && (reset_byte_rx != 0x00); } static int w1_serial_read_bit(const struct device *dev) diff --git a/drivers/watchdog/wdt_esp32.c b/drivers/watchdog/wdt_esp32.c index acaf7d7ce0c31..c045d8922bab9 100644 --- a/drivers/watchdog/wdt_esp32.c +++ b/drivers/watchdog/wdt_esp32.c @@ -7,7 +7,7 @@ #define DT_DRV_COMPAT espressif_esp32_watchdog -#if defined(CONFIG_SOC_SERIES_ESP32C6) +#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2) #include #else #include diff --git a/drivers/watchdog/wdt_gecko.c b/drivers/watchdog/wdt_gecko.c index 7ec18a9a5747e..f9f8f857f063d 100644 --- a/drivers/watchdog/wdt_gecko.c +++ b/drivers/watchdog/wdt_gecko.c @@ -87,12 +87,25 @@ static int wdt_gecko_convert_window(uint32_t window, uint32_t period) return idx; } +static bool wdt_gecko_is_enabled(WDOG_TypeDef *wdog) +{ +#if defined(CONFIG_SOC_FAMILY_SILABS_S2) + return FIELD_GET(WDOG_EN_EN, wdog->EN); +#else + return FIELD_GET(WDOG_CTRL_EN, wdog->CTRL); +#endif +} + static int wdt_gecko_setup(const struct device *dev, uint8_t options) { const struct wdt_gecko_cfg *config = dev->config; struct wdt_gecko_data *data = dev->data; WDOG_TypeDef *wdog = config->base; + if (wdt_gecko_is_enabled(wdog)) { + return -EBUSY; + } + if (!data->timeout_installed) { LOG_ERR("No valid timeouts installed"); return -EINVAL; @@ -134,8 +147,14 @@ static int wdt_gecko_disable(const struct device *dev) struct wdt_gecko_data *data = dev->data; WDOG_TypeDef *wdog = config->base; - WDOGn_Enable(wdog, false); + /* Always uninstall timeouts, independent of watchdog enable state */ data->timeout_installed = false; + + if (!wdt_gecko_is_enabled(wdog)) { + return -EFAULT; + } + + WDOGn_Enable(wdog, false); LOG_DBG("Disabled the watchdog"); return 0; @@ -144,10 +163,16 @@ static int wdt_gecko_disable(const struct device *dev) static int wdt_gecko_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg) { + const struct wdt_gecko_cfg *config = dev->config; struct wdt_gecko_data *data = dev->data; - data->wdog_config = (WDOG_Init_TypeDef)WDOG_INIT_DEFAULT; uint32_t installed_timeout; + data->wdog_config = (WDOG_Init_TypeDef)WDOG_INIT_DEFAULT; + + if (wdt_gecko_is_enabled(config->base)) { + return -EBUSY; + } + if (data->timeout_installed) { LOG_ERR("No more timeouts can be installed"); return -ENOMEM; @@ -189,13 +214,12 @@ static int wdt_gecko_install_timeout(const struct device *dev, /* Set mode of watchdog and callback */ switch (cfg->flags) { case WDT_FLAG_RESET_SOC: - case WDT_FLAG_RESET_CPU_CORE: if (cfg->callback != NULL) { LOG_ERR("Reset mode with callback not supported\n"); return -ENOTSUP; } data->wdog_config.resetDisable = false; - LOG_DBG("Configuring reset CPU/SoC mode\n"); + LOG_DBG("Configuring reset SoC mode\n"); break; case WDT_FLAG_RESET_NONE: @@ -204,6 +228,10 @@ static int wdt_gecko_install_timeout(const struct device *dev, LOG_DBG("Configuring non-reset mode\n"); break; + case WDT_FLAG_RESET_CPU_CORE: + LOG_ERR("CPU core only reset not supported"); + return -ENOTSUP; + default: LOG_ERR("Unsupported watchdog config flag"); return -EINVAL; @@ -224,6 +252,10 @@ static int wdt_gecko_feed(const struct device *dev, int channel_id) return -EINVAL; } + if (!wdt_gecko_is_enabled(wdog)) { + return -EINVAL; + } + WDOGn_Feed(wdog); LOG_DBG("Fed the watchdog"); diff --git a/drivers/watchdog/wdt_ifx_cat1.c b/drivers/watchdog/wdt_ifx_cat1.c index 5a1b1f67116b6..1c3349d9a13de 100644 --- a/drivers/watchdog/wdt_ifx_cat1.c +++ b/drivers/watchdog/wdt_ifx_cat1.c @@ -7,7 +7,8 @@ #define DT_DRV_COMPAT infineon_cat1_watchdog -#include "cyhal_wdt.h" +#include "cy_wdt.h" +#include "cy_sysclk.h" #include #include @@ -17,8 +18,177 @@ LOG_MODULE_REGISTER(wdt_infineon_cat1, CONFIG_WDT_LOG_LEVEL); #define IFX_CAT1_WDT_IS_IRQ_EN DT_NODE_HAS_PROP(DT_DRV_INST(0), interrupts) +typedef struct { + /* Minimum period in milliseconds that can be represented with this + * many ignored bits + */ + uint32_t min_period_ms; + /* Timeout threshold in milliseconds from which to round up to + * the minimum period + */ + uint32_t round_threshold_ms; +} wdt_ignore_bits_data_t; + +#if defined(CY_IP_MXS40SRSS) || defined(CY_IP_MXS40SSRSS) +#define ifx_wdt_lock() Cy_WDT_Lock() +#define ifx_wdt_unlock() Cy_WDT_Unlock() +#else +#define ifx_wdt_lock() +#define ifx_wdt_unlock() +#endif + +#if defined(SRSS_NUM_WDT_A_BITS) +#define IFX_WDT_MATCH_BITS (SRSS_NUM_WDT_A_BITS) +#elif defined(COMPONENT_CAT1A) +#if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2) +#define IFX_WDT_MATCH_BITS (16) +#endif +#elif defined(COMPONENT_CAT1B) +#define IFX_WDT_MATCH_BITS (16) +#else +#error Unhandled device type +#endif + +/* match range: 0 -> 2^(IFX_WDT_MATCH_BITS - ignore_bits) + * ignore_bits range: 0 -> (IFX_WDT_MATCH_BITS - 4) (Bottom four bits cannot be ignored) + * WDT Reset Period (timeout_ms) = CLK_DURATION * (2 * 2^(IFX_WDT_MATCH_BITS - ignore_bits) + match) + * Max WDT Reset Period = 3 * (2^IFX_WDT_MATCH_BITS) * CLK_DURATION + */ +#if defined(CY_IP_MXS40SRSS) +/* ILO, PILO, BAK all run at 32768 Hz - Period is ~0.030518 ms */ +#define IFX_WDT_MAX_TIMEOUT_MS 6000 +#define IFX_WDT_MAX_IGNORE_BITS 12 +/* ILO Frequency = 32768 Hz, ILO Period = 1 / 32768 Hz = .030518 ms */ +static const wdt_ignore_bits_data_t ifx_wdt_ignore_data[] = { + {4000, 3001}, /* 0 bit(s): min period: 4000ms, max period: 6000ms, round up from 3001+ms */ + {2000, 1501}, /* 1 bit(s): min period: 2000ms, max period: 3000ms, round up from 1501+ms */ + {1000, 751}, /* 2 bit(s): min period: 1000ms, max period: 1500ms, round up from 751+ms */ + {500, 376}, /* 3 bit(s): min period: 500ms, max period: 750ms, round up from 376+ms */ + {250, 188}, /* 4 bit(s): min period: 250ms, max period: 375ms, round up from 188+ms */ + {125, 94}, /* 5 bit(s): min period: 125ms, max period: 187ms, round up from 94+ms */ + {63, 47}, /* 6 bit(s): min period: 63ms, max period: 93ms, round up from 47+ms */ + {32, 24}, /* 7 bit(s): min period: 32ms, max period: 46ms, round up from 24+ms */ + {16, 12}, /* 8 bit(s): min period: 16ms, max period: 23ms, round up from 12+ms */ + {8, 6}, /* 9 bit(s): min period: 8ms, max period: 11ms, round up from 6+ms */ + {4, 3}, /* 10 bit(s): min period: 4ms, max period: 5ms, round up from 3+ms */ + {2, 2}, /* 11 bit(s): min period: 2ms, max period: 2ms, round up from 2+ms */ + {1, 1}, /* 12 bit(s): min period: 1ms, max period: 1ms, round up from 1+ms */ +}; +#elif defined(CY_IP_MXS40SSRSS) && (IFX_WDT_MATCH_BITS == 22) +/* ILO Frequency = 32768 Hz, ILO Period = 1 / 32768 Hz = .030518 ms */ +#define IFX_WDT_MAX_TIMEOUT_MS 384000 +#define IFX_WDT_MAX_IGNORE_BITS (IFX_WDT_MATCH_BITS - 4) +static const wdt_ignore_bits_data_t ifx_wdt_ignore_data[] = { + /* 0 bit(s): min period: 256000ms, max period: 384000ms, round up from 192001+ms */ + {256000, 192001}, + /* 1 bit(s): min period: 128000ms, max period: 192000ms, round up from 96001+ms */ + {128000, 96001}, + /* 2 bit(s): min period: 64000ms, max period: 96000ms, round up from 48001+ms */ + {64000, 48001}, + /* 3 bit(s): min period: 32000ms, max period: 48000ms, round up from 24001+ms */ + {32000, 24001}, + /* 4 bit(s): min period: 16000ms, max period: 24000ms, round up from 12001+ms */ + {16000, 12001}, + /* 5 bit(s): min period:8000ms, max period: 12000ms, round up from 6001+ms */ + {8000, 6001}, + /* 6 bit(s): min period:4000ms, max period:6000ms, round up from 3001+ms */ + {4000, 3001}, + /* 7 bit(s): min period:2000ms, max period:3000ms, round up from 1501+ms */ + {2000, 1501}, + /* 8 bit(s): min period:1000ms, max period:1500ms, round up from 751+ms */ + {1000, 751}, + /* 9 bit(s): min period: 500ms, max period: 750ms, round up from 376+ms */ + {500, 376}, + /* 10 bit(s): min period: 250ms, max period: 375ms, round up from 188+ms */ + {250, 188}, + /* 11 bit(s): min period: 125ms, max period: 187ms, round up from 94+ms */ + {125, 94}, + /* 12 bit(s): min period: 63ms, max period: 93ms, round up from 47+ms */ + {63, 47}, + /* 13 bit(s): min period: 32ms, max period: 46ms, round up from 24+ms */ + {32, 24}, + /* 14 bit(s): min period: 16ms, max period: 23ms, round up from 12+ms */ + {16, 12}, + /* 15 bit(s): min period: 8ms, max period: 11ms, round up from 6+ms */ + {8, 6}, + /* 16 bit(s): min period: 4ms, max period: 5ms, round up from 3+ms */ + {4, 3}, + /* 17 bit(s): min period: 2ms, max period: 2ms, round up from 2+ms */ + {2, 2}, + /* 18 bit(s): min period: 1ms, max period: 1ms, round up from 1+ms */ + {1, 1}, +}; +#elif defined(CY_IP_MXS40SSRSS) && (IFX_WDT_MATCH_BITS == 32) +/* ILO Frequency = 32768 Hz, ILO Period = 1 / 32768 Hz = .030518 ms */ +#define IFX_WDT_MAX_TIMEOUT_MS 393211435 +#define IFX_WDT_MAX_IGNORE_BITS (IFX_WDT_MATCH_BITS - 4) +static const wdt_ignore_bits_data_t ifx_wdt_ignore_data[] = { + /* 0 bit(s): min period: 262147000ms, max period: 393221000ms, round up from 196610001+ms */ + {262147000, 196610001}, + /* 1 bit(s): min period: 131073000ms, max period: 196610000ms, round up from 98305001+ms */ + {131073000, 98305001}, + /* 2 bit(s): min period: 65537000ms, max period: 98305000ms, round up from 49152001+ms */ + {65537000, 49152001}, + /* 3 bit(s): min period: 32768000ms, max period: 49152000ms, round up from 24576001+ms */ + {32768000, 24576001}, + /* 4 bit(s): min period: 16384000ms, max period: 24576000ms, round up from 12288001+ms */ + {16384000, 12288001}, + /* 5 bit(s): min period: 8192000ms, max period: 12288000ms, round up from 6144001+ms */ + {8192000, 6144001}, + /* 6 bit(s): min period: 4096000ms, max period: 6144000ms, round up from 3072001+ms */ + {4096000, 3072001}, + /* 7 bit(s): min period: 2048000ms, max period: 3072000ms, round up from 1536001+ms */ + {2048000, 1536001}, + /* 8 bit(s): min period: 1024000ms, max period: 1536000ms, round up from 768001+ms */ + {1024000, 768001}, + /* 9 bit(s): min period: 512000ms, max period: 768000ms, round up from 384001+ms */ + {512000, 384001}, + /* 10 bit(s): min period: 256000ms, max period: 384000ms, round up from 192001+ms */ + {256000, 192001}, + /* 11 bit(s): min period: 128000ms, max period: 192000ms, round up from 96001+ms */ + {128000, 96001}, + /* 12 bit(s): min period: 64000ms, max period: 96000ms, round up from 48001+ms */ + {64000, 48001}, + /* 13 bit(s): min period: 32000ms, max period: 48000ms, round up from 24001+ms */ + {32000, 24001}, + /* 14 bit(s): min period: 16000ms, max period: 24000ms, round up from 12001+ms */ + {16000, 12001}, + /* 15 bit(s): min period: 8000ms, max period: 12000ms, round up from 6001+ms */ + {8000, 6001}, + /* 16 bit(s): min period: 4000ms, max period: 6000ms, round up from 3001+ms */ + {4000, 3001}, + /* 17 bit(s): min period: 2000ms, max period: 3000ms, round up from 1501+ms */ + {2000, 1501}, + /* 18 bit(s): min period: 1000ms, max period: 1500ms, round up from 751+ms */ + {1000, 751}, + /* 19 bit(s): min period: 500ms, max period: 750ms, round up from 376+ms */ + {500, 376}, + /* 20 bit(s): min period: 250ms, max period: 375ms, round up from 188+ms */ + {250, 188}, + /* 21 bit(s): min period: 125ms, max period: 187ms, round up from 94+ms */ + {125, 94}, + /* 22 bit(s): min period: 63ms, max period: 93ms, round up from 47+ms */ + {63, 47}, + /* 23 bit(s): min period: 32ms, max period: 46ms, round up from 24+ms */ + {32, 24}, + /* 24 bit(s): min period: 16ms, max period: 23ms, round up from 12+ms */ + {16, 12}, + /* 25 bit(s): min period: 8ms, max period: 11ms, round up from 6+ms */ + {8, 6}, + /* 26 bit(s): min period: 4ms, max period: 5ms, round up from 3+ms */ + {4, 3}, + /* 27 bit(s): min period: 2ms, max period: 2ms, round up from 2+ms */ + {2, 2}, + /* 28 bit(s): min period: 1ms, max period: 1ms, round up from 1+ms */ + {1, 1}, +}; +#endif + struct ifx_cat1_wdt_data { - cyhal_wdt_t obj; + bool wdt_initialized; + uint32_t wdt_initial_timeout_ms; + uint32_t wdt_rounded_timeout_ms; + uint32_t wdt_ignore_bits; #ifdef IFX_CAT1_WDT_IS_IRQ_EN wdt_callback_t callback; #endif /* IFX_CAT1_WDT_IS_IRQ_EN */ @@ -26,7 +196,33 @@ struct ifx_cat1_wdt_data { bool timeout_installed; }; -struct ifx_cat1_wdt_data wdt_data; +static struct ifx_cat1_wdt_data wdt_data; + +#define IFX_DETERMINE_MATCH_BITS(bits) ((IFX_WDT_MAX_IGNORE_BITS) - (bits)) +#define IFX_GET_COUNT_FROM_MATCH_BITS(bits) (2UL << IFX_DETERMINE_MATCH_BITS(bits)) + +__STATIC_INLINE uint32_t ifx_wdt_timeout_to_match(uint32_t timeout_ms, uint32_t ignore_bits) +{ + uint32_t wrap_count_for_ignore_bits = (IFX_GET_COUNT_FROM_MATCH_BITS(ignore_bits)); + uint32_t timeout_count = ((timeout_ms * CY_SYSCLK_ILO_FREQ) / 1000UL); + /* handle multiple possible wraps of WDT counter */ + timeout_count = ((timeout_count + Cy_WDT_GetCount()) % wrap_count_for_ignore_bits); + return timeout_count; +} + +/* Rounds up *timeout_ms if it's outside of the valid timeout range (ifx_wdt_ignore_data) */ +__STATIC_INLINE uint32_t ifx_wdt_timeout_to_ignore_bits(uint32_t *timeout_ms) +{ + for (uint32_t i = 0; i <= IFX_WDT_MAX_IGNORE_BITS; i++) { + if (*timeout_ms >= ifx_wdt_ignore_data[i].round_threshold_ms) { + if (*timeout_ms < ifx_wdt_ignore_data[i].min_period_ms) { + *timeout_ms = ifx_wdt_ignore_data[i].min_period_ms; + } + return i; + } + } + return IFX_WDT_MAX_IGNORE_BITS; /* Ideally should never reach this */ +} #ifdef IFX_CAT1_WDT_IS_IRQ_EN static void ifx_cat1_wdt_isr_handler(const struct device *dev) @@ -42,13 +238,59 @@ static void ifx_cat1_wdt_isr_handler(const struct device *dev) static int ifx_cat1_wdt_setup(const struct device *dev, uint8_t options) { - cy_rslt_t result; struct ifx_cat1_wdt_data *dev_data = dev->data; /* Initialize the WDT */ - result = cyhal_wdt_init(&dev_data->obj, dev_data->timeout); - if (result != CY_RSLT_SUCCESS) { - LOG_ERR("Initialization failure : 0x%x", result); + if ((dev_data->timeout == 0) || (dev_data->timeout > IFX_WDT_MAX_TIMEOUT_MS)) { + return -ENOTSUP; + } + + if (dev_data->wdt_initialized) { + return -EBUSY; + } + + /* Unlock and disable before doing other work */ + ifx_wdt_unlock(); + Cy_WDT_Disable(); + + Cy_WDT_ClearInterrupt(); + Cy_WDT_MaskInterrupt(); + + dev_data->wdt_initial_timeout_ms = dev_data->timeout; +#if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2) + Cy_WDT_SetUpperLimit(ifx_wdt_timeout_to_match(dev_data->wdt_initial_timeout_ms)); + Cy_WDT_SetUpperAction(CY_WDT_LOW_UPPER_LIMIT_ACTION_RESET); +#else + dev_data->wdt_ignore_bits = ifx_wdt_timeout_to_ignore_bits(&dev_data->timeout); + dev_data->wdt_rounded_timeout_ms = dev_data->timeout; +#if defined(SRSS_NUM_WDT_A_BITS) && (SRSS_NUM_WDT_A_BITS == 22) + /* Cy_WDT_SetMatchBits configures the bit position above which the bits will be ignored for + * match, while ifx_wdt_timeout_to_ignore_bits returns number of timer MSB to ignore, so + * conversion is needed. + */ + Cy_WDT_SetMatchBits(IFX_DETERMINE_MATCH_BITS(dev_data->wdt_ignore_bits)); +#else + Cy_WDT_SetIgnoreBits(dev_data->wdt_ignore_bits); +#endif + +#if defined(COMPONENT_CAT1) && (CY_WDT_DRV_VERSION_MAJOR > 1) && (CY_WDT_DRV_VERSION_MINOR > 6) + /* Reset counter every time - large current counts in WDT can cause problems on some boards + */ + Cy_WDT_ResetCounter(); + /* Twice, as reading back after 1 reset gives same value as before single reset */ + Cy_WDT_ResetCounter(); +#endif + + Cy_WDT_SetMatch(ifx_wdt_timeout_to_match(dev_data->wdt_rounded_timeout_ms, + dev_data->wdt_ignore_bits)); +#endif + + Cy_WDT_Enable(); + ifx_wdt_lock(); + + dev_data->wdt_initialized = true; + + if (!Cy_WDT_IsEnabled()) { return -ENOMSG; } @@ -71,7 +313,11 @@ static int ifx_cat1_wdt_disable(const struct device *dev) irq_disable(DT_INST_IRQN(0)); #endif /* IFX_CAT1_WDT_IS_IRQ_EN */ - cyhal_wdt_free(&dev_data->obj); + ifx_wdt_unlock(); + Cy_WDT_Disable(); + ifx_wdt_lock(); + + dev_data->wdt_initialized = false; return 0; } @@ -116,7 +362,11 @@ static int ifx_cat1_wdt_feed(const struct device *dev, int channel_id) return -EINVAL; } - cyhal_wdt_kick(&data->obj); + ifx_wdt_unlock(); + Cy_WDT_ClearWatchdog(); /* Clear to prevent reset from WDT */ + Cy_WDT_SetMatch( + ifx_wdt_timeout_to_match(data->wdt_rounded_timeout_ms, data->wdt_ignore_bits)); + ifx_wdt_lock(); return 0; } diff --git a/drivers/watchdog/wdt_iwdg_stm32.c b/drivers/watchdog/wdt_iwdg_stm32.c index 682963b10701b..95dec9ad412c6 100644 --- a/drivers/watchdog/wdt_iwdg_stm32.c +++ b/drivers/watchdog/wdt_iwdg_stm32.c @@ -105,6 +105,8 @@ static int iwdg_stm32_setup(const struct device *dev, uint8_t options) LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG1_STOP); #elif defined(CONFIG_SOC_SERIES_STM32H7RSX) LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG_STOP); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_IWDG4_STOP); #else LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP); #endif diff --git a/drivers/watchdog/wdt_wwdg_stm32.c b/drivers/watchdog/wdt_wwdg_stm32.c index 5c8441c8ea3fa..e9ff988a5f3ed 100644 --- a/drivers/watchdog/wdt_wwdg_stm32.c +++ b/drivers/watchdog/wdt_wwdg_stm32.c @@ -173,7 +173,8 @@ static int wwdg_stm32_setup(const struct device *dev, uint8_t options) #elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); #endif -#if defined(CONFIG_SOC_SERIES_STM32H7X) + +#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP2X) LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_WWDG1_STOP); #elif defined(CONFIG_SOC_SERIES_STM32MP1X) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG1_STOP); diff --git a/drivers/wifi/esp32/src/esp_wifi_drv.c b/drivers/wifi/esp32/src/esp_wifi_drv.c index b6ce07024bc9e..23fd30a488418 100644 --- a/drivers/wifi/esp32/src/esp_wifi_drv.c +++ b/drivers/wifi/esp32/src/esp_wifi_drv.c @@ -13,9 +13,11 @@ LOG_MODULE_REGISTER(esp32_wifi, CONFIG_WIFI_LOG_LEVEL); #include #include #include +#if defined(CONFIG_NET_CONNECTION_MANAGER_CONNECTIVITY_WIFI_MGMT) +#include +#endif #if defined(CONFIG_ESP32_WIFI_AP_STA_MODE) #include -#include #endif #include #include @@ -993,6 +995,8 @@ NET_DEVICE_DT_INST_DEFINE(1, NET_L2_GET_CTX_TYPE(ETHERNET_L2), NET_ETH_MTU); DEFINE_WIFI_NM_INSTANCE(esp32_wifi_nm, &esp32_wifi_mgmt); +#endif +#if defined(CONFIG_NET_CONNECTION_MANAGER_CONNECTIVITY_WIFI_MGMT) CONNECTIVITY_WIFI_MGMT_BIND(Z_DEVICE_DT_DEV_ID(DT_DRV_INST(0))); #endif diff --git a/drivers/wifi/infineon/airoc_wifi.c b/drivers/wifi/infineon/airoc_wifi.c index d7df41bd01e18..9c6747a5254ce 100644 --- a/drivers/wifi/infineon/airoc_wifi.c +++ b/drivers/wifi/infineon/airoc_wifi.c @@ -258,7 +258,7 @@ static void scan_callback(whd_scan_result_t **result_ptr, void *user_data, whd_s return; } - /* We recived scan data so process it */ + /* We received scan data so process it */ if ((result_ptr != NULL) && (*result_ptr != NULL)) { memcpy(&whd_scan_result, *result_ptr, sizeof(whd_scan_result_t)); parse_scan_result(&whd_scan_result, &zephyr_scan_result); diff --git a/drivers/wifi/nrf_wifi/Kconfig.nrfwifi b/drivers/wifi/nrf_wifi/Kconfig.nrfwifi index 4b3bb0d41ca25..9b37c302872b8 100644 --- a/drivers/wifi/nrf_wifi/Kconfig.nrfwifi +++ b/drivers/wifi/nrf_wifi/Kconfig.nrfwifi @@ -934,4 +934,14 @@ config NRF_WIFI_DYNAMIC_ED help This option enables support for proprietary algorithm to enhance performance in high-traffic channels. + +config NRF_WIFI_TWT_SETUP_TIMEOUT_MS + int "TWT setup timeout (ms)" + range 100 10000 + default 250 + help + Timeout duration (in milliseconds) for the TWT setup procedure. + The STA will transmit a TWT setup request every 100 milliseconds, + continuing until this timeout value is reached. If no response is + received before the timeout expires, the TWT setup is considered failed. endif # WIFI_NRF70 diff --git a/drivers/wifi/nrf_wifi/src/wifi_mgmt.c b/drivers/wifi/nrf_wifi/src/wifi_mgmt.c index e9755e80013eb..e48ae31734a73 100644 --- a/drivers/wifi/nrf_wifi/src/wifi_mgmt.c +++ b/drivers/wifi/nrf_wifi/src/wifi_mgmt.c @@ -564,6 +564,7 @@ int nrf_wifi_set_twt(const struct device *dev, twt_info.dialog_token = twt_params->dialog_token; twt_info.twt_wake_ahead_duration = twt_params->setup.twt_wake_ahead_duration; + twt_info.twt_req_timeout = CONFIG_NRF_WIFI_TWT_SETUP_TIMEOUT_MS; status = nrf_wifi_sys_fmac_twt_setup(rpu_ctx_zep->rpu_ctx, vif_ctx_zep->vif_idx, diff --git a/drivers/wifi/nrf_wifi/src/wpa_supp_if.c b/drivers/wifi/nrf_wifi/src/wpa_supp_if.c index 2314d7992bd01..9f1fff535454b 100644 --- a/drivers/wifi/nrf_wifi/src/wpa_supp_if.c +++ b/drivers/wifi/nrf_wifi/src/wpa_supp_if.c @@ -1578,6 +1578,7 @@ enum nrf_wifi_status nrf_wifi_parse_sband( band->ht_cap.wpa_supp_ampdu_factor = event->ht_cap.nrf_wifi_ampdu_factor; band->ht_cap.wpa_supp_ampdu_density = event->ht_cap.nrf_wifi_ampdu_density; +#ifndef CONFIG_WIFI_NM_WPA_SUPPLICANT_AP band->vht_cap.wpa_supp_vht_supported = event->vht_cap.nrf_wifi_vht_supported; band->vht_cap.wpa_supp_cap = event->vht_cap.nrf_wifi_cap; @@ -1585,6 +1586,7 @@ enum nrf_wifi_status nrf_wifi_parse_sband( band->vht_cap.vht_mcs.rx_highest = event->vht_cap.vht_mcs.rx_highest; band->vht_cap.vht_mcs.tx_mcs_map = event->vht_cap.vht_mcs.tx_mcs_map; band->vht_cap.vht_mcs.tx_highest = event->vht_cap.vht_mcs.tx_highest; +#endif /* !CONFIG_WIFI_NM_WPA_SUPPLICANT_AP */ band->band = event->band; diff --git a/drivers/wifi/nxp/nxp_wifi_drv.c b/drivers/wifi/nxp/nxp_wifi_drv.c index 5890190fe3143..21fea55dd9713 100644 --- a/drivers/wifi/nxp/nxp_wifi_drv.c +++ b/drivers/wifi/nxp/nxp_wifi_drv.c @@ -579,6 +579,10 @@ static int nxp_wifi_start_ap(const struct device *dev, struct wifi_connect_req_p wlan_uap_set_hidden_ssid(params->ignore_broadcast_ssid); } + if (params->bandwidth == 0) { + params->bandwidth = WIFI_FREQ_BANDWIDTH_20MHZ; + } + switch (params->bandwidth) { case WIFI_FREQ_BANDWIDTH_20MHZ: case WIFI_FREQ_BANDWIDTH_40MHZ: diff --git a/drivers/wifi/siwx91x/siwx91x_wifi.c b/drivers/wifi/siwx91x/siwx91x_wifi.c index 5e3650d04dda4..f7f9873b526cb 100644 --- a/drivers/wifi/siwx91x/siwx91x_wifi.c +++ b/drivers/wifi/siwx91x/siwx91x_wifi.c @@ -19,6 +19,8 @@ #include "sl_wifi_callback_framework.h" #define SIWX91X_DRIVER_VERSION KERNEL_VERSION_STRING +#define SIWX91X_MAX_RTS_THRESHOLD 2347 +#define MAX_24GHZ_CHANNELS 14 LOG_MODULE_REGISTER(siwx91x_wifi); @@ -43,7 +45,7 @@ int siwx91x_status(const struct device *dev, struct wifi_iface_status *status) sl_wifi_interface_t interface = sl_wifi_get_default_interface(); sl_si91x_rsp_wireless_info_t wlan_info = { }; struct siwx91x_dev *sidev = dev->data; - uint8_t join_config; + sl_wifi_mfp_mode_t mfp; int32_t rssi; int ret; @@ -81,25 +83,15 @@ int siwx91x_status(const struct device *dev, struct wifi_iface_status *status) status->channel = wlan_info.channel_number; status->twt_capable = true; - ret = sl_si91x_get_join_configuration(interface, &join_config); + ret = sl_wifi_get_mfp(interface, &mfp); if (ret) { - LOG_ERR("Failed to get join configuration: 0x%x", ret); + LOG_ERR("Failed to get MFP configuration: 0x%x", ret); return -EINVAL; } - - if (wlan_info.sec_type == SL_WIFI_WPA3) { - status->mfp = WIFI_MFP_REQUIRED; - } else if (wlan_info.sec_type == SL_WIFI_WPA3_TRANSITION) { - status->mfp = WIFI_MFP_OPTIONAL; - } else if (wlan_info.sec_type == SL_WIFI_WPA2) { - if (join_config & SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED) { - status->mfp = WIFI_MFP_REQUIRED; - } else { - status->mfp = WIFI_MFP_OPTIONAL; - } - } else { - status->mfp = WIFI_MFP_DISABLE; - } + /* The Wiseconnect mfp values match the values expected by + * Zephyr's mfp, even though the enum type differs. + */ + status->mfp = mfp; ret = sl_wifi_get_signal_strength(SL_WIFI_CLIENT_INTERFACE, &rssi); if (ret) { @@ -369,6 +361,83 @@ static int siwx91x_get_version(const struct device *dev, struct wifi_version *pa return 0; } +static int map_sdk_region_to_zephyr_channel_info(const sli_si91x_set_region_ap_request_t *sdk_reg, + struct wifi_reg_chan_info *z_chan_info, + size_t *num_channels) +{ + uint8_t first_channel = sdk_reg->channel_info[0].first_channel; + uint8_t channel; + uint16_t freq; + + *num_channels = sdk_reg->channel_info[0].no_of_channels; + if (*num_channels > MAX_24GHZ_CHANNELS) { + return -EOVERFLOW; + } + + for (int idx = 0; idx < *num_channels; idx++) { + channel = first_channel + idx; + freq = 2407 + channel * 5; + + if (freq > 2472) { + freq = 2484; /* channel 14 */ + } + + z_chan_info[idx].center_frequency = freq; + z_chan_info[idx].max_power = sdk_reg->channel_info[0].max_tx_power; + z_chan_info[idx].supported = 1; + z_chan_info[idx].passive_only = 0; + z_chan_info[idx].dfs = 0; + } + + return 0; +} + +static int siwx91x_wifi_reg_domain(const struct device *dev, struct wifi_reg_domain *reg_domain) +{ + const sli_si91x_set_region_ap_request_t *sdk_reg = NULL; + sl_wifi_operation_mode_t oper_mode = sli_get_opermode(); + sl_wifi_region_code_t region_code; + const char *country_code; + int ret; + + __ASSERT(reg_domain, "reg_domain cannot be NULL"); + + if (reg_domain->oper == WIFI_MGMT_SET) { + region_code = siwx91x_map_country_code_to_region(reg_domain->country_code); + ret = sl_si91x_set_device_region(oper_mode, SL_WIFI_BAND_MODE_2_4GHZ, region_code); + if (ret) { + LOG_ERR("Failed to set device region: %x", ret); + return -EINVAL; + } + + if (region_code == SL_WIFI_DEFAULT_REGION) { + siwx91x_store_country_code(DEFAULT_COUNTRY_CODE); + LOG_INF("Country code not supported, using default region"); + } else { + siwx91x_store_country_code(reg_domain->country_code); + } + } else if (reg_domain->oper == WIFI_MGMT_GET) { + country_code = siwx91x_get_country_code(); + memcpy(reg_domain->country_code, country_code, WIFI_COUNTRY_CODE_LEN); + region_code = siwx91x_map_country_code_to_region(country_code); + + sdk_reg = siwx91x_find_sdk_region_table(region_code); + if (!sdk_reg) { + return -ENOENT; + } + + ret = map_sdk_region_to_zephyr_channel_info(sdk_reg, reg_domain->chan_info, + ®_domain->num_channels); + if (ret) { + return ret; + } + } else { + return -EINVAL; + } + + return 0; +} + static void siwx91x_iface_init(struct net_if *iface) { const struct siwx91x_config *siwx91x_cfg = iface->if_dev->dev->config; @@ -410,6 +479,57 @@ static void siwx91x_iface_init(struct net_if *iface) sidev->state = WIFI_STATE_INACTIVE; } +int siwx91x_get_rts_threshold(const struct device *dev, unsigned int *rts_threshold) +{ + sl_wifi_interface_t interface = sl_wifi_get_default_interface(); + struct siwx91x_dev *sidev = dev->data; + unsigned short rts_val; + int ret; + + __ASSERT(rts_threshold, "rts_threshold cannot be NULL"); + + if (sidev->state == WIFI_STATE_INTERFACE_DISABLED) { + LOG_ERR("Command given in invalid state"); + return -EINVAL; + } + + ret = sl_wifi_get_rts_threshold(interface, &rts_val); + if (ret) { + LOG_ERR("Failed to get RTS threshold: 0x%x", ret); + return -EIO; + } + *rts_threshold = rts_val; + + return 0; +} + +int siwx91x_set_rts_threshold(const struct device *dev, unsigned int rts_threshold) +{ + sl_wifi_interface_t interface = sl_wifi_get_default_interface(); + struct siwx91x_dev *sidev = dev->data; + int ret; + + __ASSERT(sidev, "sidev cannot be NULL"); + + if (sidev->state == WIFI_STATE_INTERFACE_DISABLED) { + LOG_ERR("Command given in invalid state"); + return -EINVAL; + } + + if (rts_threshold > SIWX91X_MAX_RTS_THRESHOLD) { + LOG_ERR("RTS threshold out of range: %u", rts_threshold); + return -EINVAL; + } + + ret = sl_wifi_set_rts_threshold(interface, rts_threshold); + if (ret) { + LOG_ERR("Failed to set RTS threshold: 0x%x", ret); + return -EIO; + } + + return 0; +} + static int siwx91x_dev_init(const struct device *dev) { return 0; @@ -428,10 +548,13 @@ static const struct wifi_mgmt_ops siwx91x_mgmt = { .set_twt = siwx91x_set_twt, .set_power_save = siwx91x_set_power_save, .get_power_save_config = siwx91x_get_power_save_config, + .get_rts_threshold = siwx91x_get_rts_threshold, + .set_rts_threshold = siwx91x_set_rts_threshold, #if defined(CONFIG_NET_STATISTICS_WIFI) .get_stats = siwx91x_stats, #endif .get_version = siwx91x_get_version, + .reg_domain = siwx91x_wifi_reg_domain, }; static const struct net_wifi_mgmt_offload siwx91x_api = { diff --git a/drivers/wifi/siwx91x/siwx91x_wifi_sta.c b/drivers/wifi/siwx91x/siwx91x_wifi_sta.c index 6037d7c0ce687..1ba53d6cb2563 100644 --- a/drivers/wifi/siwx91x/siwx91x_wifi_sta.c +++ b/drivers/wifi/siwx91x/siwx91x_wifi_sta.c @@ -107,55 +107,6 @@ sl_status_t siwx91x_wifi_module_stats_event_handler(sl_wifi_event_t event, void return 0; } -static enum wifi_mfp_options siwx91x_set_sta_mfp_option(sl_wifi_security_t security, - enum wifi_mfp_options mfp_conf) -{ - uint8_t join_config; - - switch (security) { - case SL_WIFI_OPEN: - case SL_WIFI_WPA: - return WIFI_MFP_DISABLE; - case SL_WIFI_WPA2: - case SL_WIFI_WPA_WPA2_MIXED: - if (mfp_conf == WIFI_MFP_REQUIRED) { - /* Handling the case for WPA2_SHA256 security type */ - /* Directly enabling the MFP Required bit in the Join Feature - * bitmap. This ensures that MFP is enforced for connections using - * WPA2_SHA256. - * - * Note: This is a workaround to configure MFP as the current SDK - * does not provide a dedicated API to configure MFP settings. - * By manipulating the join feature bitmap directly, we achieve - * the desired MFP configuration for enhanced security. - * - * This case will be updated in the future when the SDK adds - * dedicated support for configuring MFP. - */ - sl_si91x_get_join_configuration(SL_WIFI_CLIENT_INTERFACE, &join_config); - join_config |= SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED; - sl_si91x_set_join_configuration(SL_WIFI_CLIENT_INTERFACE, join_config); - return WIFI_MFP_REQUIRED; - } - /* Handling the case for WPA2 security type */ - /* Ensuring the connection happened in WPA2-PSK - * by clearing the MFP Required bit in the Join Feature bitmap. - */ - sl_si91x_get_join_configuration(SL_WIFI_CLIENT_INTERFACE, &join_config); - join_config &= ~(SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED); - sl_si91x_set_join_configuration(SL_WIFI_CLIENT_INTERFACE, join_config); - return WIFI_MFP_OPTIONAL; - case SL_WIFI_WPA3: - return WIFI_MFP_REQUIRED; - case SL_WIFI_WPA3_TRANSITION: - return WIFI_MFP_OPTIONAL; - default: - return WIFI_MFP_DISABLE; - } - - return WIFI_MFP_UNKNOWN; -} - unsigned int siwx91x_on_join(sl_wifi_event_t event, char *result, uint32_t result_size, void *arg) { @@ -252,7 +203,6 @@ int siwx91x_connect(const struct device *dev, struct wifi_connect_req_params *pa .credential_id = SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID, }; struct siwx91x_dev *sidev = dev->data; - enum wifi_mfp_options mfp_conf; int ret; if (sidev->state == WIFI_STATE_COMPLETED) { @@ -320,15 +270,14 @@ int siwx91x_connect(const struct device *dev, struct wifi_connect_req_params *pa return -EINVAL; } - if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) { - mfp_conf = siwx91x_set_sta_mfp_option(wifi_config.security, WIFI_MFP_REQUIRED); - } else { - mfp_conf = siwx91x_set_sta_mfp_option(wifi_config.security, params->mfp); - } - - if (params->mfp != mfp_conf) { - LOG_WRN("Needed MFP %s but got MFP %s, hence setting to MFP %s", - wifi_mfp_txt(mfp_conf), wifi_mfp_txt(params->mfp), wifi_mfp_txt(mfp_conf)); + /* The Zephyr mfp values match the values expected by + * Wiseconnect's mfp, even though the enum type differs. + */ + ret = sl_wifi_set_mfp(interface, (sl_wifi_mfp_mode_t)params->mfp); + if (ret != SL_STATUS_OK) { + LOG_ERR("Failed to set MFP: 0x%x", ret); + wifi_mgmt_raise_connect_result_event(sidev->iface, WIFI_STATUS_CONN_FAIL); + return -EINVAL; } if (params->channel != WIFI_CHANNEL_ANY) { diff --git a/dts/arm/adi/max32/max32666.dtsi b/dts/arm/adi/max32/max32666.dtsi index 896f91dd9c49f..756139a4bee59 100644 --- a/dts/arm/adi/max32/max32666.dtsi +++ b/dts/arm/adi/max32/max32666.dtsi @@ -6,6 +6,7 @@ #include #include +#include &clk_ipo { clock-frequency = ; diff --git a/dts/arm/atmel/sam4e.dtsi b/dts/arm/atmel/sam4e.dtsi index c90fed140b3f6..d643ca749621b 100644 --- a/dts/arm/atmel/sam4e.dtsi +++ b/dts/arm/atmel/sam4e.dtsi @@ -165,24 +165,26 @@ status = "disabled"; }; - gmac: ethernet@40034000 { - compatible = "atmel,sam-gmac"; + ethernet@40034000 { + compatible = "microchip,sam-ethernet-controller"; reg = <0x40034000 0x4000>; clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; - interrupts = <44 0>; - interrupt-names = "gmac"; - num-queues = <1>; - phy-connection-type = "mii"; - status = "disabled"; - }; - mdio: mdio@40034000 { - compatible = "atmel,sam-mdio"; - reg = <0x40034000 0x4000>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; + gmac: ethernet { + compatible = "atmel,sam-gmac"; + interrupts = <44 0>; + interrupt-names = "gmac"; + num-queues = <1>; + phy-connection-type = "mii"; + status = "disabled"; + }; + + mdio: mdio { + compatible = "atmel,sam-mdio"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; pinctrl: pinctrl@400e0e00 { diff --git a/dts/arm/atmel/same5x.dtsi b/dts/arm/atmel/same5x.dtsi index a7447d8abb98f..fa5dd832e7e6e 100644 --- a/dts/arm/atmel/same5x.dtsi +++ b/dts/arm/atmel/same5x.dtsi @@ -10,24 +10,27 @@ / { soc { - gmac: ethernet@42000800 { - compatible = "atmel,sam0-gmac"; + ethernet@42000800 { + compatible = "microchip,sam-ethernet-controller"; reg = <0x42000800 0x400>; - interrupts = <84 0>; - interrupt-names = "gmac"; - status = "disabled"; - num-queues = <1>; - local-mac-address = [00 00 00 00 00 00]; - }; + gmac: ethernet { + compatible = "atmel,sam0-gmac"; + interrupts = <84 0>; + interrupt-names = "gmac"; + status = "disabled"; - mdio: mdio@42000800 { - compatible = "atmel,sam-mdio"; - reg = <0x42000800 0x400>; - status = "disabled"; + num-queues = <1>; + local-mac-address = [00 00 00 00 00 00]; + }; + + mdio: mdio { + compatible = "atmel,sam-mdio"; + status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; }; can0: can@42000000 { diff --git a/dts/arm/atmel/samx7x.dtsi b/dts/arm/atmel/samx7x.dtsi index d38cd93d4b4fb..170bded975e9a 100644 --- a/dts/arm/atmel/samx7x.dtsi +++ b/dts/arm/atmel/samx7x.dtsi @@ -232,24 +232,26 @@ #io-channel-cells = <1>; }; - gmac: ethernet@40050000 { - compatible = "atmel,sam-gmac"; + ethernet@40050000 { + compatible = "microchip,sam-ethernet-controller"; reg = <0x40050000 0x4000>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - interrupts = <39 0>, <66 0>, <67 0>; - interrupt-names = "gmac", "q1", "q2"; - num-queues = <3>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - }; - mdio: mdio@40050000 { - compatible = "atmel,sam-mdio"; - reg = <0x40050000 0x4000>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; + gmac: ethernet { + compatible = "atmel,sam-gmac"; + interrupts = <39 0>, <66 0>, <67 0>; + interrupt-names = "gmac", "q1", "q2"; + num-queues = <3>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + + mdio: mdio { + compatible = "atmel,sam-mdio"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; tc3: tc@40054000 { diff --git a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi index 2eb32dcfd5689..45b40fb7a8716 100644 --- a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi +++ b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi @@ -7,7 +7,7 @@ #include -#define BOOTSTRAP_SIZE DT_SIZE_K(12) +#define BOOTSTRAP_SIZE DT_SIZE_K(16) #define SRAM0_SIZE (DT_SIZE_K(256) - BOOTSTRAP_SIZE) / { @@ -215,141 +215,196 @@ status = "disabled"; }; - counter0_0: counter@404a0000 { - compatible = "infineon,cat1-counter"; - reg = <0x404a0000 0x80>; - interrupts = <42 4>; - resolution = <32>; - status = "disabled"; - }; - counter0_1: counter@404a0080 { - compatible = "infineon,cat1-counter"; - reg = <0x404a0080 0x80>; - interrupts = <43 4>; - resolution = <32>; - status = "disabled"; - }; - counter1_0: counter@404a8000 { - compatible = "infineon,cat1-counter"; - reg = <0x404a8000 0x80>; - interrupts = <44 4>; - resolution = <16>; - status = "disabled"; - }; - counter1_1: counter@404a8080 { - compatible = "infineon,cat1-counter"; - reg = <0x404a8080 0x80>; - interrupts = <45 4>; - resolution = <16>; - status = "disabled"; - }; - counter1_2: counter@404a8100 { - compatible = "infineon,cat1-counter"; - reg = <0x404a8100 0x80>; - interrupts = <46 4>; - resolution = <16>; - status = "disabled"; - }; - counter1_3: counter@404a8180 { - compatible = "infineon,cat1-counter"; - reg = <0x404a8180 0x80>; - interrupts = <47 4>; - resolution = <16>; - status = "disabled"; - }; - counter1_4: counter@404a8200 { - compatible = "infineon,cat1-counter"; - reg = <0x404a8200 0x80>; - interrupts = <48 4>; - resolution = <16>; - status = "disabled"; - }; - counter1_5: counter@404a8280 { - compatible = "infineon,cat1-counter"; - reg = <0x404a8280 0x80>; - interrupts = <49 4>; - resolution = <16>; - status = "disabled"; - }; - counter1_6: counter@404a8300 { - compatible = "infineon,cat1-counter"; - reg = <0x404a8300 0x80>; - interrupts = <50 4>; - resolution = <16>; - status = "disabled"; - }; + tcpwm0: tcpwm0@404a0000 { + reg = <0x404a0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; - pwm0_0: pwm@404a0000 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a0000 0x80>; - interrupts = <42 4>; - resolution = <32>; - status = "disabled"; - #pwm-cells = <3>; - }; - pwm0_1: pwm@404a0080 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a0080 0x80>; - interrupts = <43 4>; - resolution = <32>; - status = "disabled"; - #pwm-cells = <3>; - }; - pwm1_0: pwm@404a8000 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a8000 0x80>; - interrupts = <44 4>; - resolution = <16>; - status = "disabled"; - #pwm-cells = <3>; - }; - pwm1_1: pwm@404a8080 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a8080 0x80>; - interrupts = <45 4>; - resolution = <16>; - status = "disabled"; - #pwm-cells = <3>; - }; - pwm1_2: pwm@404a8100 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a8100 0x80>; - interrupts = <46 4>; - resolution = <16>; - status = "disabled"; - #pwm-cells = <3>; - }; - pwm1_3: pwm@404a8180 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a8180 0x80>; - interrupts = <47 4>; - resolution = <16>; - status = "disabled"; - #pwm-cells = <3>; - }; - pwm1_4: pwm@404a8200 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a8200 0x80>; - interrupts = <48 4>; - resolution = <16>; - status = "disabled"; - #pwm-cells = <3>; - }; - pwm1_5: pwm@404a8280 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a8280 0x80>; - interrupts = <49 4>; - resolution = <16>; - status = "disabled"; - #pwm-cells = <3>; + tcpwm0_0: tcpwm0_0@404a0000 { + compatible = "infineon,tcpwm"; + reg = <0x404a0000 0x80>; + interrupts = <42 4>; + resolution = <32>; + status = "disabled"; + + pwm0_0: pwm0_0 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_0: counter0_0 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; + + tcpwm0_1: tcpwm0_1@404a0080 { + compatible = "infineon,tcpwm"; + reg = <0x404a0080 0x80>; + interrupts = <43 4>; + resolution = <32>; + status = "disabled"; + + pwm0_1: pwm0_1 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter0_1: counter0_1 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; }; - pwm1_6: pwm@404a8300 { - compatible = "infineon,cat1-pwm"; - reg = <0x404a8300 0x80>; - interrupts = <50 4>; - resolution = <16>; - status = "disabled"; - #pwm-cells = <3>; + + tcpwm1: tcpwm1@404a8000 { + reg = <0x404a8000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + tcpwm1_0: tcpwm1_0@404a8000 { + compatible = "infineon,tcpwm"; + reg = <0x404a8000 0x80>; + interrupts = <44 4>; + resolution = <16>; + status = "disabled"; + + pwm1_0: pwm1_0 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_0: counter1_0 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; + + tcpwm1_1: tcpwm1_1@404a8080 { + compatible = "infineon,tcpwm"; + reg = <0x404a8080 0x80>; + interrupts = <45 4>; + resolution = <16>; + status = "disabled"; + + pwm1_1: pwm1_1 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_1: counter1_1 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; + + tcpwm1_2: tcpwm1_2@404a8100 { + compatible = "infineon,tcpwm"; + reg = <0x404a8100 0x80>; + interrupts = <46 4>; + resolution = <16>; + status = "disabled"; + + pwm1_2: pwm1_2 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_2: counter1_2 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; + + tcpwm1_3: tcpwm1_3@404a8180 { + compatible = "infineon,tcpwm"; + reg = <0x404a8180 0x80>; + interrupts = <47 4>; + resolution = <16>; + status = "disabled"; + + pwm1_3: pwm1_3 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_3: counter1_3 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; + + tcpwm1_4: tcpwm1_4@404a8200 { + compatible = "infineon,tcpwm"; + reg = <0x404a8200 0x80>; + interrupts = <48 4>; + resolution = <16>; + status = "disabled"; + + pwm1_4: pwm1_4 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_4: counter1_4 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; + + tcpwm1_5: tcpwm1_5@404a8280 { + compatible = "infineon,tcpwm"; + reg = <0x404a8280 0x80>; + interrupts = <49 4>; + resolution = <16>; + status = "disabled"; + + pwm1_5: pwm1_5 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_5: counter1_5 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; + + tcpwm1_6: tcpwm1_6@404a8300 { + compatible = "infineon,tcpwm"; + reg = <0x404a8300 0x80>; + interrupts = <50 4>; + resolution = <16>; + status = "disabled"; + + pwm1_6: pwm1_6 { + compatible = "infineon,tcpwm-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + counter1_6: counter1_6 { + compatible = "infineon,tcpwm-counter"; + status = "disabled"; + }; + + }; }; dma0: dw@40180000 { diff --git a/dts/arm/nuvoton/m5531h2l.dtsi b/dts/arm/nuvoton/m5531h2l.dtsi new file mode 100644 index 0000000000000..a7148b25cdfcf --- /dev/null +++ b/dts/arm/nuvoton/m5531h2l.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20100000 { + compatible = "mmio-sram"; + reg = <0x20100000 DT_SIZE_K(1344)>; + }; + + dtcm: memory@20000000 { + compatible = "zephyr,memory-region", "arm,dtcm"; + reg = <0x20000000 DT_SIZE_K(128)>; + zephyr,memory-region = "DTCM"; + }; + + itcm: memory@0 { + compatible = "zephyr,memory-region", "arm,itcm"; + reg = <0x00000000 DT_SIZE_K(64)>; + zephyr,memory-region = "ITCM"; + }; + + soc { + fmc: flash-controller@40044000 { + flash0: flash@100000 { + reg = <0x100000 DT_SIZE_K(2048)>; + }; + }; + }; +}; diff --git a/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi index 9b3cf781d71d8..612ca24187d09 100644 --- a/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi @@ -13,12 +13,12 @@ group_b0: group-b0-map { irq = <31>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x02>; }; group_c0: group-c0-map { irq = <15>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x04>; }; }; @@ -29,42 +29,42 @@ group_a1: group-a1-map { irq = <47>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x01>; }; group_b1: group-b1-map { irq = <48>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x02>; }; group_c1: group-c1-map { irq = <49>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x04>; }; group_d1: group-d1-map { irq = <50>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x08>; }; group_e1: group-e1-map { irq = <51>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x10>; }; group_f1: group-f1-map { irq = <52>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x20>; }; group_g1: group-g1-map { irq = <53>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x40>; }; group_h1: group-h1-map { irq = <54>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x80>; }; }; @@ -75,22 +75,22 @@ group_a2: group-a2-map { irq = <60>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x01>; }; group_b2: group-b2-map { irq = <61>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x02>; }; group_c2: group-c2-map { irq = <62>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x04>; }; group_d2: group-d2-map { irq = <63>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x08>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx.dtsi b/dts/arm/nuvoton/npcx/npcx.dtsi index aaaca78d02675..e1257092843ff 100644 --- a/dts/arm/nuvoton/npcx/npcx.dtsi +++ b/dts/arm/nuvoton/npcx/npcx.dtsi @@ -325,7 +325,7 @@ compatible = "nuvoton,npcx-adc"; #io-channel-cells = <1>; reg = <0x400d1000 0x2000>; - interrupts = <10 3>; + interrupts = <10 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; vref-mv = <2816>; status = "disabled"; @@ -340,7 +340,7 @@ espi0: espi@4000a000 { compatible = "nuvoton,npcx-espi"; reg = <0x4000a000 0x2000>; - interrupts = <18 3>; /* Interrupt for eSPI Bus */ + interrupts = <18 4>; /* Interrupt for eSPI Bus */ /* clocks for eSPI modules */ clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; @@ -366,11 +366,11 @@ "pm_hcmd"; /* host sub-module IRQ and priority */ - interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ - <56 3>, /* KBC Output-Buf-Empty (OBE) */ - <26 3>, /* PMCH Input-Buf-Full (IBF) */ - <3 3>, /* PMCH Output-Buf-Empty (OBE) */ - <6 3>; /* Port80 FIFO Not Empty */ + interrupts = <25 4>, /* KBC Input-Buf-Full (IBF) */ + <56 4>, /* KBC Output-Buf-Empty (OBE) */ + <26 4>, /* PMCH Input-Buf-Full (IBF) */ + <3 4>, /* PMCH Output-Buf-Empty (OBE) */ + <6 4>; /* Port80 FIFO Not Empty */ interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", "pmch_obe", "p80_fifo"; @@ -402,7 +402,7 @@ ps2_ctrl0: ps2@400b1000 { compatible = "nuvoton,npcx-ps2-ctrl"; reg = <0x400b1000 0x1000>; - interrupts = <21 4>; + interrupts = <21 5>; clocks = <&pcc NPCX_CLOCK_BUS_FREERUN NPCX_PWDWN_CTL1 3>; /* PS2 Channels - Please use them as PS2 node */ @@ -444,7 +444,7 @@ reg = <0x400d4000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <4 4>; + interrupts = <4 5>; clocks = <&pcc NPCX_CLOCK_BUS_FMCLK NPCX_PWDWN_CTL4 5>; status = "disabled"; }; @@ -452,7 +452,7 @@ kbd: kbd@400a3000 { compatible = "nuvoton,npcx-kbd"; reg = <0x400a3000 0x2000>; - interrupts = <49 4>; + interrupts = <49 5>; clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>; wui-maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26 &wui_io25 &wui_io24 &wui_io23 &wui_io22>; @@ -464,7 +464,7 @@ reg = <0x400d2000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <57 3>; + interrupts = <57 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL4 7>; status = "disabled"; diff --git a/dts/arm/nuvoton/npcx/npcx4.dtsi b/dts/arm/nuvoton/npcx/npcx4.dtsi index 52fef6bbd6ed6..5928cece0a3b2 100644 --- a/dts/arm/nuvoton/npcx/npcx4.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4.dtsi @@ -99,7 +99,7 @@ reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; - interrupts = <28 1>; /* Event timer interrupt */ + interrupts = <28 2>; /* Event timer interrupt */ clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ }; @@ -107,7 +107,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART1 register, Index 1: MDMA1 register */ reg = <0x400E0000 0x2000 0x40011100 0x100>; - interrupts = <33 3>; + interrupts = <33 4>; /* Index 0: UART1 clock, Index 1: MDMA1 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>; @@ -119,7 +119,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART2 register, Index 1: MDMA2 register */ reg = <0x400E2000 0x2000 0x40011200 0x100>; - interrupts = <32 3>; + interrupts = <32 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>; uart-rx = <&wui_cr_sin2>; status = "disabled"; @@ -129,7 +129,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART3 register, Index 1: MDMA3 register */ reg = <0x400E4000 0x2000 0x40011300 0x100>; - interrupts = <38 3>; + interrupts = <38 4>; /* Index 0: UART3 clock, Index 1: MDMA3 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>; @@ -141,7 +141,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART4 register, Index 1: MDMA4 register */ reg = <0x400E6000 0x2000 0x40011400 0x100>; - interrupts = <39 3>; + interrupts = <39 4>; /* Index 0: UART4 clock, Index 1: MDMA4 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>; @@ -301,7 +301,7 @@ i2c_ctrl0: i2c@40009000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40009000 0x1000>; - interrupts = <13 3>; + interrupts = <13 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; smb-wui = <&wui_smb0>; status = "disabled"; @@ -310,7 +310,7 @@ i2c_ctrl1: i2c@4000b000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x4000b000 0x1000>; - interrupts = <14 3>; + interrupts = <14 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; smb-wui = <&wui_smb1>; status = "disabled"; @@ -319,7 +319,7 @@ i2c_ctrl2: i2c@400c0000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x400c0000 0x1000>; - interrupts = <36 3>; + interrupts = <36 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; smb-wui = <&wui_smb2>; status = "disabled"; @@ -328,7 +328,7 @@ i2c_ctrl3: i2c@400c2000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x400c2000 0x1000>; - interrupts = <37 3>; + interrupts = <37 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; smb-wui = <&wui_smb3>; status = "disabled"; @@ -337,7 +337,7 @@ i2c_ctrl4: i2c@40008000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40008000 0x1000>; - interrupts = <19 3>; + interrupts = <19 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; smb-wui = <&wui_smb4>; status = "disabled"; @@ -346,7 +346,7 @@ i2c_ctrl5: i2c@40017000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40017000 0x1000>; - interrupts = <20 3>; + interrupts = <20 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; smb-wui = <&wui_smb5>; status = "disabled"; @@ -355,7 +355,7 @@ i2c_ctrl6: i2c@40018000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40018000 0x1000>; - interrupts = <16 3>; + interrupts = <16 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; smb-wui = <&wui_smb6>; status = "disabled"; @@ -364,7 +364,7 @@ i2c_ctrl7: i2c@40019000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40019000 0x1000>; - interrupts = <8 3>; + interrupts = <8 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; smb-wui = <&wui_smb7>; status = "disabled"; @@ -381,7 +381,7 @@ compatible = "nuvoton,npcx-adc"; #io-channel-cells = <1>; reg = <0x400d5000 0x2000>; - interrupts = <22 3>; + interrupts = <22 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 3>; vref-mv = <3300>; channel-count = <26>; @@ -447,7 +447,7 @@ reg = <0x400f0000 0x2000>, <0x40011500 0x100>; - interrupts = <29 3>; + interrupts = <29 4>; /* Reset controller */ resets = <&rctl NPCX_RESET_I3C_1>; @@ -473,7 +473,7 @@ reg = <0x400f2000 0x2000>, <0x40011600 0x100>; - interrupts = <66 3>; + interrupts = <66 4>; /* Reset controller */ resets = <&rctl NPCX_RESET_I3C_2>; @@ -499,7 +499,7 @@ reg = <0x400f4000 0x2000>, <0x40011700 0x100>; - interrupts = <67 3>; + interrupts = <67 4>; /* Reset controller */ resets = <&rctl NPCX_RESET_I3C_3>; diff --git a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi index d8c228b424866..5194dab718547 100644 --- a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi @@ -17,32 +17,32 @@ group_a0: group-a0-map { irq = <7>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x01>; }; group_d0: group-d0-map { irq = <5>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x08>; }; group_e0: group-e0-map { irq = <11>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x10>; }; group_f0: group-f0-map { irq = <35>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x20>; }; group_g0: group-g0-map { irq = <42>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x40>; }; group_h0: group-h0-map { irq = <46>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x80>; }; }; @@ -53,22 +53,22 @@ group_e2: group-e2-map { irq = <64>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x10>; }; group_f2: group-f2-map { irq = <59>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x20>; }; group_g2: group-g2-map { irq = <55>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x40>; }; group_h2: group-h2-map { irq = <82>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x80>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx7.dtsi b/dts/arm/nuvoton/npcx/npcx7.dtsi index b163f14940046..479c322894965 100644 --- a/dts/arm/nuvoton/npcx/npcx7.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7.dtsi @@ -96,14 +96,14 @@ reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 3 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; - interrupts = <46 1>; /* Event timer interrupt */ + interrupts = <46 2>; /* Event timer interrupt */ clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ }; uart1: serial@400c4000 { compatible = "nuvoton,npcx-uart"; reg = <0x400C4000 0x2000>; - interrupts = <33 3>; + interrupts = <33 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>; uart-rx = <&wui_cr_sin1>; status = "disabled"; @@ -112,7 +112,7 @@ uart2: serial@400c6000 { compatible = "nuvoton,npcx-uart"; reg = <0x400C6000 0x2000>; - interrupts = <32 3>; + interrupts = <32 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 6>; uart-rx = <&wui_cr_sin2>; status = "disabled"; @@ -268,7 +268,7 @@ i2c_ctrl0: i2c@40009000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40009000 0x1000>; - interrupts = <13 3>; + interrupts = <13 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; smb-wui = <&wui_smb0_2>; status = "disabled"; @@ -277,7 +277,7 @@ i2c_ctrl1: i2c@4000b000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x4000b000 0x1000>; - interrupts = <14 3>; + interrupts = <14 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; smb-wui = <&wui_smb1_3>; status = "disabled"; @@ -286,7 +286,7 @@ i2c_ctrl2: i2c@400c0000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x400c0000 0x1000>; - interrupts = <36 3>; + interrupts = <36 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; smb-wui = <&wui_smb0_2>; status = "disabled"; @@ -295,7 +295,7 @@ i2c_ctrl3: i2c@400c2000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x400c2000 0x1000>; - interrupts = <37 3>; + interrupts = <37 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; smb-wui = <&wui_smb1_3>; status = "disabled"; @@ -304,7 +304,7 @@ i2c_ctrl4: i2c@40008000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40008000 0x1000>; - interrupts = <19 3>; + interrupts = <19 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; smb-wui = <&wui_smb4>; status = "disabled"; @@ -313,7 +313,7 @@ i2c_ctrl5: i2c@40017000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40017000 0x1000>; - interrupts = <20 3>; + interrupts = <20 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; smb-wui = <&wui_smb5>; status = "disabled"; @@ -322,7 +322,7 @@ i2c_ctrl6: i2c@40018000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40018000 0x1000>; - interrupts = <16 3>; + interrupts = <16 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; smb-wui = <&wui_smb6>; status = "disabled"; @@ -331,7 +331,7 @@ i2c_ctrl7: i2c@40019000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40019000 0x1000>; - interrupts = <8 3>; + interrupts = <8 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; smb-wui = <&wui_smb7>; status = "disabled"; diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi index fbf1f13694e38..3eea0f14a01dc 100644 --- a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi @@ -17,12 +17,12 @@ group_ad0: group-ad0-map { irq = <7>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x09>; }; group_efgh0: group-efgh0-map { irq = <11>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0xF0>; }; }; @@ -33,7 +33,7 @@ group_fg2: group-fg2-map { irq = <59>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x60>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx9.dtsi b/dts/arm/nuvoton/npcx/npcx9.dtsi index 78161fe58e0a8..f6e349db8109d 100644 --- a/dts/arm/nuvoton/npcx/npcx9.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9.dtsi @@ -97,7 +97,7 @@ reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; - interrupts = <28 1>; /* Event timer interrupt */ + interrupts = <28 2>; /* Event timer interrupt */ clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ }; @@ -105,7 +105,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART1 register, Index 1: MDMA1 register */ reg = <0x400E0000 0x2000 0x40011100 0x100>; - interrupts = <33 3>; + interrupts = <33 4>; /* Index 0: UART1 clock, Index 1: MDMA1 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>; @@ -117,7 +117,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART2 register, Index 1: MDMA2 register */ reg = <0x400E2000 0x2000 0x40011200 0x100>; - interrupts = <32 3>; + interrupts = <32 4>; /* Index 0: UART2 clock, Index 1: MDMA2 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 1>; @@ -129,7 +129,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART3 register, Index 1: MDMA3 register */ reg = <0x400E4000 0x2000 0x40011300 0x100>; - interrupts = <38 3>; + interrupts = <38 4>; /* Index 0: UART3 clock, Index 1: MDMA3 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>; @@ -141,7 +141,7 @@ compatible = "nuvoton,npcx-uart"; /* Index 0: UART4 register, Index 1: MDMA4 register */ reg = <0x400E6000 0x2000 0x40011400 0x100>; - interrupts = <39 3>; + interrupts = <39 4>; /* Index 0: UART4 clock, Index 1: MDMA4 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>; @@ -301,7 +301,7 @@ i2c_ctrl0: i2c@40009000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40009000 0x1000>; - interrupts = <13 3>; + interrupts = <13 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; smb-wui = <&wui_smb0_2>; status = "disabled"; @@ -310,7 +310,7 @@ i2c_ctrl1: i2c@4000b000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x4000b000 0x1000>; - interrupts = <14 3>; + interrupts = <14 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; smb-wui = <&wui_smb1_3>; status = "disabled"; @@ -319,7 +319,7 @@ i2c_ctrl2: i2c@400c0000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x400c0000 0x1000>; - interrupts = <36 3>; + interrupts = <36 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; smb-wui = <&wui_smb0_2>; status = "disabled"; @@ -328,7 +328,7 @@ i2c_ctrl3: i2c@400c2000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x400c2000 0x1000>; - interrupts = <37 3>; + interrupts = <37 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; smb-wui = <&wui_smb1_3>; status = "disabled"; @@ -337,7 +337,7 @@ i2c_ctrl4: i2c@40008000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40008000 0x1000>; - interrupts = <19 3>; + interrupts = <19 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; smb-wui = <&wui_smb4>; status = "disabled"; @@ -346,7 +346,7 @@ i2c_ctrl5: i2c@40017000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40017000 0x1000>; - interrupts = <20 3>; + interrupts = <20 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; smb-wui = <&wui_smb5>; status = "disabled"; @@ -355,7 +355,7 @@ i2c_ctrl6: i2c@40018000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40018000 0x1000>; - interrupts = <16 3>; + interrupts = <16 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; smb-wui = <&wui_smb6>; status = "disabled"; @@ -364,7 +364,7 @@ i2c_ctrl7: i2c@40019000 { compatible = "nuvoton,npcx-i2c-ctrl"; reg = <0x40019000 0x1000>; - interrupts = <8 3>; + interrupts = <8 4>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; smb-wui = <&wui_smb7>; status = "disabled"; diff --git a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi index 5beae74fc6c60..5a49b484048a9 100644 --- a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi @@ -17,32 +17,32 @@ group_a0: group-a0-map { irq = <7>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x01>; }; group_d0: group-d0-map { irq = <5>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x08>; }; group_e0: group-e0-map { irq = <11>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x10>; }; group_f0: group-f0-map { irq = <35>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x20>; }; group_g0: group-g0-map { irq = <42>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x40>; }; group_h0: group-h0-map { irq = <46>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x80>; }; }; @@ -53,12 +53,12 @@ group_f2: group-f2-map { irq = <59>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x20>; }; group_g2: group-g2-map { irq = <55>; - irq-prio = <2>; + irq-prio = <3>; group-mask = <0x40>; }; }; diff --git a/dts/arm/nxp/nxp_imx943_m33.dtsi b/dts/arm/nxp/nxp_imx943_m33.dtsi index 0990def30befd..46d4e05e4ad08 100644 --- a/dts/arm/nxp/nxp_imx943_m33.dtsi +++ b/dts/arm/nxp/nxp_imx943_m33.dtsi @@ -466,8 +466,11 @@ status = "disabled"; }; - netc_switch: switch { + netc_switch: switch@4cc00000 { compatible = "nxp,netc-switch"; + reg = <0x4cc00000 0x40000>, + <0x4ca02000 0x1000>; + reg-names = "base", "pfconfig"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/arm/nxp/nxp_mcxa153.dtsi b/dts/arm/nxp/nxp_mcxa153.dtsi index e9a120041a6ca..53d78c1471258 100644 --- a/dts/arm/nxp/nxp_mcxa153.dtsi +++ b/dts/arm/nxp/nxp_mcxa153.dtsi @@ -29,6 +29,10 @@ status = "okay"; }; + cmc { + compatible = "nxp,cmc-reset-cause"; + }; + soc { ctimer0: ctimer@40004000 { compatible = "nxp,lpc-ctimer"; diff --git a/dts/arm/nxp/nxp_mcxa156.dtsi b/dts/arm/nxp/nxp_mcxa156.dtsi index e8b1d54ea8179..f6f7d0b3ba5b0 100644 --- a/dts/arm/nxp/nxp_mcxa156.dtsi +++ b/dts/arm/nxp/nxp_mcxa156.dtsi @@ -29,6 +29,10 @@ status = "okay"; }; + cmc { + compatible = "nxp,cmc-reset-cause"; + }; + soc { syscon: syscon@40000000 { compatible = "nxp,lpc-syscon"; diff --git a/dts/arm/nxp/nxp_mcxa266.dtsi b/dts/arm/nxp/nxp_mcxa266.dtsi index c805bb361a2bc..2f8dedc6971cf 100644 --- a/dts/arm/nxp/nxp_mcxa266.dtsi +++ b/dts/arm/nxp/nxp_mcxa266.dtsi @@ -23,6 +23,10 @@ }; }; + cmc { + compatible = "nxp,cmc-reset-cause"; + }; + /* Dummy pinctrl node, filled with pin mux options at board level */ pinctrl: pinctrl { compatible = "nxp,port-pinctrl"; diff --git a/dts/arm/nxp/nxp_mcxa346.dtsi b/dts/arm/nxp/nxp_mcxa346.dtsi index 48f77c975dcad..41872646e7478 100644 --- a/dts/arm/nxp/nxp_mcxa346.dtsi +++ b/dts/arm/nxp/nxp_mcxa346.dtsi @@ -29,6 +29,10 @@ status = "okay"; }; + cmc { + compatible = "nxp,cmc-reset-cause"; + }; + soc { syscon: syscon@40091000 { compatible = "nxp,lpc-syscon"; diff --git a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi index 9b112504dd3a1..ee622e8013e1a 100644 --- a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi @@ -34,6 +34,10 @@ }; }; + cmc { + compatible = "nxp,cmc-reset-cause"; + }; + /* Dummy pinctrl node, filled with pin mux options at board level */ pinctrl: pinctrl { compatible = "nxp,port-pinctrl"; diff --git a/dts/arm/nxp/nxp_rt118x.dtsi b/dts/arm/nxp/nxp_rt118x.dtsi index 62b296d666b19..f0b2a5aa54c26 100644 --- a/dts/arm/nxp/nxp_rt118x.dtsi +++ b/dts/arm/nxp/nxp_rt118x.dtsi @@ -67,7 +67,7 @@ * or nxp_rt118x_cm7.dtsi. The base addresses on cm33 core differ * between non-secure (0x40000000) and secure modes (0x50000000). */ - iomuxc: iomuxc@2A10000 { + iomuxc: pinctrl@2A10000 { compatible = "nxp,imx-iomuxc"; reg = <0x2A10000 0x4000>; pinctrl: pinctrl { @@ -76,13 +76,13 @@ }; }; - iomuxc_aon: iomuxc@43C0000 { + iomuxc_aon: pinctrl@43C0000 { compatible = "nxp,mcux-rt-pinctrl"; reg = <0x43C0000 0x4000>; status = "okay"; }; - ccm: ccm@4450000 { + ccm: clock-controller@4450000 { compatible = "nxp,imx-ccm-rev2"; reg = <0x4450000 0x4000>; #clock-cells = <3>; @@ -94,7 +94,7 @@ }; }; - lpuart1: uart@4380000 { + lpuart1: serial@4380000 { compatible = "nxp,lpuart"; reg = <0x4380000 0x4000>; interrupts = <19 0>; @@ -104,7 +104,7 @@ status = "disabled"; }; - lpuart2: uart@4390000 { + lpuart2: serial@4390000 { compatible = "nxp,lpuart"; reg = <0x4390000 0x4000>; interrupts = <20 0>; @@ -114,7 +114,7 @@ status = "disabled"; }; - lpuart3: uart@2570000 { + lpuart3: serial@2570000 { compatible = "nxp,lpuart"; reg = <0x2570000 0x4000>; interrupts = <68 0>; @@ -124,7 +124,7 @@ status = "disabled"; }; - lpuart4: uart@2580000 { + lpuart4: serial@2580000 { compatible = "nxp,lpuart"; reg = <0x2580000 0x4000>; interrupts = <69 0>; @@ -144,7 +144,7 @@ status = "disabled"; }; - lpuart6: uart@25A0000 { + lpuart6: serial@25A0000 { compatible = "nxp,lpuart"; reg = <0x25A0000 0x4000>; interrupts = <71 0>; @@ -154,7 +154,7 @@ status = "disabled"; }; - lpuart7: uart@4570000 { + lpuart7: serial@4570000 { compatible = "nxp,lpuart"; reg = <0x4570000 0x4000>; interrupts = <196 0>; @@ -164,7 +164,7 @@ status = "disabled"; }; - lpuart8: uart@2DA0000 { + lpuart8: serial@2DA0000 { compatible = "nxp,lpuart"; reg = <0x2DA0000 0x4000>; interrupts = <197 0>; @@ -174,7 +174,7 @@ status = "disabled"; }; - lpuart9: uart@2D70000 { + lpuart9: serial@2D70000 { compatible = "nxp,lpuart"; reg = <0x2D70000 0x4000>; interrupts = <156 0>; @@ -184,7 +184,7 @@ status = "disabled"; }; - lpuart10: uart@2D80000 { + lpuart10: serial@2D80000 { compatible = "nxp,lpuart"; reg = <0x2D80000 0x4000>; interrupts = <157 0>; @@ -194,7 +194,7 @@ status = "disabled"; }; - lpuart11: uart@2D90000 { + lpuart11: serial@2D90000 { compatible = "nxp,lpuart"; reg = <0x2D90000 0x4000>; interrupts = <158 0>; @@ -204,7 +204,7 @@ status = "disabled"; }; - lpuart12: uart@4580000 { + lpuart12: serial@4580000 { compatible = "nxp,lpuart"; reg = <0x4580000 0x4000>; interrupts = <159 0>; @@ -328,7 +328,7 @@ status = "disabled"; }; - gpt1: gpt@46c0000 { + gpt1: timer@46c0000 { compatible = "nxp,imx-gpt"; reg = <0x46c0000 0x4000>; interrupts = <209 0>; @@ -337,7 +337,7 @@ status = "disabled"; }; - gpt2: gpt@2ec0000 { + gpt2: timer@2ec0000 { compatible = "nxp,imx-gpt"; reg = <0x2ec0000 0x4000>; interrupts = <210 0>; @@ -345,28 +345,28 @@ clocks = <&ccm IMX_CCM_GPT2_CLK 0x41 0>; }; - acmp1: cmp@2dc0000 { + acmp1: comparator@2dc0000 { compatible = "nxp,kinetis-acmp"; reg = <0x2dc0000 0x4000>; interrupts = <200 0>; status = "disabled"; }; - acmp2: cmp@2dd0000 { + acmp2: comparator@2dd0000 { compatible = "nxp,kinetis-acmp"; reg = <0x2dd0000 0x4000>; interrupts = <201 0>; status = "disabled"; }; - acmp3: cmp@2de0000 { + acmp3: comparator@2de0000 { compatible = "nxp,kinetis-acmp"; reg = <0x2de0000 0x4000>; interrupts = <202 0>; status = "disabled"; }; - acmp4: cmp@2df0000 { + acmp4: comparator@2df0000 { compatible = "nxp,kinetis-acmp"; reg = <0x2df0000 0x4000>; interrupts = <203 0>; @@ -412,7 +412,7 @@ #io-channel-cells = <1>; }; - qtmr1: qtmr@2690000 { + qtmr1: timer@2690000 { compatible = "nxp,imx-qtmr"; reg = <0x2690000 0x4000>; interrupts = <0 0>; @@ -439,7 +439,7 @@ }; }; - qtmr2: qtmr@26a0000 { + qtmr2: timer@26a0000 { compatible = "nxp,imx-qtmr"; reg = <0x26a0000 0x4000>; interrupts = <233 0>; @@ -466,7 +466,7 @@ }; }; - qtmr3: qtmr@26b0000 { + qtmr3: timer@26b0000 { compatible = "nxp,imx-qtmr"; reg = <0x26b0000 0x4000>; interrupts = <164 0>; @@ -493,7 +493,7 @@ }; }; - qtmr4: qtmr@26c0000 { + qtmr4: timer@26c0000 { compatible = "nxp,imx-qtmr"; reg = <0x26c0000 0x4000>; interrupts = <151 0>; @@ -520,7 +520,7 @@ }; }; - qtmr5: qtmr@26d0000 { + qtmr5: timer@26d0000 { compatible = "nxp,imx-qtmr"; reg = <0x26d0000 0x4000>; interrupts = <4 0>; @@ -547,7 +547,7 @@ }; }; - qtmr6: qtmr@26e0000 { + qtmr6: timer@26e0000 { compatible = "nxp,imx-qtmr"; reg = <0x26e0000 0x4000>; interrupts = <5 0>; @@ -574,7 +574,7 @@ }; }; - qtmr7: qtmr@26f0000 { + qtmr7: timer@26f0000 { compatible = "nxp,imx-qtmr"; reg = <0x26f0000 0x4000>; interrupts = <6 0>; @@ -601,7 +601,7 @@ }; }; - qtmr8: qtmr@2700000 { + qtmr8: timer@2700000 { compatible = "nxp,imx-qtmr"; reg = <0x2700000 0x4000>; interrupts = <7 0>; @@ -666,8 +666,11 @@ status = "disabled"; }; - switch: dsa { + switch: dsa@60a00000 { compatible = "nxp,netc-switch"; + reg = <0x60a00000 0x10000>, + <0x60002000 0x1000>; + reg-names = "base", "pfconfig"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -844,7 +847,7 @@ }; - lptmr1: lptmr@4300000 { + lptmr1: timer@4300000 { compatible = "nxp,lptmr"; reg = <0x4300000 0x1000>; interrupts = <18 0>; @@ -855,7 +858,7 @@ status = "disabled"; }; - lptmr2: lptmr@24d0000 { + lptmr2: timer@24d0000 { compatible = "nxp,lptmr"; reg = <0x24d0000 0x1000>; interrupts = <67 0>; @@ -866,7 +869,7 @@ status = "disabled"; }; - lptmr3: lptmr@2cd0000 { + lptmr3: timer@2cd0000 { compatible = "nxp,lptmr"; reg = <0x2cd0000 0x1000>; interrupts = <150 0>; @@ -893,7 +896,7 @@ status = "disabled"; }; - flexpwm1: flexpwm@2650000 { + flexpwm1: pwm@2650000 { compatible = "nxp,flexpwm"; reg = <0x2650000 0x4000>; interrupts = <23 0>; @@ -939,7 +942,7 @@ }; }; - flexpwm2: flexpwm@2660000 { + flexpwm2: pwm@2660000 { compatible = "nxp,flexpwm"; reg = <0x2660000 0x4000>; interrupts = <170 0>; @@ -985,7 +988,7 @@ }; }; - flexpwm3: flexpwm@2670000 { + flexpwm3: pwm@2670000 { compatible = "nxp,flexpwm"; reg = <0x2670000 0x4000>; interrupts = <175 0>; @@ -1031,7 +1034,7 @@ }; }; - flexpwm4: flexpwm@2680000 { + flexpwm4: pwm@2680000 { compatible = "nxp,flexpwm"; reg = <0x2680000 0x4000>; interrupts = <180 0>; @@ -1163,7 +1166,7 @@ #size-cells = <0>; }; - usdhc1: usdhc@2850000 { + usdhc1: memory-controller@2850000 { compatible = "nxp,imx-usdhc"; reg = <0x2850000 0x4000>; status = "disabled"; @@ -1175,7 +1178,7 @@ min-bus-freq = <400000>; }; - usdhc2: usdhc@2860000 { + usdhc2: memory-controller@2860000 { compatible = "nxp,imx-usdhc"; reg = <0x2860000 0x4000>; status = "disabled"; @@ -1253,6 +1256,16 @@ #size-cells = <0>; }; + kpp: kpp@2a00000 { + compatible = "nxp,mcux-kpp"; + reg = <0x2A00000 0x1000>; + interrupts = <211 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&ccm IMX_CCM_KPP_CLK 0x0 0>; + }; + lpspi2: spi@4370000 { compatible = "nxp,lpspi"; reg = <0x4370000 0x4000>; @@ -1323,7 +1336,7 @@ clk-divider = <1>; }; - rtwdog1: wdog@42e0000 { + rtwdog1: watchdog@42e0000 { compatible = "nxp,rtwdog"; reg = <0x42e0000 0x10>; status = "disabled"; @@ -1333,7 +1346,7 @@ clk-divider = <1>; }; - rtwdog2: wdog@2490000 { + rtwdog2: watchdog@2490000 { compatible = "nxp,rtwdog"; reg = <0x2490000 0x10>; status = "disabled"; @@ -1353,7 +1366,7 @@ clk-divider = <1>; }; - rtwdog4: wdog@24b0000 { + rtwdog4: watchdog@24b0000 { compatible = "nxp,rtwdog"; reg = <0x24b0000 0x10>; status = "disabled"; @@ -1373,7 +1386,7 @@ status = "disabled"; }; - usb2: usbd@2c90000 { + usb2: usb@2c90000 { compatible = "nxp,ehci"; reg = <0x2c90000 0x1000>; interrupts = <214 0>; @@ -1383,13 +1396,13 @@ status = "disabled"; }; - usbphy1: usbphy@2ca0000 { + usbphy1: usb-phy@2ca0000 { compatible = "nxp,usbphy"; reg = <0x2ca0000 0x1000>; status = "disabled"; }; - usbphy2: usbphy@2cb0000 { + usbphy2: usb-phy@2cb0000 { compatible = "nxp,usbphy"; reg = <0x2cb0000 0x1000>; status = "disabled"; @@ -1417,14 +1430,14 @@ &memory { #address-cells = <1>; #size-cells = <1>; - ocram1: ocram@0 { + ocram1: memory@0 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "OCRAM1"; /* OCRAM1 first 16K access is blocked by TRDC */ reg = <0x0 DT_SIZE_K(496)>; }; - ocram2: ocram@7c000 { + ocram2: memory@7c000 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "OCRAM2"; reg = <0x7c000 DT_SIZE_K(256)>; diff --git a/dts/arm/nxp/nxp_rt118x_cm33.dtsi b/dts/arm/nxp/nxp_rt118x_cm33.dtsi index b77431936d915..4739e3c08a645 100644 --- a/dts/arm/nxp/nxp_rt118x_cm33.dtsi +++ b/dts/arm/nxp/nxp_rt118x_cm33.dtsi @@ -10,13 +10,13 @@ / { soc { - itcm: itcm@1ffe0000 { + itcm: memory@1ffe0000 { compatible = "zephyr,memory-region", "nxp,imx-itcm"; reg = <0x1ffe0000 DT_SIZE_K(128)>; zephyr,memory-region = "ITCM"; }; - dtcm: dtcm@30000000 { + dtcm: memory@30000000 { compatible = "zephyr,memory-region", "nxp,imx-dtcm"; reg = <0x30000000 DT_SIZE_K(128)>; zephyr,memory-region = "DTCM"; @@ -26,7 +26,7 @@ ranges = <0x0 0x30484000 0x10000000>; }; - m7_itcm: itcm@303c0000 { + m7_itcm: memory@303c0000 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "M7_ITCM"; reg = <0x303c0000 DT_SIZE_K(256)>; @@ -36,11 +36,11 @@ ranges = <0x0 0x50000000 0x10000000>; }; - flexspi: spi@525e0000 { + flexspi: memory-controller@525e0000 { reg = <0x525e0000 0x4000>, <0x38000000 DT_SIZE_M(128)>; }; - flexspi2: spi@545e0000 { + flexspi2: memory-controller@545e0000 { reg = <0x545e0000 0x4000>, <0x14000000 DT_SIZE_M(64)>; }; }; diff --git a/dts/arm/nxp/nxp_rt118x_cm7.dtsi b/dts/arm/nxp/nxp_rt118x_cm7.dtsi index 1b9cde67f4ced..a50a6422a88bb 100644 --- a/dts/arm/nxp/nxp_rt118x_cm7.dtsi +++ b/dts/arm/nxp/nxp_rt118x_cm7.dtsi @@ -9,13 +9,13 @@ / { soc { - itcm: itcm@0{ + itcm: memory@0{ compatible = "zephyr,memory-region", "nxp,imx-itcm"; reg = <0x00000000 DT_SIZE_K(256)>; zephyr,memory-region = "ITCM"; }; - dtcm: dtcm@20000000 { + dtcm: memory@20000000 { compatible = "zephyr,memory-region", "nxp,imx-dtcm"; reg = <0x20000000 DT_SIZE_K(256)>; zephyr,memory-region = "DTCM"; @@ -29,11 +29,11 @@ ranges = <0x0 0x40000000 0x10000000>; }; - flexspi: spi@425e0000 { + flexspi: memory-controller@425e0000 { reg = <0x425e0000 0x4000>, <0x28000000 DT_SIZE_M(128)>; }; - flexspi2: spi@445e0000 { + flexspi2: memory-controller@445e0000 { reg = <0x445e0000 0x4000>, <0x04000000 DT_SIZE_M(64)>; }; }; diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index c855185c9ce0c..70278c757ce41 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -248,6 +248,15 @@ status = "disabled"; }; + usbh: usbh@145000 { + compatible = "nxp,uhc-ehci"; + reg = <0x145000 0x200>; + interrupts = <50 1>; + interrupt-names = "usb_otg"; + power-domains = <&power_mode3_domain>; + status = "disabled"; + }; + flexcomm0: flexcomm@106000 { compatible = "nxp,lpc-flexcomm"; reg = <0x106000 0x1000>; diff --git a/dts/arm/renesas/ra/ra2/ra2l1.dtsi b/dts/arm/renesas/ra/ra2/ra2l1.dtsi index ba8ae20da7c06..3a19b0062bd4a 100644 --- a/dts/arm/renesas/ra/ra2/ra2l1.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2l1.dtsi @@ -75,6 +75,13 @@ }; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclkb MSTPC 1>; + status = "disabled"; + }; + ioport0: gpio@40040000 { compatible = "renesas,ra-gpio-ioport"; reg = <0x40040000 0x20>; diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi index c23452e69d6c6..b1f3dcfb71b05 100644 --- a/dts/arm/renesas/ra/ra2/ra2xx.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi @@ -285,6 +285,13 @@ }; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclkb MSTPC 1>; + status = "disabled"; + }; + port_irq0: external-interrupt@40006000 { compatible = "renesas,ra-external-interrupt"; reg = <0x40006000 0x1>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi index f3049d859093c..0d445226fc404 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi @@ -306,6 +306,7 @@ port-irq5-pins = <1 10>; port-irq6-pins = <9>; port-irq7-pins = <8>; + vbatts-pins = <2>; }; &dac_global { diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index 3b4d0e4f335b8..d75e0df7a1c97 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -370,6 +370,7 @@ port-irq6-pins = <9>; port-irq7-pins = <8>; port-irq14-pins = <3>; + /delete-property/ vbatts-pins; }; &ioport8 { diff --git a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi index 8eaeda35f91c8..36c49bc313169 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi @@ -279,6 +279,13 @@ }; }; + crc: crc@40108000 { + compatible = "renesas,ra-crc"; + reg = <0x40108000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + iic0: iic0@4009f000 { compatible = "renesas,ra-iic"; channel = <0>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 14a8bd51faf57..5e33146b93dba 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -223,6 +223,7 @@ port-irq4-pins = <2>; port-irq6-pins = <9>; port-irq9-pins = <14>; + vbatts-pins = <2>; }; &ioport5 { diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi index 4558a384ea063..0e66b52989f30 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi @@ -102,6 +102,7 @@ gpio-controller; #gpio-cells = <2>; ngpios = <16>; + vbatts-pins = <2 3 4>; status = "disabled"; }; @@ -290,6 +291,13 @@ status = "disabled"; }; + crc: crc@40108000{ + compatible = "renesas,ra-crc"; + reg = <0x40108000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + dac_global: dac_global@40171000 { compatible = "renesas,ra-dac-global"; reg = <0x40171000 0x10c4>; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi index 7174188c4c5e5..949d892eb950a 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi @@ -98,6 +98,7 @@ gpio-controller; #gpio-cells = <2>; ngpios = <16>; + vbatts-pins = <2 3 4>; status = "disabled"; }; @@ -241,6 +242,13 @@ }; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + iic0: iic0@40053000 { compatible = "renesas,ra-iic"; channel = <0>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 97c0eea22d55d..36075bad02347 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -366,6 +366,7 @@ port-irq6-pins = <9>; port-irq7-pins = <8>; port-irq14-pins = <3>; + /delete-property/ vbatts-pins; }; &ioport8 { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index dbb0455c641db..54dc6489f973c 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -10,6 +10,7 @@ /delete-node/ ð /delete-node/ &mdio; +/delete-node/ &qspi0; / { soc { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index 5382c36e9fa79..a48cf6e9c4d99 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -11,6 +11,7 @@ /delete-node/ ð /delete-node/ &mdio; +/delete-node/ &qspi0; / { soc { diff --git a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi index 179c12d4cdfee..134b354b4520c 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi @@ -94,6 +94,7 @@ gpio-controller; #gpio-cells = <2>; ngpios = <16>; + vbatts-pins = <2 3 4>; status = "disabled"; }; @@ -287,6 +288,13 @@ status = "disabled"; }; + crc: crc@40108000{ + compatible = "renesas,ra-crc"; + reg = <0x40108000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + dac_global: dac_global@40171000 { compatible = "renesas,ra-dac-global"; reg = <0x40171000 0x10c4>; @@ -547,6 +555,14 @@ variant = "ctsua"; status = "disabled"; }; + + qspi0: qspi0@64000000 { + compatible = "renesas,ra-qspi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x64000000 0x808>; + status = "disabled"; + }; }; usbfs_phy: usbfs-phy { diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi index 4c4c74f33ab54..d9b966fa8ffd1 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi @@ -93,6 +93,7 @@ gpio-controller; #gpio-cells = <2>; ngpios = <16>; + vbatts-pins = <2 3 4>; status = "disabled"; }; @@ -306,6 +307,13 @@ status = "disabled"; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + dac_global: dac_global@4005e000 { compatible = "renesas,ra-dac-global"; reg = <0x4005e000 0x10c4>; @@ -656,6 +664,14 @@ variant = "ctsua"; status = "disabled"; }; + + qspi0: qspi0@64000000 { + compatible = "renesas,ra-qspi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x64000000 0x808>; + status = "disabled"; + }; }; usbfs_phy: usbfs-phy { diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi index 20d102e11fb02..02b0ec5f61abc 100644 --- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi @@ -676,6 +676,13 @@ }; }; + crc: crc@40310000 { + compatible = "renesas,ra-crc"; + reg = <0x40310000 0x100>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + eth: ethernet@40354100 { compatible = "renesas,ra-ethernet"; reg = <0x40354100 0xfc>; diff --git a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi index 0302d86c0e944..a121672ba370c 100644 --- a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi +++ b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -1060,5 +1061,50 @@ status = "disabled"; }; }; + + i2c0: i2c@80043000 { + compatible = "renesas,rz-iic"; + channel = <0>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80043000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + i2c1: i2c@80043400 { + compatible = "renesas,rz-iic"; + channel = <1>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80043400 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + i2c2: i2c@81008000 { + compatible = "renesas,rz-iic"; + channel = <2>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x81008000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + status = "disabled"; + }; }; }; diff --git a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi index 1cc1eea1ea033..da962a2ae89e0 100644 --- a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi +++ b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "renesas,r9a07g075"; @@ -1058,5 +1059,50 @@ status = "disabled"; }; }; + + i2c0: i2c@80043000 { + compatible = "renesas,rz-iic"; + channel = <0>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80043000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + i2c1: i2c@80043400 { + compatible = "renesas,rz-iic"; + channel = <1>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80043400 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + i2c2: i2c@81008000 { + compatible = "renesas,rz-iic"; + channel = <2>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x81008000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + status = "disabled"; + }; }; }; diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi index c779ff894fa97..4a45ed8d19891 100644 --- a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "renesas,r9a07g054"; @@ -775,6 +776,58 @@ status = "disabled"; }; }; + + i2c0: i2c@40058000 { + compatible = "renesas,rz-riic"; + channel = <0>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40058000 DT_SIZE_K(1)>; + interrupts = <348 1>, <349 1>, <350 1>, <351 1>, + <352 1>, <353 1>, <354 1>, <355 1>; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; + + i2c1: i2c@40058400 { + compatible = "renesas,rz-riic"; + channel = <1>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40058400 DT_SIZE_K(1)>; + interrupts = <356 1>, <357 1>, <358 1>, <359 1>, + <360 1>, <361 1>, <362 1>, <363 1>; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; + + i2c2: i2c@40058800 { + compatible = "renesas,rz-riic"; + channel = <2>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40058800 DT_SIZE_K(1)>; + interrupts = <364 1>, <365 1>, <366 1>, <367 1>, + <368 1>, <369 1>, <370 1>, <371 1>; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; + + i2c3: i2c@40058c00 { + compatible = "renesas,rz-riic"; + channel = <3>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40058c00 DT_SIZE_K(1)>; + interrupts = <372 1>, <373 1>, <374 1>, <375 1>, + <376 1>, <377 1>, <378 1>, <379 1>; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; }; }; diff --git a/dts/arm/silabs/xg21/xg21.dtsi b/dts/arm/silabs/xg21/xg21.dtsi index 8d5c44bd9c9bc..e0f74ed7b2b19 100644 --- a/dts/arm/silabs/xg21/xg21.dtsi +++ b/dts/arm/silabs/xg21/xg21.dtsi @@ -303,7 +303,7 @@ }; i2c0: i2c@5a010000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -314,7 +314,7 @@ }; i2c1: i2c@50068000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -351,6 +351,8 @@ reg = <0x5003c000 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; status = "disabled"; }; @@ -359,6 +361,8 @@ reg = <0x5003c030 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <3>; + silabs,wakeup-pins = <1>; status = "disabled"; }; @@ -367,6 +371,8 @@ reg = <0x5003c060 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <6>, <7>; + silabs,wakeup-pins = <0>, <5>; status = "disabled"; }; @@ -375,6 +381,8 @@ reg = <0x5003c090 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <9>; + silabs,wakeup-pins = <2>; status = "disabled"; }; }; diff --git a/dts/arm/silabs/xg22/xg22.dtsi b/dts/arm/silabs/xg22/xg22.dtsi index 1aaa8db3869c1..5b4981a13742c 100644 --- a/dts/arm/silabs/xg22/xg22.dtsi +++ b/dts/arm/silabs/xg22/xg22.dtsi @@ -129,7 +129,7 @@ * The minimum residency and exit latency is * managed by sl_power_manager on S2 devices. */ - cpu-power-states = <&pstate_em1 &pstate_em2>; + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em4>; #address-cells = <1>; #size-cells = <1>; @@ -158,6 +158,16 @@ compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; }; + + /* + * EM4 is a shutdown state where all clocks are off. The device + * is reset on wakeup from EM4. + */ + pstate_em4: em4 { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + status = "disabled"; + }; }; }; @@ -367,7 +377,7 @@ }; i2c0: i2c@5a010000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; reg = <0x5a010000 0x3044>; interrupts = <27 2>; @@ -378,7 +388,7 @@ }; i2c1: i2c@50068000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; reg = <0x50068000 0x3044>; interrupts = <28 2>; @@ -403,6 +413,8 @@ reg = <0x5003C000 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; status = "disabled"; }; @@ -411,6 +423,8 @@ reg = <0x5003C030 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <3>, <4>; + silabs,wakeup-pins = <1>, <3>; status = "disabled"; }; @@ -419,6 +433,8 @@ reg = <0x5003C060 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <6>, <7>, <8>; + silabs,wakeup-pins = <0>, <5>, <7>; status = "disabled"; }; @@ -427,6 +443,8 @@ reg = <0x5003C090 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <9>; + silabs,wakeup-pins = <2>; status = "disabled"; }; }; diff --git a/dts/arm/silabs/xg23/xg23.dtsi b/dts/arm/silabs/xg23/xg23.dtsi index 4feca87c7090f..2964343acce7d 100644 --- a/dts/arm/silabs/xg23/xg23.dtsi +++ b/dts/arm/silabs/xg23/xg23.dtsi @@ -149,7 +149,7 @@ device_type = "cpu"; compatible = "arm,cortex-m33"; reg = <0>; - cpu-power-states = <&pstate_em1 &pstate_em2>; + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em4>; /* * The minimum residency and exit latency is * managed by sl_power_manager on S2 devices. @@ -182,6 +182,16 @@ compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; }; + + /* + * EM4 is a shutdown state where all clocks are off. The device + * is reset on wakeup from EM4. + */ + pstate_em4: em4 { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + status = "disabled"; + }; }; }; @@ -413,7 +423,7 @@ }; i2c0: i2c@5b000000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -424,7 +434,7 @@ }; i2c1: i2c@50068000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -461,6 +471,8 @@ reg = <0x5003c030 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; status = "disabled"; }; @@ -469,6 +481,8 @@ reg = <0x5003c060 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <3>, <4>; + silabs,wakeup-pins = <1>, <3>; status = "disabled"; }; @@ -477,6 +491,8 @@ reg = <0x5003c090 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <6>, <7>, <8>; + silabs,wakeup-pins = <0>, <5>, <7>; status = "disabled"; }; @@ -485,6 +501,8 @@ reg = <0x5003c0C0 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <9>, <10>; + silabs,wakeup-pins = <2>, <5>; status = "disabled"; }; }; diff --git a/dts/arm/silabs/xg24/bgm240sa22vna.dtsi b/dts/arm/silabs/xg24/bgm240sa22vna.dtsi new file mode 100644 index 0000000000000..b06af075d3743 --- /dev/null +++ b/dts/arm/silabs/xg24/bgm240sa22vna.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2023 Fr. Sauter AG + * Copyright (c) 2025 Silicon Laboratories Inc. + * Copyright (c) 2025 Ephraim Westenberger + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,bgm240sa22vna", "silabs,efr32bg24", "silabs,xg24", + "silabs,efr32", "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1536)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg24/efr32bg24.dtsi b/dts/arm/silabs/xg24/efr32bg24.dtsi new file mode 100644 index 0000000000000..bb3c4651d2b87 --- /dev/null +++ b/dts/arm/silabs/xg24/efr32bg24.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/silabs/xg24/xg24.dtsi b/dts/arm/silabs/xg24/xg24.dtsi index 1cdab33bed43b..5bac1bd4200f0 100644 --- a/dts/arm/silabs/xg24/xg24.dtsi +++ b/dts/arm/silabs/xg24/xg24.dtsi @@ -139,7 +139,7 @@ device_type = "cpu"; compatible = "arm,cortex-m33"; reg = <0>; - cpu-power-states = <&pstate_em1 &pstate_em2>; + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em4>; /* * The minimum residency and exit latency is * managed by sl_power_manager on S2 devices. @@ -172,6 +172,16 @@ compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; }; + + /* + * EM4 is a shutdown state where all clocks are off. The device + * is reset on wakeup from EM4. + */ + pstate_em4: em4 { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + status = "disabled"; + }; }; }; @@ -394,7 +404,7 @@ }; i2c0: i2c@5b000000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -431,6 +441,8 @@ reg = <0x5003c030 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; status = "disabled"; }; @@ -439,6 +451,8 @@ reg = <0x5003c060 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <3>, <4>; + silabs,wakeup-pins = <1>, <3>; status = "disabled"; }; @@ -447,6 +461,8 @@ reg = <0x5003c090 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <6>, <7>, <8>; + silabs,wakeup-pins = <0>, <5>, <7>; status = "disabled"; }; @@ -455,6 +471,8 @@ reg = <0x5003c0C0 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <9>, <10>; + silabs,wakeup-pins = <2>, <5>; status = "disabled"; }; }; diff --git a/dts/arm/silabs/xg27/xg27.dtsi b/dts/arm/silabs/xg27/xg27.dtsi index 023551e2db70d..5f320bd55ca38 100644 --- a/dts/arm/silabs/xg27/xg27.dtsi +++ b/dts/arm/silabs/xg27/xg27.dtsi @@ -138,7 +138,7 @@ * The minimum residency and exit latency is * managed by sl_power_manager on S2 devices. */ - cpu-power-states = <&pstate_em1 &pstate_em2>; + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em4>; #address-cells = <1>; #size-cells = <1>; @@ -167,6 +167,16 @@ compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; }; + + /* + * EM4 is a shutdown state where all clocks are off. The device + * is reset on wakeup from EM4. + */ + pstate_em4: em4 { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + status = "disabled"; + }; }; }; @@ -376,7 +386,7 @@ }; i2c0: i2c@5a010000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; reg = <0x5a010000 0x3044>; interrupts = <32 2>; @@ -387,7 +397,7 @@ }; i2c1: i2c@50068000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; reg = <0x50068000 0x3044>; interrupts = <33 2>; @@ -412,6 +422,8 @@ reg = <0x5003C030 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; status = "disabled"; }; @@ -420,6 +432,8 @@ reg = <0x5003C060 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <3>, <4>; + silabs,wakeup-pins = <1>, <3>; status = "disabled"; }; @@ -428,6 +442,8 @@ reg = <0x5003C090 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <6>, <7>, <8>; + silabs,wakeup-pins = <0>, <5>, <7>; status = "disabled"; }; @@ -436,6 +452,8 @@ reg = <0x5003C0C0 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <9>; + silabs,wakeup-pins = <2>; status = "disabled"; }; }; @@ -462,9 +480,9 @@ status = "disabled"; }; - wdog0: wdog@4a018000 { + wdog0: wdog@5a018000 { compatible = "silabs,gecko-wdog"; - reg = <0x4A018000 0x3028>; + reg = <0x5A018000 0x3028>; interrupts = <49 2>; clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>; peripheral-id = <0>; diff --git a/dts/arm/silabs/xg28/efr32xg28.dtsi b/dts/arm/silabs/xg28/efr32xg28.dtsi new file mode 100644 index 0000000000000..da11c842c18ac --- /dev/null +++ b/dts/arm/silabs/xg28/efr32xg28.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + radio: radio@b0000000 { + compatible = "silabs,series2-radio"; + reg = <0xb0000000 0x1000000>; + interrupts = <31 1>, <32 1>, <33 1>, <34 1>, <35 1>, <36 1>, + <37 1>, <38 1>, <39 1>, <40 1>, <74 1>, <75 1>; + interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer", + "rac_rsm", "rac_seq", "hostmailbox", "synth", + "rfeca0", "rfeca1"; + pa-initial-power-dbm = <10>; + pa-ramp-time-us = <10>; + pa-subghz = "highest"; + pa-voltage-mv = <3300>; + pa-2p4ghz = "highest"; + + bt_hci_silabs: bt_hci_silabs { + compatible = "silabs,bt-hci-efr32"; + status = "disabled"; + }; + + pti: pti { + compatible = "silabs,pti"; + clock-frequency = ; + mode = "uart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/arm/silabs/xg28/efr32zg28.dtsi b/dts/arm/silabs/xg28/efr32zg28.dtsi new file mode 100644 index 0000000000000..da93b14638cf5 --- /dev/null +++ b/dts/arm/silabs/xg28/efr32zg28.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/silabs/xg28/efr32zg28b322f1024im68.dtsi b/dts/arm/silabs/xg28/efr32zg28b322f1024im68.dtsi new file mode 100644 index 0000000000000..60ceccbae6862 --- /dev/null +++ b/dts/arm/silabs/xg28/efr32zg28b322f1024im68.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Shontal Biton + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32zg28b322f1024im68", + "silabs,efr32zg28", "silabs,efr32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg28/xg28.dtsi b/dts/arm/silabs/xg28/xg28.dtsi index ed5bfa457ccbd..4155f2760746e 100644 --- a/dts/arm/silabs/xg28/xg28.dtsi +++ b/dts/arm/silabs/xg28/xg28.dtsi @@ -170,7 +170,7 @@ device_type = "cpu"; compatible = "arm,cortex-m33"; reg = <0>; - cpu-power-states = <&pstate_em1 &pstate_em2>; + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em4>; /* * The minimum residency and exit latency is * managed by sl_power_manager on S2 devices. @@ -196,6 +196,16 @@ compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; }; + + /* + * EM4 is a shutdown state where all clocks are off. The device + * is reset on wakeup from EM4. + */ + pstate_em4: em4 { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + status = "disabled"; + }; }; }; @@ -427,7 +437,7 @@ }; i2c0: i2c@5b000000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -438,7 +448,7 @@ }; i2c1: i2c@50068000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -475,6 +485,8 @@ reg = <0x5003c030 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; status = "disabled"; }; @@ -483,6 +495,8 @@ reg = <0x5003c060 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <3>, <4>; + silabs,wakeup-pins = <1>, <3>; status = "disabled"; }; @@ -491,6 +505,8 @@ reg = <0x5003c090 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <6>, <7>, <8>; + silabs,wakeup-pins = <0>, <5>, <7>; status = "disabled"; }; @@ -499,6 +515,8 @@ reg = <0x5003c0c0 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <9>, <10>; + silabs,wakeup-pins = <2>, <5>; status = "disabled"; }; }; diff --git a/dts/arm/silabs/xg29/xg29.dtsi b/dts/arm/silabs/xg29/xg29.dtsi index db155d3dac475..3942f7705ffa1 100644 --- a/dts/arm/silabs/xg29/xg29.dtsi +++ b/dts/arm/silabs/xg29/xg29.dtsi @@ -146,7 +146,7 @@ device_type = "cpu"; compatible = "arm,cortex-m33"; reg = <0>; - cpu-power-states = <&pstate_em1 &pstate_em2>; + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em4>; /* * The minimum residency and exit latency is * managed by sl_power_manager on S2 devices. @@ -179,6 +179,16 @@ compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; }; + + /* + * EM4 is a shutdown state where all clocks are off. The device + * is reset on wakeup from EM4. + */ + pstate_em4: em4 { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + status = "disabled"; + }; }; }; @@ -293,6 +303,8 @@ reg = <0x5003C030 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <0>; + silabs,wakeup-pins = <5>; status = "disabled"; }; @@ -301,6 +313,8 @@ reg = <0x5003C060 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <3>, <4>; + silabs,wakeup-pins = <1>, <3>; status = "disabled"; }; @@ -309,6 +323,8 @@ reg = <0x5003C090 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <6>, <7>, <8>; + silabs,wakeup-pins = <0>, <5>, <7>; status = "disabled"; }; @@ -317,6 +333,8 @@ reg = <0x5003C0C0 0x30>; gpio-controller; #gpio-cells = <2>; + silabs,wakeup-ints = <9>; + silabs,wakeup-pins = <2>; status = "disabled"; }; }; @@ -445,7 +463,7 @@ }; i2c0: i2c@5a010000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; reg = <0x5a010000 0x4000>; interrupts = <32 2>; @@ -457,7 +475,7 @@ }; i2c1: i2c@50068000 { - compatible = "silabs,gecko-i2c"; + compatible = "silabs,i2c"; clock-frequency = ; reg = <0x50068000 0x4000>; interrupts = <33 2>; diff --git a/dts/arm/st/c0/stm32c0.dtsi b/dts/arm/st/c0/stm32c0.dtsi index eb21bc3cd46c1..229ff9a57225f 100644 --- a/dts/arm/st/c0/stm32c0.dtsi +++ b/dts/arm/st/c0/stm32c0.dtsi @@ -73,6 +73,7 @@ / { chosen { zephyr,flash-controller = &flash; + zephyr,cortex-m-idle-timer = &rtc; }; cpus { @@ -83,6 +84,22 @@ device_type = "cpu"; compatible = "arm,cortex-m0+"; reg = <0>; + cpu-power-states = <&stop>; + }; + + power-states { + stop: stop { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + /* It is really hard to establish these numbers precisely. + * We are basing on RTC as a wakeup source with 62,5us tick. + * It requires a proper margin. Additionally, sys_clock_announce + * works within system tick boundaries (100us by default), + * which also introduces some shift. + */ + min-residency-us = <400>; + exit-latency-us = <300>; + }; }; }; @@ -138,7 +155,7 @@ compatible = "st,stm32-flash-controller" , "st,stm32g0-flash-controller"; reg = <0x40022000 0x400>; interrupts = <3 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; #address-cells = <1>; #size-cells = <1>; @@ -188,7 +205,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 0U)>; + clocks = <&rcc STM32_CLOCK(IOP, 0)>; }; gpiob: gpio@50000400 { @@ -196,7 +213,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000400 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 1U)>; + clocks = <&rcc STM32_CLOCK(IOP, 1)>; }; gpioc: gpio@50000800 { @@ -204,7 +221,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000800 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 2U)>; + clocks = <&rcc STM32_CLOCK(IOP, 2)>; }; gpiof: gpio@50001400 { @@ -212,7 +229,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001400 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 5U)>; + clocks = <&rcc STM32_CLOCK(IOP, 5)>; }; }; @@ -260,7 +277,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <2 0>; - clocks = <&rcc STM32_CLOCK(APB1, 10U)>; + clocks = <&rcc STM32_CLOCK(APB1, 10)>; prescaler = <32768>; alarms-count = <1>; alrm-exti-line = <19>; @@ -270,7 +287,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 2>; status = "disabled"; }; @@ -284,7 +301,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 14)>; resets = <&rctl STM32_RESET(APB1H, 14U)>; interrupts = <27 0>; status = "disabled"; @@ -293,7 +310,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -420,7 +437,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <23 0>; interrupt-names = "combined"; status = "disabled"; @@ -431,7 +448,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 12)>; interrupts = <25 0>; status = "disabled"; }; @@ -439,7 +456,7 @@ adc1: adc@40012400 { compatible = "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 20)>; interrupts = <12 0>; status = "disabled"; #io-channel-cells = <1>; @@ -458,7 +475,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <9 0 10 0 10 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-requests = <3>; dma-offset = <0>; status = "disabled"; diff --git a/dts/arm/st/c0/stm32c031.dtsi b/dts/arm/st/c0/stm32c031.dtsi index dc24fc521cd28..e3fbd5fb767ad 100644 --- a/dts/arm/st/c0/stm32c031.dtsi +++ b/dts/arm/st/c0/stm32c031.dtsi @@ -16,7 +16,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000c00 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 3U)>; + clocks = <&rcc STM32_CLOCK(IOP, 3)>; }; }; }; diff --git a/dts/arm/st/c0/stm32c071.dtsi b/dts/arm/st/c0/stm32c071.dtsi index 8ab8f3d735e35..76268141183a1 100644 --- a/dts/arm/st/c0/stm32c071.dtsi +++ b/dts/arm/st/c0/stm32c071.dtsi @@ -49,7 +49,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "global"; status = "disabled"; @@ -74,7 +74,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 0>; interrupt-names = "global"; status = "disabled"; diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi index e0c7a0a531358..b84c58ad03fb3 100644 --- a/dts/arm/st/f0/stm32f0.dtsi +++ b/dts/arm/st/f0/stm32f0.dtsi @@ -86,7 +86,7 @@ compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; reg = <0x40022000 0x400>; interrupts = <3 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; #address-cells = <1>; #size-cells = <1>; @@ -135,7 +135,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 17U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 17)>; }; gpiob: gpio@48000400 { @@ -143,7 +143,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; }; gpioc: gpio@48000800 { @@ -151,7 +151,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 19U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 19)>; }; gpiod: gpio@48000c00 { @@ -159,7 +159,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 20U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 20)>; }; gpiof: gpio@48001400 { @@ -167,14 +167,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 22)>; }; }; usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <27 0>; status = "disabled"; @@ -186,7 +186,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>, + clocks = <&rcc STM32_CLOCK(APB1, 21)>, /* I2C1 clock source should always be defined, * even for the default value */ @@ -201,7 +201,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <25 3>; status = "disabled"; }; @@ -209,7 +209,7 @@ rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; interrupts = <2 0>; prescaler = <32768>; alarms-count = <1>; @@ -226,7 +226,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 2>; status = "disabled"; }; @@ -344,7 +344,7 @@ adc1: adc@40012400 { compatible = "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <12 0>; status = "disabled"; #io-channel-cells = <1>; @@ -362,7 +362,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; interrupts = <9 0 10 0 10 0 11 0 11 0>; status = "disabled"; }; diff --git a/dts/arm/st/f0/stm32f030X8.dtsi b/dts/arm/st/f0/stm32f030X8.dtsi index 2272a0706c0f7..a440d8da64580 100644 --- a/dts/arm/st/f0/stm32f030X8.dtsi +++ b/dts/arm/st/f0/stm32f030X8.dtsi @@ -21,7 +21,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 3>; status = "disabled"; }; diff --git a/dts/arm/st/f0/stm32f030Xc.dtsi b/dts/arm/st/f0/stm32f030Xc.dtsi index 9867c17664a99..6b0b9dfd8d9f9 100644 --- a/dts/arm/st/f0/stm32f030Xc.dtsi +++ b/dts/arm/st/f0/stm32f030Xc.dtsi @@ -29,7 +29,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <29 0>; status = "disabled"; @@ -38,7 +38,7 @@ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <29 0>; status = "disabled"; @@ -47,7 +47,7 @@ usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <29 0>; status = "disabled"; @@ -56,7 +56,7 @@ usart6: serial@40011400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <29 0>; status = "disabled"; diff --git a/dts/arm/st/f0/stm32f042.dtsi b/dts/arm/st/f0/stm32f042.dtsi index 2528df8d91151..133f63fc34f7e 100644 --- a/dts/arm/st/f0/stm32f042.dtsi +++ b/dts/arm/st/f0/stm32f042.dtsi @@ -24,7 +24,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -35,7 +35,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 3>; status = "disabled"; }; @@ -44,7 +44,7 @@ compatible = "st,stm32-bxcan"; reg = <0x40006400 0x400>; interrupts = <30 0>; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -75,7 +75,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + clocks = <&rcc STM32_CLOCK(APB1, 23)>, <&rcc STM32_SRC_PLLCLK USB_SEL(1)>; status = "disabled"; }; diff --git a/dts/arm/st/f0/stm32f051.dtsi b/dts/arm/st/f0/stm32f051.dtsi index 243aea40a7595..f73e92be9f0de 100644 --- a/dts/arm/st/f0/stm32f051.dtsi +++ b/dts/arm/st/f0/stm32f051.dtsi @@ -13,7 +13,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -25,7 +25,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -36,7 +36,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 3>; status = "disabled"; }; @@ -74,7 +74,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/f0/stm32f070.dtsi b/dts/arm/st/f0/stm32f070.dtsi index b11d53fde0dd5..e9a5a3831c1b4 100644 --- a/dts/arm/st/f0/stm32f070.dtsi +++ b/dts/arm/st/f0/stm32f070.dtsi @@ -13,7 +13,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -46,7 +46,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + clocks = <&rcc STM32_CLOCK(APB1, 23)>, <&rcc STM32_SRC_PLLCLK USB_SEL(1)>; status = "disabled"; }; diff --git a/dts/arm/st/f0/stm32f070Xb.dtsi b/dts/arm/st/f0/stm32f070Xb.dtsi index 18f4039dc1687..b7c8abefe53d3 100644 --- a/dts/arm/st/f0/stm32f070Xb.dtsi +++ b/dts/arm/st/f0/stm32f070Xb.dtsi @@ -28,7 +28,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <29 0>; status = "disabled"; @@ -37,7 +37,7 @@ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <29 0>; status = "disabled"; @@ -49,7 +49,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -60,7 +60,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 3>; status = "disabled"; }; diff --git a/dts/arm/st/f0/stm32f071.dtsi b/dts/arm/st/f0/stm32f071.dtsi index d14163a721ab9..bd0d2dd51babf 100644 --- a/dts/arm/st/f0/stm32f071.dtsi +++ b/dts/arm/st/f0/stm32f071.dtsi @@ -31,7 +31,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 21)>; }; }; @@ -44,7 +44,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <29 0>; status = "disabled"; @@ -53,7 +53,7 @@ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <29 0>; status = "disabled"; diff --git a/dts/arm/st/f0/stm32f072.dtsi b/dts/arm/st/f0/stm32f072.dtsi index 3bb264c10b944..c495d9af24f20 100644 --- a/dts/arm/st/f0/stm32f072.dtsi +++ b/dts/arm/st/f0/stm32f072.dtsi @@ -14,7 +14,7 @@ compatible = "st,stm32-bxcan"; reg = <0x40006400 0x400>; interrupts = <30 0>; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -27,7 +27,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + clocks = <&rcc STM32_CLOCK(APB1, 23)>, <&rcc STM32_SRC_PLLCLK USB_SEL(1)>; status = "disabled"; }; diff --git a/dts/arm/st/f0/stm32f091.dtsi b/dts/arm/st/f0/stm32f091.dtsi index 18aea85517bd4..ff6fcd9f336a9 100644 --- a/dts/arm/st/f0/stm32f091.dtsi +++ b/dts/arm/st/f0/stm32f091.dtsi @@ -19,7 +19,7 @@ usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <29 0>; status = "disabled"; @@ -28,7 +28,7 @@ usart6: serial@40011400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <29 0>; status = "disabled"; @@ -37,7 +37,7 @@ usart7: serial@40011800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 6U)>; + clocks = <&rcc STM32_CLOCK(APB2, 6)>; resets = <&rctl STM32_RESET(APB2, 6U)>; interrupts = <29 0>; status = "disabled"; @@ -46,7 +46,7 @@ usart8: serial@40011c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 7U)>; + clocks = <&rcc STM32_CLOCK(APB2, 7)>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <29 0>; status = "disabled"; @@ -56,7 +56,7 @@ compatible = "st,stm32-bxcan"; reg = <0x40006400 0x400>; interrupts = <30 0>; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -65,7 +65,7 @@ #dma-cells = <2>; reg = <0x40020400 0x400>; interrupts = <10 0 10 0 11 0 11 0 11 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; status = "disabled"; }; }; diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi index d5f427b11f9c0..1aa03c531c6fa 100644 --- a/dts/arm/st/f1/stm32f1.dtsi +++ b/dts/arm/st/f1/stm32f1.dtsi @@ -106,7 +106,7 @@ compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; reg = <0x40022000 0x400>; interrupts = <3 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; #address-cells = <1>; #size-cells = <1>; @@ -157,7 +157,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40010800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 2U)>; + clocks = <&rcc STM32_CLOCK(APB2, 2)>; }; gpiob: gpio@40010c00 { @@ -165,7 +165,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40010c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 3U)>; + clocks = <&rcc STM32_CLOCK(APB2, 3)>; }; gpioc: gpio@40011000 { @@ -173,7 +173,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40011000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 4U)>; + clocks = <&rcc STM32_CLOCK(APB2, 4)>; }; gpiod: gpio@40011400 { @@ -181,7 +181,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; }; gpioe: gpio@40011800 { @@ -189,14 +189,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40011800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 6U)>; + clocks = <&rcc STM32_CLOCK(APB2, 6)>; }; }; usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <37 0>; status = "disabled"; @@ -205,7 +205,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -214,7 +214,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -226,7 +226,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -238,7 +238,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -249,7 +249,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; status = "disabled"; }; @@ -263,7 +263,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -359,7 +359,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; prescaler = <32768>; status = "disabled"; }; @@ -367,7 +367,7 @@ adc1: adc@40012400 { compatible = "st,stm32f1-adc", "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -381,7 +381,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; status = "disabled"; }; diff --git a/dts/arm/st/f1/stm32f100Xb.dtsi b/dts/arm/st/f1/stm32f100Xb.dtsi index 9a33217e18c43..b0a99a9187ea5 100644 --- a/dts/arm/st/f1/stm32f100Xb.dtsi +++ b/dts/arm/st/f1/stm32f100Xb.dtsi @@ -39,7 +39,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -47,7 +47,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/f1/stm32f100Xe.dtsi b/dts/arm/st/f1/stm32f100Xe.dtsi index 45a8bedd9e0ee..67a85ef347806 100644 --- a/dts/arm/st/f1/stm32f100Xe.dtsi +++ b/dts/arm/st/f1/stm32f100Xe.dtsi @@ -26,7 +26,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; diff --git a/dts/arm/st/f1/stm32f103X8.dtsi b/dts/arm/st/f1/stm32f103X8.dtsi index 67b32d576a4bd..055c97ab269cd 100644 --- a/dts/arm/st/f1/stm32f103X8.dtsi +++ b/dts/arm/st/f1/stm32f103X8.dtsi @@ -30,7 +30,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -44,7 +44,7 @@ ram-size = <512>; maximum-speed = "full-speed"; status = "disabled"; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; phys = <&usb_fs_phy>; }; @@ -53,7 +53,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; }; diff --git a/dts/arm/st/f1/stm32f103Xc.dtsi b/dts/arm/st/f1/stm32f103Xc.dtsi index 0af63d8cc6ef0..7b7806ae01344 100644 --- a/dts/arm/st/f1/stm32f103Xc.dtsi +++ b/dts/arm/st/f1/stm32f103Xc.dtsi @@ -26,7 +26,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -35,7 +35,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -88,7 +88,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0X40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -96,7 +96,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -109,7 +109,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40011c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 7U)>; + clocks = <&rcc STM32_CLOCK(APB2, 7)>; }; gpiog: gpio@40012000 { @@ -117,14 +117,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40012000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB2, 8)>; }; }; adc2: adc@40012800 { compatible = "st,stm32-adc"; reg = <0x40012800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>; + clocks = <&rcc STM32_CLOCK(APB2, 10)>; /* Shares vector with ADC1 */ interrupts = <18 0>; status = "disabled"; @@ -134,7 +134,7 @@ adc3: adc@40013c00 { compatible = "st,stm32-adc"; reg = <0x40013c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 15U)>; + clocks = <&rcc STM32_CLOCK(APB2, 15)>; interrupts = <47 0>; status = "disabled"; #io-channel-cells = <1>; @@ -143,7 +143,7 @@ timers8: timers@40013400 { compatible = "st,stm32-timers"; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; resets = <&rctl STM32_RESET(APB2, 13U)>; interrupts = <43 0>, <44 0>, <45 0>, <46 0>; interrupt-names = "brk", "up", "trgcom", "cc"; @@ -161,7 +161,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; interrupts = < 56 0 57 0 58 0 59 0 60 0>; status = "disabled"; }; diff --git a/dts/arm/st/f1/stm32f105.dtsi b/dts/arm/st/f1/stm32f105.dtsi index 2ecdd5401ff0c..23efd57b7a7a9 100644 --- a/dts/arm/st/f1/stm32f105.dtsi +++ b/dts/arm/st/f1/stm32f105.dtsi @@ -39,7 +39,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -56,7 +56,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -64,7 +64,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -73,7 +73,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -84,7 +84,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -94,7 +94,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -148,7 +148,7 @@ interrupt-names = "otgfs"; num-bidir-endpoints = <4>; ram-size = <1280>; - clocks = <&rcc STM32_CLOCK(AHB1, 12U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 12)>; maximum-speed = "full-speed"; phys = <&otgfs_phy>; status = "disabled"; diff --git a/dts/arm/st/f1/stm32f107.dtsi b/dts/arm/st/f1/stm32f107.dtsi index 8f4b2d6b99136..0e4301aab3fe4 100644 --- a/dts/arm/st/f1/stm32f107.dtsi +++ b/dts/arm/st/f1/stm32f107.dtsi @@ -14,7 +14,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; interrupts = <56 0 57 0 58 0 59 0 60 0>; status = "disabled"; }; diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi index c253defc800c4..6b6a9cd429a5c 100644 --- a/dts/arm/st/f2/stm32f2.dtsi +++ b/dts/arm/st/f2/stm32f2.dtsi @@ -131,7 +131,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; }; gpiob: gpio@40020400 { @@ -139,7 +139,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; }; gpioc: gpio@40020800 { @@ -147,7 +147,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; }; gpiod: gpio@40020c00 { @@ -155,7 +155,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 3)>; }; gpioe: gpio@40021000 { @@ -163,7 +163,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; }; gpiof: gpio@40021400 { @@ -171,7 +171,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; }; gpiog: gpio@40021800 { @@ -179,7 +179,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 6)>; }; gpioh: gpio@40021c00 { @@ -187,7 +187,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 7)>; }; gpioi: gpio@40022000 { @@ -195,14 +195,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; }; }; rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; interrupts = <41 0>; prescaler = <32768>; alarms-count = <2>; @@ -225,7 +225,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -233,7 +233,7 @@ usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 4U)>; + clocks = <&rcc STM32_CLOCK(APB2, 4)>; resets = <&rctl STM32_RESET(APB2, 4U)>; interrupts = <37 0>; status = "disabled"; @@ -242,7 +242,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -251,7 +251,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -260,7 +260,7 @@ usart6: serial@40011400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <71 0>; status = "disabled"; @@ -269,7 +269,7 @@ uart4: serial@40004c00 { compatible ="st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -278,7 +278,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -289,7 +289,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; status = "disabled"; }; @@ -299,7 +299,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -309,7 +309,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -320,7 +320,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -332,7 +332,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -344,7 +344,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -358,7 +358,7 @@ num-bidir-endpoints = <4>; ram-size = <1280>; maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 7)>, <&rcc STM32_SRC_PLL_Q NO_SEL>; phys = <&otgfs_phy>; status = "disabled"; @@ -367,7 +367,7 @@ adc1: adc@40012000 { compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB2, 8)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -386,7 +386,7 @@ #dma-cells = <4>; reg = <0x40026000 0x400>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 21)>; status = "disabled"; }; @@ -395,7 +395,7 @@ #dma-cells = <4>; reg = <0x40026400 0x400>; interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 22)>; st,mem2mem; status = "disabled"; }; @@ -403,7 +403,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -743,14 +743,14 @@ compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; interrupts = <80 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; status = "disabled"; }; backup_sram: memory@40024000 { compatible = "zephyr,memory-region", "st,stm32-backup-sram"; reg = <0x40024000 DT_SIZE_K(4)>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; zephyr,memory-region = "BACKUP_SRAM"; status = "disabled"; }; diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index ccc295176c54f..6d42d6017037d 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -79,7 +79,7 @@ compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; reg = <0x40022000 0x400>; interrupts = <4 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; #address-cells = <1>; #size-cells = <1>; @@ -132,7 +132,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 17U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 17)>; }; gpiob: gpio@48000400 { @@ -140,7 +140,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; }; gpioc: gpio@48000800 { @@ -148,7 +148,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 19U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 19)>; }; gpiod: gpio@48000c00 { @@ -156,7 +156,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 20U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 20)>; }; gpiof: gpio@48001400 { @@ -164,7 +164,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 22)>; }; }; @@ -177,7 +177,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -185,7 +185,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <37 0>; status = "disabled"; @@ -194,7 +194,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -203,7 +203,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -212,7 +212,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -224,7 +224,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>, + clocks = <&rcc STM32_CLOCK(APB1, 21)>, /* I2C clock source should always be defined, * even for the default value */ @@ -239,7 +239,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; status = "disabled"; }; @@ -247,7 +247,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -261,7 +261,7 @@ ram-size = <512>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; status = "disabled"; }; @@ -377,7 +377,7 @@ rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; interrupts = <41 0>; prescaler = <32768>; alarms-count = <2>; @@ -390,7 +390,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -398,7 +398,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; status = "disabled"; }; diff --git a/dts/arm/st/f3/stm32f302.dtsi b/dts/arm/st/f3/stm32f302.dtsi index ca0629aa83367..423cef979f191 100644 --- a/dts/arm/st/f3/stm32f302.dtsi +++ b/dts/arm/st/f3/stm32f302.dtsi @@ -22,7 +22,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>, + clocks = <&rcc STM32_CLOCK(APB1, 22)>, /* I2C clock source should always be defined, * even for the default value */ @@ -38,7 +38,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>, + clocks = <&rcc STM32_CLOCK(APB1, 30)>, /* I2C clock source should always be defined, * even for the default value */ @@ -53,7 +53,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -63,7 +63,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0X40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -104,7 +104,7 @@ adc1: adc@50000000 { compatible = "st,stm32-adc"; reg = <0x50000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 28U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 28)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; diff --git a/dts/arm/st/f3/stm32f302Xc.dtsi b/dts/arm/st/f3/stm32f302Xc.dtsi index 113716e7b0a98..bad54f7d12e0a 100644 --- a/dts/arm/st/f3/stm32f302Xc.dtsi +++ b/dts/arm/st/f3/stm32f302Xc.dtsi @@ -69,7 +69,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; interrupts = <56 0 57 0 58 0 59 0 60 0>; status = "disabled"; }; @@ -77,7 +77,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; interrupts = <53 0>; status = "disabled"; }; @@ -88,7 +88,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 21)>; }; }; }; diff --git a/dts/arm/st/f3/stm32f303.dtsi b/dts/arm/st/f3/stm32f303.dtsi index a6d67fccb39d9..14923f96f9083 100644 --- a/dts/arm/st/f3/stm32f303.dtsi +++ b/dts/arm/st/f3/stm32f303.dtsi @@ -22,7 +22,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>, + clocks = <&rcc STM32_CLOCK(APB1, 22)>, /* I2C clock source should always be defined, * even for the default value */ @@ -37,7 +37,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -55,7 +55,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -68,7 +68,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 21)>; }; }; @@ -133,7 +133,7 @@ adc1: adc@50000000 { compatible = "st,stm32-adc"; reg = <0x50000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 28U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 28)>; interrupts = <18 0>; status = "disabled"; vref-mv = <3000>; @@ -150,7 +150,7 @@ adc2: adc@50000100 { compatible = "st,stm32-adc"; reg = <0x50000100 0x4c>; - clocks = <&rcc STM32_CLOCK(AHB1, 28U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 28)>; interrupts = <18 0>; status = "disabled"; vref-mv = <3000>; diff --git a/dts/arm/st/f3/stm32f303X8.dtsi b/dts/arm/st/f3/stm32f303X8.dtsi index 2e03ffe83790e..17ea1cdd1d18c 100644 --- a/dts/arm/st/f3/stm32f303X8.dtsi +++ b/dts/arm/st/f3/stm32f303X8.dtsi @@ -28,7 +28,7 @@ dac2: dac@40009800 { compatible = "st,stm32-dac"; reg = <0x40009800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; + clocks = <&rcc STM32_CLOCK(APB1, 26)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/f3/stm32f303Xb.dtsi b/dts/arm/st/f3/stm32f303Xb.dtsi index 72935cc84cfc6..8dcff35fd9992 100644 --- a/dts/arm/st/f3/stm32f303Xb.dtsi +++ b/dts/arm/st/f3/stm32f303Xb.dtsi @@ -65,7 +65,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; interrupts = <56 0 57 0 58 0 59 0 60 0>; status = "disabled"; }; diff --git a/dts/arm/st/f3/stm32f303Xe.dtsi b/dts/arm/st/f3/stm32f303Xe.dtsi index e3ec3d7388d34..8ff7be291f5f7 100644 --- a/dts/arm/st/f3/stm32f303Xe.dtsi +++ b/dts/arm/st/f3/stm32f303Xe.dtsi @@ -108,7 +108,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; interrupts = <56 0 57 0 58 0 59 0 60 0>; status = "disabled"; }; @@ -121,7 +121,7 @@ }; }; - i2c3: i2c@4007800 { + i2c3: i2c@40007800 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; #address-cells = <1>; diff --git a/dts/arm/st/f3/stm32f334.dtsi b/dts/arm/st/f3/stm32f334.dtsi index 2eb219ee9fb7a..60435f380dc19 100644 --- a/dts/arm/st/f3/stm32f334.dtsi +++ b/dts/arm/st/f3/stm32f334.dtsi @@ -72,7 +72,7 @@ adc1: adc@50000000 { compatible = "st,stm32-adc"; reg = <0x50000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 28U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 28)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; diff --git a/dts/arm/st/f3/stm32f334X8.dtsi b/dts/arm/st/f3/stm32f334X8.dtsi index d74d77ab49a3d..caf654d77e5a9 100644 --- a/dts/arm/st/f3/stm32f334X8.dtsi +++ b/dts/arm/st/f3/stm32f334X8.dtsi @@ -28,7 +28,7 @@ dac2: dac@40009800 { compatible = "st,stm32-dac"; reg = <0x40009800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; + clocks = <&rcc STM32_CLOCK(APB1, 26)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/f3/stm32f373.dtsi b/dts/arm/st/f3/stm32f373.dtsi index 8424c604be25a..42406b3950678 100644 --- a/dts/arm/st/f3/stm32f373.dtsi +++ b/dts/arm/st/f3/stm32f373.dtsi @@ -25,7 +25,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 21)>; }; }; @@ -35,7 +35,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>, + clocks = <&rcc STM32_CLOCK(APB1, 22)>, /* I2C clock source should always be defined, * even for the default value */ @@ -50,7 +50,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -60,7 +60,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -234,7 +234,7 @@ adc1: adc@40012400 { compatible = "st,stm32f1-adc", "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; diff --git a/dts/arm/st/f3/stm32f373Xc.dtsi b/dts/arm/st/f3/stm32f373Xc.dtsi index 6ad6a7174a08a..f9898820755d5 100644 --- a/dts/arm/st/f3/stm32f373Xc.dtsi +++ b/dts/arm/st/f3/stm32f373Xc.dtsi @@ -22,7 +22,7 @@ dma2: dma@40020400 { compatible = "st,stm32-dma-v2bis"; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; interrupts = <56 0 57 0 58 0 59 0 60 0>; status = "disabled"; }; @@ -30,7 +30,7 @@ dac2: dac@40009800 { compatible = "st,stm32-dac"; reg = <0x40009800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; + clocks = <&rcc STM32_CLOCK(APB1, 26)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index b8bf17ee21b63..c4b729ac0c9c8 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -162,7 +162,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; }; gpiob: gpio@40020400 { @@ -170,7 +170,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; }; gpioc: gpio@40020800 { @@ -178,7 +178,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; }; gpiod: gpio@40020c00 { @@ -186,7 +186,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 3)>; }; gpioe: gpio@40021000 { @@ -194,7 +194,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; }; gpiof: gpio@40021400 { @@ -202,7 +202,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; }; gpiog: gpio@40021800 { @@ -210,7 +210,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 6)>; }; gpioh: gpio@40021c00 { @@ -218,7 +218,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 7)>; }; }; @@ -231,7 +231,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -239,7 +239,7 @@ usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 4U)>; + clocks = <&rcc STM32_CLOCK(APB2, 4)>; resets = <&rctl STM32_RESET(APB2, 4U)>; interrupts = <37 0>; status = "disabled"; @@ -248,7 +248,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -257,7 +257,7 @@ usart6: serial@40011400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <71 0>; status = "disabled"; @@ -269,7 +269,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -281,7 +281,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -293,7 +293,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -304,7 +304,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; status = "disabled"; }; @@ -318,7 +318,7 @@ ram-size = <1280>; maximum-speed = "full-speed"; phys = <&otgfs_phy>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 7)>, <&rcc STM32_SRC_PLL_Q NO_SEL>; status = "disabled"; }; @@ -536,7 +536,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -552,7 +552,7 @@ adc1: adc@40012000 { compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB2, 8)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -571,7 +571,7 @@ #dma-cells = <4>; reg = <0x40026000 0x400>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 21)>; status = "disabled"; }; @@ -580,7 +580,7 @@ #dma-cells = <4>; reg = <0x40026400 0x400>; interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 22)>; st,mem2mem; status = "disabled"; }; @@ -588,7 +588,7 @@ sdmmc1: sdmmc@40012c00 { compatible = "st,stm32-sdmmc"; reg = <0x40012c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 11U)>, + clocks = <&rcc STM32_CLOCK(APB2, 11)>, <&rcc STM32_SRC_PLL_Q NO_SEL>; resets = <&rctl STM32_RESET(APB2, 11U)>; interrupts = <49 0>; diff --git a/dts/arm/st/f4/stm32f401.dtsi b/dts/arm/st/f4/stm32f401.dtsi index e113144d2e1ee..523670bfc72cf 100644 --- a/dts/arm/st/f4/stm32f401.dtsi +++ b/dts/arm/st/f4/stm32f401.dtsi @@ -23,7 +23,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -43,7 +43,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <84 5>; status = "disabled"; }; @@ -53,7 +53,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; dmas = <&dma1 4 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma1 3 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -66,7 +66,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; dmas = <&dma1 5 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma1 0 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; diff --git a/dts/arm/st/f4/stm32f405.dtsi b/dts/arm/st/f4/stm32f405.dtsi index a9d74d60a474b..59cf1312a0928 100644 --- a/dts/arm/st/f4/stm32f405.dtsi +++ b/dts/arm/st/f4/stm32f405.dtsi @@ -27,7 +27,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; }; gpiog: gpio@40021800 { @@ -35,7 +35,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 6)>; }; gpioi: gpio@40022000 { @@ -43,14 +43,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; }; }; usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -59,7 +59,7 @@ uart4: serial@40004c00 { compatible ="st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -68,7 +68,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -210,7 +210,7 @@ ram-size = <4096>; maximum-speed = "full-speed"; phys = <&otghs_fs_phy>; - clocks = <&rcc STM32_CLOCK(AHB1, 29U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 29)>, <&rcc STM32_SRC_PLL_Q NO_SEL>; status = "disabled"; }; @@ -220,7 +220,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -239,14 +239,14 @@ compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; interrupts = <80 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; status = "disabled"; }; backup_sram: memory@40024000 { compatible = "zephyr,memory-region", "st,stm32-backup-sram"; reg = <0x40024000 DT_SIZE_K(4)>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; zephyr,memory-region = "BACKUP_SRAM"; status = "disabled"; }; @@ -254,7 +254,7 @@ adc2: adc@40012100 { compatible = "st,stm32-adc"; reg = <0x40012100 0x050>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -271,7 +271,7 @@ adc3: adc@40012200 { compatible = "st,stm32-adc"; reg = <0x40012200 0x050>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>; + clocks = <&rcc STM32_CLOCK(APB2, 10)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -288,7 +288,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/f4/stm32f410.dtsi b/dts/arm/st/f4/stm32f410.dtsi index 66f5ee937ad08..1dd3b2dac50cd 100644 --- a/dts/arm/st/f4/stm32f410.dtsi +++ b/dts/arm/st/f4/stm32f410.dtsi @@ -20,7 +20,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -30,7 +30,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <85 5>; status = "disabled"; }; @@ -40,7 +40,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; dmas = <&dma2 3 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma2 2 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -53,7 +53,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; dmas = <&dma1 4 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma1 3 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -66,7 +66,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <85 5>; dmas = <&dma2 6 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma2 5 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -94,7 +94,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -103,7 +103,7 @@ compatible = "st,stm32-rng"; reg = <0x40080000 0x400>; interrupts = <80 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 31U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 31)>; status = "disabled"; }; }; diff --git a/dts/arm/st/f4/stm32f411.dtsi b/dts/arm/st/f4/stm32f411.dtsi index b0dfddd40ef67..6654d294dd175 100644 --- a/dts/arm/st/f4/stm32f411.dtsi +++ b/dts/arm/st/f4/stm32f411.dtsi @@ -23,7 +23,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <85 5>; status = "disabled"; }; @@ -33,7 +33,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; dmas = <&dma2 3 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma2 2 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <84 5>; dmas = <&dma2 1 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma2 0 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -59,7 +59,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <85 5>; dmas = <&dma2 6 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma2 5 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; diff --git a/dts/arm/st/f4/stm32f412.dtsi b/dts/arm/st/f4/stm32f412.dtsi index 6bc4c31d3ce48..1264db3d1d6a1 100644 --- a/dts/arm/st/f4/stm32f412.dtsi +++ b/dts/arm/st/f4/stm32f412.dtsi @@ -36,7 +36,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; }; gpiog: gpio@40021800 { @@ -44,14 +44,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 6)>; }; }; usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -62,7 +62,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -72,7 +72,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <84 5>; status = "disabled"; }; @@ -82,7 +82,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <84 5>; dmas = <&dma2 1 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma2 0 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -204,7 +204,7 @@ compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; interrupts = <80 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; status = "disabled"; }; @@ -213,7 +213,7 @@ }; sdmmc1: sdmmc@40012c00 { - clocks = <&rcc STM32_CLOCK(APB2, 11U)>, + clocks = <&rcc STM32_CLOCK(APB2, 11)>, <&rcc STM32_SRC_CK48 SDIO_SEL(0)>; }; @@ -223,7 +223,7 @@ #size-cells = <0>; reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <92 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 1)>; status = "disabled"; }; @@ -232,7 +232,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; diff --git a/dts/arm/st/f4/stm32f413.dtsi b/dts/arm/st/f4/stm32f413.dtsi index 47b5a55f6c442..e847cedb0ec9a 100644 --- a/dts/arm/st/f4/stm32f413.dtsi +++ b/dts/arm/st/f4/stm32f413.dtsi @@ -13,7 +13,7 @@ uart4: serial@40004c00 { compatible ="st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -22,7 +22,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -31,7 +31,7 @@ uart7: serial@40007800 { compatible = "st,stm32-uart"; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; resets = <&rctl STM32_RESET(APB1, 30U)>; interrupts = <82 0>; status = "disabled"; @@ -40,7 +40,7 @@ uart8: serial@40007c00 { compatible = "st,stm32-uart"; reg = <0x40007c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; resets = <&rctl STM32_RESET(APB1, 31U)>; interrupts = <83 0>; status = "disabled"; @@ -49,7 +49,7 @@ uart9: serial@40011800 { compatible = "st,stm32-uart"; reg = <0x40011800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 6U)>; + clocks = <&rcc STM32_CLOCK(APB2, 6)>; resets = <&rctl STM32_RESET(APB2, 6U)>; interrupts = <88 0>; status = "disabled"; @@ -58,7 +58,7 @@ uart10: serial@40011c00 { compatible = "st,stm32-uart"; reg = <0x40011c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 7U)>; + clocks = <&rcc STM32_CLOCK(APB2, 7)>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <89 0>; status = "disabled"; @@ -67,7 +67,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -77,7 +77,7 @@ reg = <0x40006c00 0x400>; interrupts = <74 0>, <75 0>, <76 0>, <77 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 27U)>; + clocks = <&rcc STM32_CLOCK(APB1, 27)>; status = "disabled"; }; }; diff --git a/dts/arm/st/f4/stm32f415.dtsi b/dts/arm/st/f4/stm32f415.dtsi index 212560c2e23d8..5cf9f2f1ef919 100644 --- a/dts/arm/st/f4/stm32f415.dtsi +++ b/dts/arm/st/f4/stm32f415.dtsi @@ -13,7 +13,7 @@ cryp: cryp@50060000 { compatible = "st,stm32-cryp"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; resets = <&rctl STM32_RESET(AHB2, 4U)>; interrupts = <79 0>; status = "disabled"; diff --git a/dts/arm/st/f4/stm32f417.dtsi b/dts/arm/st/f4/stm32f417.dtsi index b6b3865fb022d..ab5412d9406a0 100644 --- a/dts/arm/st/f4/stm32f417.dtsi +++ b/dts/arm/st/f4/stm32f417.dtsi @@ -13,7 +13,7 @@ cryp: cryp@50060000 { compatible = "st,stm32-cryp"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; resets = <&rctl STM32_RESET(AHB2, 4U)>; interrupts = <79 0>; status = "disabled"; diff --git a/dts/arm/st/f4/stm32f423.dtsi b/dts/arm/st/f4/stm32f423.dtsi index b8aa21b135abe..0c42f44cc51aa 100644 --- a/dts/arm/st/f4/stm32f423.dtsi +++ b/dts/arm/st/f4/stm32f423.dtsi @@ -13,7 +13,7 @@ aes: aes@50060000 { compatible = "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; resets = <&rctl STM32_RESET(AHB2, 4U)>; interrupts = <79 0>; status = "disabled"; diff --git a/dts/arm/st/f4/stm32f427.dtsi b/dts/arm/st/f4/stm32f427.dtsi index a8f7acd546f88..5050599d5c72b 100644 --- a/dts/arm/st/f4/stm32f427.dtsi +++ b/dts/arm/st/f4/stm32f427.dtsi @@ -24,7 +24,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 9U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 9)>; }; gpiok: gpio@40022800 { @@ -32,14 +32,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 10U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 10)>; }; }; uart7: serial@40007800 { compatible = "st,stm32-uart"; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; resets = <&rctl STM32_RESET(APB1, 30U)>; interrupts = <82 0>; status = "disabled"; @@ -48,7 +48,7 @@ uart8: serial@40007c00 { compatible = "st,stm32-uart"; reg = <0x40007c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; resets = <&rctl STM32_RESET(APB1, 31U)>; interrupts = <83 0>; status = "disabled"; @@ -59,7 +59,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <84 5>; status = "disabled"; }; @@ -72,7 +72,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <85 5>; status = "disabled"; }; @@ -85,7 +85,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 21U)>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>; interrupts = <86 5>; status = "disabled"; }; @@ -93,7 +93,7 @@ fmc: memory-controller@a0000000 { compatible = "st,stm32-fmc"; reg = <0xa0000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 0)>; status = "disabled"; sdram: sdram { diff --git a/dts/arm/st/f4/stm32f429.dtsi b/dts/arm/st/f4/stm32f429.dtsi index 6409628052210..809c0a08d0673 100644 --- a/dts/arm/st/f4/stm32f429.dtsi +++ b/dts/arm/st/f4/stm32f429.dtsi @@ -14,7 +14,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -24,7 +24,7 @@ reg = <0x40016800 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_er"; - clocks = <&rcc STM32_CLOCK(APB2, 26U)>; + clocks = <&rcc STM32_CLOCK(APB2, 26)>; resets = <&rctl STM32_RESET(APB2, 26U)>; status = "disabled"; }; diff --git a/dts/arm/st/f4/stm32f437.dtsi b/dts/arm/st/f4/stm32f437.dtsi index 8e5f6510c26f8..34322274733f5 100644 --- a/dts/arm/st/f4/stm32f437.dtsi +++ b/dts/arm/st/f4/stm32f437.dtsi @@ -14,7 +14,7 @@ cryp: cryp@50060000 { compatible = "st,stm32-cryp"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; resets = <&rctl STM32_RESET(AHB2, 4U)>; interrupts = <79 0>; status = "disabled"; diff --git a/dts/arm/st/f4/stm32f439.dtsi b/dts/arm/st/f4/stm32f439.dtsi index 2144fb55ec5ae..91f775096e6b8 100644 --- a/dts/arm/st/f4/stm32f439.dtsi +++ b/dts/arm/st/f4/stm32f439.dtsi @@ -13,7 +13,7 @@ cryp: cryp@50060000 { compatible = "st,stm32-cryp"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; resets = <&rctl STM32_RESET(AHB2, 4U)>; interrupts = <79 0>; status = "disabled"; diff --git a/dts/arm/st/f4/stm32f446.dtsi b/dts/arm/st/f4/stm32f446.dtsi index a015b1d87b4f1..5103c51cc1556 100644 --- a/dts/arm/st/f4/stm32f446.dtsi +++ b/dts/arm/st/f4/stm32f446.dtsi @@ -23,7 +23,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; dmas = <&dma2 3 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL &dma2 2 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; @@ -34,7 +34,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -43,7 +43,7 @@ uart4: serial@40004c00 { compatible ="st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -52,7 +52,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -63,7 +63,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -80,7 +80,7 @@ usbotg_fs: usb@50000000 { num-bidir-endpoints = <6>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 7)>, <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; }; @@ -93,7 +93,7 @@ ram-size = <4096>; maximum-speed = "full-speed"; phys = <&otghs_fs_phy>; - clocks = <&rcc STM32_CLOCK(AHB1, 29U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 29)>, <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; status = "disabled"; }; @@ -101,7 +101,7 @@ backup_sram: memory@40024000 { compatible = "zephyr,memory-region", "st,stm32-backup-sram"; reg = <0x40024000 DT_SIZE_K(4)>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; zephyr,memory-region = "BACKUP_SRAM"; status = "disabled"; }; @@ -109,7 +109,7 @@ adc2: adc@40012100 { compatible = "st,stm32-adc"; reg = <0x40012100 0x050>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -126,7 +126,7 @@ adc3: adc@40012200 { compatible = "st,stm32-adc"; reg = <0x40012200 0x050>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>; + clocks = <&rcc STM32_CLOCK(APB2, 10)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -143,7 +143,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -151,7 +151,7 @@ fmc: memory-controller@a0000000 { compatible = "st,stm32-fmc"; reg = <0xa0000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 0)>; status = "disabled"; sdram: sdram { diff --git a/dts/arm/st/f4/stm32f469.dtsi b/dts/arm/st/f4/stm32f469.dtsi index 9daa2706b3270..709094d9a97e0 100644 --- a/dts/arm/st/f4/stm32f469.dtsi +++ b/dts/arm/st/f4/stm32f469.dtsi @@ -11,13 +11,13 @@ compatible = "st,stm32f469", "st,stm32f4", "simple-bus"; sdmmc1: sdmmc@40012c00 { - clocks = <&rcc STM32_CLOCK(APB2, 11U)>, + clocks = <&rcc STM32_CLOCK(APB2, 11)>, <&rcc STM32_SRC_SYSCLK SDMMC_SEL(1)>; }; usbotg_fs: usb@50000000 { num-bidir-endpoints = <6>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 7)>, <&rcc STM32_SRC_PLL_Q CLK48M_SEL(0)>; }; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index 9abc4d5048410..4d28054bf8e47 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -104,7 +104,7 @@ fmc: memory-controller@a0000000 { compatible = "st,stm32-fmc"; reg = <0xa0000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 0)>; status = "disabled"; sdram: sdram { @@ -170,7 +170,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; }; gpiob: gpio@40020400 { @@ -178,7 +178,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; }; gpioc: gpio@40020800 { @@ -186,7 +186,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; }; gpiod: gpio@40020C00 { @@ -194,7 +194,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020C00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 3)>; }; gpioe: gpio@40021000 { @@ -202,7 +202,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; }; gpiof: gpio@40021400 { @@ -210,7 +210,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; }; gpiog: gpio@40021800 { @@ -218,7 +218,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 6)>; }; gpioh: gpio@40021C00 { @@ -226,7 +226,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021C00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 7)>; }; gpioi: gpio@40022000 { @@ -234,7 +234,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; }; }; @@ -247,7 +247,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -255,7 +255,7 @@ usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 4U)>; + clocks = <&rcc STM32_CLOCK(APB2, 4)>; resets = <&rctl STM32_RESET(APB2, 4U)>; interrupts = <37 0>; status = "disabled"; @@ -264,7 +264,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -273,7 +273,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -282,7 +282,7 @@ uart4: serial@40004c00 { compatible ="st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -291,7 +291,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -300,7 +300,7 @@ usart6: serial@40011400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <71 0>; status = "disabled"; @@ -309,7 +309,7 @@ uart7: serial@40007800 { compatible = "st,stm32-uart"; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; resets = <&rctl STM32_RESET(APB1, 30U)>; interrupts = <82 0>; status = "disabled"; @@ -318,7 +318,7 @@ uart8: serial@40007c00 { compatible = "st,stm32-uart"; reg = <0x40007c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; resets = <&rctl STM32_RESET(APB1, 31U)>; interrupts = <83 0>; status = "disabled"; @@ -330,7 +330,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -342,7 +342,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -354,7 +354,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -365,7 +365,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 5>; status = "disabled"; }; @@ -375,7 +375,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -385,7 +385,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -395,7 +395,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <84 5>; status = "disabled"; }; @@ -405,7 +405,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <85 5>; status = "disabled"; }; @@ -415,7 +415,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; status = "disabled"; }; @@ -728,7 +728,7 @@ ram-size = <1280>; maximum-speed = "full-speed"; phys = <&otgfs_phy>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 7)>, <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; status = "disabled"; }; @@ -741,7 +741,7 @@ num-bidir-endpoints = <9>; ram-size = <4096>; maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB1, 29U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 29)>, <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; phys = <&otghs_fs_phy>; status = "disabled"; @@ -751,7 +751,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x300>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -767,7 +767,7 @@ adc1: adc@40012000 { compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012000 0x50>; - clocks = <&rcc STM32_CLOCK(APB2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB2, 8)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -784,7 +784,7 @@ adc2: adc@40012100 { compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012100 0x50>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -801,7 +801,7 @@ adc3: adc@40012200 { compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012200 0x50>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>; + clocks = <&rcc STM32_CLOCK(APB2, 10)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -818,7 +818,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -828,7 +828,7 @@ #dma-cells = <4>; reg = <0x40026000 0x400>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 21)>; status = "disabled"; }; @@ -837,7 +837,7 @@ #dma-cells = <4>; reg = <0x40026400 0x400>; interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 22)>; st,mem2mem; status = "disabled"; }; @@ -846,7 +846,7 @@ compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; interrupts = <80 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 6)>, <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; status = "disabled"; }; @@ -854,7 +854,7 @@ sdmmc1: sdmmc@40012c00 { compatible = "st,stm32-sdmmc"; reg = <0x40012c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 11U)>, + clocks = <&rcc STM32_CLOCK(APB2, 11)>, <&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>; resets = <&rctl STM32_RESET(APB2, 11U)>; interrupts = <49 0>; @@ -864,7 +864,7 @@ backup_sram: memory@40024000 { compatible = "zephyr,memory-region", "st,stm32-backup-sram"; reg = <0x40024000 DT_SIZE_K(4)>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; zephyr,memory-region = "BACKUP_SRAM"; status = "disabled"; }; @@ -875,7 +875,7 @@ #size-cells = <0>; reg = <0xa0001000 0x1000>, <0x90000000 DT_SIZE_M(256)>; interrupts = <92 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 1)>; status = "disabled"; }; }; diff --git a/dts/arm/st/f7/stm32f722.dtsi b/dts/arm/st/f7/stm32f722.dtsi index ba3b459cb7477..4a119d45081b8 100644 --- a/dts/arm/st/f7/stm32f722.dtsi +++ b/dts/arm/st/f7/stm32f722.dtsi @@ -35,7 +35,7 @@ sdmmc2: sdmmc@40011c00 { compatible = "st,stm32-sdmmc"; reg = <0x40011c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 7U)>, + clocks = <&rcc STM32_CLOCK(APB2, 7)>, <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <103 0>; diff --git a/dts/arm/st/f7/stm32f745.dtsi b/dts/arm/st/f7/stm32f745.dtsi index 999da8e962cfe..4182e49540f00 100644 --- a/dts/arm/st/f7/stm32f745.dtsi +++ b/dts/arm/st/f7/stm32f745.dtsi @@ -32,7 +32,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 9U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 9)>; }; gpiok: gpio@40022800 { @@ -40,7 +40,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 10U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 10)>; }; }; @@ -50,7 +50,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40006000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 24U)>; + clocks = <&rcc STM32_CLOCK(APB1, 24)>; interrupts = <95 0>, <96 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -61,7 +61,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 21U)>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>; interrupts = <86 5>; status = "disabled"; }; @@ -71,7 +71,7 @@ reg = <0x40006800 0x400>; interrupts = <63 0>, <64 0>, <65 0>, <66 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; + clocks = <&rcc STM32_CLOCK(APB1, 26)>; status = "disabled"; }; diff --git a/dts/arm/st/f7/stm32f746.dtsi b/dts/arm/st/f7/stm32f746.dtsi index b77ddaa2d05b2..7a5d819add739 100644 --- a/dts/arm/st/f7/stm32f746.dtsi +++ b/dts/arm/st/f7/stm32f746.dtsi @@ -16,7 +16,7 @@ reg = <0x40016800 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_err"; - clocks = <&rcc STM32_CLOCK(APB2, 26U)>; + clocks = <&rcc STM32_CLOCK(APB2, 26)>; resets = <&rctl STM32_RESET(APB2, 26U)>; status = "disabled"; }; diff --git a/dts/arm/st/f7/stm32f765.dtsi b/dts/arm/st/f7/stm32f765.dtsi index a1148f110ca2f..4720fdc0ec905 100644 --- a/dts/arm/st/f7/stm32f765.dtsi +++ b/dts/arm/st/f7/stm32f765.dtsi @@ -34,7 +34,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 9U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 9)>; }; gpiok: gpio@40022800 { @@ -42,7 +42,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40022800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 10U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 10)>; }; }; @@ -52,7 +52,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40006000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 24U)>; + clocks = <&rcc STM32_CLOCK(APB1, 24)>; interrupts = <95 0>, <96 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -63,7 +63,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 21U)>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>; interrupts = <86 5>; status = "disabled"; }; @@ -96,7 +96,7 @@ sdmmc2: sdmmc@40011c00 { compatible = "st,stm32-sdmmc"; reg = <0x40011c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 7U)>, + clocks = <&rcc STM32_CLOCK(APB2, 7)>, <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <103 0>; diff --git a/dts/arm/st/f7/stm32f767.dtsi b/dts/arm/st/f7/stm32f767.dtsi index eef8f020c807f..d7ce36ecafee7 100644 --- a/dts/arm/st/f7/stm32f767.dtsi +++ b/dts/arm/st/f7/stm32f767.dtsi @@ -17,7 +17,7 @@ reg = <0x40016800 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_err"; - clocks = <&rcc STM32_CLOCK(APB2, 26U)>; + clocks = <&rcc STM32_CLOCK(APB2, 26)>; resets = <&rctl STM32_RESET(APB2, 26U)>; status = "disabled"; }; diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi index 64cbf80e5d1cb..a332335e9db58 100644 --- a/dts/arm/st/g0/stm32g0.dtsi +++ b/dts/arm/st/g0/stm32g0.dtsi @@ -111,7 +111,7 @@ compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller"; reg = <0x40022000 0x400>; interrupts = <3 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; #address-cells = <1>; #size-cells = <1>; @@ -161,7 +161,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 0U)>; + clocks = <&rcc STM32_CLOCK(IOP, 0)>; }; gpiob: gpio@50000400 { @@ -169,7 +169,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000400 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 1U)>; + clocks = <&rcc STM32_CLOCK(IOP, 1)>; }; gpioc: gpio@50000800 { @@ -177,7 +177,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000800 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 2U)>; + clocks = <&rcc STM32_CLOCK(IOP, 2)>; }; gpiod: gpio@50000c00 { @@ -185,7 +185,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000c00 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 3U)>; + clocks = <&rcc STM32_CLOCK(IOP, 3)>; }; gpiof: gpio@50001400 { @@ -193,7 +193,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001400 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 5U)>; + clocks = <&rcc STM32_CLOCK(IOP, 5)>; }; }; @@ -201,7 +201,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <2 0>; - clocks = <&rcc STM32_CLOCK(APB1, 10U)>; + clocks = <&rcc STM32_CLOCK(APB1, 10)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <19>; @@ -229,7 +229,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 2>; status = "disabled"; }; @@ -237,7 +237,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 14)>; resets = <&rctl STM32_RESET(APB1H, 14U)>; interrupts = <27 0>; status = "disabled"; @@ -246,7 +246,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -254,7 +254,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -384,7 +384,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <23 0>; interrupt-names = "combined"; status = "disabled"; @@ -396,7 +396,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -407,7 +407,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 12)>; interrupts = <25 0>; status = "disabled"; }; @@ -417,7 +417,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 0>; status = "disabled"; }; @@ -425,7 +425,7 @@ adc1: adc@40012400 { compatible = "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 20)>; interrupts = <12 0>; status = "disabled"; #io-channel-cells = <1>; @@ -450,7 +450,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <9 0 10 0 10 0 11 0 11 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-requests = <5>; dma-offset = <0>; status = "disabled"; diff --git a/dts/arm/st/g0/stm32g031.dtsi b/dts/arm/st/g0/stm32g031.dtsi index 172d119e2a478..d63da0dedc9ec 100644 --- a/dts/arm/st/g0/stm32g031.dtsi +++ b/dts/arm/st/g0/stm32g031.dtsi @@ -14,7 +14,7 @@ lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <29 0>; status = "disabled"; diff --git a/dts/arm/st/g0/stm32g051.dtsi b/dts/arm/st/g0/stm32g051.dtsi index 6be1e56ce2338..2dd5134897322 100644 --- a/dts/arm/st/g0/stm32g051.dtsi +++ b/dts/arm/st/g0/stm32g051.dtsi @@ -69,7 +69,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/g0/stm32g070.dtsi b/dts/arm/st/g0/stm32g070.dtsi index 2985f031cc225..29c7e705e01f6 100644 --- a/dts/arm/st/g0/stm32g070.dtsi +++ b/dts/arm/st/g0/stm32g070.dtsi @@ -14,7 +14,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <29 0>; status = "disabled"; @@ -23,7 +23,7 @@ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <29 0>; status = "disabled"; diff --git a/dts/arm/st/g0/stm32g071.dtsi b/dts/arm/st/g0/stm32g071.dtsi index bb694cfb6f544..58733ee0d761b 100644 --- a/dts/arm/st/g0/stm32g071.dtsi +++ b/dts/arm/st/g0/stm32g071.dtsi @@ -15,7 +15,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <29 0>; status = "disabled"; @@ -24,7 +24,7 @@ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <29 0>; status = "disabled"; @@ -37,7 +37,7 @@ ucpd1: ucpd@4000a000 { compatible = "st,stm32-ucpd"; reg = <0x4000a000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; interrupts = <8 0>; status = "disabled"; }; @@ -45,7 +45,7 @@ ucpd2: ucpd@4000a400 { compatible = "st,stm32-ucpd"; reg = <0x4000a400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; + clocks = <&rcc STM32_CLOCK(APB1, 26)>; interrupts = <8 0>; status = "disabled"; }; diff --git a/dts/arm/st/g0/stm32g0_crypt.dtsi b/dts/arm/st/g0/stm32g0_crypt.dtsi index 70d69b0710d71..609425d1b8aa4 100644 --- a/dts/arm/st/g0/stm32g0_crypt.dtsi +++ b/dts/arm/st/g0/stm32g0_crypt.dtsi @@ -13,7 +13,7 @@ aes: aes@40026000 { compatible = "st,stm32-aes"; reg = <0x40026000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 16)>; resets = <&rctl STM32_RESET(AHB1, 16U)>; interrupts = <31 0>; status = "disabled"; @@ -23,7 +23,7 @@ compatible = "st,stm32-rng"; reg = <0x40025000 0x400>; interrupts = <31 1>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; status = "disabled"; }; }; diff --git a/dts/arm/st/g0/stm32g0b0.dtsi b/dts/arm/st/g0/stm32g0b0.dtsi index 432da38d86599..f970042066b25 100644 --- a/dts/arm/st/g0/stm32g0b0.dtsi +++ b/dts/arm/st/g0/stm32g0b0.dtsi @@ -16,14 +16,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 4U)>; + clocks = <&rcc STM32_CLOCK(IOP, 4)>; }; }; usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 8U)>; + clocks = <&rcc STM32_CLOCK(APB1, 8)>; resets = <&rctl STM32_RESET(APB1L, 8U)>; interrupts = <29 0>; status = "disabled"; @@ -32,7 +32,7 @@ usart6: serial@40013c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 9U)>; + clocks = <&rcc STM32_CLOCK(APB1, 9)>; resets = <&rctl STM32_RESET(APB1L, 9U)>; interrupts = <29 0>; status = "disabled"; @@ -62,7 +62,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40008800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -73,7 +73,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <26 3>; status = "disabled"; }; @@ -83,7 +83,7 @@ #dma-cells = <3>; reg = <0x40020400 0x400>; interrupts = <11 0 11 0 11 0 11 0 11 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-requests = <5>; dma-offset = <7>; status = "disabled"; @@ -102,7 +102,7 @@ ram-size = <2048>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 13U)>, + clocks = <&rcc STM32_CLOCK(APB1, 13)>, <&rcc STM32_SRC_HSI48 USB_SEL(0)>; status = "disabled"; }; diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi index b894ca067e6cb..deee9d378f085 100644 --- a/dts/arm/st/g0/stm32g0b1.dtsi +++ b/dts/arm/st/g0/stm32g0b1.dtsi @@ -29,7 +29,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 4U)>; + clocks = <&rcc STM32_CLOCK(IOP, 4)>; }; }; @@ -39,7 +39,7 @@ reg-names = "m_can", "message_ram"; interrupts = <21 0>, <22 0>; interrupt-names = "int0", "int1"; - clocks = <&rcc STM32_CLOCK(APB1, 12U)>; + clocks = <&rcc STM32_CLOCK(APB1, 12)>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; status = "disabled"; }; @@ -50,7 +50,7 @@ reg-names = "m_can", "message_ram"; interrupts = <21 0>, <22 0>; interrupt-names = "int0", "int1"; - clocks = <&rcc STM32_CLOCK(APB1, 12U)>; + clocks = <&rcc STM32_CLOCK(APB1, 12)>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; status = "disabled"; }; @@ -58,7 +58,7 @@ usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 8U)>; + clocks = <&rcc STM32_CLOCK(APB1, 8)>; resets = <&rctl STM32_RESET(APB1L, 8U)>; interrupts = <29 0>; status = "disabled"; @@ -67,7 +67,7 @@ usart6: serial@40013c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 9U)>; + clocks = <&rcc STM32_CLOCK(APB1, 9)>; resets = <&rctl STM32_RESET(APB1L, 9U)>; interrupts = <29 0>; status = "disabled"; @@ -76,7 +76,7 @@ lpuart2: serial@40008400 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 7U)>; + clocks = <&rcc STM32_CLOCK(APB1, 7)>; resets = <&rctl STM32_RESET(APB1L, 7U)>; interrupts = <28 0>; status = "disabled"; @@ -106,7 +106,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40008800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <26 3>; status = "disabled"; }; @@ -127,7 +127,7 @@ #dma-cells = <3>; reg = <0x40020400 0x400>; interrupts = <11 0 11 0 11 0 11 0 11 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-requests = <5>; dma-offset = <7>; status = "disabled"; @@ -147,7 +147,7 @@ ram-size = <2048>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 13U)>, + clocks = <&rcc STM32_CLOCK(APB1, 13)>, <&rcc STM32_SRC_HSI48 USB_SEL(0)>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index ec83a77392638..d4420c8bd06aa 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -106,7 +106,7 @@ adc1: adc@50000000 { compatible = "st,stm32-adc"; reg = <0x50000000 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -122,7 +122,7 @@ adc2: adc@50000100 { compatible = "st,stm32-adc"; reg = <0x50000100 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -138,7 +138,7 @@ dac1: dac@50000800 { compatible = "st,stm32-dac"; reg = <0x50000800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -146,7 +146,7 @@ dac3: dac@50001000 { compatible = "st,stm32-dac"; reg = <0x50001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 18)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -155,7 +155,7 @@ compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller"; reg = <0x40022000 0x400>; interrupts = <3 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; #address-cells = <1>; #size-cells = <1>; @@ -209,7 +209,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; }; gpiob: gpio@48000400 { @@ -217,7 +217,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; }; gpioc: gpio@48000800 { @@ -225,7 +225,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; }; gpiod: gpio@48000c00 { @@ -233,7 +233,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioe: gpio@48001000 { @@ -241,7 +241,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; gpiof: gpio@48001400 { @@ -249,7 +249,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 5)>; }; gpiog: gpio@48001800 { @@ -257,14 +257,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; }; }; usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <37 0>; status = "disabled"; @@ -273,7 +273,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -282,7 +282,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -291,7 +291,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -300,7 +300,7 @@ lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; resets = <&rctl STM32_RESET(APB1H, 0U)>; interrupts = <91 0>; status = "disabled"; @@ -315,7 +315,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -326,7 +326,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -338,7 +338,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -350,7 +350,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; interrupts = <92 0>, <93 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -362,7 +362,7 @@ #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <35 5>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; status = "disabled"; }; @@ -371,7 +371,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -381,7 +381,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -392,14 +392,14 @@ reg-names = "m_can", "message_ram"; interrupts = <21 0>, <22 0>; interrupt-names = "int0", "int1"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; status = "disabled"; }; lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -610,7 +610,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB1, 10U)>; + clocks = <&rcc STM32_CLOCK(APB1, 10)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -621,7 +621,7 @@ compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; interrupts = <90 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 26U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 26)>; status = "disabled"; }; @@ -634,7 +634,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + clocks = <&rcc STM32_CLOCK(APB1, 23)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; status = "disabled"; }; @@ -643,7 +643,7 @@ compatible = "st,stm32-dma-v2"; #dma-cells = <3>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-offset = <0>; status = "disabled"; }; @@ -652,7 +652,7 @@ compatible = "st,stm32-dma-v2"; #dma-cells = <3>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; status = "disabled"; }; @@ -661,7 +661,7 @@ #dma-cells = <3>; reg = <0x40020800 0x400>; interrupts = <94 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; dma-generators = <4>; dma-requests= <111>; status = "disabled"; @@ -670,7 +670,7 @@ ucpd1: ucpd@4000a000 { compatible = "st,stm32-ucpd"; reg = <0x4000a000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 4U)>; + clocks = <&rcc STM32_CLOCK(APB1, 4)>; interrupts = <63 0>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g473.dtsi b/dts/arm/st/g4/stm32g473.dtsi index 41f6f7fb6c33d..2ab7fbff18f44 100644 --- a/dts/arm/st/g4/stm32g473.dtsi +++ b/dts/arm/st/g4/stm32g473.dtsi @@ -31,7 +31,7 @@ adc4: adc@50000500 { compatible = "st,stm32-adc"; reg = <0x50000500 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 14U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 14)>; interrupts = <61 0>; status = "disabled"; #io-channel-cells = <1>; @@ -47,7 +47,7 @@ adc5: adc@50000600 { compatible = "st,stm32-adc"; reg = <0x50000600 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 14U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 14)>; interrupts = <62 0>; status = "disabled"; #io-channel-cells = <1>; @@ -65,7 +65,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 15U)>; + clocks = <&rcc STM32_CLOCK(APB2, 15)>; interrupts = <84 5>; status = "disabled"; }; @@ -73,7 +73,7 @@ dac2: dac@50000c00 { compatible = "st,stm32-dac"; reg = <0x50000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 17U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 17)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -81,7 +81,7 @@ dac4: dac@50001400 { compatible = "st,stm32-dac"; reg = <0x50001400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 19U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 19)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -92,7 +92,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40008400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 1)>; interrupts = <82 0>, <83 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -104,7 +104,7 @@ reg-names = "m_can", "message_ram"; interrupts = <88 0>, <89 0>; interrupt-names = "int0", "int1"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g491.dtsi b/dts/arm/st/g4/stm32g491.dtsi index 39c95a2f33c77..1534da15c8feb 100644 --- a/dts/arm/st/g4/stm32g491.dtsi +++ b/dts/arm/st/g4/stm32g491.dtsi @@ -16,7 +16,7 @@ reg-names = "m_can", "message_ram"; interrupts = <86 0>, <87 0>; interrupt-names = "int0", "int1"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; status = "disabled"; }; @@ -57,7 +57,7 @@ adc3: adc@50000400 { compatible = "st,stm32-adc"; reg = <0x50000400 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 14U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 14)>; interrupts = <47 0>; status = "disabled"; #io-channel-cells = <1>; @@ -73,7 +73,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -85,7 +85,7 @@ #size-cells = <0>; reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <95 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 8)>; status = "disabled"; }; }; diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index d90f5c06e116c..e19ca78f7bf79 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -141,7 +141,7 @@ backup_sram: memory@40036400 { compatible = "zephyr,memory-region", "st,stm32-backup-sram"; reg = <0x40036400 DT_SIZE_K(2)>; - clocks = <&rcc STM32_CLOCK(AHB1, 28U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 28)>; zephyr,memory-region = "BACKUP_SRAM"; status = "disabled"; }; @@ -191,7 +191,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; }; gpiob: gpio@42020400 { @@ -199,7 +199,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; }; gpioc: gpio@42020800 { @@ -207,7 +207,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; }; gpiod: gpio@42020c00 { @@ -215,7 +215,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioh: gpio@42021c00 { @@ -223,13 +223,13 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 7)>; }; }; lptim1: timers@44004400 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB3, 11U)>; + clocks = <&rcc STM32_CLOCK(APB3, 11)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44004400 0x400>; @@ -240,7 +240,7 @@ lptim2: timers@40009400 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40009400 0x400>; @@ -252,7 +252,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <58 0>; status = "disabled"; @@ -261,7 +261,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <59 0>; status = "disabled"; @@ -270,7 +270,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <60 0>; status = "disabled"; @@ -279,7 +279,7 @@ lpuart1: serial@44002400 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x44002400 0x400>; - clocks = <&rcc STM32_CLOCK(APB3, 6U)>; + clocks = <&rcc STM32_CLOCK(APB3, 6)>; resets = <&rctl STM32_RESET(APB3, 6U)>; interrupts = <63 0>; status = "disabled"; @@ -294,7 +294,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -302,7 +302,7 @@ dac1: dac@42028400 { compatible = "st,stm32-dac"; reg = <0x42028400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 11U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 11)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -310,7 +310,7 @@ adc1: adc@42028000 { compatible = "st,stm32-adc"; reg = <0x42028000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 10U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 10)>; interrupts = <37 0>; status = "disabled"; vref-mv = <3300>; @@ -328,7 +328,7 @@ compatible = "st,stm32-rtc"; reg = <0x44007800 0x400>; interrupts = <2 0>; - clocks = <&rcc STM32_CLOCK(APB3, 21U)>; + clocks = <&rcc STM32_CLOCK(APB3, 21)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -446,7 +446,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <51 0>, <52 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -458,7 +458,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <53 0>, <54 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -471,7 +471,7 @@ interrupt-names = "event", "error"; #address-cells = <3>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; resets = <&rctl STM32_RESET(APB1L, 23U)>; zephyr,pm-device-runtime-auto; status = "disabled"; @@ -484,7 +484,7 @@ interrupt-names = "event", "error"; #address-cells = <3>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB3, 9U)>; + clocks = <&rcc STM32_CLOCK(APB3, 9)>; resets = <&rctl STM32_RESET(APB3, 9U)>; zephyr,pm-device-runtime-auto; status = "disabled"; @@ -496,7 +496,7 @@ #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <55 5>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>, + clocks = <&rcc STM32_CLOCK(APB2, 12)>, <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; status = "disabled"; }; @@ -507,7 +507,7 @@ #size-cells = <0>; reg = <0x40003800 0x400>; interrupts = <56 5>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>, + clocks = <&rcc STM32_CLOCK(APB1, 14)>, <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; status = "disabled"; }; @@ -518,7 +518,7 @@ #size-cells = <0>; reg = <0x40003c00 0x400>; interrupts = <57 5>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>, + clocks = <&rcc STM32_CLOCK(APB1, 15)>, <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; status = "disabled"; }; @@ -529,7 +529,7 @@ reg-names = "m_can", "message_ram"; interrupts = <39 0>, <40 0>; interrupt-names = "int0", "int1"; - clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 9)>; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; status = "disabled"; }; @@ -537,7 +537,7 @@ rng: rng@420c0800 { compatible = "st,stm32-rng"; reg = <0x420c0800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 18)>; interrupts = <114 0>; nist-config = <0xf00d00>; health-test-config = <0xaac7>; @@ -572,7 +572,7 @@ #dma-cells = <3>; reg = <0x40020000 0x1000>; interrupts = <27 0 28 0 29 0 30 0 31 0 32 0 33 0 34 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-channels = <8>; dma-requests = <140>; dma-offset = <0>; @@ -584,7 +584,7 @@ #dma-cells = <3>; reg = <0x40021000 0x1000>; interrupts = <90 0 91 0 92 0 93 0 94 0 95 0 96 0 97 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-channels = <8>; dma-requests = <140>; dma-offset = <8>; @@ -596,7 +596,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>, + clocks = <&rcc STM32_CLOCK(APB2, 12)>, <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX |STM32_DMA_16BITS | \ STM32_DMA_PRIORITY_HIGH) @@ -612,7 +612,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>, + clocks = <&rcc STM32_CLOCK(APB1, 14)>, <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ STM32_DMA_PRIORITY_HIGH) @@ -628,7 +628,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>, + clocks = <&rcc STM32_CLOCK(APB1, 15)>, <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ STM32_DMA_PRIORITY_HIGH) @@ -672,7 +672,7 @@ ram-size = <2048>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB2, 24U)>, + clocks = <&rcc STM32_CLOCK(APB2, 24)>, <&rcc STM32_SRC_HSI48 USB_SEL(3)>; status = "disabled"; }; @@ -682,7 +682,7 @@ reg = <0x40008c00 0x400>; interrupts = <113 0>; interrupt-names = "digi_temp"; - clocks = <&rcc STM32_CLOCK(APB1_2, 3U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 3)>; status = "disabled"; }; }; diff --git a/dts/arm/st/h5/stm32h523.dtsi b/dts/arm/st/h5/stm32h523.dtsi new file mode 100644 index 0000000000000..5e18e8a5524a0 --- /dev/null +++ b/dts/arm/st/h5/stm32h523.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Filip Stojanovic + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/ { + soc { + compatible = "st,stm32h523", "st,stm32h5", "simple-bus"; + + gpiof: gpio@42021400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42021400 0x400>; + clocks = <&rcc STM32_CLOCK(AHB2, 7)>; + }; + + fmc: memory-controller@47000400 { + compatible = "st,stm32-fmc"; + reg = <0x47000400 0x400>; + clocks = <&rcc STM32_CLOCK(AHB4, 16)>; + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/st/h5/stm32h523Xe.dtsi b/dts/arm/st/h5/stm32h523Xe.dtsi new file mode 100644 index 0000000000000..fc122088d298c --- /dev/null +++ b/dts/arm/st/h5/stm32h523Xe.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Filip Stojanovic + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +/ { + sram1: memory@20000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(128)>; + zephyr,memory-region = "SRAM1"; + }; + + sram2: memory@20040000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20040000 DT_SIZE_K(80)>; + zephyr,memory-region = "SRAM2"; + }; + + sram3: memory@20050000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20050000 DT_SIZE_K(64)>; + zephyr,memory-region = "SRAM3"; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(512)>; + }; + }; + }; +}; diff --git a/dts/arm/st/h5/stm32h533.dtsi b/dts/arm/st/h5/stm32h533.dtsi index a3a4c69d63f91..fc07f895adaed 100644 --- a/dts/arm/st/h5/stm32h533.dtsi +++ b/dts/arm/st/h5/stm32h533.dtsi @@ -3,25 +3,11 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include + +#include / { soc { compatible = "st,stm32h533", "st,stm32h5", "simple-bus"; - - gpiof: gpio@42021400 { - compatible = "st,stm32-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x42021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; - }; - - fmc: memory-controller@47000400 { - compatible = "st,stm32-fmc"; - reg = <0x47000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 16U)>; - status = "disabled"; - }; }; }; diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index 1d238f87439df..e8b521caa908b 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -29,7 +29,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; gpiof: gpio@42021400 { @@ -37,7 +37,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 5)>; }; gpiog: gpio@42021800 { @@ -45,7 +45,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; }; gpioi: gpio@42022000 { @@ -53,7 +53,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 8)>; }; }; @@ -81,7 +81,7 @@ lptim3: timers@44004800 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB3, 12U)>; + clocks = <&rcc STM32_CLOCK(APB3, 12)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44004800 0x400>; @@ -92,7 +92,7 @@ lptim4: timers@44004c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB3, 13U)>; + clocks = <&rcc STM32_CLOCK(APB3, 13)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44004c00 0x400>; @@ -103,7 +103,7 @@ lptim5: timers@44005000 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB3, 14U)>; + clocks = <&rcc STM32_CLOCK(APB3, 14)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44005000 0x400>; @@ -114,7 +114,7 @@ lptim6: timers@44005400 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB3, 15U)>; + clocks = <&rcc STM32_CLOCK(APB3, 15)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44005400 0x400>; @@ -126,7 +126,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <61 0>; status = "disabled"; @@ -135,7 +135,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <62 0>; status = "disabled"; @@ -144,7 +144,7 @@ uart7: serial@40007800 { compatible = "st,stm32-uart"; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; resets = <&rctl STM32_RESET(APB1L, 30U)>; interrupts = <98 0>; status = "disabled"; @@ -153,7 +153,7 @@ uart8: serial@40007c00 { compatible = "st,stm32-uart"; reg = <0x40007c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; resets = <&rctl STM32_RESET(APB1L, 31U)>; interrupts = <99 0>; status = "disabled"; @@ -162,7 +162,7 @@ uart9: serial@40008000 { compatible = "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; resets = <&rctl STM32_RESET(APB1H, 0U)>; interrupts = <100 0>; status = "disabled"; @@ -171,7 +171,7 @@ usart6: serial@40006400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40006400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; resets = <&rctl STM32_RESET(APB1L, 25U)>; interrupts = <85 0>; status = "disabled"; @@ -180,7 +180,7 @@ usart10: serial@40006800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40006800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; + clocks = <&rcc STM32_CLOCK(APB1, 26)>; resets = <&rctl STM32_RESET(APB1L, 26U)>; interrupts = <86 0>; status = "disabled"; @@ -189,7 +189,7 @@ usart11: serial@40006c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40006c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 27U)>; + clocks = <&rcc STM32_CLOCK(APB1, 27)>; resets = <&rctl STM32_RESET(APB1L, 27U)>; interrupts = <87 0>; status = "disabled"; @@ -198,7 +198,7 @@ uart12: serial@40008400 { compatible = "st,stm32-uart"; reg = <0x40008400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 1)>; resets = <&rctl STM32_RESET(APB1H, 1U)>; interrupts = <101 0>; status = "disabled"; @@ -210,7 +210,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x44002800 0x400>; - clocks = <&rcc STM32_CLOCK(APB3, 7U)>; + clocks = <&rcc STM32_CLOCK(APB3, 7)>; interrupts = <80 0>, <81 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -222,7 +222,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x44002c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB3, 8U)>; + clocks = <&rcc STM32_CLOCK(APB3, 8)>; interrupts = <125 0>, <126 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -234,7 +234,7 @@ #size-cells = <0>; reg = <0x40014c00 0x400>; interrupts = <82 5>; - clocks = <&rcc STM32_CLOCK(APB2, 19U)>; + clocks = <&rcc STM32_CLOCK(APB2, 19)>; status = "disabled"; }; @@ -244,7 +244,7 @@ #size-cells = <0>; reg = <0x44002000 0x400>; interrupts = <83 5>; - clocks = <&rcc STM32_CLOCK(APB3, 5U)>; + clocks = <&rcc STM32_CLOCK(APB3, 5)>; status = "disabled"; }; @@ -254,7 +254,7 @@ #size-cells = <0>; reg = <0x40015000 0x400>; interrupts = <84 5>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; status = "disabled"; }; @@ -263,7 +263,7 @@ reg = <0x47001400 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <78 0>; clock-names = "xspix", "xspi-ker"; - clocks = <&rcc STM32_CLOCK(AHB4, 20U)>, + clocks = <&rcc STM32_CLOCK(AHB4, 20)>, <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>; #address-cells = <1>; #size-cells = <0>; @@ -273,7 +273,7 @@ adc2: adc@42028100 { compatible = "st,stm32-adc"; reg = <0x42028100 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 10U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 10)>; interrupts = <69 0>; status = "disabled"; vref-mv = <3300>; @@ -483,7 +483,7 @@ aes: aes@420c0000 { compatible = "st,stm32-aes"; reg = <0x420c0000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <116 0>; status = "disabled"; @@ -496,7 +496,7 @@ interrupts = <109 0>, <110 0>; interrupt-names = "int0", "int1"; /* common clock FDCAN 1 & 2 */ - clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 9)>; bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; status = "disabled"; }; @@ -504,7 +504,7 @@ sdmmc1: sdmmc@46008000 { compatible = "st,stm32-sdmmc"; reg = <0x46008000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 11U)>, + clocks = <&rcc STM32_CLOCK(AHB4, 11)>, <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>; resets = <&rctl STM32_RESET(AHB4, 11U)>; interrupts = <79 0>; @@ -514,7 +514,7 @@ fmc: memory-controller@47000400 { compatible = "st,stm32-fmc"; reg = <0x47000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 16)>; status = "disabled"; }; }; diff --git a/dts/arm/st/h5/stm32h563.dtsi b/dts/arm/st/h5/stm32h563.dtsi index 0b23250565cb8..b5111a48bc08d 100644 --- a/dts/arm/st/h5/stm32h563.dtsi +++ b/dts/arm/st/h5/stm32h563.dtsi @@ -13,7 +13,7 @@ sdmmc2: sdmmc@46008c00 { compatible = "st,stm32-sdmmc"; reg = <0x46008c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 12U)>, + clocks = <&rcc STM32_CLOCK(AHB4, 12)>, <&rcc STM32_SRC_PLL1_Q SDMMC2_SEL(0)>; resets = <&rctl STM32_RESET(AHB4, 12U)>; interrupts = <102 0>; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 3a4eb61e9842e..d2cc6d02fccc0 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -189,7 +189,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 0)>; }; gpiob: gpio@58020400 { @@ -197,7 +197,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 1)>; }; gpioc: gpio@58020800 { @@ -205,7 +205,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 2)>; }; gpiod: gpio@58020C00 { @@ -213,7 +213,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020C00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 3)>; }; gpioe: gpio@58021000 { @@ -221,7 +221,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 4)>; }; gpiof: gpio@58021400 { @@ -229,7 +229,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 5)>; }; gpiog: gpio@58021800 { @@ -237,7 +237,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 6)>; }; gpioh: gpio@58021C00 { @@ -245,7 +245,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021C00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 7)>; }; gpioi: gpio@58022000 { @@ -253,7 +253,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 8)>; }; gpioj: gpio@58022400 { @@ -261,7 +261,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58022400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 9U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 9)>; }; gpiok: gpio@58022800 { @@ -269,7 +269,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58022800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 10U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 10)>; }; }; @@ -282,7 +282,7 @@ wwdg: wwdg1: watchdog@50003000 { compatible = "st,stm32-window-watchdog"; reg = <0x50003000 0x1000>; - clocks = <&rcc STM32_CLOCK(APB3, 6U)>; + clocks = <&rcc STM32_CLOCK(APB3, 6)>; interrupts = <0 7>; status = "disabled"; }; @@ -290,7 +290,7 @@ usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 4U)>; + clocks = <&rcc STM32_CLOCK(APB2, 4)>; resets = <&rctl STM32_RESET(APB2, 4U)>; interrupts = <37 0>; status = "disabled"; @@ -298,7 +298,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -306,7 +306,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -314,7 +314,7 @@ uart4: serial@40004c00 { compatible ="st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -322,7 +322,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -330,7 +330,7 @@ usart6: serial@40011400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <71 0>; status = "disabled"; @@ -338,7 +338,7 @@ uart7: serial@40007800 { compatible = "st,stm32-uart"; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; resets = <&rctl STM32_RESET(APB1L, 30U)>; interrupts = <82 0>; status = "disabled"; @@ -346,7 +346,7 @@ uart8: serial@40007c00 { compatible = "st,stm32-uart"; reg = <0x40007c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; resets = <&rctl STM32_RESET(APB1L, 31U)>; interrupts = <83 0>; status = "disabled"; @@ -355,7 +355,7 @@ lpuart1: serial@58000c00 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x58000c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB4, 3U)>; + clocks = <&rcc STM32_CLOCK(APB4, 3)>; resets = <&rctl STM32_RESET(APB4, 3U)>; interrupts = <142 0>; status = "disabled"; @@ -365,7 +365,7 @@ compatible = "st,stm32-rtc"; reg = <0x58004000 0x400>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB4, 16U)>; + clocks = <&rcc STM32_CLOCK(APB4, 16)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -378,7 +378,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -390,7 +390,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -402,7 +402,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -414,7 +414,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x58001c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB4, 7U)>; + clocks = <&rcc STM32_CLOCK(APB4, 7)>; interrupts = <95 0>, <96 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -425,7 +425,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>, + clocks = <&rcc STM32_CLOCK(APB2, 12)>, <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; interrupts = <35 0>; status = "disabled"; @@ -436,7 +436,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>, + clocks = <&rcc STM32_CLOCK(APB1, 14)>, <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; interrupts = <36 0>; status = "disabled"; @@ -447,7 +447,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>, + clocks = <&rcc STM32_CLOCK(APB1, 15)>, <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; interrupts = <51 0>; status = "disabled"; @@ -458,7 +458,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <84 0>; status = "disabled"; }; @@ -468,7 +468,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <85 0>; status = "disabled"; }; @@ -478,7 +478,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x58001400 0x400>; - clocks = <&rcc STM32_CLOCK(APB4, 5U)>; + clocks = <&rcc STM32_CLOCK(APB4, 5)>; interrupts = <86 0>; status = "disabled"; }; @@ -488,7 +488,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>, + clocks = <&rcc STM32_CLOCK(APB2, 12)>, <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; dmas = <&dmamux1 0 38 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH) &dmamux1 1 37 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; @@ -502,7 +502,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>, + clocks = <&rcc STM32_CLOCK(APB1, 14)>, <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; dmas = <&dmamux1 0 40 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH) &dmamux1 1 39 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; @@ -516,7 +516,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>, + clocks = <&rcc STM32_CLOCK(APB1, 15)>, <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; dmas = <&dmamux1 0 62 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH) &dmamux1 1 61 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; @@ -529,7 +529,7 @@ compatible = "st,stm32h7-fdcan"; reg = <0x4000a000 0x400>, <0x4000ac00 0x350>; reg-names = "m_can", "message_ram"; - clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 8)>; interrupts = <19 0>, <21 0>, <63 0>; interrupt-names = "int0", "int1", "calib"; bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; @@ -540,7 +540,7 @@ compatible = "st,stm32h7-fdcan"; reg = <0x4000a400 0x400>, <0x4000ac00 0x6a0>; reg-names = "m_can", "message_ram"; - clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 8)>; interrupts = <20 0>, <22 0>, <63 0>; interrupt-names = "int0", "int1", "calib"; bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; @@ -849,7 +849,7 @@ lptim1: timers@40002400 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 9U)>; + clocks = <&rcc STM32_CLOCK(APB1, 9)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40002400 0x400>; @@ -868,7 +868,7 @@ adc1: adc@40022000 { compatible = "st,stm32-adc"; reg = <0x40022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -885,7 +885,7 @@ adc2: adc@40022100 { compatible = "st,stm32-adc"; reg = <0x40022100 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -903,7 +903,7 @@ adc1_2: adc@40022300 { compatible = "st,stm32-adc"; reg = <0x40022300 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -920,7 +920,7 @@ adc3: adc@58026000 { compatible = "st,stm32-adc"; reg = <0x58026000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 24U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 24)>; interrupts = <127 0>; status = "disabled"; #io-channel-cells = <1>; @@ -937,7 +937,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -948,7 +948,7 @@ reg = <0x40020000 0x400>; interrupts = <11 0>, <12 0>, <13 0>, <14 0>, <15 0>, <16 0>, <17 0>, <47 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; st,mem2mem; dma-offset = <0>; dma-requests = <8>; @@ -961,7 +961,7 @@ reg = <0x40020400 0x400>; interrupts = <56 0>, <57 0>, <58 0>, <59 0>, <60 0>, <68 0>, <69 0>, <70 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; st,mem2mem; dma-offset = <8>; dma-requests = <8>; @@ -974,7 +974,7 @@ reg = <0x58025400 0x400>; interrupts = <129 0>, <130 0>, <131 0>, <132 0>, <133 0>, <134 0>, <135 0>, <136 0>; - clocks = <&rcc STM32_CLOCK(AHB4, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 21)>; st,mem2mem; dma-offset = <0>; dma-requests = <8>; @@ -987,7 +987,7 @@ reg = <0x40020800 0x400>; interrupts = <102 0>; /* dmamux1 has no dedicated clock, so we enable dma1 clock */ - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-channels = <16>; dma-generators = <8>; status = "disabled"; @@ -1003,7 +1003,7 @@ reg = <0x58025800 0x400>; interrupts = <128 0>; /* dmamux2 has no dedicated clock, so we enable bdma clock */ - clocks = <&rcc STM32_CLOCK(AHB4, 21U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 21)>; dma-channels = <8>; dma-generators = <8>; status = "disabled"; @@ -1016,7 +1016,7 @@ rng: rng@48021800 { compatible = "st,stm32-rng"; reg = <0x48021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; interrupts = <80 0>; status = "disabled"; }; @@ -1024,7 +1024,7 @@ sdmmc1: sdmmc@52007000 { compatible = "st,stm32-sdmmc"; reg = <0x52007000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 16U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 16)>, <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; resets = <&rctl STM32_RESET(AHB3, 16U)>; interrupts = <49 0>; @@ -1034,7 +1034,7 @@ sdmmc2: sdmmc@48022400 { compatible = "st,stm32-sdmmc"; reg = <0x48022400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 9U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 9)>, <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; resets = <&rctl STM32_RESET(AHB2, 9U)>; interrupts = <124 0>; @@ -1067,7 +1067,7 @@ fmc: memory-controller@52004000 { compatible = "st,stm32h7-fmc"; reg = <0x52004000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 12U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 12)>; status = "disabled"; sdram: sdram { @@ -1081,7 +1081,7 @@ backup_sram: memory@38800000 { compatible = "zephyr,memory-region", "st,stm32-backup-sram"; reg = <0x38800000 DT_SIZE_K(4)>; - clocks = <&rcc STM32_CLOCK(AHB4, 28U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 28)>; zephyr,memory-region = "BACKUP_SRAM"; status = "disabled"; }; @@ -1092,7 +1092,7 @@ #size-cells = <0>; reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>; interrupts = <92 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 14U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 14)>; status = "disabled"; }; @@ -1101,7 +1101,7 @@ reg = <0x48020000 0x400>; interrupts = <78 0>; interrupt-names = "dcmi"; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi index 8a6aaf0079021..2912f74846125 100644 --- a/dts/arm/st/h7/stm32h723.dtsi +++ b/dts/arm/st/h7/stm32h723.dtsi @@ -27,7 +27,7 @@ uart9: serial@40011800 { compatible = "st,stm32-uart"; reg = <0x40011800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 6U)>; + clocks = <&rcc STM32_CLOCK(APB2, 6)>; resets = <&rctl STM32_RESET(APB2, 6U)>; interrupts = <155 0>; status = "disabled"; @@ -36,7 +36,7 @@ usart10: serial@40011c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 7U)>; + clocks = <&rcc STM32_CLOCK(APB2, 7)>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <156 0>; status = "disabled"; @@ -77,7 +77,7 @@ num-bidir-endpoints = <9>; ram-size = ; maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB1, 25U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 25)>, <&rcc STM32_SRC_HSI48 USB_SEL(3)>; phys = <&otghs_fs_phy>; status = "disabled"; @@ -88,7 +88,7 @@ reg = <0x50001000 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_er"; - clocks = <&rcc STM32_CLOCK(APB3, 3U)>; + clocks = <&rcc STM32_CLOCK(APB3, 3)>; resets = <&rctl STM32_RESET(APB3, 3U)>; status = "disabled"; }; @@ -98,7 +98,7 @@ reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>; interrupts = <92 0>; clock-names = "ospix", "ospi-ker"; - clocks = <&rcc STM32_CLOCK(AHB3, 14U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 14)>, <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; @@ -110,7 +110,7 @@ reg = <0x5200a000 0x1000>, <0x70000000 DT_SIZE_M(256)>; interrupts = <150 0>; clock-names = "ospix", "ospi-ker"; - clocks = <&rcc STM32_CLOCK(AHB3, 19U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 19)>, <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; @@ -121,7 +121,7 @@ compatible = "st,stm32h7-fdcan"; reg = <0x4000d400 0x400>, <0x4000ac00 0x9f0>; reg-names = "m_can", "message_ram"; - clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 8)>; interrupts = <159 0>, <160 0>, <63 0>; interrupt-names = "int0", "int1", "calib"; bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>; @@ -187,7 +187,7 @@ reg = <0x58006800 0x400>; interrupts = <147 0>; interrupt-names = "digi_temp"; - clocks = <&rcc STM32_CLOCK(APB4, 26U)>; + clocks = <&rcc STM32_CLOCK(APB4, 26)>; status = "disabled"; }; }; diff --git a/dts/arm/st/h7/stm32h730.dtsi b/dts/arm/st/h7/stm32h730.dtsi index 1d73fe7f52434..fdc3d22d97256 100644 --- a/dts/arm/st/h7/stm32h730.dtsi +++ b/dts/arm/st/h7/stm32h730.dtsi @@ -13,7 +13,7 @@ cryp: cryp@48021000 { compatible = "st,stm32-cryp"; reg = <0x48021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; resets = <&rctl STM32_RESET(AHB2, 4U)>; interrupts = <79 0>; status = "disabled"; diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi index 0eb82817506d7..8e29920791be3 100644 --- a/dts/arm/st/h7/stm32h745.dtsi +++ b/dts/arm/st/h7/stm32h745.dtsi @@ -41,7 +41,7 @@ reg = <0x50001000 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_er"; - clocks = <&rcc STM32_CLOCK(APB3, 3U)>; + clocks = <&rcc STM32_CLOCK(APB3, 3)>; resets = <&rctl STM32_RESET(APB3, 3U)>; status = "disabled"; }; @@ -54,7 +54,7 @@ num-bidir-endpoints = <9>; ram-size = <4096>; maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB1, 25U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 25)>, <&rcc STM32_SRC_HSI48 USB_SEL(3)>; phys = <&otghs_fs_phy>; status = "disabled"; @@ -68,7 +68,7 @@ num-bidir-endpoints = <9>; ram-size = <4096>; maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB1, 27U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 27)>, <&rcc STM32_SRC_HSI48 USB_SEL(3)>; phys = <&otghs_fs_phy>; status = "disabled"; diff --git a/dts/arm/st/h7/stm32h747.dtsi b/dts/arm/st/h7/stm32h747.dtsi index 864dda873ba58..501f2a2f44de4 100644 --- a/dts/arm/st/h7/stm32h747.dtsi +++ b/dts/arm/st/h7/stm32h747.dtsi @@ -17,7 +17,7 @@ #size-cells = <0>; reg = <0x50000000 0x1000>; clock-names = "dsiclk", "refclk", "pixelclk"; - clocks = <&rcc STM32_CLOCK(APB3, 4U)>, + clocks = <&rcc STM32_CLOCK(APB3, 4)>, <&rcc STM32_SRC_HSE NO_SEL>, <&rcc STM32_SRC_PLL3_R NO_SEL>; resets = <&rctl STM32_RESET(APB3, 4U)>; diff --git a/dts/arm/st/h7/stm32h755.dtsi b/dts/arm/st/h7/stm32h755.dtsi index 1293ec2b89cbf..34103ef2b264c 100644 --- a/dts/arm/st/h7/stm32h755.dtsi +++ b/dts/arm/st/h7/stm32h755.dtsi @@ -14,7 +14,7 @@ cryp: cryp@48021000 { compatible = "st,stm32-cryp"; reg = <0x48021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; interrupts = <79 0>; status = "disabled"; }; @@ -22,7 +22,7 @@ hash: cryp@48021400 { compatible = "st,stm32-cryp"; reg = <0x48021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 5)>; interrupts = <80 0>; status = "disabled"; }; diff --git a/dts/arm/st/h7/stm32h757.dtsi b/dts/arm/st/h7/stm32h757.dtsi index 09f038dd9b149..2d02e456de44b 100644 --- a/dts/arm/st/h7/stm32h757.dtsi +++ b/dts/arm/st/h7/stm32h757.dtsi @@ -13,7 +13,7 @@ cryp: cryp@48021000 { compatible = "st,stm32-cryp"; reg = <0x48021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; interrupts = <79 0>; status = "disabled"; }; diff --git a/dts/arm/st/h7/stm32h7_dualcore.dtsi b/dts/arm/st/h7/stm32h7_dualcore.dtsi index 081c70519f414..e84166fe941b9 100644 --- a/dts/arm/st/h7/stm32h7_dualcore.dtsi +++ b/dts/arm/st/h7/stm32h7_dualcore.dtsi @@ -19,7 +19,7 @@ mailbox: mailbox@58026400 { compatible = "st,stm32-hsem-mailbox", "st,mbox-stm32-hsem"; reg = <0x58026400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 25U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 25)>; #mbox-cells = <1>; status = "disabled"; }; @@ -27,5 +27,5 @@ }; &flash { - clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 8)>; }; diff --git a/dts/arm/st/h7/stm32h7a3.dtsi b/dts/arm/st/h7/stm32h7a3.dtsi index a93d669d46028..f1307c9d14fd7 100644 --- a/dts/arm/st/h7/stm32h7a3.dtsi +++ b/dts/arm/st/h7/stm32h7a3.dtsi @@ -40,7 +40,7 @@ num-bidir-endpoints = <9>; ram-size = <4096>; maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB1, 25U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 25)>, <&rcc STM32_SRC_HSI48 USB_SEL(3)>; phys = <&otghs_fs_phy>; status = "disabled"; @@ -51,7 +51,7 @@ reg = <0x50001000 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_er"; - clocks = <&rcc STM32_CLOCK(APB3, 3U)>; + clocks = <&rcc STM32_CLOCK(APB3, 3)>; resets = <&rctl STM32_RESET(APB3, 3U)>; status = "disabled"; }; @@ -61,7 +61,7 @@ reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>; interrupts = <92 0>; clock-names = "ospix", "ospi-ker"; - clocks = <&rcc STM32_CLOCK(AHB3, 14U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 14)>, <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; @@ -73,7 +73,7 @@ reg = <0x5200a000 0x1000>, <0x70000000 DT_SIZE_M(256)>; interrupts = <150 0>; clock-names = "ospix", "ospi-ker"; - clocks = <&rcc STM32_CLOCK(AHB3, 19U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 19)>, <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; @@ -85,7 +85,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x58001400 0x400>; - clocks = <&rcc STM32_CLOCK(APB4, 5U)>, + clocks = <&rcc STM32_CLOCK(APB4, 5)>, <&rcc STM32_SRC_PLL1_Q SPI6_SEL(0)>; dmas = <&dmamux2 0 12 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH) &dmamux2 1 11 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; @@ -105,7 +105,7 @@ reg = <0x58006800 0x400>; interrupts = <147 0>; interrupt-names = "digi_temp"; - clocks = <&rcc STM32_CLOCK(APB4, 26U)>; + clocks = <&rcc STM32_CLOCK(APB4, 26)>; status = "disabled"; }; }; diff --git a/dts/arm/st/h7/stm32h7b0.dtsi b/dts/arm/st/h7/stm32h7b0.dtsi index 2ea3a18e79db9..2a3f1f9431af4 100644 --- a/dts/arm/st/h7/stm32h7b0.dtsi +++ b/dts/arm/st/h7/stm32h7b0.dtsi @@ -18,7 +18,7 @@ cryp: cryp@48021000 { compatible = "st,stm32-cryp"; reg = <0x48021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; resets = <&rctl STM32_RESET(AHB2, 4U)>; interrupts = <79 0>; interrupt-names = "cryp"; diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index a74a48246db06..878e4f5969e1c 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -180,7 +180,7 @@ compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; reg = <0x52002000 0x400>; interrupts = <8 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 8)>; #address-cells = <1>; #size-cells = <1>; @@ -239,7 +239,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 0)>; }; gpiob: gpio@58020400 { @@ -247,7 +247,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 1)>; }; gpioc: gpio@58020800 { @@ -255,7 +255,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 2)>; }; gpiod: gpio@58020C00 { @@ -263,7 +263,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58020C00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 3)>; }; gpioe: gpio@58021000 { @@ -271,7 +271,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 4)>; }; gpiof: gpio@58021400 { @@ -279,7 +279,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 5)>; }; gpiog: gpio@58021800 { @@ -287,7 +287,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 6)>; }; gpioh: gpio@58021c00 { @@ -295,7 +295,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58021c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 7)>; }; gpiom: gpio@58023000 { @@ -303,7 +303,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58023000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 12U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 12)>; }; gpion: gpio@58023400 { @@ -311,7 +311,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58023400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 13)>; }; gpioo: gpio@58023800 { @@ -319,7 +319,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58023800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 14U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 14)>; }; gpiop: gpio@58023c00 { @@ -327,14 +327,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x58023c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 15U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 15)>; }; }; usart1: serial@42001000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x42001000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 4U)>; + clocks = <&rcc STM32_CLOCK(APB2, 4)>; resets = <&rctl STM32_RESET(APB2, 4U)>; interrupts = <82 0>; status = "disabled"; @@ -342,7 +342,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <83 0>; status = "disabled"; @@ -350,7 +350,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <84 0>; status = "disabled"; @@ -358,7 +358,7 @@ uart4: serial@40004c00 { compatible ="st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <85 0>; status = "disabled"; @@ -366,7 +366,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <86 0>; status = "disabled"; @@ -374,7 +374,7 @@ uart7: serial@40007800 { compatible = "st,stm32-uart"; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; resets = <&rctl STM32_RESET(APB1L, 30U)>; interrupts = <87 0>; status = "disabled"; @@ -382,7 +382,7 @@ uart8: serial@40007c00 { compatible = "st,stm32-uart"; reg = <0x40007c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; resets = <&rctl STM32_RESET(APB1L, 31U)>; interrupts = <88 0>; status = "disabled"; @@ -391,7 +391,7 @@ lpuart1: serial@58000c00 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x58000c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB4, 3U)>; + clocks = <&rcc STM32_CLOCK(APB4, 3)>; resets = <&rctl STM32_RESET(APB4, 3U)>; interrupts = <131 0>; status = "disabled"; @@ -403,7 +403,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <76 0>, <77 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -415,7 +415,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <78 0>, <79 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -427,7 +427,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <80 0>, <81 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -438,7 +438,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x42003000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>, + clocks = <&rcc STM32_CLOCK(APB2, 12)>, <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; interrupts = <58 0>; status = "disabled"; @@ -449,7 +449,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>, + clocks = <&rcc STM32_CLOCK(APB1, 14)>, <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; interrupts = <59 0>; status = "disabled"; @@ -460,7 +460,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>, + clocks = <&rcc STM32_CLOCK(APB1, 15)>, <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; interrupts = <60 0>; status = "disabled"; @@ -471,7 +471,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x42003400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; interrupts = <61 0>; status = "disabled"; }; @@ -481,7 +481,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x42005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB2, 20)>; interrupts = <62 0>; status = "disabled"; }; @@ -491,7 +491,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>, + clocks = <&rcc STM32_CLOCK(APB2, 12)>, <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; interrupts = <35 3>; status = "disabled"; @@ -502,7 +502,7 @@ reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>; interrupts = <105 0>; clock-names = "xspix"; - clocks = <&rcc STM32_CLOCK(AHB5, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB5, 5)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -513,7 +513,7 @@ reg = <0x5200a000 0x1000>, <0x70000000 DT_SIZE_M(256)>; interrupts = <106 0>; clock-names = "xspix"; - clocks = <&rcc STM32_CLOCK(AHB5, 12U)>; + clocks = <&rcc STM32_CLOCK(AHB5, 12)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -529,7 +529,7 @@ wwdg: wwdg1: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002c00 0x1000>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <4 7>; status = "disabled"; }; @@ -766,7 +766,7 @@ lptim1: timers@40002400 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 9U)>; + clocks = <&rcc STM32_CLOCK(APB1, 9)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40002400 0x400>; @@ -778,7 +778,7 @@ adc1: adc@40022000 { compatible = "st,stm32-adc"; reg = <0x40022000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; interrupts = <38 0>; status = "disabled"; #io-channel-cells = <1>; @@ -794,7 +794,7 @@ adc2: adc@40022100 { compatible = "st,stm32-adc"; reg = <0x40022100 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; interrupts = <38 0>; status = "disabled"; #io-channel-cells = <1>; @@ -810,7 +810,7 @@ rng: rng@48020000 { compatible = "st,stm32-rng"; reg = <0x48020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 0)>; interrupts = <37 0>; status = "disabled"; }; @@ -824,7 +824,7 @@ ram-size = <1280>; maximum-speed = "full-speed"; phys = <&otgfs_phy>; - clocks = <&rcc STM32_CLOCK(AHB1, 27U)>, + clocks = <&rcc STM32_CLOCK(AHB1, 27)>, <&rcc STM32_SRC_HSI48 OTGFS_SEL(0)>; status = "disabled"; }; diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index bcadfd5c4feae..0a1006ca20b67 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -96,7 +96,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <2 0>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -162,7 +162,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 0U)>; + clocks = <&rcc STM32_CLOCK(IOP, 0)>; }; gpiob: gpio@50000400 { @@ -170,7 +170,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000400 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 1U)>; + clocks = <&rcc STM32_CLOCK(IOP, 1)>; }; gpioc: gpio@50000800 { @@ -178,7 +178,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000800 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 2U)>; + clocks = <&rcc STM32_CLOCK(IOP, 2)>; }; gpiod: gpio@50000c00 { @@ -186,7 +186,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000c00 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 3U)>; + clocks = <&rcc STM32_CLOCK(IOP, 3)>; }; gpioh: gpio@50001c00 { @@ -194,7 +194,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001c00 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 7U)>; + clocks = <&rcc STM32_CLOCK(IOP, 7)>; }; }; @@ -207,7 +207,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 2>; status = "disabled"; }; @@ -215,7 +215,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -224,7 +224,7 @@ lpuart1: serial@40004800 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <29 0>; status = "disabled"; @@ -236,7 +236,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <23 0>; interrupt-names = "combined"; status = "disabled"; @@ -247,7 +247,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <25 3>; status = "disabled"; }; @@ -300,7 +300,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -312,7 +312,7 @@ adc1: adc@40012400 { compatible = "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <12 0>; status = "disabled"; #io-channel-cells = <1>; @@ -331,7 +331,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; status = "disabled"; }; diff --git a/dts/arm/st/l0/stm32l031.dtsi b/dts/arm/st/l0/stm32l031.dtsi index e1e61b25ed1d7..3a3a8c9d94093 100644 --- a/dts/arm/st/l0/stm32l031.dtsi +++ b/dts/arm/st/l0/stm32l031.dtsi @@ -13,7 +13,7 @@ timers22: timers@40011400 { compatible = "st,stm32-timers"; reg = <0x40011400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <22 0>; interrupt-names = "global"; diff --git a/dts/arm/st/l0/stm32l051.dtsi b/dts/arm/st/l0/stm32l051.dtsi index 2fcc76217430c..d6d263f2f7f95 100644 --- a/dts/arm/st/l0/stm32l051.dtsi +++ b/dts/arm/st/l0/stm32l051.dtsi @@ -16,7 +16,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -27,7 +27,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 3>; status = "disabled"; }; @@ -35,7 +35,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <27 0>; status = "disabled"; diff --git a/dts/arm/st/l0/stm32l053.dtsi b/dts/arm/st/l0/stm32l053.dtsi index 6209bc63abee4..480b5535da8ef 100644 --- a/dts/arm/st/l0/stm32l053.dtsi +++ b/dts/arm/st/l0/stm32l053.dtsi @@ -29,7 +29,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&otgfs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + clocks = <&rcc STM32_CLOCK(APB1, 23)>, <&rcc STM32_SRC_HSI48 HSI48_SEL(1)>; status = "disabled"; }; @@ -37,7 +37,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/l0/stm32l071.dtsi b/dts/arm/st/l0/stm32l071.dtsi index e3e67e8b2bd04..4a47411489a59 100644 --- a/dts/arm/st/l0/stm32l071.dtsi +++ b/dts/arm/st/l0/stm32l071.dtsi @@ -16,7 +16,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 4U)>; + clocks = <&rcc STM32_CLOCK(IOP, 4)>; }; }; @@ -26,7 +26,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -38,7 +38,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40007800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; interrupts = <21 0>; interrupt-names = "combined"; status = "disabled"; @@ -49,7 +49,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 3>; status = "disabled"; }; @@ -137,7 +137,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <27 0>; status = "disabled"; @@ -146,7 +146,7 @@ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <14 0>; status = "disabled"; @@ -155,7 +155,7 @@ usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <14 0>; status = "disabled"; diff --git a/dts/arm/st/l0/stm32l072.dtsi b/dts/arm/st/l0/stm32l072.dtsi index 0095909de7e3a..7f5080a716fa3 100644 --- a/dts/arm/st/l0/stm32l072.dtsi +++ b/dts/arm/st/l0/stm32l072.dtsi @@ -32,7 +32,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&otgfs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + clocks = <&rcc STM32_CLOCK(APB1, 23)>, <&rcc STM32_SRC_HSI48 HSI48_SEL(1)>; status = "disabled"; }; @@ -41,7 +41,7 @@ compatible = "st,stm32-rng"; reg = <0x40025000 0x400>; interrupts = <29 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 20U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 20)>; status = "disabled"; }; }; @@ -54,7 +54,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/l1/stm32l1.dtsi b/dts/arm/st/l1/stm32l1.dtsi index 31ce2a4fc8f3b..c6ed7026aed09 100644 --- a/dts/arm/st/l1/stm32l1.dtsi +++ b/dts/arm/st/l1/stm32l1.dtsi @@ -104,7 +104,7 @@ compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; reg = <0x40023c00 0x400>; interrupts = <4 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 15U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 15)>; #address-cells = <1>; #size-cells = <1>; @@ -135,7 +135,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -145,7 +145,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -154,7 +154,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -163,7 +163,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <48 0>; status = "disabled"; @@ -172,7 +172,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <49 0>; status = "disabled"; @@ -184,7 +184,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -196,7 +196,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -233,7 +233,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; interrupts = <35 0>; status = "disabled"; }; @@ -243,7 +243,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 0>; status = "disabled"; }; @@ -251,7 +251,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <37 0>; status = "disabled"; @@ -260,7 +260,7 @@ adc1: adc@40012400 { compatible = "st,stm32f4-adc", "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>, + clocks = <&rcc STM32_CLOCK(APB2, 9)>, <&rcc STM32_SRC_HSI NO_SEL>; interrupts = <18 0>; status = "disabled"; @@ -278,7 +278,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -448,7 +448,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; }; gpiob: gpio@40020400 { @@ -456,7 +456,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; }; gpioc: gpio@40020800 { @@ -464,7 +464,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; }; gpiod: gpio@40020c00 { @@ -472,7 +472,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40020c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 3)>; }; gpioe: gpio@40021000 { @@ -480,7 +480,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 4)>; }; gpioh: gpio@40021400 { @@ -488,7 +488,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x40021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 5)>; }; }; @@ -501,7 +501,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -515,7 +515,7 @@ compatible = "st,stm32-dma-v2bis"; #dma-cells = <2>; reg = <0x40026000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 24U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 24)>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; status = "disabled"; }; diff --git a/dts/arm/st/l1/stm32l151Xc.dtsi b/dts/arm/st/l1/stm32l151Xc.dtsi index f67163a260822..e6916a6921f4e 100644 --- a/dts/arm/st/l1/stm32l151Xc.dtsi +++ b/dts/arm/st/l1/stm32l151Xc.dtsi @@ -42,7 +42,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <47 0>; status = "disabled"; }; diff --git a/dts/arm/st/l1/stm32l152Xc.dtsi b/dts/arm/st/l1/stm32l152Xc.dtsi index 407f489e2bfb6..8d066cb78b7b0 100644 --- a/dts/arm/st/l1/stm32l152Xc.dtsi +++ b/dts/arm/st/l1/stm32l152Xc.dtsi @@ -42,7 +42,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <47 0>; status = "disabled"; }; diff --git a/dts/arm/st/l1/stm32l152Xe.dtsi b/dts/arm/st/l1/stm32l152Xe.dtsi index b58f18265faad..99f5efc42b7e3 100644 --- a/dts/arm/st/l1/stm32l152Xe.dtsi +++ b/dts/arm/st/l1/stm32l152Xe.dtsi @@ -42,7 +42,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <47 0>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index fe2e27c94eb09..b06d24bd6c4eb 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -2,6 +2,7 @@ * Copyright (c) 2017 Linaro Limited * Copyright (c) 2019 Centaur Analytics, Inc * Copyright (c) 2024 STMicroelectronics + * Copyright (c) 2025 Mario Paja * * SPDX-License-Identifier: Apache-2.0 */ @@ -124,7 +125,7 @@ compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller"; reg = <0x40022000 0x400>; interrupts = <4 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; #address-cells = <1>; #size-cells = <1>; @@ -177,7 +178,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; }; gpiob: gpio@48000400 { @@ -185,7 +186,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; }; gpioc: gpio@48000800 { @@ -193,7 +194,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; }; gpioh: gpio@48001c00 { @@ -201,7 +202,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 7)>; }; }; @@ -214,7 +215,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -222,7 +223,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <37 0>; status = "disabled"; @@ -231,7 +232,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <38 0>; status = "disabled"; @@ -240,7 +241,7 @@ lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; resets = <&rctl STM32_RESET(APB1H, 0U)>; interrupts = <70 0>; status = "disabled"; @@ -252,7 +253,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -264,7 +265,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -276,7 +277,7 @@ #size-cells = <0>; reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <71 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 8)>; status = "disabled"; }; @@ -286,7 +287,7 @@ #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <35 5>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; status = "disabled"; }; @@ -399,7 +400,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB1, 28U)>; + clocks = <&rcc STM32_CLOCK(APB1, 28)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <18>; @@ -409,7 +410,7 @@ adc1: adc@50040000 { compatible = "st,stm32-adc"; reg = <0x50040000 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -425,7 +426,7 @@ adc2: adc@50040100 { compatible = "st,stm32-adc"; reg = <0x50040100 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -443,7 +444,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-requests = <7>; status = "disabled"; }; @@ -453,14 +454,14 @@ #dma-cells = <3>; reg = <0x40020400 0x400>; interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-requests = <7>; status = "disabled"; }; lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -474,7 +475,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40009400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; interrupts = <66 1>; interrupt-names = "wakeup"; status = "disabled"; @@ -484,7 +485,7 @@ compatible = "st,stm32-rng"; reg = <0x50060800 0x400>; interrupts = <80 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, /* Following domain clock setting requires MSI * clock to be enabled with msi-range = <11>; */ @@ -567,6 +568,30 @@ i2c = <&i2c3>; status = "disabled"; }; + + sai1_a: sai1@40015404 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015404 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>, + <&rcc STM32_SRC_PLLSAI1_P SAI1_SEL(0)>; + dmas = <&dma2 1 1 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | + STM32_DMA_16BITS)>; + status = "disabled"; + }; + + sai1_b: sai1@40015424 { + compatible = "st,stm32-sai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015424 0x20>; + clocks = <&rcc STM32_CLOCK(APB2, 21)>, + <&rcc STM32_SRC_PLLSAI1_P SAI1_SEL(0)>; + dmas = <&dma2 2 1 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | + STM32_DMA_16BITS)>; + status = "disabled"; + }; }; &nvic { diff --git a/dts/arm/st/l4/stm32l412.dtsi b/dts/arm/st/l4/stm32l412.dtsi index 3084a43fdfb8c..2d1525eecd29f 100644 --- a/dts/arm/st/l4/stm32l412.dtsi +++ b/dts/arm/st/l4/stm32l412.dtsi @@ -22,7 +22,7 @@ rng: rng@50060800 { - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; @@ -35,7 +35,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>, + clocks = <&rcc STM32_CLOCK(APB1, 26)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; status = "disabled"; }; @@ -45,7 +45,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; clock-frequency = ; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; @@ -58,14 +58,14 @@ #size-cells = <0>; reg = <0x40003800 0x400>; interrupts = <36 5>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; status = "disabled"; }; usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; diff --git a/dts/arm/st/l4/stm32l422.dtsi b/dts/arm/st/l4/stm32l422.dtsi index bceee881ef17c..2101b20ac2f1e 100644 --- a/dts/arm/st/l4/stm32l422.dtsi +++ b/dts/arm/st/l4/stm32l422.dtsi @@ -13,7 +13,7 @@ aes: aes@50060000 { compatible = "st,stm32l4-aes", "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <79 0>; interrupt-names = "aes"; diff --git a/dts/arm/st/l4/stm32l431.dtsi b/dts/arm/st/l4/stm32l431.dtsi index 74fed758774f5..a604b69a395b0 100644 --- a/dts/arm/st/l4/stm32l431.dtsi +++ b/dts/arm/st/l4/stm32l431.dtsi @@ -25,7 +25,7 @@ gpiod: gpio@48000c00 { compatible = "st,stm32-gpio"; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; gpio-controller; #gpio-cells = <2>; }; @@ -33,7 +33,7 @@ gpioe: gpio@48001000 { compatible = "st,stm32-gpio"; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; gpio-controller; #gpio-cells = <2>; }; @@ -41,7 +41,7 @@ }; rng: rng@50060800 { - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; @@ -50,7 +50,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; clock-frequency = ; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; @@ -62,7 +62,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -72,7 +72,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -80,7 +80,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -106,7 +106,7 @@ can1: can@40006400 { compatible = "st,stm32-bxcan"; reg = <0x40006400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; status = "disabled"; @@ -115,7 +115,7 @@ sdmmc1: sdmmc@40012800 { compatible = "st,stm32-sdmmc"; reg = <0x40012800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>, + clocks = <&rcc STM32_CLOCK(APB2, 10)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; resets = <&rctl STM32_RESET(APB2, 10U)>; interrupts = <49 0>; @@ -125,7 +125,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; #io-channel-cells = <1>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l432.dtsi b/dts/arm/st/l4/stm32l432.dtsi index eec84445bcfe7..0d8a602aed2a5 100644 --- a/dts/arm/st/l4/stm32l432.dtsi +++ b/dts/arm/st/l4/stm32l432.dtsi @@ -21,7 +21,7 @@ compatible = "st,stm32l432", "st,stm32l4", "simple-bus"; rng: rng@50060800 { - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; @@ -30,7 +30,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -57,7 +57,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; @@ -70,7 +70,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>, + clocks = <&rcc STM32_CLOCK(APB1, 26)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; status = "disabled"; }; @@ -78,7 +78,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/st/l4/stm32l433.dtsi b/dts/arm/st/l4/stm32l433.dtsi index 040773a644fba..f234d63f6880b 100644 --- a/dts/arm/st/l4/stm32l433.dtsi +++ b/dts/arm/st/l4/stm32l433.dtsi @@ -16,7 +16,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioe: gpio@48001000 { @@ -24,7 +24,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; }; @@ -34,7 +34,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -45,7 +45,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -53,7 +53,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -62,7 +62,7 @@ sdmmc1: sdmmc@40012800 { compatible = "st,stm32-sdmmc"; reg = <0x40012800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>, + clocks = <&rcc STM32_CLOCK(APB2, 10)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; interrupts = <49 0>; status = "disabled"; diff --git a/dts/arm/st/l4/stm32l451.dtsi b/dts/arm/st/l4/stm32l451.dtsi index 6cdb14c493136..646a616e7c415 100644 --- a/dts/arm/st/l4/stm32l451.dtsi +++ b/dts/arm/st/l4/stm32l451.dtsi @@ -26,7 +26,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioe: gpio@48001000 { @@ -34,12 +34,12 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; }; rng: rng@50060800 { - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; @@ -49,7 +49,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -61,7 +61,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40008400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 1)>; interrupts = <83 0>, <84 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -72,7 +72,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -82,7 +82,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -90,7 +90,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -99,7 +99,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -131,7 +131,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -141,14 +141,14 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; sdmmc1: sdmmc@40012800 { compatible = "st,stm32-sdmmc"; reg = <0x40012800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>, + clocks = <&rcc STM32_CLOCK(APB2, 10)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; resets = <&rctl STM32_RESET(APB2, 10U)>; interrupts = <49 0>; diff --git a/dts/arm/st/l4/stm32l452.dtsi b/dts/arm/st/l4/stm32l452.dtsi index 9dfb59d7486ab..457409f6b1bd0 100644 --- a/dts/arm/st/l4/stm32l452.dtsi +++ b/dts/arm/st/l4/stm32l452.dtsi @@ -19,7 +19,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>, + clocks = <&rcc STM32_CLOCK(APB1, 26)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l462.dtsi b/dts/arm/st/l4/stm32l462.dtsi index c81b19567b85a..daa2da63892e8 100644 --- a/dts/arm/st/l4/stm32l462.dtsi +++ b/dts/arm/st/l4/stm32l462.dtsi @@ -13,7 +13,7 @@ aes: aes@50060000 { compatible = "st,stm32l4-aes", "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <79 0>; interrupt-names = "aes"; diff --git a/dts/arm/st/l4/stm32l471.dtsi b/dts/arm/st/l4/stm32l471.dtsi index 840f86cdfd670..54c8134bfca7e 100644 --- a/dts/arm/st/l4/stm32l471.dtsi +++ b/dts/arm/st/l4/stm32l471.dtsi @@ -25,7 +25,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioe: gpio@48001000 { @@ -33,7 +33,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; gpiof: gpio@48001400 { @@ -41,7 +41,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 5)>; }; gpiog: gpio@48001800 { @@ -49,14 +49,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; }; }; usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -65,7 +65,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -74,7 +74,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -86,7 +86,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -97,7 +97,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -107,7 +107,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -244,14 +244,14 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; sdmmc1: sdmmc@40012800 { compatible = "st,stm32-sdmmc"; reg = <0x40012800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>, + clocks = <&rcc STM32_CLOCK(APB2, 10)>, <&rcc STM32_SRC_MSI CLK48_SEL(3)>; resets = <&rctl STM32_RESET(APB2, 10U)>; interrupts = <49 0>; @@ -261,7 +261,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -269,7 +269,7 @@ adc3: adc@50040200 { compatible = "st,stm32-adc"; reg = <0x50040200 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <47 0>; status = "disabled"; #io-channel-cells = <1>; diff --git a/dts/arm/st/l4/stm32l475.dtsi b/dts/arm/st/l4/stm32l475.dtsi index cc76a34a14bf8..e58516aafc3f0 100644 --- a/dts/arm/st/l4/stm32l475.dtsi +++ b/dts/arm/st/l4/stm32l475.dtsi @@ -19,7 +19,7 @@ ram-size = <1280>; maximum-speed = "full-speed"; phys = <&otgfs_phy>; - clocks = <&rcc STM32_CLOCK(AHB2, 12U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 12)>, <&rcc STM32_SRC_MSI CLK48_SEL(3)>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l486.dtsi b/dts/arm/st/l4/stm32l486.dtsi index 223f1583073fb..46749e81d597c 100644 --- a/dts/arm/st/l4/stm32l486.dtsi +++ b/dts/arm/st/l4/stm32l486.dtsi @@ -13,7 +13,7 @@ aes: aes@50060000 { compatible = "st,stm32l4-aes", "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <79 0>; interrupt-names = "aes"; diff --git a/dts/arm/st/l4/stm32l496.dtsi b/dts/arm/st/l4/stm32l496.dtsi index 58cbeca390013..655e2010ec5db 100644 --- a/dts/arm/st/l4/stm32l496.dtsi +++ b/dts/arm/st/l4/stm32l496.dtsi @@ -21,7 +21,7 @@ compatible = "st,stm32l496", "st,stm32l4", "simple-bus"; rng: rng@50060800 { - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; @@ -31,7 +31,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40008400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 1)>; interrupts = <83 0>, <84 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -46,7 +46,7 @@ #gpio-cells = <2>; ngpios = <12>; reg = <0x48002000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 8)>; }; }; @@ -55,18 +55,18 @@ reg = <0x40006800 0x400>; interrupts = <86 0>, <87 0>, <88 0>, <89 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; //RCC_APB1ENR1_CAN2EN + clocks = <&rcc STM32_CLOCK(APB1, 26)>; //RCC_APB1ENR1_CAN2EN master-can-reg = <0x40006400>; status = "disabled"; }; usbotg_fs: otgfs@50000000 { - clocks = <&rcc STM32_CLOCK(AHB2, 12U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 12)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; sdmmc1: sdmmc@40012800 { - clocks = <&rcc STM32_CLOCK(APB2, 10U)>, + clocks = <&rcc STM32_CLOCK(APB2, 10)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; }; diff --git a/dts/arm/st/l4/stm32l4a6.dtsi b/dts/arm/st/l4/stm32l4a6.dtsi index 369f7f04bda0f..0822296c173e8 100644 --- a/dts/arm/st/l4/stm32l4a6.dtsi +++ b/dts/arm/st/l4/stm32l4a6.dtsi @@ -13,7 +13,7 @@ aes: aes@50060000 { compatible = "st,stm32l4-aes", "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <79 0>; interrupt-names = "aes"; diff --git a/dts/arm/st/l4/stm32l4p5.dtsi b/dts/arm/st/l4/stm32l4p5.dtsi index a05b4ef70eb04..31e309d67c75f 100644 --- a/dts/arm/st/l4/stm32l4p5.dtsi +++ b/dts/arm/st/l4/stm32l4p5.dtsi @@ -53,7 +53,7 @@ }; rng: rng@50060800 { - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; }; @@ -65,7 +65,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioe: gpio@48001000 { @@ -73,7 +73,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; gpiof: gpio@48001400 { @@ -81,7 +81,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 5)>; }; gpiog: gpio@48001800 { @@ -89,7 +89,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; }; gpioi: gpio@48002000 { @@ -97,14 +97,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48002000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 8)>; }; }; usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <39 0>; status = "disabled"; @@ -113,7 +113,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <52 0>; status = "disabled"; @@ -122,7 +122,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <53 0>; status = "disabled"; @@ -134,7 +134,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -146,7 +146,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40008400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 1)>; interrupts = <84 0>, <83 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -157,7 +157,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <36 5>; status = "disabled"; }; @@ -167,7 +167,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <51 5>; status = "disabled"; }; @@ -310,7 +310,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; @@ -322,7 +322,7 @@ num-bidir-endpoints = <6>; ram-size = <1280>; maximum-speed = "full-speed"; - clocks = <&rcc STM32_CLOCK(AHB2, 12U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 12)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; phys = <&otgfs_phy>; status = "disabled"; @@ -341,7 +341,7 @@ #dma-cells = <3>; reg = <0x40020800 0x400>; interrupts = <94 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; dma-channels = <14>; dma-generators = <4>; dma-requests= <89>; @@ -353,7 +353,7 @@ reg = <0x50050000 0x400>; interrupts = <85 0>; interrupt-names = "dcmi"; - clocks = <&rcc STM32_CLOCK(AHB2, 14U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 14)>; dmas = <&dma1 0 91 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; @@ -363,7 +363,7 @@ sdmmc1: sdmmc@50062400 { compatible = "st,stm32-sdmmc"; reg = <0x50062400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 22U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 22)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; resets = <&rctl STM32_RESET(AHB2, 22U)>; interrupts = <49 0>; @@ -374,7 +374,7 @@ sdmmc2: sdmmc@50062800 { compatible = "st,stm32-sdmmc"; reg = <0x50062800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 23U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 23)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; resets = <&rctl STM32_RESET(AHB2, 23U)>; interrupts = <47 0>; @@ -385,7 +385,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -395,9 +395,9 @@ reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <71 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; - clocks = <&rcc STM32_CLOCK(AHB3, 8U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 8)>, <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 20U)>; + <&rcc STM32_CLOCK(AHB2, 20)>; #address-cells = <1>; #size-cells = <0>; @@ -409,9 +409,9 @@ reg = <0xa0001400 0x400>, <0x70000000 DT_SIZE_M(256)>; interrupts = <76 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; - clocks = <&rcc STM32_CLOCK(AHB3, 9U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 9)>, <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 20U)>; + <&rcc STM32_CLOCK(AHB2, 20)>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/arm/st/l4/stm32l4q5.dtsi b/dts/arm/st/l4/stm32l4q5.dtsi index cc6191afb7f62..4816739125b7b 100644 --- a/dts/arm/st/l4/stm32l4q5.dtsi +++ b/dts/arm/st/l4/stm32l4q5.dtsi @@ -13,7 +13,7 @@ aes: aes@50060000 { compatible = "st,stm32l4-aes", "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <79 0>; interrupt-names = "aes"; diff --git a/dts/arm/st/l4/stm32l4r9.dtsi b/dts/arm/st/l4/stm32l4r9.dtsi index db067f754e200..5a67d82ae57df 100644 --- a/dts/arm/st/l4/stm32l4r9.dtsi +++ b/dts/arm/st/l4/stm32l4r9.dtsi @@ -17,7 +17,7 @@ reg = <0x40016800 0x200>; interrupts = <91 0>, <92 0>; interrupt-names = "ltdc", "ltdc_er"; - clocks = <&rcc STM32_CLOCK(APB2, 26U)>; + clocks = <&rcc STM32_CLOCK(APB2, 26)>; resets = <&rctl STM32_RESET(APB2, 26U)>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l4s5.dtsi b/dts/arm/st/l4/stm32l4s5.dtsi index 04ae65b6cbf89..c558b66a3bb0e 100644 --- a/dts/arm/st/l4/stm32l4s5.dtsi +++ b/dts/arm/st/l4/stm32l4s5.dtsi @@ -13,7 +13,7 @@ aes: aes@50060000 { compatible = "st,stm32l4-aes", "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <79 0>; interrupt-names = "aes"; diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi index 457a8f4b50e80..f337ae5187907 100644 --- a/dts/arm/st/l5/stm32l5.dtsi +++ b/dts/arm/st/l5/stm32l5.dtsi @@ -125,7 +125,7 @@ compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; reg = <0x40022000 0x400>; interrupts = <6 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 8)>; #address-cells = <1>; #size-cells = <1>; @@ -188,7 +188,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; }; gpiob: gpio@42020400 { @@ -196,7 +196,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; }; gpioc: gpio@42020800 { @@ -204,7 +204,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; }; gpiod: gpio@42020c00 { @@ -212,7 +212,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioe: gpio@42021000 { @@ -220,7 +220,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; gpiof: gpio@42021400 { @@ -228,7 +228,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 5)>; }; gpiog: gpio@42021800 { @@ -236,7 +236,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 6)>; }; gpioh: gpio@42021c00 { @@ -244,7 +244,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 7)>; }; }; @@ -257,7 +257,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 6>; status = "disabled"; }; @@ -265,7 +265,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <61 0>; status = "disabled"; @@ -274,7 +274,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <62 0>; status = "disabled"; @@ -283,7 +283,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <63 0>; status = "disabled"; @@ -292,7 +292,7 @@ uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <64 0>; status = "disabled"; @@ -301,7 +301,7 @@ uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <65 0>; status = "disabled"; @@ -310,7 +310,7 @@ lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; resets = <&rctl STM32_RESET(APB1H, 0U)>; interrupts = <66 0>; status = "disabled"; @@ -318,7 +318,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -332,7 +332,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-requests = <8>; dma-offset = <0>; status = "disabled"; @@ -343,7 +343,7 @@ #dma-cells = <3>; reg = <0x40020400 0x400>; interrupts = <80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-requests = <8>; dma-offset = <8>; status = "disabled"; @@ -354,7 +354,7 @@ #dma-cells = <3>; reg = <0x40020800 0x400>; interrupts = <27 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; dma-channels = <16>; dma-generators = <4>; dma-requests= <90>; @@ -367,7 +367,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <55 0>, <56 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -379,7 +379,7 @@ #size-cells = <0>; clock-frequency = ; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <57 0>, <58 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -391,14 +391,14 @@ #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <59 5>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; status = "disabled"; }; sdmmc1: sdmmc@420c8000 { compatible = "st,stm32-sdmmc"; reg = <0x420c8000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 22U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 22)>, <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; resets = <&rctl STM32_RESET(AHB2, 22U)>; interrupts = <78 0>; @@ -408,7 +408,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -419,7 +419,7 @@ #size-cells = <0>; reg = <0x40003800 0x400>; interrupts = <60 5>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; status = "disabled"; }; @@ -429,7 +429,7 @@ #size-cells = <0>; reg = <0x40003c00 0x400>; interrupts = <99 5>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; status = "disabled"; }; @@ -438,7 +438,7 @@ reg = <0x44021000 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <76 0>; clock-names = "ospix", "ospi-ker"; - clocks = <&rcc STM32_CLOCK(AHB3, 8U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 8)>, <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>; #address-cells = <1>; #size-cells = <0>; @@ -449,7 +449,7 @@ compatible = "st,stm32-rng"; reg = <0x420c0800 0x400>; interrupts = <94 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 18)>; nist-config = <0xf00d00>; health-test-magic = <0x17590abc>; health-test-config = <0xa2b3>; @@ -460,7 +460,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <2 0>; - clocks = <&rcc STM32_CLOCK(APB1, 10U)>; + clocks = <&rcc STM32_CLOCK(APB1, 10)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -667,7 +667,7 @@ adc1: adc@42028000 { compatible = "st,stm32-adc"; reg = <0x42028000 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <37 0>; status = "disabled"; #io-channel-cells = <1>; @@ -683,7 +683,7 @@ adc2: adc@42028100 { compatible = "st,stm32-adc"; reg = <0x42028100 0x100>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <37 0>; status = "disabled"; #io-channel-cells = <1>; @@ -716,7 +716,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; status = "disabled"; - clocks = <&rcc STM32_CLOCK(APB1_2, 21U)>, + clocks = <&rcc STM32_CLOCK(APB1_2, 21)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; phys = <&usb_fs_phy>; }; @@ -724,7 +724,7 @@ ucpd1: ucpd@4000dc00 { compatible = "st,stm32-ucpd"; reg = <0x4000dc00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <106 0>; status = "disabled"; }; @@ -732,7 +732,7 @@ fmc: fmc@44020000 { compatible = "st,stm32-fmc"; reg = <0x44020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 0)>; status = "disabled"; }; }; diff --git a/dts/arm/st/l5/stm32l562.dtsi b/dts/arm/st/l5/stm32l562.dtsi index 35c36715f25ea..bd3b7f26df5ae 100644 --- a/dts/arm/st/l5/stm32l562.dtsi +++ b/dts/arm/st/l5/stm32l562.dtsi @@ -13,7 +13,7 @@ aes: aes@420c0000 { compatible = "st,stm32-aes"; reg = <0x420c0000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <93 0>; status = "disabled"; diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi index 14077f5142b4a..511bcaf63b43b 100644 --- a/dts/arm/st/mp1/stm32mp157.dtsi +++ b/dts/arm/st/mp1/stm32mp157.dtsi @@ -87,7 +87,7 @@ reg = <0x50002000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 0)>; }; gpiob: gpio@50003000 { @@ -95,7 +95,7 @@ reg = <0x50003000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 1)>; }; gpioc: gpio@50004000 { @@ -103,7 +103,7 @@ reg = <0x50004000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 2)>; }; gpiod: gpio@50005000 { @@ -111,7 +111,7 @@ reg = <0x50005000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 3)>; }; gpioe: gpio@50006000 { @@ -119,7 +119,7 @@ reg = <0x50006000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 4)>; }; gpiof: gpio@50007000 { @@ -127,7 +127,7 @@ reg = <0x50007000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 5U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 5)>; }; gpiog: gpio@50008000 { @@ -135,7 +135,7 @@ reg = <0x50008000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 6U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 6)>; }; gpioh: gpio@50009000 { @@ -143,7 +143,7 @@ reg = <0x50009000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 7)>; }; gpioi: gpio@5000a000 { @@ -151,7 +151,7 @@ reg = <0x5000a000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 8)>; }; gpioj: gpio@5000b000 { @@ -159,7 +159,7 @@ reg = <0x5000b000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 9U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 9)>; }; gpiok: gpio@5000c000 { @@ -167,14 +167,14 @@ reg = <0x5000c000 0x400>; gpio-controller; #gpio-cells = <2>; - clocks = <&rcc STM32_CLOCK(AHB4, 10U)>; + clocks = <&rcc STM32_CLOCK(AHB4, 10)>; }; }; wwdg: wwdg1: watchdog@4000a000 { compatible = "st,stm32-window-watchdog"; reg = <0x4000a000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -183,7 +183,7 @@ compatible = "st,stm32-dma-v1"; #dma-cells = <4>; reg = <0x48000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; dma-offset = <0>; dma-requests = <8>; @@ -194,7 +194,7 @@ compatible = "st,stm32-dma-v1"; #dma-cells = <4>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; dma-offset = <8>; dma-requests = <8>; @@ -205,7 +205,7 @@ compatible = "st,stm32-dmamux"; #dma-cells = <3>; reg = <0x48002000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; interrupts = <102 0>; dma-channels = <16>; dma-generators = <8>; @@ -218,7 +218,7 @@ reg = <0x44004000 0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB2, 8U)>; + clocks = <&rcc STM32_CLOCK(APB2, 8)>; interrupts = <35 5>; status = "disabled"; }; @@ -228,7 +228,7 @@ reg = <0x4000b000 0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <36 5>; status = "disabled"; }; @@ -238,7 +238,7 @@ reg = <0x4000c000 0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB1, 12U)>; + clocks = <&rcc STM32_CLOCK(APB1, 12)>; interrupts = <51 5>; status = "disabled"; }; @@ -248,7 +248,7 @@ reg = <0x44005000 0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <84 5>; status = "disabled"; }; @@ -258,7 +258,7 @@ reg = <0x44009000 0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB2, 10U)>; + clocks = <&rcc STM32_CLOCK(APB2, 10)>; interrupts = <85 5>; status = "disabled"; }; @@ -266,7 +266,7 @@ usart2: serial@4000e000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x4000e000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; resets = <&rctl STM32_RESET(APB1, 14U)>; interrupts = <38 0>; status = "disabled"; @@ -275,7 +275,7 @@ usart3: serial@4000f000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x4000f000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; resets = <&rctl STM32_RESET(APB1, 15U)>; interrupts = <39 0>; status = "disabled"; @@ -284,7 +284,7 @@ uart4: serial@40010000 { compatible = "st,stm32-uart"; reg = <0x40010000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 16U)>; + clocks = <&rcc STM32_CLOCK(APB1, 16)>; resets = <&rctl STM32_RESET(APB1, 16U)>; interrupts = <52 0>; status = "disabled"; @@ -293,7 +293,7 @@ uart5: serial@40011000 { compatible = "st,stm32-uart"; reg = <0x40011000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1, 17U)>; interrupts = <53 0>; status = "disabled"; @@ -302,7 +302,7 @@ usart6: serial@44003000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x44003000 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 13U)>; + clocks = <&rcc STM32_CLOCK(APB2, 13)>; resets = <&rctl STM32_RESET(APB2, 13U)>; interrupts = <71 0>; status = "disabled"; @@ -311,7 +311,7 @@ uart7: serial@40018000 { compatible = "st,stm32-uart"; reg = <0x40018000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1, 18U)>; interrupts = <82 0>; status = "disabled"; @@ -320,7 +320,7 @@ uart8: serial@40019000 { compatible = "st,stm32-uart"; reg = <0x40019000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <83 0>; status = "disabled"; @@ -332,7 +332,7 @@ reg = <0x40015000 0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&rcc STM32_CLOCK(APB1, 24U)>; + clocks = <&rcc STM32_CLOCK(APB1, 24)>; interrupt-names = "event", "error"; interrupts = <107 0>, <108 0>; status = "disabled"; @@ -341,7 +341,7 @@ timers3: timers@40001000 { compatible = "st,stm32-timers"; reg = <0x40001000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 1U)>; + clocks = <&rcc STM32_CLOCK(APB1, 1)>; resets = <&rctl STM32_RESET(APB1, 1U)>; interrupts = <29 0>; interrupt-names = "global"; @@ -363,7 +363,7 @@ timers5: timers@40003000 { compatible = "st,stm32-timers"; reg = <0x40003000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 3U)>; + clocks = <&rcc STM32_CLOCK(APB1, 3)>; resets = <&rctl STM32_RESET(APB1, 3U)>; interrupts = <50 0>; interrupt-names = "global"; @@ -385,7 +385,7 @@ mailbox: mailbox@4c001000 { compatible = "st,stm32-ipcc-mailbox"; reg = <0x4c001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 12U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 12)>; interrupts = <103 0>, <104 0>; interrupt-names = "rxo", "txf"; status = "disabled"; @@ -396,7 +396,7 @@ reg = <0x5a001000 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_er"; - clocks = <&rcc STM32_CLOCK(APB4, 0U)>; + clocks = <&rcc STM32_CLOCK(APB4, 0)>; resets = <&rctl STM32_RESET(APB4, 26U)>; status = "disabled"; }; diff --git a/dts/arm/st/mp13/stm32mp135.dtsi b/dts/arm/st/mp13/stm32mp135.dtsi index 61a92c628164e..7644cadd235b2 100644 --- a/dts/arm/st/mp13/stm32mp135.dtsi +++ b/dts/arm/st/mp13/stm32mp135.dtsi @@ -21,25 +21,13 @@ resets = <&rctl STM32_RESET(APB4, 1)>; status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - endpoint { - remote-endpoint-label = ""; - bus-type = ; - }; - }; - - port@1 { - reg = <1>; + pipe_dump: pipe { + }; - dcmipp_pipe_dump: endpoint { - compatible = "st,stm32-dcmipp-pipe"; - }; + port { + endpoint { + remote-endpoint-label = ""; + bus-type = ; }; }; }; diff --git a/dts/arm/st/mp2/stm32mp2_m33.dtsi b/dts/arm/st/mp2/stm32mp2_m33.dtsi index 23c7b0ad99f85..a964d20a2513c 100644 --- a/dts/arm/st/mp2/stm32mp2_m33.dtsi +++ b/dts/arm/st/mp2/stm32mp2_m33.dtsi @@ -415,6 +415,21 @@ interrupt-names = "combined"; status = "disabled"; }; + + iwdg: iwdg4: watchdog@44040000 { + compatible = "st,stm32-watchdog"; + reg = <0x44040000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(IWDG4, STM32_CLK)>; + status = "disabled"; + }; + + wwdg: wwdg1: watchdog@44050000 { + compatible = "st,stm32-window-watchdog"; + reg = <0x44050000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(WWDG1, STM32_CLK)>; + interrupts = <8 0>; + status = "disabled"; + }; }; clocks { diff --git a/dts/arm/st/n6/stm32n6.dtsi b/dts/arm/st/n6/stm32n6.dtsi index 219d12783a14f..121d7d2840d8e 100644 --- a/dts/arm/st/n6/stm32n6.dtsi +++ b/dts/arm/st/n6/stm32n6.dtsi @@ -718,39 +718,28 @@ <&rctl STM32_RESET(APB5, 6)>; status = "disabled"; - ports { + pipes { + compatible = "st,stm32-dcmipp-pipes"; #address-cells = <1>; #size-cells = <0>; - port@0 { + pipe_dump: pipe@0 { reg = <0>; - - endpoint { - remote-endpoint-label = ""; - bus-type = ; - }; }; - port@1 { - #address-cells = <1>; - #size-cells = <0>; - + pipe_main: pipe@1 { reg = <1>; + }; - dcmipp_pipe_dump: endpoint@0 { - compatible = "st,stm32-dcmipp-pipe"; - reg = <0>; - }; - - dcmipp_pipe_main: endpoint@1 { - compatible = "st,stm32-dcmipp-pipe"; - reg = <1>; - }; + pipe_aux: pipe@2 { + reg = <2>; + }; + }; - dcmipp_pipe_aux: endpoint@2 { - compatible = "st,stm32-dcmipp-pipe"; - reg = <2>; - }; + port { + endpoint { + remote-endpoint-label = ""; + bus-type = ; }; }; }; @@ -1231,7 +1220,7 @@ status = "disabled"; }; - sai1_a: sai1@452005804 { + sai1_a: sai1@52005804 { compatible = "st,stm32-sai"; #address-cells = <1>; #size-cells = <0>; @@ -1274,6 +1263,14 @@ STM32_DMA_16BITS)>; status = "disabled"; }; + + npu: npu@580c0000 { + compatible = "st,stm32-npu"; + reg = <0x580c0000 0x1000>; + clocks = <&rcc STM32_CLOCK(AHB5, 31)>; + resets = <&rctl STM32_RESET(AHB5, 31)>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/n6/stm32n657X0.dtsi b/dts/arm/st/n6/stm32n657X0.dtsi index e692de0af9756..ab4cb6f326024 100644 --- a/dts/arm/st/n6/stm32n657X0.dtsi +++ b/dts/arm/st/n6/stm32n657X0.dtsi @@ -22,7 +22,7 @@ ramcfg@42023100 { axisram3: memory@34200000 { reg = <0x34200000 DT_SIZE_K(448)>; - status = "okay"; + status = "disabled"; }; }; diff --git a/dts/arm/st/u0/stm32u0.dtsi b/dts/arm/st/u0/stm32u0.dtsi index 73f7da7c3ce1e..608a3184a6194 100644 --- a/dts/arm/st/u0/stm32u0.dtsi +++ b/dts/arm/st/u0/stm32u0.dtsi @@ -168,7 +168,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 0U)>; + clocks = <&rcc STM32_CLOCK(IOP, 0)>; }; gpiob: gpio@50000400 { @@ -176,7 +176,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000400 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 1U)>; + clocks = <&rcc STM32_CLOCK(IOP, 1)>; }; gpioc: gpio@50000800 { @@ -184,7 +184,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000800 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 2U)>; + clocks = <&rcc STM32_CLOCK(IOP, 2)>; }; gpiod: gpio@50000C00 { @@ -192,7 +192,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50000C00 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 3U)>; + clocks = <&rcc STM32_CLOCK(IOP, 3)>; }; gpioe: gpio@50001000 { @@ -200,7 +200,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001000 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 4U)>; + clocks = <&rcc STM32_CLOCK(IOP, 4)>; }; gpiof: gpio@50001400 { @@ -208,14 +208,14 @@ gpio-controller; #gpio-cells = <2>; reg = <0x50001400 0x400>; - clocks = <&rcc STM32_CLOCK(IOP, 5U)>; + clocks = <&rcc STM32_CLOCK(IOP, 5)>; }; }; usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 14)>; resets = <&rctl STM32_RESET(APB1H, 14U)>; interrupts = <27 0>; status = "disabled"; @@ -224,7 +224,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <28 0>; status = "disabled"; @@ -233,7 +233,7 @@ usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 18U)>; + clocks = <&rcc STM32_CLOCK(APB1, 18)>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <29 0>; status = "disabled"; @@ -242,7 +242,7 @@ usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 19U)>; + clocks = <&rcc STM32_CLOCK(APB1, 19)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <30 0>; status = "disabled"; @@ -251,7 +251,7 @@ lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1, 20)>; resets = <&rctl STM32_RESET(APB1L, 20U)>; interrupts = <29 0>; status = "disabled"; @@ -260,7 +260,7 @@ lpuart2: serial@40008400 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 7U)>; + clocks = <&rcc STM32_CLOCK(APB1, 7)>; resets = <&rctl STM32_RESET(APB1L, 7U)>; interrupts = <28 0>; status = "disabled"; @@ -275,7 +275,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -283,7 +283,7 @@ adc1: adc@40012400 { compatible = "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 20)>; interrupts = <12 0>; status = "disabled"; #io-channel-cells = <1>; @@ -300,7 +300,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -311,7 +311,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <23 0>; interrupt-names = "combined"; status = "disabled"; @@ -323,7 +323,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -335,7 +335,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40008800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -346,7 +346,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-requests = <7>; dma-offset = <0>; status = "disabled"; @@ -368,7 +368,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 12)>; interrupts = <25 0>; status = "disabled"; }; @@ -378,7 +378,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; interrupts = <26 0>; status = "disabled"; }; @@ -388,7 +388,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + clocks = <&rcc STM32_CLOCK(APB1, 15)>; interrupts = <26 0>; status = "disabled"; }; @@ -396,7 +396,7 @@ rng: rng@40025000 { compatible = "st,stm32-rng"; reg = <0x40025000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 18)>; interrupts = <31 0>; status = "disabled"; }; @@ -404,7 +404,7 @@ aes: aes@40026000 { compatible = "st,stm32-aes"; reg = <0x40026000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 16)>; resets = <&rctl STM32_RESET(AHB1, 16U)>; interrupts = <31 0>; interrupt-names = "aes"; @@ -415,7 +415,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <2 0>; - clocks = <&rcc STM32_CLOCK(APB1, 10U)>; + clocks = <&rcc STM32_CLOCK(APB1, 10)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <28>; @@ -563,7 +563,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -575,7 +575,7 @@ lptim2: timers@40009400 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 30U)>; + clocks = <&rcc STM32_CLOCK(APB1, 30)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40009400 0x400>; @@ -587,7 +587,7 @@ tsc: tsc@40024000 { compatible = "st,stm32-tsc"; reg = <0x40024000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB1, 24U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 24)>; resets = <&rctl STM32_RESET(AHB1, 24U)>; interrupts = <21 0>; interrupt-names = "global"; diff --git a/dts/arm/st/u0/stm32u073.dtsi b/dts/arm/st/u0/stm32u073.dtsi index 52d53239acc56..afa493db5cdaf 100644 --- a/dts/arm/st/u0/stm32u073.dtsi +++ b/dts/arm/st/u0/stm32u073.dtsi @@ -16,7 +16,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x4000a000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; + clocks = <&rcc STM32_CLOCK(APB1, 25)>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; @@ -24,7 +24,7 @@ lptim3: timers@40009000 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; + clocks = <&rcc STM32_CLOCK(APB1, 26)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40009000 0x400>; @@ -38,7 +38,7 @@ #dma-cells = <3>; reg = <0x40020400 0x400>; interrupts = <11 0 11 0 11 0 11 0 11 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-requests = <5>; dma-offset = <7>; status = "disabled"; @@ -57,7 +57,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 13U)>; + clocks = <&rcc STM32_CLOCK(APB1, 13)>; status = "disabled"; }; }; diff --git a/dts/arm/st/u0/stm32u083.dtsi b/dts/arm/st/u0/stm32u083.dtsi index ac430ca0a8d6e..1f769e8f3061d 100644 --- a/dts/arm/st/u0/stm32u083.dtsi +++ b/dts/arm/st/u0/stm32u083.dtsi @@ -13,7 +13,7 @@ lpuart3: serial@40008c00 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 12U)>; + clocks = <&rcc STM32_CLOCK(APB1, 12)>; resets = <&rctl STM32_RESET(APB1L, 12U)>; interrupts = <30 0>; status = "disabled"; diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index fa521b18e8b33..c0a22872c8bd8 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -476,7 +476,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015404 0x20>; - clocks = <&rcc STM32_CLOCK(APB2, 21U)>, + clocks = <&rcc STM32_CLOCK(APB2, 21)>, <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; dmas = <&gpdma1 1 36 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | STM32_DMA_16BITS)>; @@ -488,7 +488,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40015424 0x20>; - clocks = <&rcc STM32_CLOCK(APB2, 21U)>, + clocks = <&rcc STM32_CLOCK(APB2, 21)>, <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; dmas = <&gpdma1 0 37 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | STM32_DMA_16BITS)>; @@ -725,9 +725,9 @@ reg = <0x420d2400 0x400>, <0x70000000 DT_SIZE_M(256)>; interrupts = <120 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; - clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>, + clocks = <&rcc STM32_CLOCK(AHB2_2, 8)>, <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 21U)>; + <&rcc STM32_CLOCK(AHB2, 21)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi index 214ddc4f78d2f..dd4f223e185ac 100644 --- a/dts/arm/st/wb/stm32wb.dtsi +++ b/dts/arm/st/wb/stm32wb.dtsi @@ -145,7 +145,7 @@ compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller"; reg = <0x58004000 0x400>; interrupts = <4 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 25U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 25)>; #address-cells = <1>; #size-cells = <1>; @@ -197,7 +197,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; }; gpiob: gpio@48000400 { @@ -205,7 +205,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; }; gpioc: gpio@48000800 { @@ -213,7 +213,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; }; gpiod: gpio@48000c00 { @@ -221,7 +221,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 3)>; }; gpioe: gpio@48001000 { @@ -230,7 +230,7 @@ #gpio-cells = <2>; ngpios = <5>; reg = <0x48001000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 4)>; }; gpioh: gpio@48001c00 { @@ -239,14 +239,14 @@ #gpio-cells = <2>; ngpios = <4>; reg = <0x48001c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 7)>; }; }; wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -254,7 +254,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <36 0>; status = "disabled"; @@ -266,7 +266,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <30 0>, <31 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -278,7 +278,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <32 0>, <33 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -288,7 +288,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <41 0>; - clocks = <&rcc STM32_CLOCK(APB1, 10U)>; + clocks = <&rcc STM32_CLOCK(APB1, 10)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -307,7 +307,7 @@ #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <34 5>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; status = "disabled"; }; @@ -317,14 +317,14 @@ #size-cells = <0>; reg = <0x40003800 0x400>; interrupts = <35 5>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; status = "disabled"; }; lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; resets = <&rctl STM32_RESET(APB1H, 0U)>; interrupts = <37 0>; status = "disabled"; @@ -420,7 +420,7 @@ adc1: adc@50040000 { compatible = "st,stm32-adc"; reg = <0x50040000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 13)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -441,7 +441,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -455,7 +455,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-requests = <7>; dma-offset = <0>; status = "disabled"; @@ -466,7 +466,7 @@ #dma-cells = <3>; reg = <0x40020400 0x400>; interrupts = <55 0 56 0 57 0 58 0 59 0 60 0 61 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-requests = <7>; dma-offset = <7>; status = "disabled"; @@ -477,7 +477,7 @@ #dma-cells = <3>; reg = <0x40020800 0x400>; interrupts = <62 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; dma-channels = <14>; dma-generators = <4>; dma-requests= <36>; @@ -493,7 +493,7 @@ ram-size = <1024>; maximum-speed = "full-speed"; phys = <&usb_fs_phy>; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>, + clocks = <&rcc STM32_CLOCK(APB1, 26)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; status = "disabled"; }; @@ -504,7 +504,7 @@ #size-cells = <0>; reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>; interrupts = <0x32 0x0>; - clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 8)>; status = "disabled"; }; @@ -512,14 +512,14 @@ compatible = "st,stm32-rng"; reg = <0x58001000 0x400>; interrupts = <53 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 18)>; status = "disabled"; }; aes1: aes@50060000 { compatible = "st,stm32-aes"; reg = <0x50060000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 16)>; resets = <&rctl STM32_RESET(AHB2, 16U)>; interrupts = <51 0>; status = "disabled"; @@ -582,7 +582,7 @@ ble_rf: ble_rf { compatible = "st,stm32wb-rf"; - clocks = <&rcc STM32_CLOCK(AHB3, 20U)>, + clocks = <&rcc STM32_CLOCK(AHB3, 20)>, <&rcc STM32_SRC_LSE RFWKP_SEL(1)>; }; diff --git a/dts/arm/st/wba/stm32wba.dtsi b/dts/arm/st/wba/stm32wba.dtsi index e67a069f1b1eb..6ea8a57b9dba8 100644 --- a/dts/arm/st/wba/stm32wba.dtsi +++ b/dts/arm/st/wba/stm32wba.dtsi @@ -63,7 +63,11 @@ power-state-name = "suspend-to-ram"; substate-id = <1>; min-residency-us = <1000>; - exit-latency-us = <50>; + /* + * From DS: worst case Twu_stdby with retention = 51.49 us + * Add extra margin to take resume code into account. + */ + exit-latency-us = <150>; }; }; }; @@ -246,7 +250,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; }; gpiob: gpio@42020400 { @@ -254,7 +258,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; }; gpioc: gpio@42020800 { @@ -262,7 +266,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42020800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; }; gpioh: gpio@42021c00 { @@ -270,7 +274,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x42021c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 7)>; }; }; @@ -278,7 +282,7 @@ compatible = "st,stm32-rtc"; reg = <0x46007800 0x400>; interrupts = <2 0>; - clocks = <&rcc STM32_CLOCK(APB7, 21U)>; + clocks = <&rcc STM32_CLOCK(APB7, 21)>; alarms-count = <2>; status = "disabled"; }; @@ -292,7 +296,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -300,7 +304,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <46 0>; status = "disabled"; @@ -309,7 +313,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <47 0>; status = "disabled"; @@ -318,7 +322,7 @@ lpuart1: serial@46002400 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x46002400 0x400>; - clocks = <&rcc STM32_CLOCK(APB7, 6U)>; + clocks = <&rcc STM32_CLOCK(APB7, 6)>; resets = <&rctl STM32_RESET(APB7, 6U)>; interrupts = <48 0>; status = "disabled"; @@ -330,7 +334,7 @@ #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <45 5>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; status = "disabled"; }; @@ -340,7 +344,7 @@ #size-cells = <0>; reg = <0x46002000 0x400>; interrupts = <63 5>; - clocks = <&rcc STM32_CLOCK(APB7, 5U)>; + clocks = <&rcc STM32_CLOCK(APB7, 5)>; status = "disabled"; }; @@ -350,7 +354,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <43 0>, <44 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -362,7 +366,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x46002800 0x400>; - clocks = <&rcc STM32_CLOCK(APB7, 7U)>; + clocks = <&rcc STM32_CLOCK(APB7, 7)>; interrupts = <54 0>, <55 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -484,7 +488,7 @@ adc4: adc@46021000 { compatible = "st,stm32-adc"; reg = <0x46021000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB4, 5U)>, + clocks = <&rcc STM32_CLOCK(AHB4, 5)>, <&rcc STM32_SRC_HCLK1 ADC_SEL(0)>; interrupts = <65 0>; status = "disabled"; @@ -505,7 +509,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x46004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB7, 11U)>; + clocks = <&rcc STM32_CLOCK(APB7, 11)>; interrupts = <49 1>; interrupt-names = "wakeup"; status = "disabled"; @@ -516,7 +520,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40009400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; interrupts = <50 1>; interrupt-names = "wakeup"; status = "disabled"; @@ -526,7 +530,7 @@ compatible = "st,stm32-rng"; reg = <0x420c0800 0x400>; interrupts = <59 0>; - clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 18)>, <&rcc STM32_SRC_HSI16 RNG_SEL(2)>; nist-config = <0xf00d>; health-test-config = <0xaac7>; @@ -538,7 +542,7 @@ #dma-cells = <3>; reg = <0x40020000 0x1000>; interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-channels = <8>; dma-requests = <52>; dma-offset = <0>; @@ -564,7 +568,8 @@ compatible = "swj-connector"; pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14 &debug_jtdi_pa15 &debug_jtdo_swo_pb3 - &debug_njtrst_pb4>; + /* temp fix to cover current wba5 pin naming */ + &debug_jtrst_pb4>; pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15 &analog_pb3 &analog_pb4>; pinctrl-names = "default", "sleep"; diff --git a/dts/arm/st/wba/stm32wba65.dtsi b/dts/arm/st/wba/stm32wba65.dtsi index 9a026d1bc8093..2ebebbd65d9dd 100644 --- a/dts/arm/st/wba/stm32wba65.dtsi +++ b/dts/arm/st/wba/stm32wba65.dtsi @@ -79,6 +79,16 @@ }; }; + /* + * Temporary revert of pinctrl-0 definition for stm3wba65 + * to fix issue on stm32wba5x based boards + */ + swj_port: swj_port { + pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14 + &debug_jtdi_pa15 &debug_jtdo_swo_pb3 + &debug_njtrst_pb4>; + }; + die_temp: dietemp { ts-cal1-addr = <0x0BFA0710>; ts-cal2-addr = <0x0BFA0742>; diff --git a/dts/arm/st/wl/stm32wl.dtsi b/dts/arm/st/wl/stm32wl.dtsi index 51924d337be69..a0c95dcfcc51b 100644 --- a/dts/arm/st/wl/stm32wl.dtsi +++ b/dts/arm/st/wl/stm32wl.dtsi @@ -170,7 +170,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 0)>; }; gpiob: gpio@48000400 { @@ -178,7 +178,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 1)>; }; gpioc: gpio@48000800 { @@ -186,7 +186,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 2)>; }; gpioh: gpio@48001c00 { @@ -194,13 +194,13 @@ gpio-controller; #gpio-cells = <2>; reg = <0x48001c00 0x400>; - clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; + clocks = <&rcc STM32_CLOCK(AHB2, 7)>; }; }; lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; - clocks = <&rcc STM32_CLOCK(APB1, 31U)>; + clocks = <&rcc STM32_CLOCK(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -213,7 +213,7 @@ compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <42 0>; - clocks = <&rcc STM32_CLOCK(APB1, 10U)>; + clocks = <&rcc STM32_CLOCK(APB1, 10)>; prescaler = <32768>; alarms-count = <2>; alrm-exti-line = <17>; @@ -241,7 +241,7 @@ wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 11U)>; + clocks = <&rcc STM32_CLOCK(APB1, 11)>; interrupts = <0 7>; status = "disabled"; }; @@ -249,7 +249,7 @@ usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 14U)>; + clocks = <&rcc STM32_CLOCK(APB2, 14)>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <36 0>; status = "disabled"; @@ -258,7 +258,7 @@ usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 17U)>; + clocks = <&rcc STM32_CLOCK(APB1, 17)>; resets = <&rctl STM32_RESET(APB1L, 17U)>; interrupts = <37 0>; status = "disabled"; @@ -267,7 +267,7 @@ lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; - clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; + clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; resets = <&rctl STM32_RESET(APB1H, 0U)>; interrupts = <38 0>; wakeup-line = <28>; @@ -280,7 +280,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 21U)>; + clocks = <&rcc STM32_CLOCK(APB1, 21)>; interrupts = <30 0>, <31 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -292,7 +292,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 22U)>; + clocks = <&rcc STM32_CLOCK(APB1, 22)>; interrupts = <32 0>, <33 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -304,7 +304,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 23U)>; + clocks = <&rcc STM32_CLOCK(APB1, 23)>; interrupts = <48 0>, <49 0>; interrupt-names = "event", "error"; status = "disabled"; @@ -316,7 +316,7 @@ #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <34 5>; - clocks = <&rcc STM32_CLOCK(APB2, 12U)>; + clocks = <&rcc STM32_CLOCK(APB2, 12)>; status = "disabled"; }; @@ -326,7 +326,7 @@ #size-cells = <0>; reg = <0x40003800 0x400>; interrupts = <35 5>; - clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + clocks = <&rcc STM32_CLOCK(APB1, 14)>; status = "disabled"; }; @@ -336,7 +336,7 @@ #size-cells = <0>; reg = <0x58010000 0x400>; interrupts = <44 5>; - clocks = <&rcc STM32_CLOCK(APB3, 0U)>; + clocks = <&rcc STM32_CLOCK(APB3, 0)>; status = "disabled"; use-subghzspi-nss; @@ -352,7 +352,7 @@ adc1: adc@40012400 { compatible = "st,stm32-adc"; reg = <0x40012400 0x400>; - clocks = <&rcc STM32_CLOCK(APB2, 9U)>; + clocks = <&rcc STM32_CLOCK(APB2, 9)>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; @@ -369,7 +369,7 @@ dac1: dac@40007400 { compatible = "st,stm32-dac"; reg = <0x40007400 0x400>; - clocks = <&rcc STM32_CLOCK(APB1, 29U)>; + clocks = <&rcc STM32_CLOCK(APB1, 29)>; status = "disabled"; #io-channel-cells = <1>; }; @@ -464,7 +464,7 @@ aes: aes@58001800 { compatible = "st,stm32-aes"; reg = <0x58001800 0x400>; - clocks = <&rcc STM32_CLOCK(AHB3, 17U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 17)>; resets = <&rctl STM32_RESET(AHB3, 16U)>; interrupts = <51 0>; status = "disabled"; @@ -474,7 +474,7 @@ compatible = "st,stm32-rng"; reg = <0x58001000 0x400>; interrupts = <52 0>; - clocks = <&rcc STM32_CLOCK(AHB3, 18U)>; + clocks = <&rcc STM32_CLOCK(AHB3, 18)>; health-test-magic = <0x17590abc>; health-test-config = <0xaa74>; status = "disabled"; @@ -485,7 +485,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-requests = <7>; dma-offset = <0>; status = "disabled"; @@ -496,7 +496,7 @@ #dma-cells = <3>; reg = <0x40020400 0x400>; interrupts = <54 0 55 0 56 0 57 0 58 0 59 0 60 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 1)>; dma-requests = <7>; dma-offset = <7>; status = "disabled"; @@ -507,7 +507,7 @@ #dma-cells = <3>; reg = <0x40020800 0x400>; interrupts = <61 0>; - clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; + clocks = <&rcc STM32_CLOCK(AHB1, 2)>; dma-channels = <14>; dma-generators = <4>; dma-requests= <38>; diff --git a/dts/arm/ti/mspm0/g/mspm0g.dtsi b/dts/arm/ti/mspm0/g/mspm0g.dtsi index d599264866148..2a34c24fa3c07 100644 --- a/dts/arm/ti/mspm0/g/mspm0g.dtsi +++ b/dts/arm/ti/mspm0/g/mspm0g.dtsi @@ -28,7 +28,7 @@ }; soc { - timg0: timg@40084000 { + timg0: timg0@40084000 { compatible = "ti,mspm0-timer"; reg = <0x40084000 0x2000>; clocks = <&ckm MSPM0_CLOCK_LFCLK>; @@ -37,13 +37,69 @@ ti,clk-div = <1>; status = "disabled"; - counter0: counter { + counterg0: counterg0 { compatible = "ti,mspm0-timer-counter"; resolution = <16>; + status = "disabled"; + }; + }; + + aes: aes@40442000 { + compatible = "ti,mspm0-aes"; + reg = <0x40442000 0x2000>; + interrupts = <28 0>; + status = "disabled"; + }; + + timg6: timg6@40868000 { + compatible = "ti,mspm0-timer"; + reg = <0x40868000 0x2000>; + interrupts = <17 0>; + clocks = <&ckm MSPM0_CLOCK_ULPCLK>; + ti,clk-prescaler = <255>; + ti,clk-div = <1>; + status = "disabled"; + + counterg6: counterg6 { + compatible = "ti,mspm0-timer-counter"; + resolution = <16>; + status = "disabled"; + }; + }; + + timg7: timg7@4086a000 { + compatible = "ti,mspm0-timer"; + reg = <0x4086a000 0x2000>; + interrupts = <20 0>; + clocks = <&ckm MSPM0_CLOCK_ULPCLK>; + ti,clk-prescaler = <255>; + ti,clk-div = <1>; + status = "disabled"; + + counterg7: counterg7 { + compatible = "ti,mspm0-timer-counter"; + resolution = <16>; + status = "disabled"; + }; + }; + + timg12: timg12@40870000 { + compatible = "ti,mspm0-timer"; + reg = <0x40870000 0x2000>; + interrupts = <21 0>; + clocks = <&ckm MSPM0_CLOCK_ULPCLK>; + ti,clk-prescaler = <0>; /* None */ + ti,clk-div = <1>; + status = "disabled"; + + counterg12: counterg12 { + compatible = "ti,mspm0-timer-counter"; + resolution = <32>; + status = "disabled"; }; }; - tima0: tima@40860000 { + tima0: tima0@40860000 { compatible = "ti,mspm0-timer"; reg = <0x40860000 0x2000>; clocks = <&ckm MSPM0_CLOCK_MCLK>; @@ -59,7 +115,7 @@ }; }; - tima1: tima@40862000 { + tima1: tima1@40862000 { compatible = "ti,mspm0-timer"; reg = <0x40862000 0x2000>; clocks = <&ckm MSPM0_CLOCK_MCLK>; diff --git a/dts/arm/ti/mspm0/g/mspm0gx51x.dtsi b/dts/arm/ti/mspm0/g/mspm0gx51x.dtsi index bf3c778eb5140..01d62300f4b43 100644 --- a/dts/arm/ti/mspm0/g/mspm0gx51x.dtsi +++ b/dts/arm/ti/mspm0/g/mspm0gx51x.dtsi @@ -12,5 +12,53 @@ gpio-controller; #gpio-cells = <2>; }; + + timg8: timg8@40090000 { + compatible = "ti,mspm0-timer"; + reg = <0x40090000 0x2000>; + interrupts = <2 0>; + clocks = <&ckm MSPM0_CLOCK_ULPCLK>; + ti,clk-prescaler = <255>; + ti,clk-div = <1>; + status = "disabled"; + + counterg8: counterg8 { + compatible = "ti,mspm0-timer-counter"; + resolution = <16>; + status = "disabled"; + }; + }; + + timg9: timg9@40092000 { + compatible = "ti,mspm0-timer"; + reg = <0x40092000 0x2000>; + interrupts = <8 0>; + clocks = <&ckm MSPM0_CLOCK_ULPCLK>; + ti,clk-prescaler = <255>; + ti,clk-div = <1>; + status = "disabled"; + + counterg9: counterg9 { + compatible = "ti,mspm0-timer-counter"; + resolution = <16>; + status = "disabled"; + }; + }; + + timg14: timg14@40096000 { + compatible = "ti,mspm0-timer"; + reg = <0x40096000 0x2000>; + interrupts = <22 0>; + clocks = <&ckm MSPM0_CLOCK_ULPCLK>; + ti,clk-prescaler = <255>; + ti,clk-div = <1>; + status = "disabled"; + + counterg14: counterg14 { + compatible = "ti,mspm0-timer-counter"; + resolution = <16>; + status = "disabled"; + }; + }; }; }; diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi index 80c4a53354983..550e6015f6858 100644 --- a/dts/arm/xilinx/zynqmp.dtsi +++ b/dts/arm/xilinx/zynqmp.dtsi @@ -19,12 +19,6 @@ compatible = "soc-nv-flash"; reg = <0xc0000000 DT_SIZE_M(32)>; }; - - sram0: memory@0 { - compatible = "mmio-sram"; - reg = <0 DT_SIZE_M(64)>; - }; - ocm: memory@fffc0000 { compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; reg = <0xfffc0000 DT_SIZE_K(256)>; diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi index e6b319cd5587c..64b322b727a4d 100644 --- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi @@ -90,6 +90,7 @@ ; gpio-controller; #gpio-cells = <2>; + status = "disabled"; }; gpio2: gpio@43810000 { @@ -100,6 +101,7 @@ ; gpio-controller; #gpio-cells = <2>; + status = "disabled"; }; gpio3: gpio@43820000 { @@ -110,6 +112,7 @@ ; gpio-controller; #gpio-cells = <2>; + status = "disabled"; }; gpio4: gpio@43830000 { @@ -120,6 +123,7 @@ ; gpio-controller; #gpio-cells = <2>; + status = "disabled"; }; lpuart1: serial@44380000 { diff --git a/dts/arm64/nxp/nxp_mimx943_a55.dtsi b/dts/arm64/nxp/nxp_mimx943_a55.dtsi index 3b4fee413e5f2..3152894a8e6ac 100644 --- a/dts/arm64/nxp/nxp_mimx943_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx943_a55.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include / { @@ -62,7 +63,15 @@ <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; + #address-cells = <1>; + #size-cells = <1>; status = "okay"; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0x48040000 0x20000>; + status = "okay"; + }; }; reserved-memory { @@ -85,6 +94,12 @@ #address-cells = <1>; #size-cells = <0>; + scmi_devpd: protocol@11 { + compatible = "arm,scmi-power"; + reg = <0x11>; + #power-domain-cells = <1>; + }; + scmi_clk: protocol@14 { compatible = "arm,scmi-clock"; reg = <0x14>; @@ -336,6 +351,141 @@ ngpios = <16>; status = "disabled"; }; + + netc_blk_ctrl: netc-blk-ctrl@4ceb0000 { + compatible = "nxp,imx-netc-blk-ctrl"; + reg = <0x4ceb0000 0x10000>, + <0x4cec0000 0x10000>, + <0x4c810000 0x7c>; + reg-names = "ierb", "prb", "netcmix"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + netc: ethernet { + compatible = "nxp,imx-netc"; + msi-parent = <&its>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + enetc_psi0: ethernet@4cc80000 { + compatible = "nxp,imx-netc-psi"; + reg = <0x4cc80000 0x40000>, + <0x4cb00000 0x1000>; + reg-names = "port", "pfconfig"; + msi-device-id = <0x65>; + mac-index = <0>; + si-index = <0>; + status = "disabled"; + }; + + enetc_psi1: ethernet@4ccc0000 { + compatible = "nxp,imx-netc-psi"; + reg = <0x4ccc0000 0x40000>, + <0x4cb40000 0x1000>; + reg-names = "port", "pfconfig"; + msi-device-id = <0x66>; + mac-index = <1>; + si-index = <1>; + status = "disabled"; + }; + + enetc_psi2: ethernet@4cd00000 { + compatible = "nxp,imx-netc-psi"; + reg = <0x4cd00000 0x40000>, + <0x4cb80000 0x1000>; + reg-names = "port", "pfconfig"; + msi-device-id = <0x67>; + mac-index = <2>; + si-index = <2>; + status = "disabled"; + }; + + /* Internal port */ + enetc_psi3: ethernet@4cd40000 { + compatible = "nxp,imx-netc-psi"; + reg = <0x4cd40000 0x40000>, + <0x4ca00000 0x1000>; + reg-names = "port", "pfconfig"; + mac-index = <3>; + si-index = <3>; + phy-connection-type = "internal"; + status = "disabled"; + }; + + netc_ptp_clock0: ptp_clock@4cd80000 { + compatible = "nxp,netc-ptp-clock"; + reg = <0x4cd80000 0x10000>; + clocks = <&scmi_clk IMX943_CLK_ENET>; + status = "disabled"; + }; + + netc_ptp_clock1: ptp_clock@4cda0000 { + compatible = "nxp,netc-ptp-clock"; + reg = <0x4cda0000 0x10000>; + clocks = <&scmi_clk IMX943_CLK_ENET>; + status = "disabled"; + }; + + netc_ptp_clock2: ptp_clock@4cdc0000 { + compatible = "nxp,netc-ptp-clock"; + reg = <0x4cdc0000 0x10000>; + clocks = <&scmi_clk IMX943_CLK_ENET>; + status = "disabled"; + }; + + emdio: mdio@4cbc0000 { + compatible = "nxp,imx-netc-emdio"; + reg = <0x4cde0000 0x2000>, + <0x4cbc0000 0x40000>; + reg-names = "basic", "pfconfig"; + clocks = <&scmi_clk IMX943_CLK_ENET>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + netc_switch: switch@4cc00000 { + compatible = "nxp,netc-switch"; + reg = <0x4cc00000 0x40000>, + <0x4ca02000 0x1000>; + reg-names = "base", "pfconfig"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + switch_port0: switch_port@0 { + compatible = "zephyr,dsa-port"; + reg = <0>; + status = "disabled"; + }; + + switch_port1: switch_port@1 { + compatible = "zephyr,dsa-port"; + reg = <1>; + status = "disabled"; + }; + + /* Parallel interface is muxed with enetc_psi0. */ + switch_port2: switch_port@2 { + compatible = "zephyr,dsa-port"; + reg = <2>; + status = "disabled"; + }; + + /* Internal port */ + switch_port3: switch_port@3 { + compatible = "zephyr,dsa-port"; + reg = <3>; + ethernet = <&enetc_psi3>; + phy-connection-type = "internal"; + dsa-tag-protocol = ; + status = "disabled"; + }; + }; + }; + }; }; /* diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi index 3b6f4d6f471fc..0c25555074fcc 100644 --- a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi +++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { compatible = "renesas,r9a07g063"; @@ -570,5 +571,81 @@ status = "disabled"; }; }; + + i2c0: i2c@10058000 { + compatible = "renesas,rz-riic"; + channel = <0>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10058000 DT_SIZE_K(1)>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; + + i2c1: i2c@10058400 { + compatible = "renesas,rz-riic"; + channel = <1>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10058400 DT_SIZE_K(1)>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + compatible = "renesas,rz-riic"; + channel = <2>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10058800 DT_SIZE_K(1)>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; + + i2c3: i2c@10058c00 { + compatible = "renesas,rz-riic"; + channel = <3>; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10058c00 DT_SIZE_K(1)>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "rxi", "txi", "tei", "naki", "spi", "sti", "ali", "tmoi"; + status = "disabled"; + }; }; }; diff --git a/dts/arm64/ti/ti_am62x_a53.dtsi b/dts/arm64/ti/ti_am62x_a53.dtsi index 72585a7a57ea1..584dff23d4fbd 100644 --- a/dts/arm64/ti/ti_am62x_a53.dtsi +++ b/dts/arm64/ti/ti_am62x_a53.dtsi @@ -26,6 +26,13 @@ }; }; + firmware { + psci: psci { + compatible = "arm,psci-1.1"; + method = "smc"; + }; + }; + oc_sram: memory@70000000 { reg = <0x70000000 DT_SIZE_K(64)>; }; diff --git a/dts/arm64/xilinx/versalnet_a78.dtsi b/dts/arm64/xilinx/versalnet_a78.dtsi new file mode 100644 index 0000000000000..35d913df84112 --- /dev/null +++ b/dts/arm64/xilinx/versalnet_a78.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Versal NET APU"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0>; + enable-method = "psci"; + }; + + cpu100: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu200: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu300: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + enable-method = "psci"; + reg = <0x300>; + }; + }; + + psci { + compatible = "arm,psci-1.1"; + method = "smc"; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; +}; + +&soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@e2000000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x0 0xe2000000 0x0 0x10000>, + <0x0 0xe2060000 0x0 0x200000>; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/dts/bindings/audio/nordic,nrf-pdm.yaml b/dts/bindings/audio/nordic,nrf-pdm.yaml index 78b08567b7d2b..e700a02053583 100644 --- a/dts/bindings/audio/nordic,nrf-pdm.yaml +++ b/dts/bindings/audio/nordic,nrf-pdm.yaml @@ -31,8 +31,7 @@ properties: (HFXO) for better clock accuracy and jitter performance - "ACLK": Audio PLL clock with configurable frequency (frequency for this clock must be set via the "hfclkaudio-frequency" property - in the "nordic,nrf-clock" node); this clock source is only available - in the nRF53 Series SoCs and it requires the use of HFXO + in the "nordic,nrf-clock" node); this clock source requires the use of HFXO enum: - "PCLK32M" - "PCLK32M_HFXO" diff --git a/dts/bindings/bluetooth/bt-hci.yaml b/dts/bindings/bluetooth/bt-hci.yaml index 52d3f82e4ef42..e4869bd4a5d54 100644 --- a/dts/bindings/bluetooth/bt-hci.yaml +++ b/dts/bindings/bluetooth/bt-hci.yaml @@ -21,7 +21,6 @@ properties: - "i2c" - "smd" - "virtio" - - "ipm" # Deprecated. "ipc" should be used instead. - "ipc" bt-hci-quirks: type: string-array diff --git a/dts/bindings/bluetooth/espressif,esp32-bt-hci.yaml b/dts/bindings/bluetooth/espressif,esp32-bt-hci.yaml index 47c62eeaab40c..0311b50fb6d86 100644 --- a/dts/bindings/bluetooth/espressif,esp32-bt-hci.yaml +++ b/dts/bindings/bluetooth/espressif,esp32-bt-hci.yaml @@ -8,6 +8,6 @@ properties: bt-hci-name: default: "BT ESP32" bt-hci-bus: - default: "ipm" + default: "ipc" bt-hci-quirks: default: ["no-auto-dle"] diff --git a/dts/bindings/bluetooth/nxp,hci-ble.yaml b/dts/bindings/bluetooth/nxp,hci-ble.yaml index 529e238b6ba67..8782699bcec98 100644 --- a/dts/bindings/bluetooth/nxp,hci-ble.yaml +++ b/dts/bindings/bluetooth/nxp,hci-ble.yaml @@ -11,4 +11,4 @@ properties: bt-hci-name: default: "BT NXP" bt-hci-bus: - default: "ipm" + default: "ipc" diff --git a/dts/bindings/bluetooth/renesas,bt-hci-da1469x.yaml b/dts/bindings/bluetooth/renesas,bt-hci-da1469x.yaml index 088a1f58f7b79..a05f9f5806934 100644 --- a/dts/bindings/bluetooth/renesas,bt-hci-da1469x.yaml +++ b/dts/bindings/bluetooth/renesas,bt-hci-da1469x.yaml @@ -8,4 +8,4 @@ properties: bt-hci-name: default: "BT DA1469x" bt-hci-bus: - default: "ipm" + default: "ipc" diff --git a/dts/bindings/bluetooth/st,hci-stm32wba.yaml b/dts/bindings/bluetooth/st,hci-stm32wba.yaml index 6b4fcc036d032..c1d02b66a1265 100644 --- a/dts/bindings/bluetooth/st,hci-stm32wba.yaml +++ b/dts/bindings/bluetooth/st,hci-stm32wba.yaml @@ -8,4 +8,6 @@ properties: bt-hci-name: default: "BT IPM" bt-hci-bus: - default: "ipm" + default: "ipc" + bt-hci-quirks: + default: ["no-reset"] diff --git a/dts/bindings/bluetooth/st,stm32wb-ble-rf.yaml b/dts/bindings/bluetooth/st,stm32wb-ble-rf.yaml index 5fb67d9f0434f..187f9171e03bc 100644 --- a/dts/bindings/bluetooth/st,stm32wb-ble-rf.yaml +++ b/dts/bindings/bluetooth/st,stm32wb-ble-rf.yaml @@ -14,6 +14,6 @@ properties: bt-hci-name: default: "BT IPM" bt-hci-bus: - default: "ipm" + default: "ipc" bt-hci-quirks: default: ["no-reset"] diff --git a/dts/bindings/bluetooth/zephyr,bt-hci-uart.yaml b/dts/bindings/bluetooth/zephyr,bt-hci-uart.yaml index 794fbc9c8af99..ee47c7bc2cfd5 100644 --- a/dts/bindings/bluetooth/zephyr,bt-hci-uart.yaml +++ b/dts/bindings/bluetooth/zephyr,bt-hci-uart.yaml @@ -11,3 +11,10 @@ properties: default: "H:4" bt-hci-bus: default: "uart" + reset-gpios: + type: phandle-array + reset-assert-duration-ms: + type: int + description: + Minimum duration to hold the reset-gpios pin low for. + If not specified no delay beyond the code path execution time is guaranteed. diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml index 6199eae4a9ca3..ad8f0aaeda62d 100644 --- a/dts/bindings/clock/st,stm32-rcc.yaml +++ b/dts/bindings/clock/st,stm32-rcc.yaml @@ -27,27 +27,38 @@ description: | Specifying a gated clock: - To specify a gated clock, a peripheral should define a "clocks" property encoded - in the following way: + To specify a gated clock, a peripheral should define a "clocks" property such as: ... { ... - clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; ... } - After the phandle referring to rcc node, the first index specifies the registers of - the bus controlling the peripheral and the second index specifies the bit used to - control the peripheral clock in that bus register. + + After the phandle referring to rcc node, use the STM32_CLOCK() macro which accepts + two parameters: the first specifies the bus on which the peripheral is attached, and + the second indicates the bit number controlling the peripheral clock gate in that + bus's control register in RCC. As an example, the snippet above indicates that the + peripheral gate is controlled by bit 5 in RCC_APB2ENR (USART6EN on STM32F401). The gated clock is required when accessing to the peripheral controller is needed (generally for configuring the device). If dual clock domain is not used, it is also used for peripheral operation. + Note: in situations where more than one bit is required, use the explicit form: + ... { + ... + clocks = <&rcc STM32_CLOCK_BUS_APB2 ((1 << 14) | (1 << 7))>; + ... + } + where 14 and 7 are the bits that control the peripheral clock gate. + (You can have more than two bits, and they do not have to be contiguous). + Specifying a domain clock source: Specifying a domain source clock could be done by adding a clock specifier to the clock property: ... { ... - clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>, + clocks = <&rcc STM32_CLOCK(APB2, 5)>, <&rcc STM32_SRC_HSI I2C1_SEL(2)>; ... } diff --git a/dts/bindings/clock/st,stm32wba-rcc.yaml b/dts/bindings/clock/st,stm32wba-rcc.yaml index ea6bd32e74179..9ce92b3b5a9cd 100644 --- a/dts/bindings/clock/st,stm32wba-rcc.yaml +++ b/dts/bindings/clock/st,stm32wba-rcc.yaml @@ -28,16 +28,31 @@ description: | Specifying a gated clock: - To specify a gated clock, a peripheral should define a "clocks" property encoded - in the following way: + To specify a gated clock, a peripheral should define a "clocks" property such as: ... { ... - clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>; + clocks = <&rcc STM32_CLOCK(APB2, 5)>; ... } - After the phandle referring to rcc node, the first index specifies the registers of - the bus controlling the peripheral and the second index specifies the bit used to - control the peripheral clock in that bus register. + + After the phandle referring to rcc node, use the STM32_CLOCK() macro which accepts + two parameters: the first specifies the bus on which the peripheral is attached, and + the second indicates the bit number controlling the peripheral clock gate in that + bus's control register in RCC. As an example, the snippet above indicates that the + peripheral gate is controlled by bit 5 in RCC_APB2ENR (USART6EN on STM32F401). + The gated clock is required when accessing to the peripheral controller is needed + (generally for configuring the device). If dual clock domain is not used, it is + also used for peripheral operation. + + Note: in situations where more than one bit is required, use the explicit form: + ... { + ... + clocks = <&rcc STM32_CLOCK_BUS_APB2 ((1 << 14) | (1 << 7))>; + ... + } + where 14 and 7 are the bits that control the peripheral clock gate. + (You can have more than two bits, and they do not have to be contiguous). + Specifying an alternate clock source: @@ -45,7 +60,7 @@ description: | clock property: ... { ... - clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>, + clocks = <&rcc STM32_CLOCK(APB2, 5)>, <&rcc STM32_SRC_HSI I2C1_SEL(2)>; ... } diff --git a/dts/bindings/counter/maxim,ds3231.yaml b/dts/bindings/counter/maxim,ds3231.yaml index 68567df6c6622..7ddd0c5bc3857 100644 --- a/dts/bindings/counter/maxim,ds3231.yaml +++ b/dts/bindings/counter/maxim,ds3231.yaml @@ -4,7 +4,9 @@ # SPDX-License-Identifier: Apache-2.0 # -description: Maxim DS3231 I2C RTC/TCXO +# This binding is deprecated in favor of maxim,ds3231-rtc. + +description: Maxim DS3231 I2C RTC/TCXO. compatible: "maxim,ds3231" diff --git a/dts/bindings/cpu/arm,cortex-a78.yaml b/dts/bindings/cpu/arm,cortex-a78.yaml new file mode 100644 index 0000000000000..1c7f167c9b698 --- /dev/null +++ b/dts/bindings/cpu/arm,cortex-a78.yaml @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +description: ARM Cortex-A78 CPU + +compatible: "arm,cortex-a78" + +include: cpu.yaml diff --git a/dts/bindings/cpu/renesas,rxv1.yaml b/dts/bindings/cpu/renesas,rxv1.yaml new file mode 100644 index 0000000000000..f48b766d5c88d --- /dev/null +++ b/dts/bindings/cpu/renesas,rxv1.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RXv1 CPU + +compatible: "renesas,rxv1" + +include: renesas,rx.yaml diff --git a/dts/bindings/cpu/renesas,rxv2.yaml b/dts/bindings/cpu/renesas,rxv2.yaml new file mode 100644 index 0000000000000..1f68a16bf34f4 --- /dev/null +++ b/dts/bindings/cpu/renesas,rxv2.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RXv2 CPU + +compatible: "renesas,rxv2" + +include: renesas,rx.yaml diff --git a/dts/bindings/cpu/renesas,rxv3.yaml b/dts/bindings/cpu/renesas,rxv3.yaml new file mode 100644 index 0000000000000..6da63d8d3a77c --- /dev/null +++ b/dts/bindings/cpu/renesas,rxv3.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RXv3 CPU + +compatible: "renesas,rxv3" + +include: renesas,rx.yaml diff --git a/dts/bindings/crc/renesas,ra-crc.yaml b/dts/bindings/crc/renesas,ra-crc.yaml new file mode 100644 index 0000000000000..2db50658b2490 --- /dev/null +++ b/dts/bindings/crc/renesas,ra-crc.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +title: Renesas RA CRC (Cyclic Redundancy Check) device + +description: Renesas RA CRC (Cyclic Redundancy Check) driver + +compatible: "renesas,ra-crc" + +include: [base.yaml] + +properties: + reg: + required: true + + clocks: + required: true diff --git a/dts/bindings/crypto/ti,aes.yaml b/dts/bindings/crypto/ti,aes.yaml new file mode 100644 index 0000000000000..f761d06f123dc --- /dev/null +++ b/dts/bindings/crypto/ti,aes.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Linumiz GmbH +# SPDX-License-Identifier: Apache-2.0 + +description: | + Texas Instruments MSPM0 G series Advanced Encryption Standard (AES) Engine + This peripheral provides AES-128 and AES-256 encryption and decryption. + +compatible: "ti,mspm0-aes" + +include: base.yaml + +properties: + reg: + required: true + + interrupts: + required: true diff --git a/dts/bindings/display/ilitek,ili9xxx-common.yaml b/dts/bindings/display/ilitek,ili9xxx-common.yaml index a48dd8d34c704..7ce2f5eaa9c59 100644 --- a/dts/bindings/display/ilitek,ili9xxx-common.yaml +++ b/dts/bindings/display/ilitek,ili9xxx-common.yaml @@ -7,7 +7,11 @@ title: ILI9XXX display controllers common properties. description: | Ilitek ILI9XXX is a color TFT-LCD controller series. -include: [mipi-dbi-spi-device.yaml, display-controller.yaml] +include: + - display-controller.yaml + - name: mipi-dbi-spi-device.yaml + property-blocklist: + - te-delay properties: pixel-format: diff --git a/dts/bindings/dsa/nxp,netc-switch.yaml b/dts/bindings/dsa/nxp,netc-switch.yaml index 33842d607614a..71003b058943f 100644 --- a/dts/bindings/dsa/nxp,netc-switch.yaml +++ b/dts/bindings/dsa/nxp,netc-switch.yaml @@ -5,4 +5,8 @@ description: NXP NETC ethernet switch compatible: "nxp,netc-switch" -include: [dsa.yaml] +include: [dsa.yaml, base.yaml] + +properties: + reg: + required: true diff --git a/dts/bindings/ethernet/atmel,gmac-common.yaml b/dts/bindings/ethernet/atmel,gmac-common.yaml index 0975647e1875c..fc9c758973054 100644 --- a/dts/bindings/ethernet/atmel,gmac-common.yaml +++ b/dts/bindings/ethernet/atmel,gmac-common.yaml @@ -7,9 +7,6 @@ include: - name: pinctrl-device.yaml properties: - reg: - required: true - phy-handle: required: true diff --git a/dts/bindings/ethernet/atmel,sam-gmac.yaml b/dts/bindings/ethernet/atmel,sam-gmac.yaml index cd32c2312d581..b8c636ddb0e60 100644 --- a/dts/bindings/ethernet/atmel,sam-gmac.yaml +++ b/dts/bindings/ethernet/atmel,sam-gmac.yaml @@ -6,7 +6,3 @@ description: Atmel SAM-family GMAC Ethernet compatible: "atmel,sam-gmac" include: atmel,gmac-common.yaml - -properties: - clocks: - required: true diff --git a/dts/bindings/ethernet/microchip,sam-ethernet-controller.yaml b/dts/bindings/ethernet/microchip,sam-ethernet-controller.yaml new file mode 100644 index 0000000000000..8389e08ed6266 --- /dev/null +++ b/dts/bindings/ethernet/microchip,sam-ethernet-controller.yaml @@ -0,0 +1,15 @@ +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# SPDX-License-Identifier: Apache-2.0 + +title: Microchip SAM Ethernet Controller + +description: | + Contains the Ethernet MAC and the MDIO as child nodes. + +compatible: "microchip,sam-ethernet-controller" + +include: base.yaml + +properties: + reg: + required: true diff --git a/dts/bindings/ethernet/xlnx,gem.yaml b/dts/bindings/ethernet/xlnx,gem.yaml index b2f0f2a3e6fc1..6dec354613c3d 100644 --- a/dts/bindings/ethernet/xlnx,gem.yaml +++ b/dts/bindings/ethernet/xlnx,gem.yaml @@ -225,19 +225,21 @@ properties: Optional feature flag - Enable frames to be received in half-duplex mode while transmitting. - rx-checksum-offload: + disable-rx-checksum-offload: type: boolean description: | - Optional feature flag - Enable RX IP/TCP/UDP checksum offload to - hardware. Frames with bad IP, TCP or UDP checksums will be discarded. - This option is NOT supported by the QEMU implementation of the GEM! + Disable RX IPv4/IPv6/TCP/UDP checksum offload to hardware. Checksum + offloading is enabled by default, and automatically disabled for + QEMU targets, where hardware checksum offloading is not emulated, + without having to set this flag explicitly. - tx-checksum-offload: + disable-tx-checksum-offload: type: boolean description: | - Optional feature flag - Enable TX IP/TCP/UDP checksum offload to - hardware. This option is NOT supported by the QEMU implementation - of the GEM! + Disable TX IPv4/IPv6/TCP/UDP checksum offload to hardware. Checksum + offloading is enabled by default, and automatically disabled for + QEMU targets, where hardware checksum offloading is not emulated, + without having to set this flag explicitly. disable-pause-copy: type: boolean diff --git a/dts/bindings/fuel-gauge/ti,bq40z50.yaml b/dts/bindings/fuel-gauge/ti,bq40z50.yaml new file mode 100644 index 0000000000000..98057d37a2410 --- /dev/null +++ b/dts/bindings/fuel-gauge/ti,bq40z50.yaml @@ -0,0 +1,12 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: Apache-2.0 + +description: | + Texas Instruments BQ40Z50 fuel gauge. For more info visit + https://www.ti.com/product/BQ40Z50. + + +compatible: "ti,bq40z50" + +include: [i2c-device.yaml, fuel-gauge.yaml] diff --git a/dts/bindings/gpio/arduino-header-r3.yaml b/dts/bindings/gpio/arduino-header-r3.yaml index 1dae0b2575ad9..84d194e6ba337 100644 --- a/dts/bindings/gpio/arduino-header-r3.yaml +++ b/dts/bindings/gpio/arduino-header-r3.yaml @@ -44,6 +44,8 @@ description: | 4 A4 D1 7 5 A5 D0 6 + Use ARDUINO_HEADER_R3_* constants in to refer to + specific pins using convenient constant names. compatible: "arduino-header-r3" diff --git a/dts/bindings/gpio/arduino-mkr-header.yaml b/dts/bindings/gpio/arduino-mkr-header.yaml index 03fb39d053c7d..d985522a26eb0 100644 --- a/dts/bindings/gpio/arduino-mkr-header.yaml +++ b/dts/bindings/gpio/arduino-mkr-header.yaml @@ -33,6 +33,8 @@ description: | 4 D4 D7 7 5 D5 D6 6 + Use ARDUINO_MKR_HEADER_* constants in to refer to + specific pins using convenient constant names. compatible: "arduino-mkr-header" diff --git a/dts/bindings/gpio/arduino-nano-header.yaml b/dts/bindings/gpio/arduino-nano-header.yaml index 45228b2ffe112..05433ecc83616 100644 --- a/dts/bindings/gpio/arduino-nano-header.yaml +++ b/dts/bindings/gpio/arduino-nano-header.yaml @@ -32,6 +32,8 @@ description: | 11 D11 3V3 - 12 D12 D13 13 + Use ARDUINO_NANO_HEADER_* constants in + to refer to specific pins using convenient constant names. compatible: "arduino-nano-header" diff --git a/dts/bindings/gpio/bflb,bl61x-gpio.yaml b/dts/bindings/gpio/bflb,bl61x-gpio.yaml new file mode 100644 index 0000000000000..f8e4685d31331 --- /dev/null +++ b/dts/bindings/gpio/bflb,bl61x-gpio.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +description: BouffaloLab GPIO node for BL61X serie + +compatible: "bflb,bl61x-gpio" + +include: + - name: base.yaml + - name: gpio-controller.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + "#gpio-cells": + const: 2 + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/gpio/fobe,quill-header.yaml b/dts/bindings/gpio/fobe,quill-header.yaml new file mode 100644 index 0000000000000..3ee76de8ea117 --- /dev/null +++ b/dts/bindings/gpio/fobe,quill-header.yaml @@ -0,0 +1,38 @@ +# Copyright (c) 2025 FoBE Studio +# SPDX-License-Identifier: Apache-2.0 + +title: GPIO pins exposed on the FoBE Quill connector + +description: | + The Quill layout provides two headers, one each along + opposite edges of the board. + Pin mapping overview: + * Left 14-pin header: 11 pins are mapped in this binding. + * Right 14-pin header: 12 pins are mapped in this binding. + + This binding provides a nexus mapping for 20 pins where parent pins 14 + through 19 correspond to A0 through A5, and parent pins 0 through 13 + correspond as depicted below: + + VBUS - + 3V3 - + GND - + 3V3_EN - + - BAT REF - + - RESET D2 2 + - GND D1 1 + 13 D13 D0 0 + 12 D12 A5 19 + 11 D11 A4 18 + 10 D10 A3 17 + 9 D9 A2 16 + 8 D8 A1 15 + 7 D7 A0 14 + 6 D6 + 5 D5 + 4 D4 + 3 D3 + +compatible: "fobe,quill-header" + +include: [gpio-nexus.yaml, base.yaml] diff --git a/dts/bindings/gpio/raspberrypi,csi-connector.yaml b/dts/bindings/gpio/raspberrypi,csi-connector.yaml index dc5e1881ca8a9..d1f0ea9eadceb 100644 --- a/dts/bindings/gpio/raspberrypi,csi-connector.yaml +++ b/dts/bindings/gpio/raspberrypi,csi-connector.yaml @@ -19,6 +19,9 @@ description: | 3 I2C_SCL pin 13 (15-pin based) / pin 20 (22-pin based) 4 I2C_SDA pin 14 (15-pin based) / pin 21 (22-pin based) + Use CSI_* constants in + to refer to specific pins using convenient constant names. + For reference only, Raspberry 15-pin Connector layout: 1 GND 2 CSI_D0_N diff --git a/dts/bindings/gpio/silabs,exp-header.yaml b/dts/bindings/gpio/silabs,exp-header.yaml new file mode 100644 index 0000000000000..13b0f91154d24 --- /dev/null +++ b/dts/bindings/gpio/silabs,exp-header.yaml @@ -0,0 +1,30 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +title: Silicon Labs Kit Expansion Header + +description: | + GPIO pins exposed on the Expansion Header of Silicon Labs Pro Kits, Wireless Pro Kits, + Starter Kits and Wireless Starter Kits. Dev Kits also use the Expansion Header pinout + for their breakout pads. + + The Expansion Header contains several I/O pins as well as VMCU, 3.3V and 5V power rails. + + 20 -o 3V3 BOARD_ID_SDA o- 19 + 18 -o 5V BOARD_ID_SCL o- 17 + 16 -o I2C SDA I2C SCL o- 15 + 14 -o UART RX GPIO o- 13 + 12 -o UART TX GPIO o- 11 + 10 -o SPI CS GPIO o- 9 + 8 -o SPI CLK GPIO o- 7 + 6 -o SPI CIPO GPIO o- 5 + 4 -o SPI COPI GPIO o- 3 + 2 -o VMCU GND o- 1 + + Note: The BOARD_ID I2C lines are connected to the debugger, not to the SoC, so the usable + GPIOs range from pin 3 to pin 16. Not all pins are routed on all boards, depending on the + SoC used and board design. + +compatible: "silabs,exp-header" + +include: [gpio-nexus.yaml, base.yaml] diff --git a/dts/bindings/gpio/silabs,gpio-port.yaml b/dts/bindings/gpio/silabs,gpio-port.yaml index 25aa379171bab..9462ef85b32ef 100644 --- a/dts/bindings/gpio/silabs,gpio-port.yaml +++ b/dts/bindings/gpio/silabs,gpio-port.yaml @@ -14,6 +14,18 @@ properties: "#gpio-cells": const: 2 + silabs,wakeup-ints: + type: array + description: | + List of EM4 wakeup interrupt numbers for this port. The corresponding entry + in `silabs,wakeup-pins` indicates the pin associated with the interrupt number. + + silabs,wakeup-pins: + type: array + description: | + List of EM4 wakeup capable pins for this port. The corresponding entry in + `silabs,wakeup-ints` indicates the interrupt number associated with the pin. + gpio-cells: - pin - flags diff --git a/dts/bindings/gpio/st-morpho-header.yaml b/dts/bindings/gpio/st-morpho-header.yaml index c1726b7a2d66d..2e43cd14adc46 100644 --- a/dts/bindings/gpio/st-morpho-header.yaml +++ b/dts/bindings/gpio/st-morpho-header.yaml @@ -9,6 +9,9 @@ description: | any Nucleo board. They can be used to connect shields. All signals and power pins of the STM32 are available on the ST morpho connector. + Use ST_MORPHO_* constants in + to refer to specific pins using convenient constant names. + compatible: "st-morpho-header" include: [gpio-nexus.yaml, base.yaml] diff --git a/dts/bindings/hwinfo/nxp,cmc-reset-cause.yaml b/dts/bindings/hwinfo/nxp,cmc-reset-cause.yaml new file mode 100644 index 0000000000000..5819ba7317241 --- /dev/null +++ b/dts/bindings/hwinfo/nxp,cmc-reset-cause.yaml @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: CMC reset causes + +compatible: "nxp,cmc-reset-cause" diff --git a/dts/bindings/i2c/renesas,rz-iic.yaml b/dts/bindings/i2c/renesas,rz-iic.yaml new file mode 100644 index 0000000000000..31c938475f345 --- /dev/null +++ b/dts/bindings/i2c/renesas,rz-iic.yaml @@ -0,0 +1,43 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RZ I2C controller + +compatible: "renesas,rz-iic" + +include: [i2c-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + channel: + required: true + type: int + + interrupts: + required: true + + rise-time-ns: + type: int + default: 120 + description: | + Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C specification. + + fall-time-ns: + type: int + default: 120 + description: | + Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C specification. + + duty-cycle-percent: + type: int + default: 50 + + noise-filter-stages: + type: int + default: 1 + enum: + - 1 + description: | + Set the noise filter stages. Currently, only single-stage filter is supported. diff --git a/dts/bindings/i2c/renesas,rz-riic.yaml b/dts/bindings/i2c/renesas,rz-riic.yaml index 42b7fdc5d96b9..e5e90fd7e0c72 100644 --- a/dts/bindings/i2c/renesas,rz-riic.yaml +++ b/dts/bindings/i2c/renesas,rz-riic.yaml @@ -1,7 +1,7 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RZ/G3S I2C controller +description: Renesas RZ I2C controller compatible: "renesas,rz-riic" diff --git a/dts/bindings/i2c/silabs,i2c.yaml b/dts/bindings/i2c/silabs,i2c.yaml new file mode 100644 index 0000000000000..9e80cdab889e7 --- /dev/null +++ b/dts/bindings/i2c/silabs,i2c.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: Silabs I2C node + +compatible: "silabs,i2c" + +include: [i2c-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/input/nxp,mcux-kpp.yaml b/dts/bindings/input/nxp,mcux-kpp.yaml new file mode 100644 index 0000000000000..fc4181537a958 --- /dev/null +++ b/dts/bindings/input/nxp,mcux-kpp.yaml @@ -0,0 +1,18 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP KPP controller + +compatible: "nxp,mcux-kpp" + +include: [base.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + clocks: + required: true diff --git a/dts/bindings/lora/semtech,sx126x-base.yaml b/dts/bindings/lora/semtech,sx126x-base.yaml index dd9f96381a472..d4d1c36b6622c 100644 --- a/dts/bindings/lora/semtech,sx126x-base.yaml +++ b/dts/bindings/lora/semtech,sx126x-base.yaml @@ -59,3 +59,9 @@ properties: type: int description: | Startup delay to let the TCXO stabilize after TCXO power on. + + rx-boosted: + type: boolean + description: | + Enable RX boosted mode, which increases the power consumption of + RX mode by ~2mA in exchange for ~3dB sensitivity improvement. diff --git a/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml b/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml index e3e292fefa5b5..21793683482bb 100644 --- a/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml +++ b/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml @@ -22,6 +22,12 @@ properties: Data/command gpio pin. Required when using 4 wire SPI mode (Mode C1). Set to low when sending a command, or high when sending data. + te-gpios: + type: phandle-array + description: | + Tearing Effect GPIO pin. Set to high when the display is blanking + (i.e., not actively reading pixels from its RAM). + reset-gpios: type: phandle-array description: | diff --git a/dts/bindings/misc/st,stm32-npu.yaml b/dts/bindings/misc/st,stm32-npu.yaml new file mode 100644 index 0000000000000..84cb2e047d15b --- /dev/null +++ b/dts/bindings/misc/st,stm32-npu.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +description: STM32 Neural-ART accelerator + +compatible: "st,stm32-npu" + +include: [reset-device.yaml, base.yaml] + +properties: + reg: + required: true + + clocks: + required: true + + resets: + required: true diff --git a/dts/bindings/mtd/atmel,at25xv021a.yaml b/dts/bindings/mtd/atmel,at25xv021a.yaml new file mode 100644 index 0000000000000..a3e7cf45fc8a7 --- /dev/null +++ b/dts/bindings/mtd/atmel,at25xv021a.yaml @@ -0,0 +1,60 @@ +# Copyright (c) 2025 Cirrus Logic, Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: | + AT25XV021A SPI flash variants + + Example datasheet: https://www.renesas.com/en/document/dst/at25xv021a-datasheet + + The AT25XV021A variants add sector protect and unprotect features, which + requires additional steps to program or erase data from the device when compared + to other devices in the AT25 family. + +compatible: "atmel,at25xv021a" + +include: "spi-device.yaml" + +properties: + jedec-id: + type: uint8-array + default: [0x1f, 0x43, 0x01] + description: JEDEC Standard ID + + size: + type: int + required: true + description: Flash capacity in bytes. + + page-size: + type: int + required: true + description: Flash page size in bytes. + + timeout: + type: int + default: 3 + description: | + Timeout for read/write operations in milliseconds. Per the referenced + datasheet, page program operations can take up to 2.5 milliseconds. + + timeout-erase: + type: int + default: 4000 + description: | + Timeout for erase operations (including chip erase) in milliseconds. + Per the referenced datasheet, chip erase can take up to 4 seconds. + + read-only: + type: boolean + description: Set flash device to be read-only. + + ultra-deep-sleep: + type: boolean + description: Go into ultra deep sleep mode instead of deep sleep mode. + + wp-gpios: + type: phandle-array + description: | + The WP pin of AT25XV021A is active low. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/mtd/jedec,jesd216.yaml b/dts/bindings/mtd/jedec,jesd216.yaml index c55440456c2ac..d5f75c74dd3d3 100644 --- a/dts/bindings/mtd/jedec,jesd216.yaml +++ b/dts/bindings/mtd/jedec,jesd216.yaml @@ -35,6 +35,18 @@ properties: information in cases were runtime retrieval of SFDP data is not desired. + sfdp-ff05: + type: uint8-array + description: | + Contains the 32-bit words in little-endian byte order from the JESD216 + SFDP xSPI Profile 1.0 table. + + sfdp-ff84: + type: uint8-array + description: | + Contains the 32-bit words in little-endian byte order from the JESD216 + SFDP 4-byte Address Instruction Parameter table. + quad-enable-requirements: type: string enum: diff --git a/dts/bindings/mtd/jedec,mspi-nor.yaml b/dts/bindings/mtd/jedec,mspi-nor.yaml index 09660b841591e..348e11cd98339 100644 --- a/dts/bindings/mtd/jedec,mspi-nor.yaml +++ b/dts/bindings/mtd/jedec,mspi-nor.yaml @@ -5,7 +5,20 @@ description: Generic NOR flash on MSPI bus compatible: "jedec,mspi-nor" -include: [mspi-device.yaml, "jedec,spi-nor-common.yaml"] +include: + - name: mspi-device.yaml + - name: jedec,spi-nor-common.yaml + property-allowlist: + - jedec-id + - size + - sfdp-bfp + - sfdp-ff05 + - sfdp-ff84 + - quad-enable-requirements + - has-dpd + - dpd-wakeup-sequence + - t-enter-dpd + - t-exit-dpd properties: reset-gpios: @@ -22,6 +35,8 @@ properties: type: int description: | Minimum time, in nanoseconds, the flash chip needs to recover after reset. + Such delay is performed when a GPIO or software reset is done, or after + power is supplied to the chip if the "supply-gpios" property is specified. transfer-timeout: type: int @@ -30,3 +45,18 @@ properties: Maximum time, in milliseconds, allowed for a single transfer on the MSPI bus in communication with the flash chip. The default value is the one that was previously hard-coded in the flash_mspi_nor driver. + + use-4byte-addressing: + type: boolean + description: | + Indicates that 4-byte addressing is to be used in communication with + the flash chip. The driver will use dedicated 4-byte address instruction + codes for commands that require addresses (like Read, Page Program, + or Erase) if those are supported by the flash chip, or if necessary, + it will switch the chip to 4-byte addressing mode. + + initial-soft-reset: + type: boolean + description: | + When set, the flash driver performs software reset of the flash chip + at initialization. diff --git a/dts/bindings/mtd/renesas,ra-qspi-nor.yaml b/dts/bindings/mtd/renesas,ra-qspi-nor.yaml new file mode 100644 index 0000000000000..46d85f2ad9ef2 --- /dev/null +++ b/dts/bindings/mtd/renesas,ra-qspi-nor.yaml @@ -0,0 +1,27 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA QSPI FLASH + +compatible: "renesas,ra-qspi-nor" + +include: [base.yaml] + +on-bus: qspi + +properties: + reg: + required: true + description: Flash Memory base address and size in bytes + + erase-block-size: + type: int + description: address alignment required by flash erase operations + + write-block-size: + type: int + description: address alignment required by flash write operations + + qpi-enable: + type: boolean + description: Enable Quad SPI protocol (QPI) (4-4-4) diff --git a/dts/bindings/p_state/zephyr,native-sim-pstate.yaml b/dts/bindings/p_state/zephyr,native-sim-pstate.yaml new file mode 100644 index 0000000000000..d8a4803836b5f --- /dev/null +++ b/dts/bindings/p_state/zephyr,native-sim-pstate.yaml @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +description: Native Sim mock implementation of custom properties for performance state (pstate) + +compatible: "zephyr,native-sim-pstate" + +include: "zephyr,pstate.yaml" + +properties: + pstate-id: + type: int + required: true + description: | + Identifier of performance state. diff --git a/dts/bindings/p_state/zephyr,pstate.yaml b/dts/bindings/p_state/zephyr,pstate.yaml new file mode 100644 index 0000000000000..aeec540e8222e --- /dev/null +++ b/dts/bindings/p_state/zephyr,pstate.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +description: Common properties for performance states (pstate) + +compatible: "zephyr,pstate" + +properties: + load-threshold: + type: int + description: | + CPU load threshold, in percent, for entering this performance state. Once + the CPU load exceeds this threshold, it becomes a valid performance state + for the P-state driver to switch to. diff --git a/dts/bindings/phy/st,stm32u5-otghs-phy.yaml b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml index 6a316dd71528b..aa9373b306a18 100644 --- a/dts/bindings/phy/st,stm32u5-otghs-phy.yaml +++ b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml @@ -22,19 +22,19 @@ properties: Supported configurations: /* HSE */ - clocks = <&rcc STM32_CLOCK(AHB2, 15U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 15)>, <&rcc STM32_SRC_HSE OTGHS_SEL(0)>; /* HSE/2 */ - clocks = <&rcc STM32_CLOCK(AHB2, 15U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 15)>, <&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) OTGHS_SEL(2)>; /* PLL1_P_CK */ - clocks = <&rcc STM32_CLOCK(AHB2, 15U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 15)>, <&rcc STM32_SRC_PLL1_P OTGHS_SEL(1)>; /* PLL1_P_CK/2 */ - clocks = <&rcc STM32_CLOCK(AHB2, 15U)>, + clocks = <&rcc STM32_CLOCK(AHB2, 15)>, <&rcc (STM32_SRC_PLL1_P | STM32_CLOCK_DIV(2)) OTGHS_SEL(3)>; clock-reference: diff --git a/dts/bindings/pwm/infineon,cat1-pwm.yaml b/dts/bindings/pwm/infineon,cat1-pwm.yaml deleted file mode 100644 index 42408ea62d9f2..0000000000000 --- a/dts/bindings/pwm/infineon,cat1-pwm.yaml +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -description: Infineon CAT1 PWM - -compatible: "infineon,cat1-pwm" - -include: [pwm-controller.yaml, pinctrl-device.yaml, "infineon,system-interrupts.yaml"] - -properties: - reg: - type: array - required: true - - interrupts: - type: array - description: Required for non-cat1c devices - - system-interrupts: - description: Required for cat1c devices - - pinctrl-0: - description: | - PORT pin configuration for the PWM signal. - We expect that the phandles will reference pinctrl nodes. These - nodes will have a nodelabel that matches the Infineon SoC Pinctrl - defines and have following - format: p___. - - Examples: - pinctrl-0 = <&p1_1_pwm0_0>; - required: true - - pinctrl-names: - required: true - - resolution: - type: int - - divider-type: - type: int - description: | - Specifies which type of divider to use. - Defined by cy_en_divider_types_t in cy_sysclk.h. - required: true - - divider-sel: - type: int - description: | - Specifies which divider of the selected type to configure. - required: true - - divider-val: - type: int - description: | - Causes integer division of (divider value + 1), or division by 1 to 256 - (8-bit divider) or 1 to 65536 (16-bit divider). - required: true - - "#pwm-cells": - const: 3 - description: | - Number of items to expect in a PWM - - channel of the timer used for PWM (not used) - - period to set in ns - - flags: standard flags like PWM_POLARITY_NORMAL - -pwm-cells: - - channel - - period - - flags diff --git a/dts/bindings/pwm/infineon,tcpwm-pwm.yaml b/dts/bindings/pwm/infineon,tcpwm-pwm.yaml new file mode 100644 index 0000000000000..0d76bd907a567 --- /dev/null +++ b/dts/bindings/pwm/infineon,tcpwm-pwm.yaml @@ -0,0 +1,39 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +description: Infineon TCPWM PWM + +compatible: "infineon,tcpwm-pwm" + +include: [pwm-controller.yaml, pinctrl-device.yaml, "infineon,system-interrupts.yaml"] + +properties: + "#pwm-cells": + const: 3 + description: | + Number of items to expect in a PWM + - channel of the timer used for PWM (not used) + - period to set in ns + - flags: standard flags like PWM_POLARITY_NORMAL + + pinctrl-0: + description: | + PORT pin configuration for the PWM signal. + We expect that the phandles will reference pinctrl nodes. These + nodes will have a nodelabel that matches the Infineon SoC Pinctrl + defines and have following + format: p___. + + Examples: + pinctrl-0 = <&p1_1_pwm0_0>; + required: true + + pinctrl-names: + required: true + +pwm-cells: + - channel + - period + - flags diff --git a/dts/bindings/pwm/intel,blinky-pwm.yaml b/dts/bindings/pwm/intel,blinky-pwm.yaml index 10822317c09b1..97db3146e332c 100644 --- a/dts/bindings/pwm/intel,blinky-pwm.yaml +++ b/dts/bindings/pwm/intel,blinky-pwm.yaml @@ -27,6 +27,14 @@ properties: required: true description: Maximum number of pins supported by platform + reg-upper32: + type: int + default: 0 + description: | + Few platforms have 64 bit PWM register address, + this property will be used to share the higher + 32 bits(63-32). + "#pwm-cells": const: 2 diff --git a/dts/bindings/pwm/nxp,ftm-pwm.yaml b/dts/bindings/pwm/nxp,ftm-pwm.yaml index a07fe5945feef..f444b5ef9ab43 100644 --- a/dts/bindings/pwm/nxp,ftm-pwm.yaml +++ b/dts/bindings/pwm/nxp,ftm-pwm.yaml @@ -1,4 +1,4 @@ -# Copyright 2017, 2024 NXP +# Copyright 2017, 2024-2025 NXP # SPDX-License-Identifier: Apache-2.0 description: NXP FlexTimer Module (FTM) PWM controller @@ -14,25 +14,6 @@ properties: pinctrl-0: required: true - clock-source: - type: string - required: true - enum: - - "system" - - "fixed" - - "external" - description: | - Select one of three possible clock sources for the FTM counter: - * system: it's the bus interface clock driving the FTM module. Usually - provides higher timer resolution than the other two clock sources. - * fixed: it's a fixed clock defined by chip integration. - * external: it's a clock that can be accessed externally to the chip and - passes through a sychronizer clocked by the FTM bus interface clock. - - This clock source selection is independent of the bus interface clock - driving the FTM module. Refer to the chip specific documentation for - further information. - pwm-cells: - channel # period in terms of nanoseconds diff --git a/dts/bindings/pwm/ti,mspm0-pwm.yaml b/dts/bindings/pwm/ti,mspm0-pwm.yaml index 7ccb9656612eb..339249d5e9e67 100644 --- a/dts/bindings/pwm/ti,mspm0-pwm.yaml +++ b/dts/bindings/pwm/ti,mspm0-pwm.yaml @@ -7,7 +7,7 @@ description: | timer0: timer { pwm0: pwm { - compatible = "ti,mspm0g-timer-pwm"; + compatible = "ti,mspm0-timer-pwm"; #pwm-cells = <3>; ti,cc-index = <0>; diff --git a/dts/bindings/qspi/renesas,ra-qspi.yaml b/dts/bindings/qspi/renesas,ra-qspi.yaml new file mode 100644 index 0000000000000..a19cbc4cbc9e4 --- /dev/null +++ b/dts/bindings/qspi/renesas,ra-qspi.yaml @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA QSPI + +compatible: "renesas,ra-qspi" + +include: [base.yaml, pinctrl-device.yaml] + +bus: qspi + +properties: + reg: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml b/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml index f204d1679a4fe..016675dbf01ff 100644 --- a/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml +++ b/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml @@ -30,3 +30,8 @@ properties: type: boolean description: | Enables setting VPR core's secure attribute to secure. + + enable-dma-secure: + type: boolean + description: | + Enables setting VPR core's DMA secure attribute to secure. diff --git a/dts/bindings/rx/renesas,rx-swint.yaml b/dts/bindings/rx/renesas,rx-swint.yaml new file mode 100644 index 0000000000000..e510f6a2b7bae --- /dev/null +++ b/dts/bindings/rx/renesas,rx-swint.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RX SWINT (Software Interrupt) + +compatible: "renesas,rx-swint" + +include: base.yaml + +properties: + reg: + required: true + + interrupts: + required: true diff --git a/dts/bindings/sensor/st,lsm9ds1.yaml b/dts/bindings/sensor/st,lsm9ds1.yaml index 88fc8ea662cb5..8cdde3af703d1 100644 --- a/dts/bindings/sensor/st,lsm9ds1.yaml +++ b/dts/bindings/sensor/st,lsm9ds1.yaml @@ -2,8 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STMicroelectronics LSM9DS1 9-axis IMU (Inertial Measurement Unit) sensor - accessed through I2C bus. + STMicroelectronics LSM9DS1 3-axis accelerometer + gyroscope accessed + through I2C bus. This binding describe only the inertial part : accelerometer and gyroscope. diff --git a/dts/bindings/sensor/st,lsm9ds1_mag.yaml b/dts/bindings/sensor/st,lsm9ds1_mag.yaml index 4493c42c34f9c..e7647c09e71a6 100644 --- a/dts/bindings/sensor/st,lsm9ds1_mag.yaml +++ b/dts/bindings/sensor/st,lsm9ds1_mag.yaml @@ -2,8 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STMicroelectronics LSM9DS1 9-axis IMU (Inertial Measurement Unit) sensor - accessed through I2C bus. + STMicroelectronics LSM9DS1-MAG 3-axis magnetometer accessed + through I2C bus. This binding describes only the magnetometer. diff --git a/dts/bindings/sensor/we,wsen-isds-2536030320001-common.yaml b/dts/bindings/sensor/we,wsen-isds-2536030320001-common.yaml new file mode 100644 index 0000000000000..266bac00f7466 --- /dev/null +++ b/dts/bindings/sensor/we,wsen-isds-2536030320001-common.yaml @@ -0,0 +1,194 @@ +# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +properties: + events-interrupt-gpios: + type: phandle-array + description: | + Events Interrupt pin (Tap, Freefall, .. etc) (INT0 Pin). + Interrupts are active high by default. + + drdy-interrupt-gpios: + type: phandle-array + description: | + DRDY Interrupt pin (INT1 Pin). + Interrupts are active high by default. + + accel-odr: + type: string + required: true + enum: + - "0" # Accelerometer turned off + - "12.5" + - "26" + - "52" + - "104" + - "208" + - "416" + - "833" + - "1660" + - "3330" + - "6660" + - "1.6" + description: Accelerometer output data rate in Hz + + accel-range: + type: int + default: 2 + enum: + - 2 # 2g + - 16 # 16g + - 4 # 4g + - 8 # 8g + description: Accelerometer range (full scale) in g. Defaults to 2, which is + the configuration at power-up. + + gyro-odr: + type: string + required: true + enum: + - "0" # Gyroscope turned off + - "12.5" + - "26" + - "52" + - "104" + - "208" + - "416" + - "833" + - "1660" + - "3330" + - "6660" + description: Gyroscope output data rate in Hz + + gyro-range: + type: int + default: 250 + enum: + - 250 + - 125 + - 500 + - 1000 + - 2000 + description: Gyroscope range (full scale) in degrees per second. Defaults to 250, + which is the configuration at power-up. + + tap-mode: + type: int + default: 0 + enum: + - 0 # Only single tap + - 1 # Single and double tap + description: Tap mode (only single tap or single and double tap). + Defaults to 0, which is the configuration at power-up. + + tap-threshold: + type: int + default: 0 + description: | + Tap X/Y/Z axis threshold (unsigned 5-bit, ranging from 0x00 to 0x1F). + Defaults to zero, which is the configuration at power-up. + + Threshold for tap recognition on the X/Y/Z axes depending on selected + measurement range (full scale). + + Example: + + tap-threshold = <6> + + For FS=2g, this sets the threshold to 6 \* 2g/32 = 375mg. + + tap-axis-enable: + type: array + default: [1, 1, 1] + description: | + Enable/disable tap recognition on X/Y/Z axis. + + Defaults to "<1>, <1>, <1>", i.e. tap recognition enabled for all three axes. + Setting elements of this array to zero disables tap recognition for the + corresponding axes. + + tap-shock: + type: int + default: 0x0 + description: | + Maximum duration of over-threshold event when detecting taps (unsigned + 2-bit, ranging from 0x0 to 0x3). Defaults to zero, which is the + configuration at power-up. + + A value of 0 corresponds to 4 \* 1/ODR and 1 LSB = 8 \* 1/ODR. + + tap-latency: + type: int + default: 0x0 + description: | + Maximum duration time gap for double-tap recognition (unsigned 4-bit, + ranging from 0x0 to 0xF). Defaults to zero, which is the + configuration at power-up. + + A value of 0 corresponds to 16 \* 1/ODR and 1 LSB = 32 \* 1/ODR. + + tap-quiet: + type: int + default: 0x0 + description: | + Expected quiet time for double-tap recognition (unsigned 2-bit, ranging + from 0x0 to 0x3). This defines the time after the first detected tap in + which there must not be any over-threshold event. Defaults to zero, which + is the configuration at power-up. + + A value of 0 corresponds to 2 \* 1/ODR and 1 LSB = 4 \* 1/ODR. + + freefall-duration: + type: int + default: 0x0 + description: | + Minimum duration of free-fall event (unsigned 6-bit, ranging from 0x0 + to 0x3F). Defaults to 0, which is the configuration at power-up. + + 1 LSB = 1 \* 1/ODR. + + freefall-threshold: + type: int + default: 0x0 + enum: + - 0 # 156 mg + - 1 # 219 mg + - 2 # 250 mg + - 3 # 312 mg + - 4 # 344 mg + - 5 # 406 mg + - 6 # 469 mg + - 7 # 500 mg + description: | + Free-fall threshold (amplitude of the "free-fall zone" around zero-g + level where the accelerations of all axes are small enough to generate + the free-fall interrupt). Defaults to 0, which is the configuration + at power-up. + + delta-duration: + type: int + default: 0x0 + enum: + - 0 + - 1 + - 2 + - 3 + description: | + Wake-up duration, i.e. minimum duration of wake-up event to be + recognized (unsigned 2-bit, ranging from 0x0 to 0x3). + Defaults to 0, which is the configuration at power-up. + + 1 LSB = 1 \* 1/ODR + + delta-threshold: + type: int + default: 0x0 + description: | + Wake-up threshold (unsigned 6-bit, ranging from 0x0 to 0x3F). + The threshold value is applicable to both positive and negative + acceleration data. A wake-up event is recognized, if at least + one of the acceleration axis values exceeds the threshold value. + + Defaults to 0, which is the configuration at power-up. + + 1 LSB = 1/64 of measurement range (full scale). diff --git a/dts/bindings/sensor/we,wsen-isds-2536030320001-i2c.yaml b/dts/bindings/sensor/we,wsen-isds-2536030320001-i2c.yaml new file mode 100644 index 0000000000000..18d0ac3eb3538 --- /dev/null +++ b/dts/bindings/sensor/we,wsen-isds-2536030320001-i2c.yaml @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +description: | + Würth Elektronik WSEN-ISDS-2536030320001 acceleration and gyroscope sensor with + integrated temperature sensor (I2C bus) + +compatible: "we,wsen-isds-2536030320001" + +include: ["i2c-device.yaml", "we,wsen-isds-2536030320001-common.yaml"] diff --git a/dts/bindings/sensor/we,wsen-isds-2536030320001-spi.yaml b/dts/bindings/sensor/we,wsen-isds-2536030320001-spi.yaml new file mode 100644 index 0000000000000..b6f4f49c7f3e4 --- /dev/null +++ b/dts/bindings/sensor/we,wsen-isds-2536030320001-spi.yaml @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +description: | + Würth Elektronik WSEN-ISDS-2536030320001 acceleration and gyroscope sensor with + integrated temperature sensor (SPI bus) + +compatible: "we,wsen-isds-2536030320001" + +include: ["spi-device.yaml", "we,wsen-isds-2536030320001-common.yaml"] diff --git a/dts/bindings/timer/infineon,tcpwm.yaml b/dts/bindings/timer/infineon,tcpwm.yaml new file mode 100644 index 0000000000000..70411440a3723 --- /dev/null +++ b/dts/bindings/timer/infineon,tcpwm.yaml @@ -0,0 +1,48 @@ +# Copyright (c) 2025 Infineon Technologies AG, +# or an affiliate of Infineon Technologies AG. +# +# SPDX-License-Identifier: Apache-2.0 + +description: Infineon CAT1 TCPWM (Timer/Counter/PWM) node + +compatible: "infineon,tcpwm" + +include: base.yaml + +properties: + reg: + type: array + required: true + description: Register base address and size information + + interrupts: + type: array + description: Interrupt mapping for TCPWM instance + + divider-type: + type: int + description: | + Specifies which type of divider to use. + Defined by cy_en_divider_types_t in cy_sysclk.h. + required: true + + divider-sel: + type: int + description: | + Specifies which divider of the selected type to configure. + required: true + + divider-val: + type: int + description: | + Causes integer division of (divider value + 1), or division by 1 to 256 + (8-bit divider) or 1 to 65536 (16-bit divider). + required: true + + resolution: + type: int + required: true + description: Counter/timer resolution (16 or 32 bits) + enum: + - 16 + - 32 diff --git a/dts/bindings/timer/nxp,ftm.yaml b/dts/bindings/timer/nxp,ftm.yaml index 064f7ab9f8a24..43a4316083ace 100644 --- a/dts/bindings/timer/nxp,ftm.yaml +++ b/dts/bindings/timer/nxp,ftm.yaml @@ -1,4 +1,4 @@ -# Copyright (c) 2017, NXP +# Copyright (c) 2017, 2025 NXP # SPDX-License-Identifier: Apache-2.0 description: NXP FlexTimer Module (FTM) @@ -27,3 +27,22 @@ properties: - 64 - 128 description: Input clock prescaler + + clock-source: + type: string + required: true + enum: + - "system" + - "fixed" + - "external" + description: | + Select one of three possible clock sources for the FTM counter: + * system: it's the bus interface clock driving the FTM module. Usually + provides higher timer resolution than the other two clock sources. + * fixed: it's a fixed clock defined by chip integration. + * external: it's a clock that can be accessed externally to the chip and + passes through a sychronizer clocked by the FTM bus interface clock. + + This clock source selection is independent of the bus interface clock + driving the FTM module. Refer to the chip specific documentation for + further information. diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index c917e337099d6..bc00b613813e9 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -247,6 +247,7 @@ festo Festo SE & Co. KG fii Foxconn Industrial Internet fintek Feature Integration Technology Inc. firefly Firefly +fobe FoBE Studio focaltech FocalTech Systems Co.,Ltd franzininho Franzininho frida Shenzhen Frida LCD Co., Ltd. diff --git a/dts/bindings/video/st,stm32-dcmipp.yaml b/dts/bindings/video/st,stm32-dcmipp.yaml index 125554dad72e4..7aaaa8521e0c7 100644 --- a/dts/bindings/video/st,stm32-dcmipp.yaml +++ b/dts/bindings/video/st,stm32-dcmipp.yaml @@ -48,9 +48,8 @@ properties: child-binding: child-binding: - child-binding: - include: video-interfaces.yaml + include: video-interfaces.yaml - properties: - bus-type: - required: true + properties: + bus-type: + required: true diff --git a/dts/bindings/video/video-interfaces.yaml b/dts/bindings/video/video-interfaces.yaml index fb17d69462770..98b3b1835b76c 100644 --- a/dts/bindings/video/video-interfaces.yaml +++ b/dts/bindings/video/video-interfaces.yaml @@ -81,7 +81,7 @@ properties: data-shift: type: int description: | - On parallel data busses, if bus-width is used to specify the number of + On parallel data buses, if bus-width is used to specify the number of data lines, data-shift can be used to specify which data lines are used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used. @@ -123,7 +123,7 @@ properties: Physical clock lane index. Position of an entry determines the logical lane number, while the value of an entry indicates physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lane = <0>;", which places the - clock lane on hardware lane 0. This property is valid for serial busses + clock lane on hardware lane 0. This property is valid for serial buses only (e.g. MIPI CSI-2). data-lanes: @@ -135,10 +135,10 @@ properties: assuming the clock lane is on hardware lane 0. If the hardware does not support lane reordering, monotonically incremented values shall be used from 0 or 1 onwards, depending on whether or not there is also a clock - lane. This property is valid for serial busses only (e.g. MIPI CSI-2). + lane. This property is valid for serial buses only (e.g. MIPI CSI-2). # For parallel bus only bus-width: type: int description: | - Number of data lines actively used, only valid for parallel busses. + Number of data lines actively used, only valid for parallel buses. diff --git a/dts/riscv/bflb/bl61x.dtsi b/dts/riscv/bflb/bl61x.dtsi index 5e4de9d544e95..6a0b3d050dcaf 100644 --- a/dts/riscv/bflb/bl61x.dtsi +++ b/dts/riscv/bflb/bl61x.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include / { #address-cells = <1>; @@ -115,7 +117,7 @@ status = "okay"; gpio0: gpio@20000000 { - compatible = "bflb,gpio"; + compatible = "bflb,bl61x-gpio"; reg = <0x20000000 0x1000>; #gpio-cells = <2>; #bflb,pin-cells = <2>; @@ -156,9 +158,9 @@ status = "disabled"; }; - uart1: uart@4000a100 { + uart1: uart@2000a100 { compatible = "bflb,uart"; - reg = <0x4000a100 0x100>; + reg = <0x2000a100 0x100>; interrupts = <45 1>; interrupt-parent = <&clic>; status = "disabled"; diff --git a/dts/riscv/espressif/esp32h2/esp32h2_common.dtsi b/dts/riscv/espressif/esp32h2/esp32h2_common.dtsi new file mode 100644 index 0000000000000..dac7b6ec9959c --- /dev/null +++ b/dts/riscv/espressif/esp32h2/esp32h2_common.dtsi @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + die-temp0 = &coretemp; + }; + + chosen { + zephyr,canbus = &twai; + zephyr,entropy = &trng0; + zephyr,flash-controller = &flash; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "espressif,riscv"; + riscv,isa = "rv32imac_zicsr"; + reg = <0>; + clock-source = ; + clock-frequency = ; + xtal-freq = ; + }; + }; + + pinctrl: pin-controller { + compatible = "espressif,esp32-pinctrl"; + status = "okay"; + }; + + clock: clock { + compatible = "espressif,esp32-clock"; + fast-clk-src = ; + slow-clk-src = ; + #clock-cells = <1>; + status = "okay"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + sramhp: memory@40800000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x40800000 DT_SIZE_K(320)>; + zephyr,memory-region = "SRAMHP"; + }; + + sramlp: memory@50000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x50000000 DT_SIZE_K(4)>; + zephyr,memory-region = "SRAMLP"; + }; + + intc: interrupt-controller@60010000 { + compatible = "espressif,esp32-intc"; + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60010000 DT_SIZE_K(4)>; + status = "okay"; + }; + + systimer0: systimer@6000b000 { + compatible = "espressif,esp32-systimer"; + reg = <0x6000B000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + status = "okay"; + }; + + timer0: counter@60009000 { + compatible = "espressif,esp32-timer"; + reg = <0x60009000 DT_SIZE_K(4)>; + clocks = <&clock ESP32_TIMG0_MODULE>; + group = <0>; + index = <0>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + + counter { + compatible = "espressif,esp32-counter"; + status = "disabled"; + }; + }; + + timer1: counter@6000a000 { + compatible = "espressif,esp32-timer"; + reg = <0x6000A000 DT_SIZE_K(4)>; + clocks = <&clock ESP32_TIMG1_MODULE>; + group = <1>; + index = <0>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + + counter { + compatible = "espressif,esp32-counter"; + status = "disabled"; + }; + }; + + rtc_timer: rtc_timer@600b0c00 { + compatible = "espressif,esp32-rtc_timer"; + reg = <0x600B0C00 DT_SIZE_K(1)>; + clocks = <&clock ESP32_MODULE_MAX>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + trng0: trng@600b2808 { + compatible = "espressif,esp32-trng"; + reg = <0x600B2808 0x4>; + clocks = <&clock ESP32_RNG_MODULE>; + status = "disabled"; + }; + + wdt0: watchdog@60009048 { + compatible = "espressif,esp32-watchdog"; + reg = <0x60009048 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_TIMG0_MODULE>; + status = "disabled"; + }; + + wdt1: watchdog@6000a048 { + compatible = "espressif,esp32-watchdog"; + reg = <0x6000A048 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_TIMG1_MODULE>; + status = "disabled"; + }; + + flash: flash-controller@60002000 { + compatible = "espressif,esp32-flash-controller"; + reg = <0x60002000 DT_SIZE_K(4)>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + erase-block-size = <4096>; + write-block-size = <4>; + /* Flash size is specified in SOC/SIP dtsi */ + }; + }; + + coretemp: coretemp@6000e058 { + compatible = "espressif,esp32-temp"; + friendly-name = "coretemp"; + reg = <0x6000E058 0x4>; + status = "disabled"; + }; + + gpio0: gpio@60091000 { + compatible = "espressif,esp32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60091000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + ngpios = <32>; + gpio-reserved-ranges = + <6 2>, /* GPIO6–7 */ + <15 7>, /* GPIO15–21 */ + <28 4>; /* GPIO28–31 */ + }; + + uart0: uart@60000000 { + compatible = "espressif,esp32-uart"; + reg = <0x60000000 DT_SIZE_K(4)>; + status = "disabled"; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_UART0_MODULE>; + }; + + uart1: uart@60001000 { + compatible = "espressif,esp32-uart"; + reg = <0x60001000 DT_SIZE_K(4)>; + status = "disabled"; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_UART1_MODULE>; + }; + + usb_serial: uart@6000f000 { + compatible = "espressif,esp32-usb-serial"; + reg = <0x6000F000 DT_SIZE_K(4)>; + status = "disabled"; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_USB_DEVICE_MODULE>; + }; + + spi2: spi@60081000 { + compatible = "espressif,esp32-spi"; + reg = <0x60081000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_SPI2_MODULE>; + dma-host = <0>; + status = "disabled"; + }; + + dma: dma@60080000 { + compatible = "espressif,esp32-gdma"; + reg = <0x60080000 DT_SIZE_K(4)>; + #dma-cells = <1>; + interrupts = + , + , + , + , + , + ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_GDMA_MODULE>; + dma-channels = <6>; + dma-buf-addr-alignment = <4>; + status = "disabled"; + }; + + i2c0: i2c@60004000 { + compatible = "espressif,esp32-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60004000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_I2C0_MODULE>; + status = "disabled"; + }; + + i2c1: i2c@60005000 { + compatible = "espressif,esp32-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60005000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_I2C1_MODULE>; + status = "disabled"; + }; + + i2s: i2s@6000d000 { + compatible = "espressif,esp32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6000D000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_I2S1_MODULE>; + unit = <0>; + status = "disabled"; + }; + + adc0: adc@6000e000 { + compatible = "espressif,esp32-adc"; + reg = <0x6000E000 0x4>; + clocks = <&clock ESP32_SARADC_MODULE>; + unit = <1>; + channel-count = <5>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + ledc0: ledc@60008000 { + compatible = "espressif,esp32-ledc"; + pwm-controller; + #pwm-cells = <3>; + reg = <0x60008000 DT_SIZE_K(4)>; + clocks = <&clock ESP32_LEDC_MODULE>; + status = "disabled"; + }; + + mcpwm0: mcpwm@60014000 { + compatible = "espressif,esp32-mcpwm"; + reg = <0x60014000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_MCPWM0_MODULE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + twai: can@6000c000 { + compatible = "espressif,esp32-twai"; + reg = <0x6000c000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_TWAI0_MODULE>; + status = "disabled"; + }; + + pcnt: pcnt@60012000 { + compatible = "espressif,esp32-pcnt"; + reg = <0x60012000 DT_SIZE_K(4)>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&clock ESP32_PCNT_MODULE>; + status = "disabled"; + }; + }; +}; diff --git a/dts/riscv/espressif/esp32h2/esp32h2_mini_h2.dtsi b/dts/riscv/espressif/esp32h2/esp32h2_mini_h2.dtsi new file mode 100644 index 0000000000000..e67b0e6475ad4 --- /dev/null +++ b/dts/riscv/espressif/esp32h2/esp32h2_mini_h2.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include "esp32h2_common.dtsi" + +/* 2MB flash */ +&flash0 { + reg = <0x0 DT_SIZE_M(2)>; +}; diff --git a/dts/riscv/espressif/esp32h2/esp32h2_mini_h4.dtsi b/dts/riscv/espressif/esp32h2/esp32h2_mini_h4.dtsi new file mode 100644 index 0000000000000..e4de9fd312f97 --- /dev/null +++ b/dts/riscv/espressif/esp32h2/esp32h2_mini_h4.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include "esp32h2_common.dtsi" + +/* 4MB flash */ +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; diff --git a/dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h2.dtsi b/dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h2.dtsi new file mode 100644 index 0000000000000..e67b0e6475ad4 --- /dev/null +++ b/dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h2.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include "esp32h2_common.dtsi" + +/* 2MB flash */ +&flash0 { + reg = <0x0 DT_SIZE_M(2)>; +}; diff --git a/dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h4.dtsi b/dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h4.dtsi new file mode 100644 index 0000000000000..e4de9fd312f97 --- /dev/null +++ b/dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h4.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include "esp32h2_common.dtsi" + +/* 4MB flash */ +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; diff --git a/dts/riscv/ite/it51xxx.dtsi b/dts/riscv/ite/it51xxx.dtsi index 1e417c7431c44..b46b98d6d5d13 100644 --- a/dts/riscv/ite/it51xxx.dtsi +++ b/dts/riscv/ite/it51xxx.dtsi @@ -971,6 +971,14 @@ #wuc-cells = <1>; }; + bbram: bb-ram@f02200 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ite,it8xxx2-bbram"; + status = "okay"; + reg = <0x00f02200 0x80>; + }; + i2cbase: i2cbase@f04100 { compatible = "ite,it51xxx-i2cbase"; reg = <0x00f04100 1 diff --git a/dts/rx/renesas/rx-qemu.dtsi b/dts/rx/renesas/rx-qemu.dtsi index 1fb6442eb99d9..1737456b4a550 100644 --- a/dts/rx/renesas/rx-qemu.dtsi +++ b/dts/rx/renesas/rx-qemu.dtsi @@ -22,7 +22,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "renesas,rx"; + compatible = "renesas,rxv1"; device_type = "cpu"; reg = <0>; status = "okay"; @@ -31,6 +31,8 @@ icu: interrupt-controller@87000 { #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; compatible = "renesas,rx-icu"; interrupt-controller; reg = <0x0087000 0xff>, @@ -40,7 +42,15 @@ <0x0087500 0x0f>, <0x0087510 0x01>, <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR","IRQCR","IRQFLTE","IRQFLTC0"; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; + + swint1: swint1@872e0 { + compatible = "renesas,rx-swint"; + reg = <0x000872e0 0x01>; + interrupts = <27 14>; + interrupt-parent = <&icu>; + status = "okay"; + }; }; clocks: clocks { diff --git a/dts/rx/renesas/rx130-common.dtsi b/dts/rx/renesas/rx130-common.dtsi index b7dd10272de39..428de7456b386 100644 --- a/dts/rx/renesas/rx130-common.dtsi +++ b/dts/rx/renesas/rx130-common.dtsi @@ -22,7 +22,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "renesas,rx"; + compatible = "renesas,rxv1"; device_type = "cpu"; reg = <0>; status = "okay"; @@ -31,6 +31,8 @@ icu: interrupt-controller@87000 { #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; compatible = "renesas,rx-icu"; interrupt-controller; reg = <0x0087000 0xff>, @@ -40,7 +42,15 @@ <0x0087500 0x0f>, <0x0087510 0x01>, <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR","IRQCR","IRQFLTE","IRQFLTC0"; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR","IRQFLTE","IRQFLTC0"; + + swint1: swint1@872e0 { + compatible = "renesas,rx-swint"; + reg = <0x000872e0 0x01>; + interrupts = <27 14>; + interrupt-parent = <&icu>; + status = "okay"; + }; }; soc { diff --git a/dts/rx/renesas/rx261-common.dtsi b/dts/rx/renesas/rx261-common.dtsi index 49308688966e7..4764af0e72a84 100644 --- a/dts/rx/renesas/rx261-common.dtsi +++ b/dts/rx/renesas/rx261-common.dtsi @@ -20,7 +20,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "renesas,rx"; + compatible = "renesas,rxv3"; device_type = "cpu"; reg = <0>; status = "okay"; @@ -29,6 +29,8 @@ icu: interrupt-controller@87000 { #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; compatible = "renesas,rx-icu"; interrupt-controller; reg = <0x0087000 0xff>, @@ -38,8 +40,16 @@ <0x0087500 0x0f>, <0x0087510 0x01>, <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR","IRQCR","IRQFLTE","IRQFLTC0"; - }; /* icu */ + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; + + swint1: swint1@872e0 { + compatible = "renesas,rx-swint"; + reg = <0x000872e0 0x01>; + interrupts = <27 14>; + interrupt-parent = <&icu>; + status = "okay"; + }; + }; soc { #address-cells = <1>; diff --git a/dts/vendor/amd/versalnet_apu.dtsi b/dts/vendor/amd/versalnet_apu.dtsi new file mode 100644 index 0000000000000..14af3aae67bb8 --- /dev/null +++ b/dts/vendor/amd/versalnet_apu.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + /* + * OCM (On-Chip Memory) is used by TF-A (Trusted Firmware-A) by default. + * Enable this node only if TF-A is not using this memory region or if + * explicit coordination is established between TF-A and Zephyr. + */ + ocm: memory@bbf00000 { + compatible = "zephyr,memory-region"; + reg = <0x0 0xbbf00000 0x0 DT_SIZE_M(1)>; + status = "disabled"; + zephyr,memory-region = "OCM"; + }; + + uart0: uart@f1920000 { + compatible = "arm,sbsa-uart"; + reg = <0x0 0xf1920000 0x0 0x4c>; + status = "disabled"; + interrupt-names = "irq_0"; + interrupts = ; + }; + + uart1: uart@f1930000 { + compatible = "arm,sbsa-uart"; + reg = <0x0 0xf1930000 0x0 0x1000>; + status = "disabled"; + interrupt-names = "irq_1"; + interrupts = ; + }; + }; +}; diff --git a/dts/vendor/nordic/nrf5340_cpuapp_ns_partition.dtsi b/dts/vendor/nordic/nrf5340_cpuapp_ns_partition.dtsi new file mode 100644 index 0000000000000..fdf17828390da --- /dev/null +++ b/dts/vendor/nordic/nrf5340_cpuapp_ns_partition.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright 2024 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + * + * Default memory partitioning for nRF5340 application CPU. + */ + +&flash0 { + /* + * Default Flash planning for nRF5340 series SoCs. + * This layout matches (by necessity) that in the TF-M repository: + * + * 0x0000_0000 BL2 - MCUBoot (64 KB) + * 0x0001_0000 Primary image area (448 KB): + * 0x0001_0000 Secure image primary (256 KB) + * 0x0005_0000 Non-secure image primary (192 KB) + * 0x0008_0000 Secondary image area (448 KB): + * 0x0008_0000 Secure image secondary (256 KB) + * 0x000c_0000 Non-secure image secondary (192 KB) + * 0x000f_0000 Protected Storage Area (16 KB) + * 0x000f_4000 Internal Trusted Storage Area (8 KB) + * 0x000f_6000 OTP / NV counters area (8 KB) + * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x10000>; + }; + + slot0_partition: partition@10000 { + compatible = "fixed-subpartitions"; + label = "image-0"; + reg = <0x00010000 0x70000>; + ranges = <0x0 0x10000 0x70000>; + #address-cells = <1>; + #size-cells = <1>; + + slot0_s_partition: partition@0 { + label = "image-0-secure"; + reg = <0x00000000 0x40000>; + }; + + slot0_ns_partition: partition@40000 { + label = "image-0-nonsecure"; + reg = <0x00040000 0x30000>; + }; + }; + + slot1_partition: partition@80000 { + compatible = "fixed-subpartitions"; + label = "image-1"; + reg = <0x00080000 0x70000>; + ranges = <0x0 0x80000 0x70000>; + #address-cells = <1>; + #size-cells = <1>; + + slot1_s_partition: partition@0 { + label = "image-1-secure"; + reg = <0x00000000 0x40000>; + }; + + slot1_ns_partition: partition@40000 { + label = "image-1-nonsecure"; + reg = <0x00040000 0x30000>; + }; + }; + + tfm_ps_partition: partition@f0000 { + label = "tfm-ps"; + reg = <0x000f0000 0x00004000>; + }; + + tfm_its_partition: partition@f4000 { + label = "tfm-its"; + reg = <0x000f4000 0x00002000>; + }; + + tfm_otp_partition: partition@f6000 { + label = "tfm-otp"; + reg = <0x000f6000 0x00002000>; + }; + + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +#include "nrf5340_sram_partition.dtsi" +#include "nrf5340_shared_sram_partition.dtsi" diff --git a/dts/vendor/nordic/nrf5340_cpuapp_partition.dtsi b/dts/vendor/nordic/nrf5340_cpuapp_partition.dtsi index e16b90addc5e4..37158c092b59e 100644 --- a/dts/vendor/nordic/nrf5340_cpuapp_partition.dtsi +++ b/dts/vendor/nordic/nrf5340_cpuapp_partition.dtsi @@ -1,5 +1,6 @@ /* * Copyright 2024 Embeint Inc + * Copyright (c) 2025 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 * @@ -7,23 +8,6 @@ */ &flash0 { - /* - * Default Flash planning for nRF5340 series SoCs. - * This layout matches (by necessity) that in the TF-M repository: - * - * 0x0000_0000 BL2 - MCUBoot (64 KB) - * 0x0001_0000 Primary image area (448 KB): - * 0x0001_0000 Secure image primary (256 KB) - * 0x0005_0000 Non-secure image primary (192 KB) - * 0x0008_0000 Secondary image area (448 KB): - * 0x0008_0000 Secure image secondary (256 KB) - * 0x000c_0000 Non-secure image secondary (192 KB) - * 0x000f_0000 Protected Storage Area (16 KB) - * 0x000f_4000 Internal Trusted Storage Area (8 KB) - * 0x000f_6000 OTP / NV counters area (8 KB) - * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, - * otherwise unused (32 KB) - */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -35,56 +19,13 @@ }; slot0_partition: partition@10000 { - compatible = "fixed-subpartitions"; label = "image-0"; - reg = <0x00010000 0x70000>; - ranges = <0x0 0x10000 0x70000>; - #address-cells = <1>; - #size-cells = <1>; - - slot0_s_partition: partition@0 { - label = "image-0-secure"; - reg = <0x00000000 0x40000>; - }; - - slot0_ns_partition: partition@40000 { - label = "image-0-nonsecure"; - reg = <0x00040000 0x30000>; - }; + reg = <0x00010000 0x74000>; }; - slot1_partition: partition@80000 { - compatible = "fixed-subpartitions"; + slot1_partition: partition@84000 { label = "image-1"; - reg = <0x00080000 0x70000>; - ranges = <0x0 0x80000 0x70000>; - #address-cells = <1>; - #size-cells = <1>; - - slot1_s_partition: partition@0 { - label = "image-1-secure"; - reg = <0x00000000 0x40000>; - }; - - slot1_ns_partition: partition@40000 { - label = "image-1-nonsecure"; - reg = <0x00040000 0x30000>; - }; - }; - - tfm_ps_partition: partition@f0000 { - label = "tfm-ps"; - reg = <0x000f0000 0x00004000>; - }; - - tfm_its_partition: partition@f4000 { - label = "tfm-its"; - reg = <0x000f4000 0x00002000>; - }; - - tfm_otp_partition: partition@f6000 { - label = "tfm-otp"; - reg = <0x000f6000 0x00002000>; + reg = <0x00084000 0x74000>; }; storage_partition: partition@f8000 { @@ -94,40 +35,5 @@ }; }; -/ { - /* Default SRAM planning when building for nRF5340 with ARM TF-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Upper 256 kB allocated to Non-Secure image (sram0_ns) - * Of the memory allocated to the Non-Secure image - * - 192 kB SRAM allocated to the Non-Secure application (sram0_ns_app). - * - 64 kB allocated to shared memory (sram0_shared). - * (See nrf5340_shared_sram_partition.dtsi) - */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - reg = <0x20000000 DT_SIZE_K(448)>; - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - reg = <0x20000000 0x40000>; - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - reg = <0x20040000 0x40000>; - }; - - sram0_ns_app: image_ns_app@20040000 { - /* Non-Secure image memory */ - reg = <0x20040000 0x30000>; - }; - }; -}; - +#include "nrf5340_sram_partition.dtsi" #include "nrf5340_shared_sram_partition.dtsi" diff --git a/dts/vendor/nordic/nrf5340_sram_partition.dtsi b/dts/vendor/nordic/nrf5340_sram_partition.dtsi new file mode 100644 index 0000000000000..db1d9dd4f1603 --- /dev/null +++ b/dts/vendor/nordic/nrf5340_sram_partition.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright 2024 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* Default SRAM planning when building for nRF5340 with ARM TF-M support + * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) + * - Upper 256 kB allocated to Non-Secure image (sram0_ns) + * Of the memory allocated to the Non-Secure image + * - 192 kB SRAM allocated to the Non-Secure application (sram0_ns_app). + * - 64 kB allocated to shared memory (sram0_shared). + * (See nrf5340_shared_sram_partition.dtsi) + */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_image: image@20000000 { + /* Zephyr image(s) memory */ + reg = <0x20000000 DT_SIZE_K(448)>; + }; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + reg = <0x20000000 0x40000>; + }; + + sram0_ns: image_ns@20040000 { + /* Non-Secure image memory */ + reg = <0x20040000 0x40000>; + }; + + sram0_ns_app: image_ns_app@20040000 { + /* Non-Secure image memory */ + reg = <0x20040000 0x30000>; + }; + }; +}; diff --git a/dts/x86/intel/panther_lake_h.dtsi b/dts/x86/intel/panther_lake_h.dtsi index 8fd5ea216d100..02b216cd713fc 100644 --- a/dts/x86/intel/panther_lake_h.dtsi +++ b/dts/x86/intel/panther_lake_h.dtsi @@ -293,6 +293,17 @@ status = "disabled"; }; + pwm0: pwm@5d0000 { + compatible = "intel,blinky-pwm"; + reg = <0x5d0000 0x500>; + reg-upper32 = <0x40>; + reg-offset = <0x434>; + clock-frequency = <32768>; + max-pins = <1>; + #pwm-cells = <2>; + status = "disabled"; + }; + rtc: counter: rtc@70 { compatible = "motorola,mc146818"; reg = <0x70 0x0D 0x71 0x0D>; diff --git a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld index ba5413c1a770b..1567c50a78031 100644 --- a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld +++ b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld @@ -240,6 +240,7 @@ SECTIONS __rom_region_end = .; MPU_ALIGN(__rodata_region_end - __rom_region_start); _image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1; + __rom_region_mpu_size_bits = (LOG2CEIL(__rodata_region_end - __rom_region_start) - 1) << 1; GROUP_END(ROMABLE_REGION) diff --git a/include/zephyr/arch/arm/error.h b/include/zephyr/arch/arm/error.h index 9ad8b550070b9..69aa4d7e54bbf 100644 --- a/include/zephyr/arch/arm/error.h +++ b/include/zephyr/arch/arm/error.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. - * Copyright (c) 2023 Arm Limited + * Copyright 2023, 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -39,6 +39,7 @@ do {\ __asm__ volatile( \ "mov r0, %[_reason]\n" \ "svc %[id]\n" \ + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) \ :: [_reason] "r" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \ : "r0", "memory"); \ } while (false) @@ -59,6 +60,7 @@ do { \ "push {lr}\n\t" \ "cpsie i\n\t" \ "svc %[id]\n\t" \ + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n\t")) \ "pop {lr}\n\t" \ : \ : "r" (r0), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \ diff --git a/include/zephyr/arch/arm/syscall.h b/include/zephyr/arch/arm/syscall.h index e07dab12a9e2c..5e36d453cf021 100644 --- a/include/zephyr/arch/arm/syscall.h +++ b/include/zephyr/arch/arm/syscall.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 Linaro Limited. + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,6 +28,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -50,6 +52,7 @@ static inline uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2, register uint32_t r6 __asm__("r6") = call_id; __asm__ volatile("svc %[svid]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) : [svid] "i" (_SVC_CALL_SYSTEM_CALL), "r" (ret), "r" (r1), "r" (r2), "r" (r3), @@ -72,6 +75,7 @@ static inline uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2, register uint32_t r6 __asm__("r6") = call_id; __asm__ volatile("svc %[svid]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) : [svid] "i" (_SVC_CALL_SYSTEM_CALL), "r" (ret), "r" (r1), "r" (r2), "r" (r3), @@ -92,6 +96,7 @@ static inline uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2, register uint32_t r6 __asm__("r6") = call_id; __asm__ volatile("svc %[svid]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) : [svid] "i" (_SVC_CALL_SYSTEM_CALL), "r" (ret), "r" (r1), "r" (r2), "r" (r3), @@ -111,6 +116,7 @@ static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2, register uint32_t r6 __asm__("r6") = call_id; __asm__ volatile("svc %[svid]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) : "=r"(ret), "=r"(r1), "=r"(r2) : [svid] "i" (_SVC_CALL_SYSTEM_CALL), "r" (ret), "r" (r1), "r" (r2), "r" (r6) @@ -127,6 +133,7 @@ static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2, register uint32_t r6 __asm__("r6") = call_id; __asm__ volatile("svc %[svid]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) : "=r"(ret), "=r"(r1) : [svid] "i" (_SVC_CALL_SYSTEM_CALL), "r" (ret), "r" (r1), "r" (r6) @@ -142,6 +149,7 @@ static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1, register uint32_t r6 __asm__("r6") = call_id; __asm__ volatile("svc %[svid]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) : "=r"(ret) : [svid] "i" (_SVC_CALL_SYSTEM_CALL), "r" (ret), "r" (r6) @@ -155,6 +163,7 @@ static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id) register uint32_t r6 __asm__("r6") = call_id; __asm__ volatile("svc %[svid]\n" + IF_ENABLED(CONFIG_ARM_BTI, ("bti\n")) : "=r"(ret) : [svid] "i" (_SVC_CALL_SYSTEM_CALL), "r" (ret), "r" (r6) diff --git a/include/zephyr/arch/arm/thread.h b/include/zephyr/arch/arm/thread.h index 139f606809f9d..d65f1bf0effd2 100644 --- a/include/zephyr/arch/arm/thread.h +++ b/include/zephyr/arch/arm/thread.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 Intel Corporation + * Copyright 2025 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -60,6 +61,15 @@ struct _preempt_float { }; #endif +#if defined(CONFIG_ARM_PAC_PER_THREAD) +struct pac_keys { + uint32_t key_0; + uint32_t key_1; + uint32_t key_2; + uint32_t key_3; +}; +#endif + struct _thread_arch { /* interrupt locking key */ @@ -134,6 +144,10 @@ struct _thread_arch { #endif #endif #endif + +#if defined(CONFIG_ARM_PAC_PER_THREAD) + struct pac_keys pac_keys; +#endif }; #if defined(CONFIG_FPU_SHARING) && defined(CONFIG_MPU_STACK_GUARD) diff --git a/include/zephyr/arch/cache.h b/include/zephyr/arch/cache.h index 088de27c01802..ea262df7e7bae 100644 --- a/include/zephyr/arch/cache.h +++ b/include/zephyr/arch/cache.h @@ -13,9 +13,8 @@ #define ZEPHYR_INCLUDE_ARCH_CACHE_H_ /** - * @brief Cache Controller Interface - * @defgroup cache_arch_interface Cache Controller Interface - * @ingroup io_interfaces + * @defgroup arch-cache Architecture-specific cache controllers. + * @ingroup arch-interface * @{ */ diff --git a/include/zephyr/arch/common/init.h b/include/zephyr/arch/common/init.h new file mode 100644 index 0000000000000..ed1d05069dc63 --- /dev/null +++ b/include/zephyr/arch/common/init.h @@ -0,0 +1,35 @@ +/** + * SPDX-License-Identifier: Apache-2.0 + * Copyright The Zephyr Project Contributors + */ + +#ifndef ZEPHYR_ARCH_COMMON_INIT_H_ +#define ZEPHYR_ARCH_COMMON_INIT_H_ + +FUNC_NORETURN void z_cstart(void); + +/* Early boot functions */ +void arch_early_memset(void *dst, int c, size_t n); +void arch_early_memcpy(void *dst, const void *src, size_t n); + +void arch_bss_zero(void); + +#ifdef CONFIG_LINKER_USE_BOOT_SECTION +void arch_bss_zero_boot(void); +#else +static inline void arch_bss_zero_boot(void) +{ + /* Do nothing */ +} +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ + +#ifdef CONFIG_LINKER_USE_PINNED_SECTION +void arch_bss_zero_pinned(void); +#else +static inline void arch_bss_zero_pinned(void) +{ + /* Do nothing */ +} +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ + +#endif /* ZEPHYR_ARCH_COMMON_INIT_H_ */ diff --git a/include/zephyr/arch/common/xip.h b/include/zephyr/arch/common/xip.h new file mode 100644 index 0000000000000..7d719ec306427 --- /dev/null +++ b/include/zephyr/arch/common/xip.h @@ -0,0 +1,27 @@ +/* + * Copyright The Zephyr Project Contributors + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_INCLUDE_XIP_H_ +#define ZEPHYR_ARCH_INCLUDE_XIP_H_ + +#ifndef _ASMLANGUAGE +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_XIP +void arch_data_copy(void); +#else +static inline void arch_data_copy(void) +{ + /* Do nothing */ +} +#endif /* CONFIG_XIP */ +#ifdef __cplusplus +} +#endif + +#endif /* _ASMLANGUAGE */ +#endif /* ZEPHYR_ARCH_INCLUDE_XIP_H_ */ diff --git a/include/zephyr/arch/rx/linker.ld b/include/zephyr/arch/rx/linker.ld index 4f310c1558387..f0cdc4b18c9a9 100644 --- a/include/zephyr/arch/rx/linker.ld +++ b/include/zephyr/arch/rx/linker.ld @@ -26,10 +26,24 @@ #endif #define RAMABLE_REGION RAM -/* single bank configuration with 2 MB of code flash */ -#define ROM_START (DT_REG_ADDR(DT_NODELABEL(code_flash))) +#if defined(CONFIG_ROM_END_OFFSET) +#define ROM_END_OFFSET CONFIG_ROM_END_OFFSET +#else +#define ROM_END_OFFSET 0 +#endif + +#if defined(CONFIG_FLASH_LOAD_OFFSET) +#define FLASH_LOAD_OFFSET CONFIG_FLASH_LOAD_OFFSET +#else +#define FLASH_LOAD_OFFSET 0 +#endif -#define ROM_SIZE (DT_REG_SIZE(DT_NODELABEL(code_flash))) +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_flash), okay) +#define ROM_START (CONFIG_FLASH_BASE_ADDRESS + FLASH_LOAD_OFFSET) +#ifndef ROM_SIZE +#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - ROM_END_OFFSET) +#endif +#endif #define RAM_START (CONFIG_SRAM_BASE_ADDRESS) #define RAM_SIZE (KB(CONFIG_SRAM_SIZE)) @@ -61,10 +75,22 @@ SECTIONS . = ROM_START; /* for kernel logging */ PLACE_SYMBOL_HERE(__rodata_region_start); - .fvectors 0xFFFFFF80: AT(0xFFFFFF80) +#if CONFIG_HAS_EXCEPT_VECTOR_TABLE + .exvectors 0xFFFFFF80: AT(0xFFFFFF80) + { + KEEP(*(.exvectors)) + } GROUP_LINK_IN(ROMABLE_REGION) + + .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC) { KEEP(*(.fvectors)) } GROUP_LINK_IN(ROMABLE_REGION) +#else + .fvectors 0xFFFFFF80: AT(0xFFFFFF80) + { + KEEP(*(.fvectors)) + } GROUP_LINK_IN(ROMABLE_REGION) +#endif SECTION_PROLOGUE(_TEXT_SECTION_NAME,ROM_START,) { diff --git a/include/zephyr/arch/x86/arch.h b/include/zephyr/arch/x86/arch.h index adb8d06fa6ccf..29a2932340f3c 100644 --- a/include/zephyr/arch/x86/arch.h +++ b/include/zephyr/arch/x86/arch.h @@ -31,6 +31,7 @@ #include #include #include +#include #include #ifdef __cplusplus diff --git a/include/zephyr/arch/x86/cet.h b/include/zephyr/arch/x86/cet.h new file mode 100644 index 0000000000000..b629385e70786 --- /dev/null +++ b/include/zephyr/arch/x86/cet.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef ZEPHYR_INCLUDE_ARCH_X86_CET_H_ +#define ZEPHYR_INCLUDE_ARCH_X86_CET_H_ + +#ifndef _ASMLANGUAGE + +#ifdef CONFIG_HW_SHADOW_STACK + +extern FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry, + void *p1, void *p2, void *p3); + +typedef uintptr_t arch_thread_hw_shadow_stack_t; + +#define ARCH_THREAD_HW_SHADOW_STACK_SIZE(size_) \ + MAX(ROUND_UP((CONFIG_HW_SHADOW_STACK_PERCENTAGE_SIZE * (size_) / 100), \ + CONFIG_X86_CET_SHADOW_STACK_ALIGNMENT), \ + CONFIG_HW_SHADOW_STACK_MIN_SIZE) + +#define ARCH_THREAD_HW_SHADOW_STACK_DECLARE(sym, size) \ + extern arch_thread_hw_shadow_stack_t sym[size / sizeof(arch_thread_hw_shadow_stack_t)] + +#define ARCH_THREAD_HW_SHADOW_STACK_ARRAY_DECLARE(sym, nmemb, size) \ + extern arch_thread_hw_shadow_stack_t \ + sym[nmemb][size / sizeof(arch_thread_hw_shadow_stack_t)] + +#define ARCH_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE(name, nmemb, size) \ + arch_thread_hw_shadow_stack_t Z_GENERIC_SECTION(.x86shadowstack.arr_ ##name) \ + __aligned(CONFIG_X86_CET_SHADOW_STACK_ALIGNMENT) \ + name[MAX(nmemb, 1)][size / sizeof(arch_thread_hw_shadow_stack_t)] = \ + { \ + [0][0] = nmemb, \ + } + +#ifdef CONFIG_X86_64 +#define ARCH_THREAD_HW_SHADOW_STACK_DEFINE(name, size) \ + arch_thread_hw_shadow_stack_t Z_GENERIC_SECTION(.x86shadowstack) \ + __aligned(CONFIG_X86_CET_SHADOW_STACK_ALIGNMENT) \ + name[size / sizeof(arch_thread_hw_shadow_stack_t)] = \ + { [size / sizeof(arch_thread_hw_shadow_stack_t) - 5] = \ + (uintptr_t)name + size - 4 * sizeof(arch_thread_hw_shadow_stack_t) + 1, \ + [size / sizeof(arch_thread_hw_shadow_stack_t) - 4] = \ + (uintptr_t)name + size - 1 * sizeof(arch_thread_hw_shadow_stack_t), \ + [size / sizeof(arch_thread_hw_shadow_stack_t) - 3] = \ + (uintptr_t)z_thread_entry, \ + [size / sizeof(arch_thread_hw_shadow_stack_t) - 2] = \ + (uintptr_t)X86_KERNEL_CS } + +#else /* CONFIG_X86_64 */ + +#ifdef CONFIG_X86_DEBUG_INFO +extern void z_x86_thread_entry_wrapper(k_thread_entry_t entry, + void *p1, void *p2, void *p3); +#define ___x86_entry_point z_x86_thread_entry_wrapper +#else +#define ___x86_entry_point z_thread_entry +#endif + +#define ARCH_THREAD_HW_SHADOW_STACK_DEFINE(name, size) \ + arch_thread_hw_shadow_stack_t Z_GENERIC_SECTION(.x86shadowstack) \ + __aligned(CONFIG_X86_CET_SHADOW_STACK_ALIGNMENT) \ + name[size / sizeof(arch_thread_hw_shadow_stack_t)] = \ + { [size / sizeof(arch_thread_hw_shadow_stack_t) - 4] = \ + (uintptr_t)name + size - 2 * sizeof(arch_thread_hw_shadow_stack_t), \ + [size / sizeof(arch_thread_hw_shadow_stack_t) - 3] = 0, \ + [size / sizeof(arch_thread_hw_shadow_stack_t) - 2] = \ + (uintptr_t)___x86_entry_point, \ + } +#endif /* CONFIG_X86_64 */ + +int arch_thread_hw_shadow_stack_attach(struct k_thread *thread, + arch_thread_hw_shadow_stack_t *stack, + size_t stack_size); + +#endif /* CONFIG_HW_SHADOW_STACK */ + +#endif /* _ASMLANGUAGE */ +#endif /* ZEPHYR_INCLUDE_ARCH_X86_CET_H_ */ diff --git a/include/zephyr/arch/x86/ia32/arch.h b/include/zephyr/arch/x86/ia32/arch.h index 8c61b9788ad6a..ad3c5ac669a67 100644 --- a/include/zephyr/arch/x86/ia32/arch.h +++ b/include/zephyr/arch/x86/ia32/arch.h @@ -59,7 +59,7 @@ */ #define MK_ISR_NAME(x) __isr__##x -#define Z_DYN_STUB_SIZE 4 +#define Z_DYN_STUB_SIZE 8 #define Z_DYN_STUB_OFFSET 0 #define Z_DYN_STUB_LONG_JMP_EXTRA_SIZE 3 #define Z_DYN_STUB_PER_BLOCK 32 @@ -210,6 +210,7 @@ typedef struct s_isrList { ".pushsection " IRQSTUBS_TEXT_SECTION "\n\t" \ ".global %c[isr]_irq%c[irq]_stub\n\t" \ "%c[isr]_irq%c[irq]_stub:\n\t" \ + "endbr32\n\t" \ "pushl %[isr_param]\n\t" \ "pushl %[isr]\n\t" \ "jmp _interrupt_enter\n\t" \ diff --git a/include/zephyr/arch/x86/ia32/linker.ld b/include/zephyr/arch/x86/ia32/linker.ld index 298e8e4f56eac..22e86a0716b05 100644 --- a/include/zephyr/arch/x86/ia32/linker.ld +++ b/include/zephyr/arch/x86/ia32/linker.ld @@ -470,6 +470,32 @@ SECTIONS #include #include +#ifdef CONFIG_HW_SHADOW_STACK +SECTION_PROLOGUE(.x86shadowstack,,) +{ + MMU_PAGE_ALIGN + + __x86shadowstack_start = .; + + *(.x86shadowstack) + + MMU_PAGE_ALIGN + + __x86shadowstack_end = .; +} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +SECTION_PROLOGUE(.x86shadowstack.arr,,) +{ + MMU_PAGE_ALIGN + + *(.x86shadowstack.arr*) + + MMU_PAGE_ALIGN + + __x86shadowstack_end = .; +} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif + /* Must be last in RAM */ #include #endif /* !CONFIG_LINKER_USE_PINNED_SECTION */ diff --git a/include/zephyr/arch/x86/ia32/segmentation.h b/include/zephyr/arch/x86/ia32/segmentation.h index 6eae975b64705..5e4617a521650 100644 --- a/include/zephyr/arch/x86/ia32/segmentation.h +++ b/include/zephyr/arch/x86/ia32/segmentation.h @@ -50,7 +50,7 @@ extern "C" { #ifndef _ASMLANGUAGE -/* Section 7.2.1 of IA architecture SW developer manual, Vol 3. */ +/* Section 8.2.1 of IA architecture SW developer manual, Vol 3. */ struct __packed task_state_segment { uint16_t backlink; uint16_t reserved_1; @@ -91,6 +91,7 @@ struct __packed task_state_segment { uint8_t t:1; /* Trap bit */ uint16_t reserved_12:15; uint16_t iomap; + uint32_t ssp; }; #define SEG_SELECTOR(index, table, dpl) (index << 3 | table << 2 | dpl) diff --git a/include/zephyr/arch/x86/ia32/structs.h b/include/zephyr/arch/x86/ia32/structs.h index 91112a8578c54..1429e1cadc2e7 100644 --- a/include/zephyr/arch/x86/ia32/structs.h +++ b/include/zephyr/arch/x86/ia32/structs.h @@ -24,7 +24,14 @@ struct _cpu_arch { */ struct k_thread *fpu_owner; -#elif defined(__cplusplus) +#endif +#if defined(CONFIG_HW_SHADOW_STACK) + long *shstk_addr; /* Latest top of shadow stack */ + long *shstk_base; /* Base of shadow stack */ + size_t shstk_size; +#endif +#if defined(__cplusplus) && !defined(CONFIG_FPU_SHARING) && \ + !defined(CONFIG_HW_SHADOW_STACK) /* Ensure this struct does not have a size of 0 which is not allowed in C++. */ uint8_t dummy; #endif diff --git a/include/zephyr/arch/x86/ia32/thread.h b/include/zephyr/arch/x86/ia32/thread.h index ad0d8f8e24e0a..b66ba31f835a9 100644 --- a/include/zephyr/arch/x86/ia32/thread.h +++ b/include/zephyr/arch/x86/ia32/thread.h @@ -236,6 +236,12 @@ struct _thread_arch { #endif /* CONFIG_LAZY_FPU_SHARING */ tPreempFloatReg preempFloatReg; /* volatile float register storage */ + +#ifdef CONFIG_HW_SHADOW_STACK + long *shstk_addr; + long *shstk_base; + size_t shstk_size; +#endif }; typedef struct _thread_arch _thread_arch_t; diff --git a/include/zephyr/arch/x86/intel64/arch.h b/include/zephyr/arch/x86/intel64/arch.h index 671d331f3bd24..8bf6f95ff1887 100644 --- a/include/zephyr/arch/x86/intel64/arch.h +++ b/include/zephyr/arch/x86/intel64/arch.h @@ -15,6 +15,8 @@ #define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_ #include +#include +#include #include #include #if defined(CONFIG_PCIE) && !defined(_ASMLANGUAGE) diff --git a/include/zephyr/arch/x86/intel64/linker.ld b/include/zephyr/arch/x86/intel64/linker.ld index d220d8ccac4d2..b20f40258b12b 100644 --- a/include/zephyr/arch/x86/intel64/linker.ld +++ b/include/zephyr/arch/x86/intel64/linker.ld @@ -189,6 +189,32 @@ SECTIONS #include #include +#ifdef CONFIG_HW_SHADOW_STACK +SECTION_PROLOGUE(.x86shadowstack,,) +{ + MMU_PAGE_ALIGN + + __x86shadowstack_start = .; + + *(.x86shadowstack) + + MMU_PAGE_ALIGN + +} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +SECTION_PROLOGUE(.x86shadowstack.arr,,) +{ + MMU_PAGE_ALIGN + + *(.x86shadowstack.arr*) + + MMU_PAGE_ALIGN + + __x86shadowstack_end = .; + +} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif + /* Located in generated directory. This file is populated by the * zephyr_linker_sources() Cmake function. */ diff --git a/include/zephyr/arch/x86/intel64/thread.h b/include/zephyr/arch/x86/intel64/thread.h index ae03c29f1a743..809ad77222fbc 100644 --- a/include/zephyr/arch/x86/intel64/thread.h +++ b/include/zephyr/arch/x86/intel64/thread.h @@ -84,6 +84,11 @@ struct x86_tss64 { */ struct _cpu *cpu; +#ifdef CONFIG_HW_SHADOW_STACK + uintptr_t *shstk_addr; + uintptr_t exception_shstk_addr; +#endif + #ifdef CONFIG_USERSPACE /* Privilege mode stack pointer value when doing a system call */ char *psp; @@ -135,6 +140,12 @@ struct _thread_arch { uint64_t cs; #endif +#ifdef CONFIG_HW_SHADOW_STACK + uintptr_t *shstk_addr; + uintptr_t *shstk_base; + size_t shstk_size; +#endif + uint64_t rax; uint64_t rcx; uint64_t rdx; diff --git a/include/zephyr/arch/x86/msr.h b/include/zephyr/arch/x86/msr.h index 0ccd3806bbfb5..8bd7b31a7b6bd 100644 --- a/include/zephyr/arch/x86/msr.h +++ b/include/zephyr/arch/x86/msr.h @@ -6,6 +6,8 @@ #ifndef ZEPHYR_INCLUDE_ARCH_X86_MSR_H_ #define ZEPHYR_INCLUDE_ARCH_X86_MSR_H_ +#include + /* * Model specific registers (MSR). Access with z_x86_msr_read/write(). */ @@ -24,6 +26,19 @@ #define X86_X2APIC_BASE_MSR 0x00000800 /* .. thru 0x00000BFF */ +#define X86_U_CET_MSR 0x000006A0 + +#define X86_S_CET_MSR 0x000006A2 +#define X86_S_CET_MSR_SHSTK BIT(0) +#define X86_S_CET_MSR_WR_SHSTK BIT(1) +#define X86_S_CET_MSR_ENDBR BIT(2) +#define X86_S_CET_MSR_NO_TRACK BIT(4) + +#define X86_S_CET_MSR_SHSTK_EN (X86_S_CET_MSR_SHSTK | \ + X86_S_CET_MSR_WR_SHSTK) + +#define X86_INTERRUPT_SSP_TABLE_MSR 0x00006A8 + #define X86_EFER_MSR 0xC0000080U #define X86_EFER_MSR_SCE BIT(0) #define X86_EFER_MSR_LME BIT(8) diff --git a/include/zephyr/bindesc.h b/include/zephyr/bindesc.h index 88e51dbf89b9f..39305334d6a61 100644 --- a/include/zephyr/bindesc.h +++ b/include/zephyr/bindesc.h @@ -4,9 +4,21 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @brief Header file for binary descriptors + * @ingroup bindesc + */ + #ifndef ZEPHYR_INCLUDE_ZEPHYR_BINDESC_H_ #define ZEPHYR_INCLUDE_ZEPHYR_BINDESC_H_ +/** + * @defgroup bindesc Binary Descriptors + * @ingroup os_services + * @{ + */ + #include #ifdef __cplusplus @@ -17,19 +29,28 @@ extern "C" { * Corresponds to the definitions in scripts/west_commands/bindesc.py. * Do not change without syncing the definitions in both files! */ + +/** Magic number used to identify binary descriptor sections in firmware images */ #define BINDESC_MAGIC 0xb9863e5a7ea46046 +/** Required memory alignment for binary descriptor entries */ #define BINDESC_ALIGNMENT 4 -#define BINDESC_TYPE_UINT 0x0 -#define BINDESC_TYPE_STR 0x1 -#define BINDESC_TYPE_BYTES 0x2 -#define BINDESC_TYPE_DESCRIPTORS_END 0xf -/* sizeof ignores the data as it's a flexible array */ + +/** @name Binary Descriptor Types */ +/** @{ */ +#define BINDESC_TYPE_UINT 0x0 /**< Unsigned integer data */ +#define BINDESC_TYPE_STR 0x1 /**< String data */ +#define BINDESC_TYPE_BYTES 0x2 /**< Byte array data */ +#define BINDESC_TYPE_DESCRIPTORS_END 0xf /**< Marks the end of binary descriptor section */ +/** @} */ + +/** Size of the header of a binary descriptor entry */ +/* Needed as sizeof ignores the data as it's a flexible array */ #define BINDESC_ENTRY_HEADER_SIZE (sizeof(struct bindesc_entry)) /** - * @brief Binary Descriptor Definition - * @defgroup bindesc_define Bindesc Define - * @ingroup os_services + * @brief Macros for defining binary descriptors in firmware images + * @defgroup bindesc_define Binary Descriptor Definition + * @ingroup bindesc * @{ */ @@ -119,6 +140,7 @@ extern "C" { /** The C++ compiler version */ #define BINDESC_ID_CXX_COMPILER_VERSION 0xb04 +/** The end of binary descriptor section */ #define BINDESC_TAG_DESCRIPTORS_END BINDESC_TAG(DESCRIPTORS_END, 0x0fff) /** @@ -292,9 +314,15 @@ extern "C" { * @} */ -/* - * An entry of the binary descriptor header. Each descriptor is - * described by one of these entries. +/** + * @brief Functions for reading binary descriptors from firmware images + * @defgroup bindesc_read Binary Descriptor Reading + * @ingroup bindesc + * @{ + */ + +/** + * @brief Structure for a binary descriptor entry */ struct bindesc_entry { /** Tag of the entry */ @@ -305,6 +333,7 @@ struct bindesc_entry { uint8_t data[]; } __packed; +/** @cond INTERNAL_HIDDEN */ /* * We're assuming that `struct bindesc_entry` has a specific layout in * memory, so it's worth making sure that the layout is really what we @@ -314,8 +343,13 @@ struct bindesc_entry { BUILD_ASSERT(offsetof(struct bindesc_entry, tag) == 0, "Incorrect memory layout"); BUILD_ASSERT(offsetof(struct bindesc_entry, len) == 2, "Incorrect memory layout"); BUILD_ASSERT(offsetof(struct bindesc_entry, data) == 4, "Incorrect memory layout"); +/** @endcond */ +/** + * @brief Handle for reading binary descriptors from firmware images + */ struct bindesc_handle { + /** @cond INTERNAL_HIDDEN */ const uint8_t *address; enum { BINDESC_HANDLE_TYPE_RAM, @@ -328,15 +362,9 @@ struct bindesc_handle { uint8_t buffer[sizeof(struct bindesc_entry) + CONFIG_BINDESC_READ_FLASH_MAX_DATA_SIZE] __aligned(BINDESC_ALIGNMENT); #endif /* IS_ENABLED(CONFIG_BINDESC_READ_FLASH) */ + /** @endcond */ }; -/** - * @brief Reading Binary Descriptors of other images. - * @defgroup bindesc_read Bindesc Read - * @ingroup os_services - * @{ - */ - /** * @brief Callback type to be called on descriptors found during a walk * @@ -355,7 +383,7 @@ typedef int (*bindesc_callback_t)(const struct bindesc_entry *entry, void *user_ * Memory mapped flash is any flash that can be directly accessed by the CPU, * without needing to use the flash API for copying the data to RAM. * - * @param handle Bindesc handle to be given to subsequent calls + * @param[out] handle Bindesc handle to be given to subsequent calls * @param offset The offset from the beginning of the flash that the bindesc magic can be found at * * @retval 0 On success @@ -371,9 +399,9 @@ int bindesc_open_memory_mapped_flash(struct bindesc_handle *handle, size_t offse * It's assumed that the whole bindesc context was copied to RAM prior to calling * this function, either by the user or by a bootloader. * - * @note The given address must be aligned to BINDESC_ALIGNMENT + * @note The given address must be aligned to @ref BINDESC_ALIGNMENT * - * @param handle Bindesc handle to be given to subsequent calls + * @param[out] handle Bindesc handle to be given to subsequent calls * @param address The address that the bindesc magic can be found at * @param max_size Maximum size of the given buffer * @@ -392,10 +420,12 @@ int bindesc_open_ram(struct bindesc_handle *handle, const uint8_t *address, size * backend requires reading the data from flash to an internal buffer * using the flash API * - * @param handle Bindesc handle to be given to subsequent calls + * @param[out] handle Bindesc handle to be given to subsequent calls * @param offset The offset from the beginning of the flash that the bindesc magic can be found at * @param flash_device Flash device to read descriptors from * + * @kconfig_dep{CONFIG_BINDESC_READ_FLASH} + * * @retval 0 On success * @retval -ENOENT If no bindesc magic was found at the given offset */ @@ -599,4 +629,8 @@ extern const struct bindesc_entry BINDESC_NAME(cxx_compiler_version); } #endif +/** + * @} + */ + #endif /* ZEPHYR_INCLUDE_ZEPHYR_BINDESC_H_ */ diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h index 2e4ae33a1ca46..27f42432e227d 100644 --- a/include/zephyr/bluetooth/audio/bap.h +++ b/include/zephyr/bluetooth/audio/bap.h @@ -54,6 +54,9 @@ extern "C" { /** An invalid Broadcast ID */ #define BT_BAP_INVALID_BROADCAST_ID 0xFFFFFFFFU +/** Value that represents an unset presentation delay value */ +#define BT_BAP_PD_UNSET 0xFFFFFFFFU + /** * @brief Recommended connectable advertising parameters * @@ -1744,6 +1747,33 @@ int bt_bap_unicast_group_foreach_stream(struct bt_bap_unicast_group *unicast_gro bt_bap_unicast_group_foreach_stream_func_t func, void *user_data); +/** Structure holding information of audio stream endpoint */ +struct bt_bap_unicast_group_info { + /** Presentation delay for sink ASEs + * + * Will be @ref BT_BAP_PD_UNSET if no sink ASEs have been QoS configured + */ + uint32_t sink_pd; + + /** Presentation delay for source ASEs + * + * Will be @ref BT_BAP_PD_UNSET if no source ASEs have been QoS configured + */ + uint32_t source_pd; +}; + +/** + * @brief Return structure holding information of unicast group + * + * @param unicast_group The unicast group object. + * @param info The structure object to be filled with the info. + * + * @retval 0 Success + * @retval -EINVAL @p unicast_group or @p info are NULL + */ +int bt_bap_unicast_group_get_info(const struct bt_bap_unicast_group *unicast_group, + struct bt_bap_unicast_group_info *info); + /** Unicast Client callback structure */ struct bt_bap_unicast_client_cb { /** diff --git a/include/zephyr/bluetooth/audio/cap.h b/include/zephyr/bluetooth/audio/cap.h index 358167a30959a..29e6524fc5087 100644 --- a/include/zephyr/bluetooth/audio/cap.h +++ b/include/zephyr/bluetooth/audio/cap.h @@ -424,6 +424,24 @@ int bt_cap_unicast_group_foreach_stream(struct bt_cap_unicast_group *unicast_gro bt_cap_unicast_group_foreach_stream_func_t func, void *user_data); +/** Structure holding information of audio stream endpoint */ +struct bt_cap_unicast_group_info { + /** Pointer to the underlying Basic Audio Profile unicast group */ + const struct bt_bap_unicast_group *unicast_group; +}; + +/** + * @brief Return structure holding information of unicast group + * + * @param unicast_group The unicast group object. + * @param info The structure object to be filled with the info. + * + * @retval 0 Success + * @retval -EINVAL @p unicast_group or @p info are NULL + */ +int bt_cap_unicast_group_get_info(const struct bt_cap_unicast_group *unicast_group, + struct bt_cap_unicast_group_info *info); + /** Stream specific parameters for the bt_cap_initiator_unicast_audio_start() function */ struct bt_cap_unicast_audio_start_stream_param { /** Coordinated or ad-hoc set member. */ @@ -812,6 +830,32 @@ int bt_cap_initiator_broadcast_audio_delete(struct bt_cap_broadcast_source *broa int bt_cap_initiator_broadcast_get_base(struct bt_cap_broadcast_source *broadcast_source, struct net_buf_simple *base_buf); +/** Callback function for bt_cap_initiator_broadcast_foreach_stream() + * + * @param stream The audio stream + * @param user_data User data + * + * @retval true Stop iterating. + * @retval false Continue iterating. + */ +typedef bool (*bt_cap_initiator_broadcast_foreach_stream_func_t)(struct bt_cap_stream *stream, + void *user_data); + +/** + * @brief Iterate through all streams in a broadcast source + * + * @param broadcast_source The broadcast source. + * @param func The callback function. + * @param user_data User specified data that is sent to the callback function. + * + * @retval 0 Success (even if no streams exists in the group). + * @retval -ECANCELED The @p func returned true. + * @retval -EINVAL @p broadcast_source or @p func were NULL. + */ +int bt_cap_initiator_broadcast_foreach_stream(struct bt_cap_broadcast_source *broadcast_source, + bt_cap_initiator_broadcast_foreach_stream_func_t func, + void *user_data); + /** Parameters for bt_cap_handover_unicast_to_broadcast() */ struct bt_cap_handover_unicast_to_broadcast_param { /** The type of the set. */ @@ -830,9 +874,6 @@ struct bt_cap_handover_unicast_to_broadcast_param { */ struct bt_le_ext_adv *ext_adv; - /** The SID of the advertising set. */ - uint8_t sid; - /** The periodic advertising interval configured for the advertising set. */ uint16_t pa_interval; diff --git a/include/zephyr/bluetooth/audio/ccp.h b/include/zephyr/bluetooth/audio/ccp.h index 5c907d569590c..c57432c9cf6b1 100644 --- a/include/zephyr/bluetooth/audio/ccp.h +++ b/include/zephyr/bluetooth/audio/ccp.h @@ -93,6 +93,33 @@ int bt_ccp_call_control_server_register_bearer(const struct bt_tbs_register_para */ int bt_ccp_call_control_server_unregister_bearer(struct bt_ccp_call_control_server_bearer *bearer); +/** + * @brief Set a new bearer provider name. + * + * @param bearer The bearer to set the name for. + * @param name The new bearer provider name. + * + * @retval 0 Success + * @retval -EINVAL @p bearer or @p name is NULL, or @p name is the empty string or @p name is larger + * than @kconfig{CONFIG_BT_TBS_MAX_PROVIDER_NAME_LENGTH} + * @retval -EFAULT @p bearer is not registered + */ +int bt_ccp_call_control_server_set_bearer_provider_name( + struct bt_ccp_call_control_server_bearer *bearer, const char *name); + +/** + * @brief Get the bearer provider name. + * + * @param[in] bearer The bearer to get the name for. + * @param[out] name Pointer that will be updated to be the bearer provider name. + * + * @retval 0 Success + * @retval -EINVAL @p bearer or @p name is NULL + * @retval -EFAULT @p bearer is not registered + */ +int bt_ccp_call_control_server_get_bearer_provider_name( + struct bt_ccp_call_control_server_bearer *bearer, const char **name); + /** @} */ /* End of group bt_ccp_call_control_server */ /** diff --git a/include/zephyr/bluetooth/bluetooth.h b/include/zephyr/bluetooth/bluetooth.h index b1b4482c5c1cd..1656f1f568447 100644 --- a/include/zephyr/bluetooth/bluetooth.h +++ b/include/zephyr/bluetooth/bluetooth.h @@ -1620,6 +1620,9 @@ struct bt_le_ext_adv_info { /** Currently selected Transmit Power (dBM). */ int8_t tx_power; + /** Advertising Set ID */ + uint8_t sid; + /** Current local advertising address used. */ const bt_addr_le_t *addr; diff --git a/include/zephyr/bluetooth/classic/a2dp.h b/include/zephyr/bluetooth/classic/a2dp.h index 985e5088a7838..cc56ea32c3e26 100644 --- a/include/zephyr/bluetooth/classic/a2dp.h +++ b/include/zephyr/bluetooth/classic/a2dp.h @@ -391,6 +391,15 @@ struct bt_a2dp_discover_param { * it save endpoint info internally. */ struct bt_avdtp_sep_info *seps_info; + /** The AVDTP version of the peer's A2DP sdp service. + * Stack uses it to determine using get_all_cap or get_cap cmd. When both + * versions are v1.3 or bigger version, get_all_cap is used, otherwise + * get_cap is used. + * It is the same value of the avdtp sepcificaiton's version value. + * For example: 0x0103 means version 1.3 + * If the value is 0 (unknown), stack process it as less than v1.3 + */ + uint16_t avdtp_version; /** The max count of seps (stream endpoint) that can be got in this call route */ uint8_t sep_count; }; diff --git a/include/zephyr/bluetooth/classic/avdtp.h b/include/zephyr/bluetooth/classic/avdtp.h index dd7307ae3748f..8756516d0bd0d 100644 --- a/include/zephyr/bluetooth/classic/avdtp.h +++ b/include/zephyr/bluetooth/classic/avdtp.h @@ -15,6 +15,10 @@ extern "C" { #endif +#define AVDTP_VERSION_1_3 0x0103 /**< AVDTP version 1.3 value */ + +#define AVDTP_VERSION AVDTP_VERSION_1_3 /**< AVDTP version used by Zephyr */ + /** * @brief AVDTP error code */ @@ -120,6 +124,14 @@ enum bt_avdtp_service_category { BT_AVDTP_SERVICE_DELAY_REPORTING = 0x08, }; +/** @brief service category Recovery Capabilities type*/ +enum bt_avdtp_recovery_type { + /** Forbidden */ + BT_AVDTP_RECOVERY_TYPE_FORBIDDEN = 0x00, + /** RFC2733 */ + BT_ADVTP_RECOVERY_TYPE_RFC2733 = 0x01, +}; + /** @brief AVDTP Stream End Point */ struct bt_avdtp_sep { /** Stream End Point information */ diff --git a/include/zephyr/bluetooth/classic/avrcp.h b/include/zephyr/bluetooth/classic/avrcp.h index 35c41318acc3e..9db8448d99bd8 100644 --- a/include/zephyr/bluetooth/classic/avrcp.h +++ b/include/zephyr/bluetooth/classic/avrcp.h @@ -141,6 +141,124 @@ typedef enum __packed { BT_AVRCP_BUTTON_RELEASED = 1, } bt_avrcp_button_state_t; +/** + * @brief AVRCP status and error codes. + * + * These status codes are used in AVRCP responses to indicate the result of a command. + */ +typedef enum __packed { + /** Invalid command. + * Valid for Commands: All + */ + BT_AVRCP_STATUS_INVALID_COMMAND = 0x00, + + /** Invalid parameter. + * Valid for Commands: All + */ + BT_AVRCP_STATUS_INVALID_PARAMETER = 0x01, + + /** Parameter content error. + * Valid for Commands: All + */ + BT_AVRCP_STATUS_PARAMETER_CONTENT_ERROR = 0x02, + + /** Internal error. + * Valid for Commands: All + */ + BT_AVRCP_STATUS_INTERNAL_ERROR = 0x03, + + /** Operation completed without error. + * Valid for Commands: All except where the response CType is AV/C REJECTED + */ + BT_AVRCP_STATUS_OPERATION_COMPLETED = 0x04, + + /** The UIDs on the device have changed. + * Valid for Commands: All + */ + BT_AVRCP_STATUS_UID_CHANGED = 0x05, + + /** The Direction parameter is invalid. + * Valid for Commands: ChangePath + */ + BT_AVRCP_STATUS_INVALID_DIRECTION = 0x07, + + /** The UID provided does not refer to a folder item. + * Valid for Commands: ChangePath + */ + BT_AVRCP_STATUS_NOT_A_DIRECTORY = 0x08, + + /** The UID provided does not refer to any currently valid item. + * Valid for Commands: ChangePath, PlayItem, AddToNowPlaying, GetItemAttributes + */ + BT_AVRCP_STATUS_DOES_NOT_EXIST = 0x09, + + /** Invalid scope. + * Valid for Commands: GetFolderItems, PlayItem, AddToNowPlayer, GetItemAttributes, + * GetTotalNumberOfItems + */ + BT_AVRCP_STATUS_INVALID_SCOPE = 0x0a, + + /** Range out of bounds. + * Valid for Commands: GetFolderItems + */ + BT_AVRCP_STATUS_RANGE_OUT_OF_BOUNDS = 0x0b, + + /** Folder item is not playable. + * Valid for Commands: Play Item, AddToNowPlaying + */ + BT_AVRCP_STATUS_FOLDER_ITEM_IS_NOT_PLAYABLE = 0x0c, + + /** Media in use. + * Valid for Commands: PlayItem, AddToNowPlaying + */ + BT_AVRCP_STATUS_MEDIA_IN_USE = 0x0d, + + /** Now Playing List full. + * Valid for Commands: AddToNowPlaying + */ + BT_AVRCP_STATUS_NOW_PLAYING_LIST_FULL = 0x0e, + + /** Search not supported. + * Valid for Commands: Search + */ + BT_AVRCP_STATUS_SEARCH_NOT_SUPPORTED = 0x0f, + + /** Search in progress. + * Valid for Commands: Search + */ + BT_AVRCP_STATUS_SEARCH_IN_PROGRESS = 0x10, + + /** The specified Player Id does not refer to a valid player. + * Valid for Commands: SetAddressedPlayer, SetBrowsedPlayer + */ + BT_AVRCP_STATUS_INVALID_PLAYER_ID = 0x11, + + /** Player not browsable. + * Valid for Commands: SetBrowsedPlayer + */ + BT_AVRCP_STATUS_PLAYER_NOT_BROWSABLE = 0x12, + + /** Player not addressed. + * Valid for Commands: Search, SetBrowsedPlayer + */ + BT_AVRCP_STATUS_PLAYER_NOT_ADDRESSED = 0x13, + + /** No valid search results. + * Valid for Commands: GetFolderItems + */ + BT_AVRCP_STATUS_NO_VALID_SEARCH_RESULTS = 0x14, + + /** No available players. + * Valid for Commands: ALL + */ + BT_AVRCP_STATUS_NO_AVAILABLE_PLAYERS = 0x15, + + /** Addressed player changed. + * Valid for Commands: All Register Notification commands + */ + BT_AVRCP_STATUS_ADDRESSED_PLAYER_CHANGED = 0x16, +} bt_avrcp_status_t; + /** @brief AVRCP CT structure */ struct bt_avrcp_ct; /** @brief AVRCP TG structure */ @@ -167,13 +285,34 @@ struct bt_avrcp_passthrough_rsp { uint8_t byte0; /**< [7]: state_flag, [6:0]: opid */ uint8_t data_len; uint8_t data[]; -}; +} __packed; struct bt_avrcp_get_cap_rsp { uint8_t cap_id; /**< bt_avrcp_cap_t */ uint8_t cap_cnt; /**< number of items contained in *cap */ uint8_t cap[]; /**< 1 or 3 octets each depends on cap_id */ -}; +} __packed; + +/** @brief AVRCP Character Set IDs */ +typedef enum __packed { + BT_AVRCP_CHARSET_UTF8 = 0x006a, +} bt_avrcp_charset_t; + +/** @brief get folder name (response) */ +struct bt_avrcp_folder_name { + uint16_t folder_name_len; + uint8_t folder_name[]; +} __packed; + +/** @brief Set browsed player response structure */ +struct bt_avrcp_set_browsed_player_rsp { + uint8_t status; /**< Status see bt_avrcp_status_t.*/ + uint16_t uid_counter; /**< UID counter */ + uint32_t num_items; /**< Number of items in the folder */ + uint16_t charset_id; /**< Character set ID */ + uint8_t folder_depth; /**< Folder depth */ + struct bt_avrcp_folder_name folder_names[0]; /**< Folder names data */ +} __packed; struct bt_avrcp_ct_cb { /** @brief An AVRCP CT connection has been established. @@ -195,6 +334,25 @@ struct bt_avrcp_ct_cb { */ void (*disconnected)(struct bt_avrcp_ct *ct); + /** @brief An AVRCP CT browsing connection has been established. + * + * This callback notifies the application of an avrcp browsing connection, + * i.e., an AVCTP browsing L2CAP connection. + * + * @param conn Connection object. + * @param ct AVRCP CT connection object. + */ + void (*browsing_connected)(struct bt_conn *conn, struct bt_avrcp_ct *ct); + + /** @brief An AVRCP CT browsing connection has been disconnected. + * + * This callback notifies the application that an avrcp browsing connection + * has been disconnected. + * + * @param ct AVRCP CT connection object. + */ + void (*browsing_disconnected)(struct bt_avrcp_ct *ct); + /** @brief Callback function for bt_avrcp_get_cap(). * * Called when the get capabilities process is completed. @@ -239,6 +397,19 @@ struct bt_avrcp_ct_cb { */ void (*passthrough_rsp)(struct bt_avrcp_ct *ct, uint8_t tid, bt_avrcp_rsp_t result, const struct bt_avrcp_passthrough_rsp *rsp); + + /** @brief Callback function for bt_avrcp_ct_set_browsed_player(). + * + * Called when the set browsed player process is completed. + * + * @param ct AVRCP CT connection object. + * @param tid The transaction label of the response. + * @param buf The response buffer containing the set browsed player response data. + * The application can parse this payload according to the format defined in + * @ref bt_avrcp_set_browsed_player_rsp. Note that the data is encoded in + * big-endian format. + */ + void (*browsed_player_rsp)(struct bt_avrcp_ct *ct, uint8_t tid, struct net_buf *buf); }; /** @brief Connect AVRCP. @@ -264,6 +435,40 @@ int bt_avrcp_connect(struct bt_conn *conn); */ int bt_avrcp_disconnect(struct bt_conn *conn); +/** + * @brief Allocate a net_buf for AVRCP PDU transmission, reserving headroom + * for AVRCP, AVRCTP, L2CAP, and ACL headers. + * + * This function allocates a buffer from the specified pool and reserves + * sufficient headroom for protocol headers required by AVRCP over Bluetooth. + * + * @param pool The buffer pool to allocate from. + * + * @return A newly allocated net_buf with reserved headroom. + */ +struct net_buf *bt_avrcp_create_pdu(struct net_buf_pool *pool); + +/** @brief Connect AVRCP browsing channel. + * + * This function is to be called after the AVRCP control channel is established. + * The API is to be used to establish AVRCP browsing connection between devices. + * + * @param conn Pointer to bt_conn structure. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_browsing_connect(struct bt_conn *conn); + +/** @brief Disconnect AVRCP browsing channel. + * + * This function close AVCTP browsing channel L2CAP connection. + * + * @param conn Pointer to bt_conn structure. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_browsing_disconnect(struct bt_conn *conn); + /** @brief Register callback. * * Register AVRCP callbacks to monitor the state and interact with the remote device. @@ -326,6 +531,18 @@ int bt_avrcp_ct_get_subunit_info(struct bt_avrcp_ct *ct, uint8_t tid); int bt_avrcp_ct_passthrough(struct bt_avrcp_ct *ct, uint8_t tid, uint8_t opid, uint8_t state, const uint8_t *payload, uint8_t len); +/** @brief Set browsed player. + * + * This function sets the browsed player on the remote device. + * + * @param ct The AVRCP CT instance. + * @param tid The transaction label of the response, valid from 0 to 15. + * @param player_id The player ID to be set as browsed player. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_ct_set_browsed_player(struct bt_avrcp_ct *ct, uint8_t tid, uint16_t player_id); + struct bt_avrcp_tg_cb { /** @brief An AVRCP TG connection has been established. * @@ -354,6 +571,35 @@ struct bt_avrcp_tg_cb { * @param tg AVRCP TG connection object. */ void (*unit_info_req)(struct bt_avrcp_tg *tg, uint8_t tid); + + /** @brief An AVRCP TG browsing connection has been established. + * + * This callback notifies the application of an avrcp browsing connection, + * i.e., an AVCTP browsing L2CAP connection. + * + * @param conn Connection object. + * @param tg AVRCP TG connection object. + */ + void (*browsing_connected)(struct bt_conn *conn, struct bt_avrcp_tg *tg); + + /** @brief An AVRCP TG browsing connection has been disconnected. + * + * This callback notifies the application that an avrcp browsing connection + * has been disconnected. + * + * @param tg AVRCP TG connection object. + */ + void (*browsing_disconnected)(struct bt_avrcp_tg *tg); + + /** @brief Set browsed player request callback. + * + * This callback is called whenever an AVRCP set browsed player request is received. + * + * @param tg AVRCP TG connection object. + * @param tid The transaction label of the request. + * @param player_id The player ID to be set as browsed player. + */ + void (*set_browsed_player_req)(struct bt_avrcp_tg *tg, uint8_t tid, uint16_t player_id); }; /** @brief Register callback. @@ -378,6 +624,19 @@ int bt_avrcp_tg_register_cb(const struct bt_avrcp_tg_cb *cb); */ int bt_avrcp_tg_send_unit_info_rsp(struct bt_avrcp_tg *tg, uint8_t tid, struct bt_avrcp_unit_info_rsp *rsp); + +/** @brief Send the set browsed player response. + * + * This function is called by the application to send the set browsed player response. + * + * @param tg The AVRCP TG instance. + * @param tid The transaction label of the response, valid from 0 to 15. + * @param buf The response buffer containing the set browsed player response data. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_tg_send_set_browsed_player_rsp(struct bt_avrcp_tg *tg, uint8_t tid, + struct net_buf *buf); #ifdef __cplusplus } #endif diff --git a/include/zephyr/bluetooth/classic/sdp.h b/include/zephyr/bluetooth/classic/sdp.h index 94c307a484d54..041197f8a6aeb 100644 --- a/include/zephyr/bluetooth/classic/sdp.h +++ b/include/zephyr/bluetooth/classic/sdp.h @@ -310,7 +310,7 @@ struct bt_sdp_record { struct bt_sdp_attribute *attrs; /**< Base addr of attr array */ size_t attr_count; /**< Number of attributes */ uint8_t index; /**< Index of the record in LL */ - struct bt_sdp_record *next; /**< Next service record */ + sys_snode_t node; }; /* @@ -566,6 +566,30 @@ enum { BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR, }; +/** Initializes SDP attribute ID range */ +#define BT_SDP_ATTR_ID_RANGE(beginning, ending) {(beginning), (ending)} + +/** + * @brief SDP attribute ID range + * + * If the beginning attribute ID is same with the ending attribute ID, the range represents a + * single attribute ID. + */ +struct bt_sdp_attribute_id_range { + /** Beginning attribute ID of the range */ + uint16_t beginning; + /** Ending attribute ID of the range */ + uint16_t ending; +}; + +/** @brief SDP attribute ID list for Service Attribute and Service Search Attribute transactions */ +struct bt_sdp_attribute_id_list { + /** Count of the SDP attribute ID range */ + size_t count; + /** Attribute ID range array list */ + struct bt_sdp_attribute_id_range *ranges; +}; + /** @brief Main user structure used in SDP discovery of remote. */ struct bt_sdp_discover_params { sys_snode_t _node; @@ -581,6 +605,13 @@ struct bt_sdp_discover_params { struct net_buf_pool *pool; /** Discover type */ uint8_t type; + /** + * Attribute ID list for Service Attribute and Service Search Attribute transactions + * + * If the `ids` is NULL or `ids->count` is 0, the default range `(0x0000, 0xffff)` will + * be used. + */ + struct bt_sdp_attribute_id_list *ids; }; /** @brief Allows user to start SDP discovery session. @@ -604,12 +635,14 @@ struct bt_sdp_discover_params { * Service Attribute: The SDP Client generates an * SDP_SERVICE_ATTR_REQ to retrieve specified * attribute values from a specific service - * record (`params->handle`). + * record (`params->handle`). The AttributeIDList + * is specified by `params->ids`. * Service Search Attribute: The SDP Client generates an * SDP_SERVICE_SEARCH_ATTR_REQ to retrieve * specified attribute values that match the * service search pattern (`params->uuid`) * given as the first parameter of the PDU. + * The AttributeIDList is specified by `params->ids`. * * @param conn Object identifying connection to remote. * @param params SDP discovery parameters. @@ -639,6 +672,7 @@ int bt_sdp_discover_cancel(struct bt_conn *conn, /** @brief Protocols to be asked about specific parameters */ enum bt_sdp_proto { BT_SDP_PROTO_RFCOMM = 0x0003, + BT_SDP_PROTO_AVDTP = 0x0019, BT_SDP_PROTO_L2CAP = 0x0100, }; diff --git a/include/zephyr/bluetooth/conn.h b/include/zephyr/bluetooth/conn.h index b1b7377ba5117..6a4b7c238c898 100644 --- a/include/zephyr/bluetooth/conn.h +++ b/include/zephyr/bluetooth/conn.h @@ -519,24 +519,60 @@ struct bt_conn_le_cs_fae_table { int8_t *remote_fae_table; }; +/** @brief Extract main mode part from @ref bt_conn_le_cs_mode + * + * @private + * + * @param x @ref bt_conn_le_cs_mode value + * @retval 1 Matches @ref BT_HCI_OP_LE_CS_MAIN_MODE_1 (0x01) + * @retval 2 Matches @ref BT_HCI_OP_LE_CS_MAIN_MODE_2 (0x02) + * @retval 3 Matches @ref BT_HCI_OP_LE_CS_MAIN_MODE_3 (0x03) + * + * @note Returned values match the HCI main mode values. + */ #define BT_CONN_LE_CS_MODE_MAIN_MODE_PART(x) ((x) & 0x3) + +/** @brief Extract sub-mode part from @ref bt_conn_le_cs_mode + * + * @private + * + * @param x @ref bt_conn_le_cs_mode value + * @retval 0 Internal encoding for @ref BT_HCI_OP_LE_CS_SUB_MODE_UNUSED (0xFF) + * @retval 1 Matches @ref BT_HCI_OP_LE_CS_SUB_MODE_1 (0x01) + * @retval 2 Matches @ref BT_HCI_OP_LE_CS_SUB_MODE_2 (0x02) + * @retval 3 Matches @ref BT_HCI_OP_LE_CS_SUB_MODE_3 (0x03) + * + * @note The value 0 encodes HCI 0xFF. This allows @ref bt_conn_le_cs_mode to + * fit in one byte. To obtain the HCI sub-mode value, use `(sub_mode == 0 ? 0xFF + * : sub_mode)`, where `sub_mode` is the value returned by this macro. + */ #define BT_CONN_LE_CS_MODE_SUB_MODE_PART(x) (((x) >> 4) & 0x3) -/** Channel sounding main and sub mode */ +/** @brief Channel sounding mode (main and sub-mode) + * + * Represents the combination of Channel Sounding (CS) main mode and sub-mode. + * + * @note The underlying numeric values are an internal encoding and are + * not stable API. Do not assume a direct concatenation of HCI values + * when inspecting the raw enum value. + * + * @sa BT_CONN_LE_CS_MODE_MAIN_MODE_PART + * @sa BT_CONN_LE_CS_MODE_SUB_MODE_PART + */ enum bt_conn_le_cs_mode { - /** Mode-1 (RTT) Main Mode, Unused Sub Mode */ + /** Main mode 1 (RTT), sub-mode: unused */ BT_CONN_LE_CS_MAIN_MODE_1_NO_SUB_MODE = BT_HCI_OP_LE_CS_MAIN_MODE_1, - /** Mode-2 (PBR) Main Mode, Unused Sub Mode */ + /** Main mode 2 (PBR), sub-mode: unused */ BT_CONN_LE_CS_MAIN_MODE_2_NO_SUB_MODE = BT_HCI_OP_LE_CS_MAIN_MODE_2, - /** Mode-3 (RTT and PBR) Main Mode, Unused Sub Mode */ + /** Main mode 3 (RTT and PBR), sub-mode: unused */ BT_CONN_LE_CS_MAIN_MODE_3_NO_SUB_MODE = BT_HCI_OP_LE_CS_MAIN_MODE_3, - /** Mode-2 (PBR) Main Mode, Mode-1 (RTT) Sub Mode */ + /** Main mode 2 (PBR), sub-mode 1 (RTT) */ BT_CONN_LE_CS_MAIN_MODE_2_SUB_MODE_1 = BT_HCI_OP_LE_CS_MAIN_MODE_2 | (BT_HCI_OP_LE_CS_SUB_MODE_1 << 4), - /** Mode-2 (PBR) Main Mode, Mode-3 (RTT and PBR) Sub Mode */ + /** Main mode 2 (PBR), sub-mode 3 (RTT and PBR) */ BT_CONN_LE_CS_MAIN_MODE_2_SUB_MODE_3 = BT_HCI_OP_LE_CS_MAIN_MODE_2 | (BT_HCI_OP_LE_CS_SUB_MODE_3 << 4), - /** Mode-3 (RTT and PBR) Main Mode, Mode-2 (PBR) Sub Mode */ + /** Main mode 3 (RTT and PBR), sub-mode 2 (PBR) */ BT_CONN_LE_CS_MAIN_MODE_3_SUB_MODE_2 = BT_HCI_OP_LE_CS_MAIN_MODE_3 | (BT_HCI_OP_LE_CS_SUB_MODE_2 << 4), }; @@ -893,6 +929,12 @@ struct bt_conn_br_info { const bt_addr_t *dst; /**< Destination (Remote) BR/EDR address */ }; +/** SCO Connection Info Structure */ +struct bt_conn_sco_info { + uint8_t link_type; /**< SCO link type */ + uint8_t air_mode; /**< SCO air mode (codec type) */ +}; + enum { BT_CONN_ROLE_CENTRAL = 0, BT_CONN_ROLE_PERIPHERAL = 1, @@ -959,6 +1001,8 @@ struct bt_conn_info { struct bt_conn_le_info le; /** BR/EDR Connection specific Info. */ struct bt_conn_br_info br; + /** SCO Connection specific Info. */ + struct bt_conn_sco_info sco; }; /** Connection state. */ enum bt_conn_state state; diff --git a/include/zephyr/bluetooth/gatt.h b/include/zephyr/bluetooth/gatt.h index 2c7d36a67588e..17b125d602c5f 100644 --- a/include/zephyr/bluetooth/gatt.h +++ b/include/zephyr/bluetooth/gatt.h @@ -1897,6 +1897,9 @@ struct bt_gatt_read_params; * When reading using by_uuid, `params->start_handle` is the attribute handle * for this `data` item. * + * If the received data length is invalid, the callback will called with the + * error @ref BT_ATT_ERR_INVALID_PDU. + * * @param conn Connection object. * @param err ATT error code. * @param params Read parameters used. @@ -2005,6 +2008,8 @@ struct bt_gatt_read_params { * The Response comes in callback @p params->func. The callback is run from * the context specified by 'config BT_RECV_CONTEXT'. * @p params must remain valid until start of callback. + * If the received data length is invalid, the callback @p params->func will + * called with the error @ref BT_ATT_ERR_INVALID_PDU. * * @param conn Connection object. * @param params Read parameters. diff --git a/include/zephyr/bluetooth/iso.h b/include/zephyr/bluetooth/iso.h index 5edebcab087ee..631d48b0c3deb 100644 --- a/include/zephyr/bluetooth/iso.h +++ b/include/zephyr/bluetooth/iso.h @@ -75,21 +75,21 @@ extern "C" { #define BT_ISO_DATA_PATH_VS_ID_MIN 0x01 /** The maximum value for vendor specific data path ID */ #define BT_ISO_DATA_PATH_VS_ID_MAX 0xFE -/** Minimum controller delay in microseconds (0 s) */ +/** Minimum controller delay in microseconds (0 us) */ #define BT_ISO_CONTROLLER_DELAY_MIN 0x000000 -/** Maximum controller delay in microseconds (4 s) */ +/** Maximum controller delay in microseconds (4,000,000 us) */ #define BT_ISO_CONTROLLER_DELAY_MAX 0x3D0900 -/** Minimum interval value in microseconds */ +/** Minimum interval value in microseconds (255 us) */ #define BT_ISO_SDU_INTERVAL_MIN 0x0000FFU -/** Maximum interval value in microseconds */ +/** Maximum interval value in microseconds (1,048,575 us) */ #define BT_ISO_SDU_INTERVAL_MAX 0x0FFFFFU -/** Minimum ISO interval (N * 1.25 ms) */ +/** Minimum ISO interval in units of 1.25 ms (5 ms) */ #define BT_ISO_ISO_INTERVAL_MIN 0x0004U -/** Maximum ISO interval (N * 1.25 ms) */ +/** Maximum ISO interval in units of 1.25 ms (4,000 ms) */ #define BT_ISO_ISO_INTERVAL_MAX 0x0C80U -/** Minimum latency value in milliseconds */ +/** Minimum latency value in milliseconds (5 ms) */ #define BT_ISO_LATENCY_MIN 0x0005 -/** Maximum latency value in milliseconds */ +/** Maximum latency value in milliseconds (4,000 ms)*/ #define BT_ISO_LATENCY_MAX 0x0FA0 /** Packets will be sent sequentially between the channels in the group */ #define BT_ISO_PACKING_SEQUENTIAL 0x00 @@ -99,62 +99,73 @@ extern "C" { #define BT_ISO_FRAMING_UNFRAMED 0x00 /** Packets are always framed */ #define BT_ISO_FRAMING_FRAMED 0x01 -/** Maximum number of isochronous channels in a single group */ +/** Maximum number of isochronous channels in a single group (31) */ #define BT_ISO_MAX_GROUP_ISO_COUNT 0x1F -/** Minimum SDU size */ +/** Minimum SDU size (1 octet) */ #define BT_ISO_MIN_SDU 0x0001 -/** Maximum SDU size */ +/** Maximum SDU size (4095 octets) */ #define BT_ISO_MAX_SDU 0x0FFF -/** Minimum PDU size */ +/** Minimum PDU size (0 octet) */ #define BT_ISO_CONNECTED_PDU_MIN 0x0000U -/** Minimum PDU size */ +/** Minimum PDU size (1 octet) */ #define BT_ISO_BROADCAST_PDU_MIN 0x0001U -/** Maximum PDU size */ +/** Maximum PDU size (251 octets) */ #define BT_ISO_PDU_MAX 0x00FBU -/** Minimum burst number */ +/** Minimum burst number (1) */ #define BT_ISO_BN_MIN 0x01U -/** Maximum burst number */ +/** Maximum burst number (15) */ #define BT_ISO_BN_MAX 0x0FU -/** Minimum flush timeout */ +/** Minimum flush timeout in multiples of ISO interval (1) */ #define BT_ISO_FT_MIN 0x01U -/** Maximum flush timeout */ +/** Maximum flush timeout in multiples of ISO interval (255) */ #define BT_ISO_FT_MAX 0xFFU -/** Minimum number of subevents */ +/** Minimum number of subevents (1) */ #define BT_ISO_NSE_MIN 0x01U -/** Maximum number of subevents */ +/** Maximum number of subevents (31) */ #define BT_ISO_NSE_MAX 0x1FU -/** Minimum BIG sync timeout value (N * 10 ms) */ +/** Minimum BIG sync timeout value in units of 10 ms (100 ms) */ #define BT_ISO_SYNC_TIMEOUT_MIN 0x000A -/** Maximum BIG sync timeout value (N * 10 ms) */ +/** Maximum BIG sync timeout value in units of 10 ms (163,840 ms) */ #define BT_ISO_SYNC_TIMEOUT_MAX 0x4000 /** Controller controlled maximum subevent count value */ #define BT_ISO_SYNC_MSE_ANY 0x00 -/** Minimum BIG sync maximum subevent count value */ +/** Minimum BIG sync maximum subevent count value (1) */ #define BT_ISO_SYNC_MSE_MIN 0x01 -/** Maximum BIG sync maximum subevent count value */ +/** Maximum BIG sync maximum subevent count value (31) */ #define BT_ISO_SYNC_MSE_MAX 0x1F -/** Maximum connected ISO retransmission value */ +/** Minimum connected ISO retransmission value (0) */ +#define BT_ISO_CONNECTED_RTN_MIN 0x00 +/** Maximum connected ISO retransmission value (255) */ #define BT_ISO_CONNECTED_RTN_MAX 0xFF -/** Maximum broadcast ISO retransmission value */ +/** Minimum broadcast ISO retransmission value (0) */ +#define BT_ISO_BROADCAST_RTN_MIN 0x00 +/** Maximum broadcast ISO retransmission value (30) */ #define BT_ISO_BROADCAST_RTN_MAX 0x1E -/** Broadcast code size */ -#define BT_ISO_BROADCAST_CODE_SIZE 16 -/** Lowest BIS index */ +/** Broadcast code size (16 octets) */ +#define BT_ISO_BROADCAST_CODE_SIZE 0x10 +/** Lowest BIS index (1) */ #define BT_ISO_BIS_INDEX_MIN 0x01 -/** Highest BIS index */ +/** Highest BIS index (31) */ #define BT_ISO_BIS_INDEX_MAX 0x1F -/** Minimum Immediate Repetition Count */ +/** Minimum Immediate Repetition Count (1) */ #define BT_ISO_IRC_MIN 0x01U -/** Maximum Immediate Repetition Count */ +/** Maximum Immediate Repetition Count (15) */ #define BT_ISO_IRC_MAX 0x0FU -/** Minimum pre-transmission offset */ +/** Minimum pre-transmission offset (0) */ #define BT_ISO_PTO_MIN 0x00U -/** Maximum pre-transmission offset */ +/** Maximum pre-transmission offset (15) */ #define BT_ISO_PTO_MAX 0x0FU /** No subinterval */ -#define BT_ISO_SUBINTERVAL_NONE 0x00000000U +#define BT_ISO_SUBINTERVAL_NONE 0x00000000U /** Unknown subinterval */ -#define BT_ISO_SUBINTERVAL_UNKNOWN 0xFFFFFFFFU +#define BT_ISO_SUBINTERVAL_UNKNOWN 0xFFFFFFFFU +/** Minimum subinterval in microseconds (400 us) */ +#define BT_ISO_SUBINTERVAL_MIN 0x00000190U +/** @brief Maximum subinterval in microseconds (3,999,999 us) + * + * This maximum depends on the ISO interval, as the subinterval shall be less than the ISO interval + */ +#define BT_ISO_SUBINTERVAL_MAX 0x00009C3FU /** * @brief Check if ISO BIS bitfield is valid (BT_ISO_BIS_INDEX_BIT(1)|..|BT_ISO_BIS_INDEX_BIT(31)) @@ -1302,6 +1313,9 @@ int bt_iso_big_create(struct bt_le_ext_adv *padv, struct bt_iso_big_create_param /** * @brief Terminates a BIG as a broadcaster or receiver * + * This function cannot be called while in @ref bt_iso_big_cb.started, @ref bt_iso_big_cb.stopped, + * @ref bt_iso_chan_ops.connected or @ref bt_iso_chan_ops.disconnected callbacks. + * * @param big Pointer to the BIG structure. * * @return 0 in case of success or negative value in case of error. diff --git a/include/zephyr/bluetooth/mesh/statistic.h b/include/zephyr/bluetooth/mesh/statistic.h index 288cd77ff8ff3..33b374803b8f6 100644 --- a/include/zephyr/bluetooth/mesh/statistic.h +++ b/include/zephyr/bluetooth/mesh/statistic.h @@ -51,7 +51,7 @@ struct bt_mesh_statistic { /** @brief Get mesh frame handling statistic. * - * @param st Bluetooh Mesh statistic. + * @param st Bluetooth Mesh statistic. */ void bt_mesh_stat_get(struct bt_mesh_statistic *st); diff --git a/include/zephyr/cache.h b/include/zephyr/cache.h index d113071dcaff7..bf4b2eb579d37 100644 --- a/include/zephyr/cache.h +++ b/include/zephyr/cache.h @@ -35,15 +35,6 @@ extern "C" { * @{ */ -/** - * @cond INTERNAL_HIDDEN - * - */ - -#define _CPU DT_PATH(cpus, cpu_0) - -/** @endcond */ - /** * @brief Enable the d-cache * @@ -398,7 +389,6 @@ static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t * * - At run-time when @kconfig{CONFIG_DCACHE_LINE_SIZE_DETECT} is set. * - At compile time using the value set in @kconfig{CONFIG_DCACHE_LINE_SIZE}. - * - At compile time using the `d-cache-line-size` CPU0 property of the DT. * - 0 otherwise * * @retval size Size of the d-cache line. @@ -408,10 +398,10 @@ static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void) { #ifdef CONFIG_DCACHE_LINE_SIZE_DETECT return cache_data_line_size_get(); -#elif (CONFIG_DCACHE_LINE_SIZE != 0) +#elif defined(CONFIG_DCACHE_LINE_SIZE) return CONFIG_DCACHE_LINE_SIZE; #else - return DT_PROP_OR(_CPU, d_cache_line_size, 0); + return 0; #endif } @@ -425,7 +415,6 @@ static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void) * * - At run-time when @kconfig{CONFIG_ICACHE_LINE_SIZE_DETECT} is set. * - At compile time using the value set in @kconfig{CONFIG_ICACHE_LINE_SIZE}. - * - At compile time using the `i-cache-line-size` CPU0 property of the DT. * - 0 otherwise * * @retval size Size of the d-cache line. @@ -435,10 +424,10 @@ static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void) { #ifdef CONFIG_ICACHE_LINE_SIZE_DETECT return cache_instr_line_size_get(); -#elif (CONFIG_ICACHE_LINE_SIZE != 0) +#elif defined(CONFIG_ICACHE_LINE_SIZE) return CONFIG_ICACHE_LINE_SIZE; #else - return DT_PROP_OR(_CPU, i_cache_line_size, 0); + return 0; #endif } diff --git a/include/zephyr/cpu_freq/cpu_freq.h b/include/zephyr/cpu_freq/cpu_freq.h new file mode 100644 index 0000000000000..8936b29495188 --- /dev/null +++ b/include/zephyr/cpu_freq/cpu_freq.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_CPU_FREQ_H_ +#define ZEPHYR_SUBSYS_CPU_FREQ_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @brief Dynamic CPU Frequency Scaling + * @defgroup subsys_cpu_freq CPU Frequency (CPUFreq) + * @since 4.3 + * @version 0.1.0 + * @ingroup os_services + * @{ + */ + +/** + * @brief Request processor set the given performance state. + * + * To be implemented by the SoC. This API abstracts the hardware and SoC specific calls required to + * change the performance state of the processor. + * + * @note It is not guaranteed that the performance state will be set immediately, or at all. + * + * @param state Pointer to performance state. + * + * + * @retval 0 if request received successfully, -errno in case of failure. + */ +int cpu_freq_pstate_set(const struct pstate *state); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SUBSYS_CPU_FREQ_H_ */ diff --git a/include/zephyr/cpu_freq/policy.h b/include/zephyr/cpu_freq/policy.h new file mode 100644 index 0000000000000..0cfde039c6538 --- /dev/null +++ b/include/zephyr/cpu_freq/policy.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_CPU_FREQ_POLICY_H_ +#define ZEPHYR_SUBSYS_CPU_FREQ_POLICY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CPU Frequency Policy Interface - to be implemented by each policy. + */ + +#include +#include + + +/** + * @brief CPU Frequency Scaling Policy + * @defgroup subsys_cpu_freq_policy CPU Frequency Policy + * @since 4.3 + * @version 0.1.0 + * @ingroup subsys_cpu_freq + * @{ + */ + +/** + * @brief Get the next P-state from CPU Frequency Policy + * + * This function is implemented by a CPU Freq policy selected via Kconfig. + * + * @param pstate Pointer to the P-state struct where the next P-state is returned. + * + * @retval 0 in case of success, nonzero in case of failure. + */ +int cpu_freq_policy_select_pstate(const struct pstate **pstate); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SUBSYS_CPU_FREQ_POLICY_H_ */ diff --git a/include/zephyr/cpu_freq/pstate.h b/include/zephyr/cpu_freq/pstate.h new file mode 100644 index 0000000000000..d3a2073a8ec4f --- /dev/null +++ b/include/zephyr/cpu_freq/pstate.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_CPU_FREQ_PSTATE_H_ +#define ZEPHYR_SUBSYS_CPU_FREQ_PSTATE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @brief CPU Frequency Scaling Performance State (pstate) + * @defgroup subsys_cpu_freq_pstate CPU Frequency pstate + * @since 4.3 + * @version 0.1.0 + * @ingroup subsys_cpu_freq + * @{ + */ + +/** Synthesize symbol of pstate from devicetree dependency ordinal */ +#define PSTATE_DT_SYM(_node) _CONCAT(__pstate_, DT_DEP_ORD(_node)) + +/** + * @brief Define all pstate information for the given node identifier. + * + * @param _node Node identifier. + * @param _config Pointer to the SoC specific configuration for the pstate. + */ +#define PSTATE_DT_DEFINE(_node, _config) \ + const struct pstate PSTATE_DT_SYM(_node) = { \ + .load_threshold = DT_PROP(_node, load_threshold), \ + .config = _config, \ + }; + +/** + * @brief Get a pstate reference from a devicetree node identifier. + * + * To be used in DT_FOREACH_CHILD() or similar macros + * + * @param _node Node identifier. + */ +#define PSTATE_DT_GET(_node) &PSTATE_DT_SYM(_node) + + +/** + * @brief CPU performance state (pstate) struct. + * + * This struct holds information about a CPU pstate as well as a reference to vendor-specific + * devicetree properties. + */ +struct pstate { + uint8_t load_threshold; /**< CPU load threshold at which P-state should be triggered */ + const void *config; /**< Vendor specific devicetree properties */ +}; + +/* Define performance-states as extern to be picked up by CPU Freq policy */ +#define Z_DECLARE_PSTATE_EXTERN(_node) \ + extern const struct pstate PSTATE_DT_SYM(_node); + +DT_FOREACH_CHILD_STATUS_OKAY(DT_PATH(performance_states), Z_DECLARE_PSTATE_EXTERN) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SUBSYS_CPU_FREQ_PSTATE_H_ */ diff --git a/include/zephyr/cpu_load/cpu_load.h b/include/zephyr/cpu_load/cpu_load.h new file mode 100644 index 0000000000000..44dd09f808753 --- /dev/null +++ b/include/zephyr/cpu_load/cpu_load.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_CPU_LOAD_H_ +#define ZEPHYR_SUBSYS_CPU_LOAD_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief CPU Load Monitoring + * @defgroup subsys_cpu_load CPU Load + * @since 4.3 + * @version 0.1.0 + * @ingroup os_services + * @{ + */ + +/** + * @brief Get the CPU load as a percentage. + * + * Return the percent that the CPU has spent in the active (non-idle) state between calls to this + * function. + * + * @param cpu_id The ID of the CPU for which to get the load. + * + * @retval CPU load in percent (0-100) in case of success + * @retval -errno code in case of failure. + * + */ +int cpu_load_get(int cpu_id); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SUBSYS_CPU_LOAD_H_ */ diff --git a/include/zephyr/crypto/cipher.h b/include/zephyr/crypto/cipher.h index 71d8e590b41be..4430b62b42127 100644 --- a/include/zephyr/crypto/cipher.h +++ b/include/zephyr/crypto/cipher.h @@ -47,6 +47,8 @@ enum cipher_mode { CRYPTO_CIPHER_MODE_CTR = 3, CRYPTO_CIPHER_MODE_CCM = 4, CRYPTO_CIPHER_MODE_GCM = 5, + CRYPTO_CIPHER_MODE_CFB = 6, + CRYPTO_CIPHER_MODE_OFB = 7, }; /* Forward declarations */ @@ -57,7 +59,7 @@ struct cipher_pkt; typedef int (*block_op_t)(struct cipher_ctx *ctx, struct cipher_pkt *pkt); /* Function signatures for encryption/ decryption using standard cipher modes - * like CBC, CTR, CCM. + * like CBC, CTR, CCM, CFB, OFB. */ typedef int (*cbc_op_t)(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv); @@ -71,6 +73,10 @@ typedef int (*ccm_op_t)(struct cipher_ctx *ctx, struct cipher_aead_pkt *pkt, typedef int (*gcm_op_t)(struct cipher_ctx *ctx, struct cipher_aead_pkt *pkt, uint8_t *nonce); +typedef int (*cfb_op_t)(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv); + +typedef int (*ofb_op_t)(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv); + struct cipher_ops { enum cipher_mode cipher_mode; @@ -81,6 +87,8 @@ struct cipher_ops { ctr_op_t ctr_crypt_hndlr; ccm_op_t ccm_crypt_hndlr; gcm_op_t gcm_crypt_hndlr; + cfb_op_t cfb_crypt_hndlr; + ofb_op_t ofb_crypt_hndlr; }; }; diff --git a/include/zephyr/crypto/crypto.h b/include/zephyr/crypto/crypto.h index 6a8ad73e7142c..8dec4a233ae4b 100644 --- a/include/zephyr/crypto/crypto.h +++ b/include/zephyr/crypto/crypto.h @@ -280,6 +280,48 @@ static inline int cipher_cbc_op(struct cipher_ctx *ctx, return ctx->ops.cbc_crypt_hndlr(ctx, pkt, iv); } +/** + * @brief Perform Cipher Feedback (CFB) crypto operation. + * + * @param ctx Pointer to the crypto context of this op. + * @param pkt Structure holding the input/output buffer pointers. + * @param iv Initialization Vector (IV) for the operation. Same + * IV value should not be reused across multiple + * operations (within a session context) for security. + * + * @return 0 on success, negative errno code on fail. + */ +static inline int cipher_cfb_op(struct cipher_ctx *ctx, + struct cipher_pkt *pkt, uint8_t *iv) +{ + __ASSERT(ctx->ops.cipher_mode == CRYPTO_CIPHER_MODE_CFB, "CFB mode " + "session invoking a different mode handler"); + + pkt->ctx = ctx; + return ctx->ops.cfb_crypt_hndlr(ctx, pkt, iv); +} + +/** + * @brief Perform Output Feedback (OFB) mode crypto operation. + * + * @param ctx Pointer to the crypto context of this op. + * @param pkt Structure holding the input/output buffer pointers. + * @param iv Initialization Vector (IV) for the operation. Same + * IV value should not be reused across multiple + * operations (within a session context) for security. + * + * @return 0 on success, negative errno code on fail. + */ +static inline int cipher_ofb_op(struct cipher_ctx *ctx, + struct cipher_pkt *pkt, uint8_t *iv) +{ + __ASSERT(ctx->ops.cipher_mode == CRYPTO_CIPHER_MODE_OFB, "OFB mode " + "session invoking a different mode handler"); + + pkt->ctx = ctx; + return ctx->ops.ofb_crypt_hndlr(ctx, pkt, iv); +} + /** * @brief Perform Counter (CTR) mode crypto operation. * diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h index 68dac5081f8b8..ded261d66cd08 100644 --- a/include/zephyr/devicetree.h +++ b/include/zephyr/devicetree.h @@ -3817,6 +3817,134 @@ #define DT_PHA_HAS_CELL(node_id, pha, cell) \ DT_PHA_HAS_CELL_AT_IDX(node_id, pha, 0, cell) +/** + * @brief Iterate over all cells in a phandle array element by index + * + * This macro calls @p fn(cell_value) for each cell value in the + * phandle array element at index @p idx. + * + * In general, this macro expands to: + * + * fn(node_id, pha, idx, cell[0]) fn(node_id, pha, idx, cell[1]) [...] + * fn(node_id, pha, idx, cell[n-1]) + * + * where `n` is the number of cells in @p pha, as it would be + * returned by `DT_PHA_NUM_CELLS_BY_IDX(node_id, pha, idx)`, and cell[x] is the NAME of the cell + * in the specifier. + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param idx index of the phandle array element + * @param fn macro to call for each cell value + */ +#define DT_FOREACH_PHA_CELL_BY_IDX(node_id, pha, idx, fn) \ + DT_CAT6(node_id, _P_, pha, _IDX_, idx, _FOREACH_CELL)(fn) + +/** + * @brief Iterate over all cells in a phandle array element by index with separator + * + * This is like DT_FOREACH_PHA_CELL_BY_IDX(), but @p sep is placed between + * each invocation of @p fn. + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param idx index of the phandle array element + * @param fn macro to call for each cell value + * @param sep separator (e.g. comma or semicolon) + */ +#define DT_FOREACH_PHA_CELL_BY_IDX_SEP(node_id, pha, idx, fn, sep) \ + DT_CAT6(node_id, _P_, pha, _IDX_, idx, _FOREACH_CELL_SEP)(fn, sep) + +/** + * @brief Get the number of cells in a phandle array element by index + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param idx index of the phandle array element + * @return number of cells in the element at index @p idx + */ +#define DT_PHA_NUM_CELLS_BY_IDX(node_id, pha, idx) \ + DT_CAT6(node_id, _P_, pha, _IDX_, idx, _NUM_CELLS) + +/** + * @brief Get the name of a phandle array element by index + * + * This returns the name in the *-names property of the node + * corresponding to the index @p idx of @p pha + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param idx index of the phandle array element + * @return name of the element at index @p idx + */ +#define DT_PHA_ELEM_NAME_BY_IDX(node_id, pha, idx) \ + DT_CAT6(node_id, _P_, pha, _IDX_, idx, _NAME) + +/** + * @brief Iterate over all cells in a phandle array element by name + * + * This macro calls @p fn(cell_value) for each cell value in the + * phandle array @p pha element with the given @p name in the *-names property. + * + * In general, this macro expands to: + * + * fn(node_id, pha, name, cell[0]) fn(node_id, pha, idx, cell[1]) [...] + * fn(node_id, pha, idx, cell[n-1]) + * + * where `n` is the number of cells in @p pha, as it would be + * returned by `DT_PHA_NUM_CELLS_BY_NAME(node_id, pha, name)`, and cell[x] is the NAME of the cell + * in the specifier. + * + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param name lowercase-and-underscores name of the phandle array element + * @param fn macro to call for each cell value + */ +#define DT_FOREACH_PHA_CELL_BY_NAME(node_id, pha, name, fn) \ + DT_CAT6(node_id, _P_, pha, _NAME_, name, _FOREACH_CELL)(fn) + +/** + * @brief Iterate over all cells in a phandle array element by name with separator + * + * This is like DT_FOREACH_PHA_CELL_BY_NAME(), but @p sep is placed between + * each invocation of @p fn. + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param name lowercase-and-underscores name of the phandle array element + * @param fn macro to call for each cell value + * @param sep separator (e.g. comma or semicolon) + */ +#define DT_FOREACH_PHA_CELL_BY_NAME_SEP(node_id, pha, name, fn, sep) \ + DT_CAT6(node_id, _P_, pha, _NAME_, name, _FOREACH_CELL_SEP)(fn, sep) + +/** + * @brief Get the number of cells in a phandle array element by name + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param name lowercase-and-underscores name of the phandle array element + * @return number of cells in the element with the given @p name + */ +#define DT_PHA_NUM_CELLS_BY_NAME(node_id, pha, name) \ + DT_CAT6(node_id, _P_, pha, _NAME_, name, _NUM_CELLS) + +/** + * @brief Get the index of a phandle array element by name + * + * This returns the index of the @p pha which has the name @p name in the corresponding + * *-names property. + * + * @param node_id node identifier + * @param pha lowercase-and-underscores property with type `phandle-array` + * @param name lowercase-and-underscores name of the phandle array element + * @return index of the element with the given @p name + */ +#define DT_PHA_ELEM_IDX_BY_NAME(node_id, pha, name) \ + DT_CAT6(node_id, _P_, pha, _NAME_, name, _IDX) + + /** * @} */ diff --git a/include/zephyr/devicetree/can.h b/include/zephyr/devicetree/can.h index a98a3ea7f0e0f..9097a9b3f53c1 100644 --- a/include/zephyr/devicetree/can.h +++ b/include/zephyr/devicetree/can.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-can Devicetree CAN API * @ingroup devicetree + * @ingroup can_interface * @{ */ diff --git a/include/zephyr/devicetree/clocks.h b/include/zephyr/devicetree/clocks.h index 1721de650ec90..8a345bfd12e46 100644 --- a/include/zephyr/devicetree/clocks.h +++ b/include/zephyr/devicetree/clocks.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-clocks Devicetree Clocks API * @ingroup devicetree + * @ingroup clock_control_interface * @{ */ diff --git a/include/zephyr/devicetree/display.h b/include/zephyr/devicetree/display.h index f73fdf5cd823c..833e06c9715ec 100644 --- a/include/zephyr/devicetree/display.h +++ b/include/zephyr/devicetree/display.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-display Devicetree Display API * @ingroup devicetree + * @ingroup display_interface * @{ */ diff --git a/include/zephyr/devicetree/dma.h b/include/zephyr/devicetree/dma.h index 3dff82928f6f5..3dc1eac4e2c7e 100644 --- a/include/zephyr/devicetree/dma.h +++ b/include/zephyr/devicetree/dma.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-dmas Devicetree DMA API * @ingroup devicetree + * @ingroup dma_interface * @{ */ diff --git a/include/zephyr/devicetree/gpio.h b/include/zephyr/devicetree/gpio.h index 93426796f8965..3c8ca264e3f05 100644 --- a/include/zephyr/devicetree/gpio.h +++ b/include/zephyr/devicetree/gpio.h @@ -20,7 +20,13 @@ extern "C" { /** * @defgroup devicetree-gpio Devicetree GPIO API * @ingroup devicetree + * @ingroup gpio_interface * @{ + * + * @defgroup devicetree-gpio-pin-headers GPIO pin headers + * @brief Constants for pins exposed on common GPIO pin headers + * @{ + * @} */ /** diff --git a/include/zephyr/devicetree/mbox.h b/include/zephyr/devicetree/mbox.h index d1e990e247083..d3d47db7f4cb1 100644 --- a/include/zephyr/devicetree/mbox.h +++ b/include/zephyr/devicetree/mbox.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-mbox Devicetree MBOX API * @ingroup devicetree + * @ingroup mbox_interface * @{ */ diff --git a/include/zephyr/devicetree/pinctrl.h b/include/zephyr/devicetree/pinctrl.h index a5fde6a8fc162..0e86c389b184f 100644 --- a/include/zephyr/devicetree/pinctrl.h +++ b/include/zephyr/devicetree/pinctrl.h @@ -14,6 +14,7 @@ /** * @defgroup devicetree-pinctrl Pin control * @ingroup devicetree + * @ingroup pinctrl_interface * @{ */ diff --git a/include/zephyr/devicetree/pwms.h b/include/zephyr/devicetree/pwms.h index 4f5e8d41a9764..4b43abc412350 100644 --- a/include/zephyr/devicetree/pwms.h +++ b/include/zephyr/devicetree/pwms.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-pwms Devicetree PWMs API * @ingroup devicetree + * @ingroup pwm_interface * @{ */ diff --git a/include/zephyr/devicetree/reset.h b/include/zephyr/devicetree/reset.h index bb1f9bf888b47..9ce1d6d7e0f6a 100644 --- a/include/zephyr/devicetree/reset.h +++ b/include/zephyr/devicetree/reset.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-reset-controller Devicetree Reset Controller API * @ingroup devicetree + * @ingroup reset_controller_interface * @{ */ diff --git a/include/zephyr/devicetree/spi.h b/include/zephyr/devicetree/spi.h index db1b4996f6440..321bfc1cb1300 100644 --- a/include/zephyr/devicetree/spi.h +++ b/include/zephyr/devicetree/spi.h @@ -19,6 +19,7 @@ extern "C" { /** * @defgroup devicetree-spi Devicetree SPI API * @ingroup devicetree + * @ingroup spi_interface * @{ */ diff --git a/include/zephyr/display/mipi_display.h b/include/zephyr/display/mipi_display.h index f369cb8de42c7..cd271334e7af0 100644 --- a/include/zephyr/display/mipi_display.h +++ b/include/zephyr/display/mipi_display.h @@ -7,6 +7,7 @@ /** * @file * @brief Display definitions for MIPI devices + * @ingroup mipi_interface */ #ifndef ZEPHYR_INCLUDE_DISPLAY_MIPI_DISPLAY_H_ @@ -15,11 +16,10 @@ /** * @brief MIPI Display definitions * @defgroup mipi_interface MIPI Display interface - * @ingroup io_interfaces + * @ingroup display_interface * @{ */ - #ifdef __cplusplus extern "C" { #endif diff --git a/include/zephyr/drivers/adc.h b/include/zephyr/drivers/adc.h index cd9a465fdba1c..596990f7d61f5 100644 --- a/include/zephyr/drivers/adc.h +++ b/include/zephyr/drivers/adc.h @@ -1,8 +1,3 @@ -/** - * @file - * @brief ADC public API header file. - */ - /* * Copyright (c) 2018 Nordic Semiconductor ASA * Copyright (c) 2015 Intel Corporation @@ -10,6 +5,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup adc_interface + * @brief Main header file for ADC (Analog-to-Digital Converter) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_ADC_H_ #define ZEPHYR_INCLUDE_DRIVERS_ADC_H_ @@ -22,8 +23,8 @@ extern "C" { #endif /** - * @brief ADC driver APIs - * @defgroup adc_interface ADC driver APIs + * @brief Interfaces for Analog-to-Digital Converters (ADC). + * @defgroup adc_interface ADC * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/auxdisplay.h b/include/zephyr/drivers/auxdisplay.h index a56c9b7699380..4927e86df52e9 100644 --- a/include/zephyr/drivers/auxdisplay.h +++ b/include/zephyr/drivers/auxdisplay.h @@ -6,15 +6,16 @@ /** * @file - * @brief Public API for auxiliary (textual/non-graphical) display drivers + * @ingroup auxdisplay_interface + * @brief Main header file for auxiliary (textual/non-graphical) display driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_AUXDISPLAY_H_ #define ZEPHYR_INCLUDE_DRIVERS_AUXDISPLAY_H_ /** - * @brief Auxiliary (Text) Display Interface - * @defgroup auxdisplay_interface Text Display Interface + * @brief Interfaces for auxiliary (textual/non-graphical) displays. + * @defgroup auxdisplay_interface Auxiliary (Text) Display * @since 3.4 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/bbram.h b/include/zephyr/drivers/bbram.h index 30df6a5dd7d2b..55dd11ec4e1f2 100644 --- a/include/zephyr/drivers/bbram.h +++ b/include/zephyr/drivers/bbram.h @@ -4,6 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup bbram_interface + * @brief Main header file for Battery-Backed RAM (BBRAM) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_BBRAM_H #define ZEPHYR_INCLUDE_DRIVERS_BBRAM_H @@ -12,8 +18,8 @@ #include /** - * @brief BBRAM Interface - * @defgroup bbram_interface BBRAM Interface + * @brief Interfaces for Battery-Backed RAM (BBRAM). + * @defgroup bbram_interface BBRAM * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/bluetooth.h b/include/zephyr/drivers/bluetooth.h index 7e3a72be1fb90..b86ae24e06b8a 100644 --- a/include/zephyr/drivers/bluetooth.h +++ b/include/zephyr/drivers/bluetooth.h @@ -5,12 +5,19 @@ * * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @ingroup bt_hci_api + * @brief Main header file for Bluetooth HCI driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_BLUETOOTH_H_ #define ZEPHYR_INCLUDE_DRIVERS_BLUETOOTH_H_ /** - * @brief Bluetooth HCI APIs - * @defgroup bt_hci_api Bluetooth HCI APIs + * @brief Interfaces for Bluetooth Host Controller Interface (HCI). + * @defgroup bt_hci_api Bluetooth HCI * * @since 3.7 * @version 0.2.0 @@ -72,8 +79,6 @@ enum bt_hci_bus { BT_HCI_BUS_SMD = 9, BT_HCI_BUS_VIRTIO = 10, BT_HCI_BUS_IPC = 11, - /* IPM is deprecated and simply an alias for IPC */ - BT_HCI_BUS_IPM = BT_HCI_BUS_IPC, }; #define BT_DT_HCI_QUIRK_OR(node_id, prop, idx) \ @@ -89,8 +94,8 @@ enum bt_hci_bus { #define BT_DT_HCI_NAME_GET(node_id) DT_PROP_OR(node_id, bt_hci_name, "HCI") #define BT_DT_HCI_NAME_INST_GET(inst) BT_DT_HCI_NAME_GET(DT_DRV_INST(inst)) -#define BT_DT_HCI_BUS_GET(node_id) \ - UTIL_CAT(BT_HCI_BUS_, DT_STRING_UPPER_TOKEN_OR(node_id, bt_hci_bus, VIRTUAL)) +#define BT_DT_HCI_BUS_GET(node_id) DT_ENUM_IDX_OR(node_id, bt_hci_bus, BT_HCI_BUS_VIRTUAL) + #define BT_DT_HCI_BUS_INST_GET(inst) BT_DT_HCI_BUS_GET(DT_DRV_INST(inst)) typedef int (*bt_hci_recv_t)(const struct device *dev, struct net_buf *buf); diff --git a/include/zephyr/drivers/cache.h b/include/zephyr/drivers/cache.h index b5b01dfea336f..8ad4e817c10f2 100644 --- a/include/zephyr/drivers/cache.h +++ b/include/zephyr/drivers/cache.h @@ -6,7 +6,8 @@ /** * @file - * Public APIs for external cache controller drivers + * @ingroup cache_external_interface + * @brief Main header file for external cache controller driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_CACHE_H_ @@ -15,8 +16,8 @@ #include /** - * @brief External Cache Controller Interface - * @defgroup cache_external_interface External Cache Controller Interface + * @brief Interfaces for external cache controllers. + * @defgroup cache_external_interface External Cache Controller * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index edebeed3fff41..4cfa440b705bb 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -8,7 +8,8 @@ /** * @file - * @brief Controller Area Network (CAN) driver API. + * @brief Header file for Controller Area Network (CAN) controller driver API. + * @ingroup can_controller */ #ifndef ZEPHYR_INCLUDE_DRIVERS_CAN_H_ @@ -28,11 +29,16 @@ extern "C" { #endif /** - * @brief CAN Interface - * @defgroup can_interface CAN Interface + * @brief Interfaces for Controller Area Network (CAN) controllers and transceivers + * @defgroup can_interface CAN + * @ingroup io_interfaces + * + * @defgroup can_controller CAN Controller + * @brief Interfaces for CAN controllers + * @ingroup can_interface * @since 1.12 * @version 1.1.0 - * @ingroup io_interfaces + * * @{ */ diff --git a/include/zephyr/drivers/can/transceiver.h b/include/zephyr/drivers/can/transceiver.h index 9dcf2cafb6c67..67542701101e5 100644 --- a/include/zephyr/drivers/can/transceiver.h +++ b/include/zephyr/drivers/can/transceiver.h @@ -4,6 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup can_transceiver + * @brief Header file for CAN transceiver driver API + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_CAN_TRANSCEIVER_H_ #define ZEPHYR_INCLUDE_DRIVERS_CAN_TRANSCEIVER_H_ @@ -15,11 +21,11 @@ extern "C" { #endif /** - * @brief CAN Transceiver Driver APIs + * @brief Interfaces for CAN transceivers * @defgroup can_transceiver CAN Transceiver * @since 3.1 * @version 0.1.0 - * @ingroup io_interfaces + * @ingroup can_interface * @{ */ diff --git a/include/zephyr/drivers/cellular.h b/include/zephyr/drivers/cellular.h index 91ea72fedf2f0..88e29a272bc11 100644 --- a/include/zephyr/drivers/cellular.h +++ b/include/zephyr/drivers/cellular.h @@ -6,16 +6,17 @@ */ /** - * @file drivers/cellular.h - * @brief Public cellular network API + * @file + * @ingroup cellular_interface + * @brief Main header file for cellular modem driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_CELLULAR_H_ #define ZEPHYR_INCLUDE_DRIVERS_CELLULAR_H_ /** - * @brief Cellular interface - * @defgroup cellular_interface Cellular Interface + * @brief Interfaces for cellular modems. + * @defgroup cellular_interface Cellular * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/charger.h b/include/zephyr/drivers/charger.h index ded5c37d99721..27e4602560e20 100644 --- a/include/zephyr/drivers/charger.h +++ b/include/zephyr/drivers/charger.h @@ -6,15 +6,16 @@ /** * @file - * @brief Charger APIs + * @ingroup charger_interface + * @brief Main header file for battery charger driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_CHARGER_H_ #define ZEPHYR_INCLUDE_DRIVERS_CHARGER_H_ /** - * @brief Charger Interface - * @defgroup charger_interface Charger Interface + * @brief Interfaces for battery chargers. + * @defgroup charger_interface Battery Charger * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/clock_control.h b/include/zephyr/drivers/clock_control.h index 6e322a8b07a34..d09daf9638604 100644 --- a/include/zephyr/drivers/clock_control.h +++ b/include/zephyr/drivers/clock_control.h @@ -8,15 +8,16 @@ /** * @file - * @brief Public Clock Control APIs + * @ingroup clock_control_interface + * @brief Main header file for clock control driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_H_ #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_H_ /** - * @brief Clock Control Interface - * @defgroup clock_control_interface Clock Control Interface + * @brief Interfaces for clock controllers. + * @defgroup clock_control_interface Clock Control * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/clock_control/esp32_clock_control.h b/include/zephyr/drivers/clock_control/esp32_clock_control.h index eb6bebc138ef8..a56e9142e9d5d 100644 --- a/include/zephyr/drivers/clock_control/esp32_clock_control.h +++ b/include/zephyr/drivers/clock_control/esp32_clock_control.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,6 +19,8 @@ #include #elif defined(CONFIG_SOC_SERIES_ESP32C6) #include +#elif defined(CONFIG_SOC_SERIES_ESP32H2) +#include #endif /* CONFIG_SOC_SERIES_ESP32xx */ #define ESP32_CLOCK_CONTROL_SUBSYS_CPU 50 diff --git a/include/zephyr/drivers/comparator.h b/include/zephyr/drivers/comparator.h index 1a6609cafa5b1..d886a9facd2e8 100644 --- a/include/zephyr/drivers/comparator.h +++ b/include/zephyr/drivers/comparator.h @@ -8,8 +8,14 @@ #define ZEPHYR_INCLUDE_DRIVERS_COMPARATOR_H_ /** - * @brief Comparator Interface - * @defgroup comparator_interface Comparator Interface + * @file + * @ingroup comparator_interface + * @brief Main header file for comparator driver API. + */ + +/** + * @brief Interfaces for comparators. + * @defgroup comparator_interface Comparator * @since 4.0 * @version 0.1.0 * @ingroup io_interfaces @@ -35,7 +41,12 @@ enum comparator_trigger { COMPARATOR_TRIGGER_BOTH_EDGES }; -/** Comparator callback template */ +/** + * @brief Comparator callback template + * + * @param dev Comparator device + * @param user_data Pointer to the user data that was provided when the trigger callback was set + */ typedef void (*comparator_callback_t)(const struct device *dev, void *user_data); /** @cond INTERNAL_HIDDEN */ diff --git a/include/zephyr/drivers/coredump.h b/include/zephyr/drivers/coredump.h index e7ebd50e2f078..4a40c87dbf4fd 100644 --- a/include/zephyr/drivers/coredump.h +++ b/include/zephyr/drivers/coredump.h @@ -6,7 +6,8 @@ /** * @file - * @brief Public APIs for coredump pseudo-device driver + * @ingroup coredump_device_interface + * @brief Main header file for coredump pseudo-device driver API. */ #ifndef INCLUDE_ZEPHYR_DRIVERS_COREDUMP_H_ @@ -20,8 +21,8 @@ extern "C" { #endif /** - * @brief Coredump pseudo-device driver APIs - * @defgroup coredump_device_interface Coredump pseudo-device driver APIs + * @brief Interfaces for coredump pseudo-device. + * @defgroup coredump_device_interface Coredump pseudo-device * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/counter.h b/include/zephyr/drivers/counter.h index d929c0d8332a0..f8d19bc69dafa 100644 --- a/include/zephyr/drivers/counter.h +++ b/include/zephyr/drivers/counter.h @@ -7,15 +7,16 @@ /** * @file - * @brief Public API for counter and timer drivers + * @ingroup counter_interface + * @brief Main header file for counter driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_COUNTER_H_ #define ZEPHYR_INCLUDE_DRIVERS_COUNTER_H_ /** - * @brief Counter Interface - * @defgroup counter_interface Counter Interface + * @brief Interfaces for counters. + * @defgroup counter_interface Counter * @since 1.14 * @version 0.8.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/crc.h b/include/zephyr/drivers/crc.h new file mode 100644 index 0000000000000..ec840d725dbf1 --- /dev/null +++ b/include/zephyr/drivers/crc.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2024 Brill Power Ltd. + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief CRC public API header file. + * @ingroup crc_interface + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CRC_H +#define ZEPHYR_INCLUDE_DRIVERS_CRC_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Interfaces for Cyclic Redundancy Check (CRC) devices. + * @defgroup crc_interface CRC driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @name CRC input/output string flags + * @anchor CRC_FLAGS + * + * @{ + */ + +/** + * @brief Reverse input string + */ +#define CRC_FLAG_REVERSE_INPUT BIT(0) + +/** + * @brief Reverse output string + */ +#define CRC_FLAG_REVERSE_OUTPUT BIT(1) + +/** @} */ + +/** + * @cond INTERNAL_HIDDEN + * Internally seed values for CRC algorithms are defined. + * These values are used to initialize the CRC calculation. + */ + +/** CRC4 initial value */ +#define CRC4_INIT_VAL 0x0 + +/** CRC4_TI initial value */ +#define CRC4_TI_INIT_VAL 0x0 + +/** CRC7_BE initial value */ +#define CRC7_BE_INIT_VAL 0x0 + +/** CRC8 initial value */ +#define CRC8_INIT_VAL 0x0 + +/** CRC8_CCITT initial value */ +#define CRC8_CCITT_INIT_VAL 0xFF + +/** CRC8_ROHC initial value */ +#define CRC8_ROHC_INIT_VAL 0xFF + +/** CRC16 initial value */ +#define CRC16_INIT_VAL 0x0 + +/** CRC16_ANSI initial value */ +#define CRC16_ANSI_INIT_VAL 0x0 + +/** CRC16_CCITT initial value */ +#define CRC16_CCITT_INIT_VAL 0x0000 + +/** CRC16_ITU_T initial value */ +#define CRC16_ITU_T_INIT_VAL 0x0000 + +/** CRC24_PGP initial value */ +#define CRC24_PGP_INIT_VALUE 0x00B704CEU + +/** CRC32_C initial value */ +#define CRC32_IEEE_INIT_VAL 0xFFFFFFFFU + +/** CRC32_K_4_2 initial value */ +#define CRC32_C_INIT_VAL 0xFFFFFFFFU + +/** @endcond */ + +/** + * @brief CRC state enumeration + */ + +enum crc_state { + /** CRC device is in IDLE state. */ + CRC_STATE_IDLE = 0, + /** CRC calculation is in-progress. */ + CRC_STATE_IN_PROGRESS +}; + +/** + * @brief Provides a type to hold CRC initial seed value + */ +typedef uint32_t crc_init_val_t; + +/** + * @brief Provides a type to hold CRC polynomial value. + * See @a CRC_POLYNOMIAL for predefined polynomial values. + */ +typedef uint32_t crc_poly_t; + +/** + * @brief Provides a type to hold CRC result value + */ +typedef uint32_t crc_result_t; + +/** + * @brief CRC context structure + * + * This structure holds the state of the CRC calculation, including + * the type of CRC being calculated, the current state, the polynomial, + * the initial seed value, and the result of the CRC calculation. + */ + +struct crc_ctx { + /** CRC calculation type */ + enum crc_type type; + /** Current CRC device state */ + enum crc_state state; + /** CRC input/output reverse flags */ + uint32_t reversed; + /** CRC polynomial */ + crc_poly_t polynomial; + /** CRC initial seed value */ + crc_init_val_t seed; + /** CRC result */ + crc_result_t result; +}; + +/** + * @brief Callback API upon CRC calculation begin + * See @a crc_begin() for argument description + */ +typedef int (*crc_api_begin)(const struct device *dev, struct crc_ctx *ctx); + +/** + * @brief Callback API upon CRC calculation stream update + * See @a crc_update() for argument description + */ +typedef int (*crc_api_update)(const struct device *dev, struct crc_ctx *ctx, const void *buffer, + size_t bufsize); + +/** + * @brief Callback API upon CRC calculation finish + * See @a crc_finish() for argument description + */ +typedef int (*crc_api_finish)(const struct device *dev, struct crc_ctx *ctx); + +__subsystem struct crc_driver_api { + crc_api_begin begin; + crc_api_update update; + crc_api_finish finish; +}; + +/** + * @brief Configure CRC unit for calculation + * + * @param dev Pointer to the device structure + * @param ctx Pointer to the CRC context structure + * + * @retval 0 if successful + * @retval -ENOSYS if function is not implemented + * @retval errno code on failure + */ +__syscall int crc_begin(const struct device *dev, struct crc_ctx *ctx); + +static inline int z_impl_crc_begin(const struct device *dev, struct crc_ctx *ctx) +{ + const struct crc_driver_api *api = (const struct crc_driver_api *)dev->api; + + if (api->begin == NULL) { + return -ENOSYS; + } + + return api->begin(dev, ctx); +} + +/** + * @brief Perform CRC calculation on the provided data buffer and retrieve result + * + * @param dev Pointer to the device structure + * @param ctx Pointer to the CRC context structure + * @param buffer Pointer to input data buffer + * @param bufsize Number of bytes in *buffer + * + * @retval 0 if successful + * @retval -ENOSYS if function is not implemented + * @retval errno code on failure + */ +__syscall int crc_update(const struct device *dev, struct crc_ctx *ctx, const void *buffer, + size_t bufsize); + +static inline int z_impl_crc_update(const struct device *dev, struct crc_ctx *ctx, + const void *buffer, size_t bufsize) +{ + const struct crc_driver_api *api = (const struct crc_driver_api *)dev->api; + + if (api->update == NULL) { + return -ENOSYS; + } + + return api->update(dev, ctx, buffer, bufsize); +} + +/** + * @brief Finalize CRC calculation + * + * @param dev Pointer to the device structure + * @param ctx Pointer to the CRC context structure + * + * @retval 0 if successful + * @retval -ENOSYS if function is not implemented + * @retval errno code on failure + */ +__syscall int crc_finish(const struct device *dev, struct crc_ctx *ctx); + +static inline int z_impl_crc_finish(const struct device *dev, struct crc_ctx *ctx) +{ + const struct crc_driver_api *api = (const struct crc_driver_api *)dev->api; + + if (api->finish == NULL) { + return -ENOSYS; + } + + return api->finish(dev, ctx); +} + +/** + * @brief Verify CRC result + * + * @param ctx Pointer to the CRC context structure + * @param expected Expected CRC result + * + * @retval 0 if successful + * @retval -EBUSY if CRC calculation is not completed + * @retval -EPERM if CRC verification failed + */ +static inline int crc_verify(struct crc_ctx *ctx, crc_result_t expected) +{ + if (ctx == NULL) { + return -EINVAL; + } + + if (ctx->state == CRC_STATE_IN_PROGRESS) { + return -EBUSY; + } + + if (expected != ctx->result) { + return -EPERM; + } + + return 0; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#include + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CRC_H */ diff --git a/include/zephyr/drivers/dac.h b/include/zephyr/drivers/dac.h index fea4e3298fadf..d603f8701cef5 100644 --- a/include/zephyr/drivers/dac.h +++ b/include/zephyr/drivers/dac.h @@ -6,7 +6,8 @@ /** * @file - * @brief DAC public API header file. + * @ingroup dac_interface + * @brief Main header file for DAC (Digital-to-Analog Converter) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_DAC_H_ @@ -19,8 +20,8 @@ extern "C" { #endif /** - * @brief DAC driver APIs - * @defgroup dac_interface DAC driver APIs + * @brief Interfaces for Digital-to-Analog Converters. + * @defgroup dac_interface DAC * @since 2.3 * @version 0.8.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/dai.h b/include/zephyr/drivers/dai.h index b70e5bb057248..9ac60be2eb2f3 100644 --- a/include/zephyr/drivers/dai.h +++ b/include/zephyr/drivers/dai.h @@ -6,18 +6,19 @@ /** * @file - * @brief Public APIs for the DAI (Digital Audio Interface) bus drivers. + * @ingroup dai_interface + * @brief Main header file for DAI (Digital Audio Interface) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_DAI_H_ #define ZEPHYR_INCLUDE_DRIVERS_DAI_H_ /** - * @defgroup dai_interface DAI Interface + * @defgroup dai_interface DAI * @since 3.1 * @version 0.1.0 * @ingroup io_interfaces - * @brief DAI Interface + * @brief Interfaces for Digital Audio Interfaces. * * The DAI API provides support for the standard I2S (SSP) and its common variants. * It supports also DMIC, HDA and SDW backends. The API has a config function diff --git a/include/zephyr/drivers/disk.h b/include/zephyr/drivers/disk.h index c248ccd93db3c..18b1c0f3ede32 100644 --- a/include/zephyr/drivers/disk.h +++ b/include/zephyr/drivers/disk.h @@ -7,7 +7,8 @@ /** * @file - * @brief Disk Driver Interface + * @ingroup disk_driver_interface + * @brief Main header file for disk driver API. * * This file contains interface for disk access. Apart from disks, various * other storage media like Flash and RAM disks may implement this interface to @@ -19,8 +20,8 @@ #define ZEPHYR_INCLUDE_DRIVERS_DISK_H_ /** - * @brief Disk Driver Interface - * @defgroup disk_driver_interface Disk Driver Interface + * @brief Interfaces for disks. + * @defgroup disk_driver_interface Disk Access * @since 1.6 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/disks/sdmmc_stm32.h b/include/zephyr/drivers/disk/sdmmc_stm32.h similarity index 85% rename from include/zephyr/drivers/disks/sdmmc_stm32.h rename to include/zephyr/drivers/disk/sdmmc_stm32.h index 6a76a693fb03a..ed132903d605a 100644 --- a/include/zephyr/drivers/disks/sdmmc_stm32.h +++ b/include/zephyr/drivers/disk/sdmmc_stm32.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DRIVERS_DISKS_SDMMC_STM32_H_ -#define ZEPHYR_INCLUDE_DRIVERS_DISKS_SDMMC_STM32_H_ +#ifndef ZEPHYR_INCLUDE_DRIVERS_DISK_SDMMC_STM32_H_ +#define ZEPHYR_INCLUDE_DRIVERS_DISK_SDMMC_STM32_H_ #include #include @@ -28,4 +28,4 @@ */ void stm32_sdmmc_get_card_cid(const struct device *dev, uint32_t cid[4]); -#endif /* ZEPHYR_INCLUDE_DRIVERS_DISKS_SDMMC_STM32_H_ */ +#endif /* ZEPHYR_INCLUDE_DRIVERS_DISK_SDMMC_STM32_H_ */ diff --git a/include/zephyr/drivers/display.h b/include/zephyr/drivers/display.h index e00e83e0a62b3..08d55557ae975 100644 --- a/include/zephyr/drivers/display.h +++ b/include/zephyr/drivers/display.h @@ -6,15 +6,16 @@ /** * @file - * @brief Public API for display drivers and applications + * @ingroup display_interface + * @brief Main header file for display driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_DISPLAY_H_ #define ZEPHYR_INCLUDE_DRIVERS_DISPLAY_H_ /** - * @brief Display Interface - * @defgroup display_interface Display Interface + * @brief Interfaces for display controllers. + * @defgroup display_interface Display * @since 1.14 * @version 0.8.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/dma.h b/include/zephyr/drivers/dma.h index 5237f78b70d3a..8fd42dd9a1e67 100644 --- a/include/zephyr/drivers/dma.h +++ b/include/zephyr/drivers/dma.h @@ -1,15 +1,15 @@ -/** - * @file - * - * @brief Public APIs for the DMA drivers. - */ - /* * Copyright (c) 2016 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup dma_interface + * @brief Main header file for DMA (Direct Memory Access) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_H_ #define ZEPHYR_INCLUDE_DRIVERS_DMA_H_ @@ -20,10 +20,9 @@ extern "C" { #endif - /** - * @brief DMA Interface - * @defgroup dma_interface DMA Interface + * @brief Interfaces for DMA (Direct Memory Access) controllers. + * @defgroup dma_interface DMA * @since 1.5 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/dma/dma_stm32.h b/include/zephyr/drivers/dma/dma_stm32.h index 38f395b0108fc..d369ab2ae2ce5 100644 --- a/include/zephyr/drivers/dma/dma_stm32.h +++ b/include/zephyr/drivers/dma/dma_stm32.h @@ -85,4 +85,21 @@ #define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) 0 #endif +#if defined(CONFIG_SOC_SERIES_STM32H5X) || defined(CONFIG_SOC_SERIES_STM32H7RSX) || \ + defined(CONFIG_SOC_SERIES_STM32MP2X) || defined(CONFIG_SOC_SERIES_STM32N6X) || \ + defined(CONFIG_SOC_SERIES_STM32U3X) || defined(CONFIG_SOC_SERIES_STM32U5X) || \ + defined(CONFIG_SOC_SERIES_STM32WBAX) +#define STM32_DMA_GET_CHANNEL_INSTANCE LL_DMA_GET_CHANNEL_INSTANCE +#else +#define STM32_DMA_GET_CHANNEL_INSTANCE __LL_DMA_GET_CHANNEL_INSTANCE +#endif + +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1) +#define STM32_DMA_GET_INSTANCE(reg, channel) \ + __LL_DMA_GET_STREAM_INSTANCE((reg), (channel) - STM32_DMA_STREAM_OFFSET); +#else +#define STM32_DMA_GET_INSTANCE(reg, channel) \ + STM32_DMA_GET_CHANNEL_INSTANCE((reg), (channel) - STM32_DMA_STREAM_OFFSET); +#endif + #endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_ */ diff --git a/include/zephyr/drivers/edac.h b/include/zephyr/drivers/edac.h index e54cfc601a480..8c47c713af7c0 100644 --- a/include/zephyr/drivers/edac.h +++ b/include/zephyr/drivers/edac.h @@ -6,7 +6,8 @@ /** * @file - * @brief EDAC API header file + * @ingroup edac_interface + * @brief Main header file for EDAC (Error Detection and Correction) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_EDAC_H_ @@ -17,7 +18,8 @@ #include /** - * @defgroup edac EDAC API + * @brief Interfaces for Error Detection and Correction (EDAC) controllers. + * @defgroup edac_interface EDAC * @since 2.5 * @version 0.8.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/eeprom.h b/include/zephyr/drivers/eeprom.h index ff5b21cbd5c7f..753318928ad2e 100644 --- a/include/zephyr/drivers/eeprom.h +++ b/include/zephyr/drivers/eeprom.h @@ -10,15 +10,16 @@ /** * @file - * @brief Public API for EEPROM drivers + * @ingroup eeprom_interface + * @brief Main header file for EEPROM driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_EEPROM_H_ #define ZEPHYR_INCLUDE_DRIVERS_EEPROM_H_ /** - * @brief EEPROM Interface - * @defgroup eeprom_interface EEPROM Interface + * @brief Interfaces for Electrically Erasable Programmable Read-Only Memory (EEPROM). + * @defgroup eeprom_interface EEPROM * @since 2.1 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/entropy.h b/include/zephyr/drivers/entropy.h index de2d0f2c2d649..185b0d8f019f9 100644 --- a/include/zephyr/drivers/entropy.h +++ b/include/zephyr/drivers/entropy.h @@ -1,21 +1,23 @@ -/** - * @file drivers/entropy.h - * - * @brief Public APIs for the entropy driver. - */ - /* * Copyright (c) 2016 ARM Ltd. * Copyright (c) 2017 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DRIVERS_ENTROPY_H_ + +/** + * @file + * @ingroup entropy_interface + * @brief Main header file for entropy driver API. + */ + + + #ifndef ZEPHYR_INCLUDE_DRIVERS_ENTROPY_H_ #define ZEPHYR_INCLUDE_DRIVERS_ENTROPY_H_ /** - * @brief Entropy Interface - * @defgroup entropy_interface Entropy Interface + * @brief Interfaces for entropy hardware. + * @defgroup entropy_interface Entropy * @since 1.10 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/espi.h b/include/zephyr/drivers/espi.h index ba510fc18dc0e..6733166323dc0 100644 --- a/include/zephyr/drivers/espi.h +++ b/include/zephyr/drivers/espi.h @@ -6,7 +6,8 @@ /** * @file - * @brief Public APIs for eSPI driver + * @ingroup espi_interface + * @brief Main header file for eSPI (Enhanced Serial Peripheral Interface) driver API. */ #ifndef ZEPHYR_INCLUDE_ESPI_H_ @@ -24,8 +25,9 @@ extern "C" { #endif /** - * @brief eSPI Driver APIs - * @defgroup espi_interface ESPI Driver APIs + * @brief Interfaces for Enhanced Serial Peripheral Interface (eSPI) + * controllers. + * @defgroup espi_interface ESPI * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/espi_emul.h b/include/zephyr/drivers/espi_emul.h index e03b6cd5bfa98..1b572cef71120 100644 --- a/include/zephyr/drivers/espi_emul.h +++ b/include/zephyr/drivers/espi_emul.h @@ -4,6 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup espi_emul_interface + * @brief Main header file for eSPI emulation driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_ESPI_SPI_EMUL_H_ #define ZEPHYR_INCLUDE_DRIVERS_ESPI_SPI_EMUL_H_ @@ -13,12 +19,6 @@ #include #include -/** - * @file - * - * @brief Public APIs for the eSPI emulation drivers. - */ - /** * @brief eSPI Emulation Interface * @defgroup espi_emul_interface eSPI Emulation Interface diff --git a/include/zephyr/drivers/espi_saf.h b/include/zephyr/drivers/espi_saf.h index d9a25a8d654f1..bee662dd174fd 100644 --- a/include/zephyr/drivers/espi_saf.h +++ b/include/zephyr/drivers/espi_saf.h @@ -21,13 +21,13 @@ extern "C" { #endif /** - * @brief eSPI SAF Driver APIs - * @defgroup espi_interface ESPI Driver APIs - * @ingroup io_interfaces + * @brief Interfaces for eSPI SAF (Serial Attached Flash) + * controllers. + * @defgroup espi_saf_interface eSPI SAF + * @ingroup espi_interface * @{ */ - /** * @code *+----------------------------------------------------------------------+ diff --git a/include/zephyr/drivers/firmware/scmi/nxp/cpu.h b/include/zephyr/drivers/firmware/scmi/nxp/cpu.h index 2b3c9eedd07ee..7d7f742a6aaf6 100644 --- a/include/zephyr/drivers/firmware/scmi/nxp/cpu.h +++ b/include/zephyr/drivers/firmware/scmi/nxp/cpu.h @@ -23,6 +23,8 @@ #define SCMI_CPU_MAX_PDCONFIGS_T 7U +#define SCMI_CPU_IRQ_WAKE_NUM 22U + /** * @struct scmi_cpu_sleep_mode_config * @@ -52,6 +54,18 @@ struct scmi_cpu_pd_lpm_config { struct scmi_pd_lpm_settings cfgs[SCMI_CPU_MAX_PDCONFIGS_T]; }; +/** + * @struct scmi_cpu_irq_mask_config + * + * @brief Describes the parameters for the CPU_IRQ_WAKE_SET command + */ +struct scmi_cpu_irq_mask_config { + uint32_t cpu_id; + uint32_t mask_idx; + uint32_t num_mask; + uint32_t mask[SCMI_CPU_IRQ_WAKE_NUM]; +}; + /** * @brief CPU domain protocol command message IDs */ @@ -93,4 +107,14 @@ int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg); * @retval negative errno if failure */ int scmi_cpu_pd_lpm_set(struct scmi_cpu_pd_lpm_config *cfg); + +/** + * @brief Send the CPU_IRQ_WAKE_SET command and get its reply + * + * @param cfg pointer to structure containing configuration to be set + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_cpu_set_irq_mask(struct scmi_cpu_irq_mask_config *cfg); #endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_ */ diff --git a/include/zephyr/drivers/flash.h b/include/zephyr/drivers/flash.h index 36fadfe76838e..d8f39c4278be8 100644 --- a/include/zephyr/drivers/flash.h +++ b/include/zephyr/drivers/flash.h @@ -7,16 +7,17 @@ /** * @file - * @brief Public API for FLASH drivers + * @ingroup flash_interface + * @brief Main header file for Flash driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_FLASH_H_ #define ZEPHYR_INCLUDE_DRIVERS_FLASH_H_ /** - * @brief FLASH internal Interface - * @defgroup flash_internal_interface FLASH internal Interface - * @ingroup io_interfaces + * @brief Internal interfaces for flash memory controllers. + * @defgroup flash_internal_interface Flash Internal + * @ingroup flash_interface * @{ */ @@ -43,8 +44,8 @@ struct flash_pages_layout { */ /** - * @brief FLASH Interface - * @defgroup flash_interface FLASH Interface + * @brief Interfaces for flash memory controllers. + * @defgroup flash_interface Flash * @since 1.2 * @version 1.0.0 * @ingroup io_interfaces @@ -94,8 +95,8 @@ struct flash_parameters { #define FLASH_ERASE_C_VAL_BIT 0x04 #define FLASH_ERASE_UNIFORM_PAGE 0x08 - -/* @brief Parser for flash_parameters for retrieving erase capabilities +/** + * @brief Parser for flash_parameters for retrieving erase capabilities * * The functions parses flash_parameters type object and returns combination * of erase capabilities of 0 if device does not have any. diff --git a/include/zephyr/drivers/flash/ra_flash_api_extensions.h b/include/zephyr/drivers/flash/ra_flash_api_extensions.h index b8cc340caf8b7..a9f9bdbfebbe2 100644 --- a/include/zephyr/drivers/flash/ra_flash_api_extensions.h +++ b/include/zephyr/drivers/flash/ra_flash_api_extensions.h @@ -38,6 +38,10 @@ enum ra_ex_ops { * current write protection settings. Can be @a NULL if the statis is not needed. */ FLASH_RA_EX_OP_WRITE_PROTECT = FLASH_EX_OP_VENDOR_BASE, + /** + * Reset Flash device (at QPI(4-4-4) mode). + */ + QSPI_FLASH_EX_OP_EXIT_QPI, }; /** diff --git a/include/zephyr/drivers/fpga.h b/include/zephyr/drivers/fpga.h index 61e9c1cf0dda4..b3c15e5339f07 100644 --- a/include/zephyr/drivers/fpga.h +++ b/include/zephyr/drivers/fpga.h @@ -4,6 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup fpga_interface + * @brief Main header file for FPGA driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_FPGA_H_ #define ZEPHYR_INCLUDE_DRIVERS_FPGA_H_ @@ -17,6 +23,15 @@ extern "C" { #endif +/** + * @brief Interfaces for Field-Programmable Gate Arrays (FPGA). + * @defgroup fpga_interface FPGA + * @since 2.7 + * @version 0.1.0 + * @ingroup io_interfaces + * @{ + */ + enum FPGA_status { /* Inactive is when the FPGA cannot accept the bitstream * and will not be programmed correctly @@ -172,6 +187,8 @@ static inline int fpga_off(const struct device *dev) return api->off(dev); } +/** @} */ + #ifdef __cplusplus } #endif diff --git a/include/zephyr/drivers/fuel_gauge.h b/include/zephyr/drivers/fuel_gauge.h index 3a9061aca0d44..9dee971c4df06 100644 --- a/include/zephyr/drivers/fuel_gauge.h +++ b/include/zephyr/drivers/fuel_gauge.h @@ -6,12 +6,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup fuel_gauge_interface + * @brief Main header file for fuel gauge driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_BATTERY_H_ #define ZEPHYR_INCLUDE_DRIVERS_BATTERY_H_ /** - * @brief Fuel Gauge Interface - * @defgroup fuel_gauge_interface Fuel Gauge Interface + * @brief Interfaces for fuel gauges. + * @defgroup fuel_gauge_interface Fuel Gauge * @since 3.3 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/gnss.h b/include/zephyr/drivers/gnss.h index bb6fc835e2834..d27a639848226 100644 --- a/include/zephyr/drivers/gnss.h +++ b/include/zephyr/drivers/gnss.h @@ -5,16 +5,17 @@ */ /** - * @file gnss.h - * @brief Public GNSS API. + * @file + * @ingroup gnss_interface + * @brief Main header file for GNSS driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_GNSS_H_ #define ZEPHYR_INCLUDE_DRIVERS_GNSS_H_ /** - * @brief GNSS Interface - * @defgroup gnss_interface GNSS Interface + * @brief Interfaces for Global Navigation Satellite System (GNSS) receivers. + * @defgroup gnss_interface GNSS * @since 3.6 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/gpio.h b/include/zephyr/drivers/gpio.h index 78747f80e9c29..33962528136f0 100644 --- a/include/zephyr/drivers/gpio.h +++ b/include/zephyr/drivers/gpio.h @@ -9,8 +9,8 @@ /** * @file - * @brief Public APIs for GPIO drivers * @ingroup gpio_interface + * @brief Main header file for GPIO driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_H_ @@ -32,8 +32,9 @@ extern "C" { #endif /** - * @brief GPIO Driver APIs - * @defgroup gpio_interface GPIO Driver APIs + * @brief Interfaces for General Purpose Input/Output (GPIO) + * controllers. + * @defgroup gpio_interface GPIO * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces @@ -794,6 +795,16 @@ enum gpio_int_trig { GPIO_INT_TRIG_BOTH = GPIO_INT_LOW_0 | GPIO_INT_HIGH_1, /* Trigger a system wakeup. */ GPIO_INT_TRIG_WAKE = GPIO_INT_WAKEUP, + /* Trigger a system wakeup when input state is (or transitions to) + * physical low. (Edge Falling or Active Low) + */ + GPIO_INT_TRIG_WAKE_LOW = GPIO_INT_LOW_0 | GPIO_INT_WAKEUP, + /* Trigger a system wakeup when input state is (or transitions to) + * physical high. (Edge Rising or Active High) + */ + GPIO_INT_TRIG_WAKE_HIGH = GPIO_INT_HIGH_1 | GPIO_INT_WAKEUP, + /* Trigger a system wakeup on pin rising or falling edge. */ + GPIO_INT_TRIG_WAKE_BOTH = GPIO_INT_LOW_0 | GPIO_INT_HIGH_1 | GPIO_INT_WAKEUP, }; __subsystem struct gpio_driver_api { @@ -948,9 +959,11 @@ static inline int z_impl_gpio_pin_interrupt_configure(const struct device *port, * * This is equivalent to: * - * gpio_pin_interrupt_configure(spec->port, spec->pin, flags); + * gpio_pin_interrupt_configure(spec->port, spec->pin, combined_flags); * - * The spec->dt_flags value is not used. + * Where combined_flags is the combination of the flags argument + * and the GPIO_INT_WAKEUP flag from spec->dt_flags if set. Other + * flags from spec->dt_flags are ignored. * * @param spec GPIO specification from devicetree * @param flags interrupt configuration flags @@ -959,7 +972,8 @@ static inline int z_impl_gpio_pin_interrupt_configure(const struct device *port, static inline int gpio_pin_interrupt_configure_dt(const struct gpio_dt_spec *spec, gpio_flags_t flags) { - return gpio_pin_interrupt_configure(spec->port, spec->pin, flags); + return gpio_pin_interrupt_configure(spec->port, spec->pin, + flags | (spec->dt_flags & GPIO_INT_WAKEUP)); } /** diff --git a/include/zephyr/drivers/haptics.h b/include/zephyr/drivers/haptics.h index 9949672c2f294..b00d821ccba3e 100644 --- a/include/zephyr/drivers/haptics.h +++ b/include/zephyr/drivers/haptics.h @@ -4,12 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup haptics_interface + * @brief Main header file for haptics driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_HAPTICS_H_ #define ZEPHYR_INCLUDE_DRIVERS_HAPTICS_H_ /** - * @brief Haptics Interface - * @defgroup haptics_interface Haptics Interface + * @brief Interfaces for haptic devices. + * @defgroup haptics_interface Haptics * @ingroup io_interfaces * @{ * diff --git a/include/zephyr/drivers/hwinfo.h b/include/zephyr/drivers/hwinfo.h index 807e091cc598d..55bd5f0a7d920 100644 --- a/include/zephyr/drivers/hwinfo.h +++ b/include/zephyr/drivers/hwinfo.h @@ -1,21 +1,21 @@ -/** - * @file - * - * @brief Public APIs to get device Information. - */ - /* * Copyright (c) 2018 Alexander Wachter * * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup hwinfo_interface + * @brief Main header file for hardware information (hwinfo) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_HWINFO_H_ #define ZEPHYR_INCLUDE_DRIVERS_HWINFO_H_ /** - * @brief Hardware Information Interface - * @defgroup hwinfo_interface Hardware Info Interface + * @brief Interfaces allowing to obtain hardware information. + * @defgroup hwinfo_interface Hardware Info * @since 1.14 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/hwspinlock.h b/include/zephyr/drivers/hwspinlock.h index c1e6c02d9f2ff..b2fe7e6591254 100644 --- a/include/zephyr/drivers/hwspinlock.h +++ b/include/zephyr/drivers/hwspinlock.h @@ -4,12 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup hwspinlock_interface + * @brief Main header file for hardware spinlock driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_HWSPINLOCK_H_ #define ZEPHYR_INCLUDE_DRIVERS_HWSPINLOCK_H_ /** - * @brief HW spinlock Interface - * @defgroup hwspinlock_interface HW spinlock Interface + * @brief Interfaces for hardware spinlocks. + * @defgroup hwspinlock_interface Hardware Spinlock * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/i2c.h b/include/zephyr/drivers/i2c.h index 1580fb8aad5be..3e3c104a291da 100644 --- a/include/zephyr/drivers/i2c.h +++ b/include/zephyr/drivers/i2c.h @@ -1,20 +1,21 @@ -/** - * @file - * - * @brief Public APIs for the I2C drivers. - */ - /* * Copyright (c) 2015 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @ingroup i2c_interface + * @brief Main header file for I2C (Inter-Integrated Circuit) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_I2C_H_ #define ZEPHYR_INCLUDE_DRIVERS_I2C_H_ /** - * @brief I2C Interface - * @defgroup i2c_interface I2C Interface + * @brief Interfaces for Inter-Integrated Circuit (I2C) controllers. + * @defgroup i2c_interface I2C * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/i2c/target/eeprom.h b/include/zephyr/drivers/i2c/target/eeprom.h index adfdcd3eaabb5..3146c8b29b942 100644 --- a/include/zephyr/drivers/i2c/target/eeprom.h +++ b/include/zephyr/drivers/i2c/target/eeprom.h @@ -13,11 +13,11 @@ #define ZEPHYR_INCLUDE_DRIVERS_I2C_TARGET_EEPROM_H_ /** - * @brief I2C EEPROM Target Driver API - * @defgroup i2c_eeprom_target_api I2C EEPROM Target Driver API + * @brief Interfaces for I2C EEPROM target devices. + * @defgroup i2c_eeprom_target_api I2C EEPROM Target * @since 1.13 * @version 1.0.0 - * @ingroup io_interfaces + * @ingroup i2c_interface * @{ */ diff --git a/include/zephyr/drivers/i2s.h b/include/zephyr/drivers/i2s.h index 0889a29148e1e..406789c365da9 100644 --- a/include/zephyr/drivers/i2s.h +++ b/include/zephyr/drivers/i2s.h @@ -6,18 +6,19 @@ /** * @file - * @brief Public APIs for the I2S (Inter-IC Sound) bus drivers. + * @ingroup i2s_interface + * @brief Main header file for I2S (Inter-IC Sound) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_I2S_H_ #define ZEPHYR_INCLUDE_DRIVERS_I2S_H_ /** - * @defgroup i2s_interface I2S Interface + * @defgroup i2s_interface I2S * @since 1.9 * @version 1.0.0 * @ingroup io_interfaces - * @brief I2S (Inter-IC Sound) Interface + * @brief Interfaces for Inter-IC Sound (I2S) controllers. * * The I2S API provides support for the standard I2S interface standard as well * as common non-standard extensions such as PCM Short/Long Frame Sync, diff --git a/include/zephyr/drivers/i3c.h b/include/zephyr/drivers/i3c.h index c124d0ccc4dea..67a00e197e74f 100644 --- a/include/zephyr/drivers/i3c.h +++ b/include/zephyr/drivers/i3c.h @@ -5,12 +5,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup i3c_interface + * @brief Main header file for I3C (Inter-Integrated Circuit) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_I3C_H_ #define ZEPHYR_INCLUDE_DRIVERS_I3C_H_ /** - * @brief I3C Interface - * @defgroup i3c_interface I3C Interface + * @brief Interfaces for Improved Inter-Integrated Circuit (I3C) controllers. + * @defgroup i3c_interface I3C * @since 3.2 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/ipm.h b/include/zephyr/drivers/ipm.h index 02c881e2c12b5..4aa698ea536ec 100644 --- a/include/zephyr/drivers/ipm.h +++ b/include/zephyr/drivers/ipm.h @@ -1,21 +1,21 @@ -/** - * @file - * - * @brief Generic low-level inter-processor mailbox communication API. - */ - /* * Copyright (c) 2015 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup ipm_interface + * @brief Main header file for IPM (Inter-Processor Mailbox) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_IPM_H_ #define ZEPHYR_INCLUDE_DRIVERS_IPM_H_ /** - * @brief IPM Interface - * @defgroup ipm_interface IPM Interface + * @brief Interfaces for Inter-Processor Mailbox (IPM) controllers. + * @defgroup ipm_interface IPM * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/led.h b/include/zephyr/drivers/led.h index 7f3a182d0a872..36928d2888c88 100644 --- a/include/zephyr/drivers/led.h +++ b/include/zephyr/drivers/led.h @@ -6,15 +6,16 @@ /** * @file - * @brief Public LED driver APIs + * @ingroup led_interface + * @brief Main header file for LED driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_LED_H_ #define ZEPHYR_INCLUDE_DRIVERS_LED_H_ /** - * @brief LED Interface - * @defgroup led_interface LED Interface + * @brief Interfaces for Light-Emitting Diode (LED) controllers. + * @defgroup led_interface LED * @since 1.12 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/led_strip.h b/include/zephyr/drivers/led_strip.h index 7c297cbc6cdc1..3932a6737b331 100644 --- a/include/zephyr/drivers/led_strip.h +++ b/include/zephyr/drivers/led_strip.h @@ -7,7 +7,8 @@ /** * @file - * @brief Public API for controlling linear strips of LEDs. + * @ingroup led_strip_interface + * @brief Main header file for LED strip driver API. * * This library abstracts the chipset drivers for individually * addressable strips of LEDs. @@ -17,8 +18,8 @@ #define ZEPHYR_INCLUDE_DRIVERS_LED_STRIP_H_ /** - * @brief LED Strip Interface - * @defgroup led_strip_interface LED Strip Interface + * @brief Interfaces for LED strips. + * @defgroup led_strip_interface LED Strip * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/lora.h b/include/zephyr/drivers/lora.h index 2ac3e8ac2f1e7..76abd2340e261 100644 --- a/include/zephyr/drivers/lora.h +++ b/include/zephyr/drivers/lora.h @@ -6,16 +6,15 @@ /** * @file - * @ingroup lora_api - * @brief Public LoRa driver APIs + * @ingroup lora_interface + * @brief Main header file for LoRa driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_LORA_H_ #define ZEPHYR_INCLUDE_DRIVERS_LORA_H_ /** - * @file - * @brief Public LoRa APIs - * @defgroup lora_api LoRa APIs + * @brief Interfaces for LoRa transceivers. + * @defgroup lora_interface LoRa * @since 2.2 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/mbox.h b/include/zephyr/drivers/mbox.h index 1945879bc83dd..4f96d5ab85815 100644 --- a/include/zephyr/drivers/mbox.h +++ b/include/zephyr/drivers/mbox.h @@ -3,6 +3,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup mbox_interface + * @brief Main header file for MBOX (Mailbox) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_MBOX_H_ #define ZEPHYR_INCLUDE_DRIVERS_MBOX_H_ @@ -18,8 +24,8 @@ extern "C" { #endif /** - * @brief MBOX Interface - * @defgroup mbox_interface MBOX Interface + * @brief Interfaces for mailbox (MBOX) devices. + * @defgroup mbox_interface MBOX * @since 1.0 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/mdio.h b/include/zephyr/drivers/mdio.h index ba1deedfb83ff..7da289d2b8851 100644 --- a/include/zephyr/drivers/mdio.h +++ b/include/zephyr/drivers/mdio.h @@ -1,21 +1,22 @@ -/** - * @file - * - * @brief Public APIs for MDIO drivers. - */ - /* * Copyright (c) 2021 IP-Logix Inc. * Copyright 2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @ingroup mdio_interface + * @brief Main header file for MDIO (Management Data Input/Output) driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_MDIO_H_ #define ZEPHYR_INCLUDE_DRIVERS_MDIO_H_ /** - * @brief MDIO Interface - * @defgroup mdio_interface MDIO Interface + * @brief Interfaces for Management Data Input/Output (MDIO) controllers. + * @defgroup mdio_interface MDIO * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/mipi_dbi.h b/include/zephyr/drivers/mipi_dbi.h index 109741e3d84b4..27a477cb8cf9f 100644 --- a/include/zephyr/drivers/mipi_dbi.h +++ b/include/zephyr/drivers/mipi_dbi.h @@ -6,12 +6,13 @@ /** * @file - * @brief Public APIs for MIPI-DBI drivers + * @ingroup mipi_dbi_interface + * @brief Main header file for MIPI-DBI (Display Bus Interface) driver API. * * MIPI-DBI defines the following 3 interfaces: - * Type A: Motorola 6800 type parallel bus - * Type B: Intel 8080 type parallel bus - * Type C: SPI Type (1 bit bus) with 3 options: + * - Type A: Motorola 6800 type parallel bus + * - Type B: Intel 8080 type parallel bus + * - Type C: SPI Type (1 bit bus) with 3 options: * 1. 9 write clocks per byte, final bit is command/data selection bit * 2. Same as above, but 16 write clocks per byte * 3. 8 write clocks per byte. Command/data selected via GPIO pin @@ -22,11 +23,11 @@ #define ZEPHYR_INCLUDE_DRIVERS_MIPI_DBI_H_ /** - * @brief MIPI-DBI driver APIs - * @defgroup mipi_dbi_interface MIPI-DBI driver APIs + * @brief Interfaces for MIPI-DBI (Display Bus Interface). + * @defgroup mipi_dbi_interface MIPI-DBI * @since 3.6 - * @version 0.1.0 - * @ingroup io_interfaces + * @version 0.8.0 + * @ingroup display_interface * @{ */ diff --git a/include/zephyr/drivers/mipi_dsi.h b/include/zephyr/drivers/mipi_dsi.h index 0b942621247f3..3e26436317a37 100644 --- a/include/zephyr/drivers/mipi_dsi.h +++ b/include/zephyr/drivers/mipi_dsi.h @@ -6,18 +6,19 @@ /** * @file - * @brief Public APIs for MIPI-DSI drivers + * @ingroup mipi_dsi_interface + * @brief Main header file for MIPI-DSI (Display Serial Interface) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_MIPI_DSI_H_ #define ZEPHYR_INCLUDE_DRIVERS_MIPI_DSI_H_ /** - * @brief MIPI-DSI driver APIs - * @defgroup mipi_dsi_interface MIPI-DSI driver APIs + * @brief Interfaces for MIPI-DSI (Display Serial Interface). + * @defgroup mipi_dsi_interface MIPI-DSI * @since 3.1 - * @version 0.1.0 - * @ingroup io_interfaces + * @version 0.8.0 + * @ingroup display_interface * @{ */ #include diff --git a/include/zephyr/drivers/misc/coresight/stmesp.h b/include/zephyr/drivers/misc/coresight/stmesp.h index d14e6e42c6956..ce0f64b52dded 100644 --- a/include/zephyr/drivers/misc/coresight/stmesp.h +++ b/include/zephyr/drivers/misc/coresight/stmesp.h @@ -10,8 +10,8 @@ #include /** - * @brief Coresight STMESP (STM Extended Stimulus Port) Interface - * @defgroup stmsp_interface Coresight STMESP interface + * @brief Interfaces for Coresight STMESP (STM Extended Stimulus Port) + * @defgroup stmsp_interface Coresight STMESP * @ingroup misc_interfaces * @{ */ diff --git a/include/zephyr/drivers/misc/devmux/devmux.h b/include/zephyr/drivers/misc/devmux/devmux.h index 4c084199d5ab6..58c457205bcdf 100644 --- a/include/zephyr/drivers/misc/devmux/devmux.h +++ b/include/zephyr/drivers/misc/devmux/devmux.h @@ -7,6 +7,7 @@ /** * @file * @brief Public APIs for the Device Multiplexer driver + * @ingroup demux_interface */ #ifndef INCLUDE_ZEPHYR_DRIVERS_MISC_DEVMUX_H_ @@ -22,8 +23,8 @@ extern "C" { #endif /** - * @brief Devmux Driver APIs - * @defgroup demux_interface Devmux Driver APIs + * @brief Interfaces for device multiplexers. + * @defgroup demux_interface Devmux * @ingroup misc_interfaces * * @details diff --git a/include/zephyr/drivers/misc/ft8xx/ft8xx.h b/include/zephyr/drivers/misc/ft8xx/ft8xx.h index 7147bd574ccbe..6441a1054fea8 100644 --- a/include/zephyr/drivers/misc/ft8xx/ft8xx.h +++ b/include/zephyr/drivers/misc/ft8xx/ft8xx.h @@ -7,6 +7,7 @@ /** * @file * @brief FT8XX public API + * @ingroup ft8xx_interface */ #ifndef ZEPHYR_DRIVERS_MISC_FT8XX_FT8XX_H_ @@ -20,8 +21,8 @@ extern "C" { #endif /** - * @brief FT8xx driver public APIs - * @defgroup ft8xx_interface FT8xx driver APIs + * @brief Interfaces for FTDI FT8xx graphic controller. + * @defgroup ft8xx_interface FTDI FT8xx * @ingroup misc_interfaces * @{ */ diff --git a/include/zephyr/drivers/misc/grove_lcd/grove_lcd.h b/include/zephyr/drivers/misc/grove_lcd/grove_lcd.h index 33eeb77801e35..4d36bb0040256 100644 --- a/include/zephyr/drivers/misc/grove_lcd/grove_lcd.h +++ b/include/zephyr/drivers/misc/grove_lcd/grove_lcd.h @@ -16,8 +16,8 @@ extern "C" { #endif /** - * @brief Grove display APIs - * @defgroup grove_display Grove display APIs + * @brief Interfaces for Grove LCD RGB display. + * @defgroup grove_display Grove display * @ingroup third_party * @{ */ diff --git a/include/zephyr/drivers/misc/interconn/renesas_elc/renesas_elc.h b/include/zephyr/drivers/misc/interconn/renesas_elc/renesas_elc.h index 1e8bc93fcb3cb..15f5869d23274 100644 --- a/include/zephyr/drivers/misc/interconn/renesas_elc/renesas_elc.h +++ b/include/zephyr/drivers/misc/interconn/renesas_elc/renesas_elc.h @@ -7,14 +7,15 @@ /** * @file * @brief Public APIs for the Renesas ELC driver + * @ingroup renesas_elc_interface */ #ifndef ZEPHYR_INCLUDE_DRIVERS_MISC_RENESAS_ELC_H_ #define ZEPHYR_INCLUDE_DRIVERS_MISC_RENESAS_ELC_H_ /** - * @brief Renesas ELC driver public APIs - * @defgroup renesas_elc_interface Renesas ELC driver APIs + * @brief Interfaces for Renesas Event Link Controller (ELC). + * @defgroup renesas_elc_interface Renesas ELC * @ingroup misc_interfaces * @{ */ diff --git a/include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h b/include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h index 573fe2852c98e..e967714d0dcf0 100644 --- a/include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h +++ b/include/zephyr/drivers/misc/nxp_flexio/nxp_flexio.h @@ -14,8 +14,8 @@ #define ZEPHYR_DRIVERS_MISC_NXP_FLEXIO_NXP_FLEXIO_H_ /** - * @brief NXP FlexIO driver APIs - * @defgroup nxp_flexio_interface NXP FlexIO driver APIs + * @brief Interfaces for NXP FlexIO. + * @defgroup nxp_flexio_interface NXP FlexIO * @ingroup misc_interfaces * * @{ diff --git a/include/zephyr/drivers/misc/pio_rpi_pico/pio_rpi_pico.h b/include/zephyr/drivers/misc/pio_rpi_pico/pio_rpi_pico.h index f6dc273b33ac9..3339391c0ae58 100644 --- a/include/zephyr/drivers/misc/pio_rpi_pico/pio_rpi_pico.h +++ b/include/zephyr/drivers/misc/pio_rpi_pico/pio_rpi_pico.h @@ -16,8 +16,8 @@ #define ZEPHYR_DRIVERS_MISC_PIO_PICO_RPI_PIO_PICO_RPI_H_ /** - * @brief Raspberry Pi Pico PIO driver APIs - * @defgroup pio_rpi_pico_interface Raspberry Pi Pico PIO Driver APIs + * @brief Interfaces for Raspberry Pi Pico Programmable I/O (PIO). + * @defgroup pio_rpi_pico_interface Raspberry Pi Pico PIO * @ingroup misc_interfaces * * @{ @@ -148,7 +148,10 @@ * @param dev Pointer to device structure for rpi_pio device instance * @return PIO object */ -PIO pio_rpi_pico_get_pio(const struct device *dev); +inline PIO pio_rpi_pico_get_pio(const struct device *dev) +{ + return *(PIO *)(dev->config); +} /** * Allocate a state machine. diff --git a/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h b/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h index 095844bed41a8..20ebf0ad4a312 100644 --- a/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h +++ b/include/zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h @@ -7,13 +7,14 @@ /** * @file * @brief Public APIs for Time-aware GPIO drivers + * @ingroup tgpio_interface */ #ifndef ZEPHYR_DRIVERS_MISC_TIMEAWARE_GPIO_TIMEAWARE_GPIO #define ZEPHYR_DRIVERS_MISC_TIMEAWARE_GPIO_TIMEAWARE_GPIO /** - * @brief Time-aware GPIO Interface - * @defgroup tgpio_interface Time-aware GPIO Interface + * @brief Interfaces for time-aware GPIO controllers. + * @defgroup tgpio_interface Time-aware GPIO * @since 3.5 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/mspi.h b/include/zephyr/drivers/mspi.h index 4f054dda81e23..c486f48a8ddfc 100644 --- a/include/zephyr/drivers/mspi.h +++ b/include/zephyr/drivers/mspi.h @@ -6,9 +6,8 @@ /** * @file - * @brief Public APIs for MSPI driver - * @since 3.7 - * @version 0.1.0 + * @ingroup mspi_interface + * @brief Main header file for MSPI (Multi-Master Serial Peripheral Interface) driver API. */ #ifndef ZEPHYR_INCLUDE_MSPI_H_ @@ -27,8 +26,11 @@ extern "C" { #endif /** - * @brief MSPI Driver APIs - * @defgroup mspi_interface MSPI Driver APIs + * @brief Interfaces for Multi-bit Serial Peripheral Interface (MSPI) + * controllers. + * @defgroup mspi_interface MSPI + * @since 3.7 + * @version 0.1.0 * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/mspi/devicetree.h b/include/zephyr/drivers/mspi/devicetree.h index a3e5b65319e0c..fa60f3243113e 100644 --- a/include/zephyr/drivers/mspi/devicetree.h +++ b/include/zephyr/drivers/mspi/devicetree.h @@ -10,7 +10,7 @@ /** * @brief MSPI Devicetree related macros * @defgroup mspi_devicetree MSPI Devicetree related macros - * @ingroup io_interfaces + * @ingroup mspi_interface * @{ */ diff --git a/include/zephyr/drivers/pcie/controller.h b/include/zephyr/drivers/pcie/controller.h index 11a0fa068b82e..d38bc8afed5ff 100644 --- a/include/zephyr/drivers/pcie/controller.h +++ b/include/zephyr/drivers/pcie/controller.h @@ -21,9 +21,9 @@ #endif /** - * @brief PCI Express Controller Interface - * @defgroup pcie_controller_interface PCI Express Controller Interface - * @ingroup io_interfaces + * @brief Interfaces for PCIe Controllers. + * @defgroup pcie_controller_interface PCIe Controller + * @ingroup pcie_interface * @{ */ diff --git a/include/zephyr/drivers/pcie/pcie.h b/include/zephyr/drivers/pcie/pcie.h index a6a494902994d..c79694f780ae6 100644 --- a/include/zephyr/drivers/pcie/pcie.h +++ b/include/zephyr/drivers/pcie/pcie.h @@ -8,10 +8,16 @@ #define ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_ /** - * @brief PCIe Host Interface - * @defgroup pcie_host_interface PCIe Host Interface + * @brief Interfaces for PCIe devices. + * @defgroup pcie_interface PCIe * @ingroup io_interfaces * @{ + * @} + * + * @brief Interfaces for PCIe Host. + * @defgroup pcie_host_interface PCIe Host + * @ingroup pcie_interface + * @{ */ #include @@ -191,7 +197,7 @@ extern void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data); typedef bool (*pcie_scan_cb_t)(pcie_bdf_t bdf, pcie_id_t id, void *cb_data); enum { - /** Scan all available PCI host controllers and sub-busses */ + /** Scan all available PCI host controllers and sub-buses */ PCIE_SCAN_RECURSIVE = BIT(0), /** Do the callback for all endpoint types, including bridges */ PCIE_SCAN_CB_ALL = BIT(1), diff --git a/include/zephyr/drivers/peci.h b/include/zephyr/drivers/peci.h index ebc110706c53a..c7a9a28f8ec68 100644 --- a/include/zephyr/drivers/peci.h +++ b/include/zephyr/drivers/peci.h @@ -6,15 +6,17 @@ /** * @file - * @brief Public Platform Environment Control Interface driver APIs + * @ingroup peci_interface + * @brief Main header file for PECI (Platform Environment Control Interface) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_PECI_H_ #define ZEPHYR_INCLUDE_DRIVERS_PECI_H_ /** - * @brief PECI Interface 3.0 - * @defgroup peci_interface PECI Interface + * @brief Interfaces for Platform Environment Control Interface (PECI) + * devices. + * @defgroup peci_interface PECI * @since 2.1 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/pinctrl.h b/include/zephyr/drivers/pinctrl.h index de36288f451c4..f3d85649680fb 100644 --- a/include/zephyr/drivers/pinctrl.h +++ b/include/zephyr/drivers/pinctrl.h @@ -5,15 +5,16 @@ /** * @file - * Public APIs for pin control drivers + * @brief Main header file for pin control driver API. + * @ingroup pinctrl_interface */ #ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_H_ #define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_H_ /** - * @brief Pin Controller Interface - * @defgroup pinctrl_interface Pin Controller Interface + * @brief Interfaces for pin controllers. + * @defgroup pinctrl_interface Pin Control * @since 3.0 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/ps2.h b/include/zephyr/drivers/ps2.h index 6060ba60478f4..cd71aa3e49fc1 100644 --- a/include/zephyr/drivers/ps2.h +++ b/include/zephyr/drivers/ps2.h @@ -6,9 +6,8 @@ /** * @file - * @brief Public API for PS/2 devices such as keyboard and mouse. - * Callers of this API are responsible for setting the typematic rate - * and decode keys using their desired scan code tables. + * @ingroup ps2_interface + * @brief Main header file for PS/2 (Personal System/2) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_PS2_H_ @@ -24,9 +23,13 @@ extern "C" { #endif /** - * @brief PS/2 Driver APIs - * @defgroup ps2_interface PS/2 Driver APIs + * @brief Interfaces for PS/2 devices. + * @defgroup ps2_interface PS/2 * @ingroup io_interfaces + * + * Callers of this API are responsible for setting the typematic rate + * and decode keys using their desired scan code tables. + * * @{ */ diff --git a/include/zephyr/drivers/psi5/psi5.h b/include/zephyr/drivers/psi5/psi5.h index a5961469aefd9..0bb81c2bd82f1 100644 --- a/include/zephyr/drivers/psi5/psi5.h +++ b/include/zephyr/drivers/psi5/psi5.h @@ -20,8 +20,8 @@ extern "C" { #endif /** - * @brief PSI5 Interface - * @defgroup psi5_interface PSI5 Interface + * @brief Interfaces for Peripheral Sensor Interface (PSI5). + * @defgroup psi5_interface PSI5 * @since 4.2 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/ptp_clock.h b/include/zephyr/drivers/ptp_clock.h index 21692cfa32f3c..94f28fbd80843 100644 --- a/include/zephyr/drivers/ptp_clock.h +++ b/include/zephyr/drivers/ptp_clock.h @@ -4,9 +4,22 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup ptp_clock_interface + * @brief Main header file for PTP (Precision Time Protocol) clock driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_PTP_CLOCK_H_ #define ZEPHYR_INCLUDE_DRIVERS_PTP_CLOCK_H_ +/** + * @brief Interfaces for Precision Time Protocol (PTP) clocks. + * @defgroup ptp_clock_interface PTP Clock + * @ingroup io_interfaces + * @{ + */ + #include #include #include @@ -103,4 +116,8 @@ static inline int ptp_clock_rate_adjust(const struct device *dev, double rate) #include +/** + * @} + */ + #endif /* ZEPHYR_INCLUDE_DRIVERS_PTP_CLOCK_H_ */ diff --git a/include/zephyr/drivers/pwm.h b/include/zephyr/drivers/pwm.h index 73a17aeb23b4d..a56ed4dc6e7c5 100644 --- a/include/zephyr/drivers/pwm.h +++ b/include/zephyr/drivers/pwm.h @@ -7,15 +7,16 @@ /** * @file - * @brief Public PWM Driver APIs + * @ingroup pwm_interface + * @brief Main header file for PWM (Pulse Width Modulation) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_PWM_H_ #define ZEPHYR_INCLUDE_DRIVERS_PWM_H_ /** - * @brief PWM Interface - * @defgroup pwm_interface PWM Interface + * @brief Interfaces for Pulse Width Modulation (PWM) controllers. + * @defgroup pwm_interface PWM * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/regulator.h b/include/zephyr/drivers/regulator.h index 1d8e2255a3c25..9146c69e4cc22 100644 --- a/include/zephyr/drivers/regulator.h +++ b/include/zephyr/drivers/regulator.h @@ -7,12 +7,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup regulator_interface + * @brief Main header file for regulator driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_REGULATOR_H_ #define ZEPHYR_INCLUDE_DRIVERS_REGULATOR_H_ /** - * @brief Regulator Interface - * @defgroup regulator_interface Regulator Interface + * @brief Interfaces for regulators. + * @defgroup regulator_interface Regulator * @since 2.4 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/reset.h b/include/zephyr/drivers/reset.h index 0bf2031b9ccf9..2165cfd90d87c 100644 --- a/include/zephyr/drivers/reset.h +++ b/include/zephyr/drivers/reset.h @@ -6,15 +6,16 @@ /** * @file - * @brief Public Reset Controller driver APIs + * @ingroup reset_controller_interface + * @brief Main header file for reset controller driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_RESET_H_ #define ZEPHYR_INCLUDE_DRIVERS_RESET_H_ /** - * @brief Reset Controller Interface - * @defgroup reset_controller_interface Reset Controller Interface + * @brief Interfaces for reset controllers. + * @defgroup reset_controller_interface Reset Controller * @since 3.1 * @version 0.2.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/retained_mem.h b/include/zephyr/drivers/retained_mem.h index a7efafbc7d413..d265341e9fe48 100644 --- a/include/zephyr/drivers/retained_mem.h +++ b/include/zephyr/drivers/retained_mem.h @@ -6,7 +6,8 @@ /** * @file - * @brief Public API for retained memory drivers + * @ingroup retained_mem_interface + * @brief Main header file for retained memory driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_RETAINED_MEM_ @@ -28,8 +29,8 @@ BUILD_ASSERT(!(sizeof(off_t) > sizeof(size_t)), "Size of off_t must be equal or less than size of size_t"); /** - * @brief Retained memory driver interface - * @defgroup retained_mem_interface Retained memory driver interface + * @brief Interfaces for retained memory. + * @defgroup retained_mem_interface Retained memory * @since 3.4 * @version 0.8.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/rtc.h b/include/zephyr/drivers/rtc.h index ac6ba54aa7787..9abd929a44d48 100644 --- a/include/zephyr/drivers/rtc.h +++ b/include/zephyr/drivers/rtc.h @@ -7,15 +7,16 @@ /** * @file drivers/rtc.h - * @brief Public real time clock driver API + * @ingroup rtc_interface + * @brief Main header file for real-time clock (RTC) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_RTC_H_ #define ZEPHYR_INCLUDE_DRIVERS_RTC_H_ /** - * @brief RTC Interface - * @defgroup rtc_interface RTC Interface + * @brief Interfaces for real-time clocks (RTC). + * @defgroup rtc_interface RTC * @since 3.4 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/rtc/maxim_ds3231.h b/include/zephyr/drivers/rtc/maxim_ds3231.h index 1dd6be932b01a..a4b174ae9f7f0 100644 --- a/include/zephyr/drivers/rtc/maxim_ds3231.h +++ b/include/zephyr/drivers/rtc/maxim_ds3231.h @@ -207,9 +207,10 @@ extern "C" { #define MAXIM_DS3231_ALARM_FLAGS_AUTODISABLE BIT(7) /** - * @brief RTC DS3231 Driver-Specific API - * @defgroup rtc_ds3231_interface RTC DS3231 Interface - * @ingroup io_interfaces + * @brief Interface for Maxim DS3231 RTC (using counter API). + * @defgroup rtc_ds3231_interface RTC DS3231 (legacy). + * @ingroup misc_interfaces + * @deprecated Use MFD driver instead. See `maxim,ds3231-rtc` compatible. * @{ */ diff --git a/include/zephyr/drivers/sdhc.h b/include/zephyr/drivers/sdhc.h index 98f651cfeec0e..3a4409fa002a2 100644 --- a/include/zephyr/drivers/sdhc.h +++ b/include/zephyr/drivers/sdhc.h @@ -6,7 +6,8 @@ /** * @file - * @brief SD Host Controller public API header file. + * @ingroup sdhc_interface + * @brief Main header file for SDHC (Secure Digital Host Controller) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_SDHC_H_ @@ -17,8 +18,8 @@ #include /** - * @brief SDHC interface - * @defgroup sdhc_interface SDHC interface + * @brief Interfaces for Secure Digital Host Controllers (SDHC). + * @defgroup sdhc_interface SDHC * @since 3.1 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/sensor.h b/include/zephyr/drivers/sensor.h index 0ffead4c25c06..db09942626e3d 100644 --- a/include/zephyr/drivers/sensor.h +++ b/include/zephyr/drivers/sensor.h @@ -1,20 +1,20 @@ -/** - * @file drivers/sensor.h - * - * @brief Public APIs for the sensor driver. - */ - /* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ +* Copyright (c) 2016 Intel Corporation +* +* SPDX-License-Identifier: Apache-2.0 +*/ #ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_H_ #define ZEPHYR_INCLUDE_DRIVERS_SENSOR_H_ /** - * @brief Sensor Interface - * @defgroup sensor_interface Sensor Interface + * @file + * @ingroup sensor_interface + * @brief Main header file for sensor driver API. + */ + +/** + * @brief Interfaces for sensors. + * @defgroup sensor_interface Sensor * @since 1.2 * @version 1.0.0 * @ingroup io_interfaces @@ -927,22 +927,23 @@ static inline int z_impl_sensor_channel_get(const struct device *dev, * Generic data structure used for encoding the sample timestamp and number of channels sampled. */ struct __attribute__((__packed__)) sensor_data_generic_header { - /* The timestamp at which the data was collected from the sensor */ + /** The timestamp at which the data was collected from the sensor */ uint64_t timestamp_ns; /* - * The number of channels present in the frame. This will be the true number of elements in - * channel_info and in the q31 values that follow the header. + ** The number of channels present in the frame. + * This will be the true number of elements in channel_info and in the q31 values that + * follow the header. */ uint32_t num_channels; - /* Shift value for all samples in the frame */ + /** Shift value for all samples in the frame */ int8_t shift; /* This padding is needed to make sure that the 'channels' field is aligned */ int8_t _padding[sizeof(struct sensor_chan_spec) - 1]; - /* Channels present in the frame */ + /** Channels present in the frame */ struct sensor_chan_spec channels[0]; }; diff --git a/include/zephyr/drivers/sensor/afbr_s50.h b/include/zephyr/drivers/sensor/afbr_s50.h index 39a8a428df059..5682bf08486cc 100644 --- a/include/zephyr/drivers/sensor/afbr_s50.h +++ b/include/zephyr/drivers/sensor/afbr_s50.h @@ -30,6 +30,9 @@ extern "C" { /** Disregard pixel reading if contains this value */ #define AFBR_PIXEL_INVALID_VALUE 0x80000000 +/** + * Custom sensor channels for AFBR-S50 + */ enum sensor_channel_afbr_s50 { /** * Obtain matrix of pixels, with readings in meters. diff --git a/include/zephyr/drivers/sensor/fdc2x1x.h b/include/zephyr/drivers/sensor/fdc2x1x.h index 0dc33b118dea0..ebb37e1c3f68b 100644 --- a/include/zephyr/drivers/sensor/fdc2x1x.h +++ b/include/zephyr/drivers/sensor/fdc2x1x.h @@ -6,26 +6,37 @@ /** * @file - * @brief Extended public API for the Texas Instruments FDC2X1X + * @brief Header file for extended sensor API of FDC2X1X sensor + * @ingroup fdc2x1x_interface */ #ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_FDC2X1X_H_ #define ZEPHYR_INCLUDE_DRIVERS_SENSOR_FDC2X1X_H_ +/** + * @brief Texas Instruments FDC2X1X capacitive sensor + * @defgroup fdc2x1x_interface FDC2X1X + * @ingroup sensor_interface_ext + * @{ + */ + #ifdef __cplusplus extern "C" { #endif #include +/** + * Custom sensor channels for FDC2X1X + */ enum sensor_channel_fdc2x1x { - /** CH0 Capacitance, in Picofarad **/ + /** CH0 Capacitance, in picofarad **/ SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH0 = SENSOR_CHAN_PRIV_START, - /** CH1 Capacitance, in Picofarad **/ + /** CH1 Capacitance, in picofarad **/ SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH1, - /** CH2 Capacitance, in Picofarad **/ + /** CH2 Capacitance, in picofarad **/ SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH2, - /** CH3 Capacitance, in Picofarad **/ + /** CH3 Capacitance, in picofarad **/ SENSOR_CHAN_FDC2X1X_CAPACITANCE_CH3, /** CH0 Frequency, in MHz **/ @@ -42,4 +53,8 @@ enum sensor_channel_fdc2x1x { } #endif +/** + * @} + */ + #endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_FDC2X1X_ */ diff --git a/include/zephyr/drivers/sensor/pat9136.h b/include/zephyr/drivers/sensor/pat9136.h index a88de369d76de..41b1cd37157ca 100644 --- a/include/zephyr/drivers/sensor/pat9136.h +++ b/include/zephyr/drivers/sensor/pat9136.h @@ -5,16 +5,32 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @brief Header file for extended sensor API of PAT9136 sensor + * @ingroup pat9136_interface + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAT9136_H_ #define ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAT9136_H_ +/** + * @brief Pixart PAT9136 optical flow sensor + * @defgroup pat9136_interface PAT9136 + * @ingroup sensor_interface_ext + * @{ + */ + #include #ifdef __cplusplus extern "C" { #endif -/** This sensor does have the ability to provide DXY in meaningful units, and +/** + * Custom sensor channels for PAT9136 + * + * This sensor does have the ability to provide DXY in meaningful units, and * since the standard channels' unit is in points (SENSOR_CHAN_POS_DX, * SENSOR_CHAN_POS_DY, SENSOR_CHAN_POS_DXYZ), we've captured the following * channels to provide an alternative for this sensor. @@ -35,4 +51,8 @@ enum sensor_channel_pat9136 { } #endif +/** + * @} + */ + #endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAT9136_H_ */ diff --git a/include/zephyr/drivers/sent/sent.h b/include/zephyr/drivers/sent/sent.h index c3d29c69da452..c7e0d1bd8108b 100644 --- a/include/zephyr/drivers/sent/sent.h +++ b/include/zephyr/drivers/sent/sent.h @@ -7,6 +7,7 @@ /** * @file * @brief Single Edge Nibble Transmission (SENT) driver API. + * @ingroup sent_interface */ #ifndef ZEPHYR_INCLUDE_DRIVERS_SENT_H_ @@ -20,8 +21,8 @@ extern "C" { #endif /** - * @brief SENT Interface - * @defgroup sent_interface SENT Interface + * @brief Interfaces for Single Edge Nibble Transmission (SENT) peripherals. + * @defgroup sent_interface SENT * @since 4.2 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/smbus.h b/include/zephyr/drivers/smbus.h index de197becbc2a5..00e8d5767ef93 100644 --- a/include/zephyr/drivers/smbus.h +++ b/include/zephyr/drivers/smbus.h @@ -6,15 +6,16 @@ /** * @file - * @brief Public SMBus Driver APIs + * @ingroup smbus_interface + * @brief Main header file for SMBus (System Management Bus) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_SMBUS_H_ #define ZEPHYR_INCLUDE_DRIVERS_SMBUS_H_ /** - * @brief SMBus Interface - * @defgroup smbus_interface SMBus Interface + * @brief Interfaces for System Management Bus (SMBus). + * @defgroup smbus_interface SMBus * @since 3.4 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/spi.h b/include/zephyr/drivers/spi.h index 08a3f03137bc2..aac753c31d7fc 100644 --- a/include/zephyr/drivers/spi.h +++ b/include/zephyr/drivers/spi.h @@ -6,15 +6,17 @@ /** * @file - * @brief Public API for SPI drivers and applications + * @ingroup spi_interface + * @brief Main header file for SPI (Serial Peripheral Interface) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_SPI_H_ #define ZEPHYR_INCLUDE_DRIVERS_SPI_H_ /** - * @brief SPI Interface - * @defgroup spi_interface SPI Interface + * @brief Interfaces for Serial Peripheral Interface (SPI) + * controllers. + * @defgroup spi_interface SPI * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/stepper.h b/include/zephyr/drivers/stepper.h index 3440cc2e084ab..4d5ba757b9232 100644 --- a/include/zephyr/drivers/stepper.h +++ b/include/zephyr/drivers/stepper.h @@ -6,15 +6,16 @@ /** * @file drivers/stepper.h - * @brief Public API for Stepper Driver + * @ingroup stepper_interface + * @brief Main header file for stepper driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_STEPPER_H_ #define ZEPHYR_INCLUDE_DRIVERS_STEPPER_H_ /** - * @brief Stepper Driver Interface - * @defgroup stepper_interface Stepper Driver Interface + * @brief Interfaces for stepper motor controllers. + * @defgroup stepper_interface Stepper * @since 4.0 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/swdp.h b/include/zephyr/drivers/swdp.h index d742280e883f9..e16819a1909cb 100644 --- a/include/zephyr/drivers/swdp.h +++ b/include/zephyr/drivers/swdp.h @@ -6,7 +6,8 @@ /** * @file - * @brief Serial Wire Debug Port interface driver API + * @ingroup swdp_interface + * @brief Main header file for SWDP (Serial Wire Debug Port) driver API. */ #ifndef ZEPHYR_INCLUDE_SWDP_H_ @@ -18,28 +19,77 @@ extern "C" { #endif -/* SWDP packet request bits */ +/** + * @brief Interfaces for Serial Wire Debug Port (SWDP). + * @defgroup swdp_interface SWDP + * @since 3.7 + * @version 0.1.0 + * @ingroup io_interfaces + * @{ + */ + +/** + * @name SWD Packet Request Bits + * + * Bit definitions for SWD packet request fields. + * These bits are used to construct the 8-bit request packet header sent during an SWD transaction. + * + * @{ + */ + +/** Access Port (AP) or Debug Port (DP). 1 = AP, 0 = DP */ #define SWDP_REQUEST_APnDP BIT(0) +/** Read (1) or Write (0) operation */ #define SWDP_REQUEST_RnW BIT(1) +/** Address bit 2 for register selection */ #define SWDP_REQUEST_A2 BIT(2) +/** Address bit 3 for register selection */ #define SWDP_REQUEST_A3 BIT(3) -/* SWDP acknowledge response bits */ +/** @} */ + +/** + * @name SWD Acknowledge (ACK) Response Bits + * + * Bit definitions for SWD acknowledge response fields. + * These bits are used to indicate the result of an SWD transaction. + * + * @{ + */ + +/** Transaction completed successfully */ #define SWDP_ACK_OK BIT(0) +/** Target requests to retry the transaction later */ #define SWDP_ACK_WAIT BIT(1) +/** Target detected a fault condition */ #define SWDP_ACK_FAULT BIT(2) -/* SWDP transfer or parity error */ +/** @} */ + +/** Transfer or parity error detected during transaction */ #define SWDP_TRANSFER_ERROR BIT(3) -/* SWDP Interface pins */ +/** + * @name SWDP Interface Pin Definitions + * + * Pin identifiers for SWDP interface control. + * These constants define bit positions for controlling individual pins in the SWDP interface. + * + * @{ + */ + +/** Serial Wire Clock (SWCLK) pin identifier */ #define SWDP_SWCLK_PIN 0U +/** Serial Wire Data Input/Output (SWDIO) pin identifier */ #define SWDP_SWDIO_PIN 1U +/** Active-low reset (nRESET) pin identifier */ #define SWDP_nRESET_PIN 7U -/* - * Serial Wire Interface (SWDP) driver API. - * This is the mandatory API any Serial Wire driver needs to expose. +/** @} */ + +/** + * Serial Wire Debug Port (SWDP) driver API. + * This is the mandatory API any Serial Wire Debug Port driver needs to expose. */ struct swdp_api { /** @@ -148,4 +198,6 @@ struct swdp_api { } #endif +/** @} */ + #endif /* ZEPHYR_INCLUDE_SWDP_H_ */ diff --git a/include/zephyr/drivers/syscon.h b/include/zephyr/drivers/syscon.h index 6db686d8fbefc..afe41413fa403 100644 --- a/include/zephyr/drivers/syscon.h +++ b/include/zephyr/drivers/syscon.h @@ -6,15 +6,16 @@ /** * @file - * @brief Public SYSCON driver APIs + * @ingroup syscon_interface + * @brief Main header file for SYSCON (System Control) driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_SYSCON_H_ #define ZEPHYR_INCLUDE_DRIVERS_SYSCON_H_ /** - * @brief SYSCON Interface - * @defgroup syscon_interface SYSCON Interface + * @brief Interfaces for system control registers. + * @defgroup syscon_interface System control (SYSCON) * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/tee.h b/include/zephyr/drivers/tee.h index 97ceb76df4bed..11ae15bab05a0 100644 --- a/include/zephyr/drivers/tee.h +++ b/include/zephyr/drivers/tee.h @@ -5,9 +5,9 @@ */ /** - * @file drivers/tee.h - * - * @brief Public APIs for the tee driver. + * @file + * @ingroup tee_interface + * @brief Main header file for TEE (Trusted Execution Environment) driver API. */ /* @@ -44,8 +44,8 @@ #include /** - * @brief Trusted Execution Environment Interface - * @defgroup tee_interface TEE Interface + * @brief Interfaces to work with Trusted Execution Environment (TEE). + * @defgroup tee_interface TEE * @ingroup io_interfaces * @{ * diff --git a/include/zephyr/drivers/timer/ifx_tcpwm.h b/include/zephyr/drivers/timer/ifx_tcpwm.h new file mode 100644 index 0000000000000..d2cf610caa4a5 --- /dev/null +++ b/include/zephyr/drivers/timer/ifx_tcpwm.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * The TCPWM function and macros in the PDL use a complex set of arrays and marcos to + * reference a specific TCPWM instance. With the information in the .dtsi file, we + * have the absolute address for each TCPWM instance. We will make use of that + * when we provide the ADDRESS to the macros below. This means that the cntNum parameter + * is always 0. + */ + +#if !defined(IFX_TCPWM_H) +#define IFX_TCPWM_H + +#include +#include "cy_tcpwm.h" + +#define IFX_TCPWM_GetTrigPinLevel(ADDRESS, TRIGGERSELECT) \ + Cy_TCPWM_GetTrigPinLevel((TCPWM_Type *)ADDRESS, 0, TRIGGERSELECT) +#define IFX_TCPWM_SetDebugFreeze(ADDRESS, ENABLE) \ + Cy_TCPWM_SetDebugFreeze((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_Block_GetCC0BufVal(ADDRESS) Cy_TCPWM_Block_GetCC0BufVal((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Block_GetCC0Val(ADDRESS) Cy_TCPWM_Block_GetCC0Val((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Block_GetCC1BufVal(ADDRESS) Cy_TCPWM_Block_GetCC1BufVal((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Block_GetCC1Val(ADDRESS) Cy_TCPWM_Block_GetCC1Val((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Block_GetCounter(ADDRESS) Cy_TCPWM_Block_GetCounter((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Block_GetPeriod(ADDRESS) Cy_TCPWM_Block_GetPeriod((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_GetInterruptMask(ADDRESS) Cy_TCPWM_GetInterruptMask((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_GetInterruptStatus(ADDRESS) Cy_TCPWM_GetInterruptStatus((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_GetInterruptStatusMasked(ADDRESS) \ + Cy_TCPWM_GetInterruptStatusMasked((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Block_EnableCompare0Swap(ADDRESS, ENABLE) \ + Cy_TCPWM_Block_EnableCompare0Swap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_Block_EnableCompare1Swap(ADDRESS, ENABLE) \ + Cy_TCPWM_Block_EnableCompare1Swap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_Block_SetCC0BufVal(ADDRESS, COMPARE1) \ + Cy_TCPWM_Block_SetCC0BufVal((TCPWM_Type *)ADDRESS, 0, COMPARE1) +#define IFX_TCPWM_Block_SetCC0Val(ADDRESS, COMPARE0) \ + Cy_TCPWM_Block_SetCC0Val((TCPWM_Type *)ADDRESS, 0, COMPARE0) +#define IFX_TCPWM_Block_SetCC1BufVal(ADDRESS, COMPAREBUF1) \ + Cy_TCPWM_Block_SetCC1BufVal((TCPWM_Type *)ADDRESS, 0, COMPAREBUF1) +#define IFX_TCPWM_Block_SetCC1Val(ADDRESS, COMPARE1) \ + Cy_TCPWM_Block_SetCC1Val((TCPWM_Type *)ADDRESS, 0, COMPARE1) +#define IFX_TCPWM_Block_SetCounter(ADDRESS, COUNT) \ + Cy_TCPWM_Block_SetCounter((TCPWM_Type *)ADDRESS, 0, COUNT) +#define IFX_TCPWM_Block_SetPeriod(ADDRESS, PERIOD) \ + Cy_TCPWM_Block_SetPeriod((TCPWM_Type *)ADDRESS, 0, PERIOD) +#define IFX_TCPWM_ClearInterrupt(ADDRESS, SOURCE) \ + Cy_TCPWM_ClearInterrupt((TCPWM_Type *)ADDRESS, 0, SOURCE) +#define IFX_TCPWM_Disable_Single(ADDRESS) Cy_TCPWM_Disable_Single((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Enable_Single(ADDRESS) Cy_TCPWM_Enable_Single((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_SetInterrupt(ADDRESS, SOURCE) \ + Cy_TCPWM_SetInterrupt((TCPWM_Type *)ADDRESS, 0, SOURCE) +#define IFX_TCPWM_SetInterruptMask(ADDRESS, MASK) \ + Cy_TCPWM_SetInterruptMask((TCPWM_Type *)ADDRESS, 0, MASK) +#define IFX_TCPWM_TriggerCapture0(ADDRESS) Cy_TCPWM_TriggerCapture0((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_TriggerCapture1(ADDRESS) Cy_TCPWM_TriggerCapture1((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_TriggerStart_Single(ADDRESS) \ + Cy_TCPWM_TriggerStart_Single((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_TriggerStopOrKill_Single(ADDRESS) \ + Cy_TCPWM_TriggerStopOrKill_Single((TCPWM_Type *)ADDRESS, 0) + +#define IFX_TCPWM_Counter_GetCapture0BufVal(ADDRESS) \ + Cy_TCPWM_Counter_GetCapture0BufVal((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCapture0Val(ADDRESS) \ + Cy_TCPWM_Counter_GetCapture0Val((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCapture1BufVal(ADDRESS) \ + Cy_TCPWM_Counter_GetCapture1BufVal((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCapture1Val(ADDRESS) \ + Cy_TCPWM_Counter_GetCapture1Val((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCompare0BufVal(ADDRESS) \ + Cy_TCPWM_Counter_GetCompare0BufVal((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCompare0Val(ADDRESS) \ + Cy_TCPWM_Counter_GetCompare0Val((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCompare1BufVal(ADDRESS) \ + Cy_TCPWM_Counter_GetCompare1BufVal((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCompare1Val(ADDRESS) \ + Cy_TCPWM_Counter_GetCompare1Val((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetCounter(ADDRESS) Cy_TCPWM_Counter_GetCounter((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetPeriod(ADDRESS) Cy_TCPWM_Counter_GetPeriod((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_GetStatus(ADDRESS) Cy_TCPWM_Counter_GetStatus((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_Disable(ADDRESS) Cy_TCPWM_Counter_Disable((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_Enable(ADDRESS) Cy_TCPWM_Counter_Enable((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_Counter_EnableCompare0Swap(ADDRESS, ENABLE) \ + Cy_TCPWM_Counter_EnableCompare0Swap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_Counter_EnableCompare1Swap(ADDRESS, ENABLE) \ + Cy_TCPWM_Counter_EnableCompare1Swap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_Counter_EnableSwap(ADDRESS, ENABLE) \ + Cy_TCPWM_Counter_EnableSwap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_Counter_SetCompare0BufVal(ADDRESS, COMPARE1) \ + Cy_TCPWM_Counter_SetCompare0BufVal((TCPWM_Type *)ADDRESS, 0, COMPARE1) +#define IFX_TCPWM_Counter_SetCompare0Val(ADDRESS, COMPARE0) \ + Cy_TCPWM_Counter_SetCompare0Val((TCPWM_Type *)ADDRESS, 0, COMPARE0) +#define IFX_TCPWM_Counter_SetCompare1BufVal(ADDRESS, COMPAREBUF1) \ + Cy_TCPWM_Counter_SetCompare1BufVal((TCPWM_Type *)ADDRESS, 0, COMPAREBUF1) +#define IFX_TCPWM_Counter_SetCompare1Val(ADDRESS, COMPARE1) \ + Cy_TCPWM_Counter_SetCompare1Val((TCPWM_Type *)ADDRESS, 0, COMPARE1) +#define IFX_TCPWM_Counter_SetCounter(ADDRESS, COUNT) \ + Cy_TCPWM_Counter_SetCounter((TCPWM_Type *)ADDRESS, 0, COUNT) +#define IFX_TCPWM_Counter_SetDirection_Change_Mode(ADDRESS, DIRECTION_MODE) \ + Cy_TCPWM_Counter_SetDirection_Change_Mode((TCPWM_Type *)ADDRESS, 0, DIRECTION_MODE) +#define IFX_TCPWM_Counter_SetPeriod(ADDRESS, PERIOD) \ + Cy_TCPWM_Counter_SetPeriod((TCPWM_Type *)ADDRESS, 0, PERIOD) + +#define IFX_TCPWM_PWM_GetCompare0BufVal(ADDRESS) \ + Cy_TCPWM_PWM_GetCompare0BufVal((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_GetCompare0Val(ADDRESS) Cy_TCPWM_PWM_GetCompare0Val((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_GetCounter(ADDRESS) Cy_TCPWM_PWM_GetCounter((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_GetDtCounter(ADDRESS) Cy_TCPWM_PWM_GetDtCounter((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_GetPeriod0(ADDRESS) Cy_TCPWM_PWM_GetPeriod0((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_GetPeriod1(ADDRESS) Cy_TCPWM_PWM_GetPeriod1((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_GetStatus(ADDRESS) Cy_TCPWM_PWM_GetStatus((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_Disable(ADDRESS) Cy_TCPWM_PWM_Disable((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_Enable(ADDRESS) Cy_TCPWM_PWM_Enable((TCPWM_Type *)ADDRESS, 0) +#define IFX_TCPWM_PWM_EnableCompare0Swap(ADDRESS, ENABLE) \ + Cy_TCPWM_PWM_EnableCompare0Swap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_PWM_EnableLineSelectSwap(ADDRESS, ENABLE) \ + Cy_TCPWM_PWM_EnableLineSelectSwap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_PWM_EnablePeriodSwap(ADDRESS, ENABLE) \ + Cy_TCPWM_PWM_EnablePeriodSwap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_PWM_EnableSwap(ADDRESS, ENABLE) \ + Cy_TCPWM_PWM_EnableSwap((TCPWM_Type *)ADDRESS, 0, ENABLE) +#define IFX_TCPWM_PWM_Init(ADDRESS, CONFIG) Cy_TCPWM_PWM_Init((TCPWM_Type *)ADDRESS, 0, CONFIG) +#define IFX_TCPWM_PWM_PWMDeadTime(ADDRESS, DEADTIME) \ + Cy_TCPWM_PWM_PWMDeadTime((TCPWM_Type *)ADDRESS, 0, DEADTIME) +#define IFX_TCPWM_PWM_PWMDeadTimeBuff(ADDRESS, DEADTIME) \ + Cy_TCPWM_PWM_PWMDeadTimeBuff((TCPWM_Type *)ADDRESS, 0, DEADTIME) +#define IFX_TCPWM_PWM_PWMDeadTimeBuffN(ADDRESS, DEADTIME) \ + Cy_TCPWM_PWM_PWMDeadTimeBuffN((TCPWM_Type *)ADDRESS, 0, DEADTIME) +#define IFX_TCPWM_PWM_PWMDeadTimeN(ADDRESS, DEADTIME) \ + Cy_TCPWM_PWM_PWMDeadTimeN((TCPWM_Type *)ADDRESS, 0, DEADTIME) +#define IFX_TCPWM_PWM_SetCompare0BufVal(ADDRESS, COMPAREBUF0) \ + Cy_TCPWM_PWM_SetCompare0BufVal((TCPWM_Type *)ADDRESS, 0, COMPAREBUF0) +#define IFX_TCPWM_PWM_SetCompare0Val(ADDRESS, COMPARE0) \ + Cy_TCPWM_PWM_SetCompare0Val((TCPWM_Type *)ADDRESS, 0, COMPARE0) +#define IFX_TCPWM_PWM_SetCounter(ADDRESS, COUNT) \ + Cy_TCPWM_PWM_SetCounter((TCPWM_Type *)ADDRESS, 0, COUNT) +#define IFX_TCPWM_PWM_SetDT(ADDRESS, DEADTIME) \ + Cy_TCPWM_PWM_SetDT((TCPWM_Type *)ADDRESS, 0, DEADTIME) +#define IFX_TCPWM_PWM_SetDTBuff(ADDRESS, DEADTIME) \ + Cy_TCPWM_PWM_SetDTBuff((TCPWM_Type *)ADDRESS, 0, DEADTIME) +#define IFX_TCPWM_PWM_SetPeriod0(ADDRESS, PERIOD0) \ + Cy_TCPWM_PWM_SetPeriod0((TCPWM_Type *)ADDRESS, 0, PERIOD0) +#define IFX_TCPWM_PWM_SetPeriod1(ADDRESS, PERIOD1) \ + Cy_TCPWM_PWM_SetPeriod1((TCPWM_Type *)ADDRESS, 0, PERIOD1) +#define IFX_en_tcpwm_status_t(ADDRESS, MODE, PERIOD, DUTY, LIMITER) \ + cy_en_tcpwm_status_t Cy_TCPWM_PWM_Configure_Dithering((TCPWM_Type *)ADDRESS, 0, MODE, \ + PERIOD, DUTY, LIMITER) +#define IFX_TCPWM_TriggerCaptureOrSwap_Single(ADDRESS) \ + Cy_TCPWM_TriggerCaptureOrSwap_Single((TCPWM_Type *)ADDRESS, 0) +#endif /* CY_TCPWM_H */ diff --git a/include/zephyr/drivers/uart.h b/include/zephyr/drivers/uart.h index d6ce894cf28d1..b4edee1310999 100644 --- a/include/zephyr/drivers/uart.h +++ b/include/zephyr/drivers/uart.h @@ -7,15 +7,17 @@ /** * @file - * @brief Public APIs for UART drivers + * @ingroup uart_interface + * @brief Main header file for UART driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_UART_H_ #define ZEPHYR_INCLUDE_DRIVERS_UART_H_ /** - * @brief UART Interface - * @defgroup uart_interface UART Interface + * @brief Interfaces for Universal Asynchronous Receiver/Transmitter (UART) + * controllers. + * @defgroup uart_interface UART * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/usb/udc.h b/include/zephyr/drivers/usb/udc.h index 197cfe60e5575..9b1f25e78e093 100644 --- a/include/zephyr/drivers/usb/udc.h +++ b/include/zephyr/drivers/usb/udc.h @@ -295,8 +295,8 @@ struct udc_data { /** * @brief New USB device controller (UDC) driver API - * @defgroup udc_api USB device controller driver API - * @ingroup io_interfaces + * @defgroup udc_api USB Device Controller + * @ingroup usb_interfaces * @since 3.3 * @version 0.1.0 * @{ diff --git a/include/zephyr/drivers/usb/uhc.h b/include/zephyr/drivers/usb/uhc.h index b15afbf845e6c..1e0acd71aad1f 100644 --- a/include/zephyr/drivers/usb/uhc.h +++ b/include/zephyr/drivers/usb/uhc.h @@ -20,8 +20,8 @@ /** * @brief USB host controller (UHC) driver API - * @defgroup uhc_api USB host controller driver API - * @ingroup io_interfaces + * @defgroup uhc_api USB Host Controller + * @ingroup usb_interfaces * @since 3.3 * @version 0.1.1 * @{ diff --git a/include/zephyr/drivers/usb/usb_bc12.h b/include/zephyr/drivers/usb/usb_bc12.h index f433896bfc9f9..d5e710607e320 100644 --- a/include/zephyr/drivers/usb/usb_bc12.h +++ b/include/zephyr/drivers/usb/usb_bc12.h @@ -19,9 +19,9 @@ extern "C" { #endif /** - * @brief BC1.2 driver APIs - * @defgroup b12_interface BC1.2 driver APIs - * @ingroup io_interfaces + * @brief USB Battery Charging (BC1.2) driver APIs + * @defgroup b12_interface Battery Charging (BC1.2) + * @ingroup usb_interfaces * @{ */ diff --git a/include/zephyr/drivers/usb_c/usbc_tc.h b/include/zephyr/drivers/usb_c/usbc_tc.h index 0b8ac1cbf6fa8..ab87bb75d97cc 100644 --- a/include/zephyr/drivers/usb_c/usbc_tc.h +++ b/include/zephyr/drivers/usb_c/usbc_tc.h @@ -15,9 +15,9 @@ #define ZEPHYR_INCLUDE_DRIVERS_USBC_USBC_TC_H_ /** - * @brief USB Type-C + * @brief Support for USB Type-C cables and connectors * @defgroup usb_type_c USB Type-C - * @ingroup io_interfaces + * @ingroup usb_interfaces * @{ */ diff --git a/include/zephyr/drivers/video-controls.h b/include/zephyr/drivers/video-controls.h index fbd56c16b3128..f1bb7ad8dbbf8 100644 --- a/include/zephyr/drivers/video-controls.h +++ b/include/zephyr/drivers/video-controls.h @@ -10,8 +10,8 @@ /** * @file - * - * @brief Public APIs for Video. + * @ingroup video_controls + * @brief Main header file for video controls driver API. */ /** diff --git a/include/zephyr/drivers/video.h b/include/zephyr/drivers/video.h index b4da982476ef6..6eef2d9ebcaa1 100644 --- a/include/zephyr/drivers/video.h +++ b/include/zephyr/drivers/video.h @@ -1,9 +1,3 @@ -/** - * @file - * - * @brief Public APIs for Video. - */ - /* * Copyright (c) 2019 Linaro Limited. * Copyright 2025 NXP @@ -11,12 +5,19 @@ * * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @ingroup video_interface + * @brief Main header file for video driver API. + */ + #ifndef ZEPHYR_INCLUDE_VIDEO_H_ #define ZEPHYR_INCLUDE_VIDEO_H_ /** - * @brief Video Interface - * @defgroup video_interface Video Interface + * @brief Interfaces for video devices. + * @defgroup video_interface Video * @since 2.1 * @version 1.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/virtio.h b/include/zephyr/drivers/virtio.h index 5f4f97c4e5e7b..ef2ca4907bca6 100644 --- a/include/zephyr/drivers/virtio.h +++ b/include/zephyr/drivers/virtio.h @@ -4,6 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup virtio_interface + * @brief Main header file for Virtio driver API. + */ + #ifndef ZEPHYR_VIRTIO_VIRTIO_H_ #define ZEPHYR_VIRTIO_VIRTIO_H_ #include @@ -14,8 +20,8 @@ extern "C" { #endif /** - * @brief Virtio Interface - * @defgroup virtio_interface Virtio Interface + * @brief Interfaces for Virtual I/O (VIRTIO) devices. + * @defgroup virtio_interface VIRTIO * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/virtualization/ivshmem.h b/include/zephyr/drivers/virtualization/ivshmem.h index b0662d08d5524..597380fc803ff 100644 --- a/include/zephyr/drivers/virtualization/ivshmem.h +++ b/include/zephyr/drivers/virtualization/ivshmem.h @@ -8,8 +8,8 @@ #define ZEPHYR_INCLUDE_DRIVERS_VIRTUALIZATION_IVSHMEM_H_ /** - * @brief Inter-VM Shared Memory (ivshmem) reference API - * @defgroup ivshmem Inter-VM Shared Memory (ivshmem) reference API + * @brief Interfaces for Inter-VM Shared Memory (ivshmem). + * @defgroup ivshmem Inter-VM Shared Memory * @ingroup io_interfaces * @{ */ diff --git a/include/zephyr/drivers/w1.h b/include/zephyr/drivers/w1.h index fe264489e10eb..73d2f9b6a3301 100644 --- a/include/zephyr/drivers/w1.h +++ b/include/zephyr/drivers/w1.h @@ -6,8 +6,9 @@ */ /** - * @file - * @brief Public 1-Wire Driver APIs + * @file zephyr/drivers/w1.h + * @ingroup w1_interface + * @brief Main header file for 1-Wire driver API. */ #ifndef ZEPHYR_INCLUDE_DRIVERS_W1_H_ @@ -24,8 +25,8 @@ extern "C" { #endif /** - * @brief 1-Wire Interface - * @defgroup w1_interface 1-Wire Interface + * @brief Interfaces for 1-Wire devices. + * @defgroup w1_interface 1-Wire * @since 3.2 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/drivers/watchdog.h b/include/zephyr/drivers/watchdog.h index fdeb9ef0c3489..820d7b880f27c 100644 --- a/include/zephyr/drivers/watchdog.h +++ b/include/zephyr/drivers/watchdog.h @@ -5,12 +5,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @ingroup watchdog_interface + * @brief Main header file for watchdog driver API. + */ + #ifndef ZEPHYR_INCLUDE_DRIVERS_WATCHDOG_H_ #define ZEPHYR_INCLUDE_DRIVERS_WATCHDOG_H_ /** - * @brief Watchdog Interface - * @defgroup watchdog_interface Watchdog Interface + * @brief Interfaces for watchdog devices. + * @defgroup watchdog_interface Watchdog * @since 1.0 * @version 1.0.0 * @ingroup io_interfaces diff --git a/include/zephyr/dt-bindings/clock/esp32h2_clock.h b/include/zephyr/dt-bindings/clock/esp32h2_clock.h new file mode 100644 index 0000000000000..0ef72eb34e65f --- /dev/null +++ b/include/zephyr/dt-bindings/clock/esp32h2_clock.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_ + +/* Supported CPU clock Sources */ +#define ESP32_CPU_CLK_SRC_XTAL 0U +#define ESP32_CPU_CLK_SRC_PLL 1U +#define ESP32_CLK_SRC_RC_FAST 2U +#define ESP32_CPU_CLK_SRC_FLASH_PLL 3U + +/* Supported CPU frequencies */ +#define ESP32_CLK_CPU_PLL_48M 48000000 +#define ESP32_CLK_CPU_FLASH_PLL_64M 64000000 +#define ESP32_CLK_CPU_PLL_96M 96000000 +#define ESP32_CLK_CPU_RC_FAST_FREQ 8500000 + +/* Supported XTAL Frequencies */ +#define ESP32_CLK_XTAL_32M 32000000 + +/* Supported RTC fast clock sources */ +#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0 +#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1 + +/* Supported RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 +#define ESP32_RTC_SLOW_CLK_SRC_RC32K 2 +#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 + +/* RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 +#define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ 32768 + +/* Modules IDs + * These IDs are actually offsets in CLK and RST Control registers. + * These IDs shouldn't be changed unless there is a Hardware change + * from Espressif. + * + * Basic Modules + * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG + */ +#define ESP32_LEDC_MODULE 0 +#define ESP32_UART0_MODULE 1 +#define ESP32_UART1_MODULE 2 +#define ESP32_USB_DEVICE_MODULE 3 +#define ESP32_I2C0_MODULE 4 +#define ESP32_I2C1_MODULE 5 +#define ESP32_I2S1_MODULE 6 +#define ESP32_TIMG0_MODULE 7 +#define ESP32_TIMG1_MODULE 8 +#define ESP32_UHCI0_MODULE 9 +#define ESP32_RMT_MODULE 10 +#define ESP32_PCNT_MODULE 11 +#define ESP32_SPI_MODULE 12 +#define ESP32_SPI2_MODULE 13 +#define ESP32_TWAI0_MODULE 14 +#define ESP32_RNG_MODULE 15 +#define ESP32_RSA_MODULE 16 +#define ESP32_AES_MODULE 17 +#define ESP32_SHA_MODULE 18 +#define ESP32_ECC_MODULE 19 +#define ESP32_HMAC_MODULE 20 +#define ESP32_DS_MODULE 21 +#define ESP32_ECDSA_MODULE 22 +#define ESP32_GDMA_MODULE 23 +#define ESP32_MCPWM0_MODULE 24 +#define ESP32_ETM_MODULE 25 +#define ESP32_PARLIO_MODULE 26 +#define ESP32_SYSTIMER_MODULE 27 +#define ESP32_SARADC_MODULE 28 +#define ESP32_TEMPSENSOR_MODULE 29 +#define ESP32_REGDMA_MODULE 30 +/* Peripherals clock managed by the modem_clock driver must be listed last */ +#define ESP32_BT_MODULE 31 +#define ESP32_IEEE802154_MODULE 32 +#define ESP32_COEX_MODULE 33 +#define ESP32_PHY_MODULE 34 +#define ESP32_ANA_I2C_MASTER_MODULE 35 +#define ESP32_MODEM_ETM_MODULE 36 +#define ESP32_MODEM_ADC_COMMON_FE_MODULE 37 +#define ESP32_MODULE_MAX 38 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_ */ diff --git a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h index 6df244712536e..a83de65a7060c 100644 --- a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h +++ b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h @@ -155,6 +155,9 @@ #define IMX_CCM_LPIT2_CLK 0x2301UL #define IMX_CCM_LPIT3_CLK 0x2302UL +/* KPP */ +#define IMX_CCM_KPP_CLK 0x2400UL + /* QTMR */ #define IMX_CCM_QTMR_CLK 0x6000UL #define IMX_CCM_QTMR1_CLK 0x6000UL diff --git a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h index 895d227e3a60c..5a11ed64d4049 100644 --- a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h @@ -69,7 +69,11 @@ #define STM32_CLOCK_PERIPH_I2C7 0x7BC #define STM32_CLOCK_PERIPH_I2C8 0x7C0 +/* Watchdog Peripheral */ +#define STM32_CLOCK_PERIPH_IWDG4 0x894 +#define STM32_CLOCK_PERIPH_WWDG1 0x89C + #define STM32_CLOCK_PERIPH_MIN STM32_CLOCK_PERIPH_GPIOA -#define STM32_CLOCK_PERIPH_MAX STM32_CLOCK_PERIPH_I2C8 +#define STM32_CLOCK_PERIPH_MAX STM32_CLOCK_PERIPH_WWDG1 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/dma/silabs/xg28-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg28-dma.h index 904e80ccef88b..70ff063a0df4f 100644 --- a/include/zephyr/dt-bindings/dma/silabs/xg28-dma.h +++ b/include/zephyr/dt-bindings/dma/silabs/xg28-dma.h @@ -7,7 +7,7 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_XG28_DMA_H_ #include -#include +#include "common-dma.h" /** * Definition of Silabs LDMA request signal @@ -57,5 +57,6 @@ #define DMA_REQSEL_EUSART2TXFL (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 1)) #define DMA_REQSEL_LESENSEFIFO (FIELD_PREP(DMA_SRC_MASK, 19) | FIELD_PREP(DMA_SIG_MASK, 0)) #define DMA_REQSEL_LCD (FIELD_PREP(DMA_SRC_MASK, 20) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_MVPREQ (FIELD_PREP(DMA_SRC_MASK, 21) | FIELD_PREP(DMA_SIG_MASK, 0)) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_XG28_DMA_H_ */ diff --git a/include/zephyr/dt-bindings/gnss/u_blox_m8.h b/include/zephyr/dt-bindings/gnss/u_blox_m8.h deleted file mode 100644 index 38ab27eee00e1..0000000000000 --- a/include/zephyr/dt-bindings/gnss/u_blox_m8.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GNSS_U_BLOX_M8_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_GNSS_U_BLOX_M8_H_ - -#include - -/* UART Baudrate. */ -#define UBX_M8_UART_BAUDRATE_4800 0x00 -#define UBX_M8_UART_BAUDRATE_9600 0x01 -#define UBX_M8_UART_BAUDRATE_19200 0x02 -#define UBX_M8_UART_BAUDRATE_38400 0x03 -#define UBX_M8_UART_BAUDRATE_57600 0x04 -#define UBX_M8_UART_BAUDRATE_115200 0x05 -#define UBX_M8_UART_BAUDRATE_230400 0x06 -#define UBX_M8_UART_BAUDRATE_460800 0x07 -#define UBX_M8_UART_BAUDRATE_921600 0x08 - -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GNSS_U_BLOX_M8_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/arduino-header-r3.h b/include/zephyr/dt-bindings/gpio/arduino-header-r3.h index d54913ba9aff4..ceac67e3347b0 100644 --- a/include/zephyr/dt-bindings/gpio/arduino-header-r3.h +++ b/include/zephyr/dt-bindings/gpio/arduino-header-r3.h @@ -1,33 +1,48 @@ -/** +/* * Copyright (c) 2025 TOKITA Hiroshi * * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @brief Arduino Uno (R3) header pin constants + * @ingroup arduino-header-r3 + */ + #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_ -#define ARDUINO_HEADER_R3_A0 0 -#define ARDUINO_HEADER_R3_A1 1 -#define ARDUINO_HEADER_R3_A2 2 -#define ARDUINO_HEADER_R3_A3 3 -#define ARDUINO_HEADER_R3_A4 4 -#define ARDUINO_HEADER_R3_A5 5 -#define ARDUINO_HEADER_R3_D0 6 -#define ARDUINO_HEADER_R3_D1 7 -#define ARDUINO_HEADER_R3_D2 8 -#define ARDUINO_HEADER_R3_D3 9 -#define ARDUINO_HEADER_R3_D4 10 -#define ARDUINO_HEADER_R3_D5 11 -#define ARDUINO_HEADER_R3_D6 12 -#define ARDUINO_HEADER_R3_D7 13 -#define ARDUINO_HEADER_R3_D8 14 -#define ARDUINO_HEADER_R3_D9 15 -#define ARDUINO_HEADER_R3_D10 16 -#define ARDUINO_HEADER_R3_D11 17 -#define ARDUINO_HEADER_R3_D12 18 -#define ARDUINO_HEADER_R3_D13 19 -#define ARDUINO_HEADER_R3_D14 20 -#define ARDUINO_HEADER_R3_D15 21 +/** + * @defgroup arduino-header-r3 Arduino Uno (R3) header + * @brief Constants for pins exposed on Arduino Uno (R3) header + * @ingroup devicetree-gpio-pin-headers + * @{ + */ + +#define ARDUINO_HEADER_R3_A0 0 /**< Analog pin 0 (A0) */ +#define ARDUINO_HEADER_R3_A1 1 /**< Analog pin 1 (A1) */ +#define ARDUINO_HEADER_R3_A2 2 /**< Analog pin 2 (A2) */ +#define ARDUINO_HEADER_R3_A3 3 /**< Analog pin 3 (A3) */ +#define ARDUINO_HEADER_R3_A4 4 /**< Analog pin 4 (A4) */ +#define ARDUINO_HEADER_R3_A5 5 /**< Analog pin 5 (A5) */ +#define ARDUINO_HEADER_R3_D0 6 /**< Digital pin 0 (D0) */ +#define ARDUINO_HEADER_R3_D1 7 /**< Digital pin 1 (D1) */ +#define ARDUINO_HEADER_R3_D2 8 /**< Digital pin 2 (D2) */ +#define ARDUINO_HEADER_R3_D3 9 /**< Digital pin 3 (D3) */ +#define ARDUINO_HEADER_R3_D4 10 /**< Digital pin 4 (D4) */ +#define ARDUINO_HEADER_R3_D5 11 /**< Digital pin 5 (D5) */ +#define ARDUINO_HEADER_R3_D6 12 /**< Digital pin 6 (D6) */ +#define ARDUINO_HEADER_R3_D7 13 /**< Digital pin 7 (D7) */ +#define ARDUINO_HEADER_R3_D8 14 /**< Digital pin 8 (D8) */ +#define ARDUINO_HEADER_R3_D9 15 /**< Digital pin 9 (D9) */ +#define ARDUINO_HEADER_R3_D10 16 /**< Digital pin 10 (D10) */ +#define ARDUINO_HEADER_R3_D11 17 /**< Digital pin 11 (D11) */ +#define ARDUINO_HEADER_R3_D12 18 /**< Digital pin 12 (D12) */ +#define ARDUINO_HEADER_R3_D13 19 /**< Digital pin 13 (D13) */ +#define ARDUINO_HEADER_R3_D14 20 /**< Digital pin 14 (D14) */ +#define ARDUINO_HEADER_R3_D15 21 /**< Digital pin 15 (D15) */ + +/** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/arduino-mkr-header.h b/include/zephyr/dt-bindings/gpio/arduino-mkr-header.h index d6c511424252d..ce96d22ef0a0e 100644 --- a/include/zephyr/dt-bindings/gpio/arduino-mkr-header.h +++ b/include/zephyr/dt-bindings/gpio/arduino-mkr-header.h @@ -1,33 +1,48 @@ -/** +/* * Copyright (c) 2025 TOKITA Hiroshi * * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @brief Arduino MKR header pin constants + * @ingroup arduino-mkr-header + */ + #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_MKR_HEADER_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_MKR_HEADER_H_ -#define ARDUINO_MKR_HEADER_D0 0 -#define ARDUINO_MKR_HEADER_D1 1 -#define ARDUINO_MKR_HEADER_D2 2 -#define ARDUINO_MKR_HEADER_D3 3 -#define ARDUINO_MKR_HEADER_D4 4 -#define ARDUINO_MKR_HEADER_D5 5 -#define ARDUINO_MKR_HEADER_D6 6 -#define ARDUINO_MKR_HEADER_D7 7 -#define ARDUINO_MKR_HEADER_D8 8 -#define ARDUINO_MKR_HEADER_D9 9 -#define ARDUINO_MKR_HEADER_D10 10 -#define ARDUINO_MKR_HEADER_D11 11 -#define ARDUINO_MKR_HEADER_D12 12 -#define ARDUINO_MKR_HEADER_D13 13 -#define ARDUINO_MKR_HEADER_D14 14 -#define ARDUINO_MKR_HEADER_A0 15 -#define ARDUINO_MKR_HEADER_A1 16 -#define ARDUINO_MKR_HEADER_A2 17 -#define ARDUINO_MKR_HEADER_A3 18 -#define ARDUINO_MKR_HEADER_A4 19 -#define ARDUINO_MKR_HEADER_A5 20 -#define ARDUINO_MKR_HEADER_A6 21 +/** + * @defgroup arduino-mkr-header Arduino MKR header + * @brief Constants for pins exposed on Arduino MKR header + * @ingroup devicetree-gpio-pin-headers + * @{ + */ + +#define ARDUINO_MKR_HEADER_D0 0 /**< Digital pin 0 (D0) */ +#define ARDUINO_MKR_HEADER_D1 1 /**< Digital pin 1 (D1) */ +#define ARDUINO_MKR_HEADER_D2 2 /**< Digital pin 2 (D2) */ +#define ARDUINO_MKR_HEADER_D3 3 /**< Digital pin 3 (D3) */ +#define ARDUINO_MKR_HEADER_D4 4 /**< Digital pin 4 (D4) */ +#define ARDUINO_MKR_HEADER_D5 5 /**< Digital pin 5 (D5) */ +#define ARDUINO_MKR_HEADER_D6 6 /**< Digital pin 6 (D6) */ +#define ARDUINO_MKR_HEADER_D7 7 /**< Digital pin 7 (D7) */ +#define ARDUINO_MKR_HEADER_D8 8 /**< Digital pin 8 (D8/COPI) */ +#define ARDUINO_MKR_HEADER_D9 9 /**< Digital pin 9 (D9/SCK) */ +#define ARDUINO_MKR_HEADER_D10 10 /**< Digital pin 10 (D10/CIPO) */ +#define ARDUINO_MKR_HEADER_D11 11 /**< Digital pin 11 (D11/SDA) */ +#define ARDUINO_MKR_HEADER_D12 12 /**< Digital pin 12 (D12/SCL) */ +#define ARDUINO_MKR_HEADER_D13 13 /**< Digital pin 13 (D13/RX) */ +#define ARDUINO_MKR_HEADER_D14 14 /**< Digital pin 14 (D14/TX) */ +#define ARDUINO_MKR_HEADER_A0 15 /**< Analog pin 0 (A0/D15/DAC0) */ +#define ARDUINO_MKR_HEADER_A1 16 /**< Analog pin 1 (A1/D16) */ +#define ARDUINO_MKR_HEADER_A2 17 /**< Analog pin 2 (A2/D17) */ +#define ARDUINO_MKR_HEADER_A3 18 /**< Analog pin 3 (A3/D18) */ +#define ARDUINO_MKR_HEADER_A4 19 /**< Analog pin 4 (A4/D19) */ +#define ARDUINO_MKR_HEADER_A5 20 /**< Analog pin 5 (A5/D20) */ +#define ARDUINO_MKR_HEADER_A6 21 /**< Analog pin 6 (A6/D21) */ + +/** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_MKR_HEADER_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/arduino-nano-header.h b/include/zephyr/dt-bindings/gpio/arduino-nano-header.h index c88074ae6d87e..6d712ccf2fdfe 100644 --- a/include/zephyr/dt-bindings/gpio/arduino-nano-header.h +++ b/include/zephyr/dt-bindings/gpio/arduino-nano-header.h @@ -1,41 +1,56 @@ -/** +/* * Copyright (c) 2025 TOKITA Hiroshi * * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @brief Arduino Nano header pin constants + * @ingroup arduino-nano-header + */ + #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_NANO_HEADER_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_NANO_HEADER_H_ -#define ARDUINO_NANO_HEADER_D0 0 -#define ARDUINO_NANO_HEADER_D1 1 -#define ARDUINO_NANO_HEADER_D2 2 -#define ARDUINO_NANO_HEADER_D3 3 -#define ARDUINO_NANO_HEADER_D4 4 -#define ARDUINO_NANO_HEADER_D5 5 -#define ARDUINO_NANO_HEADER_D6 6 -#define ARDUINO_NANO_HEADER_D7 7 -#define ARDUINO_NANO_HEADER_D8 8 -#define ARDUINO_NANO_HEADER_D9 9 -#define ARDUINO_NANO_HEADER_D10 10 -#define ARDUINO_NANO_HEADER_D11 11 -#define ARDUINO_NANO_HEADER_D12 12 -#define ARDUINO_NANO_HEADER_D13 13 -#define ARDUINO_NANO_HEADER_D14 14 -#define ARDUINO_NANO_HEADER_D15 15 -#define ARDUINO_NANO_HEADER_D16 16 -#define ARDUINO_NANO_HEADER_D17 17 -#define ARDUINO_NANO_HEADER_D18 18 -#define ARDUINO_NANO_HEADER_D19 19 -#define ARDUINO_NANO_HEADER_D20 20 -#define ARDUINO_NANO_HEADER_D21 21 -#define ARDUINO_NANO_HEADER_A0 14 -#define ARDUINO_NANO_HEADER_A1 15 -#define ARDUINO_NANO_HEADER_A2 16 -#define ARDUINO_NANO_HEADER_A3 19 -#define ARDUINO_NANO_HEADER_A4 18 -#define ARDUINO_NANO_HEADER_A5 18 -#define ARDUINO_NANO_HEADER_A6 20 -#define ARDUINO_NANO_HEADER_A7 21 +/** + * @defgroup arduino-nano-header Arduino Nano header + * @brief Constants for pins exposed on Arduino Nano header + * @ingroup devicetree-gpio-pin-headers + * @{ + */ + +#define ARDUINO_NANO_HEADER_D0 0 /**< Digital pin 0 (D0/RX) */ +#define ARDUINO_NANO_HEADER_D1 1 /**< Digital pin 1 (D1/TX) */ +#define ARDUINO_NANO_HEADER_D2 2 /**< Digital pin 2 (D2) */ +#define ARDUINO_NANO_HEADER_D3 3 /**< Digital pin 3 (D3) */ +#define ARDUINO_NANO_HEADER_D4 4 /**< Digital pin 4 (D4) */ +#define ARDUINO_NANO_HEADER_D5 5 /**< Digital pin 5 (D5) */ +#define ARDUINO_NANO_HEADER_D6 6 /**< Digital pin 6 (D6) */ +#define ARDUINO_NANO_HEADER_D7 7 /**< Digital pin 7 (D7) */ +#define ARDUINO_NANO_HEADER_D8 8 /**< Digital pin 8 (D8) */ +#define ARDUINO_NANO_HEADER_D9 9 /**< Digital pin 9 (D9) */ +#define ARDUINO_NANO_HEADER_D10 10 /**< Digital pin 10 (D10/SS) */ +#define ARDUINO_NANO_HEADER_D11 11 /**< Digital pin 11 (D11/COPI) */ +#define ARDUINO_NANO_HEADER_D12 12 /**< Digital pin 12 (D12/CIPO) */ +#define ARDUINO_NANO_HEADER_D13 13 /**< Digital pin 13 (D13/SCK) */ +#define ARDUINO_NANO_HEADER_D14 14 /**< Digital pin 14 (D14) */ +#define ARDUINO_NANO_HEADER_D15 15 /**< Digital pin 15 (D15) */ +#define ARDUINO_NANO_HEADER_D16 16 /**< Digital pin 16 (D16) */ +#define ARDUINO_NANO_HEADER_D17 17 /**< Digital pin 17 (D17) */ +#define ARDUINO_NANO_HEADER_D18 18 /**< Digital pin 18 (D18) */ +#define ARDUINO_NANO_HEADER_D19 19 /**< Digital pin 19 (D19) */ +#define ARDUINO_NANO_HEADER_D20 20 /**< Digital pin 20 (D20) */ +#define ARDUINO_NANO_HEADER_D21 21 /**< Digital pin 21 (D21) */ +#define ARDUINO_NANO_HEADER_A0 14 /**< Analog pin 0 (A0) */ +#define ARDUINO_NANO_HEADER_A1 15 /**< Analog pin 1 (A1) */ +#define ARDUINO_NANO_HEADER_A2 16 /**< Analog pin 2 (A2) */ +#define ARDUINO_NANO_HEADER_A3 19 /**< Analog pin 3 (A3) */ +#define ARDUINO_NANO_HEADER_A4 18 /**< Analog pin 4 (A4) */ +#define ARDUINO_NANO_HEADER_A5 19 /**< Analog pin 5 (A5) */ +#define ARDUINO_NANO_HEADER_A6 20 /**< Analog pin 6 (A6) */ +#define ARDUINO_NANO_HEADER_A7 21 /**< Analog pin 7 (A7) */ + +/** @} */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_NANO_HEADER_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/dvp-20pin-connector.h b/include/zephyr/dt-bindings/gpio/dvp-20pin-connector.h index 5d156c4d1d0f9..2eaf16695d86c 100644 --- a/include/zephyr/dt-bindings/gpio/dvp-20pin-connector.h +++ b/include/zephyr/dt-bindings/gpio/dvp-20pin-connector.h @@ -2,11 +2,20 @@ * Copyright (c) 2025 tinyVision.ai Inc. * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @brief Arducam DVP 20-pin connector pin constants + * @ingroup dvp-20pin-connector + */ + #ifndef INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_DVP_20PIN_CONNECTOR_H_ #define INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_DVP_20PIN_CONNECTOR_H_ /** - * @name Arducam DVP 20-pin or 18-pin connector pinout + * @defgroup dvp-20pin-connector Arducam DVP 20-pin connector + * @brief Constants for pins exposed on Arducam DVP 20-pin or 18-pin connector + * @ingroup devicetree-gpio-pin-headers * @{ */ #define DVP_20PIN_SCL 3 /**< I2C clock pin */ diff --git a/include/zephyr/dt-bindings/gpio/gpio.h b/include/zephyr/dt-bindings/gpio/gpio.h index 29efad3a9f085..03b8aa7f7689b 100644 --- a/include/zephyr/dt-bindings/gpio/gpio.h +++ b/include/zephyr/dt-bindings/gpio/gpio.h @@ -13,7 +13,7 @@ */ /** Mask for DT GPIO flags. */ -#define GPIO_DT_FLAGS_MASK 0x3F +#define GPIO_DT_FLAGS_MASK 0x7F /** * @name GPIO pin active level flags diff --git a/include/zephyr/dt-bindings/gpio/raspberrypi-csi-connector.h b/include/zephyr/dt-bindings/gpio/raspberrypi-csi-connector.h index eadc896aa892a..dd775ecf3aaad 100644 --- a/include/zephyr/dt-bindings/gpio/raspberrypi-csi-connector.h +++ b/include/zephyr/dt-bindings/gpio/raspberrypi-csi-connector.h @@ -2,11 +2,20 @@ * Copyright (c) 2025 STMicroelectronics * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @brief Raspberry Pi CSI camera connector pin constants + * @ingroup raspberrypi-csi-connector + */ + #ifndef INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_RASPBERRYPI_CSI_CONNECTOR_H_ #define INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_RASPBERRYPI_CSI_CONNECTOR_H_ /** - * @name CSI camera connector GPIO list + * @defgroup raspberrypi-csi-connector Raspberry Pi CSI connector + * @brief Constants for pins exposed on Raspberry Pi CSI camera connector + * @ingroup devicetree-gpio-pin-headers * @{ */ #define CSI_IO0 1 /**< GPIO0 */ diff --git a/include/zephyr/dt-bindings/gpio/realtek-gpio.h b/include/zephyr/dt-bindings/gpio/realtek-gpio.h index 4ba33e70d36d6..f3d84e3d49114 100644 --- a/include/zephyr/dt-bindings/gpio/realtek-gpio.h +++ b/include/zephyr/dt-bindings/gpio/realtek-gpio.h @@ -39,4 +39,128 @@ /** Interrupt Mask since rts5912 does not support GPIO_INT_LEVELS_LOGICAL*/ #define RTS5912_GPIO_INTR_MASK (1U << 21 | 1U << 22 | 1U << 24 | 1U << 25 | 1U << 26) +/** + * @brief Map GPIO signal name to devicetree binding. + * + * RTS5912 documentation uses octal GPIO pin + * numbering. These macros do not require the user to do the transfer for gpio. + * + * Example DT usage: + * + * @code{.dts} + * gpios = ; + * @endcode + * + * @{ + */ + +#define RTS5912_GPIO000 &gpioa 0 +#define RTS5912_GPIO001 &gpioa 1 +#define RTS5912_GPIO002 &gpioa 2 +#define RTS5912_GPIO003 &gpioa 3 +#define RTS5912_GPIO004 &gpioa 4 +#define RTS5912_GPIO009 &gpioa 9 +#define RTS5912_GPIO013 &gpioa 13 +#define RTS5912_GPIO014 &gpioa 14 +#define RTS5912_GPIO015 &gpioa 15 +#define RTS5912_GPIO016 &gpiob 0 +#define RTS5912_GPIO017 &gpiob 1 +#define RTS5912_GPIO018 &gpiob 2 +#define RTS5912_GPIO019 &gpiob 3 +#define RTS5912_GPIO020 &gpiob 4 +#define RTS5912_GPIO021 &gpiob 5 +#define RTS5912_GPIO022 &gpiob 6 +#define RTS5912_GPIO023 &gpiob 7 +#define RTS5912_GPIO025 &gpiob 9 +#define RTS5912_GPIO026 &gpiob 10 +#define RTS5912_GPIO027 &gpiob 11 +#define RTS5912_GPIO028 &gpiob 12 +#define RTS5912_GPIO029 &gpiob 13 +#define RTS5912_GPIO030 &gpiob 14 +#define RTS5912_GPIO031 &gpiob 15 +#define RTS5912_GPIO040 &gpioc 8 +#define RTS5912_GPIO041 &gpioc 9 +#define RTS5912_GPIO042 &gpioc 10 +#define RTS5912_GPIO043 &gpioc 11 +#define RTS5912_GPIO044 &gpioc 12 +#define RTS5912_GPIO045 &gpioc 13 +#define RTS5912_GPIO046 &gpioc 14 +#define RTS5912_GPIO047 &gpioc 15 +#define RTS5912_GPIO048 &gpiod 0 +#define RTS5912_GPIO049 &gpiod 1 +#define RTS5912_GPIO050 &gpiod 2 +#define RTS5912_GPIO051 &gpiod 3 +#define RTS5912_GPIO052 &gpiod 4 +#define RTS5912_GPIO053 &gpiod 5 +#define RTS5912_GPIO055 &gpiod 7 +#define RTS5912_GPIO056 &gpiod 8 +#define RTS5912_GPIO057 &gpiod 9 +#define RTS5912_GPIO058 &gpiod 10 +#define RTS5912_GPIO059 &gpiod 11 +#define RTS5912_GPIO060 &gpiod 12 +#define RTS5912_GPIO061 &gpiod 13 +#define RTS5912_GPIO064 &gpioe 0 +#define RTS5912_GPIO065 &gpioe 1 +#define RTS5912_GPIO066 &gpioe 2 +#define RTS5912_GPIO067 &gpioe 3 +#define RTS5912_GPIO068 &gpioe 4 +#define RTS5912_GPIO069 &gpioe 5 +#define RTS5912_GPIO070 &gpioe 6 +#define RTS5912_GPIO071 &gpioe 7 +#define RTS5912_GPIO074 &gpioe 10 +#define RTS5912_GPIO075 &gpioe 11 +#define RTS5912_GPIO076 &gpioe 12 +#define RTS5912_GPIO077 &gpioe 13 +#define RTS5912_GPIO078 &gpioe 14 +#define RTS5912_GPIO079 &gpioe 15 +#define RTS5912_GPIO080 &gpiof 0 +#define RTS5912_GPIO081 &gpiof 1 +#define RTS5912_GPIO083 &gpiof 3 +#define RTS5912_GPIO084 &gpiof 4 +#define RTS5912_GPIO085 &gpiof 5 +#define RTS5912_GPIO086 &gpiof 6 +#define RTS5912_GPIO087 &gpiof 7 +#define RTS5912_GPIO088 &gpiof 8 +#define RTS5912_GPIO089 &gpiof 9 +#define RTS5912_GPIO090 &gpiof 10 +#define RTS5912_GPIO091 &gpiof 11 +#define RTS5912_GPIO092 &gpiof 12 +#define RTS5912_GPIO093 &gpiof 13 +#define RTS5912_GPIO094 &gpiof 14 +#define RTS5912_GPIO095 &gpiof 15 +#define RTS5912_GPIO096 &gpiog 0 +#define RTS5912_GPIO097 &gpiog 1 +#define RTS5912_GPIO099 &gpiog 3 +#define RTS5912_GPIO100 &gpiog 4 +#define RTS5912_GPIO101 &gpiog 5 +#define RTS5912_GPIO102 &gpiog 6 +#define RTS5912_GPIO103 &gpiog 7 +#define RTS5912_GPIO104 &gpiog 8 +#define RTS5912_GPIO105 &gpiog 9 +#define RTS5912_GPIO106 &gpiog 10 +#define RTS5912_GPIO107 &gpiog 11 +#define RTS5912_GPIO108 &gpiog 12 +#define RTS5912_GPIO109 &gpiog 13 +#define RTS5912_GPIO111 &gpiog 15 +#define RTS5912_GPIO112 &gpioh 0 +#define RTS5912_GPIO113 &gpioh 1 +#define RTS5912_GPIO114 &gpioh 2 +#define RTS5912_GPIO115 &gpioh 3 +#define RTS5912_GPIO117 &gpioh 5 +#define RTS5912_GPIO118 &gpioh 6 +#define RTS5912_GPIO119 &gpioh 7 +#define RTS5912_GPIO120 &gpioh 8 +#define RTS5912_GPIO121 &gpioh 9 +#define RTS5912_GPIO122 &gpioh 10 +#define RTS5912_GPIO123 &gpioh 11 +#define RTS5912_GPIO124 &gpioh 12 +#define RTS5912_GPIO125 &gpioh 13 +#define RTS5912_GPIO126 &gpioh 14 +#define RTS5912_GPIO127 &gpioh 15 +#define RTS5912_GPIO128 &gpioi 0 +#define RTS5912_GPIO130 &gpioi 2 +#define RTS5912_GPIO131 &gpioi 3 + +/** @} */ + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/renesas-rtk0eg0019b01002bj.h b/include/zephyr/dt-bindings/gpio/renesas-rtk0eg0019b01002bj.h new file mode 100644 index 0000000000000..e4ccdc6cdb68f --- /dev/null +++ b/include/zephyr/dt-bindings/gpio/renesas-rtk0eg0019b01002bj.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RTK0EG0019B01002BJ_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RTK0EG0019B01002BJ_H_ + +#define RTK0EG0019B01002BJ_CN1_LED_ROW0 13 +#define RTK0EG0019B01002BJ_CN1_LED_ROW1 14 +#define RTK0EG0019B01002BJ_CN1_LED_ROW2 11 +#define RTK0EG0019B01002BJ_CN1_LED_ROW3 12 + +#define RTK0EG0019B01002BJ_CN1_LED_COL0 4 +#define RTK0EG0019B01002BJ_CN1_LED_COL1 5 +#define RTK0EG0019B01002BJ_CN1_LED_COL2 6 +#define RTK0EG0019B01002BJ_CN1_LED_COL3 7 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RTK0EG0019B01002BJ_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/st-morpho-header.h b/include/zephyr/dt-bindings/gpio/st-morpho-header.h index 12f537d8b8d06..2ec335b1d8f44 100644 --- a/include/zephyr/dt-bindings/gpio/st-morpho-header.h +++ b/include/zephyr/dt-bindings/gpio/st-morpho-header.h @@ -2,161 +2,171 @@ * Copyright (c) 2023 Teslabs Engineering S.L. * SPDX-License-Identifier: Apache-2.0 */ + +/** + * @file + * @brief ST Morpho header pin constants + * @ingroup st-morpho-header + */ + #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_ -/** ST Morpho pin mask (0...143). */ -#define ST_MORPHO_PIN_MASK 0xFF - /** - * @name ST Morpho pin identifiers + * @defgroup st-morpho-header ST Morpho header + * @brief Constants for pins exposed on ST Morpho header + * @ingroup devicetree-gpio-pin-headers * @{ */ -#define ST_MORPHO_L_1 0 -#define ST_MORPHO_L_2 1 -#define ST_MORPHO_L_3 2 -#define ST_MORPHO_L_4 3 -#define ST_MORPHO_L_5 4 -#define ST_MORPHO_L_6 5 -#define ST_MORPHO_L_7 6 -#define ST_MORPHO_L_8 7 -#define ST_MORPHO_L_9 8 -#define ST_MORPHO_L_10 9 -#define ST_MORPHO_L_11 10 -#define ST_MORPHO_L_12 11 -#define ST_MORPHO_L_13 12 -#define ST_MORPHO_L_14 13 -#define ST_MORPHO_L_15 14 -#define ST_MORPHO_L_16 15 -#define ST_MORPHO_L_17 16 -#define ST_MORPHO_L_18 17 -#define ST_MORPHO_L_19 18 -#define ST_MORPHO_L_20 19 -#define ST_MORPHO_L_21 20 -#define ST_MORPHO_L_22 21 -#define ST_MORPHO_L_23 22 -#define ST_MORPHO_L_24 23 -#define ST_MORPHO_L_25 24 -#define ST_MORPHO_L_26 25 -#define ST_MORPHO_L_27 26 -#define ST_MORPHO_L_28 27 -#define ST_MORPHO_L_29 28 -#define ST_MORPHO_L_30 29 -#define ST_MORPHO_L_31 30 -#define ST_MORPHO_L_32 31 -#define ST_MORPHO_L_33 32 -#define ST_MORPHO_L_34 33 -#define ST_MORPHO_L_35 34 -#define ST_MORPHO_L_36 35 -#define ST_MORPHO_L_37 36 -#define ST_MORPHO_L_38 37 -#define ST_MORPHO_L_39 38 -#define ST_MORPHO_L_40 39 -#define ST_MORPHO_L_41 40 -#define ST_MORPHO_L_42 41 -#define ST_MORPHO_L_43 42 -#define ST_MORPHO_L_44 43 -#define ST_MORPHO_L_45 44 -#define ST_MORPHO_L_46 45 -#define ST_MORPHO_L_47 46 -#define ST_MORPHO_L_48 47 -#define ST_MORPHO_L_49 48 -#define ST_MORPHO_L_50 49 -#define ST_MORPHO_L_51 50 -#define ST_MORPHO_L_52 51 -#define ST_MORPHO_L_53 52 -#define ST_MORPHO_L_54 53 -#define ST_MORPHO_L_55 54 -#define ST_MORPHO_L_56 55 -#define ST_MORPHO_L_57 56 -#define ST_MORPHO_L_58 57 -#define ST_MORPHO_L_59 58 -#define ST_MORPHO_L_60 59 -#define ST_MORPHO_L_61 60 -#define ST_MORPHO_L_62 61 -#define ST_MORPHO_L_63 62 -#define ST_MORPHO_L_64 63 -#define ST_MORPHO_L_65 64 -#define ST_MORPHO_L_66 65 -#define ST_MORPHO_L_67 66 -#define ST_MORPHO_L_68 67 -#define ST_MORPHO_L_69 68 -#define ST_MORPHO_L_70 69 -#define ST_MORPHO_L_71 70 -#define ST_MORPHO_L_72 71 -#define ST_MORPHO_R_1 72 -#define ST_MORPHO_R_2 73 -#define ST_MORPHO_R_3 74 -#define ST_MORPHO_R_4 75 -#define ST_MORPHO_R_5 76 -#define ST_MORPHO_R_6 77 -#define ST_MORPHO_R_7 78 -#define ST_MORPHO_R_8 79 -#define ST_MORPHO_R_9 80 -#define ST_MORPHO_R_10 81 -#define ST_MORPHO_R_11 82 -#define ST_MORPHO_R_12 83 -#define ST_MORPHO_R_13 84 -#define ST_MORPHO_R_14 85 -#define ST_MORPHO_R_15 86 -#define ST_MORPHO_R_16 87 -#define ST_MORPHO_R_17 88 -#define ST_MORPHO_R_18 89 -#define ST_MORPHO_R_19 90 -#define ST_MORPHO_R_20 91 -#define ST_MORPHO_R_21 92 -#define ST_MORPHO_R_22 93 -#define ST_MORPHO_R_23 94 -#define ST_MORPHO_R_24 95 -#define ST_MORPHO_R_25 96 -#define ST_MORPHO_R_26 97 -#define ST_MORPHO_R_27 98 -#define ST_MORPHO_R_28 99 -#define ST_MORPHO_R_29 100 -#define ST_MORPHO_R_30 101 -#define ST_MORPHO_R_31 102 -#define ST_MORPHO_R_32 103 -#define ST_MORPHO_R_33 104 -#define ST_MORPHO_R_34 105 -#define ST_MORPHO_R_35 106 -#define ST_MORPHO_R_36 107 -#define ST_MORPHO_R_37 108 -#define ST_MORPHO_R_38 109 -#define ST_MORPHO_R_39 110 -#define ST_MORPHO_R_40 111 -#define ST_MORPHO_R_41 112 -#define ST_MORPHO_R_42 113 -#define ST_MORPHO_R_43 114 -#define ST_MORPHO_R_44 115 -#define ST_MORPHO_R_45 116 -#define ST_MORPHO_R_46 117 -#define ST_MORPHO_R_47 118 -#define ST_MORPHO_R_48 119 -#define ST_MORPHO_R_49 120 -#define ST_MORPHO_R_50 121 -#define ST_MORPHO_R_51 122 -#define ST_MORPHO_R_52 123 -#define ST_MORPHO_R_53 124 -#define ST_MORPHO_R_54 125 -#define ST_MORPHO_R_55 126 -#define ST_MORPHO_R_56 127 -#define ST_MORPHO_R_57 128 -#define ST_MORPHO_R_58 129 -#define ST_MORPHO_R_59 130 -#define ST_MORPHO_R_60 131 -#define ST_MORPHO_R_61 132 -#define ST_MORPHO_R_62 133 -#define ST_MORPHO_R_63 134 -#define ST_MORPHO_R_64 135 -#define ST_MORPHO_R_65 136 -#define ST_MORPHO_R_66 137 -#define ST_MORPHO_R_67 138 -#define ST_MORPHO_R_68 139 -#define ST_MORPHO_R_69 140 -#define ST_MORPHO_R_70 141 -#define ST_MORPHO_R_71 142 -#define ST_MORPHO_R_72 143 +/** ST Morpho pin mask (0...143). */ +#define ST_MORPHO_PIN_MASK 0xFF + +#define ST_MORPHO_L_1 0 /**< Left pin 1 */ +#define ST_MORPHO_L_2 1 /**< Left pin 2 */ +#define ST_MORPHO_L_3 2 /**< Left pin 3 */ +#define ST_MORPHO_L_4 3 /**< Left pin 4 */ +#define ST_MORPHO_L_5 4 /**< Left pin 5 */ +#define ST_MORPHO_L_6 5 /**< Left pin 6 */ +#define ST_MORPHO_L_7 6 /**< Left pin 7 */ +#define ST_MORPHO_L_8 7 /**< Left pin 8 */ +#define ST_MORPHO_L_9 8 /**< Left pin 9 */ +#define ST_MORPHO_L_10 9 /**< Left pin 10 */ +#define ST_MORPHO_L_11 10 /**< Left pin 11 */ +#define ST_MORPHO_L_12 11 /**< Left pin 12 */ +#define ST_MORPHO_L_13 12 /**< Left pin 13 */ +#define ST_MORPHO_L_14 13 /**< Left pin 14 */ +#define ST_MORPHO_L_15 14 /**< Left pin 15 */ +#define ST_MORPHO_L_16 15 /**< Left pin 16 */ +#define ST_MORPHO_L_17 16 /**< Left pin 17 */ +#define ST_MORPHO_L_18 17 /**< Left pin 18 */ +#define ST_MORPHO_L_19 18 /**< Left pin 19 */ +#define ST_MORPHO_L_20 19 /**< Left pin 20 */ +#define ST_MORPHO_L_21 20 /**< Left pin 21 */ +#define ST_MORPHO_L_22 21 /**< Left pin 22 */ +#define ST_MORPHO_L_23 22 /**< Left pin 23 */ +#define ST_MORPHO_L_24 23 /**< Left pin 24 */ +#define ST_MORPHO_L_25 24 /**< Left pin 25 */ +#define ST_MORPHO_L_26 25 /**< Left pin 26 */ +#define ST_MORPHO_L_27 26 /**< Left pin 27 */ +#define ST_MORPHO_L_28 27 /**< Left pin 28 */ +#define ST_MORPHO_L_29 28 /**< Left pin 29 */ +#define ST_MORPHO_L_30 29 /**< Left pin 30 */ +#define ST_MORPHO_L_31 30 /**< Left pin 31 */ +#define ST_MORPHO_L_32 31 /**< Left pin 32 */ +#define ST_MORPHO_L_33 32 /**< Left pin 33 */ +#define ST_MORPHO_L_34 33 /**< Left pin 34 */ +#define ST_MORPHO_L_35 34 /**< Left pin 35 */ +#define ST_MORPHO_L_36 35 /**< Left pin 36 */ +#define ST_MORPHO_L_37 36 /**< Left pin 37 */ +#define ST_MORPHO_L_38 37 /**< Left pin 38 */ +#define ST_MORPHO_L_39 38 /**< Left pin 39 */ +#define ST_MORPHO_L_40 39 /**< Left pin 40 */ +#define ST_MORPHO_L_41 40 /**< Left pin 41 */ +#define ST_MORPHO_L_42 41 /**< Left pin 42 */ +#define ST_MORPHO_L_43 42 /**< Left pin 43 */ +#define ST_MORPHO_L_44 43 /**< Left pin 44 */ +#define ST_MORPHO_L_45 44 /**< Left pin 45 */ +#define ST_MORPHO_L_46 45 /**< Left pin 46 */ +#define ST_MORPHO_L_47 46 /**< Left pin 47 */ +#define ST_MORPHO_L_48 47 /**< Left pin 48 */ +#define ST_MORPHO_L_49 48 /**< Left pin 49 */ +#define ST_MORPHO_L_50 49 /**< Left pin 50 */ +#define ST_MORPHO_L_51 50 /**< Left pin 51 */ +#define ST_MORPHO_L_52 51 /**< Left pin 52 */ +#define ST_MORPHO_L_53 52 /**< Left pin 53 */ +#define ST_MORPHO_L_54 53 /**< Left pin 54 */ +#define ST_MORPHO_L_55 54 /**< Left pin 55 */ +#define ST_MORPHO_L_56 55 /**< Left pin 56 */ +#define ST_MORPHO_L_57 56 /**< Left pin 57 */ +#define ST_MORPHO_L_58 57 /**< Left pin 58 */ +#define ST_MORPHO_L_59 58 /**< Left pin 59 */ +#define ST_MORPHO_L_60 59 /**< Left pin 60 */ +#define ST_MORPHO_L_61 60 /**< Left pin 61 */ +#define ST_MORPHO_L_62 61 /**< Left pin 62 */ +#define ST_MORPHO_L_63 62 /**< Left pin 63 */ +#define ST_MORPHO_L_64 63 /**< Left pin 64 */ +#define ST_MORPHO_L_65 64 /**< Left pin 65 */ +#define ST_MORPHO_L_66 65 /**< Left pin 66 */ +#define ST_MORPHO_L_67 66 /**< Left pin 67 */ +#define ST_MORPHO_L_68 67 /**< Left pin 68 */ +#define ST_MORPHO_L_69 68 /**< Left pin 69 */ +#define ST_MORPHO_L_70 69 /**< Left pin 70 */ +#define ST_MORPHO_L_71 70 /**< Left pin 71 */ +#define ST_MORPHO_L_72 71 /**< Left pin 72 */ + +#define ST_MORPHO_R_1 72 /**< Right pin 1 */ +#define ST_MORPHO_R_2 73 /**< Right pin 2 */ +#define ST_MORPHO_R_3 74 /**< Right pin 3 */ +#define ST_MORPHO_R_4 75 /**< Right pin 4 */ +#define ST_MORPHO_R_5 76 /**< Right pin 5 */ +#define ST_MORPHO_R_6 77 /**< Right pin 6 */ +#define ST_MORPHO_R_7 78 /**< Right pin 7 */ +#define ST_MORPHO_R_8 79 /**< Right pin 8 */ +#define ST_MORPHO_R_9 80 /**< Right pin 9 */ +#define ST_MORPHO_R_10 81 /**< Right pin 10 */ +#define ST_MORPHO_R_11 82 /**< Right pin 11 */ +#define ST_MORPHO_R_12 83 /**< Right pin 12 */ +#define ST_MORPHO_R_13 84 /**< Right pin 13 */ +#define ST_MORPHO_R_14 85 /**< Right pin 14 */ +#define ST_MORPHO_R_15 86 /**< Right pin 15 */ +#define ST_MORPHO_R_16 87 /**< Right pin 16 */ +#define ST_MORPHO_R_17 88 /**< Right pin 17 */ +#define ST_MORPHO_R_18 89 /**< Right pin 18 */ +#define ST_MORPHO_R_19 90 /**< Right pin 19 */ +#define ST_MORPHO_R_20 91 /**< Right pin 20 */ +#define ST_MORPHO_R_21 92 /**< Right pin 21 */ +#define ST_MORPHO_R_22 93 /**< Right pin 22 */ +#define ST_MORPHO_R_23 94 /**< Right pin 23 */ +#define ST_MORPHO_R_24 95 /**< Right pin 24 */ +#define ST_MORPHO_R_25 96 /**< Right pin 25 */ +#define ST_MORPHO_R_26 97 /**< Right pin 26 */ +#define ST_MORPHO_R_27 98 /**< Right pin 27 */ +#define ST_MORPHO_R_28 99 /**< Right pin 28 */ +#define ST_MORPHO_R_29 100 /**< Right pin 29 */ +#define ST_MORPHO_R_30 101 /**< Right pin 30 */ +#define ST_MORPHO_R_31 102 /**< Right pin 31 */ +#define ST_MORPHO_R_32 103 /**< Right pin 32 */ +#define ST_MORPHO_R_33 104 /**< Right pin 33 */ +#define ST_MORPHO_R_34 105 /**< Right pin 34 */ +#define ST_MORPHO_R_35 106 /**< Right pin 35 */ +#define ST_MORPHO_R_36 107 /**< Right pin 36 */ +#define ST_MORPHO_R_37 108 /**< Right pin 37 */ +#define ST_MORPHO_R_38 109 /**< Right pin 38 */ +#define ST_MORPHO_R_39 110 /**< Right pin 39 */ +#define ST_MORPHO_R_40 111 /**< Right pin 40 */ +#define ST_MORPHO_R_41 112 /**< Right pin 41 */ +#define ST_MORPHO_R_42 113 /**< Right pin 42 */ +#define ST_MORPHO_R_43 114 /**< Right pin 43 */ +#define ST_MORPHO_R_44 115 /**< Right pin 44 */ +#define ST_MORPHO_R_45 116 /**< Right pin 45 */ +#define ST_MORPHO_R_46 117 /**< Right pin 46 */ +#define ST_MORPHO_R_47 118 /**< Right pin 47 */ +#define ST_MORPHO_R_48 119 /**< Right pin 48 */ +#define ST_MORPHO_R_49 120 /**< Right pin 49 */ +#define ST_MORPHO_R_50 121 /**< Right pin 50 */ +#define ST_MORPHO_R_51 122 /**< Right pin 51 */ +#define ST_MORPHO_R_52 123 /**< Right pin 52 */ +#define ST_MORPHO_R_53 124 /**< Right pin 53 */ +#define ST_MORPHO_R_54 125 /**< Right pin 54 */ +#define ST_MORPHO_R_55 126 /**< Right pin 55 */ +#define ST_MORPHO_R_56 127 /**< Right pin 56 */ +#define ST_MORPHO_R_57 128 /**< Right pin 57 */ +#define ST_MORPHO_R_58 129 /**< Right pin 58 */ +#define ST_MORPHO_R_59 130 /**< Right pin 59 */ +#define ST_MORPHO_R_60 131 /**< Right pin 60 */ +#define ST_MORPHO_R_61 132 /**< Right pin 61 */ +#define ST_MORPHO_R_62 133 /**< Right pin 62 */ +#define ST_MORPHO_R_63 134 /**< Right pin 63 */ +#define ST_MORPHO_R_64 135 /**< Right pin 64 */ +#define ST_MORPHO_R_65 136 /**< Right pin 65 */ +#define ST_MORPHO_R_66 137 /**< Right pin 66 */ +#define ST_MORPHO_R_67 138 /**< Right pin 67 */ +#define ST_MORPHO_R_68 139 /**< Right pin 68 */ +#define ST_MORPHO_R_69 140 /**< Right pin 69 */ +#define ST_MORPHO_R_70 141 /**< Right pin 70 */ +#define ST_MORPHO_R_71 142 /**< Right pin 71 */ +#define ST_MORPHO_R_72 143 /**< Right pin 72 */ /** @} */ diff --git a/include/zephyr/dt-bindings/input/input-event-codes.h b/include/zephyr/dt-bindings/input/input-event-codes.h index 108691dbba442..1b2562cdd2946 100644 --- a/include/zephyr/dt-bindings/input/input-event-codes.h +++ b/include/zephyr/dt-bindings/input/input-event-codes.h @@ -206,8 +206,8 @@ #define INPUT_BTN_EAST 0x131 /**< East button */ #define INPUT_BTN_EXTRA 0x114 /**< Extra button */ #define INPUT_BTN_FORWARD 0x115 /**< Forward button */ -#define INPUT_BTN_GEAR_DOWN 0x150 /**< Gear Up button */ -#define INPUT_BTN_GEAR_UP 0x151 /**< Gear Down button */ +#define INPUT_BTN_GEAR_DOWN 0x150 /**< Gear Down button */ +#define INPUT_BTN_GEAR_UP 0x151 /**< Gear Up button */ #define INPUT_BTN_LEFT 0x110 /**< Left button */ #define INPUT_BTN_MIDDLE 0x112 /**< Middle button */ #define INPUT_BTN_MODE 0x13c /**< Mode button */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32h2-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32h2-intmux.h new file mode 100644 index 0000000000000..febe62c3ce060 --- /dev/null +++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32h2-intmux.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_ + +#define PMU_INTR_SOURCE 0 +#define EFUSE_INTR_SOURCE 1 +#define LP_RTC_TIMER_INTR_SOURCE 2 +#define LP_BLE_TIMER_INTR_SOURCE 3 +#define LP_WDT_INTR_SOURCE 4 +#define LP_PERI_TIMEOUT_INTR_SOURCE 5 +#define LP_APM_M0_INTR_SOURCE 6 +#define FROM_CPU_INTR0_SOURCE 7 +#define FROM_CPU_INTR1_SOURCE 8 +#define FROM_CPU_INTR2_SOURCE 9 +#define FROM_CPU_INTR3_SOURCE 10 +#define ASSIST_DEBUG_INTR_SOURCE 11 +#define TRACE_INTR_SOURCE 12 +#define CACHE_INTR_SOURCE 13 +#define CPU_PERI_TIMEOUT_INTR_SOURCE 14 +#define BT_MAC_INTR_SOURCE 15 +#define BT_BB_INTR_SOURCE 16 +#define BT_BB_NMI_INTR_SOURCE 17 +#define COEX_INTR_SOURCE 18 +#define BLE_TIMER_INTR_SOURCE 19 +#define BLE_SEC_INTR_SOURCE 20 +#define ZB_MAC_INTR_SOURCE 21 +#define GPIO_INTR_SOURCE 22 +#define GPIO_NMI_SOURCE 23 +#define PAU_INTR_SOURCE 24 +#define HP_PERI_TIMEOUT_INTR_SOURCE 25 +#define HP_APM_M0_INTR_SOURCE 26 +#define HP_APM_M1_INTR_SOURCE 27 +#define HP_APM_M2_INTR_SOURCE 28 +#define HP_APM_M3_INTR_SOURCE 29 +#define MSPI_INTR_SOURCE 30 +#define I2S1_INTR_SOURCE 31 +#define UHCI0_INTR_SOURCE 32 +#define UART0_INTR_SOURCE 33 +#define UART1_INTR_SOURCE 34 +#define LEDC_INTR_SOURCE 35 +#define TWAI0_INTR_SOURCE 36 +#define USB_SERIAL_JTAG_INTR_SOURCE 37 +#define RMT_INTR_SOURCE 38 +#define I2C_EXT0_INTR_SOURCE 39 +#define I2C_EXT1_INTR_SOURCE 40 +#define TG0_T0_LEVEL_INTR_SOURCE 41 +#define TG0_WDT_LEVEL_INTR_SOURCE 42 +#define TG1_T0_LEVEL_INTR_SOURCE 43 +#define TG1_WDT_LEVEL_INTR_SOURCE 44 +#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 45 +#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 46 +#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 47 +#define APB_ADC_INTR_SOURCE 48 +#define MCPWM0_INTR_SOURCE 49 +#define PCNT_INTR_SOURCE 50 +#define PARL_IO_TX_INTR_SOURCE 51 +#define PARL_IO_RX_INTR_SOURCE 52 +#define DMA_IN_CH0_INTR_SOURCE 53 +#define DMA_IN_CH1_INTR_SOURCE 54 +#define DMA_IN_CH2_INTR_SOURCE 55 +#define DMA_OUT_CH0_INTR_SOURCE 56 +#define DMA_OUT_CH1_INTR_SOURCE 57 +#define DMA_OUT_CH2_INTR_SOURCE 58 +#define GSPI2_INTR_SOURCE 59 +#define AES_INTR_SOURCE 60 +#define SHA_INTR_SOURCE 61 +#define RSA_INTR_SOURCE 62 +#define ECC_INTR_SOURCE 63 +#define ECDSA_INTR_SOURCE 64 +#define MAX_INTR_SOURCE 65 + +/* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */ +#define IRQ_DEFAULT_PRIORITY 0 + +#define ESP_INTR_FLAG_SHARED (1 << 8) /* Interrupt can be shared between ISRs */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_ */ diff --git a/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h b/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h index b767b1804d291..a83ba669d3883 100644 --- a/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h +++ b/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h @@ -8,9 +8,7 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_ /** - * @brief MIPI-DBI driver APIs - * @defgroup mipi_dbi_interface MIPI-DBI driver APIs - * @ingroup io_interfaces + * @addtogroup mipi_dbi_interface * @{ */ @@ -54,7 +52,7 @@ */ #define MIPI_DBI_MODE_SPI_4WIRE 0x2 /** - * Parallel Bus protocol for MIPI DBI Type A based on Motorola 6800 bus. + * @name Parallel Bus protocol for MIPI DBI Type A based on Motorola 6800 bus. * * -. .--------. .------------------------ * CS '---' '---' @@ -77,12 +75,15 @@ * D[7:0] * * Please refer to the MIPI DBI specification for a detailed cycle diagram. + * + * @{ */ -#define MIPI_DBI_MODE_6800_BUS_16_BIT 0x3 -#define MIPI_DBI_MODE_6800_BUS_9_BIT 0x4 -#define MIPI_DBI_MODE_6800_BUS_8_BIT 0x5 +#define MIPI_DBI_MODE_6800_BUS_16_BIT 0x3 /**< Motorola 6800 parallel bus, 16-bit width */ +#define MIPI_DBI_MODE_6800_BUS_9_BIT 0x4 /**< Motorola 6800 parallel bus, 9-bit width */ +#define MIPI_DBI_MODE_6800_BUS_8_BIT 0x5 /**< Motorola 6800 parallel bus, 8-bit width */ +/** @} */ /** - * Parallel Bus protocol for MIPI DBI Type B based on Intel 8080 bus. + * @name Parallel Bus protocol for MIPI DBI Type B based on Intel 8080 bus. * * -. .- * CS '---------------------------------------' @@ -105,58 +106,78 @@ * D[7:0] * * Please refer to the MIPI DBI specification for a detailed cycle diagram. + * @{ */ -#define MIPI_DBI_MODE_8080_BUS_16_BIT 0x6 -#define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7 -#define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8 +#define MIPI_DBI_MODE_8080_BUS_16_BIT 0x6 /**< Intel 8080 parallel bus, 16-bit width */ +#define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7 /**< Intel 8080 parallel bus, 9-bit width */ +#define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8 /**< Intel 8080 parallel bus, 8-bit width */ +/** @} */ -/** Color coding for MIPI DBI Type A or Type B interface. */ /** - * For 8-bit data bus width, 1 pixel is sent in 1 cycle. For 16-bit data bus width, - * 2 pixels are sent in 1 cycle. + * @name Color coding for MIPI DBI Type A or Type B interface. + * @{ + */ +/** + * RGB332 (8 bpp). + * + * - For 8-bit data bus width, 1 pixel is sent in 1 cycle. + * - For 16-bit data bus width, 2 pixels are sent in 1 cycle. */ #define MIPI_DBI_MODE_RGB332 (0x1 << 4U) /** - * For 8-bit data bus width, 2 pixels are sent in 3 cycles. For 16-bit data bus width, - * 1 pixel is sent in 1 cycle, the high 4 bits are not used. + * RGB444 (12 bpp). + * + * - For 8-bit data bus width, 2 pixels are sent in 3 cycles. + * - For 16-bit data bus width, 1 pixel is sent in 1 cycle, the high 4 bits are not used. */ #define MIPI_DBI_MODE_RGB444 (0x2 << 4U) /** - * For 8-bit data bus width, 1 pixel is sent in 2 cycles. For 16-bit data bus width, - * 1 pixel is sent in 1 cycle. + * RGB565 (16 bpp). + * + * - For 8-bit data bus width, 1 pixel is sent in 2 cycles. + * - For 16-bit data bus width, 1 pixel is sent in 1 cycle. */ #define MIPI_DBI_MODE_RGB565 (0x3 << 4U) /** - * For 8-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2 - * are the same. 1 pixel is sent in 3 cycles, R component first, and the low 2 - * bits are not used. - * For 9-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2 - * are the same. 1 pixel is sent in 2 cycles. - * For 16-bit data bus width, MIPI_DBI_MODE_RGB666_1 is option 1, - * 2 pixels are sent in 3 cycles. The first pixel's R/G/B components are sent in - * cycle 1 bits 10-15, cycle 1 bits 2-7 and cycle 2 bits 10-15. - * The second pixel's R/G/B components are sent in cycle 2 bits 2-7, cycle 3 bits - * 10-15 and cycle 3 bits 2-7. - * MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's - * R/G/B components are sent in cycle 1 bits 2-7, cycle 2 bits 10-15 and cycle 2 - * bits 2-7. + * RGB666 (18 bpp). + * + * - For 8-bit data bus width, #MIPI_DBI_MODE_RGB666_1 and #MIPI_DBI_MODE_RGB666_2 are the same. + * 1 pixel is sent in 3 cycles, R component first, and the low 2 bits are not used. + * - For 9-bit data bus width, #MIPI_DBI_MODE_RGB666_1 and #MIPI_DBI_MODE_RGB666_2 are the same. + * 1 pixel is sent in 2 cycles. + * - For 16-bit data bus width, #MIPI_DBI_MODE_RGB666_1 is option 1, 2 pixels are sent in 3 cycles. + * The first pixel's R/G/B components are sent in cycle 1 bits 10-15, cycle 1 bits 2-7 and cycle + * 2 bits 10-15. The second pixel's R/G/B components are sent in cycle 2 bits 2-7, cycle 3 bits + * 10-15 and cycle 3 bits 2-7. #MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. + * The pixel's R/G/B components are sent in cycle 1 bits 2-7, cycle 2 bits 10-15 and cycle 2 bits + * 2-7. */ #define MIPI_DBI_MODE_RGB666_1 (0x4 << 4U) +/** + * RGB666 (18 bpp). + * + * @see MIPI_DBI_MODE_RGB666_1 + */ #define MIPI_DBI_MODE_RGB666_2 (0x5 << 4U) /** - * For 8-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2 - * are the same. 1 pixel is sent in 3 cycles, R component first. - * For 16-bit data bus width, MIPI_DBI_MODE_RGB666_1 is option 1, - * 2 pixels are sent in 3 cycles. The first pixel's R/G/B components are sent in - * cycle 1 bits 8-15, cycle 1 bits 0-7 and cycle 2 bits 0-15. - * The second pixel's R/G/B components are sent in cycle 2 bits 0-7, cycle 3 bits - * 8-15 and cycle 3 bits 0-7. - * MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's - * R/G/B components are sent in cycle 1 bits 0-7, cycle 2 bits 8-15 and cycle 2 - * bits 0-7. + * RGB666 (18 bpp). + * + * - For 8-bit data bus width, #MIPI_DBI_MODE_RGB666_1 and #MIPI_DBI_MODE_RGB666_2 are the same. + * 1 pixel is sent in 3 cycles, R component first. + * - For 16-bit data bus width, #MIPI_DBI_MODE_RGB666_1 is option 1, 2 pixels are sent in 3 cycles. + * The first pixel's R/G/B components are sent in cycle 1 bits 8-15, cycle 1 bits 0-7 and cycle 2 + * bits 0-15. The second pixel's R/G/B components are sent in cycle 2 bits 0-7, cycle 3 bits 8-15 + * and cycle 3 bits 0-7. + * #MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's R/G/B components + * are sent in cycle 1 bits 0-7, cycle 2 bits 8-15 and cycle 2 bits 0-7. */ #define MIPI_DBI_MODE_RGB888_1 (0x6 << 4U) +/** + * RGB888 (24 bpp). + * @see MIPI_DBI_MODE_RGB888_1 + */ #define MIPI_DBI_MODE_RGB888_2 (0x7 << 4U) +/** @} */ /** MIPI DBI tearing enable synchronization is disabled. */ #define MIPI_DBI_TE_NO_EDGE 0x0 diff --git a/include/zephyr/dt-bindings/mipi_dsi/mipi_dsi.h b/include/zephyr/dt-bindings/mipi_dsi/mipi_dsi.h index e94469d0349a0..58cd67e869527 100644 --- a/include/zephyr/dt-bindings/mipi_dsi/mipi_dsi.h +++ b/include/zephyr/dt-bindings/mipi_dsi/mipi_dsi.h @@ -8,9 +8,7 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_ /** - * @brief MIPI-DSI driver APIs - * @defgroup mipi_dsi_interface MIPI-DSI driver APIs - * @ingroup io_interfaces + * @addtogroup mipi_dsi_interface * @{ */ diff --git a/include/zephyr/dt-bindings/pinctrl/esp32h2-gpio-sigmap.h b/include/zephyr/dt-bindings/pinctrl/esp32h2-gpio-sigmap.h new file mode 100644 index 0000000000000..f27fbeab0c8cc --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/esp32h2-gpio-sigmap.h @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32H2_GPIO_SIGMAP_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32H2_GPIO_SIGMAP_H_ + +#define ESP_NOSIG ESP_SIG_INVAL + +#define ESP_EXT_ADC_START 0 +#define ESP_LEDC_LS_SIG_OUT0 0 +#define ESP_MODEM_DIAG0 0 +#define ESP_LEDC_LS_SIG_OUT1 1 +#define ESP_MODEM_DIAG1 1 +#define ESP_LEDC_LS_SIG_OUT2 2 +#define ESP_MODEM_DIAG2 2 +#define ESP_LEDC_LS_SIG_OUT3 3 +#define ESP_MODEM_DIAG3 3 +#define ESP_LEDC_LS_SIG_OUT4 4 +#define ESP_MODEM_DIAG4 4 +#define ESP_LEDC_LS_SIG_OUT5 5 +#define ESP_MODEM_DIAG5 5 +#define ESP_U0RXD_IN 6 +#define ESP_U0TXD_OUT 6 +#define ESP_U0CTS_IN 7 +#define ESP_U0RTS_OUT 7 +#define ESP_U0DSR_IN 8 +#define ESP_U0DTR_OUT 8 +#define ESP_U1RXD_IN 9 +#define ESP_U1TXD_OUT 9 +#define ESP_U1CTS_IN 10 +#define ESP_U1RTS_OUT 10 +#define ESP_MODEM_DIAG6 10 +#define ESP_U1DSR_IN 11 +#define ESP_U1DTR_OUT 11 +#define ESP_I2S_MCLK_IN 12 +#define ESP_I2S_MCLK_OUT 12 +#define ESP_I2SO_BCK_IN 13 +#define ESP_I2SO_BCK_OUT 13 +#define ESP_I2SO_WS_IN 14 +#define ESP_I2SO_WS_OUT 14 +#define ESP_I2SI_SD_IN 15 +#define ESP_I2SO_SD_OUT 15 +#define ESP_I2SI_BCK_IN 16 +#define ESP_I2SI_BCK_OUT 16 +#define ESP_I2SI_WS_IN 17 +#define ESP_I2SI_WS_OUT 17 +#define ESP_I2SO_SD1_OUT 18 +#define ESP_USB_JTAG_TDO_BRIDGE 19 +#define ESP_USB_JTAG_TRST 19 +#define ESP_CPU_TESTBUS0 20 +#define ESP_CPU_TESTBUS1 21 +#define ESP_CPU_TESTBUS2 22 +#define ESP_CPU_TESTBUS3 23 +#define ESP_CPU_TESTBUS4 24 +#define ESP_CPU_TESTBUS5 25 +#define ESP_CPU_TESTBUS6 26 +#define ESP_CPU_TESTBUS7 27 +#define ESP_CPU_GPIO_IN0 28 +#define ESP_CPU_GPIO_OUT0 28 +#define ESP_CPU_GPIO_IN1 29 +#define ESP_CPU_GPIO_OUT1 29 +#define ESP_CPU_GPIO_IN2 30 +#define ESP_CPU_GPIO_OUT2 30 +#define ESP_CPU_GPIO_IN3 31 +#define ESP_CPU_GPIO_OUT3 31 +#define ESP_CPU_GPIO_IN4 32 +#define ESP_CPU_GPIO_OUT4 32 +#define ESP_CPU_GPIO_IN5 33 +#define ESP_CPU_GPIO_OUT5 33 +#define ESP_CPU_GPIO_IN6 34 +#define ESP_CPU_GPIO_OUT6 34 +#define ESP_CPU_GPIO_IN7 35 +#define ESP_CPU_GPIO_OUT7 35 +#define ESP_USB_JTAG_TCK 36 +#define ESP_USB_JTAG_TMS 37 +#define ESP_USB_JTAG_TDI 38 +#define ESP_USB_JTAG_TDO 39 +#define ESP_USB_EXTPHY_VP 40 +#define ESP_USB_EXTPHY_OEN 40 +#define ESP_USB_EXTPHY_VM 41 +#define ESP_USB_EXTPHY_SPEED 41 +#define ESP_USB_EXTPHY_RCV 42 +#define ESP_USB_EXTPHY_VPO 42 +#define ESP_USB_EXTPHY_VMO 43 +#define ESP_USB_EXTPHY_SUSPND 44 +#define ESP_I2CEXT0_SCL_IN 45 +#define ESP_I2CEXT0_SCL_OUT 45 +#define ESP_I2CEXT0_SDA_IN 46 +#define ESP_I2CEXT0_SDA_OUT 46 +#define ESP_PARL_RX_DATA0 47 +#define ESP_PARL_TX_DATA0 47 +#define ESP_PARL_RX_DATA1 48 +#define ESP_PARL_TX_DATA1 48 +#define ESP_PARL_RX_DATA2 49 +#define ESP_PARL_TX_DATA2 49 +#define ESP_PARL_RX_DATA3 50 +#define ESP_PARL_TX_DATA3 50 +#define ESP_PARL_RX_DATA4 51 +#define ESP_PARL_TX_DATA4 51 +#define ESP_PARL_RX_DATA5 52 +#define ESP_PARL_TX_DATA5 52 +#define ESP_PARL_RX_DATA6 53 +#define ESP_PARL_TX_DATA6 53 +#define ESP_PARL_RX_DATA7 54 +#define ESP_PARL_TX_DATA7 54 +#define ESP_I2CEXT1_SCL_IN 55 +#define ESP_I2CEXT1_SCL_OUT 55 +#define ESP_I2CEXT1_SDA_IN 56 +#define ESP_I2CEXT1_SDA_OUT 56 +#define ESP_CTE_ANT0 57 +#define ESP_CTE_ANT1 58 +#define ESP_CTE_ANT2 59 +#define ESP_CTE_ANT3 60 +#define ESP_CTE_ANT4 61 +#define ESP_CTE_ANT5 62 +#define ESP_FSPICLK_IN 63 +#define ESP_FSPICLK_OUT 63 +#define ESP_FSPIQ_IN 64 +#define ESP_FSPIQ_OUT 64 +#define ESP_FSPID_IN 65 +#define ESP_FSPID_OUT 65 +#define ESP_FSPIHD_IN 66 +#define ESP_FSPIHD_OUT 66 +#define ESP_FSPIWP_IN 67 +#define ESP_FSPIWP_OUT 67 +#define ESP_FSPICS0_IN 68 +#define ESP_FSPICS0_OUT 68 +#define ESP_MODEM_DIAG7 68 +#define ESP_PARL_RX_CLK_IN 69 +#define ESP_PARL_RX_CLK_OUT 69 +#define ESP_PARL_TX_CLK_IN 70 +#define ESP_PARL_TX_CLK_OUT 70 +#define ESP_RMT_SIG_IN0 71 +#define ESP_RMT_SIG_OUT0 71 +#define ESP_MODEM_DIAG8 71 +#define ESP_RMT_SIG_IN1 72 +#define ESP_RMT_SIG_OUT1 72 +#define ESP_MODEM_DIAG9 72 +#define ESP_TWAI_RX 73 +#define ESP_TWAI_TX 73 +#define ESP_MODEM_DIAG10 73 +#define ESP_TWAI_BUS_OFF_ON 74 +#define ESP_MODEM_DIAG11 74 +#define ESP_TWAI_CLKOUT 75 +#define ESP_MODEM_DIAG12 75 +#define ESP_TWAI_STANDBY 76 +#define ESP_MODEM_DIAG13 76 +#define ESP_CTE_ANT6 77 +#define ESP_CTE_ANT7 78 +#define ESP_CTE_ANT8 79 +#define ESP_CTE_ANT9 80 +#define ESP_EXTERN_PRIORITY_I 81 +#define ESP_EXTERN_PRIORITY_O 81 +#define ESP_EXTERN_ACTIVE_I 82 +#define ESP_EXTERN_ACTIVE_O 82 +#define ESP_GPIO_SD0_OUT 83 +#define ESP_GPIO_SD1_OUT 84 +#define ESP_GPIO_SD2_OUT 85 +#define ESP_GPIO_SD3_OUT 86 +#define ESP_PWM0_SYNC0_IN 87 +#define ESP_PWM0_OUT0A 87 +#define ESP_MODEM_DIAG14 87 +#define ESP_PWM0_SYNC1_IN 88 +#define ESP_PWM0_OUT0B 88 +#define ESP_MODEM_DIAG15 88 +#define ESP_PWM0_SYNC2_IN 89 +#define ESP_PWM0_OUT1A 89 +#define ESP_MODEM_DIAG16 89 +#define ESP_PWM0_F0_IN 90 +#define ESP_PWM0_OUT1B 90 +#define ESP_MODEM_DIAG17 90 +#define ESP_PWM0_F1_IN 91 +#define ESP_PWM0_OUT2A 91 +#define ESP_MODEM_DIAG18 91 +#define ESP_PWM0_F2_IN 92 +#define ESP_PWM0_OUT2B 92 +#define ESP_MODEM_DIAG19 92 +#define ESP_PWM0_CAP0_IN 93 +#define ESP_ANT_SEL0 93 +#define ESP_PWM0_CAP1_IN 94 +#define ESP_ANT_SEL1 94 +#define ESP_PWM0_CAP2_IN 95 +#define ESP_ANT_SEL2 95 +#define ESP_ANT_SEL3 96 +#define ESP_SIG_IN_FUNC_97 97 +#define ESP_SIG_IN_FUNC97 97 +#define ESP_SIG_IN_FUNC_98 98 +#define ESP_SIG_IN_FUNC98 98 +#define ESP_SIG_IN_FUNC_99 99 +#define ESP_SIG_IN_FUNC99 99 +#define ESP_SIG_IN_FUNC_100 100 +#define ESP_SIG_IN_FUNC100 100 +#define ESP_PCNT_SIG_CH0_IN0 101 +#define ESP_FSPICS1_OUT 101 +#define ESP_MODEM_DIAG20 101 +#define ESP_PCNT_SIG_CH1_IN0 102 +#define ESP_FSPICS2_OUT 102 +#define ESP_MODEM_DIAG21 102 +#define ESP_PCNT_CTRL_CH0_IN0 103 +#define ESP_FSPICS3_OUT 103 +#define ESP_MODEM_DIAG22 103 +#define ESP_PCNT_CTRL_CH1_IN0 104 +#define ESP_FSPICS4_OUT 104 +#define ESP_MODEM_DIAG23 104 +#define ESP_PCNT_SIG_CH0_IN1 105 +#define ESP_FSPICS5_OUT 105 +#define ESP_MODEM_DIAG24 105 +#define ESP_PCNT_SIG_CH1_IN1 106 +#define ESP_CTE_ANT10 106 +#define ESP_PCNT_CTRL_CH0_IN1 107 +#define ESP_CTE_ANT11 107 +#define ESP_PCNT_CTRL_CH1_IN1 108 +#define ESP_CTE_ANT12 108 +#define ESP_PCNT_SIG_CH0_IN2 109 +#define ESP_CTE_ANT13 109 +#define ESP_PCNT_SIG_CH1_IN2 110 +#define ESP_CTE_ANT14 110 +#define ESP_PCNT_CTRL_CH0_IN2 111 +#define ESP_CTE_ANT15 111 +#define ESP_PCNT_CTRL_CH1_IN2 112 +#define ESP_MODEM_DIAG25 112 +#define ESP_PCNT_SIG_CH0_IN3 113 +#define ESP_MODEM_DIAG26 113 +#define ESP_PCNT_SIG_CH1_IN3 114 +#define ESP_SPICLK_OUT 114 +#define ESP_PCNT_CTRL_CH0_IN3 115 +#define ESP_SPICS0_OUT 115 +#define ESP_MODEM_DIAG27 115 +#define ESP_PCNT_CTRL_CH1_IN3 116 +#define ESP_SPICS1_OUT 116 +#define ESP_MODEM_DIAG28 116 +#define ESP_GPIO_EVENT_MATRIX_IN0 117 +#define ESP_GPIO_TASK_MATRIX_OUT0 117 +#define ESP_GPIO_EVENT_MATRIX_IN1 118 +#define ESP_GPIO_TASK_MATRIX_OUT1 118 +#define ESP_GPIO_EVENT_MATRIX_IN2 119 +#define ESP_GPIO_TASK_MATRIX_OUT2 119 +#define ESP_GPIO_EVENT_MATRIX_IN3 120 +#define ESP_GPIO_TASK_MATRIX_OUT3 120 +#define ESP_SPIQ_IN 121 +#define ESP_SPIQ_OUT 121 +#define ESP_SPID_IN 122 +#define ESP_SPID_OUT 122 +#define ESP_SPIHD_IN 123 +#define ESP_SPIHD_OUT 123 +#define ESP_SPIWP_IN 124 +#define ESP_SPIWP_OUT 124 +#define ESP_CLK_OUT_OUT1 125 +#define ESP_MODEM_DIAG29 125 +#define ESP_CLK_OUT_OUT2 126 +#define ESP_MODEM_DIAG30 126 +#define ESP_CLK_OUT_OUT3 127 +#define ESP_MODEM_DIAG31 127 +#define ESP_SIG_GPIO_OUT 128 +#define ESP_GPIO_MAP_DATE 0x2201120 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32H2_GPIO_SIGMAP_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/esp32h2-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32h2-pinctrl.h new file mode 100644 index 0000000000000..0da126323f525 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/esp32h2-pinctrl.h @@ -0,0 +1,2859 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * NOTE: Autogenerated file using esp_genpinctrl.py + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32H2_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32H2_PINCTRL_H_ + +/* SPIM2_CSEL */ +#define SPIM2_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS0_OUT) + +/* SPIM2_CSEL1 */ +#define SPIM2_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS1_OUT) + +/* SPIM2_CSEL2 */ +#define SPIM2_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS2_OUT) + +/* SPIM2_CSEL3 */ +#define SPIM2_CSEL3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS3_OUT) + +/* SPIM2_CSEL4 */ +#define SPIM2_CSEL4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS4_OUT) + +/* SPIM2_CSEL5 */ +#define SPIM2_CSEL5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS5_OUT) + +/* SPIM2_MISO */ +#define SPIM2_MISO_GPIO0 ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO1 ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO2 ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO3 ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO4 ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO5 ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO8 ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO9 ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO10 ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO11 ESP32_PINMUX(11, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO12 ESP32_PINMUX(12, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO13 ESP32_PINMUX(13, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO14 ESP32_PINMUX(14, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO22 ESP32_PINMUX(22, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO23 ESP32_PINMUX(23, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO24 ESP32_PINMUX(24, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO25 ESP32_PINMUX(25, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO26 ESP32_PINMUX(26, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO27 ESP32_PINMUX(27, ESP_FSPIQ_IN, ESP_NOSIG) + +/* SPIM2_MOSI */ +#define SPIM2_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPID_OUT) + +/* SPIM2_SCLK */ +#define SPIM2_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICLK_OUT) + +/* I2C0_SCL */ +#define I2C0_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO24 ESP32_PINMUX(24, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +#define I2C0_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) + +/* I2C0_SDA */ +#define I2C0_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO24 ESP32_PINMUX(24, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +#define I2C0_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +/* I2C1_SCL */ +#define I2C1_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO24 ESP32_PINMUX(24, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +#define I2C1_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) + +/* I2C1_SDA */ +#define I2C1_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO24 ESP32_PINMUX(24, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +#define I2C1_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +/* I2S_I_BCK */ +#define I2S_I_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO22 ESP32_PINMUX(22, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO23 ESP32_PINMUX(23, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO24 ESP32_PINMUX(24, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO25 ESP32_PINMUX(25, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +/* I2S_I_SD */ +#define I2S_I_SD_GPIO0 ESP32_PINMUX(0, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO1 ESP32_PINMUX(1, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO2 ESP32_PINMUX(2, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO3 ESP32_PINMUX(3, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO4 ESP32_PINMUX(4, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO5 ESP32_PINMUX(5, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO8 ESP32_PINMUX(8, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO9 ESP32_PINMUX(9, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO10 ESP32_PINMUX(10, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO11 ESP32_PINMUX(11, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO12 ESP32_PINMUX(12, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO13 ESP32_PINMUX(13, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO14 ESP32_PINMUX(14, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO22 ESP32_PINMUX(22, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO23 ESP32_PINMUX(23, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO24 ESP32_PINMUX(24, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO25 ESP32_PINMUX(25, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO26 ESP32_PINMUX(26, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO27 ESP32_PINMUX(27, ESP_I2SI_SD_IN, ESP_NOSIG) + +/* I2S_I_WS */ +#define I2S_I_WS_GPIO0 ESP32_PINMUX(0, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO1 ESP32_PINMUX(1, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO2 ESP32_PINMUX(2, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO3 ESP32_PINMUX(3, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO4 ESP32_PINMUX(4, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO5 ESP32_PINMUX(5, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO8 ESP32_PINMUX(8, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO9 ESP32_PINMUX(9, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO10 ESP32_PINMUX(10, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO11 ESP32_PINMUX(11, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO12 ESP32_PINMUX(12, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO13 ESP32_PINMUX(13, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO14 ESP32_PINMUX(14, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO22 ESP32_PINMUX(22, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO23 ESP32_PINMUX(23, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO24 ESP32_PINMUX(24, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO25 ESP32_PINMUX(25, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO26 ESP32_PINMUX(26, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO27 ESP32_PINMUX(27, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +/* I2S_MCLK */ +#define I2S_MCLK_GPIO0 ESP32_PINMUX(0, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO1 ESP32_PINMUX(1, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO2 ESP32_PINMUX(2, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO3 ESP32_PINMUX(3, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO4 ESP32_PINMUX(4, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO5 ESP32_PINMUX(5, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO8 ESP32_PINMUX(8, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO9 ESP32_PINMUX(9, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO10 ESP32_PINMUX(10, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO11 ESP32_PINMUX(11, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO12 ESP32_PINMUX(12, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO13 ESP32_PINMUX(13, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO14 ESP32_PINMUX(14, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO22 ESP32_PINMUX(22, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO23 ESP32_PINMUX(23, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO24 ESP32_PINMUX(24, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO25 ESP32_PINMUX(25, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO26 ESP32_PINMUX(26, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO27 ESP32_PINMUX(27, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +/* I2S_O_BCK */ +#define I2S_O_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO22 ESP32_PINMUX(22, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO23 ESP32_PINMUX(23, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO24 ESP32_PINMUX(24, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO25 ESP32_PINMUX(25, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +/* I2S_O_SD */ +#define I2S_O_SD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2SO_SD_OUT) + +/* I2S_O_WS */ +#define I2S_O_WS_GPIO0 ESP32_PINMUX(0, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO1 ESP32_PINMUX(1, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO2 ESP32_PINMUX(2, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO3 ESP32_PINMUX(3, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO4 ESP32_PINMUX(4, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO5 ESP32_PINMUX(5, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO8 ESP32_PINMUX(8, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO9 ESP32_PINMUX(9, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO10 ESP32_PINMUX(10, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO11 ESP32_PINMUX(11, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO12 ESP32_PINMUX(12, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO13 ESP32_PINMUX(13, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO14 ESP32_PINMUX(14, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO22 ESP32_PINMUX(22, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO23 ESP32_PINMUX(23, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO24 ESP32_PINMUX(24, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO25 ESP32_PINMUX(25, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO26 ESP32_PINMUX(26, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO27 ESP32_PINMUX(27, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +/* LEDC_CH0 */ +#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +/* LEDC_CH1 */ +#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +/* LEDC_CH2 */ +#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +/* LEDC_CH3 */ +#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +/* LEDC_CH4 */ +#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +/* LEDC_CH5 */ +#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +/* MCPWM0_CAP0 */ +#define MCPWM0_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO22 ESP32_PINMUX(22, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO23 ESP32_PINMUX(23, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO24 ESP32_PINMUX(24, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO25 ESP32_PINMUX(25, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +/* MCPWM0_CAP1 */ +#define MCPWM0_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO22 ESP32_PINMUX(22, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO23 ESP32_PINMUX(23, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO24 ESP32_PINMUX(24, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO25 ESP32_PINMUX(25, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +/* MCPWM0_CAP2 */ +#define MCPWM0_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO22 ESP32_PINMUX(22, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO23 ESP32_PINMUX(23, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO24 ESP32_PINMUX(24, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO25 ESP32_PINMUX(25, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +/* MCPWM0_FAULT0 */ +#define MCPWM0_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO22 ESP32_PINMUX(22, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO23 ESP32_PINMUX(23, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO24 ESP32_PINMUX(24, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO25 ESP32_PINMUX(25, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F0_IN, ESP_NOSIG) + +/* MCPWM0_FAULT1 */ +#define MCPWM0_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO22 ESP32_PINMUX(22, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO23 ESP32_PINMUX(23, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO24 ESP32_PINMUX(24, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO25 ESP32_PINMUX(25, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F1_IN, ESP_NOSIG) + +/* MCPWM0_FAULT2 */ +#define MCPWM0_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO22 ESP32_PINMUX(22, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO23 ESP32_PINMUX(23, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO24 ESP32_PINMUX(24, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO25 ESP32_PINMUX(25, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F2_IN, ESP_NOSIG) + +/* MCPWM0_OUT0A */ +#define MCPWM0_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0A) + +/* MCPWM0_OUT0B */ +#define MCPWM0_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0B) + +/* MCPWM0_OUT1A */ +#define MCPWM0_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1A) + +/* MCPWM0_OUT1B */ +#define MCPWM0_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1B) + +/* MCPWM0_OUT2A */ +#define MCPWM0_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2A) + +/* MCPWM0_OUT2B */ +#define MCPWM0_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2B) + +/* MCPWM0_SYNC0 */ +#define MCPWM0_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO22 ESP32_PINMUX(22, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO23 ESP32_PINMUX(23, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO24 ESP32_PINMUX(24, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO25 ESP32_PINMUX(25, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +/* MCPWM0_SYNC1 */ +#define MCPWM0_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO22 ESP32_PINMUX(22, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO23 ESP32_PINMUX(23, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO24 ESP32_PINMUX(24, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO25 ESP32_PINMUX(25, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +/* MCPWM0_SYNC2 */ +#define MCPWM0_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO22 ESP32_PINMUX(22, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO23 ESP32_PINMUX(23, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO24 ESP32_PINMUX(24, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO25 ESP32_PINMUX(25, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +/* TWAI_BUS_OFF */ +#define TWAI_BUS_OFF_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +#define TWAI_BUS_OFF_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) + +/* TWAI_CLKOUT */ +#define TWAI_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_CLKOUT) + +#define TWAI_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_CLKOUT) + +/* TWAI_RX */ +#define TWAI_RX_GPIO0 ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO1 ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO2 ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO3 ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO4 ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO5 ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO8 ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO9 ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO10 ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO11 ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO12 ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO13 ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO14 ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO22 ESP32_PINMUX(22, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO23 ESP32_PINMUX(23, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO24 ESP32_PINMUX(24, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO25 ESP32_PINMUX(25, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO26 ESP32_PINMUX(26, ESP_TWAI_RX, ESP_NOSIG) + +#define TWAI_RX_GPIO27 ESP32_PINMUX(27, ESP_TWAI_RX, ESP_NOSIG) + +/* TWAI_TX */ +#define TWAI_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_TX) + +#define TWAI_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_TX) + +/* PCNT0_CH0CTRL */ +#define PCNT0_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) + +/* PCNT0_CH0SIG */ +#define PCNT0_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +#define PCNT0_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) + +/* PCNT0_CH1CTRL */ +#define PCNT0_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) + +/* PCNT0_CH1SIG */ +#define PCNT0_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +#define PCNT0_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) + +/* PCNT1_CH0CTRL */ +#define PCNT1_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) + +/* PCNT1_CH0SIG */ +#define PCNT1_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +#define PCNT1_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) + +/* PCNT1_CH1CTRL */ +#define PCNT1_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) + +/* PCNT1_CH1SIG */ +#define PCNT1_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +#define PCNT1_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) + +/* PCNT2_CH0CTRL */ +#define PCNT2_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) + +/* PCNT2_CH0SIG */ +#define PCNT2_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +#define PCNT2_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN2, ESP_NOSIG) + +/* PCNT2_CH1CTRL */ +#define PCNT2_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) + +/* PCNT2_CH1SIG */ +#define PCNT2_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +#define PCNT2_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) + +/* PCNT3_CH0CTRL */ +#define PCNT3_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) + +/* PCNT3_CH0SIG */ +#define PCNT3_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +#define PCNT3_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) + +/* PCNT3_CH1CTRL */ +#define PCNT3_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO24 ESP32_PINMUX(24, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) + +/* PCNT3_CH1SIG */ +#define PCNT3_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO24 ESP32_PINMUX(24, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +#define PCNT3_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) + +/* UART0_CTS */ +#define UART0_CTS_GPIO0 ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO1 ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO2 ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO3 ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO4 ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO5 ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO8 ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO9 ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO10 ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO11 ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO12 ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO13 ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO14 ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO22 ESP32_PINMUX(22, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO23 ESP32_PINMUX(23, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO24 ESP32_PINMUX(24, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO25 ESP32_PINMUX(25, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO26 ESP32_PINMUX(26, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO27 ESP32_PINMUX(27, ESP_U0CTS_IN, ESP_NOSIG) + +/* UART0_DSR */ +#define UART0_DSR_GPIO0 ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO1 ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO2 ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO3 ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO4 ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO5 ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO8 ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO9 ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO10 ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO11 ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO12 ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO13 ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO14 ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO22 ESP32_PINMUX(22, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO23 ESP32_PINMUX(23, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO24 ESP32_PINMUX(24, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO25 ESP32_PINMUX(25, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO26 ESP32_PINMUX(26, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO27 ESP32_PINMUX(27, ESP_U0DSR_IN, ESP_NOSIG) + +/* UART0_DTR */ +#define UART0_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0DTR_OUT) + +/* UART0_RTS */ +#define UART0_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0RTS_OUT) + +/* UART0_RX */ +#define UART0_RX_GPIO0 ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO1 ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO2 ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO3 ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO4 ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO5 ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO8 ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO9 ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO10 ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO11 ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO12 ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO13 ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO14 ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO22 ESP32_PINMUX(22, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO23 ESP32_PINMUX(23, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO24 ESP32_PINMUX(24, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO25 ESP32_PINMUX(25, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO26 ESP32_PINMUX(26, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO27 ESP32_PINMUX(27, ESP_U0RXD_IN, ESP_NOSIG) + +/* UART0_TX */ +#define UART0_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0TXD_OUT) + +/* UART1_CTS */ +#define UART1_CTS_GPIO0 ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO1 ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO2 ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO3 ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO4 ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO5 ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO8 ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO9 ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO10 ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO11 ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO12 ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO13 ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO14 ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO22 ESP32_PINMUX(22, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO23 ESP32_PINMUX(23, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO24 ESP32_PINMUX(24, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO25 ESP32_PINMUX(25, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO26 ESP32_PINMUX(26, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO27 ESP32_PINMUX(27, ESP_U1CTS_IN, ESP_NOSIG) + +/* UART1_DSR */ +#define UART1_DSR_GPIO0 ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO1 ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO2 ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO3 ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO4 ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO5 ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO8 ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO9 ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO10 ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO11 ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO12 ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO13 ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO14 ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO22 ESP32_PINMUX(22, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO23 ESP32_PINMUX(23, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO24 ESP32_PINMUX(24, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO25 ESP32_PINMUX(25, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO26 ESP32_PINMUX(26, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO27 ESP32_PINMUX(27, ESP_U1DSR_IN, ESP_NOSIG) + +/* UART1_DTR */ +#define UART1_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1DTR_OUT) + +/* UART1_RTS */ +#define UART1_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1RTS_OUT) + +/* UART1_RX */ +#define UART1_RX_GPIO0 ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO1 ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO2 ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO3 ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO4 ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO5 ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO8 ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO9 ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO10 ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO11 ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO12 ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO13 ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO14 ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO22 ESP32_PINMUX(22, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO23 ESP32_PINMUX(23, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO24 ESP32_PINMUX(24, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO25 ESP32_PINMUX(25, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO26 ESP32_PINMUX(26, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO27 ESP32_PINMUX(27, ESP_U1RXD_IN, ESP_NOSIG) + +/* UART1_TX */ +#define UART1_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO24 ESP32_PINMUX(24, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1TXD_OUT) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32H2_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h index fdb9d92ecd033..8d35a0d4d5343 100644 --- a/include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h @@ -2,7 +2,7 @@ * Copyright (c) 2025 Silicon Laboratories Inc. * SPDX-License-Identifier: Apache-2.0 * - * Pin Control for Silicon Labs PG28 devices + * Pin Control for Silicon Labs XG28 devices * * This file was generated by the script gen_pinctrl.py in the hal_silabs module. * Do not manually edit. @@ -11,7 +11,7 @@ #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_ #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_ -#include +#include #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1) @@ -43,6 +43,10 @@ #define SILABS_DBUS_EUSART2_TX(port, pin) SILABS_DBUS(port, pin, 49, 1, 4, 6) #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2) +#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 57, 1, 0, 1) +#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 57, 1, 1, 2) +#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 57, 1, 2, 3) + #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 62, 1, 0, 1) #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 62, 1, 1, 2) @@ -992,6 +996,91 @@ #define EUSART2_CTS_PD14 SILABS_DBUS_EUSART2_CTS(0x3, 0xe) #define EUSART2_CTS_PD15 SILABS_DBUS_EUSART2_CTS(0x3, 0xf) +#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) +#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) +#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) +#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) +#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) +#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) +#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6) +#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7) +#define PTI_DCLK_PC8 SILABS_DBUS_PTI_DCLK(0x2, 0x8) +#define PTI_DCLK_PC9 SILABS_DBUS_PTI_DCLK(0x2, 0x9) +#define PTI_DCLK_PC10 SILABS_DBUS_PTI_DCLK(0x2, 0xa) +#define PTI_DCLK_PC11 SILABS_DBUS_PTI_DCLK(0x2, 0xb) +#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) +#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) +#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) +#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) +#define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4) +#define PTI_DCLK_PD5 SILABS_DBUS_PTI_DCLK(0x3, 0x5) +#define PTI_DCLK_PD6 SILABS_DBUS_PTI_DCLK(0x3, 0x6) +#define PTI_DCLK_PD7 SILABS_DBUS_PTI_DCLK(0x3, 0x7) +#define PTI_DCLK_PD8 SILABS_DBUS_PTI_DCLK(0x3, 0x8) +#define PTI_DCLK_PD9 SILABS_DBUS_PTI_DCLK(0x3, 0x9) +#define PTI_DCLK_PD10 SILABS_DBUS_PTI_DCLK(0x3, 0xa) +#define PTI_DCLK_PD11 SILABS_DBUS_PTI_DCLK(0x3, 0xb) +#define PTI_DCLK_PD12 SILABS_DBUS_PTI_DCLK(0x3, 0xc) +#define PTI_DCLK_PD13 SILABS_DBUS_PTI_DCLK(0x3, 0xd) +#define PTI_DCLK_PD14 SILABS_DBUS_PTI_DCLK(0x3, 0xe) +#define PTI_DCLK_PD15 SILABS_DBUS_PTI_DCLK(0x3, 0xf) +#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) +#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) +#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) +#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) +#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) +#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) +#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6) +#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7) +#define PTI_DFRAME_PC8 SILABS_DBUS_PTI_DFRAME(0x2, 0x8) +#define PTI_DFRAME_PC9 SILABS_DBUS_PTI_DFRAME(0x2, 0x9) +#define PTI_DFRAME_PC10 SILABS_DBUS_PTI_DFRAME(0x2, 0xa) +#define PTI_DFRAME_PC11 SILABS_DBUS_PTI_DFRAME(0x2, 0xb) +#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) +#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) +#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) +#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) +#define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4) +#define PTI_DFRAME_PD5 SILABS_DBUS_PTI_DFRAME(0x3, 0x5) +#define PTI_DFRAME_PD6 SILABS_DBUS_PTI_DFRAME(0x3, 0x6) +#define PTI_DFRAME_PD7 SILABS_DBUS_PTI_DFRAME(0x3, 0x7) +#define PTI_DFRAME_PD8 SILABS_DBUS_PTI_DFRAME(0x3, 0x8) +#define PTI_DFRAME_PD9 SILABS_DBUS_PTI_DFRAME(0x3, 0x9) +#define PTI_DFRAME_PD10 SILABS_DBUS_PTI_DFRAME(0x3, 0xa) +#define PTI_DFRAME_PD11 SILABS_DBUS_PTI_DFRAME(0x3, 0xb) +#define PTI_DFRAME_PD12 SILABS_DBUS_PTI_DFRAME(0x3, 0xc) +#define PTI_DFRAME_PD13 SILABS_DBUS_PTI_DFRAME(0x3, 0xd) +#define PTI_DFRAME_PD14 SILABS_DBUS_PTI_DFRAME(0x3, 0xe) +#define PTI_DFRAME_PD15 SILABS_DBUS_PTI_DFRAME(0x3, 0xf) +#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) +#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) +#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) +#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) +#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) +#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) +#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6) +#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7) +#define PTI_DOUT_PC8 SILABS_DBUS_PTI_DOUT(0x2, 0x8) +#define PTI_DOUT_PC9 SILABS_DBUS_PTI_DOUT(0x2, 0x9) +#define PTI_DOUT_PC10 SILABS_DBUS_PTI_DOUT(0x2, 0xa) +#define PTI_DOUT_PC11 SILABS_DBUS_PTI_DOUT(0x2, 0xb) +#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) +#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) +#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) +#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) +#define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4) +#define PTI_DOUT_PD5 SILABS_DBUS_PTI_DOUT(0x3, 0x5) +#define PTI_DOUT_PD6 SILABS_DBUS_PTI_DOUT(0x3, 0x6) +#define PTI_DOUT_PD7 SILABS_DBUS_PTI_DOUT(0x3, 0x7) +#define PTI_DOUT_PD8 SILABS_DBUS_PTI_DOUT(0x3, 0x8) +#define PTI_DOUT_PD9 SILABS_DBUS_PTI_DOUT(0x3, 0x9) +#define PTI_DOUT_PD10 SILABS_DBUS_PTI_DOUT(0x3, 0xa) +#define PTI_DOUT_PD11 SILABS_DBUS_PTI_DOUT(0x3, 0xb) +#define PTI_DOUT_PD12 SILABS_DBUS_PTI_DOUT(0x3, 0xc) +#define PTI_DOUT_PD13 SILABS_DBUS_PTI_DOUT(0x3, 0xd) +#define PTI_DOUT_PD14 SILABS_DBUS_PTI_DOUT(0x3, 0xe) +#define PTI_DOUT_PD15 SILABS_DBUS_PTI_DOUT(0x3, 0xf) + #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) @@ -2115,6 +2204,476 @@ #define LETIMER0_OUT1_PB6 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x6) #define LETIMER0_OUT1_PB7 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x7) +#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) +#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) +#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) +#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) +#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) +#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) +#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) +#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7) +#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8) +#define MODEM_ANT0_PA9 SILABS_DBUS_MODEM_ANT0(0x0, 0x9) +#define MODEM_ANT0_PA10 SILABS_DBUS_MODEM_ANT0(0x0, 0xa) +#define MODEM_ANT0_PA11 SILABS_DBUS_MODEM_ANT0(0x0, 0xb) +#define MODEM_ANT0_PA12 SILABS_DBUS_MODEM_ANT0(0x0, 0xc) +#define MODEM_ANT0_PA13 SILABS_DBUS_MODEM_ANT0(0x0, 0xd) +#define MODEM_ANT0_PA14 SILABS_DBUS_MODEM_ANT0(0x0, 0xe) +#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) +#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) +#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2) +#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3) +#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4) +#define MODEM_ANT0_PB5 SILABS_DBUS_MODEM_ANT0(0x1, 0x5) +#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) +#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) +#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) +#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) +#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) +#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) +#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6) +#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7) +#define MODEM_ANT0_PC8 SILABS_DBUS_MODEM_ANT0(0x2, 0x8) +#define MODEM_ANT0_PC9 SILABS_DBUS_MODEM_ANT0(0x2, 0x9) +#define MODEM_ANT0_PC10 SILABS_DBUS_MODEM_ANT0(0x2, 0xa) +#define MODEM_ANT0_PC11 SILABS_DBUS_MODEM_ANT0(0x2, 0xb) +#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) +#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) +#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) +#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) +#define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4) +#define MODEM_ANT0_PD5 SILABS_DBUS_MODEM_ANT0(0x3, 0x5) +#define MODEM_ANT0_PD6 SILABS_DBUS_MODEM_ANT0(0x3, 0x6) +#define MODEM_ANT0_PD7 SILABS_DBUS_MODEM_ANT0(0x3, 0x7) +#define MODEM_ANT0_PD8 SILABS_DBUS_MODEM_ANT0(0x3, 0x8) +#define MODEM_ANT0_PD9 SILABS_DBUS_MODEM_ANT0(0x3, 0x9) +#define MODEM_ANT0_PD10 SILABS_DBUS_MODEM_ANT0(0x3, 0xa) +#define MODEM_ANT0_PD11 SILABS_DBUS_MODEM_ANT0(0x3, 0xb) +#define MODEM_ANT0_PD12 SILABS_DBUS_MODEM_ANT0(0x3, 0xc) +#define MODEM_ANT0_PD13 SILABS_DBUS_MODEM_ANT0(0x3, 0xd) +#define MODEM_ANT0_PD14 SILABS_DBUS_MODEM_ANT0(0x3, 0xe) +#define MODEM_ANT0_PD15 SILABS_DBUS_MODEM_ANT0(0x3, 0xf) +#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) +#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) +#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) +#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) +#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) +#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) +#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) +#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7) +#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8) +#define MODEM_ANT1_PA9 SILABS_DBUS_MODEM_ANT1(0x0, 0x9) +#define MODEM_ANT1_PA10 SILABS_DBUS_MODEM_ANT1(0x0, 0xa) +#define MODEM_ANT1_PA11 SILABS_DBUS_MODEM_ANT1(0x0, 0xb) +#define MODEM_ANT1_PA12 SILABS_DBUS_MODEM_ANT1(0x0, 0xc) +#define MODEM_ANT1_PA13 SILABS_DBUS_MODEM_ANT1(0x0, 0xd) +#define MODEM_ANT1_PA14 SILABS_DBUS_MODEM_ANT1(0x0, 0xe) +#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) +#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) +#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2) +#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3) +#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4) +#define MODEM_ANT1_PB5 SILABS_DBUS_MODEM_ANT1(0x1, 0x5) +#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) +#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) +#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) +#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) +#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) +#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) +#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6) +#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7) +#define MODEM_ANT1_PC8 SILABS_DBUS_MODEM_ANT1(0x2, 0x8) +#define MODEM_ANT1_PC9 SILABS_DBUS_MODEM_ANT1(0x2, 0x9) +#define MODEM_ANT1_PC10 SILABS_DBUS_MODEM_ANT1(0x2, 0xa) +#define MODEM_ANT1_PC11 SILABS_DBUS_MODEM_ANT1(0x2, 0xb) +#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) +#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) +#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) +#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) +#define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4) +#define MODEM_ANT1_PD5 SILABS_DBUS_MODEM_ANT1(0x3, 0x5) +#define MODEM_ANT1_PD6 SILABS_DBUS_MODEM_ANT1(0x3, 0x6) +#define MODEM_ANT1_PD7 SILABS_DBUS_MODEM_ANT1(0x3, 0x7) +#define MODEM_ANT1_PD8 SILABS_DBUS_MODEM_ANT1(0x3, 0x8) +#define MODEM_ANT1_PD9 SILABS_DBUS_MODEM_ANT1(0x3, 0x9) +#define MODEM_ANT1_PD10 SILABS_DBUS_MODEM_ANT1(0x3, 0xa) +#define MODEM_ANT1_PD11 SILABS_DBUS_MODEM_ANT1(0x3, 0xb) +#define MODEM_ANT1_PD12 SILABS_DBUS_MODEM_ANT1(0x3, 0xc) +#define MODEM_ANT1_PD13 SILABS_DBUS_MODEM_ANT1(0x3, 0xd) +#define MODEM_ANT1_PD14 SILABS_DBUS_MODEM_ANT1(0x3, 0xe) +#define MODEM_ANT1_PD15 SILABS_DBUS_MODEM_ANT1(0x3, 0xf) +#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0) +#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1) +#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2) +#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3) +#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4) +#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5) +#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6) +#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7) +#define MODEM_ANTROLLOVER_PC8 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x8) +#define MODEM_ANTROLLOVER_PC9 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x9) +#define MODEM_ANTROLLOVER_PC10 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xa) +#define MODEM_ANTROLLOVER_PC11 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xb) +#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0) +#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1) +#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2) +#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3) +#define MODEM_ANTROLLOVER_PD4 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x4) +#define MODEM_ANTROLLOVER_PD5 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x5) +#define MODEM_ANTROLLOVER_PD6 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x6) +#define MODEM_ANTROLLOVER_PD7 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x7) +#define MODEM_ANTROLLOVER_PD8 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x8) +#define MODEM_ANTROLLOVER_PD9 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x9) +#define MODEM_ANTROLLOVER_PD10 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xa) +#define MODEM_ANTROLLOVER_PD11 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xb) +#define MODEM_ANTROLLOVER_PD12 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xc) +#define MODEM_ANTROLLOVER_PD13 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xd) +#define MODEM_ANTROLLOVER_PD14 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xe) +#define MODEM_ANTROLLOVER_PD15 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xf) +#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0) +#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1) +#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2) +#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3) +#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4) +#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5) +#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6) +#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7) +#define MODEM_ANTRR0_PC8 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x8) +#define MODEM_ANTRR0_PC9 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x9) +#define MODEM_ANTRR0_PC10 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xa) +#define MODEM_ANTRR0_PC11 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xb) +#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0) +#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1) +#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2) +#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3) +#define MODEM_ANTRR0_PD4 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x4) +#define MODEM_ANTRR0_PD5 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x5) +#define MODEM_ANTRR0_PD6 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x6) +#define MODEM_ANTRR0_PD7 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x7) +#define MODEM_ANTRR0_PD8 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x8) +#define MODEM_ANTRR0_PD9 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x9) +#define MODEM_ANTRR0_PD10 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xa) +#define MODEM_ANTRR0_PD11 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xb) +#define MODEM_ANTRR0_PD12 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xc) +#define MODEM_ANTRR0_PD13 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xd) +#define MODEM_ANTRR0_PD14 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xe) +#define MODEM_ANTRR0_PD15 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xf) +#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0) +#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1) +#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2) +#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3) +#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4) +#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5) +#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6) +#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7) +#define MODEM_ANTRR1_PC8 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x8) +#define MODEM_ANTRR1_PC9 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x9) +#define MODEM_ANTRR1_PC10 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xa) +#define MODEM_ANTRR1_PC11 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xb) +#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0) +#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1) +#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2) +#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3) +#define MODEM_ANTRR1_PD4 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x4) +#define MODEM_ANTRR1_PD5 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x5) +#define MODEM_ANTRR1_PD6 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x6) +#define MODEM_ANTRR1_PD7 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x7) +#define MODEM_ANTRR1_PD8 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x8) +#define MODEM_ANTRR1_PD9 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x9) +#define MODEM_ANTRR1_PD10 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xa) +#define MODEM_ANTRR1_PD11 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xb) +#define MODEM_ANTRR1_PD12 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xc) +#define MODEM_ANTRR1_PD13 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xd) +#define MODEM_ANTRR1_PD14 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xe) +#define MODEM_ANTRR1_PD15 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xf) +#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0) +#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1) +#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2) +#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3) +#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4) +#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5) +#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6) +#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7) +#define MODEM_ANTRR2_PC8 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x8) +#define MODEM_ANTRR2_PC9 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x9) +#define MODEM_ANTRR2_PC10 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xa) +#define MODEM_ANTRR2_PC11 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xb) +#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0) +#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1) +#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2) +#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3) +#define MODEM_ANTRR2_PD4 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x4) +#define MODEM_ANTRR2_PD5 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x5) +#define MODEM_ANTRR2_PD6 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x6) +#define MODEM_ANTRR2_PD7 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x7) +#define MODEM_ANTRR2_PD8 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x8) +#define MODEM_ANTRR2_PD9 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x9) +#define MODEM_ANTRR2_PD10 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xa) +#define MODEM_ANTRR2_PD11 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xb) +#define MODEM_ANTRR2_PD12 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xc) +#define MODEM_ANTRR2_PD13 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xd) +#define MODEM_ANTRR2_PD14 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xe) +#define MODEM_ANTRR2_PD15 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xf) +#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0) +#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1) +#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2) +#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3) +#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4) +#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5) +#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6) +#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7) +#define MODEM_ANTRR3_PC8 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x8) +#define MODEM_ANTRR3_PC9 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x9) +#define MODEM_ANTRR3_PC10 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xa) +#define MODEM_ANTRR3_PC11 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xb) +#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0) +#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1) +#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2) +#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3) +#define MODEM_ANTRR3_PD4 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x4) +#define MODEM_ANTRR3_PD5 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x5) +#define MODEM_ANTRR3_PD6 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x6) +#define MODEM_ANTRR3_PD7 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x7) +#define MODEM_ANTRR3_PD8 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x8) +#define MODEM_ANTRR3_PD9 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x9) +#define MODEM_ANTRR3_PD10 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xa) +#define MODEM_ANTRR3_PD11 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xb) +#define MODEM_ANTRR3_PD12 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xc) +#define MODEM_ANTRR3_PD13 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xd) +#define MODEM_ANTRR3_PD14 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xe) +#define MODEM_ANTRR3_PD15 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xf) +#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0) +#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1) +#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2) +#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3) +#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4) +#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5) +#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6) +#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7) +#define MODEM_ANTRR4_PC8 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x8) +#define MODEM_ANTRR4_PC9 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x9) +#define MODEM_ANTRR4_PC10 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xa) +#define MODEM_ANTRR4_PC11 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xb) +#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0) +#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1) +#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2) +#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3) +#define MODEM_ANTRR4_PD4 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x4) +#define MODEM_ANTRR4_PD5 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x5) +#define MODEM_ANTRR4_PD6 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x6) +#define MODEM_ANTRR4_PD7 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x7) +#define MODEM_ANTRR4_PD8 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x8) +#define MODEM_ANTRR4_PD9 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x9) +#define MODEM_ANTRR4_PD10 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xa) +#define MODEM_ANTRR4_PD11 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xb) +#define MODEM_ANTRR4_PD12 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xc) +#define MODEM_ANTRR4_PD13 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xd) +#define MODEM_ANTRR4_PD14 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xe) +#define MODEM_ANTRR4_PD15 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xf) +#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0) +#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1) +#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2) +#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3) +#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4) +#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5) +#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6) +#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7) +#define MODEM_ANTRR5_PC8 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x8) +#define MODEM_ANTRR5_PC9 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x9) +#define MODEM_ANTRR5_PC10 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xa) +#define MODEM_ANTRR5_PC11 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xb) +#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0) +#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1) +#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2) +#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3) +#define MODEM_ANTRR5_PD4 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x4) +#define MODEM_ANTRR5_PD5 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x5) +#define MODEM_ANTRR5_PD6 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x6) +#define MODEM_ANTRR5_PD7 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x7) +#define MODEM_ANTRR5_PD8 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x8) +#define MODEM_ANTRR5_PD9 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x9) +#define MODEM_ANTRR5_PD10 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xa) +#define MODEM_ANTRR5_PD11 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xb) +#define MODEM_ANTRR5_PD12 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xc) +#define MODEM_ANTRR5_PD13 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xd) +#define MODEM_ANTRR5_PD14 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xe) +#define MODEM_ANTRR5_PD15 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xf) +#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0) +#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1) +#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2) +#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3) +#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4) +#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5) +#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6) +#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7) +#define MODEM_ANTSWEN_PC8 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x8) +#define MODEM_ANTSWEN_PC9 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x9) +#define MODEM_ANTSWEN_PC10 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xa) +#define MODEM_ANTSWEN_PC11 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xb) +#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0) +#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1) +#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2) +#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3) +#define MODEM_ANTSWEN_PD4 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x4) +#define MODEM_ANTSWEN_PD5 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x5) +#define MODEM_ANTSWEN_PD6 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x6) +#define MODEM_ANTSWEN_PD7 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x7) +#define MODEM_ANTSWEN_PD8 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x8) +#define MODEM_ANTSWEN_PD9 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x9) +#define MODEM_ANTSWEN_PD10 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xa) +#define MODEM_ANTSWEN_PD11 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xb) +#define MODEM_ANTSWEN_PD12 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xc) +#define MODEM_ANTSWEN_PD13 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xd) +#define MODEM_ANTSWEN_PD14 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xe) +#define MODEM_ANTSWEN_PD15 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xf) +#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0) +#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1) +#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2) +#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3) +#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4) +#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5) +#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6) +#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7) +#define MODEM_ANTSWUS_PC8 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x8) +#define MODEM_ANTSWUS_PC9 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x9) +#define MODEM_ANTSWUS_PC10 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xa) +#define MODEM_ANTSWUS_PC11 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xb) +#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0) +#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1) +#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2) +#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3) +#define MODEM_ANTSWUS_PD4 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x4) +#define MODEM_ANTSWUS_PD5 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x5) +#define MODEM_ANTSWUS_PD6 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x6) +#define MODEM_ANTSWUS_PD7 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x7) +#define MODEM_ANTSWUS_PD8 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x8) +#define MODEM_ANTSWUS_PD9 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x9) +#define MODEM_ANTSWUS_PD10 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xa) +#define MODEM_ANTSWUS_PD11 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xb) +#define MODEM_ANTSWUS_PD12 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xc) +#define MODEM_ANTSWUS_PD13 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xd) +#define MODEM_ANTSWUS_PD14 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xe) +#define MODEM_ANTSWUS_PD15 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xf) +#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0) +#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1) +#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2) +#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3) +#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4) +#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5) +#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6) +#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7) +#define MODEM_ANTTRIG_PC8 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x8) +#define MODEM_ANTTRIG_PC9 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x9) +#define MODEM_ANTTRIG_PC10 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xa) +#define MODEM_ANTTRIG_PC11 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xb) +#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0) +#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1) +#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2) +#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3) +#define MODEM_ANTTRIG_PD4 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x4) +#define MODEM_ANTTRIG_PD5 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x5) +#define MODEM_ANTTRIG_PD6 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x6) +#define MODEM_ANTTRIG_PD7 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x7) +#define MODEM_ANTTRIG_PD8 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x8) +#define MODEM_ANTTRIG_PD9 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x9) +#define MODEM_ANTTRIG_PD10 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xa) +#define MODEM_ANTTRIG_PD11 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xb) +#define MODEM_ANTTRIG_PD12 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xc) +#define MODEM_ANTTRIG_PD13 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xd) +#define MODEM_ANTTRIG_PD14 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xe) +#define MODEM_ANTTRIG_PD15 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xf) +#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0) +#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1) +#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2) +#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3) +#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4) +#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5) +#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6) +#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7) +#define MODEM_ANTTRIGSTOP_PC8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x8) +#define MODEM_ANTTRIGSTOP_PC9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x9) +#define MODEM_ANTTRIGSTOP_PC10 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xa) +#define MODEM_ANTTRIGSTOP_PC11 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xb) +#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0) +#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1) +#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2) +#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3) +#define MODEM_ANTTRIGSTOP_PD4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x4) +#define MODEM_ANTTRIGSTOP_PD5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x5) +#define MODEM_ANTTRIGSTOP_PD6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x6) +#define MODEM_ANTTRIGSTOP_PD7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x7) +#define MODEM_ANTTRIGSTOP_PD8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x8) +#define MODEM_ANTTRIGSTOP_PD9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x9) +#define MODEM_ANTTRIGSTOP_PD10 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xa) +#define MODEM_ANTTRIGSTOP_PD11 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xb) +#define MODEM_ANTTRIGSTOP_PD12 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xc) +#define MODEM_ANTTRIGSTOP_PD13 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xd) +#define MODEM_ANTTRIGSTOP_PD14 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xe) +#define MODEM_ANTTRIGSTOP_PD15 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xf) +#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) +#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) +#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) +#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) +#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) +#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) +#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) +#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7) +#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8) +#define MODEM_DCLK_PA9 SILABS_DBUS_MODEM_DCLK(0x0, 0x9) +#define MODEM_DCLK_PA10 SILABS_DBUS_MODEM_DCLK(0x0, 0xa) +#define MODEM_DCLK_PA11 SILABS_DBUS_MODEM_DCLK(0x0, 0xb) +#define MODEM_DCLK_PA12 SILABS_DBUS_MODEM_DCLK(0x0, 0xc) +#define MODEM_DCLK_PA13 SILABS_DBUS_MODEM_DCLK(0x0, 0xd) +#define MODEM_DCLK_PA14 SILABS_DBUS_MODEM_DCLK(0x0, 0xe) +#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) +#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) +#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2) +#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3) +#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4) +#define MODEM_DCLK_PB5 SILABS_DBUS_MODEM_DCLK(0x1, 0x5) +#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) +#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) +#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) +#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) +#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) +#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) +#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) +#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7) +#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8) +#define MODEM_DOUT_PA9 SILABS_DBUS_MODEM_DOUT(0x0, 0x9) +#define MODEM_DOUT_PA10 SILABS_DBUS_MODEM_DOUT(0x0, 0xa) +#define MODEM_DOUT_PA11 SILABS_DBUS_MODEM_DOUT(0x0, 0xb) +#define MODEM_DOUT_PA12 SILABS_DBUS_MODEM_DOUT(0x0, 0xc) +#define MODEM_DOUT_PA13 SILABS_DBUS_MODEM_DOUT(0x0, 0xd) +#define MODEM_DOUT_PA14 SILABS_DBUS_MODEM_DOUT(0x0, 0xe) +#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) +#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) +#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2) +#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3) +#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4) +#define MODEM_DOUT_PB5 SILABS_DBUS_MODEM_DOUT(0x1, 0x5) +#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) +#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) +#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) +#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) +#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) +#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) +#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) +#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7) +#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8) +#define MODEM_DIN_PA9 SILABS_DBUS_MODEM_DIN(0x0, 0x9) +#define MODEM_DIN_PA10 SILABS_DBUS_MODEM_DIN(0x0, 0xa) +#define MODEM_DIN_PA11 SILABS_DBUS_MODEM_DIN(0x0, 0xb) +#define MODEM_DIN_PA12 SILABS_DBUS_MODEM_DIN(0x0, 0xc) +#define MODEM_DIN_PA13 SILABS_DBUS_MODEM_DIN(0x0, 0xd) +#define MODEM_DIN_PA14 SILABS_DBUS_MODEM_DIN(0x0, 0xe) +#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) +#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) +#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2) +#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3) +#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4) +#define MODEM_DIN_PB5 SILABS_DBUS_MODEM_DIN(0x1, 0x5) + #define PCNT0_S0IN_PA0 SILABS_DBUS_PCNT0_S0IN(0x0, 0x0) #define PCNT0_S0IN_PA1 SILABS_DBUS_PCNT0_S0IN(0x0, 0x1) #define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2) diff --git a/include/zephyr/dt-bindings/pwm/pwm.h b/include/zephyr/dt-bindings/pwm/pwm.h index 48389b2eb1b86..11f0363783682 100644 --- a/include/zephyr/dt-bindings/pwm/pwm.h +++ b/include/zephyr/dt-bindings/pwm/pwm.h @@ -7,9 +7,7 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_ /** - * @brief PWM Interface - * @defgroup pwm_interface PWM Interface - * @ingroup io_interfaces + * @addtogroup pwm_interface * @{ */ diff --git a/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h b/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h deleted file mode 100644 index 75216175d6535..0000000000000 --- a/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h +++ /dev/null @@ -1,14 +0,0 @@ -/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_CAT1_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_CAT1_H_ -/** - * Divider Type - */ -#define CY_SYSCLK_DIV_8_BIT 0 -#define CY_SYSCLK_DIV_16_BIT 1 - -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_CAT1_H_ */ diff --git a/include/zephyr/dt-bindings/pwm/pwm_ifx_tcpwm.h b/include/zephyr/dt-bindings/pwm/pwm_ifx_tcpwm.h new file mode 100644 index 0000000000000..64cd8622bc103 --- /dev/null +++ b/include/zephyr/dt-bindings/pwm/pwm_ifx_tcpwm.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_TCPWM_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_TCPWM_H_ +/** + * Divider Type + */ +#define PWM_IFX_SYSCLK_DIV_8_BIT 0 +#define PWM_IFX_SYSCLK_DIV_16_BIT 1 + +/** + * Custom PWM flags for Infineon TCPWM + * These flags can be used with the PWM API in the upper 8 bits of pwm_flags_t. + * They allow configuring the output behavior of the PWM pins when the PWM is + * disabled. + */ +#define PWM_IFX_TCPWM_OUTPUT_HIGHZ 0 +#define PWM_IFX_TCPWM_OUTPUT_RETAIN 1 +#define PWM_IFX_TCPWM_OUTPUT_LOW 2 +#define PWM_IFX_TCPWM_OUTPUT_HIGH 3 + +#define PWM_IFX_TCPWM_OUTPUT_MASK 0x3 +#define PWM_IFX_TCPWM_OUTPUT_POS 8 /* Place at the end of flags */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_TCPWM_H_ */ diff --git a/include/zephyr/dt-bindings/sent/sent.h b/include/zephyr/dt-bindings/sent/sent.h index 351101d4ec936..7115fe31586ac 100644 --- a/include/zephyr/dt-bindings/sent/sent.h +++ b/include/zephyr/dt-bindings/sent/sent.h @@ -8,9 +8,7 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_SENT_H_ /** - * @brief SENT Interface - * @defgroup sent_interface SENT Interface - * @ingroup io_interfaces + * @addtogroup sent_interface * @{ */ diff --git a/include/zephyr/dt-bindings/spi/spi.h b/include/zephyr/dt-bindings/spi/spi.h index 2d9709d946bd3..17d030392d79a 100644 --- a/include/zephyr/dt-bindings/spi/spi.h +++ b/include/zephyr/dt-bindings/spi/spi.h @@ -7,9 +7,7 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_ /** - * @brief SPI Interface - * @defgroup spi_interface SPI Interface - * @ingroup io_interfaces + * @addtogroup spi_interface * @{ */ diff --git a/include/zephyr/fs/nvs.h b/include/zephyr/fs/nvs.h index df70b64f58bce..f654933166f9e 100644 --- a/include/zephyr/fs/nvs.h +++ b/include/zephyr/fs/nvs.h @@ -48,7 +48,7 @@ struct nvs_fs { /** Data write address */ uint32_t data_wra; /** File system is split into sectors, each sector must be multiple of erase-block-size */ - uint16_t sector_size; + uint32_t sector_size; /** Number of sectors in the file system */ uint16_t sector_count; /** Flag indicating if the file system is initialized */ diff --git a/include/zephyr/fs/zms.h b/include/zephyr/fs/zms.h index 9136d6587d495..41ba053c93c0e 100644 --- a/include/zephyr/fs/zms.h +++ b/include/zephyr/fs/zms.h @@ -85,7 +85,7 @@ struct zms_fs { * @retval 0 on success. * @retval -ENOTSUP if the detected file system is not ZMS. * @retval -EPROTONOSUPPORT if the ZMS version is not supported. - * @retval -EINVAL if any of the flash parameters or the sector layout is invalid. + * @retval -EINVAL if `fs` is NULL or any of the flash parameters or the sector layout is invalid. * @retval -ENXIO if there is a device error. * @retval -EIO if there is a memory read/write error. */ @@ -101,6 +101,7 @@ int zms_mount(struct zms_fs *fs); * @retval -EACCES if `fs` is not mounted. * @retval -ENXIO if there is a device error. * @retval -EIO if there is a memory read/write error. + * @retval -EINVAL if `fs` is NULL. */ int zms_clear(struct zms_fs *fs); @@ -124,7 +125,7 @@ int zms_clear(struct zms_fs *fs); * @retval -EACCES if ZMS is still not initialized. * @retval -ENXIO if there is a device error. * @retval -EIO if there is a memory read/write error. - * @retval -EINVAL if `len` is invalid. + * @retval -EINVAL if `fs` is NULL or `len` is invalid. * @retval -ENOSPC if no space is left on the device. */ ssize_t zms_write(struct zms_fs *fs, uint32_t id, const void *data, size_t len); @@ -139,6 +140,7 @@ ssize_t zms_write(struct zms_fs *fs, uint32_t id, const void *data, size_t len); * @retval -EACCES if ZMS is still not initialized. * @retval -ENXIO if there is a device error. * @retval -EIO if there is a memory read/write error. + * @retval -EINVAL if `fs` is NULL. */ int zms_delete(struct zms_fs *fs, uint32_t id); @@ -157,6 +159,7 @@ int zms_delete(struct zms_fs *fs, uint32_t id); * @retval -EACCES if ZMS is still not initialized. * @retval -EIO if there is a memory read/write error. * @retval -ENOENT if there is no entry with the given `id`. + * @retval -EINVAL if `fs` is NULL. */ ssize_t zms_read(struct zms_fs *fs, uint32_t id, void *data, size_t len); @@ -177,6 +180,7 @@ ssize_t zms_read(struct zms_fs *fs, uint32_t id, void *data, size_t len); * @retval -EACCES if ZMS is still not initialized. * @retval -EIO if there is a memory read/write error. * @retval -ENOENT if there is no entry with the given `id` and history counter. + * @retval -EINVAL if `fs` is NULL. */ ssize_t zms_read_hist(struct zms_fs *fs, uint32_t id, void *data, size_t len, uint32_t cnt); @@ -192,6 +196,7 @@ ssize_t zms_read_hist(struct zms_fs *fs, uint32_t id, void *data, size_t len, ui * @retval -EACCES if ZMS is still not initialized. * @retval -EIO if there is a memory read/write error. * @retval -ENOENT if there is no entry with the given id. + * @retval -EINVAL if `fs` is NULL. */ ssize_t zms_get_data_length(struct zms_fs *fs, uint32_t id); @@ -207,6 +212,7 @@ ssize_t zms_get_data_length(struct zms_fs *fs, uint32_t id); * @retval Number of free bytes (>= 0) on success. * @retval -EACCES if ZMS is still not initialized. * @retval -EIO if there is a memory read/write error. + * @retval -EINVAL if `fs` is NULL. */ ssize_t zms_calc_free_space(struct zms_fs *fs); @@ -217,8 +223,9 @@ ssize_t zms_calc_free_space(struct zms_fs *fs); * * @retval >=0 Number of free bytes in the currently active sector * @retval -EACCES if ZMS is still not initialized. + * @retval -EINVAL if `fs` is NULL. */ -size_t zms_active_sector_free_space(struct zms_fs *fs); +ssize_t zms_active_sector_free_space(struct zms_fs *fs); /** * @brief Close the currently active sector and switch to the next one. @@ -234,6 +241,7 @@ size_t zms_active_sector_free_space(struct zms_fs *fs); * @retval 0 on success. * @retval -EACCES if ZMS is still not initialized. * @retval -EIO if there is a memory read/write error. + * @retval -EINVAL if `fs` is NULL. */ int zms_sector_use_next(struct zms_fs *fs); diff --git a/include/zephyr/input/input.h b/include/zephyr/input/input.h index 497573c81eaba..36ac6386ba99c 100644 --- a/include/zephyr/input/input.h +++ b/include/zephyr/input/input.h @@ -14,8 +14,8 @@ #define ZEPHYR_INCLUDE_INPUT_H_ /** - * @brief Input Interface - * @defgroup input_interface Input Interface + * @brief Interfaces for input devices. + * @defgroup input_interface Input * @since 3.4 * @version 0.1.0 * @ingroup io_interfaces diff --git a/include/zephyr/kernel.h b/include/zephyr/kernel.h index 7fe1920c14701..0aa9e789b1247 100644 --- a/include/zephyr/kernel.h +++ b/include/zephyr/kernel.h @@ -2507,6 +2507,52 @@ __syscall uint32_t k_event_wait(struct k_event *event, uint32_t events, __syscall uint32_t k_event_wait_all(struct k_event *event, uint32_t events, bool reset, k_timeout_t timeout); +/** + * @brief Wait for any of the specified events (safe version) + * + * This call is nearly identical to @ref k_event_wait with the main difference + * being that the safe version atomically clears received events from the + * event object. This mitigates the need for calling @ref k_event_clear, or + * passing a "reset" argument, since doing so may result in lost event + * information. + * + * @param event Address of the event object + * @param events Set of desired events on which to wait + * @param reset If true, clear the set of events tracked by the event object + * before waiting. If false, do not clear the events. + * @param timeout Waiting period for the desired set of events or one of the + * special values K_NO_WAIT and K_FOREVER. + * + * @retval set of matching events upon success + * @retval 0 if no matching event was received within the specified time + */ +__syscall uint32_t k_event_wait_safe(struct k_event *event, uint32_t events, + bool reset, k_timeout_t timeout); + +/** + * @brief Wait for all of the specified events (safe version) + * + * This call is nearly identical to @ref k_event_wait_all with the main + * difference being that the safe version atomically clears received events + * from the event object. This mitigates the need for calling + * @ref k_event_clear, or passing a "reset" argument, since doing so may + * result in lost event information. + * + * @param event Address of the event object + * @param events Set of desired events on which to wait + * @param reset If true, clear the set of events tracked by the event object + * before waiting. If false, do not clear the events. + * @param timeout Waiting period for the desired set of events or one of the + * special values K_NO_WAIT and K_FOREVER. + * + * @retval set of matching events upon success + * @retval 0 if all matching events were not received within the specified time + */ +__syscall uint32_t k_event_wait_all_safe(struct k_event *event, uint32_t events, + bool reset, k_timeout_t timeout); + + + /** * @brief Test the events currently tracked in the event object * @@ -3416,6 +3462,97 @@ static inline unsigned int z_impl_k_sem_count_get(struct k_sem *sem) /** @} */ +#if defined(CONFIG_SCHED_IPI_SUPPORTED) || defined(__DOXYGEN__) +struct k_ipi_work; + +/** + * @cond INTERNAL_HIDDEN + */ + +typedef void (*k_ipi_func_t)(struct k_ipi_work *work); + +struct k_ipi_work { + sys_dnode_t node[CONFIG_MP_MAX_NUM_CPUS]; /* Node in IPI work queue */ + k_ipi_func_t func; /* Function to execute on target CPU */ + struct k_event event; /* Event to signal when processed */ + uint32_t bitmask; /* Bitmask of targeted CPUs */ +}; + +/** @endcond */ + +/** + * @brief Initialize the specified IPI work item + * + * @kconfig_dep{CONFIG_SCHED_IPI_SUPPORTED} + * + * @param work Pointer to the IPI work item to be initialized + */ +static inline void k_ipi_work_init(struct k_ipi_work *work) +{ + k_event_init(&work->event); + for (unsigned int i = 0; i < CONFIG_MP_MAX_NUM_CPUS; i++) { + sys_dnode_init(&work->node[i]); + } + work->bitmask = 0; +} + +/** + * @brief Add an IPI work item to the IPI work queue + * + * Adds the specified IPI work item to the IPI work queues of each CPU + * identified by @a cpu_bitmask. The specified IPI work item will subsequently + * execute at ISR level as those CPUs process their received IPIs. Do not + * re-use the specified IPI work item until it has been processed by all of + * the identified CPUs. + * + * @kconfig_dep{CONFIG_SCHED_IPI_SUPPORTED} + * + * @param work Pointer to the IPI work item + * @param cpu_bitmask Set of CPUs to which the IPI work item will be sent + * @param func Function to execute on the targeted CPU(s) + * + * @retval 0 on success + * @retval -EBUSY if the specified IPI work item is still being processed + */ +int k_ipi_work_add(struct k_ipi_work *work, uint32_t cpu_bitmask, + k_ipi_func_t func); + +/** + * @brief Wait until the IPI work item has been processed by all targeted CPUs + * + * This routine waits until the IPI work item has been processed by all CPUs + * to which it was sent. If called from an ISR, then @a timeout must be set to + * K_NO_WAIT. To prevent deadlocks the caller must not have IRQs locked when + * calling this function. + * + * @note It is not in general possible to poll safely for completion of this + * function in ISR or locked contexts where the calling CPU cannot service IPIs + * (because the targeted CPUs may themselves be waiting on the calling CPU). + * Application code must be prepared for failure or to poll from a thread + * context. + * + * @kconfig_dep{CONFIG_SCHED_IPI_SUPPORTED} + * + * @param work Pointer to the IPI work item + * @param timeout Maximum time to wait for IPI work to be processed + * + * @retval -EAGAIN Waiting period timed out. + * @retval 0 if processed by all targeted CPUs + */ +int k_ipi_work_wait(struct k_ipi_work *work, k_timeout_t timeout); + +/** + * @brief Signal that there is one or more IPI work items to process + * + * This routine sends an IPI to the set of CPUs identified by calls to + * k_ipi_work_add() since this CPU sent its last set of IPIs. + * + * @kconfig_dep{CONFIG_SCHED_IPI_SUPPORTED} + */ +void k_ipi_work_signal(void); + +#endif /* CONFIG_SCHED_IPI_SUPPORTED */ + /** * @cond INTERNAL_HIDDEN */ @@ -5120,206 +5257,6 @@ void k_mbox_data_get(struct k_mbox_msg *rx_msg, void *buffer); */ __syscall void k_pipe_init(struct k_pipe *pipe, uint8_t *buffer, size_t buffer_size); -#ifdef CONFIG_PIPES -/** Pipe Structure */ -struct k_pipe { - unsigned char *buffer; /**< Pipe buffer: may be NULL */ - size_t size; /**< Buffer size */ - size_t bytes_used; /**< Number of bytes used in buffer */ - size_t read_index; /**< Where in buffer to read from */ - size_t write_index; /**< Where in buffer to write */ - struct k_spinlock lock; /**< Synchronization lock */ - - struct { - _wait_q_t readers; /**< Reader wait queue */ - _wait_q_t writers; /**< Writer wait queue */ - } wait_q; /** Wait queue */ - - Z_DECL_POLL_EVENT - - uint8_t flags; /**< Flags */ - - SYS_PORT_TRACING_TRACKING_FIELD(k_pipe) - -#ifdef CONFIG_OBJ_CORE_PIPE - struct k_obj_core obj_core; -#endif -}; - -/** - * @cond INTERNAL_HIDDEN - */ -#define K_PIPE_FLAG_ALLOC BIT(0) /** Buffer was allocated */ - -#define Z_PIPE_INITIALIZER(obj, pipe_buffer, pipe_buffer_size) \ - { \ - .buffer = pipe_buffer, \ - .size = pipe_buffer_size, \ - .bytes_used = 0, \ - .read_index = 0, \ - .write_index = 0, \ - .lock = {}, \ - .wait_q = { \ - .readers = Z_WAIT_Q_INIT(&obj.wait_q.readers), \ - .writers = Z_WAIT_Q_INIT(&obj.wait_q.writers) \ - }, \ - Z_POLL_EVENT_OBJ_INIT(obj) \ - .flags = 0, \ - } - -/** - * INTERNAL_HIDDEN @endcond - */ - -/** - * @brief Statically define and initialize a pipe. - * - * The pipe can be accessed outside the module where it is defined using: - * - * @code extern struct k_pipe ; @endcode - * - * @param name Name of the pipe. - * @param pipe_buffer_size Size of the pipe's ring buffer (in bytes), - * or zero if no ring buffer is used. - * @param pipe_align Alignment of the pipe's ring buffer (power of 2). - * - */ -#define K_PIPE_DEFINE(name, pipe_buffer_size, pipe_align) \ - static unsigned char __noinit __aligned(pipe_align) \ - _k_pipe_buf_##name[pipe_buffer_size]; \ - STRUCT_SECTION_ITERABLE(k_pipe, name) = \ - Z_PIPE_INITIALIZER(name, _k_pipe_buf_##name, pipe_buffer_size) - -/** - * @deprecated Dynamic allocation of pipe buffers will be removed in the new k_pipe API. - * @brief Release a pipe's allocated buffer - * - * If a pipe object was given a dynamically allocated buffer via - * k_pipe_alloc_init(), this will free it. This function does nothing - * if the buffer wasn't dynamically allocated. - * - * @param pipe Address of the pipe. - * @retval 0 on success - * @retval -EAGAIN nothing to cleanup - */ -__deprecated int k_pipe_cleanup(struct k_pipe *pipe); - -/** - * @deprecated Dynamic allocation of pipe buffers will be removed in the new k_pipe API. - * @brief Initialize a pipe and allocate a buffer for it - * - * Storage for the buffer region will be allocated from the calling thread's - * resource pool. This memory will be released if k_pipe_cleanup() is called, - * or userspace is enabled and the pipe object loses all references to it. - * - * This function should only be called on uninitialized pipe objects. - * - * @param pipe Address of the pipe. - * @param size Size of the pipe's ring buffer (in bytes), or zero if no ring - * buffer is used. - * @retval 0 on success - * @retval -ENOMEM if memory couldn't be allocated - */ -__deprecated __syscall int k_pipe_alloc_init(struct k_pipe *pipe, size_t size); - -/** - * @deprecated k_pipe_put() is replaced by k_pipe_write(...) in the new k_pipe API. - * @brief Write data to a pipe. - * - * This routine writes up to @a bytes_to_write bytes of data to @a pipe. - * - * @param pipe Address of the pipe. - * @param data Address of data to write. - * @param bytes_to_write Size of data (in bytes). - * @param bytes_written Address of area to hold the number of bytes written. - * @param min_xfer Minimum number of bytes to write. - * @param timeout Waiting period to wait for the data to be written, - * or one of the special values K_NO_WAIT and K_FOREVER. - * - * @retval 0 At least @a min_xfer bytes of data were written. - * @retval -EIO Returned without waiting; zero data bytes were written. - * @retval -EAGAIN Waiting period timed out; between zero and @a min_xfer - * minus one data bytes were written. - */ -__deprecated __syscall int k_pipe_put(struct k_pipe *pipe, const void *data, - size_t bytes_to_write, size_t *bytes_written, - size_t min_xfer, k_timeout_t timeout); - -/** - * @deprecated k_pipe_get() is replaced by k_pipe_read(...) in the new k_pipe API. - * @brief Read data from a pipe. - * - * This routine reads up to @a bytes_to_read bytes of data from @a pipe. - * - * @param pipe Address of the pipe. - * @param data Address to place the data read from pipe. - * @param bytes_to_read Maximum number of data bytes to read. - * @param bytes_read Address of area to hold the number of bytes read. - * @param min_xfer Minimum number of data bytes to read. - * @param timeout Waiting period to wait for the data to be read, - * or one of the special values K_NO_WAIT and K_FOREVER. - * - * @retval 0 At least @a min_xfer bytes of data were read. - * @retval -EINVAL invalid parameters supplied - * @retval -EIO Returned without waiting; zero data bytes were read. - * @retval -EAGAIN Waiting period timed out; between zero and @a min_xfer - * minus one data bytes were read. - */ -__deprecated __syscall int k_pipe_get(struct k_pipe *pipe, void *data, - size_t bytes_to_read, size_t *bytes_read, - size_t min_xfer, k_timeout_t timeout); - -/** - * @deprecated k_pipe_read_avail() will be removed in the new k_pipe API. - * @brief Query the number of bytes that may be read from @a pipe. - * - * @param pipe Address of the pipe. - * - * @retval a number n such that 0 <= n <= @ref k_pipe.size; the - * result is zero for unbuffered pipes. - */ -__deprecated __syscall size_t k_pipe_read_avail(struct k_pipe *pipe); - -/** - * @deprecated k_pipe_write_avail() will be removed in the new k_pipe API. - * @brief Query the number of bytes that may be written to @a pipe - * - * @param pipe Address of the pipe. - * - * @retval a number n such that 0 <= n <= @ref k_pipe.size; the - * result is zero for unbuffered pipes. - */ -__deprecated __syscall size_t k_pipe_write_avail(struct k_pipe *pipe); - -/** - * @deprecated k_pipe_flush() will be removed in the new k_pipe API. - * @brief Flush the pipe of write data - * - * This routine flushes the pipe. Flushing the pipe is equivalent to reading - * both all the data in the pipe's buffer and all the data waiting to go into - * that pipe into a large temporary buffer and discarding the buffer. Any - * writers that were previously pended become unpended. - * - * @param pipe Address of the pipe. - */ -__deprecated __syscall void k_pipe_flush(struct k_pipe *pipe); - -/** - * @deprecated k_pipe_buffer_flush will be removed in the new k_pipe API. - * @brief Flush the pipe's internal buffer - * - * This routine flushes the pipe's internal buffer. This is equivalent to - * reading up to N bytes from the pipe (where N is the size of the pipe's - * buffer) into a temporary buffer and then discarding that buffer. If there - * were writers previously pending, then some may unpend as they try to fill - * up the pipe's emptied buffer. - * - * @param pipe Address of the pipe. - */ -__deprecated __syscall void k_pipe_buffer_flush(struct k_pipe *pipe); - -#else /* CONFIG_PIPES */ - enum pipe_flags { PIPE_FLAG_OPEN = BIT(0), PIPE_FLAG_RESET = BIT(1), @@ -5345,11 +5282,11 @@ struct k_pipe { */ #define Z_PIPE_INITIALIZER(obj, pipe_buffer, pipe_buffer_size) \ { \ + .waiting = 0, \ .buf = RING_BUF_INIT(pipe_buffer, pipe_buffer_size), \ .data = Z_WAIT_Q_INIT(&obj.data), \ .space = Z_WAIT_Q_INIT(&obj.space), \ .flags = PIPE_FLAG_OPEN, \ - .waiting = 0, \ Z_POLL_EVENT_OBJ_INIT(obj) \ } /** @@ -5433,7 +5370,6 @@ __syscall void k_pipe_reset(struct k_pipe *pipe); * @param pipe Address of the pipe. */ __syscall void k_pipe_close(struct k_pipe *pipe); -#endif /* CONFIG_PIPES */ /** @} */ /** diff --git a/include/zephyr/kernel/thread.h b/include/zephyr/kernel/thread.h index ae43d71115d7b..43721f1249534 100644 --- a/include/zephyr/kernel/thread.h +++ b/include/zephyr/kernel/thread.h @@ -42,18 +42,6 @@ struct __thread_entry { struct k_thread; -/* - * This _pipe_desc structure is used by the pipes kernel module when - * CONFIG_PIPES has been selected. - */ - -struct _pipe_desc { - sys_dnode_t node; - unsigned char *buffer; /* Position in src/dest buffer */ - size_t bytes_to_xfer; /* # bytes left to transfer */ - struct k_thread *thread; /* Back pointer to pended thread */ -}; - /* can be used for creating 'dummy' threads, e.g. for pending on objects */ struct _thread_base { @@ -279,7 +267,7 @@ struct k_thread { #if defined(CONFIG_EVENTS) struct k_thread *next_event_link; - uint32_t events; + uint32_t events; /* dual purpose - wait on and then received */ uint32_t event_options; /** true if timeout should not wake the thread */ @@ -361,11 +349,6 @@ struct k_thread { struct k_mem_paging_stats_t paging_stats; #endif /* CONFIG_DEMAND_PAGING_THREAD_STATS */ -#ifdef CONFIG_PIPES - /** Pipe descriptor used with blocking k_pipe operations */ - struct _pipe_desc pipe_desc; -#endif /* CONFIG_PIPES */ - #ifdef CONFIG_OBJ_CORE_THREAD struct k_obj_core obj_core; #endif /* CONFIG_OBJ_CORE_THREAD */ diff --git a/include/zephyr/kernel/thread_stack.h b/include/zephyr/kernel/thread_stack.h index 2989624e04367..7857a6f31e27e 100644 --- a/include/zephyr/kernel/thread_stack.h +++ b/include/zephyr/kernel/thread_stack.h @@ -112,6 +112,156 @@ static inline char *z_stack_ptr_align(char *ptr) * @{ */ +#ifdef CONFIG_HW_SHADOW_STACK +/** + * @typedef k_thread_hw_shadow_stack_t + * @brief Typedef of arch_thread_hw_shadow_stack_t + * + * This is an opaque type that represents a hardware shadow stack. + * The architecture implementation defines the actual type. + */ +#define k_thread_hw_shadow_stack_t arch_thread_hw_shadow_stack_t + +/** + * @brief Calculate the size of a hardware shadow stack + * + * This macro calculates the size to be allocated for a hardware shadow + * stack. It accepts the indicated "size" as a parameter and pads some + * extra bytes (e.g. for alignment). + * + * @param size Size of the shadow stack memory region + */ +#define K_THREAD_HW_SHADOW_STACK_SIZE(size_) \ + ARCH_THREAD_HW_SHADOW_STACK_SIZE(size_) + +/** + * @brief Declare a hardware shadow stack + * + * This macro declares the symbol of a hardware shadow stack defined + * elsewhere in the current scope. + * + * @param sym Hardware shadow stack symbol name + * @param size Size of the shadow stack memory region + */ +#define K_KERNEL_HW_SHADOW_STACK_DECLARE(sym, size) \ + ARCH_THREAD_HW_SHADOW_STACK_DECLARE(__ ## sym ## _shstk, size) + +/** + * @brief Declare a hardware shadow stack array + * + * This macro declares the symbol of a hardware shadow stack array defined + * elsewhere in the current scope. + * + * @param sym Hardware shadow stack array symbol name + * @param nmemb Number of stacks defined + * @param size Size of the shadow stack memory region + */ +#define K_KERNEL_HW_SHADOW_STACK_ARRAY_DECLARE(sym, nmemb, size) \ + ARCH_THREAD_HW_SHADOW_STACK_ARRAY_DECLARE(__ ## sym ## _shstk_arr, \ + nmemb, size) + +struct _stack_to_hw_shadow_stack { + k_thread_stack_t *stack; + k_thread_hw_shadow_stack_t *shstk_addr; + size_t size; +}; + + +/** + * @brief Define a hardware shadow stack + * + * This macro defines a hardware shadow stack. Note that an application + * usually doesn't have to define a hardware shadow stack directly, + * as it is automatically defined by the kernel when a thread stack is + * defined with K_THREAD_STACK_DEFINE(). + * + * @param sym Hardware shadow stack symbol name + * @param size Size of the shadow stack memory region + */ +#define K_THREAD_HW_SHADOW_STACK_DEFINE(sym, size_) \ + ARCH_THREAD_HW_SHADOW_STACK_DEFINE(__ ## sym ## _shstk, size_); \ + static const STRUCT_SECTION_ITERABLE(_stack_to_hw_shadow_stack, \ + sym ## _stack_to_shstk_attach) = { \ + .stack = sym, \ + .shstk_addr = __ ## sym ## _shstk, \ + .size = size_, \ + } + +struct _stack_to_hw_shadow_stack_arr { + uintptr_t stack_addr; + uintptr_t shstk_addr; + size_t stack_size; + size_t shstk_size; + size_t nmemb; +}; + +/** + * @brief Define a hardware shadow stack array + * + * This macro defines a hardware shadow stack array. Note that an application + * usually doesn't have to define a hardware shadow stack array directly, + * as it is automatically defined by the kernel when a thread stack array is + * defined with K_THREAD_STACK_ARRAY_DEFINE(). + * + * @param sym Hardware shadow stack array symbol name + * @param nmemb Number of stacks defined + * @param size Size of the shadow stack memory region + */ +#define K_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE(sym, nmemb_, size_) \ + ARCH_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE(__ ## sym ## _shstk_arr, nmemb_, \ + K_THREAD_HW_SHADOW_STACK_SIZE(size_)); \ + static const STRUCT_SECTION_ITERABLE(_stack_to_hw_shadow_stack_arr, \ + sym ## _stack_to_shstk_attach) = { \ + .stack_addr = (uintptr_t)sym, \ + .stack_size = K_KERNEL_STACK_LEN(size_), \ + .nmemb = nmemb_, \ + .shstk_addr = (uintptr_t)__ ## sym ## _shstk_arr, \ + .shstk_size = K_THREAD_HW_SHADOW_STACK_SIZE(size_), \ + } + +/** + * @brief Attach a hardware shadow stack to a thread + * + * This macro attaches a hardware shadow stack to a thread. Note that an + * application usually doesn't have to attach a hardware shadow stack + * directly, as it is automatically attached by the kernel when a thread + * is created. + */ +#define k_thread_hw_shadow_stack_attach arch_thread_hw_shadow_stack_attach + +struct _thread_hw_shadow_stack_static { + struct k_thread *thread; + k_thread_hw_shadow_stack_t *shstk_addr; + size_t size; +}; + +/** + * @brief Attach a hardware shadow stack to a thread + * + * This macro attaches a hardware shadow stack to a thread. Note that an + * application usually doesn't have to attach a hardware shadow stack + * directly, as it is automatically attached by the kernel when a thread + * is created. + * + * @param thread_ Thread to attach the hardware shadow stack to + * @param shstk_addr_ Address of the hardware shadow stack + * @param size_ Size of the hardware shadow stack memory region + */ +#define K_THREAD_HW_SHADOW_STACK_ATTACH(thread_, shstk_addr_, size_) \ + static const STRUCT_SECTION_ITERABLE(_thread_hw_shadow_stack_static, \ + thread ## _shstk_attach_static) = { \ + .thread = thread_, \ + .shstk_addr = shstk_addr_, \ + .size = size_, \ + } + +#else +#define K_KERNEL_HW_SHADOW_STACK_DECLARE(sym, size) +#define K_KERNEL_HW_SHADOW_STACK_ARRAY_DECLARE(sym, nmemb, size) +#define K_THREAD_HW_SHADOW_STACK_DEFINE(sym, size) +#define K_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE(sym, nmemb, size_) +#endif + /** * @brief Declare a reference to a thread stack * @@ -122,6 +272,7 @@ static inline char *z_stack_ptr_align(char *ptr) * @param size Size of the stack memory region */ #define K_KERNEL_STACK_DECLARE(sym, size) \ + K_KERNEL_HW_SHADOW_STACK_DECLARE(sym, K_THREAD_HW_SHADOW_STACK_SIZE(size)); \ extern struct z_thread_stack_element \ sym[K_KERNEL_STACK_LEN(size)] @@ -136,6 +287,7 @@ static inline char *z_stack_ptr_align(char *ptr) * @param size Size of the stack memory region */ #define K_KERNEL_STACK_ARRAY_DECLARE(sym, nmemb, size) \ + K_KERNEL_HW_SHADOW_STACK_ARRAY_DECLARE(sym, nmemb, K_THREAD_HW_SHADOW_STACK_SIZE(size)); \ extern struct z_thread_stack_element \ sym[nmemb][K_KERNEL_STACK_LEN(size)] @@ -150,6 +302,7 @@ static inline char *z_stack_ptr_align(char *ptr) * @param size Size of the stack memory region */ #define K_KERNEL_PINNED_STACK_ARRAY_DECLARE(sym, nmemb, size) \ + K_KERNEL_HW_SHADOW_STACK_ARRAY_DECLARE(sym, nmemb, K_THREAD_HW_SHADOW_STACK_SIZE(size)); \ extern struct z_thread_stack_element \ sym[nmemb][K_KERNEL_STACK_LEN(size)] @@ -212,7 +365,9 @@ static inline char *z_stack_ptr_align(char *ptr) * @param size Size of the stack memory region */ #define K_KERNEL_STACK_DEFINE(sym, size) \ - Z_KERNEL_STACK_DEFINE_IN(sym, size, __kstackmem) + Z_KERNEL_STACK_DEFINE_IN(sym, size, __kstackmem); \ + K_THREAD_HW_SHADOW_STACK_DEFINE(sym, \ + K_THREAD_HW_SHADOW_STACK_SIZE(size)) /** * @brief Define a toplevel kernel stack memory region in pinned section @@ -228,10 +383,14 @@ static inline char *z_stack_ptr_align(char *ptr) */ #if defined(CONFIG_LINKER_USE_PINNED_SECTION) #define K_KERNEL_PINNED_STACK_DEFINE(sym, size) \ - Z_KERNEL_STACK_DEFINE_IN(sym, size, __pinned_noinit) + Z_KERNEL_STACK_DEFINE_IN(sym, size, __pinned_noinit); \ + K_THREAD_HW_SHADOW_STACK_DEFINE(sym, \ + K_THREAD_HW_SHADOW_STACK_SIZE(size)) #else #define K_KERNEL_PINNED_STACK_DEFINE(sym, size) \ - Z_KERNEL_STACK_DEFINE_IN(sym, size, __kstackmem) + Z_KERNEL_STACK_DEFINE_IN(sym, size, __kstackmem); \ + K_THREAD_HW_SHADOW_STACK_DEFINE(sym, \ + K_THREAD_HW_SHADOW_STACK_SIZE(size)) #endif /* CONFIG_LINKER_USE_PINNED_SECTION */ /** @@ -244,7 +403,9 @@ static inline char *z_stack_ptr_align(char *ptr) * @param size Size of the stack memory region */ #define K_KERNEL_STACK_ARRAY_DEFINE(sym, nmemb, size) \ - Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, __kstackmem) + Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, __kstackmem); \ + K_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE(sym, nmemb, size) + /** * @brief Define a toplevel array of kernel stack memory regions in pinned section @@ -261,10 +422,12 @@ static inline char *z_stack_ptr_align(char *ptr) */ #if defined(CONFIG_LINKER_USE_PINNED_SECTION) #define K_KERNEL_PINNED_STACK_ARRAY_DEFINE(sym, nmemb, size) \ - Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, __pinned_noinit) + Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, __pinned_noinit); \ + K_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE(sym, nmemb, size) #else #define K_KERNEL_PINNED_STACK_ARRAY_DEFINE(sym, nmemb, size) \ - Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, __kstackmem) + Z_KERNEL_STACK_ARRAY_DEFINE_IN(sym, nmemb, size, __kstackmem); \ + K_THREAD_HW_SHADOW_STACK_ARRAY_DEFINE(sym, nmemb, size) #endif /* CONFIG_LINKER_USE_PINNED_SECTION */ /** diff --git a/include/zephyr/kernel_structs.h b/include/zephyr/kernel_structs.h index 5bf9ae6df1c50..be883530b842a 100644 --- a/include/zephyr/kernel_structs.h +++ b/include/zephyr/kernel_structs.h @@ -196,6 +196,10 @@ struct _cpu { struct k_obj_core obj_core; #endif +#ifdef CONFIG_SCHED_IPI_SUPPORTED + sys_dlist_t ipi_workq; +#endif + /* Per CPU architecture specifics */ struct _cpu_arch arch; }; diff --git a/include/zephyr/linker/common-ram.ld b/include/zephyr/linker/common-ram.ld index 792574c9d37a2..c85bdce6c7093 100644 --- a/include/zephyr/linker/common-ram.ld +++ b/include/zephyr/linker/common-ram.ld @@ -126,6 +126,7 @@ ITERABLE_SECTION_RAM(scmi_protocol, Z_LINK_ITERABLE_SUBALIGN) #if defined(CONFIG_RTIO) ITERABLE_SECTION_RAM(rtio, Z_LINK_ITERABLE_SUBALIGN) + ITERABLE_SECTION_RAM(rtio_pool, Z_LINK_ITERABLE_SUBALIGN) ITERABLE_SECTION_RAM(rtio_iodev, Z_LINK_ITERABLE_SUBALIGN) ITERABLE_SECTION_RAM(rtio_sqe_pool, Z_LINK_ITERABLE_SUBALIGN) ITERABLE_SECTION_RAM(rtio_cqe_pool, Z_LINK_ITERABLE_SUBALIGN) diff --git a/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld b/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld index 94a1e8365eb1c..716a845134c36 100644 --- a/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld +++ b/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld @@ -100,4 +100,9 @@ } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) #endif /* !CONFIG_DEVICE_DEPS_DYNAMIC */ +#ifdef CONFIG_HW_SHADOW_STACK + ITERABLE_SECTION_ROM(_stack_to_hw_shadow_stack, Z_LINK_ITERABLE_SUBALIGN) + ITERABLE_SECTION_ROM(_stack_to_hw_shadow_stack_arr, Z_LINK_ITERABLE_SUBALIGN) +#endif + #include diff --git a/include/zephyr/linker/linker-defs.h b/include/zephyr/linker/linker-defs.h index 397c3181dd2ed..635b418897c83 100644 --- a/include/zephyr/linker/linker-defs.h +++ b/include/zephyr/linker/linker-defs.h @@ -131,11 +131,11 @@ extern char __kernel_ram_start[]; extern char __kernel_ram_end[]; extern char __kernel_ram_size[]; -/* Used by z_bss_zero or arch-specific implementation */ +/* Used by arch_bss_zero or arch-specific implementation */ extern char __bss_start[]; extern char __bss_end[]; -/* Used by z_data_copy() or arch-specific implementation */ +/* Used by arch_data_copy() or arch-specific implementation */ #ifdef CONFIG_XIP extern char __data_region_load_start[]; extern char __data_region_start[]; @@ -246,14 +246,21 @@ extern char __sg_size[]; * with a MPU. Start and end will be aligned for memory management/protection * hardware for the target architecture. * - * All the functions with '__nocache' keyword will be placed into this - * section. + * All the variables with '__nocache' keyword will be placed into the nocache + * section, variables with '__nocache_load' keyword will be placed into the + * nocache section that is loaded from ROM. */ #ifdef CONFIG_NOCACHE_MEMORY extern char _nocache_ram_start[]; extern char _nocache_ram_end[]; extern char _nocache_ram_size[]; -extern char _nocache_load_start[]; +extern char _nocache_noload_ram_start[]; +extern char _nocache_noload_ram_end[]; +extern char _nocache_noload_ram_size[]; +extern char _nocache_load_ram_start[]; +extern char _nocache_load_ram_end[]; +extern char _nocache_load_ram_size[]; +extern char _nocache_load_rom_start[]; #endif /* CONFIG_NOCACHE_MEMORY */ /* Memory owned by the kernel. Start and end will be aligned for memory diff --git a/include/zephyr/linker/section_tags.h b/include/zephyr/linker/section_tags.h index ab73c0445016f..e0124575b6667 100644 --- a/include/zephyr/linker/section_tags.h +++ b/include/zephyr/linker/section_tags.h @@ -53,9 +53,11 @@ #if defined(CONFIG_NOCACHE_MEMORY) #define __nocache __in_section_unique(_NOCACHE_SECTION_NAME) +#define __nocache_load __in_section_unique(_NOCACHE_LOAD_SECTION_NAME) #define __nocache_noinit __nocache #else #define __nocache +#define __nocache_load #define __nocache_noinit __noinit #endif /* CONFIG_NOCACHE_MEMORY */ diff --git a/include/zephyr/linker/sections.h b/include/zephyr/linker/sections.h index dc6fce72e6be6..ef9f4463bea5c 100644 --- a/include/zephyr/linker/sections.h +++ b/include/zephyr/linker/sections.h @@ -77,6 +77,7 @@ #ifdef CONFIG_NOCACHE_MEMORY #define _NOCACHE_SECTION_NAME nocache +#define _NOCACHE_LOAD_SECTION_NAME nocache_load #endif /* Symbol table section */ diff --git a/include/zephyr/logging/log_backend_net.h b/include/zephyr/logging/log_backend_net.h index 4aafb1deb7f57..71b22e1e0e9e0 100644 --- a/include/zephyr/logging/log_backend_net.h +++ b/include/zephyr/logging/log_backend_net.h @@ -65,7 +65,7 @@ bool log_backend_net_set_ip(const struct sockaddr *addr); * @param len Length of the hostname array. */ #if defined(CONFIG_NET_HOSTNAME_ENABLE) -void log_backend_net_hostname_set(char *hostname, size_t len); +void log_backend_net_hostname_set(const char *hostname, size_t len); #else static inline void log_backend_net_hostname_set(const char *hostname, size_t len) { diff --git a/include/zephyr/lorawan/lorawan.h b/include/zephyr/lorawan/lorawan.h index 9f8688189cbe8..21df1ceb28d31 100644 --- a/include/zephyr/lorawan/lorawan.h +++ b/include/zephyr/lorawan/lorawan.h @@ -454,18 +454,19 @@ int lorawan_device_time_get(uint32_t *gps_time); */ int lorawan_request_link_check(bool force_request); -#ifdef CONFIG_LORAWAN_APP_CLOCK_SYNC - /** * @brief Run Application Layer Clock Synchronization service * * This service sends out its current time in a regular interval (configurable - * via Kconfig) and receives a correction offset from the application server if - * the clock deviation is considered too large. + * via Kconfig, using @kconfig{CONFIG_LORAWAN_APP_CLOCK_SYNC_PERIODICITY}) and + * receives a correction offset from the application server if the clock + * deviation is considered too large. * * Clock synchronization is required for firmware upgrades over multicast * sessions, but can also be used independent of a FUOTA process. * + * @kconfig_dep{CONFIG_LORAWAN_APP_CLOCK_SYNC} + * * @return 0 if successful, negative errno otherwise. */ int lorawan_clock_sync_run(void); @@ -478,16 +479,14 @@ int lorawan_clock_sync_run(void); * The GPS epoch started on 1980-01-06T00:00:00Z, but has since diverged * from UTC, as it does not consider corrections like leap seconds. * + * @kconfig_dep{CONFIG_LORAWAN_APP_CLOCK_SYNC} + * * @param gps_time Synchronized time in GPS epoch format truncated to 32-bit. * * @return 0 if successful, -EAGAIN if the clock is not yet synchronized. */ int lorawan_clock_sync_get(uint32_t *gps_time); -#endif /* CONFIG_LORAWAN_APP_CLOCK_SYNC */ - -#ifdef CONFIG_LORAWAN_FRAG_TRANSPORT - /** * @brief Register a handle descriptor callback function. * @@ -495,7 +494,9 @@ int lorawan_clock_sync_get(uint32_t *gps_time); * whenever a FragSessionSetupReq is received and Descriptor field should be * handled. * - * @param transport_descriptor_cb Callback for notification. + * @kconfig_dep{CONFIG_LORAWAN_FRAG_TRANSPORT} + * + * @param cb Callback for notification. */ void lorawan_frag_transport_register_descriptor_callback(transport_descriptor_cb cb); @@ -507,14 +508,14 @@ void lorawan_frag_transport_register_descriptor_callback(transport_descriptor_cb * * After all fragments have been received, the provided callback is invoked. * + * @kconfig_dep{CONFIG_LORAWAN_FRAG_TRANSPORT} + * * @param transport_finished_cb Callback for notification of finished data transfer. * * @return 0 if successful, negative errno otherwise. */ int lorawan_frag_transport_run(void (*transport_finished_cb)(void)); -#endif /* CONFIG_LORAWAN_FRAG_TRANSPORT */ - #ifdef __cplusplus } #endif diff --git a/include/zephyr/mgmt/ec_host_cmd/backend.h b/include/zephyr/mgmt/ec_host_cmd/backend.h index 66f04e97868f4..d917a56e0874a 100644 --- a/include/zephyr/mgmt/ec_host_cmd/backend.h +++ b/include/zephyr/mgmt/ec_host_cmd/backend.h @@ -7,11 +7,19 @@ /** * @file * @brief Public APIs for Host Command backends that respond to host commands + * @ingroup ec_host_cmd_backend */ #ifndef ZEPHYR_INCLUDE_MGMT_EC_HOST_CMD_BACKEND_H_ #define ZEPHYR_INCLUDE_MGMT_EC_HOST_CMD_BACKEND_H_ +/** + * @brief Interface to EC Host Command backends + * @defgroup ec_host_cmd_backend Backends + * @ingroup ec_host_cmd_interface + * @{ + */ + #include #include #include @@ -22,20 +30,16 @@ extern "C" { #endif +/** + * @brief EC Host Command Backend + */ struct ec_host_cmd_backend { - /** API provided by the backed. */ + /** API provided by the backend. */ const struct ec_host_cmd_backend_api *api; - /** Context for the backed. */ + /** Context for the backend. */ void *ctx; }; -/** - * @brief EC Host Command Interface - * @defgroup ec_host_cmd_interface EC Host Command Interface - * @ingroup io_interfaces - * @{ - */ - /** * @brief Context for host command backend and handler to pass rx data. */ @@ -58,7 +62,7 @@ struct ec_host_cmd_rx_ctx { */ struct ec_host_cmd_tx_buf { /** - * Data to write to the host The buffer is provided by the handler if + * Data to write to the host. The buffer is provided by the handler if * CONFIG_EC_HOST_CMD_HANDLER_TX_BUFFER_SIZE > 0. Otherwise, the backend should provide * the buffer on its own and overwrites @a buf pointer and @a len_max * in the init function. @@ -158,6 +162,14 @@ struct ec_host_cmd_backend *ec_host_cmd_backend_get_uart(const struct device *de */ struct ec_host_cmd_backend *ec_host_cmd_backend_get_spi(struct gpio_dt_spec *cs); +/** + * @brief Signal event over USB + * + * Signal event using USB interrupt endpoint. It informs host that there is a pending event that has + * to be handled. The function performs remote wake-up if needed. + */ +void ec_host_cmd_backend_usb_trigger_event(void); + /** * @} */ diff --git a/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h b/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h index 9a01116c9e4af..f08639383bc7c 100644 --- a/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h +++ b/include/zephyr/mgmt/ec_host_cmd/ec_host_cmd.h @@ -12,7 +12,7 @@ * @defgroup ec_host_cmd_interface EC Host Command Interface * @since 2.4 * @version 0.1.0 - * @ingroup io_interfaces + * @ingroup device_mgmt * @{ */ @@ -72,24 +72,54 @@ enum ec_host_cmd_status { EC_HOST_CMD_MAX = UINT16_MAX /* Force enum to be 16 bits. */ } __packed; +/** + * @brief Host command log levels + */ enum ec_host_cmd_log_level { - EC_HOST_CMD_DEBUG_OFF, /* No Host Command debug output */ - EC_HOST_CMD_DEBUG_NORMAL, /* Normal output mode; skips repeated commands */ - EC_HOST_CMD_DEBUG_EVERY, /* Print every command */ - EC_HOST_CMD_DEBUG_PARAMS, /* ... and print params for request/response */ - EC_HOST_CMD_DEBUG_MODES /* Number of host command debug modes */ + EC_HOST_CMD_DEBUG_OFF, /**< No Host Command debug output */ + EC_HOST_CMD_DEBUG_NORMAL, /**< Normal output mode; skips repeated commands */ + EC_HOST_CMD_DEBUG_EVERY, /**< Print every command */ + EC_HOST_CMD_DEBUG_PARAMS, /**< ... and print params for request/response */ + EC_HOST_CMD_DEBUG_MODES /**< Number of host command debug modes */ }; +/** + * @brief Host command state + */ enum ec_host_cmd_state { - EC_HOST_CMD_STATE_DISABLED = 0, - EC_HOST_CMD_STATE_RECEIVING, - EC_HOST_CMD_STATE_PROCESSING, - EC_HOST_CMD_STATE_SENDING, + EC_HOST_CMD_STATE_DISABLED = 0, /**< Host command subsystem is disabled */ + EC_HOST_CMD_STATE_RECEIVING, /**< Receiving command data from host */ + EC_HOST_CMD_STATE_PROCESSING, /**< Processing received command */ + EC_HOST_CMD_STATE_SENDING, /**< Sending response to host */ }; +/** + * @brief User callback function type for host command reception + * + * This callback is invoked after a host command is received and validated + * but before command processing begins. It allows user code to perform + * custom actions based on the received command. + * + * @param rx_ctx Pointer to the receive context containing command data + * @param user_data User-defined data pointer passed during callback registration + */ typedef void (*ec_host_cmd_user_cb_t)(const struct ec_host_cmd_rx_ctx *rx_ctx, void *user_data); + +/** + * @brief In-progress callback function type + * + * This callback is executed asynchronously for commands that return + * EC_HOST_CMD_IN_PROGRESS status. It allows long-running operations + * to complete in the background. + * + * @param user_data User-provided data passed to the callback + * @return Final status code for the command + */ typedef enum ec_host_cmd_status (*ec_host_cmd_in_progress_cb_t)(void *user_data); +/** + * Host command context structure + */ struct ec_host_cmd { struct ec_host_cmd_rx_ctx rx_ctx; struct ec_host_cmd_tx_buf tx; @@ -138,7 +168,19 @@ struct ec_host_cmd_handler_args { uint16_t output_buf_size; }; +/** + * @brief Host command handler callback function type + * + * This callback is invoked to process a host command that matches the handler's + * command ID and version. The handler processes the incoming command data and + * generates a response. + * + * @param args Pointer to an @ref ec_host_cmd_handler_args structure containing command data and + * buffers + * @return Status code indicating the result of command processing + */ typedef enum ec_host_cmd_status (*ec_host_cmd_handler_cb)(struct ec_host_cmd_handler_args *args); + /** * @brief Structure use for statically registering host command handlers */ @@ -334,38 +376,44 @@ const struct ec_host_cmd *ec_host_cmd_get_hc(void); FUNC_NORETURN void ec_host_cmd_task(void); #endif -#ifdef CONFIG_EC_HOST_CMD_IN_PROGRESS_STATUS +#if defined(CONFIG_EC_HOST_CMD_IN_PROGRESS_STATUS) || defined(__DOXYGEN__) /** - * @brief Check if a Host Command that sent EC_HOST_CMD_IN_PROGRESS status has ended. + * @brief Check if a Host Command that sent @ref EC_HOST_CMD_IN_PROGRESS status has ended. + * + * A Host Command that sends @ref EC_HOST_CMD_IN_PROGRESS status doesn't send a final result. + * The final result can be obtained with the @ref ec_host_cmd_send_in_progress_status function. * - * A Host Command that sends EC_HOST_CMD_IN_PROGRESS status doesn't send a final result. - * The final result can be get with the ec_host_cmd_send_in_progress_status function. + * @kconfig_dep{CONFIG_EC_HOST_CMD_IN_PROGRESS_STATUS} * * @retval true if the Host Command endded */ bool ec_host_cmd_send_in_progress_ended(void); /** - * @brief Get final result of a last Host Command that has sent EC_HOST_CMD_IN_PROGRESS status. + * @brief Get final result of a last Host Command that has sent @ref EC_HOST_CMD_IN_PROGRESS status. * - * A Host Command that sends EC_HOST_CMD_IN_PROGRESS status doesn't send a final result. - * Get the saved status with this function. The status can be get only once. Further calls return - * EC_HOST_CMD_UNAVAILABLE. + * A Host Command that sends @ref EC_HOST_CMD_IN_PROGRESS status doesn't send a final result. + * Get the saved status with this function. The status can be obtained only once. Further calls + * return @ref EC_HOST_CMD_UNAVAILABLE. * * Saving status of Host Commands that send response data is not supported. * + * @kconfig_dep{CONFIG_EC_HOST_CMD_IN_PROGRESS_STATUS} + * * @retval The final status or EC_HOST_CMD_UNAVAILABLE if not available. */ enum ec_host_cmd_status ec_host_cmd_send_in_progress_status(void); /** - * @brief Continue processing a handler in callback after returning EC_HOST_CMD_IN_PROGRESS. + * @brief Continue processing a handler in callback after returning @ref EC_HOST_CMD_IN_PROGRESS. + * + * A Host Command handler may return the @ref EC_HOST_CMD_IN_PROGRESS, but needs to continue work. + * This function should be called before returning @ref EC_HOST_CMD_IN_PROGRESS with a callback that + * will be executed. The return status of the callback will be stored and can be obtained with the + * @ref ec_host_cmd_send_in_progress_status function. The @ref ec_host_cmd_send_in_progress_ended + * function can be used to check if the callback has ended. * - * A Host Command handler may return the EC_HOST_CMD_IN_PROGRESS, but needs to continue work. - * This function should be called before returning EC_HOST_CMD_IN_PROGRESS with a callback that - * will be executed. The return status of the callback will be stored and can be get with the - * ec_host_cmd_send_in_progress_status function. The ec_host_cmd_send_in_progress_ended function - * can be used to check if the callback has ended. + * @kconfig_dep{CONFIG_EC_HOST_CMD_IN_PROGRESS_STATUS} * * @param[in] cb A callback to be called after returning from a command handler. * @param[in] user_data User data to be passed to the callback. diff --git a/include/zephyr/mgmt/ec_host_cmd/simulator.h b/include/zephyr/mgmt/ec_host_cmd/simulator.h index f6110740a9f30..3fe1afd13951e 100644 --- a/include/zephyr/mgmt/ec_host_cmd/simulator.h +++ b/include/zephyr/mgmt/ec_host_cmd/simulator.h @@ -4,13 +4,21 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_MGMT_EC_HOST_CMD_SIMULATOR_H_ -#define ZEPHYR_INCLUDE_MGMT_EC_HOST_CMD_SIMULATOR_H_ - /** * @file * @brief Header for commands to interact with the simulator outside of normal * device interface. + * @ingroup ec_host_cmd_simulator + */ + +#ifndef ZEPHYR_INCLUDE_MGMT_EC_HOST_CMD_SIMULATOR_H_ +#define ZEPHYR_INCLUDE_MGMT_EC_HOST_CMD_SIMULATOR_H_ + +/** + * @brief Interface to EC Host Command Simulator + * @defgroup ec_host_cmd_simulator Simulator + * @ingroup ec_host_cmd_interface + * @{ */ /* For ec_host_cmd_backend_api_send function pointer type */ @@ -45,4 +53,8 @@ void ec_host_cmd_backend_sim_install_send_cb(ec_host_cmd_backend_api_send cb, */ int ec_host_cmd_backend_sim_data_received(const uint8_t *buffer, size_t len); +/** + * @} + */ + #endif /* ZEPHYR_INCLUDE_MGMT_EC_HOST_CMD_SIMULATOR_H_ */ diff --git a/include/zephyr/modbus/modbus.h b/include/zephyr/modbus/modbus.h index 89b0727f10228..1b49fb782b4db 100644 --- a/include/zephyr/modbus/modbus.h +++ b/include/zephyr/modbus/modbus.h @@ -23,7 +23,7 @@ /** * @brief MODBUS transport protocol API * @defgroup modbus MODBUS - * @ingroup io_interfaces + * @ingroup connectivity * @{ */ diff --git a/include/zephyr/modem/chat.h b/include/zephyr/modem/chat.h index 0836451d689d4..5d10b433e5801 100644 --- a/include/zephyr/modem/chat.h +++ b/include/zephyr/modem/chat.h @@ -19,6 +19,15 @@ extern "C" { #endif +/** + * @brief Modem Chat + * @defgroup modem_chat Modem Chat + * @since 3.5 + * @version 1.0.0 + * @ingroup modem + * @{ + */ + struct modem_chat; /** @@ -82,6 +91,10 @@ struct modem_chat_match { #define MODEM_CHAT_MATCH_DEFINE(_sym, _match, _separators, _callback) \ const static struct modem_chat_match _sym = MODEM_CHAT_MATCH(_match, _separators, _callback) +#define MODEM_CHAT_MATCH_WILDCARD_DEFINE(_sym, _match, _separators, _callback) \ + const static struct modem_chat_match _sym = \ + MODEM_CHAT_MATCH_WILDCARD(_match, _separators, _callback) + /* Helper struct to match any response without callback. */ extern const struct modem_chat_match modem_chat_any_match; @@ -520,6 +533,10 @@ void modem_chat_script_set_callback(struct modem_chat_script *script, */ void modem_chat_script_set_timeout(struct modem_chat_script *script, uint32_t timeout_s); +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/include/zephyr/modem/cmux.h b/include/zephyr/modem/cmux.h index f1fa0beec32a5..3332c40bd18eb 100644 --- a/include/zephyr/modem/cmux.h +++ b/include/zephyr/modem/cmux.h @@ -37,6 +37,8 @@ extern "C" { /** * @brief Modem CMUX * @defgroup modem_cmux Modem CMUX + * @since 3.5 + * @version 1.0.0 * @ingroup modem * @{ */ diff --git a/include/zephyr/modem/pipe.h b/include/zephyr/modem/pipe.h index b91dfb505a4cb..5e95d1f809f7f 100644 --- a/include/zephyr/modem/pipe.h +++ b/include/zephyr/modem/pipe.h @@ -17,6 +17,8 @@ extern "C" { /** * @brief Modem Pipe * @defgroup modem_pipe Modem Pipe + * @since 3.5 + * @version 1.0.0 * @ingroup modem * @{ */ diff --git a/include/zephyr/modem/pipelink.h b/include/zephyr/modem/pipelink.h index ca788aaeefb7c..5cacd362e8f71 100644 --- a/include/zephyr/modem/pipelink.h +++ b/include/zephyr/modem/pipelink.h @@ -18,6 +18,8 @@ extern "C" { /** * @brief Modem pipelink * @defgroup modem_pipelink Modem pipelink + * @since 3.7 + * @version 1.0.0 * @ingroup modem * @{ */ diff --git a/include/zephyr/modem/ppp.h b/include/zephyr/modem/ppp.h index 799aac60b0b13..2b91e51a35c99 100644 --- a/include/zephyr/modem/ppp.h +++ b/include/zephyr/modem/ppp.h @@ -24,6 +24,8 @@ extern "C" { /** * @brief Modem PPP * @defgroup modem_ppp Modem PPP + * @since 3.5 + * @version 1.0.0 * @ingroup modem * @{ */ diff --git a/include/zephyr/modem/ubx.h b/include/zephyr/modem/ubx.h index fd4b05cea7475..2ad047a47bfa4 100644 --- a/include/zephyr/modem/ubx.h +++ b/include/zephyr/modem/ubx.h @@ -23,6 +23,8 @@ extern "C" { /** * @brief Modem Ubx * @defgroup modem_ubx Modem Ubx + * @since 3.7 + * @version 1.0.0 * @ingroup modem * @{ */ diff --git a/include/zephyr/net/dns_resolve.h b/include/zephyr/net/dns_resolve.h index be61a11ced7d4..3d5b6069a0c66 100644 --- a/include/zephyr/net/dns_resolve.h +++ b/include/zephyr/net/dns_resolve.h @@ -38,10 +38,16 @@ extern "C" { enum dns_query_type { /** IPv4 query */ DNS_QUERY_TYPE_A = 1, - /** PTR query */ + /** Canonical name query */ + DNS_QUERY_TYPE_CNAME = 5, + /** Pointer query */ DNS_QUERY_TYPE_PTR = 12, + /** Text query */ + DNS_QUERY_TYPE_TXT = 16, /** IPv6 query */ - DNS_QUERY_TYPE_AAAA = 28 + DNS_QUERY_TYPE_AAAA = 28, + /** Service location query */ + DNS_QUERY_TYPE_SRV = 33 }; /** @@ -69,6 +75,13 @@ enum dns_server_source { #define DNS_MAX_NAME_SIZE 20 #endif /* CONFIG_DNS_RESOLVER_MAX_NAME_LEN */ +/** Max size of the resolved txt record. */ +#if defined(CONFIG_DNS_RESOLVER_MAX_TEXT_LEN) +#define DNS_MAX_TEXT_SIZE CONFIG_DNS_RESOLVER_MAX_TEXT_LEN +#else +#define DNS_MAX_TEXT_SIZE 64 +#endif /* CONFIG_DNS_RESOLVER_MAX_TEXT_LEN */ + /** @cond INTERNAL_HIDDEN */ #define DNS_BUF_TIMEOUT K_MSEC(500) /* ms */ @@ -266,18 +279,57 @@ int dns_dispatcher_unregister(struct dns_socket_dispatcher *ctx); /** @endcond */ +/** + * Enumerate the extensions that are available in the address info + */ +enum dns_resolve_extension { + DNS_RESOLVE_NONE = 0, + DNS_RESOLVE_TXT, + DNS_RESOLVE_SRV, +}; + +struct dns_resolve_txt { + size_t textlen; + char text[DNS_MAX_TEXT_SIZE + 1]; +}; + +struct dns_resolve_srv { + uint16_t priority; + uint16_t weight; + uint16_t port; + size_t targetlen; + char target[DNS_MAX_NAME_SIZE + 1]; +}; + /** * Address info struct is passed to callback that gets all the results. */ struct dns_addrinfo { - /** IP address information */ - struct sockaddr ai_addr; - /** Length of the ai_addr field */ - socklen_t ai_addrlen; - /** Address family of the address information */ - uint8_t ai_family; - /** Canonical name of the address */ - char ai_canonname[DNS_MAX_NAME_SIZE + 1]; + /** Address family of the address information and discriminator */ + uint8_t ai_family; + + union { + struct { + /** Length of the ai_addr field or ai_canonname */ + socklen_t ai_addrlen; + + /* AF_INET or AF_INET6 address info */ + struct sockaddr ai_addr; + + /** AF_LOCAL Canonical name of the address */ + char ai_canonname[DNS_MAX_NAME_SIZE + 1]; + }; + + /* AF_UNSPEC extensions */ + struct { + enum dns_resolve_extension ai_extension; + + union { + struct dns_resolve_txt ai_txt; + struct dns_resolve_srv ai_srv; + }; + }; + }; }; /** diff --git a/include/zephyr/net/icmp.h b/include/zephyr/net/icmp.h index 9cfcd38cc539a..b1fa9ddd7cdfe 100644 --- a/include/zephyr/net/icmp.h +++ b/include/zephyr/net/icmp.h @@ -4,11 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 */ -/** @file icmp.h - * - * @brief ICMP sending and receiving. +/** + * @file icmp.h + * @brief Header file for ICMP protocol support. + * @ingroup icmp * - * @defgroup icmp Send and receive IPv4 or IPv6 ICMP Echo Request messages. + * @defgroup icmp ICMP + * @brief Send and receive IPv4 or IPv6 ICMP (Internet Control Message Protocol) + * Echo Request messages. * @since 3.5 * @version 0.8.0 * @ingroup networking diff --git a/include/zephyr/net/net_pkt.h b/include/zephyr/net/net_pkt.h index 9f9df111f02c4..e6abfcc8db64b 100644 --- a/include/zephyr/net/net_pkt.h +++ b/include/zephyr/net/net_pkt.h @@ -237,6 +237,7 @@ struct net_pkt { uint8_t chksum_done : 1; /* Checksum has already been computed for * the packet. */ + uint8_t loopback : 1; /* Packet is a loop back packet. */ #if defined(CONFIG_NET_IP_FRAGMENT) uint8_t ip_reassembled : 1; /* Packet is a reassembled IP packet. */ #endif @@ -1020,6 +1021,17 @@ static inline void net_pkt_set_ipv6_fragment_id(struct net_pkt *pkt, } #endif /* CONFIG_NET_IPV6_FRAGMENT */ +static inline bool net_pkt_is_loopback(struct net_pkt *pkt) +{ + return !!(pkt->loopback); +} + +static inline void net_pkt_set_loopback(struct net_pkt *pkt, + bool loopback) +{ + pkt->loopback = loopback; +} + #if defined(CONFIG_NET_IP_FRAGMENT) static inline bool net_pkt_is_ip_reassembled(struct net_pkt *pkt) { diff --git a/include/zephyr/posix/posix_features.h b/include/zephyr/posix/posix_features.h index ed4bffb1cf3e1..a78b4c2a8d941 100644 --- a/include/zephyr/posix/posix_features.h +++ b/include/zephyr/posix/posix_features.h @@ -245,138 +245,4 @@ /* #define _XOPEN_UNIX (-1L) */ /* #define _XOPEN_UUCP (-1L) */ -#if _POSIX_C_SOURCE >= 200809L && (__PICOLIBC__ > 1 || \ -(__PICOLIBC__ == 1 && (__PICOLIBC_MINOR__ > 8 || \ -__PICOLIBC_MINOR__ == 8 && __PICOLIBC_PATCHLEVEL__ >= 9))) -/* Use picolibc's limits.h when building POSIX code */ -#include -#else - -/* - * clang-format and checkpatch disagree on formatting here, so rely on checkpatch and disable - * clang-format since checkpatch cannot be selectively disabled. - */ - -/* clang-format off */ - -/* Maximum values */ -#define _POSIX_CLOCKRES_MIN (20000000L) - -/* Minimum values */ -#define _POSIX_AIO_LISTIO_MAX (2) -#define _POSIX_AIO_MAX (1) -#define _POSIX_ARG_MAX (4096) -#define _POSIX_CHILD_MAX (25) -#define _POSIX_DELAYTIMER_MAX (32) -#define _POSIX_HOST_NAME_MAX (255) -#define _POSIX_LINK_MAX (8) -#define _POSIX_LOGIN_NAME_MAX (9) -#define _POSIX_MAX_CANON (255) -#define _POSIX_MAX_INPUT (255) -#define _POSIX_MQ_OPEN_MAX (8) -#define _POSIX_MQ_PRIO_MAX (32) -#define _POSIX_NAME_MAX (14) -#define _POSIX_NGROUPS_MAX (8) -#define _POSIX_OPEN_MAX (20) -#define _POSIX_PATH_MAX (256) -#define _POSIX_PIPE_BUF (512) -#define _POSIX_RE_DUP_MAX (255) -#define _POSIX_RTSIG_MAX (8) -#define _POSIX_SEM_NSEMS_MAX (256) -#define _POSIX_SEM_VALUE_MAX (32767) -#define _POSIX_SIGQUEUE_MAX (32) -#define _POSIX_SSIZE_MAX (32767) -#define _POSIX_SS_REPL_MAX (4) -#define _POSIX_STREAM_MAX (8) -#define _POSIX_SYMLINK_MAX (255) -#define _POSIX_SYMLOOP_MAX (8) -#define _POSIX_THREAD_DESTRUCTOR_ITERATIONS (4) -#define _POSIX_THREAD_KEYS_MAX (128) -#define _POSIX_THREAD_THREADS_MAX (64) -#define _POSIX_TIMER_MAX (32) -#define _POSIX_TRACE_EVENT_NAME_MAX (30) -#define _POSIX_TRACE_NAME_MAX (8) -#define _POSIX_TRACE_SYS_MAX (8) -#define _POSIX_TRACE_USER_EVENT_MAX (32) -#define _POSIX_TTY_NAME_MAX (9) -#define _POSIX_TZNAME_MAX (6) -#define _POSIX2_BC_BASE_MAX (99) -#define _POSIX2_BC_DIM_MAX (2048) -#define _POSIX2_BC_SCALE_MAX (99) -#define _POSIX2_BC_STRING_MAX (1000) -#define _POSIX2_CHARCLASS_NAME_MAX (14) -#define _POSIX2_COLL_WEIGHTS_MAX (2) -#define _POSIX2_EXPR_NEST_MAX (32) -#define _POSIX2_LINE_MAX (2048) -#define _XOPEN_IOV_MAX (16) -#define _XOPEN_NAME_MAX (255) -#define _XOPEN_PATH_MAX (1024) - -#endif /* __PICOLIBC__ */ - -/* Other invariant values */ -#define NL_LANGMAX (14) -#define NL_MSGMAX (32767) -#define NL_SETMAX (255) -#define NL_TEXTMAX (_POSIX2_LINE_MAX) -#define NZERO (20) - -/* Runtime invariant values */ -#define AIO_LISTIO_MAX _POSIX_AIO_LISTIO_MAX -#define AIO_MAX _POSIX_AIO_MAX -#define AIO_PRIO_DELTA_MAX (0) -#ifndef ARG_MAX -#define ARG_MAX _POSIX_ARG_MAX -#endif -#ifndef ATEXIT_MAX -#define ATEXIT_MAX (32) -#endif -#define DELAYTIMER_MAX \ - COND_CODE_1(CONFIG_POSIX_TIMERS, (CONFIG_POSIX_DELAYTIMER_MAX), (0)) -#define HOST_NAME_MAX \ - COND_CODE_1(CONFIG_POSIX_NETWORKING, (CONFIG_POSIX_HOST_NAME_MAX), (0)) -#define LOGIN_NAME_MAX _POSIX_LOGIN_NAME_MAX -#define MQ_OPEN_MAX \ - COND_CODE_1(CONFIG_POSIX_MESSAGE_PASSING, (CONFIG_POSIX_MQ_OPEN_MAX), (0)) -#define MQ_PRIO_MAX _POSIX_MQ_PRIO_MAX -#ifndef OPEN_MAX -#define OPEN_MAX CONFIG_POSIX_OPEN_MAX -#endif -#define PAGE_SIZE CONFIG_POSIX_PAGE_SIZE -#define PAGESIZE CONFIG_POSIX_PAGE_SIZE -#ifndef PATH_MAX -#define PATH_MAX _POSIX_PATH_MAX -#endif -#define PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS -#define PTHREAD_KEYS_MAX \ - COND_CODE_1(CONFIG_POSIX_THREADS, (CONFIG_POSIX_THREAD_KEYS_MAX), (0)) -#define PTHREAD_THREADS_MAX \ - COND_CODE_1(CONFIG_POSIX_THREADS, (CONFIG_POSIX_THREAD_THREADS_MAX), (0)) -#define RTSIG_MAX \ - COND_CODE_1(CONFIG_POSIX_REALTIME_SIGNALS, (CONFIG_POSIX_RTSIG_MAX), (0)) -#define SEM_NSEMS_MAX \ - COND_CODE_1(CONFIG_POSIX_SEMAPHORES, (CONFIG_POSIX_SEM_NSEMS_MAX), (0)) -#define SEM_VALUE_MAX \ - COND_CODE_1(CONFIG_POSIX_SEMAPHORES, (CONFIG_POSIX_SEM_VALUE_MAX), (0)) -#define SIGQUEUE_MAX _POSIX_SIGQUEUE_MAX -#define STREAM_MAX _POSIX_STREAM_MAX -#define SYMLOOP_MAX _POSIX_SYMLOOP_MAX -#define TIMER_MAX \ - COND_CODE_1(CONFIG_POSIX_TIMERS, (CONFIG_POSIX_TIMER_MAX), (0)) -#define TTY_NAME_MAX _POSIX_TTY_NAME_MAX -#ifndef TZNAME_MAX -#define TZNAME_MAX _POSIX_TZNAME_MAX -#endif - -/* Pathname variable values */ -#define FILESIZEBITS (32) -#define POSIX_ALLOC_SIZE_MIN (256) -#define POSIX_REC_INCR_XFER_SIZE (1024) -#define POSIX_REC_MAX_XFER_SIZE (32767) -#define POSIX_REC_MIN_XFER_SIZE (1) -#define POSIX_REC_XFER_ALIGN (4) -#define SYMLINK_MAX _POSIX_SYMLINK_MAX - -/* clang-format on */ - #endif /* INCLUDE_ZEPHYR_POSIX_POSIX_FEATURES_H_ */ diff --git a/include/zephyr/posix/posix_limits.h b/include/zephyr/posix/posix_limits.h new file mode 100644 index 0000000000000..9c225b4b4d4e0 --- /dev/null +++ b/include/zephyr/posix/posix_limits.h @@ -0,0 +1,129 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ZEPHYR_POSIX_POSIX_LIMITS_H_ +#define ZEPHYR_INCLUDE_ZEPHYR_POSIX_POSIX_LIMITS_H_ + +#if defined(_POSIX_C_SOURCE) || defined(__DOXYGEN__) + +/* + * clang-format and checkpatch disagree on formatting here, so rely on checkpatch and disable + * clang-format since checkpatch cannot be selectively disabled. + */ + +/* clang-format off */ + +/* Maximum values */ +#define _POSIX_CLOCKRES_MIN (20000000L) + +/* Minimum values */ +#define _POSIX_AIO_LISTIO_MAX (2) +#define _POSIX_AIO_MAX (1) +#define _POSIX_ARG_MAX (4096) +#define _POSIX_CHILD_MAX (25) +#define _POSIX_DELAYTIMER_MAX (32) +#define _POSIX_HOST_NAME_MAX (255) +#define _POSIX_LINK_MAX (8) +#define _POSIX_LOGIN_NAME_MAX (9) +#define _POSIX_MAX_CANON (255) +#define _POSIX_MAX_INPUT (255) +#define _POSIX_MQ_OPEN_MAX (8) +#define _POSIX_MQ_PRIO_MAX (32) +#define _POSIX_NAME_MAX (14) +#define _POSIX_NGROUPS_MAX (8) +#define _POSIX_OPEN_MAX (20) +#define _POSIX_PATH_MAX (256) +#define _POSIX_PIPE_BUF (512) +#define _POSIX_RE_DUP_MAX (255) +#define _POSIX_RTSIG_MAX (8) +#define _POSIX_SEM_NSEMS_MAX (256) +#define _POSIX_SEM_VALUE_MAX (32767) +#define _POSIX_SIGQUEUE_MAX (32) +#define _POSIX_SSIZE_MAX (32767) +#define _POSIX_SS_REPL_MAX (4) +#define _POSIX_STREAM_MAX (8) +#define _POSIX_SYMLINK_MAX (255) +#define _POSIX_SYMLOOP_MAX (8) +#define _POSIX_THREAD_DESTRUCTOR_ITERATIONS (4) +#define _POSIX_THREAD_KEYS_MAX (128) +#define _POSIX_THREAD_THREADS_MAX (64) +#define _POSIX_TIMER_MAX (32) +#define _POSIX_TRACE_EVENT_NAME_MAX (30) +#define _POSIX_TRACE_NAME_MAX (8) +#define _POSIX_TRACE_SYS_MAX (8) +#define _POSIX_TRACE_USER_EVENT_MAX (32) +#define _POSIX_TTY_NAME_MAX (9) +#define _POSIX_TZNAME_MAX (6) +#define _POSIX2_BC_BASE_MAX (99) +#define _POSIX2_BC_DIM_MAX (2048) +#define _POSIX2_BC_SCALE_MAX (99) +#define _POSIX2_BC_STRING_MAX (1000) +#define _POSIX2_CHARCLASS_NAME_MAX (14) +#define _POSIX2_COLL_WEIGHTS_MAX (2) +#define _POSIX2_EXPR_NEST_MAX (32) +#define _POSIX2_LINE_MAX (2048) +#define _XOPEN_IOV_MAX (16) +#define _XOPEN_NAME_MAX (255) +#define _XOPEN_PATH_MAX (1024) + +/* Other invariant values */ +#define NL_LANGMAX (14) +#define NL_MSGMAX (32767) +#define NL_SETMAX (255) +#define NL_TEXTMAX (_POSIX2_LINE_MAX) +#define NZERO (20) + +/* Runtime invariant values */ +#define AIO_LISTIO_MAX _POSIX_AIO_LISTIO_MAX +#define AIO_MAX _POSIX_AIO_MAX +#define AIO_PRIO_DELTA_MAX (0) +#define ARG_MAX _POSIX_ARG_MAX +#define ATEXIT_MAX (32) +#define DELAYTIMER_MAX \ + COND_CODE_1(CONFIG_POSIX_TIMERS, (CONFIG_POSIX_DELAYTIMER_MAX), (0)) +#define HOST_NAME_MAX \ + COND_CODE_1(CONFIG_POSIX_NETWORKING, (CONFIG_POSIX_HOST_NAME_MAX), (0)) +#define LOGIN_NAME_MAX _POSIX_LOGIN_NAME_MAX +#define MQ_OPEN_MAX \ + COND_CODE_1(CONFIG_POSIX_MESSAGE_PASSING, (CONFIG_POSIX_MQ_OPEN_MAX), (0)) +#define MQ_PRIO_MAX _POSIX_MQ_PRIO_MAX +#define OPEN_MAX CONFIG_POSIX_OPEN_MAX +#define PAGE_SIZE CONFIG_POSIX_PAGE_SIZE +#define PAGESIZE CONFIG_POSIX_PAGE_SIZE +#define PATH_MAX _POSIX_PATH_MAX +#define PTHREAD_DESTRUCTOR_ITERATIONS _POSIX_THREAD_DESTRUCTOR_ITERATIONS +#define PTHREAD_KEYS_MAX \ + COND_CODE_1(CONFIG_POSIX_THREADS, (CONFIG_POSIX_THREAD_KEYS_MAX), (0)) +#define PTHREAD_THREADS_MAX \ + COND_CODE_1(CONFIG_POSIX_THREADS, (CONFIG_POSIX_THREAD_THREADS_MAX), (0)) +#define RTSIG_MAX \ + COND_CODE_1(CONFIG_POSIX_REALTIME_SIGNALS, (CONFIG_POSIX_RTSIG_MAX), (0)) +#define SEM_NSEMS_MAX \ + COND_CODE_1(CONFIG_POSIX_SEMAPHORES, (CONFIG_POSIX_SEM_NSEMS_MAX), (0)) +#define SEM_VALUE_MAX \ + COND_CODE_1(CONFIG_POSIX_SEMAPHORES, (CONFIG_POSIX_SEM_VALUE_MAX), (0)) +#define SIGQUEUE_MAX _POSIX_SIGQUEUE_MAX +#define STREAM_MAX _POSIX_STREAM_MAX +#define SYMLOOP_MAX _POSIX_SYMLOOP_MAX +#define TIMER_MAX \ + COND_CODE_1(CONFIG_POSIX_TIMERS, (CONFIG_POSIX_TIMER_MAX), (0)) +#define TTY_NAME_MAX _POSIX_TTY_NAME_MAX +#define TZNAME_MAX _POSIX_TZNAME_MAX + +/* Pathname variable values */ +#define FILESIZEBITS (32) +#define POSIX_ALLOC_SIZE_MIN (256) +#define POSIX_REC_INCR_XFER_SIZE (1024) +#define POSIX_REC_MAX_XFER_SIZE (32767) +#define POSIX_REC_MIN_XFER_SIZE (1) +#define POSIX_REC_XFER_ALIGN (4) +#define SYMLINK_MAX _POSIX_SYMLINK_MAX + +/* clang-format on */ + +#endif + +#endif /* ZEPHYR_INCLUDE_ZEPHYR_POSIX_POSIX_LIMITS_H_ */ diff --git a/include/zephyr/posix/sys/dirent.h b/include/zephyr/posix/sys/dirent.h index 63d02dc511edc..fde312136ebb2 100644 --- a/include/zephyr/posix/sys/dirent.h +++ b/include/zephyr/posix/sys/dirent.h @@ -9,8 +9,6 @@ #include -#include - #if !defined(NAME_MAX) && defined(_XOPEN_SOURCE) #define NAME_MAX _XOPEN_NAME_MAX #endif diff --git a/include/zephyr/rtio/rtio.h b/include/zephyr/rtio/rtio.h index 092f13f002d42..cb46d6fa8df10 100644 --- a/include/zephyr/rtio/rtio.h +++ b/include/zephyr/rtio/rtio.h @@ -580,7 +580,7 @@ struct rtio_iodev { /** An operation to sends I3C CCC */ #define RTIO_OP_I3C_CCC (RTIO_OP_I3C_CONFIGURE+1) -/** An operation to suspend bus while awaiting signal */ +/** An operation to await a signal while blocking the iodev (if one is provided) */ #define RTIO_OP_AWAIT (RTIO_OP_I3C_CCC+1) /** @@ -745,6 +745,20 @@ static inline void rtio_sqe_prep_transceive(struct rtio_sqe *sqe, sqe->userdata = userdata; } +/** + * @brief Prepare an await op submission + * + * The await operation will await the completion signal before the sqe completes. + * + * If an rtio_iodev is provided then it will be blocked while awaiting. This facilitates a + * low-latency continuation of the rtio sequence, a sort of "critical section" during a bus + * operation if you will. + * Note that it is the responsibility of the rtio_iodev driver to properly block during the + * operation. + * + * See @ref rtio_sqe_prep_await_iodev for a helper, where an rtio_iodev is blocked. + * See @ref rtio_sqe_prep_await_executor for a helper, where no rtio_iodev is blocked. + */ static inline void rtio_sqe_prep_await(struct rtio_sqe *sqe, const struct rtio_iodev *iodev, int8_t prio, @@ -757,6 +771,39 @@ static inline void rtio_sqe_prep_await(struct rtio_sqe *sqe, sqe->userdata = userdata; } +/** + * @brief Prepare an await op submission which blocks an rtio_iodev until completion + * + * This variant can be useful if the await op is part of a sequence which must run within a tight + * time window as it effectively keeps the underlying bus locked while awaiting completion. + * Note that it is the responsibility of the rtio_iodev driver to properly block during the + * operation. + * + * See @ref rtio_sqe_prep_await for details. + * See @ref rtio_sqe_prep_await_executor for a counterpart where no rtio_iodev is blocked. + */ +static inline void rtio_sqe_prep_await_iodev(struct rtio_sqe *sqe, const struct rtio_iodev *iodev, + int8_t prio, void *userdata) +{ + __ASSERT_NO_MSG(iodev != NULL); + rtio_sqe_prep_await(sqe, iodev, prio, userdata); +} + +/** + * @brief Prepare an await op submission which completes the sqe after being signaled + * + * This variant can be useful when the await op serves as a logical piece of a sequence without + * requirements for a low-latency continuation of the sequence upon completion, or if the await + * op is expected to take "a long time" to complete. + * + * See @ref rtio_sqe_prep_await for details. + * See @ref rtio_sqe_prep_await_iodev for a counterpart where an rtio_iodev is blocked. + */ +static inline void rtio_sqe_prep_await_executor(struct rtio_sqe *sqe, int8_t prio, void *userdata) +{ + rtio_sqe_prep_await(sqe, NULL, prio, userdata); +} + static inline void rtio_sqe_prep_delay(struct rtio_sqe *sqe, k_timeout_t timeout, void *userdata) @@ -1175,6 +1222,32 @@ static inline void rtio_cqe_release(struct rtio *r, struct rtio_cqe *cqe) rtio_cqe_pool_free(r->cqe_pool, cqe); } +/** + * @brief Flush completion queue + * + * @param r RTIO context + * @return The operation completion result + * @retval 0 if the queued operations completed with no error + * @retval <0 on error + */ +static inline int rtio_flush_completion_queue(struct rtio *r) +{ + struct rtio_cqe *cqe; + int res = 0; + + do { + cqe = rtio_cqe_consume(r); + if (cqe != NULL) { + if ((cqe->result < 0) && (res == 0)) { + res = cqe->result; + } + rtio_cqe_release(r, cqe); + } + } while (cqe != NULL); + + return res; +} + /** * @brief Compute the CQE flags from the rtio_iodev_sqe entry * @@ -1421,6 +1494,9 @@ static inline void z_impl_rtio_release_buffer(struct rtio *r, void *buff, uint32 /** * Grant access to an RTIO context to a user thread + * + * @param r RTIO context + * @param t Thread to grant permissions to */ static inline void rtio_access_grant(struct rtio *r, struct k_thread *t) { @@ -1435,6 +1511,26 @@ static inline void rtio_access_grant(struct rtio *r, struct k_thread *t) #endif } + +/** + * Revoke access to an RTIO context from a user thread + * + * @param r RTIO context + * @param t Thread to revoke permissions from + */ +static inline void rtio_access_revoke(struct rtio *r, struct k_thread *t) +{ + k_object_access_revoke(r, t); + +#ifdef CONFIG_RTIO_SUBMIT_SEM + k_object_access_revoke(r->submit_sem, t); +#endif + +#ifdef CONFIG_RTIO_CONSUME_SEM + k_object_access_revoke(r->consume_sem, t); +#endif +} + /** * @brief Attempt to cancel an SQE * @@ -1674,6 +1770,108 @@ static inline int z_impl_rtio_submit(struct rtio *r, uint32_t wait_count) } #endif /* CONFIG_RTIO_SUBMIT_SEM */ +/** + * @brief Pool of RTIO contexts to use with dynamically created threads + */ +struct rtio_pool { + /** Size of the pool */ + size_t pool_size; + + /** Array containing contexts of the pool */ + struct rtio **contexts; + + /** Atomic bitmap to signal a member is used/unused */ + atomic_t *used; +}; + +/** + * @brief Obtain an RTIO context from a pool + * + * @param pool RTIO pool to acquire a context from + * + * @retval NULL no available contexts + * @retval r Valid context with permissions granted to the calling thread + */ +__syscall struct rtio *rtio_pool_acquire(struct rtio_pool *pool); + +static inline struct rtio *z_impl_rtio_pool_acquire(struct rtio_pool *pool) +{ + struct rtio *r = NULL; + + for (size_t i = 0; i < pool->pool_size; i++) { + if (atomic_test_and_set_bit(pool->used, i) == 0) { + r = pool->contexts[i]; + break; + } + } + + if (r != NULL) { + rtio_access_grant(r, k_current_get()); + } + + return r; +} + +/** + * @brief Return an RTIO context to a pool + * + * @param pool RTIO pool to return a context to + * @param r RTIO context to return to the pool + */ +__syscall void rtio_pool_release(struct rtio_pool *pool, struct rtio *r); + +static inline void z_impl_rtio_pool_release(struct rtio_pool *pool, struct rtio *r) +{ + + if (k_is_user_context()) { + rtio_access_revoke(r, k_current_get()); + } + + for (size_t i = 0; i < pool->pool_size; i++) { + if (pool->contexts[i] == r) { + atomic_clear_bit(pool->used, i); + break; + } + } +} + +/* clang-format off */ + +/** @cond ignore */ + +#define Z_RTIO_POOL_NAME_N(n, name) \ + name##_##n + +#define Z_RTIO_POOL_DEFINE_N(n, name, sq_sz, cq_sz) \ + RTIO_DEFINE(Z_RTIO_POOL_NAME_N(n, name), sq_sz, cq_sz) + +#define Z_RTIO_POOL_REF_N(n, name) \ + &Z_RTIO_POOL_NAME_N(n, name) + +/** @endcond */ + +/** + * @brief Statically define and initialize a pool of RTIO contexts + * + * @param name Name of the RTIO pool + * @param pool_sz Number of RTIO contexts to allocate in the pool + * @param sq_sz Size of the submission queue entry pool per context + * @param cq_sz Size of the completion queue entry pool per context + */ +#define RTIO_POOL_DEFINE(name, pool_sz, sq_sz, cq_sz) \ + LISTIFY(pool_sz, Z_RTIO_POOL_DEFINE_N, (;), name, sq_sz, cq_sz); \ + static struct rtio *name##_contexts[] = { \ + LISTIFY(pool_sz, Z_RTIO_POOL_REF_N, (,), name) \ + }; \ + ATOMIC_DEFINE(name##_used, pool_sz); \ + STRUCT_SECTION_ITERABLE(rtio_pool, name) = { \ + .pool_size = pool_sz, \ + .contexts = name##_contexts, \ + .used = name##_used, \ + } + +/* clang-format on */ + /** * @} */ diff --git a/include/zephyr/sensing/sensing.h b/include/zephyr/sensing/sensing.h index 96fb119b0ed54..725f3a6bba8ba 100644 --- a/include/zephyr/sensing/sensing.h +++ b/include/zephyr/sensing/sensing.h @@ -8,32 +8,26 @@ #define ZEPHYR_INCLUDE_SENSING_H_ /** - * @defgroup sensing Sensing - * @defgroup sensing_api Sensing Subsystem API - * @ingroup sensing - * @defgroup sensing_sensor_types Sensor Types - * @ingroup sensing - * @defgroup sensing_datatypes Data Types - * @ingroup sensing + * @defgroup sensing_api Sensing + * @brief High-level sensor framework. + * @ingroup os_services + * + * The Sensing subsystem provides a high-level API for applications to discover sensors, open sensor + * instances, configure reporting behavior, and receive sampled data via callbacks. + * For low-level sensor access, see @ref sensor_interface. + * + * @{ */ #include #include #include -/** - * @brief Sensing Subsystem API - * @addtogroup sensing_api - * @{ - */ - #ifdef __cplusplus extern "C" { #endif - /** - * @struct sensing_sensor_version * @brief Sensor Version */ struct sensing_sensor_version { @@ -49,8 +43,13 @@ struct sensing_sensor_version { }; /** - * @brief Macro to create a sensor version value. + * @brief Build a packed @ref sensing_sensor_version value. * + * @param _major Major version. + * @param _minor Minor version. + * @param _hotfix Hotfix version. + * @param _build Build number. + * @return 32-bit packed version value */ #define SENSING_SENSOR_VERSION(_major, _minor, _hotfix, _build) \ (FIELD_PREP(GENMASK(31, 24), _major) | \ @@ -58,33 +57,43 @@ struct sensing_sensor_version { FIELD_PREP(GENMASK(15, 8), _hotfix) | \ FIELD_PREP(GENMASK(7, 0), _build)) +/** + * @name Sensor reporting flags + * @{ + */ /** - * @brief Sensor flag indicating if this sensor is on event reporting data. + * @brief Sensor flag indicating if this sensor is reporting data on event. * * Reporting sensor data when the sensor event occurs, such as a motion detect sensor reporting * a motion or motionless detected event. + * + * @note Mutually exclusive with \ref SENSING_SENSOR_FLAG_REPORT_ON_CHANGE */ #define SENSING_SENSOR_FLAG_REPORT_ON_EVENT BIT(0) /** - * @brief Sensor flag indicating if this sensor is on change reporting data. + * @brief Sensor flag indicating if this sensor is reporting data on change. * * Reporting sensor data when the sensor data changes. * - * Exclusive with \ref SENSING_SENSOR_FLAG_REPORT_ON_EVENT + * @note Mutually exclusive with \ref SENSING_SENSOR_FLAG_REPORT_ON_EVENT */ #define SENSING_SENSOR_FLAG_REPORT_ON_CHANGE BIT(1) +/** @} */ + /** - * @brief SENSING_SENSITIVITY_INDEX_ALL indicating sensitivity of each data field should be set + * @brief Sentinel index meaning "apply to all data fields". * + * Used with sensitivity configuration where a sensor provides multiple fields in a single sample. */ #define SENSING_SENSITIVITY_INDEX_ALL -1 /** - * @brief Sensing subsystem sensor state. + * @brief Sensor state. * + * This enumeration defines the possible states of a sensor. */ enum sensing_sensor_state { SENSING_SENSOR_STATE_READY = 0, /**< The sensor is ready. */ @@ -92,32 +101,53 @@ enum sensing_sensor_state { }; /** - * @brief Sensing subsystem sensor config attribute + * @brief Sensor configuration attribute. * + * This enumeration defines the possible attributes of a sensor configuration. */ enum sensing_sensor_attribute { - /** The interval attribute of a sensor configuration. */ + /** + * Reporting interval between samples, in microseconds (us). + * + * See @ref sensing_sensor_config::interval. + */ SENSING_SENSOR_ATTRIBUTE_INTERVAL = 0, - /** The sensitivity attribute of a sensor configuration. */ + + /** + * Per-field sensitivity threshold. + * + * See @ref sensing_sensor_config::sensitivity. + */ SENSING_SENSOR_ATTRIBUTE_SENSITIVITY = 1, - /** The latency attribute of a sensor configuration. */ + + /** + * Maximum batching latency, in microseconds (us). + * + * See @ref sensing_sensor_config::latency. + */ SENSING_SENSOR_ATTRIBUTE_LATENCY = 2, - /** The maximum number of attributes that a sensor configuration can have. */ + + /** Number of supported attributes. */ SENSING_SENSOR_ATTRIBUTE_MAX, }; /** - * @brief Define Sensing subsystem sensor handle + * @brief Opaque handle to an opened sensor instance. * + * A valid handle is obtained from @ref sensing_open_sensor or @ref sensing_open_sensor_by_dt and + * must be closed with @ref sensing_close_sensor when no longer needed. */ typedef void *sensing_sensor_handle_t; /** - * @brief Sensor data event receive callback. + * @brief Data event callback signature. * - * @param handle The sensor instance handle. - * @param buf The data buffer with sensor data. - * @param context User provided context pointer. + * The Sensing subsystem invokes this callback to deliver buffered samples for the opened sensor. + * + * @param handle Sensor instance handle passed to @ref sensing_open_sensor. + * @param buf Pointer to a sensor-type-specific sample buffer; see @ref sensing_datatypes and + * @ref sensing_sensor_types. + * @param context User context pointer as provided in @ref sensing_callback_list::context. */ typedef void (*sensing_data_event_t)( sensing_sensor_handle_t handle, @@ -125,9 +155,7 @@ typedef void (*sensing_data_event_t)( void *context); /** - * @struct sensing_sensor_info - * @brief Sensor basic constant information - * + * @brief Read-only description of a sensor instance. */ struct sensing_sensor_info { /** Name of the sensor instance */ @@ -154,9 +182,13 @@ struct sensing_sensor_info { * @brief Sensing subsystem event callback list * */ + +/** + * @brief Callback registration for a sensor instance. + */ struct sensing_callback_list { sensing_data_event_t on_data_event; /**< Callback function for a sensor data event. */ - void *context; /**< Associated context with on_data_event */ + void *context; /**< Context that will be passed to the callback. */ }; /** diff --git a/include/zephyr/sensing/sensing_datatypes.h b/include/zephyr/sensing/sensing_datatypes.h index b18b22b41800a..ad77733ca96eb 100644 --- a/include/zephyr/sensing/sensing_datatypes.h +++ b/include/zephyr/sensing/sensing_datatypes.h @@ -11,14 +11,15 @@ #include /** - * @brief Data Types - * @addtogroup sensing_datatypes + * @defgroup sensing_datatypes Data Types + * @ingroup sensing_api + * @brief Sensor data structures used by the sensing subsystem + * * @{ */ /** - * @struct sensing_sensor_value_header - * @brief sensor value header + * @brief Common header for all sensor value payloads. * * Each sensor value data structure should have this header * diff --git a/include/zephyr/sensing/sensing_sensor.h b/include/zephyr/sensing/sensing_sensor.h index 2c5e526f760b6..de7fe6c9e3b84 100644 --- a/include/zephyr/sensing/sensing_sensor.h +++ b/include/zephyr/sensing/sensing_sensor.h @@ -13,15 +13,9 @@ #include /** - * @defgroup sensing_sensor Sensing Sensor API - * @ingroup sensing - * @defgroup sensing_sensor_callbacks Sensor Callbacks - * @ingroup sensing_sensor - */ - -/** - * @brief Sensing Sensor API - * @addtogroup sensing_sensor + * @brief Interfaces to manipulate sensors in the sensing subsystem + * @defgroup sensing_sensor Sensors (Sensing) + * @ingroup sensing_api * @{ */ @@ -390,7 +384,7 @@ extern const struct rtio_iodev_api __sensing_iodev_api; SENSING_SENSORS_DT_DEFINE(DT_DRV_INST(inst), __VA_ARGS__) /** - * @brief Get reporter handles of a given sensor instance by sensor type. + * @brief Get reporter handles of a given sensor instance by sensor type. * * @param dev The sensor instance device structure. * @param type The given type, \ref SENSING_SENSOR_TYPE_ALL to get reporters diff --git a/include/zephyr/sensing/sensing_sensor_types.h b/include/zephyr/sensing/sensing_sensor_types.h index de9328c7b2189..5469e09d7f482 100644 --- a/include/zephyr/sensing/sensing_sensor_types.h +++ b/include/zephyr/sensing/sensing_sensor_types.h @@ -8,47 +8,63 @@ #define ZEPHYR_INCLUDE_SENSING_SENSOR_TYPES_H_ /** - * @brief Sensor Types Definition + * @defgroup sensing_sensor_types Sensor Types (Sensing) + * @ingroup sensing_api + * + * @brief Sensor type identifiers used by the sensing subsystem. * * Sensor types definition followed HID standard. * https://usb.org/sites/default/files/hutrr39b_0.pdf * * TODO: will add more types - * - * @addtogroup sensing_sensor_types * @{ */ /** - * sensor category light + * @name Light sensors + * @{ */ + +/** Sensor type for ambient light sensors. */ #define SENSING_SENSOR_TYPE_LIGHT_AMBIENTLIGHT 0x41 +/** @} */ + /** - * sensor category motion + * @name Motion sensors + * @{ */ -/* Sensor type for 3D accelerometers. */ + +/** Sensor type for 3D accelerometers. */ #define SENSING_SENSOR_TYPE_MOTION_ACCELEROMETER_3D 0x73 -/* Sensor type for 3D gyrometers. */ +/** Sensor type for 3D gyrometers. */ #define SENSING_SENSOR_TYPE_MOTION_GYROMETER_3D 0x76 -/* Sensor type for motion detectors. */ +/** Sensor type for motion detectors. */ #define SENSING_SENSOR_TYPE_MOTION_MOTION_DETECTOR 0x77 +/** Sensor type for uncalibrated 3D accelerometers. */ +#define SENSING_SENSOR_TYPE_MOTION_UNCALIB_ACCELEROMETER_3D 0x240 +/** Sensor type for hinge angle sensors. */ +#define SENSING_SENSOR_TYPE_MOTION_HINGE_ANGLE 0x20B +/** @} */ /** - * sensor category other + * @name Other sensors + * @{ */ -#define SENSING_SENSOR_TYPE_OTHER_CUSTOM 0xE1 -/* Sensor type for uncalibrated 3D accelerometers. */ -#define SENSING_SENSOR_TYPE_MOTION_UNCALIB_ACCELEROMETER_3D 0x240 -/* Sensor type for hinge angle sensors. */ -#define SENSING_SENSOR_TYPE_MOTION_HINGE_ANGLE 0x20B +/** Sensor type for custom sensors. */ +#define SENSING_SENSOR_TYPE_OTHER_CUSTOM 0xE1 + +/** @} */ /** * @brief Sensor type for all sensors. * * This macro defines the sensor type for all sensors. + * + * @note This value is not a valid sensor type and is used as a sentinel value to indicate all + * sensor types. */ #define SENSING_SENSOR_TYPE_ALL 0xFFFF diff --git a/include/zephyr/shell/shell_mqtt.h b/include/zephyr/shell/shell_mqtt.h index 92ce6987efefc..4a96f9f0eac5d 100644 --- a/include/zephyr/shell/shell_mqtt.h +++ b/include/zephyr/shell/shell_mqtt.h @@ -25,7 +25,8 @@ extern "C" { #define SH_MQTT_BUFFER_SIZE 64 #define DEVICE_ID_BIN_MAX_SIZE 3 #define DEVICE_ID_HEX_MAX_SIZE ((DEVICE_ID_BIN_MAX_SIZE * 2) + 1) -#define SH_MQTT_TOPIC_MAX_SIZE DEVICE_ID_HEX_MAX_SIZE + 3 +#define SH_MQTT_TOPIC_RX_MAX_SIZE DEVICE_ID_HEX_MAX_SIZE + sizeof(CONFIG_SHELL_MQTT_TOPIC_RX_ID) +#define SH_MQTT_TOPIC_TX_MAX_SIZE DEVICE_ID_HEX_MAX_SIZE + sizeof(CONFIG_SHELL_MQTT_TOPIC_TX_ID) extern const struct shell_transport_api shell_mqtt_transport_api; @@ -40,8 +41,8 @@ struct shell_mqtt_tx_buf { /** MQTT-based shell transport. */ struct shell_mqtt { char device_id[DEVICE_ID_HEX_MAX_SIZE]; - char sub_topic[SH_MQTT_TOPIC_MAX_SIZE]; - char pub_topic[SH_MQTT_TOPIC_MAX_SIZE]; + char sub_topic[SH_MQTT_TOPIC_RX_MAX_SIZE]; + char pub_topic[SH_MQTT_TOPIC_TX_MAX_SIZE]; /** Handler function registered by shell. */ shell_transport_handler_t shell_handler; diff --git a/include/zephyr/storage/stream_flash.h b/include/zephyr/storage/stream_flash.h index 5a1e096e6d10d..6be67896013a3 100644 --- a/include/zephyr/storage/stream_flash.h +++ b/include/zephyr/storage/stream_flash.h @@ -106,6 +106,15 @@ int stream_flash_init(struct stream_flash_ctx *ctx, const struct device *fdev, */ size_t stream_flash_bytes_written(const struct stream_flash_ctx *ctx); +/** + * @brief Read number of bytes buffered for the next flash write. + * + * @param ctx context + * + * @return Number of payload bytes buffered for the next flash write. + */ +size_t stream_flash_bytes_buffered(const struct stream_flash_ctx *ctx); + /** * @brief Process input buffers to be written to flash device in single blocks. * Will store remainder between calls. diff --git a/include/zephyr/sys/clock.h b/include/zephyr/sys/clock.h index 00e0a9a1ade57..24ee4301bc6f9 100644 --- a/include/zephyr/sys/clock.h +++ b/include/zephyr/sys/clock.h @@ -166,6 +166,12 @@ typedef struct { /* added tick needed to account for tick in progress */ #define _TICK_ALIGN 1 +/* The minimum duration in ticks strictly greater than that of K_NO_WAIT */ +#define K_TICK_MIN ((k_ticks_t)1) + +/* The maximum duration in ticks strictly and semantically "less than" K_FOREVER */ +#define K_TICK_MAX ((k_ticks_t)(IS_ENABLED(CONFIG_TIMEOUT_64BIT) ? INT64_MAX : UINT32_MAX - 1)) + /** @endcond */ #ifndef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME diff --git a/include/zephyr/sys/crc.h b/include/zephyr/sys/crc.h index 1337326f1ccc7..3e6e79760dc0c 100644 --- a/include/zephyr/sys/crc.h +++ b/include/zephyr/sys/crc.h @@ -51,6 +51,51 @@ extern "C" { * @{ */ +/** + * @brief CRC polynomial definitions + * @anchor CRC_POLYNOMIAL + * + * @{ + */ + +/** CRC4 polynomial */ +#define CRC4_POLY 0x3 + +/** CRC4_TI polynomial */ +#define CRC4_REFLECT_POLY 0xC + +/** CRC7_BE polynomial */ +#define CRC7_BE_POLY 0x09 + +/** CRC8 polynomial */ +#define CRC8_POLY 0x07 + +/** CRC8_CCITT polynomial */ +#define CRC8_REFLECT_POLY 0xE0 + +/** CRC8_ROHC polynomial */ +#define CRC16_POLY 0x8005 + +/** CRC16_ANSI polynomial */ +#define CRC16_REFLECT_POLY 0xA001 + +/** CRC16_CCITT polynomial */ +#define CRC16_CCITT_POLY 0x1021 + +/** CRC16_ITU_T polynomial */ +#define CRC24_PGP_POLY 0x01864CFBU + +/** CRC32_C polynomial */ +#define CRC32_IEEE_POLY 0x04C11DB7U + +/** CRC32C polynomial */ +#define CRC32C_POLY 0x1EDC6F41U + +/** CRC32_K_4_2 polynomial */ +#define CRC32K_4_2_POLY 0x93A409EBU + +/** @} */ + /** * @brief CRC algorithm enumeration * diff --git a/include/zephyr/sys/spsc_pbuf.h b/include/zephyr/sys/spsc_pbuf.h index a65d15cc5c474..e26690baa583a 100644 --- a/include/zephyr/sys/spsc_pbuf.h +++ b/include/zephyr/sys/spsc_pbuf.h @@ -40,10 +40,10 @@ extern "C" { /**@} */ -#if CONFIG_DCACHE_LINE_SIZE != 0 +#ifdef CONFIG_DCACHE_LINE_SIZE #define Z_SPSC_PBUF_LOCAL_DCACHE_LINE CONFIG_DCACHE_LINE_SIZE #else -#define Z_SPSC_PBUF_LOCAL_DCACHE_LINE DT_PROP_OR(CPU, d_cache_line_size, 0) +#define Z_SPSC_PBUF_LOCAL_DCACHE_LINE 0 #endif #ifndef CONFIG_SPSC_PBUF_REMOTE_DCACHE_LINE diff --git a/include/zephyr/sys/timeutil.h b/include/zephyr/sys/timeutil.h index 7c5db054f36fb..09214789b376f 100644 --- a/include/zephyr/sys/timeutil.h +++ b/include/zephyr/sys/timeutil.h @@ -40,6 +40,44 @@ extern "C" { #endif +/* Maximum and minimum value TIME_T can hold */ +#define SYS_TIME_T_MAX ((((time_t)1 << (8 * sizeof(time_t) - 2)) - 1) * 2 + 1) +#define SYS_TIME_T_MIN (-SYS_TIME_T_MAX - 1) + +/* Converts ticks to seconds, discarding any fractional seconds */ +#define SYS_TICKS_TO_SECS(ticks) \ + (((uint64_t)(ticks) >= (uint64_t)K_TICKS_FOREVER) ? SYS_TIME_T_MAX \ + : k_ticks_to_sec_floor64(ticks)) + +/* Converts ticks to nanoseconds, modulo NSEC_PER_SEC */ +#define SYS_TICKS_TO_NSECS(ticks) \ + (((uint64_t)(ticks) >= (uint64_t)K_TICKS_FOREVER) \ + ? (NSEC_PER_SEC - 1) \ + : k_ticks_to_ns_floor32((uint64_t)(ticks) % CONFIG_SYS_CLOCK_TICKS_PER_SEC)) + +/* Define a timespec */ +#define SYS_TIMESPEC(sec, nsec) \ + ((struct timespec){ \ + .tv_sec = (time_t)CLAMP((int64_t)(sec), SYS_TIME_T_MIN, SYS_TIME_T_MAX), \ + .tv_nsec = (long)(nsec), \ + }) + +/* Initialize a struct timespec object from a tick count */ +#define SYS_TICKS_TO_TIMESPEC(ticks) SYS_TIMESPEC(SYS_TICKS_TO_SECS(ticks), \ + SYS_TICKS_TO_NSECS(ticks)) + +/* The semantic equivalent of K_NO_WAIT but expressed as a timespec object*/ +#define SYS_TIMESPEC_NO_WAIT SYS_TICKS_TO_TIMESPEC(0) + +/* The semantic equivalent of K_TICK_MIN but expressed as a timespec object */ +#define SYS_TIMESPEC_MIN SYS_TICKS_TO_TIMESPEC(K_TICK_MIN) + +/* The semantic equivalent of K_TICK_MAX but expressed as a timespec object */ +#define SYS_TIMESPEC_MAX SYS_TICKS_TO_TIMESPEC(K_TICK_MAX) + +/* The semantic equivalent of K_FOREVER but expressed as a timespec object*/ +#define SYS_TIMESPEC_FOREVER SYS_TIMESPEC(SYS_TIME_T_MAX, NSEC_PER_SEC - 1) + /** * @defgroup timeutil_apis Time Utility APIs * @ingroup utilities @@ -383,14 +421,25 @@ static inline bool timespec_normalize(struct timespec *ts) #if defined(CONFIG_SPEED_OPTIMIZATIONS) && HAS_BUILTIN(__builtin_add_overflow) + int64_t sec = 0; int sign = (ts->tv_nsec >= 0) - (ts->tv_nsec < 0); - int64_t sec = (ts->tv_nsec >= (long)NSEC_PER_SEC) * (ts->tv_nsec / (long)NSEC_PER_SEC) + - ((ts->tv_nsec < 0) && (ts->tv_nsec != LONG_MIN)) * - DIV_ROUND_UP((unsigned long)-ts->tv_nsec, (long)NSEC_PER_SEC) + - (ts->tv_nsec == LONG_MIN) * ((LONG_MAX / NSEC_PER_SEC) + 1); - bool overflow = __builtin_add_overflow(ts->tv_sec, sign * sec, &ts->tv_sec); - ts->tv_nsec -= sign * (long)NSEC_PER_SEC * sec; + /* only one of the following should be non-zero */ + sec += (ts->tv_nsec >= (long)NSEC_PER_SEC) * (ts->tv_nsec / (long)NSEC_PER_SEC); + sec += ((sizeof(ts->tv_nsec) != sizeof(int64_t)) && (ts->tv_nsec != LONG_MIN) && + (ts->tv_nsec < 0)) * + DIV_ROUND_UP((unsigned long)-ts->tv_nsec, (long)NSEC_PER_SEC); + sec += ((sizeof(ts->tv_nsec) == sizeof(int64_t)) && (ts->tv_nsec != INT64_MIN) && + (ts->tv_nsec < 0)) * + DIV_ROUND_UP((uint64_t)-ts->tv_nsec, NSEC_PER_SEC); + sec += ((sizeof(ts->tv_nsec) != sizeof(int64_t)) && (ts->tv_nsec == LONG_MIN)) * + ((LONG_MAX / NSEC_PER_SEC) + 1); + sec += ((sizeof(ts->tv_nsec) == sizeof(int64_t)) && (ts->tv_nsec == INT64_MIN)) * + ((INT64_MAX / NSEC_PER_SEC) + 1); + + ts->tv_nsec -= sec * sign * NSEC_PER_SEC; + + bool overflow = __builtin_add_overflow(ts->tv_sec, sign * sec, &ts->tv_sec); if (!overflow) { __ASSERT_NO_MSG(timespec_is_valid(ts)); @@ -405,16 +454,12 @@ static inline bool timespec_normalize(struct timespec *ts) if (ts->tv_nsec >= (long)NSEC_PER_SEC) { sec = ts->tv_nsec / (long)NSEC_PER_SEC; } else if (ts->tv_nsec < 0) { - if ((sizeof(ts->tv_nsec) == sizeof(uint32_t)) && (ts->tv_nsec == LONG_MIN)) { - sec = DIV_ROUND_UP(LONG_MAX / NSEC_PER_USEC, USEC_PER_SEC); - } else { - sec = DIV_ROUND_UP((unsigned long)-ts->tv_nsec, NSEC_PER_SEC); - } + sec = DIV_ROUND_UP((unsigned long)-ts->tv_nsec, NSEC_PER_SEC); } else { sec = 0; } - if ((ts->tv_nsec < 0) && (ts->tv_sec < 0) && (ts->tv_sec - INT64_MIN < sec)) { + if ((ts->tv_nsec < 0) && (ts->tv_sec < 0) && (ts->tv_sec - SYS_TIME_T_MIN < sec)) { /* * When `tv_nsec` is negative and `tv_sec` is already most negative, * further subtraction would cause integer overflow. @@ -423,7 +468,7 @@ static inline bool timespec_normalize(struct timespec *ts) } if ((ts->tv_nsec >= (long)NSEC_PER_SEC) && (ts->tv_sec > 0) && - (INT64_MAX - ts->tv_sec < sec)) { + (SYS_TIME_T_MAX - ts->tv_sec < sec)) { /* * When `tv_nsec` is >= `NSEC_PER_SEC` and `tv_sec` is already most * positive, further addition would cause integer overflow. @@ -444,7 +489,6 @@ static inline bool timespec_normalize(struct timespec *ts) __ASSERT_NO_MSG(timespec_is_valid(ts)); return true; - #endif } @@ -476,12 +520,12 @@ static inline bool timespec_add(struct timespec *a, const struct timespec *b) #else - if ((a->tv_sec < 0) && (b->tv_sec < 0) && (INT64_MIN - a->tv_sec > b->tv_sec)) { + if ((a->tv_sec < 0) && (b->tv_sec < 0) && (SYS_TIME_T_MIN - a->tv_sec > b->tv_sec)) { /* negative integer overflow would occur */ return false; } - if ((a->tv_sec > 0) && (b->tv_sec > 0) && (INT64_MAX - a->tv_sec < b->tv_sec)) { + if ((a->tv_sec > 0) && (b->tv_sec > 0) && (SYS_TIME_T_MAX - a->tv_sec < b->tv_sec)) { /* positive integer overflow would occur */ return false; } @@ -517,10 +561,8 @@ static inline bool timespec_negate(struct timespec *ts) #else - /* note: must check for 32-bit size here until #90029 is resolved */ - if (((sizeof(ts->tv_sec) == sizeof(int32_t)) && (ts->tv_sec == INT32_MIN)) || - ((sizeof(ts->tv_sec) == sizeof(int64_t)) && (ts->tv_sec == INT64_MIN))) { - /* -INT64_MIN > INT64_MAX, so +ve integer overflow would occur */ + if (ts->tv_sec == SYS_TIME_T_MIN) { + /* -SYS_TIME_T_MIN > SYS_TIME_T_MAX, so positive integer overflow would occur */ return false; } @@ -614,123 +656,104 @@ static inline bool timespec_equal(const struct timespec *a, const struct timespe * This function converts time durations expressed as Zephyr @ref k_timeout_t * objects to `struct timespec` objects. * + * @note This function will assert if assertions are enabled and @p timeout is not relative, + * (i.e. a timeout generated by `K_TIMEOUT_ABS_TICKS` or similar is used). + * * @param timeout the kernel timeout to convert * @param[out] ts the timespec to store the result */ static inline void timespec_from_timeout(k_timeout_t timeout, struct timespec *ts) { __ASSERT_NO_MSG(ts != NULL); - -#if defined(CONFIG_SPEED_OPTIMIZATIONS) - - uint64_t ns = k_ticks_to_ns_ceil64(timeout.ticks); - - *ts = (struct timespec){ - .tv_sec = (timeout.ticks == K_TICKS_FOREVER) * INT64_MAX + - (timeout.ticks != K_TICKS_FOREVER) * (ns / NSEC_PER_SEC), - .tv_nsec = (timeout.ticks == K_TICKS_FOREVER) * (NSEC_PER_SEC - 1) + - (timeout.ticks != K_TICKS_FOREVER) * (ns % NSEC_PER_SEC), - }; - -#else - - if (timeout.ticks == 0) { - /* This is equivalent to K_NO_WAIT, but without including */ - ts->tv_sec = 0; - ts->tv_nsec = 0; - } else if (timeout.ticks == K_TICKS_FOREVER) { - /* This is roughly equivalent to K_FOREVER, but not including */ - ts->tv_sec = (time_t)INT64_MAX; - ts->tv_nsec = NSEC_PER_SEC - 1; + __ASSERT_NO_MSG(Z_IS_TIMEOUT_RELATIVE(timeout) || + (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && + K_TIMEOUT_EQ(timeout, (k_timeout_t){K_TICKS_FOREVER}))); + + /* equivalent of K_FOREVER without including kernel.h */ + if (K_TIMEOUT_EQ(timeout, (k_timeout_t){K_TICKS_FOREVER})) { + /* duration == K_TICKS_FOREVER ticks */ + *ts = SYS_TIMESPEC_FOREVER; + /* equivalent of K_NO_WAIT without including kernel.h */ + } else if (K_TIMEOUT_EQ(timeout, (k_timeout_t){0})) { + /* duration <= 0 ticks */ + *ts = SYS_TIMESPEC_NO_WAIT; } else { - uint64_t ns = k_ticks_to_ns_ceil64(timeout.ticks); - - ts->tv_sec = ns / NSEC_PER_SEC; - ts->tv_nsec = ns - ts->tv_sec * NSEC_PER_SEC; + *ts = SYS_TICKS_TO_TIMESPEC(timeout.ticks); } -#endif - __ASSERT_NO_MSG(timespec_is_valid(ts)); } /** * @brief Convert a timespec to a kernel timeout * - * This function converts durations expressed as a `struct timespec` to Zephyr @ref k_timeout_t - * objects. + * This function converts a time duration, @p req, expressed as a `timespec` object, to a Zephyr + * @ref k_timeout_t object. + * + * If @p req contains a negative duration or if both `tv_sec` and `tv_nsec` fields are zero, this + * function will return @ref K_NO_WAIT. + * + * If @p req contains the maximum representable `timespec`, `{max(time_t), 999999999}`, then this + * function will return @ref K_FOREVER. * - * Given that the range of a `struct timespec` is much larger than the range of @ref k_timeout_t, - * and also given that the functions are only intended to be used to convert time durations - * (which are always positive), the function will saturate to @ref K_NO_WAIT if the `tv_sec` field - * of @a ts is negative. + * If @p req contains a value that is greater than the maximum equivalent tick duration, then this + * function will return the maximum representable tick duration (i.e. @p req will be rounded-down). * - * Similarly, if the duration is too large to fit in @ref k_timeout_t, the function will - * saturate to @ref K_FOREVER. + * Otherwise, this function will return the `k_timeout_t` that is rounded-up to a tick boundary. * - * @param ts the timespec to convert - * @return the kernel timeout + * If @p rem is not `NULL`, it will be set to the remainder of the conversion, i.e. the difference + * between the requested duration and the converted duration as a `timespec` object, approximately + * as shown below. + * + * ```python + * rem = requested_duration - converted_duration + * ``` + * + * @param req the requested `timespec` to convert + * @param[out] rem optional pointer to a `timespec` to store the remainder + * @return the corresponding kernel timeout */ -static inline k_timeout_t timespec_to_timeout(const struct timespec *ts) +static inline k_timeout_t timespec_to_timeout(const struct timespec *req, struct timespec *rem) { - __ASSERT_NO_MSG((ts != NULL) && timespec_is_valid(ts)); + k_timeout_t timeout; -#if defined(CONFIG_SPEED_OPTIMIZATIONS) - - return (k_timeout_t){ - /* note: must check for 32-bit size here until #90029 is resolved */ - .ticks = ((sizeof(ts->tv_sec) == sizeof(int32_t) && (ts->tv_sec == INT32_MAX) && - (ts->tv_nsec == NSEC_PER_SEC - 1)) || - ((sizeof(ts->tv_sec) == sizeof(int64_t)) && (ts->tv_sec == INT64_MAX) && - (ts->tv_nsec == NSEC_PER_SEC - 1))) * - K_TICKS_FOREVER + - ((sizeof(ts->tv_sec) == sizeof(int32_t) && (ts->tv_sec == INT32_MAX) && - (ts->tv_nsec == NSEC_PER_SEC - 1)) || - ((sizeof(ts->tv_sec) == sizeof(int64_t)) && (ts->tv_sec != INT64_MAX) && - (ts->tv_sec >= 0))) * - (IS_ENABLED(CONFIG_TIMEOUT_64BIT) - ? (int64_t)(CLAMP( - k_sec_to_ticks_floor64(ts->tv_sec) + - k_ns_to_ticks_floor64(ts->tv_nsec), - 0, (uint64_t)INT64_MAX)) - : (uint32_t)(CLAMP( - k_sec_to_ticks_floor64(ts->tv_sec) + - k_ns_to_ticks_floor64(ts->tv_nsec), - 0, (uint64_t)UINT32_MAX)))}; + __ASSERT_NO_MSG((req != NULL) && timespec_is_valid(req)); -#else + if (timespec_compare(req, &SYS_TIMESPEC_NO_WAIT) <= 0) { + if (rem != NULL) { + *rem = *req; + } + /* equivalent of K_NO_WAIT without including kernel.h */ + timeout.ticks = 0; + return timeout; + } - if ((ts->tv_sec < 0) || (ts->tv_sec == 0 && ts->tv_nsec == 0)) { - /* This is equivalent to K_NO_WAIT, but without including */ - return (k_timeout_t){ - .ticks = 0, - }; - /* note: must check for 32-bit size here until #90029 is resolved */ - } else if (((sizeof(ts->tv_sec) == sizeof(int32_t)) && (ts->tv_sec == INT32_MAX) && - (ts->tv_nsec == NSEC_PER_SEC - 1)) || - ((sizeof(ts->tv_sec) == sizeof(int64_t)) && (ts->tv_sec == INT64_MAX) && - (ts->tv_nsec == NSEC_PER_SEC - 1))) { - /* This is equivalent to K_FOREVER, but not including */ - return (k_timeout_t){ - .ticks = K_TICKS_FOREVER, - }; - } else { - if (IS_ENABLED(CONFIG_TIMEOUT_64BIT)) { - return (k_timeout_t){ - .ticks = (int64_t)CLAMP(k_sec_to_ticks_floor64(ts->tv_sec) + - k_ns_to_ticks_floor64(ts->tv_nsec), - 0, (uint64_t)INT64_MAX), - }; - } else { - return (k_timeout_t){ - .ticks = (uint32_t)CLAMP(k_sec_to_ticks_floor64(ts->tv_sec) + - k_ns_to_ticks_floor64(ts->tv_nsec), - 0, (uint64_t)UINT32_MAX), - }; + if (timespec_compare(req, &SYS_TIMESPEC_FOREVER) == 0) { + if (rem != NULL) { + *rem = SYS_TIMESPEC_NO_WAIT; } + /* equivalent of K_FOREVER without including kernel.h */ + timeout.ticks = K_TICKS_FOREVER; + return timeout; } -#endif + if (timespec_compare(req, &SYS_TIMESPEC_MAX) >= 0) { + /* round down to align to max ticks */ + timeout.ticks = K_TICK_MAX; + } else { + /* round up to align to next tick boundary */ + timeout.ticks = CLAMP(k_ns_to_ticks_ceil64(req->tv_nsec) + + k_sec_to_ticks_ceil64(req->tv_sec), + K_TICK_MIN, K_TICK_MAX); + } + + if (rem != NULL) { + timespec_from_timeout(timeout, rem); + timespec_sub(rem, req); + timespec_negate(rem); + } + + return timeout; } /** diff --git a/include/zephyr/sys/util.h b/include/zephyr/sys/util.h index 82ec9ad72ea1e..38d9b14ea71cb 100644 --- a/include/zephyr/sys/util.h +++ b/include/zephyr/sys/util.h @@ -432,6 +432,22 @@ extern "C" { */ #define IN_RANGE(val, min, max) ((val) >= (min) && (val) <= (max)) +/** + * Find number of contiguous bits which are not set in the bit mask (32 bits). + * + * It is possible to return immediately when requested number of bits is found or + * iterate over whole mask and return the best fit (smallest from available options). + * + * @param[in] mask 32 bit mask. + * @param[in] num_bits Number of bits to find. + * @param[in] total_bits Total number of LSB bits that can be used in the mask. + * @param[in] first_match If true returns when first match is found, else returns the best fit. + * + * @retval -1 Contiguous bits not found. + * @retval non-negative Starting index of the bits group. + */ +int bitmask_find_gap(uint32_t mask, size_t num_bits, size_t total_bits, bool first_match); + /** * @brief Is @p x a power of two? * @param x value to check @@ -645,49 +661,6 @@ static inline int64_t sign_extend_64(uint64_t value, uint8_t index) return (int64_t)(value << shift) >> shift; } -/** - * @brief Properly truncate a NULL-terminated UTF-8 string - * - * Take a NULL-terminated UTF-8 string and ensure that if the string has been - * truncated (by setting the NULL terminator) earlier by other means, that - * the string ends with a properly formatted UTF-8 character (1-4 bytes). - * - * Example: - * - * @code{.c} - * char test_str[] = "€€€"; - * char trunc_utf8[8]; - * - * printf("Original : %s\n", test_str); // €€€ - * strncpy(trunc_utf8, test_str, sizeof(trunc_utf8)); - * trunc_utf8[sizeof(trunc_utf8) - 1] = '\0'; - * printf("Bad : %s\n", trunc_utf8); // €€� - * utf8_trunc(trunc_utf8); - * printf("Truncated: %s\n", trunc_utf8); // €€ - * @endcode - * - * @param utf8_str NULL-terminated string - * - * @return Pointer to the @p utf8_str - */ -char *utf8_trunc(char *utf8_str); - -/** - * @brief Copies a UTF-8 encoded string from @p src to @p dst - * - * The resulting @p dst will always be NULL terminated if @p n is larger than 0, - * and the @p dst string will always be properly UTF-8 truncated. - * - * @param dst The destination of the UTF-8 string. - * @param src The source string - * @param n The size of the @p dst buffer. Maximum number of characters copied - * is @p n - 1. If 0 nothing will be done, and the @p dst will not be - * NULL terminated. - * - * @return Pointer to the @p dst - */ -char *utf8_lcpy(char *dst, const char *src, size_t n); - #define __z_log2d(x) (32 - __builtin_clz(x) - 1) #define __z_log2q(x) (64 - __builtin_clzll(x) - 1) #define __z_log2(x) (sizeof(__typeof__(x)) > 4 ? __z_log2q(x) : __z_log2d(x)) @@ -819,6 +792,41 @@ static inline bool util_eq(const void *m1, size_t len1, const void *m2, size_t l return len1 == len2 && (m1 == m2 || util_memeq(m1, m2, len1)); } +/** + * @brief Returns the number of bits set in a value + * + * @param value The value to count number of bits set of + * @param len The number of octets in @p value + */ +static inline size_t sys_count_bits(const void *value, size_t len) +{ + size_t cnt = 0U; + size_t i = 0U; + +#ifdef POPCOUNT + for (; i < len / sizeof(unsigned int); i++) { + unsigned int val; + (void)memcpy(&val, (const uint8_t *)value + i * sizeof(unsigned int), + sizeof(unsigned int)); + + cnt += POPCOUNT(val); + } + i *= sizeof(unsigned int); /* convert to a uint8_t index for the remainder (if any) */ +#endif + + for (; i < len; i++) { + uint8_t value_u8 = ((const uint8_t *)value)[i]; + + /* Implements Brian Kernighan’s Algorithm to count bits */ + while (value_u8) { + value_u8 &= (value_u8 - 1); + cnt++; + } + } + + return cnt; +} + #ifdef __cplusplus } #endif diff --git a/include/zephyr/sys/util_utf8.h b/include/zephyr/sys/util_utf8.h new file mode 100644 index 0000000000000..ee9a13a3534f1 --- /dev/null +++ b/include/zephyr/sys/util_utf8.h @@ -0,0 +1,93 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief UTF-8 utilities + * + * Misc UTF-8 utilities. + */ + +#ifndef ZEPHYR_INCLUDE_SYS_UTIL_UFT8_H_ +#define ZEPHYR_INCLUDE_SYS_UTIL_UFT8_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup sys-util + * @{ + */ + +/** + * @brief Properly truncate a NULL-terminated UTF-8 string + * + * Take a NULL-terminated UTF-8 string and ensure that if the string has been + * truncated (by setting the NULL terminator) earlier by other means, that + * the string ends with a properly formatted UTF-8 character (1-4 bytes). + * + * Example: + * + * @code{.c} + * char test_str[] = "€€€"; + * char trunc_utf8[8]; + * + * printf("Original : %s\n", test_str); // €€€ + * strncpy(trunc_utf8, test_str, sizeof(trunc_utf8)); + * trunc_utf8[sizeof(trunc_utf8) - 1] = '\0'; + * printf("Bad : %s\n", trunc_utf8); // €€� + * utf8_trunc(trunc_utf8); + * printf("Truncated: %s\n", trunc_utf8); // €€ + * @endcode + * + * @param utf8_str NULL-terminated string + * + * @return Pointer to the @p utf8_str + */ +char *utf8_trunc(char *utf8_str); + +/** + * @brief Copies a UTF-8 encoded string from @p src to @p dst + * + * The resulting @p dst will always be NULL terminated if @p n is larger than 0, + * and the @p dst string will always be properly UTF-8 truncated. + * + * @param dst The destination of the UTF-8 string. + * @param src The source string + * @param n The size of the @p dst buffer. Maximum number of characters copied + * is @p n - 1. If 0 nothing will be done, and the @p dst will not be + * NULL terminated. + * + * @return Pointer to the @p dst + */ +char *utf8_lcpy(char *dst, const char *src, size_t n); + +/** + * @brief Counts the characters in a UTF-8 encoded string @p s + * + * Counts the number of UTF-8 characters (code points) in a null-terminated string. + * This function steps through each UTF-8 sequence by checking leading byte patterns. + * It does not fully validate UTF-8 correctness, only counts characters. + * + * @param s The input string + * + * @return Number of UTF-8 characters in @p s on success or (negative) error code + * otherwise. + */ +int utf8_count_chars(const char *s); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_SYS_UTIL_UFT8_H_ */ diff --git a/include/zephyr/toolchain/llvm.h b/include/zephyr/toolchain/llvm.h index 8dbe3c0eadc92..e5b5a8d5d8b09 100644 --- a/include/zephyr/toolchain/llvm.h +++ b/include/zephyr/toolchain/llvm.h @@ -32,6 +32,26 @@ #include +/* clear out common version. The build assert assert from gcc.h is defined to be empty */ +#undef BUILD_ASSERT + +#if defined(__cplusplus) && (__cplusplus >= 201103L) + +/* C++11 has static_assert built in */ +#define BUILD_ASSERT(EXPR, MSG...) static_assert(EXPR, "" MSG) + +#elif !defined(__cplusplus) && ((__STDC_VERSION__) >= 201100) + +/* C11 has static_assert built in */ +#define BUILD_ASSERT(EXPR, MSG...) _Static_assert((EXPR), "" MSG) + +#else + +/* Rely on that the C-library provides a static assertion function */ +#define BUILD_ASSERT(EXPR, MSG...) _Static_assert((EXPR), "" MSG) + +#endif + #define TOOLCHAIN_WARNING_SIZEOF_ARRAY_DECAY "-Wsizeof-array-decay" #define TOOLCHAIN_WARNING_UNNEEDED_INTERNAL_DECLARATION "-Wunneeded-internal-declaration" diff --git a/include/zephyr/usb/bos.h b/include/zephyr/usb/bos.h index 79dd802bf26e9..da767786dd3f9 100644 --- a/include/zephyr/usb/bos.h +++ b/include/zephyr/usb/bos.h @@ -5,6 +5,12 @@ * SPDX-License-Identifier: Apache-2.0 */ +/** + * @file + * @brief USB Binary Device Object Store support + * @ingroup usb_bos + */ + #ifndef ZEPHYR_INCLUDE_USB_BOS_H_ #define ZEPHYR_INCLUDE_USB_BOS_H_ @@ -21,47 +27,103 @@ /** Root BOS Descriptor */ struct usb_bos_descriptor { + /** Size of this descriptor in bytes (5). */ uint8_t bLength; + /** Descriptor type. Must be set to @ref USB_DESC_BOS. */ uint8_t bDescriptorType; + /** + * Total length of this descriptor and all associated device + * capability descriptors. + */ uint16_t wTotalLength; + /** Number of device capability descriptors that follow. */ uint8_t bNumDeviceCaps; } __packed; /** Device capability type codes */ enum usb_bos_capability_types { + /** USB 2.0 Extension capability. */ USB_BOS_CAPABILITY_EXTENSION = 0x02, + /** Platform-specific capability (e.g., WebUSB, MS OS). */ USB_BOS_CAPABILITY_PLATFORM = 0x05, }; -/** BOS USB 2.0 extension capability descriptor */ +/** + * BOS USB 2.0 extension capability descriptor + * + * Used to indicate support for USB 2.0 Link Power Management (LPM) and associated best effort + * service latency (BESL) parameters. + */ struct usb_bos_capability_lpm { + /** Size of this descriptor in bytes. */ uint8_t bLength; + + /** Descriptor type. Must be set to @ref USB_DESC_DEVICE_CAPABILITY. */ uint8_t bDescriptorType; + + /** Device capability type. Must be @ref USB_BOS_CAPABILITY_EXTENSION. */ uint8_t bDevCapabilityType; + + /** + * Bitmap of supported attributes. + */ uint32_t bmAttributes; } __packed; -/** BOS platform capability descriptor */ +/** + * BOS platform capability descriptor + * + * Used to describe platform-specific capabilities, identified by a UUID. + */ struct usb_bos_platform_descriptor { + /** Size of this descriptor in bytes (20). */ uint8_t bLength; + /** Descriptor type. Must be set to @c USB_DESC_DEVICE_CAPABILITY. */ uint8_t bDescriptorType; + /** Device capability type. Must be @c USB_BOS_CAPABILITY_PLATFORM. */ uint8_t bDevCapabilityType; + /** Reserved (must be zero). */ uint8_t bReserved; + /** Platform capability UUID (16 bytes, little-endian). */ uint8_t PlatformCapabilityUUID[16]; } __packed; -/** WebUSB specific part of platform capability descriptor */ +/** + * WebUSB specific part of platform capability descriptor + * + * Defines the WebUSB-specific fields that extend the generic platform capability descriptor. + */ struct usb_bos_capability_webusb { + /** WebUSB specification version in BCD format (e.g., 0x0100). */ uint16_t bcdVersion; + /** + * Vendor-specific request code used by the host to retrieve WebUSB descriptors. + */ uint8_t bVendorCode; + + /** + * Index of the landing page string descriptor. + * Zero means no landing page is defined. + */ uint8_t iLandingPage; } __packed; -/** Microsoft OS 2.0 descriptor specific part of platform capability descriptor */ +/** + * Microsoft OS 2.0 descriptor specific part of platform capability descriptor + * + * Defines the Microsoft OS 2.0 descriptor set, used to describe device capabilities to Windows + * hosts. + */ struct usb_bos_capability_msos { + /** Windows version supported (e.g., 0x0A000000UL for Windows 10). */ uint32_t dwWindowsVersion; + /** Total length of the MS OS 2.0 descriptor set. */ uint16_t wMSOSDescriptorSetTotalLength; + /** + * Vendor-specific request code used to retrieve the MS OS 2.0 descriptor set. + */ uint8_t bMS_VendorCode; + /** Alternate enumeration code (or 0 if not used). */ uint8_t bAltEnumCode; } __packed; diff --git a/include/zephyr/usb/usbh.h b/include/zephyr/usb/usbh.h index 852d8b9ac6986..e2e6f3074000e 100644 --- a/include/zephyr/usb/usbh.h +++ b/include/zephyr/usb/usbh.h @@ -36,7 +36,7 @@ extern "C" { /** * USB host support runtime context */ -struct usbh_contex { +struct usbh_context { /** Name of the USB device */ const char *name; /** Access mutex */ @@ -53,7 +53,7 @@ struct usbh_contex { #define USBH_CONTROLLER_DEFINE(device_name, uhc_dev) \ SYS_BITARRAY_DEFINE_STATIC(ba_##device_name, 128); \ - static STRUCT_SECTION_ITERABLE(usbh_contex, device_name) = { \ + static STRUCT_SECTION_ITERABLE(usbh_context, device_name) = { \ .name = STRINGIFY(device_name), \ .mutex = Z_MUTEX_INITIALIZER(device_name.mutex), \ .dev = uhc_dev, \ @@ -80,20 +80,20 @@ struct usbh_class_data { struct usbh_code_triple code; /** Initialization of the class implementation */ - /* int (*init)(struct usbh_contex *const uhs_ctx); */ + /* int (*init)(struct usbh_context *const uhs_ctx); */ /** Request completion event handler */ - int (*request)(struct usbh_contex *const uhs_ctx, + int (*request)(struct usbh_context *const uhs_ctx, struct uhc_transfer *const xfer, int err); /** Device connected handler */ - int (*connected)(struct usbh_contex *const uhs_ctx); + int (*connected)(struct usbh_context *const uhs_ctx); /** Device removed handler */ - int (*removed)(struct usbh_contex *const uhs_ctx); + int (*removed)(struct usbh_context *const uhs_ctx); /** Bus remote wakeup handler */ - int (*rwup)(struct usbh_contex *const uhs_ctx); + int (*rwup)(struct usbh_context *const uhs_ctx); /** Bus suspended handler */ - int (*suspended)(struct usbh_contex *const uhs_ctx); + int (*suspended)(struct usbh_context *const uhs_ctx); /** Bus resumed handler */ - int (*resumed)(struct usbh_contex *const uhs_ctx); + int (*resumed)(struct usbh_context *const uhs_ctx); }; /** @@ -109,7 +109,7 @@ struct usbh_class_data { * * @return 0 on success, other values on fail. */ -int usbh_init(struct usbh_contex *uhs_ctx); +int usbh_init(struct usbh_context *uhs_ctx); /** * @brief Enable the USB host support and class instances @@ -120,7 +120,7 @@ int usbh_init(struct usbh_contex *uhs_ctx); * * @return 0 on success, other values on fail. */ -int usbh_enable(struct usbh_contex *uhs_ctx); +int usbh_enable(struct usbh_context *uhs_ctx); /** * @brief Disable the USB host support @@ -131,7 +131,7 @@ int usbh_enable(struct usbh_contex *uhs_ctx); * * @return 0 on success, other values on fail. */ -int usbh_disable(struct usbh_contex *uhs_ctx); +int usbh_disable(struct usbh_context *uhs_ctx); /** * @brief Shutdown the USB host support @@ -142,7 +142,7 @@ int usbh_disable(struct usbh_contex *uhs_ctx); * * @return 0 on success, other values on fail. */ -int usbh_shutdown(struct usbh_contex *const uhs_ctx); +int usbh_shutdown(struct usbh_context *const uhs_ctx); /** * @} diff --git a/include/zephyr/zbus/zbus.h b/include/zephyr/zbus/zbus.h index a6bdf8af0d81e..4911fe298f369 100644 --- a/include/zephyr/zbus/zbus.h +++ b/include/zephyr/zbus/zbus.h @@ -180,7 +180,7 @@ struct zbus_channel_observation_mask { }; /** - * @brief Structure for linking observers to chanels + * @brief Structure for linking observers to channels */ struct zbus_channel_observation { const struct zbus_channel *chan; diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 075e091cbb62d..7b7eabec0e20a 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -10,6 +10,17 @@ zephyr_syscall_header( ${ZEPHYR_BASE}/include/zephyr/sys/time_units.h ) +# Helper macro to append files to the kernel_files list +macro(kernel_sources_ifdef feature_toggle) + if(${${feature_toggle}}) + list(APPEND kernel_files ${ARGN}) + endif() +endmacro() + +macro(kernel_sources) + list(APPEND kernel_files ${ARGN}) +endmacro() + if(NOT CONFIG_ERRNO_IN_TLS AND NOT CONFIG_LIBC_ERRNO) zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/sys/errno_private.h) endif() @@ -47,7 +58,7 @@ else() # FIXME: SHADOW_VARS: Remove this once we have enabled -Wshadow globally. add_compile_options($) -list(APPEND kernel_files +kernel_sources( main_weak.c banner.c busy_wait.c @@ -61,14 +72,11 @@ list(APPEND kernel_files version.c ) -if(CONFIG_SCHED_CPU_MASK) -list(APPEND kernel_files +kernel_sources_ifdef(CONFIG_SCHED_CPU_MASK cpu_mask.c ) -endif() -if(CONFIG_MULTITHREADING) -list(APPEND kernel_files +kernel_sources_ifdef(CONFIG_MULTITHREADING idle.c mailbox.c msg_q.c @@ -81,59 +89,27 @@ list(APPEND kernel_files condvar.c thread.c sched.c + pipe.c ) +if(CONFIG_MULTITHREADING) if (CONFIG_SCHED_SCALABLE OR CONFIG_WAITQ_SCALABLE) -list(APPEND kernel_files priority_queues.c) +kernel_sources(priority_queues.c) endif() -# FIXME: Once the prior pipe implementation is removed, this should be included in the above list -if(NOT CONFIG_PIPES) -list(APPEND kernel_files pipe.c) -endif() # NOT CONFIG_PIPES -if(CONFIG_SMP) -list(APPEND kernel_files +kernel_sources_ifdef(CONFIG_SMP smp.c ipi.c) -endif() else() # CONFIG_MULTITHREADING -list(APPEND kernel_files - nothread.c - ) +kernel_sources(nothread.c) endif() # CONFIG_MULTITHREADING -if(CONFIG_TIMESLICING) -list(APPEND kernel_files - timeslicing.c) -endif() - -if(CONFIG_SPIN_VALIDATE) -list(APPEND kernel_files - spinlock_validate.c) -endif() - -if(CONFIG_IRQ_OFFLOAD) -list(APPEND kernel_files - irq_offload.c - ) -endif() - - -if(CONFIG_THREAD_MONITOR) -list(APPEND kernel_files - thread_monitor.c) -endif() - - -if(CONFIG_XIP) -list(APPEND kernel_files - xip.c) -endif() - -if(CONFIG_DEMAND_PAGING_STATS) -list(APPEND kernel_files - paging/statistics.c) -endif() +kernel_sources_ifdef(CONFIG_TIMESLICING timeslicing.c) +kernel_sources_ifdef(CONFIG_SPIN_VALIDATE spinlock_validate.c) +kernel_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) +kernel_sources_ifdef(CONFIG_BOOTARGS boot_args.c) +kernel_sources_ifdef(CONFIG_THREAD_MONITOR thread_monitor.c) +kernel_sources_ifdef(CONFIG_DEMAND_PAGING_STATS paging/statistics.c) add_library(kernel ${kernel_files}) @@ -153,7 +129,6 @@ target_sources_ifdef(CONFIG_ATOMIC_OPERATIONS_C kernel PRIVATE atomic_c.c) target_sources_ifdef(CONFIG_MMU kernel PRIVATE mmu.c) target_sources_ifdef(CONFIG_POLL kernel PRIVATE poll.c) target_sources_ifdef(CONFIG_EVENTS kernel PRIVATE events.c) -target_sources_ifdef(CONFIG_PIPES kernel PRIVATE pipes.c) target_sources_ifdef(CONFIG_SCHED_THREAD_USAGE kernel PRIVATE usage.c) target_sources_ifdef(CONFIG_OBJ_CORE kernel PRIVATE obj_core.c) diff --git a/kernel/Kconfig b/kernel/Kconfig index 524fe7a34a1db..bb2c5bade905b 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -742,20 +742,6 @@ config EVENTS Note that setting this option slightly increases the size of the thread structure. -config PIPES - bool "Pipe objects" - select DEPRECATED - help - This option enables kernel pipes. A pipe is a kernel object that - allows a thread to send a byte stream to another thread. Pipes can - be used to synchronously transfer chunks of data in whole or in part. - - Note that setting this option slightly increases the size of the - thread structure. - This Kconfig is deprecated and will be removed, by disabling this - kconfig another implementation of k_pipe will be available when - CONFIG_MULTITHREADING is enabled. - config KERNEL_MEM_POOL bool "Use Kernel Memory Pool" default y @@ -894,16 +880,6 @@ config BUSYWAIT_CPU_LOOPS_PER_USEC system timer support. If accuracy is very important then implementing arch_busy_wait() should be considered. -config XIP - bool "Execute in place" - help - This option allows the kernel to operate with its text and read-only - sections residing in ROM (or similar read-only memory). Not all boards - support this option so it must be used with care; you must also - supply a linker command file when building your image. Enabling this - option increases both the code and data footprint of the image. - - menu "Security Options" config REQUIRES_STACK_CANARIES @@ -1029,6 +1005,57 @@ config BOUNDS_CHECK_BYPASS_MITIGATION mitigations after bounds checking any array index parameters passed in from untrusted sources (user mode threads). When disabled, these macros do nothing. + +config HW_SHADOW_STACK + bool "Use hardware shadow stack mechanism to provide stack protection [EXPERIMENTAL]" + depends on ARCH_HAS_HW_SHADOW_STACK + select EXPERIMENTAL + help + This option enables the use of hardware shadow stack to provide + stack protection. When enabled, threads that provide a shadow stack + will use the hardware shadow stack to store the return address of + function calls. This will help to protect against return-oriented + programming (ROP) attacks. + + Currently, not all threads created by the kernel will have a shadow + stack. Indeed, threads need to manually attach a shadow stack to + use this feature. See the documentation for more information. + +config HW_SHADOW_STACK_PERCENTAGE_SIZE + int "Percentage of the stack size used to define shadow stack size" + depends on HW_SHADOW_STACK + default 30 + range 0 100 + help + This option specifies the percentage of the stack to be used for + shadow stack. The value is a percentage of the total stack size. + The default value is 30%, which means that the shadow stack size + will be 30% of the stack size, in *addition* to the stack size. + used for shadow stack. Note that this size is constrained by the + HW_SHADOW_STACK_MIN_SIZE config option. + +config HW_SHADOW_STACK_MIN_SIZE + int "Minimum size of the hardware shadow stack" + depends on HW_SHADOW_STACK + default 256 + help + This option specifies the minimum size of the hardware shadow stack, + in bytes, so that threads that use minimal stack size can still + have a sensible shadow stack size. The default value is 256 bytes, + which means that the shadow stack size will be at least 256 bytes, + even if the percentage defined via HW_SHADOW_STACK_PERCENTAGE_SIZE + would define a smaller size. + +config HW_SHADOW_STACK_ALLOW_REUSE + bool "Allow reuse of the shadow stack" + depends on HW_SHADOW_STACK + default y if ZTEST + help + This option allows the reuse of the shadow stack. This is meant to + accommodate thread reuse, when the same thread is created again, + such as done by the test suite. It is not meant to be used to share + the shadow stack between threads. + endmenu rsource "Kconfig.mem_domain" @@ -1082,20 +1109,20 @@ config STATIC_INIT_GNU will emit an error if constructors are needed and this option has been disabled. -config BOOTARGS +menuconfig BOOTARGS bool "Support bootargs" help Enables bootargs support and passing them to main(). +if BOOTARGS config DYNAMIC_BOOTARGS bool "Support dynamic bootargs" - depends on BOOTARGS help Enables dynamic bootargs support. config BOOTARGS_STRING string "static bootargs string" - depends on BOOTARGS && !DYNAMIC_BOOTARGS + depends on !DYNAMIC_BOOTARGS help Static bootargs string. It includes argv[0], so if its expected that it contains executable name it should be put at the beginning of this string. @@ -1103,10 +1130,11 @@ config BOOTARGS_STRING config BOOTARGS_ARGS_BUFFER_SIZE int "Size of buffer containing main arguments in bytes" default 1024 - depends on BOOTARGS help Configures size of buffer containing all arguments passed to main. +endif # BOOTARGS + endmenu rsource "Kconfig.device" diff --git a/kernel/Kconfig.smp b/kernel/Kconfig.smp index 33bc58a311ac3..3aecfccb7658d 100644 --- a/kernel/Kconfig.smp +++ b/kernel/Kconfig.smp @@ -48,6 +48,7 @@ config MP_MAX_NUM_CPUS config SCHED_IPI_SUPPORTED bool + select EVENTS help True if the architecture supports a call to arch_sched_broadcast_ipi() to broadcast an interrupt that will call z_sched_ipi() on other CPUs diff --git a/kernel/boot_args.c b/kernel/boot_args.c new file mode 100644 index 0000000000000..0aaf4f74414fa --- /dev/null +++ b/kernel/boot_args.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: Apache-2.0 + * Copyright The Zephyr Project contributors + */ + +#include +#include +#include +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +extern const char *get_bootargs(void); +char **prepare_main_args(int *argc) +{ +#ifdef CONFIG_DYNAMIC_BOOTARGS + const char *bootargs = get_bootargs(); +#else + const char bootargs[] = CONFIG_BOOTARGS_STRING; +#endif + + /* beginning of the buffer contains argument's strings, end of it contains argvs */ + static char args_buf[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; + char *strings_end = (char *)args_buf; + char **argv_begin = (char **)WB_DN( + args_buf + CONFIG_BOOTARGS_ARGS_BUFFER_SIZE - sizeof(char *)); + int i = 0; + + *argc = 0; + *argv_begin = NULL; + +#ifdef CONFIG_DYNAMIC_BOOTARGS + if (!bootargs) { + return argv_begin; + } +#endif + + while (1) { + while (isspace(bootargs[i])) { + i++; + } + + if (bootargs[i] == '\0') { + return argv_begin; + } + + if (strings_end + sizeof(char *) >= (char *)argv_begin) { + LOG_WRN("not enough space in args buffer to accommodate all bootargs" + " - bootargs truncated"); + return argv_begin; + } + + argv_begin--; + memmove(argv_begin, argv_begin + 1, *argc * sizeof(char *)); + argv_begin[*argc] = strings_end; + + bool quoted = false; + + if (bootargs[i] == '\"' || bootargs[i] == '\'') { + char delimiter = bootargs[i]; + + for (int j = i + 1; bootargs[j] != '\0'; j++) { + if (bootargs[j] == delimiter) { + quoted = true; + break; + } + } + } + + if (quoted) { + char delimiter = bootargs[i]; + + i++; /* strip quotes */ + while (bootargs[i] != delimiter + && strings_end < (char *)argv_begin) { + *strings_end++ = bootargs[i++]; + } + i++; /* strip quotes */ + } else { + while (!isspace(bootargs[i]) + && bootargs[i] != '\0' + && strings_end < (char *)argv_begin) { + *strings_end++ = bootargs[i++]; + } + } + + if (strings_end < (char *)argv_begin) { + *strings_end++ = '\0'; + } else { + LOG_WRN("not enough space in args buffer to accommodate all bootargs" + " - bootargs truncated"); + argv_begin[*argc] = NULL; + return argv_begin; + } + (*argc)++; + } +} diff --git a/kernel/device.c b/kernel/device.c index 88e1d074ab189..ec36f885ed813 100644 --- a/kernel/device.c +++ b/kernel/device.c @@ -13,6 +13,7 @@ #include #include #include +#include /** * @brief Initialize state for all static devices. @@ -27,6 +28,71 @@ void z_device_state_init(void) } } +int do_device_init(const struct device *dev) +{ + int rc = 0; + + if (dev->ops.init != NULL) { + rc = dev->ops.init(dev); + /* If initialization failed, record in dev->state->init_res + * the POSITIVE value of the resulting errno + */ + if (rc != 0) { + /* device's init function should return: + * 0 on success + * a negative value on failure (-errno) + * errno value maps to an uint8_t range as of now. + */ + __ASSERT(rc >= -UINT8_MAX && rc < 0, "device %s init: invalid error (%d)", + dev->name, rc); + + if (rc < 0) { + rc = -rc; + } + /* handle error value overflow in production + * this is likely a bug in the device's init function. Signals it + */ + if (rc > UINT8_MAX) { + rc = UINT8_MAX; + } + dev->state->init_res = rc; + } + } + + /* device initialization has been invoked */ + dev->state->initialized = true; + + if (rc == 0) { + /* Run automatic device runtime enablement */ + (void)pm_device_runtime_auto_enable(dev); + } + + /* here, the value of rc is either 0 or +errno + * flip the sign to return a negative value on failure as expected + */ + return -rc; +} + +int z_impl_device_init(const struct device *dev) +{ + if (dev->state->initialized) { + return -EALREADY; + } + + return do_device_init(dev); +} + +#ifdef CONFIG_USERSPACE +static inline int z_vrfy_device_init(const struct device *dev) +{ + K_OOPS(K_SYSCALL_OBJ_INIT(dev, K_OBJ_ANY)); + + return z_impl_device_init(dev); +} +#include +#endif + + const struct device *z_impl_device_get_binding(const char *name) { /* A null string identifies no device. So does an empty diff --git a/kernel/events.c b/kernel/events.c index 038697d931f98..8fd8984481265 100644 --- a/kernel/events.c +++ b/kernel/events.c @@ -38,11 +38,13 @@ #define K_EVENT_WAIT_ALL 0x01 /* Wait for all events */ #define K_EVENT_WAIT_MASK 0x01 -#define K_EVENT_WAIT_RESET 0x02 /* Reset events prior to waiting */ +#define K_EVENT_OPTION_RESET 0x02 /* Reset events prior to waiting */ +#define K_EVENT_OPTION_CLEAR 0x04 /* Clear events that are received */ struct event_walk_data { struct k_thread *head; uint32_t events; + uint32_t clear_events; }; #ifdef CONFIG_OBJ_CORE_EVENT @@ -77,7 +79,7 @@ void z_vrfy_k_event_init(struct k_event *event) #endif /* CONFIG_USERSPACE */ /** - * @brief determine if desired set of events been satisfied + * @brief determine the set of events that have been satisfied * * This routine determines if the current set of events satisfies the desired * set of events. If @a wait_condition is K_EVENT_WAIT_ALL, then at least @@ -85,30 +87,47 @@ void z_vrfy_k_event_init(struct k_event *event) * wait_condition is not K_EVENT_WAIT_ALL, it is assumed to be K_EVENT_WAIT_ANY. * In the K_EVENT_WAIT_ANY case, the request is satisfied when any of the * current set of events are present in the desired set of events. + * + * @return event bits that satisfy the wait condition or zero */ -static bool are_wait_conditions_met(uint32_t desired, uint32_t current, - unsigned int wait_condition) +static uint32_t are_wait_conditions_met(uint32_t desired, uint32_t current, + unsigned int wait_condition) { - uint32_t match = current & desired; + uint32_t match = current & desired; - if (wait_condition == K_EVENT_WAIT_ALL) { - return match == desired; + if ((wait_condition == K_EVENT_WAIT_ALL) && (match != desired)) { + /* special case for K_EVENT_WAIT_ALL */ + return 0; } - /* wait_condition assumed to be K_EVENT_WAIT_ANY */ - - return match != 0; + /* return the matched events for any wait condition */ + return match; } static int event_walk_op(struct k_thread *thread, void *data) { - unsigned int wait_condition; + uint32_t match; + unsigned int wait_condition; struct event_walk_data *event_data = data; wait_condition = thread->event_options & K_EVENT_WAIT_MASK; - if (are_wait_conditions_met(thread->events, event_data->events, - wait_condition)) { + match = are_wait_conditions_met(thread->events, event_data->events, + wait_condition); + if (match != 0) { + /* + * The wait conditions have been satisfied. So, set the + * received events and then add this thread to the list + * of threads to unpend. + * + * NOTE: thread event options can consume an event + */ + thread->events = match; + if (thread->event_options & K_EVENT_OPTION_CLEAR) { + event_data->clear_events |= match; + } + thread->next_event_link = event_data->head; + event_data->head = thread; /* * Events create a list of threads to wake up. We do @@ -117,13 +136,6 @@ static int event_walk_op(struct k_thread *thread, void *data) * have been processed. */ thread->no_wake_on_timeout = true; - - /* - * The wait conditions have been satisfied. Add this - * thread to the list of threads to unpend. - */ - thread->next_event_link = event_data->head; - event_data->head = thread; z_abort_timeout(&thread->base.timeout); } @@ -147,8 +159,7 @@ static uint32_t k_event_post_internal(struct k_event *event, uint32_t events, previous_events = event->events & events_mask; events = (event->events & ~events_mask) | (events & events_mask); - event->events = events; - data.events = events; + /* * Posting an event has the potential to wake multiple pended threads. * It is desirable to unpend all affected threads simultaneously. This @@ -159,6 +170,8 @@ static uint32_t k_event_post_internal(struct k_event *event, uint32_t events, * 3. Ready each of the threads in the linked list */ + data.events = events; + data.clear_events = 0; z_sched_waitq_walk(&event->wait_q, event_walk_op, &data); if (data.head != NULL) { @@ -166,13 +179,15 @@ static uint32_t k_event_post_internal(struct k_event *event, uint32_t events, struct k_thread *next; do { arch_thread_return_value_set(thread, 0); - thread->events = events; next = thread->next_event_link; z_sched_wake_thread(thread, false); thread = next; } while (thread != NULL); } + /* stash any events not consumed */ + event->events = data.events & ~data.clear_events; + z_reschedule(&event->lock, key); SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_event, post, event, events, @@ -262,21 +277,22 @@ static uint32_t k_event_wait_internal(struct k_event *event, uint32_t events, k_spinlock_key_t key = k_spin_lock(&event->lock); - if (options & K_EVENT_WAIT_RESET) { + if (options & K_EVENT_OPTION_RESET) { event->events = 0; } /* Test if the wait conditions have already been met. */ - - if (are_wait_conditions_met(events, event->events, wait_condition)) { - rv = event->events; + rv = are_wait_conditions_met(events, event->events, wait_condition); + if (rv != 0) { + /* clear the events that are matched */ + if (options & K_EVENT_OPTION_CLEAR) { + event->events &= ~rv; + } k_spin_unlock(&event->lock, key); goto out; } - /* Match conditions have not been met. */ - if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) { k_spin_unlock(&event->lock, key); goto out; @@ -299,10 +315,9 @@ static uint32_t k_event_wait_internal(struct k_event *event, uint32_t events, } out: - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_event, wait, event, - events, rv & events); + SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_event, wait, event, events, rv); - return rv & events; + return rv; } /** @@ -311,7 +326,7 @@ static uint32_t k_event_wait_internal(struct k_event *event, uint32_t events, uint32_t z_impl_k_event_wait(struct k_event *event, uint32_t events, bool reset, k_timeout_t timeout) { - uint32_t options = reset ? K_EVENT_WAIT_RESET : 0; + uint32_t options = reset ? K_EVENT_OPTION_RESET : 0; return k_event_wait_internal(event, events, options, timeout); } @@ -331,7 +346,7 @@ uint32_t z_vrfy_k_event_wait(struct k_event *event, uint32_t events, uint32_t z_impl_k_event_wait_all(struct k_event *event, uint32_t events, bool reset, k_timeout_t timeout) { - uint32_t options = reset ? (K_EVENT_WAIT_RESET | K_EVENT_WAIT_ALL) + uint32_t options = reset ? (K_EVENT_OPTION_RESET | K_EVENT_WAIT_ALL) : K_EVENT_WAIT_ALL; return k_event_wait_internal(event, events, options, timeout); @@ -347,6 +362,45 @@ uint32_t z_vrfy_k_event_wait_all(struct k_event *event, uint32_t events, #include #endif /* CONFIG_USERSPACE */ +uint32_t z_impl_k_event_wait_safe(struct k_event *event, uint32_t events, + bool reset, k_timeout_t timeout) +{ + uint32_t options = reset ? (K_EVENT_OPTION_CLEAR | K_EVENT_OPTION_RESET) + : K_EVENT_OPTION_CLEAR; + + return k_event_wait_internal(event, events, options, timeout); +} + +#ifdef CONFIG_USERSPACE +uint32_t z_vrfy_k_event_wait_safe(struct k_event *event, uint32_t events, + bool reset, k_timeout_t timeout) +{ + K_OOPS(K_SYSCALL_OBJ(event, K_OBJ_EVENT)); + return z_impl_k_event_wait_safe(event, events, reset, timeout); +} +#include +#endif /* CONFIG_USERSPACE */ + +uint32_t z_impl_k_event_wait_all_safe(struct k_event *event, uint32_t events, + bool reset, k_timeout_t timeout) +{ + uint32_t options = reset ? (K_EVENT_OPTION_CLEAR | + K_EVENT_OPTION_RESET | K_EVENT_WAIT_ALL) + : (K_EVENT_OPTION_CLEAR | K_EVENT_WAIT_ALL); + + return k_event_wait_internal(event, events, options, timeout); +} + +#ifdef CONFIG_USERSPACE +uint32_t z_vrfy_k_event_wait_all_safe(struct k_event *event, uint32_t events, + bool reset, k_timeout_t timeout) +{ + K_OOPS(K_SYSCALL_OBJ(event, K_OBJ_EVENT)); + return z_impl_k_event_wait_all_safe(event, events, reset, timeout); +} +#include +#endif /* CONFIG_USERSPACE */ + #ifdef CONFIG_OBJ_CORE_EVENT static int init_event_obj_core_list(void) { diff --git a/kernel/include/ipi.h b/kernel/include/ipi.h index b353a676d4624..95070787dcb84 100644 --- a/kernel/include/ipi.h +++ b/kernel/include/ipi.h @@ -17,6 +17,8 @@ (IS_ENABLED(CONFIG_IPI_OPTIMIZE) ? BIT(cpu_id) : IPI_ALL_CPUS_MASK) +void z_sched_ipi(void); + /* defined in ipi.c when CONFIG_SMP=y */ #ifdef CONFIG_SMP void flag_ipi(uint32_t ipi_mask); diff --git a/kernel/include/kernel_internal.h b/kernel/include/kernel_internal.h index eadacf936c964..c731a27b286a8 100644 --- a/kernel/include/kernel_internal.h +++ b/kernel/include/kernel_internal.h @@ -16,6 +16,7 @@ #include #include +#include #include #ifndef _ASMLANGUAGE @@ -31,42 +32,9 @@ void z_init_cpu(int id); void z_init_thread_base(struct _thread_base *thread_base, int priority, uint32_t initial_state, unsigned int options); -/* Early boot functions */ -void z_early_memset(void *dst, int c, size_t n); -void z_early_memcpy(void *dst, const void *src, size_t n); - -void z_bss_zero(void); -#ifdef CONFIG_XIP -void z_data_copy(void); -#else -static inline void z_data_copy(void) -{ - /* Do nothing */ -} -#endif /* CONFIG_XIP */ - -#ifdef CONFIG_LINKER_USE_BOOT_SECTION -void z_bss_zero_boot(void); -#else -static inline void z_bss_zero_boot(void) -{ - /* Do nothing */ -} -#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ - -#ifdef CONFIG_LINKER_USE_PINNED_SECTION -void z_bss_zero_pinned(void); -#else -static inline void z_bss_zero_pinned(void) -{ - /* Do nothing */ -} -#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ FUNC_NORETURN void z_cstart(void); -void z_device_state_init(void); - extern FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry, void *p1, void *p2, void *p3); @@ -144,9 +112,6 @@ extern int z_stack_adjust_initialized; extern struct k_thread z_main_thread; -#ifdef CONFIG_MULTITHREADING -extern struct k_thread z_idle_threads[CONFIG_MP_MAX_NUM_CPUS]; -#endif /* CONFIG_MULTITHREADING */ K_KERNEL_PINNED_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_ISR_STACK_SIZE); K_THREAD_STACK_DECLARE(z_main_stack, CONFIG_MAIN_STACK_SIZE); diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h index 171e25cc37beb..8910529031b4d 100644 --- a/kernel/include/ksched.h +++ b/kernel/include/ksched.h @@ -65,12 +65,10 @@ void *z_get_next_switch_handle(void *interrupted); void z_time_slice(void); void z_reset_time_slice(struct k_thread *curr); -void z_sched_ipi(void); void z_sched_start(struct k_thread *thread); void z_ready_thread(struct k_thread *thread); void z_requeue_current(struct k_thread *curr); struct k_thread *z_swap_next_thread(void); -void z_thread_abort(struct k_thread *thread); void move_thread_to_end_of_prio_q(struct k_thread *thread); bool thread_is_sliceable(struct k_thread *thread); diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h index 45a1fec06a1a5..70cefba25ad94 100644 --- a/kernel/include/kthread.h +++ b/kernel/include/kthread.h @@ -30,6 +30,10 @@ extern struct k_spinlock z_thread_monitor_lock; #endif /* CONFIG_THREAD_MONITOR */ +#ifdef CONFIG_MULTITHREADING +extern struct k_thread z_idle_threads[CONFIG_MP_MAX_NUM_CPUS]; +#endif /* CONFIG_MULTITHREADING */ + void idle(void *unused1, void *unused2, void *unused3); /* clean up when a thread is aborted */ @@ -42,6 +46,7 @@ void z_thread_monitor_exit(struct k_thread *thread); } while (false) #endif /* CONFIG_THREAD_MONITOR */ +void z_thread_abort(struct k_thread *thread); static inline void thread_schedule_new(struct k_thread *thread, k_timeout_t delay) { diff --git a/kernel/init.c b/kernel/init.c index dd9f3d7258f58..1ce417276d60b 100644 --- a/kernel/init.c +++ b/kernel/init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -37,8 +38,9 @@ #include #include #include -#include #include +#include + LOG_MODULE_REGISTER(os, CONFIG_KERNEL_LOG_LEVEL); /* the only struct z_kernel instance */ @@ -177,123 +179,6 @@ static struct k_obj_core_stats_desc kernel_stats_desc = { #endif /* CONFIG_OBJ_CORE_STATS_SYSTEM */ #endif /* CONFIG_OBJ_CORE_SYSTEM */ -/* LCOV_EXCL_START - * - * This code is called so early in the boot process that code coverage - * doesn't work properly. In addition, not all arches call this code, - * some like x86 do this with optimized assembly - */ - -/** - * @brief equivalent of memset() for early boot usage - * - * Architectures that can't safely use the regular (optimized) memset very - * early during boot because e.g. hardware isn't yet sufficiently initialized - * may override this with their own safe implementation. - */ -__boot_func -void __weak z_early_memset(void *dst, int c, size_t n) -{ - (void) memset(dst, c, n); -} - -/** - * @brief equivalent of memcpy() for early boot usage - * - * Architectures that can't safely use the regular (optimized) memcpy very - * early during boot because e.g. hardware isn't yet sufficiently initialized - * may override this with their own safe implementation. - */ -__boot_func -void __weak z_early_memcpy(void *dst, const void *src, size_t n) -{ - (void) memcpy(dst, src, n); -} - -/** - * @brief Clear BSS - * - * This routine clears the BSS region, so all bytes are 0. - */ -__boot_func -void z_bss_zero(void) -{ - if (IS_ENABLED(CONFIG_SKIP_BSS_CLEAR)) { - return; - } - - z_early_memset(__bss_start, 0, __bss_end - __bss_start); -#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm)) - z_early_memset(&__ccm_bss_start, 0, - (uintptr_t) &__ccm_bss_end - - (uintptr_t) &__ccm_bss_start); -#endif -#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) - z_early_memset(&__dtcm_bss_start, 0, - (uintptr_t) &__dtcm_bss_end - - (uintptr_t) &__dtcm_bss_start); -#endif -#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ocm)) - z_early_memset(&__ocm_bss_start, 0, - (uintptr_t) &__ocm_bss_end - - (uintptr_t) &__ocm_bss_start); -#endif -#ifdef CONFIG_CODE_DATA_RELOCATION - extern void bss_zeroing_relocation(void); - - bss_zeroing_relocation(); -#endif /* CONFIG_CODE_DATA_RELOCATION */ -#ifdef CONFIG_COVERAGE_GCOV - z_early_memset(&__gcov_bss_start, 0, - ((uintptr_t) &__gcov_bss_end - (uintptr_t) &__gcov_bss_start)); -#endif /* CONFIG_COVERAGE_GCOV */ -#ifdef CONFIG_NOCACHE_MEMORY -z_early_memset(&_nocache_ram_start, 0, - (uintptr_t) &_nocache_ram_end - - (uintptr_t) &_nocache_ram_start); -#endif -} - -#ifdef CONFIG_LINKER_USE_BOOT_SECTION -/** - * @brief Clear BSS within the boot region - * - * This routine clears the BSS within the boot region. - * This is separate from z_bss_zero() as boot region may - * contain symbols required for the boot process before - * paging is initialized. - */ -__boot_func -void z_bss_zero_boot(void) -{ - z_early_memset(&lnkr_boot_bss_start, 0, - (uintptr_t)&lnkr_boot_bss_end - - (uintptr_t)&lnkr_boot_bss_start); -} -#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ - -#ifdef CONFIG_LINKER_USE_PINNED_SECTION -/** - * @brief Clear BSS within the pinned region - * - * This routine clears the BSS within the pinned region. - * This is separate from z_bss_zero() as pinned region may - * contain symbols required for the boot process before - * paging is initialized. - */ -#ifdef CONFIG_LINKER_USE_BOOT_SECTION -__boot_func -#else -__pinned_func -#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ -void z_bss_zero_pinned(void) -{ - z_early_memset(&lnkr_pinned_bss_start, 0, - (uintptr_t)&lnkr_pinned_bss_end - - (uintptr_t)&lnkr_pinned_bss_start); -} -#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ - #ifdef CONFIG_REQUIRES_STACK_CANARIES #ifdef CONFIG_STACK_CANARIES_TLS extern Z_THREAD_LOCAL volatile uintptr_t __stack_chk_guard; @@ -307,34 +192,20 @@ extern volatile uintptr_t __stack_chk_guard; __pinned_bss bool z_sys_post_kernel; -static int do_device_init(const struct device *dev) -{ - int rc = 0; - - if (dev->ops.init != NULL) { - rc = dev->ops.init(dev); - /* Mark device initialized. If initialization - * failed, record the error condition. - */ - if (rc != 0) { - if (rc < 0) { - rc = -rc; - } - if (rc > UINT8_MAX) { - rc = UINT8_MAX; - } - dev->state->init_res = rc; - } - } - - dev->state->initialized = true; +/* defined in device.c */ +extern int do_device_init(const struct device *dev); - if (rc == 0) { - /* Run automatic device runtime enablement */ - (void)pm_device_runtime_auto_enable(dev); +/** + * @brief Initialize state for all static devices. + * + * The state object is always zero-initialized, but this may not be + * sufficient. + */ +static void z_device_state_init(void) +{ + STRUCT_SECTION_FOREACH(device, dev) { + k_object_init(dev); } - - return rc; } /** @@ -380,116 +251,9 @@ static void z_sys_init_run_level(enum init_level level) } } - -int z_impl_device_init(const struct device *dev) -{ - if (dev->state->initialized) { - return -EALREADY; - } - - return do_device_init(dev); -} - -#ifdef CONFIG_USERSPACE -static inline int z_vrfy_device_init(const struct device *dev) -{ - K_OOPS(K_SYSCALL_OBJ_INIT(dev, K_OBJ_ANY)); - - return z_impl_device_init(dev); -} -#include -#endif - +/* defined in banner.c */ extern void boot_banner(void); -#ifdef CONFIG_BOOTARGS -extern const char *get_bootargs(void); -static char **prepare_main_args(int *argc) -{ -#ifdef CONFIG_DYNAMIC_BOOTARGS - const char *bootargs = get_bootargs(); -#else - const char bootargs[] = CONFIG_BOOTARGS_STRING; -#endif - - /* beginning of the buffer contains argument's strings, end of it contains argvs */ - static char args_buf[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE]; - char *strings_end = (char *)args_buf; - char **argv_begin = (char **)WB_DN( - args_buf + CONFIG_BOOTARGS_ARGS_BUFFER_SIZE - sizeof(char *)); - int i = 0; - - *argc = 0; - *argv_begin = NULL; - -#ifdef CONFIG_DYNAMIC_BOOTARGS - if (!bootargs) { - return argv_begin; - } -#endif - - while (1) { - while (isspace(bootargs[i])) { - i++; - } - - if (bootargs[i] == '\0') { - return argv_begin; - } - - if (strings_end + sizeof(char *) >= (char *)argv_begin) { - LOG_WRN("not enough space in args buffer to accommodate all bootargs" - " - bootargs truncated"); - return argv_begin; - } - - argv_begin--; - memmove(argv_begin, argv_begin + 1, *argc * sizeof(char *)); - argv_begin[*argc] = strings_end; - - bool quoted = false; - - if (bootargs[i] == '\"' || bootargs[i] == '\'') { - char delimiter = bootargs[i]; - - for (int j = i + 1; bootargs[j] != '\0'; j++) { - if (bootargs[j] == delimiter) { - quoted = true; - break; - } - } - } - - if (quoted) { - char delimiter = bootargs[i]; - - i++; /* strip quotes */ - while (bootargs[i] != delimiter - && strings_end < (char *)argv_begin) { - *strings_end++ = bootargs[i++]; - } - i++; /* strip quotes */ - } else { - while (!isspace(bootargs[i]) - && bootargs[i] != '\0' - && strings_end < (char *)argv_begin) { - *strings_end++ = bootargs[i++]; - } - } - - if (strings_end < (char *)argv_begin) { - *strings_end++ = '\0'; - } else { - LOG_WRN("not enough space in args buffer to accommodate all bootargs" - " - bootargs truncated"); - argv_begin[*argc] = NULL; - return argv_begin; - } - (*argc)++; - } -} - -#endif #ifdef CONFIG_STATIC_INIT_GNU @@ -576,6 +340,7 @@ static void bg_thread_main(void *unused1, void *unused2, void *unused3) #ifdef CONFIG_BOOTARGS extern int main(int, char **); + extern char **prepare_main_args(int *argc); int argc = 0; char **argv = prepare_main_args(&argc); @@ -657,6 +422,10 @@ void z_init_cpu(int id) sizeof(struct k_cycle_stats)); #endif #endif + +#ifdef CONFIG_SCHED_IPI_SUPPORTED + sys_dlist_init(&_kernel.cpus[id].ipi_workq); +#endif } /** @@ -749,7 +518,7 @@ void __weak z_early_rand_get(uint8_t *buf, size_t length) state = state * 2862933555777941757ULL + 3037000493ULL; val = (uint32_t)(state >> 32); rc = MIN(length, sizeof(val)); - z_early_memcpy((void *)buf, &val, rc); + arch_early_memcpy((void *)buf, &val, rc); length -= rc; buf += rc; diff --git a/kernel/ipi.c b/kernel/ipi.c index 3c16fa1369746..a6b6ad6db4291 100644 --- a/kernel/ipi.c +++ b/kernel/ipi.c @@ -8,11 +8,12 @@ #include #include +static struct k_spinlock ipi_lock; + #ifdef CONFIG_TRACE_SCHED_IPI extern void z_trace_sched_ipi(void); #endif - void flag_ipi(uint32_t ipi_mask) { #if defined(CONFIG_SCHED_IPI_SUPPORTED) @@ -75,6 +76,7 @@ void signal_pending_ipi(void) * pending_ipi, the IPI will be sent the next time through * this code. */ + #if defined(CONFIG_SCHED_IPI_SUPPORTED) if (arch_num_cpus() > 1) { uint32_t cpu_bitmap; @@ -91,6 +93,92 @@ void signal_pending_ipi(void) #endif /* CONFIG_SCHED_IPI_SUPPORTED */ } +#ifdef CONFIG_SCHED_IPI_SUPPORTED +static struct k_ipi_work *first_ipi_work(sys_dlist_t *list) +{ + sys_dnode_t *work = sys_dlist_peek_head(list); + unsigned int cpu_id = _current_cpu->id; + + return (work == NULL) ? NULL + : CONTAINER_OF(work, struct k_ipi_work, node[cpu_id]); +} + +int k_ipi_work_add(struct k_ipi_work *work, uint32_t cpu_bitmask, + k_ipi_func_t func) +{ + __ASSERT(work != NULL, ""); + __ASSERT(func != NULL, ""); + + k_spinlock_key_t key = k_spin_lock(&ipi_lock); + + /* Verify the IPI work item is not currently in use */ + + if (k_event_wait_all(&work->event, work->bitmask, + false, K_NO_WAIT) != work->bitmask) { + k_spin_unlock(&ipi_lock, key); + return -EBUSY; + } + + /* + * Add the IPI work item to the list(s)--but not for the current + * CPU as the architecture may not support sending an IPI to itself. + */ + + unsigned int cpu_id = _current_cpu->id; + + cpu_bitmask &= (IPI_ALL_CPUS_MASK & ~BIT(cpu_id)); + + k_event_clear(&work->event, IPI_ALL_CPUS_MASK); + work->func = func; + work->bitmask = cpu_bitmask; + + for (unsigned int id = 0; id < arch_num_cpus(); id++) { + if ((cpu_bitmask & BIT(id)) != 0) { + sys_dlist_append(&_kernel.cpus[id].ipi_workq, &work->node[id]); + } + } + + flag_ipi(cpu_bitmask); + + k_spin_unlock(&ipi_lock, key); + + return 0; +} + +int k_ipi_work_wait(struct k_ipi_work *work, k_timeout_t timeout) +{ + uint32_t rv = k_event_wait_all(&work->event, work->bitmask, + false, timeout); + + return (rv == 0) ? -EAGAIN : 0; +} + +void k_ipi_work_signal(void) +{ + signal_pending_ipi(); +} + +static void ipi_work_process(sys_dlist_t *list) +{ + unsigned int cpu_id = _current_cpu->id; + + k_spinlock_key_t key = k_spin_lock(&ipi_lock); + + for (struct k_ipi_work *work = first_ipi_work(list); + work != NULL; work = first_ipi_work(list)) { + sys_dlist_remove(&work->node[cpu_id]); + k_spin_unlock(&ipi_lock, key); + + work->func(work); + + key = k_spin_lock(&ipi_lock); + k_event_post(&work->event, BIT(cpu_id)); + } + + k_spin_unlock(&ipi_lock, key); +} +#endif /* CONFIG_SCHED_IPI_SUPPORTED */ + void z_sched_ipi(void) { /* NOTE: When adding code to this, make sure this is called @@ -109,4 +197,8 @@ void z_sched_ipi(void) #ifdef CONFIG_ARCH_IPI_LAZY_COPROCESSORS_SAVE arch_ipi_lazy_coprocessors_save(); #endif + +#ifdef CONFIG_SCHED_IPI_SUPPORTED + ipi_work_process(&_kernel.cpus[_current_cpu->id].ipi_workq); +#endif } diff --git a/kernel/mmu.c b/kernel/mmu.c index cb83b2f117618..322fc61c5c0b0 100644 --- a/kernel/mmu.c +++ b/kernel/mmu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -1176,7 +1177,7 @@ void z_mem_manage_init(void) * and the BSS pages can be brought into physical * memory to be cleared. */ - z_bss_zero(); + arch_bss_zero(); #endif /* CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT */ } diff --git a/kernel/pipes.c b/kernel/pipes.c deleted file mode 100644 index 11d0d936f6b0f..0000000000000 --- a/kernel/pipes.c +++ /dev/null @@ -1,842 +0,0 @@ -/* - * Copyright (c) 2016 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * - * @brief Pipes - */ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -struct waitq_walk_data { - sys_dlist_t *list; - size_t bytes_requested; - size_t bytes_available; -}; - -static int pipe_get_internal(k_spinlock_key_t key, struct k_pipe *pipe, - void *data, size_t bytes_to_read, - size_t *bytes_read, size_t min_xfer, - k_timeout_t timeout); -#ifdef CONFIG_OBJ_CORE_PIPE -static struct k_obj_type obj_type_pipe; -#endif /* CONFIG_OBJ_CORE_PIPE */ - - -void z_impl_k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size) -{ - pipe->buffer = buffer; - pipe->size = size; - pipe->bytes_used = 0U; - pipe->read_index = 0U; - pipe->write_index = 0U; - pipe->lock = (struct k_spinlock){}; - z_waitq_init(&pipe->wait_q.writers); - z_waitq_init(&pipe->wait_q.readers); - SYS_PORT_TRACING_OBJ_INIT(k_pipe, pipe, buffer, size); - - pipe->flags = 0; - -#if defined(CONFIG_POLL) - sys_dlist_init(&pipe->poll_events); -#endif /* CONFIG_POLL */ - k_object_init(pipe); - -#ifdef CONFIG_OBJ_CORE_PIPE - k_obj_core_init_and_link(K_OBJ_CORE(pipe), &obj_type_pipe); -#endif /* CONFIG_OBJ_CORE_PIPE */ -} - -int z_impl_k_pipe_alloc_init(struct k_pipe *pipe, size_t size) -{ - void *buffer; - int ret; - - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, alloc_init, pipe); - - if (size != 0U) { - buffer = z_thread_malloc(size); - if (buffer != NULL) { - k_pipe_init(pipe, buffer, size); - pipe->flags = K_PIPE_FLAG_ALLOC; - ret = 0; - } else { - ret = -ENOMEM; - } - } else { - k_pipe_init(pipe, NULL, 0U); - ret = 0; - } - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, alloc_init, pipe, ret); - - return ret; -} - -#ifdef CONFIG_USERSPACE -static inline void z_vrfy_k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size) -{ - K_OOPS(K_SYSCALL_OBJ_NEVER_INIT(pipe, K_OBJ_PIPE)); - K_OOPS(K_SYSCALL_MEMORY_WRITE(buffer, size)); - - z_impl_k_pipe_init(pipe, buffer, size); -} -#include - -static inline int z_vrfy_k_pipe_alloc_init(struct k_pipe *pipe, size_t size) -{ - K_OOPS(K_SYSCALL_OBJ_NEVER_INIT(pipe, K_OBJ_PIPE)); - - return z_impl_k_pipe_alloc_init(pipe, size); -} -#include -#endif /* CONFIG_USERSPACE */ - -static inline bool handle_poll_events(struct k_pipe *pipe) -{ -#ifdef CONFIG_POLL - return z_handle_obj_poll_events(&pipe->poll_events, K_POLL_STATE_PIPE_DATA_AVAILABLE); -#else - ARG_UNUSED(pipe); - return false; -#endif /* CONFIG_POLL */ -} - -void z_impl_k_pipe_flush(struct k_pipe *pipe) -{ - size_t bytes_read; - - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, flush, pipe); - - k_spinlock_key_t key = k_spin_lock(&pipe->lock); - - (void) pipe_get_internal(key, pipe, NULL, (size_t) -1, &bytes_read, 0U, - K_NO_WAIT); - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, flush, pipe); -} - -#ifdef CONFIG_USERSPACE -void z_vrfy_k_pipe_flush(struct k_pipe *pipe) -{ - K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE)); - - z_impl_k_pipe_flush(pipe); -} -#include -#endif /* CONFIG_USERSPACE */ - -void z_impl_k_pipe_buffer_flush(struct k_pipe *pipe) -{ - size_t bytes_read; - - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, buffer_flush, pipe); - - k_spinlock_key_t key = k_spin_lock(&pipe->lock); - - if (pipe->buffer != NULL) { - (void) pipe_get_internal(key, pipe, NULL, pipe->size, - &bytes_read, 0U, K_NO_WAIT); - } else { - k_spin_unlock(&pipe->lock, key); - } - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, buffer_flush, pipe); -} - -#ifdef CONFIG_USERSPACE -void z_vrfy_k_pipe_buffer_flush(struct k_pipe *pipe) -{ - K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE)); - - z_impl_k_pipe_buffer_flush(pipe); -} -#endif /* CONFIG_USERSPACE */ - -int k_pipe_cleanup(struct k_pipe *pipe) -{ - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, cleanup, pipe); - - k_spinlock_key_t key = k_spin_lock(&pipe->lock); - - CHECKIF((z_waitq_head(&pipe->wait_q.readers) != NULL) || - (z_waitq_head(&pipe->wait_q.writers) != NULL)) { - k_spin_unlock(&pipe->lock, key); - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, cleanup, pipe, -EAGAIN); - - return -EAGAIN; - } - - if ((pipe->flags & K_PIPE_FLAG_ALLOC) != 0U) { - k_free(pipe->buffer); - pipe->buffer = NULL; - - /* - * Freeing the buffer changes the pipe into a bufferless - * pipe. Reset the pipe's counters to prevent malfunction. - */ - - pipe->size = 0U; - pipe->bytes_used = 0U; - pipe->read_index = 0U; - pipe->write_index = 0U; - pipe->flags &= ~K_PIPE_FLAG_ALLOC; - } - - k_spin_unlock(&pipe->lock, key); - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, cleanup, pipe, 0U); - - return 0; -} - -/** - * @brief Copy bytes from @a src to @a dest - * - * @return Number of bytes copied - */ -static size_t pipe_xfer(unsigned char *dest, size_t dest_size, - const unsigned char *src, size_t src_size) -{ - size_t num_bytes = MIN(dest_size, src_size); - - if (dest == NULL) { - /* Data is being flushed. Pretend the data was copied. */ - return num_bytes; - } - - (void) memcpy(dest, src, num_bytes); - - return num_bytes; -} - -/** - * @brief Callback routine used to populate wait list - * - * @return 1 to stop further walking; 0 to continue walking - */ -static int pipe_walk_op(struct k_thread *thread, void *data) -{ - struct waitq_walk_data *walk_data = data; - struct _pipe_desc *desc = (struct _pipe_desc *)thread->base.swap_data; - - sys_dlist_append(walk_data->list, &desc->node); - - walk_data->bytes_available += desc->bytes_to_xfer; - - if (walk_data->bytes_available >= walk_data->bytes_requested) { - return 1; - } - - return 0; -} - -/** - * @brief Popluate pipe descriptors for copying to/from waiters' buffers - * - * This routine cycles through the waiters on the wait queue and creates - * a list of threads that will have data directly copied to / read from - * their buffers. This list helps us avoid double copying later. - * - * @return # of bytes available for direct copying - */ -static size_t pipe_waiter_list_populate(sys_dlist_t *list, - _wait_q_t *wait_q, - size_t bytes_to_xfer) -{ - struct waitq_walk_data walk_data; - - walk_data.list = list; - walk_data.bytes_requested = bytes_to_xfer; - walk_data.bytes_available = 0; - - (void) z_sched_waitq_walk(wait_q, pipe_walk_op, &walk_data); - - return walk_data.bytes_available; -} - -/** - * @brief Populate pipe descriptors for copying to/from pipe buffer - * - * This routine is only called if the pipe buffer is not empty (when reading), - * or if not full (when writing). - */ -static size_t pipe_buffer_list_populate(sys_dlist_t *list, - struct _pipe_desc *desc, - unsigned char *buffer, - size_t size, - size_t start, - size_t end) -{ - sys_dlist_append(list, &desc[0].node); - - desc[0].thread = NULL; - desc[0].buffer = &buffer[start]; - - if (start < end) { - desc[0].bytes_to_xfer = end - start; - return end - start; - } - - desc[0].bytes_to_xfer = size - start; - - desc[1].thread = NULL; - desc[1].buffer = &buffer[0]; - desc[1].bytes_to_xfer = end; - - sys_dlist_append(list, &desc[1].node); - - return size - start + end; -} - -/** - * @brief Determine the correct return code - * - * Bytes Xferred No Wait Wait - * >= Minimum 0 0 - * < Minimum -EIO* -EAGAIN - * - * * The "-EIO No Wait" case was already checked after the list of pipe - * descriptors was created. - * - * @return See table above - */ -static int pipe_return_code(size_t min_xfer, size_t bytes_remaining, - size_t bytes_requested) -{ - if ((bytes_requested - bytes_remaining) >= min_xfer) { - /* - * At least the minimum number of requested - * bytes have been transferred. - */ - return 0; - } - - return -EAGAIN; -} - -/** - * @brief Copy data from source(s) to destination(s) - */ - -static size_t pipe_write(struct k_pipe *pipe, sys_dlist_t *src_list, - sys_dlist_t *dest_list, bool *reschedule) -{ - struct _pipe_desc *src; - struct _pipe_desc *dest; - size_t bytes_copied; - size_t num_bytes_written = 0U; - - src = (struct _pipe_desc *)sys_dlist_get(src_list); - dest = (struct _pipe_desc *)sys_dlist_get(dest_list); - - while ((src != NULL) && (dest != NULL)) { - bytes_copied = pipe_xfer(dest->buffer, dest->bytes_to_xfer, - src->buffer, src->bytes_to_xfer); - - num_bytes_written += bytes_copied; - - dest->buffer += bytes_copied; - dest->bytes_to_xfer -= bytes_copied; - - src->buffer += bytes_copied; - src->bytes_to_xfer -= bytes_copied; - - if (dest->thread == NULL) { - - /* Writing to the pipe buffer. Update details. */ - - pipe->bytes_used += bytes_copied; - pipe->write_index += bytes_copied; - if (pipe->write_index >= pipe->size) { - pipe->write_index -= pipe->size; - } - } else if (dest->bytes_to_xfer == 0U) { - - /* The thread's read request has been satisfied. */ - - z_unpend_thread(dest->thread); - z_ready_thread(dest->thread); - - *reschedule = true; - } - - if (src->bytes_to_xfer == 0U) { - src = (struct _pipe_desc *)sys_dlist_get(src_list); - } - - if (dest->bytes_to_xfer == 0U) { - dest = (struct _pipe_desc *)sys_dlist_get(dest_list); - } - } - - return num_bytes_written; -} - -int z_impl_k_pipe_put(struct k_pipe *pipe, const void *data, - size_t bytes_to_write, size_t *bytes_written, - size_t min_xfer, k_timeout_t timeout) -{ - struct _pipe_desc pipe_desc[2]; - struct _pipe_desc isr_desc; - struct _pipe_desc *src_desc; - sys_dlist_t dest_list; - sys_dlist_t src_list; - size_t bytes_can_write; - bool reschedule_needed = false; - - __ASSERT(((arch_is_in_isr() == false) || - K_TIMEOUT_EQ(timeout, K_NO_WAIT)), ""); - - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, put, pipe, timeout); - - CHECKIF((min_xfer > bytes_to_write) || (bytes_written == NULL)) { - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, put, pipe, timeout, - -EINVAL); - - return -EINVAL; - } - - sys_dlist_init(&src_list); - sys_dlist_init(&dest_list); - - k_spinlock_key_t key = k_spin_lock(&pipe->lock); - - /* - * First, write to any waiting readers, if any exist. - * Second, write to the pipe buffer, if it exists. - */ - - bytes_can_write = pipe_waiter_list_populate(&dest_list, - &pipe->wait_q.readers, - bytes_to_write); - - if (pipe->bytes_used != pipe->size) { - bytes_can_write += pipe_buffer_list_populate(&dest_list, - pipe_desc, - pipe->buffer, - pipe->size, - pipe->write_index, - pipe->read_index); - } - - if ((bytes_can_write < min_xfer) && - (K_TIMEOUT_EQ(timeout, K_NO_WAIT))) { - - /* The request can not be fulfilled. */ - - k_spin_unlock(&pipe->lock, key); - *bytes_written = 0U; - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, put, pipe, - timeout, -EIO); - - return -EIO; - } - - /* - * Do not use the pipe descriptor stored within k_thread if - * invoked from within an ISR as that is not safe to do. - */ - - src_desc = k_is_in_isr() ? &isr_desc : &_current->pipe_desc; - - src_desc->buffer = (unsigned char *)data; - src_desc->bytes_to_xfer = bytes_to_write; - src_desc->thread = _current; - sys_dlist_append(&src_list, &src_desc->node); - - *bytes_written = pipe_write(pipe, &src_list, - &dest_list, &reschedule_needed); - - /* - * Only handle poll events if the pipe has had some bytes written and - * there are bytes remaining after any pending readers have read from it - */ - - if ((pipe->bytes_used != 0U) && (*bytes_written != 0U)) { - reschedule_needed = handle_poll_events(pipe) || reschedule_needed; - } - - /* - * The immediate success conditions below are backwards - * compatible with an earlier pipe implementation. - */ - - if ((*bytes_written == bytes_to_write) || - (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) || - ((*bytes_written >= min_xfer) && (min_xfer > 0U))) { - - /* The minimum amount of data has been copied */ - - if (reschedule_needed) { - z_reschedule(&pipe->lock, key); - } else { - k_spin_unlock(&pipe->lock, key); - } - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, put, pipe, timeout, 0); - - return 0; - } - - /* The minimum amount of data has not been copied. Block. */ - - SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_pipe, put, pipe, timeout); - - _current->base.swap_data = src_desc; - - z_sched_wait(&pipe->lock, key, &pipe->wait_q.writers, timeout, NULL); - - /* - * On SMP systems, threads in the processing list may timeout before - * the data has finished copying. The following spin lock/unlock pair - * prevents those threads from executing further until the data copying - * is complete. - */ - - key = k_spin_lock(&pipe->lock); - k_spin_unlock(&pipe->lock, key); - - *bytes_written = bytes_to_write - src_desc->bytes_to_xfer; - - int ret = pipe_return_code(min_xfer, src_desc->bytes_to_xfer, - bytes_to_write); - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, put, pipe, timeout, ret); - - return ret; -} - -#ifdef CONFIG_USERSPACE -int z_vrfy_k_pipe_put(struct k_pipe *pipe, const void *data, - size_t bytes_to_write, size_t *bytes_written, - size_t min_xfer, k_timeout_t timeout) -{ - K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE)); - K_OOPS(K_SYSCALL_MEMORY_WRITE(bytes_written, sizeof(*bytes_written))); - K_OOPS(K_SYSCALL_MEMORY_READ(data, bytes_to_write)); - - return z_impl_k_pipe_put(pipe, data, - bytes_to_write, bytes_written, min_xfer, - timeout); -} -#include -#endif /* CONFIG_USERSPACE */ - -static int pipe_get_internal(k_spinlock_key_t key, struct k_pipe *pipe, - void *data, size_t bytes_to_read, - size_t *bytes_read, size_t min_xfer, - k_timeout_t timeout) -{ - sys_dlist_t src_list; - struct _pipe_desc pipe_desc[2]; - struct _pipe_desc isr_desc; - struct _pipe_desc *dest_desc; - struct _pipe_desc *src_desc; - size_t num_bytes_read = 0U; - size_t bytes_copied; - size_t bytes_can_read = 0U; - bool reschedule_needed = false; - - /* - * Data copying takes place in the following order. - * 1. Copy data from the pipe buffer to the receive buffer. - * 2. Copy data from the waiting writer(s) to the receive buffer. - * 3. Refill the pipe buffer from the waiting writer(s). - */ - - sys_dlist_init(&src_list); - - if (pipe->bytes_used != 0) { - bytes_can_read = pipe_buffer_list_populate(&src_list, - pipe_desc, - pipe->buffer, - pipe->size, - pipe->read_index, - pipe->write_index); - } - - bytes_can_read += pipe_waiter_list_populate(&src_list, - &pipe->wait_q.writers, - bytes_to_read); - - if ((bytes_can_read < min_xfer) && - (K_TIMEOUT_EQ(timeout, K_NO_WAIT))) { - - /* The request can not be fulfilled. */ - - k_spin_unlock(&pipe->lock, key); - *bytes_read = 0; - - return -EIO; - } - - /* - * Do not use the pipe descriptor stored within k_thread if - * invoked from within an ISR as that is not safe to do. - */ - - dest_desc = k_is_in_isr() ? &isr_desc : &_current->pipe_desc; - - dest_desc->buffer = data; - dest_desc->bytes_to_xfer = bytes_to_read; - dest_desc->thread = _current; - - src_desc = (struct _pipe_desc *)sys_dlist_get(&src_list); - while (src_desc != NULL) { - bytes_copied = pipe_xfer(dest_desc->buffer, - dest_desc->bytes_to_xfer, - src_desc->buffer, - src_desc->bytes_to_xfer); - - num_bytes_read += bytes_copied; - - src_desc->buffer += bytes_copied; - src_desc->bytes_to_xfer -= bytes_copied; - - if (dest_desc->buffer != NULL) { - dest_desc->buffer += bytes_copied; - } - dest_desc->bytes_to_xfer -= bytes_copied; - - if (src_desc->thread == NULL) { - - /* Reading from the pipe buffer. Update details. */ - - pipe->bytes_used -= bytes_copied; - pipe->read_index += bytes_copied; - if (pipe->read_index >= pipe->size) { - pipe->read_index -= pipe->size; - } - } else if (src_desc->bytes_to_xfer == 0U) { - - /* The thread's write request has been satisfied. */ - - z_unpend_thread(src_desc->thread); - z_ready_thread(src_desc->thread); - - reschedule_needed = true; - } - src_desc = (struct _pipe_desc *)sys_dlist_get(&src_list); - } - - if (pipe->bytes_used != pipe->size) { - sys_dlist_t pipe_list; - - /* - * The pipe is not full. If there are any waiting writers, - * refill the pipe. - */ - - sys_dlist_init(&src_list); - sys_dlist_init(&pipe_list); - - (void) pipe_waiter_list_populate(&src_list, - &pipe->wait_q.writers, - pipe->size - pipe->bytes_used); - - (void) pipe_buffer_list_populate(&pipe_list, pipe_desc, - pipe->buffer, pipe->size, - pipe->write_index, - pipe->read_index); - - (void) pipe_write(pipe, &src_list, - &pipe_list, &reschedule_needed); - } - - /* - * The immediate success conditions below are backwards - * compatible with an earlier pipe implementation. - */ - - if ((num_bytes_read == bytes_to_read) || - (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) || - ((num_bytes_read >= min_xfer) && (min_xfer > 0U))) { - - /* The minimum amount of data has been copied */ - - *bytes_read = num_bytes_read; - if (reschedule_needed) { - z_reschedule(&pipe->lock, key); - } else { - k_spin_unlock(&pipe->lock, key); - } - - return 0; - } - - /* The minimum amount of data has not been copied. Block. */ - - SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_pipe, get, pipe, timeout); - - _current->base.swap_data = dest_desc; - - z_sched_wait(&pipe->lock, key, &pipe->wait_q.readers, timeout, NULL); - - /* - * On SMP systems, threads in the processing list may timeout before - * the data has finished copying. The following spin lock/unlock pair - * prevents those threads from executing further until the data copying - * is complete. - */ - - key = k_spin_lock(&pipe->lock); - k_spin_unlock(&pipe->lock, key); - - *bytes_read = bytes_to_read - dest_desc->bytes_to_xfer; - - int ret = pipe_return_code(min_xfer, dest_desc->bytes_to_xfer, - bytes_to_read); - - return ret; -} - -int z_impl_k_pipe_get(struct k_pipe *pipe, void *data, size_t bytes_to_read, - size_t *bytes_read, size_t min_xfer, k_timeout_t timeout) -{ - __ASSERT(((arch_is_in_isr() == false) || - K_TIMEOUT_EQ(timeout, K_NO_WAIT)), ""); - - SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, get, pipe, timeout); - - CHECKIF((min_xfer > bytes_to_read) || (bytes_read == NULL)) { - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, get, pipe, - timeout, -EINVAL); - - return -EINVAL; - } - - k_spinlock_key_t key = k_spin_lock(&pipe->lock); - - int ret = pipe_get_internal(key, pipe, data, bytes_to_read, bytes_read, - min_xfer, timeout); - - SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, get, pipe, timeout, ret); - - return ret; -} - -#ifdef CONFIG_USERSPACE -int z_vrfy_k_pipe_get(struct k_pipe *pipe, void *data, size_t bytes_to_read, - size_t *bytes_read, size_t min_xfer, k_timeout_t timeout) -{ - K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE)); - K_OOPS(K_SYSCALL_MEMORY_WRITE(bytes_read, sizeof(*bytes_read))); - K_OOPS(K_SYSCALL_MEMORY_WRITE(data, bytes_to_read)); - - return z_impl_k_pipe_get(pipe, data, - bytes_to_read, bytes_read, min_xfer, - timeout); -} -#include -#endif /* CONFIG_USERSPACE */ - -size_t z_impl_k_pipe_read_avail(struct k_pipe *pipe) -{ - size_t res; - k_spinlock_key_t key; - - /* Buffer and size are fixed. No need to spin. */ - if ((pipe->buffer == NULL) || (pipe->size == 0U)) { - res = 0; - goto out; - } - - key = k_spin_lock(&pipe->lock); - - if (pipe->read_index == pipe->write_index) { - res = pipe->bytes_used; - } else if (pipe->read_index < pipe->write_index) { - res = pipe->write_index - pipe->read_index; - } else { - res = pipe->size - (pipe->read_index - pipe->write_index); - } - - k_spin_unlock(&pipe->lock, key); - -out: - return res; -} - -#ifdef CONFIG_USERSPACE -size_t z_vrfy_k_pipe_read_avail(struct k_pipe *pipe) -{ - K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE)); - - return z_impl_k_pipe_read_avail(pipe); -} -#include -#endif /* CONFIG_USERSPACE */ - -size_t z_impl_k_pipe_write_avail(struct k_pipe *pipe) -{ - size_t res; - k_spinlock_key_t key; - - /* Buffer and size are fixed. No need to spin. */ - if ((pipe->buffer == NULL) || (pipe->size == 0U)) { - res = 0; - goto out; - } - - key = k_spin_lock(&pipe->lock); - - if (pipe->write_index == pipe->read_index) { - res = pipe->size - pipe->bytes_used; - } else if (pipe->write_index < pipe->read_index) { - res = pipe->read_index - pipe->write_index; - } else { - res = pipe->size - (pipe->write_index - pipe->read_index); - } - - k_spin_unlock(&pipe->lock, key); - -out: - return res; -} - -#ifdef CONFIG_USERSPACE -size_t z_vrfy_k_pipe_write_avail(struct k_pipe *pipe) -{ - K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE)); - - return z_impl_k_pipe_write_avail(pipe); -} -#include -#endif /* CONFIG_USERSPACE */ - -#ifdef CONFIG_OBJ_CORE_PIPE -static int init_pipe_obj_core_list(void) -{ - /* Initialize pipe object type */ - - z_obj_type_init(&obj_type_pipe, K_OBJ_TYPE_PIPE_ID, - offsetof(struct k_pipe, obj_core)); - - /* Initialize and link statically defined pipes */ - - STRUCT_SECTION_FOREACH(k_pipe, pipe) { - k_obj_core_init_and_link(K_OBJ_CORE(pipe), &obj_type_pipe); - } - - return 0; -} - -SYS_INIT(init_pipe_obj_core_list, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); -#endif /* CONFIG_OBJ_CORE_PIPE */ diff --git a/kernel/poll.c b/kernel/poll.c index b6e20b24c3a23..da956a268cc81 100644 --- a/kernel/poll.c +++ b/kernel/poll.c @@ -88,11 +88,7 @@ static inline bool is_condition_met(struct k_poll_event *event, uint32_t *state) } break; case K_POLL_TYPE_PIPE_DATA_AVAILABLE: -#ifdef CONFIG_PIPES - if (event->pipe->bytes_used != 0) { -#else if (!ring_buf_is_empty(&event->pipe->buf)) { -#endif *state = K_POLL_STATE_PIPE_DATA_AVAILABLE; return true; } diff --git a/kernel/thread.c b/kernel/thread.c index f77d70ce494fb..bfcd9c87772fb 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -501,6 +501,70 @@ static char *setup_thread_stack(struct k_thread *new_thread, return stack_ptr; } +#ifdef CONFIG_HW_SHADOW_STACK +static void setup_shadow_stack(struct k_thread *new_thread, + k_thread_stack_t *stack) +{ + int ret = -ENOENT; + + STRUCT_SECTION_FOREACH(_stack_to_hw_shadow_stack, stk_to_hw_shstk) { + if (stk_to_hw_shstk->stack == stack) { + ret = k_thread_hw_shadow_stack_attach(new_thread, + stk_to_hw_shstk->shstk_addr, + stk_to_hw_shstk->size); + if (ret != 0) { + LOG_ERR("Could not set thread %p shadow stack %p, got error %d", + new_thread, stk_to_hw_shstk->shstk_addr, ret); + k_panic(); + } + break; + } + } + + /* Check if the stack isn't in a stack array, and use the corresponding + * shadow stack. + */ + if (ret != -ENOENT) { + return; + } + + STRUCT_SECTION_FOREACH(_stack_to_hw_shadow_stack_arr, stk_to_hw_shstk) { + if ((uintptr_t)stack >= stk_to_hw_shstk->stack_addr && + (uintptr_t)stack < stk_to_hw_shstk->stack_addr + + stk_to_hw_shstk->stack_size * stk_to_hw_shstk->nmemb) { + /* Now we have to guess which index of the stack array is being used */ + uintptr_t stack_offset = (uintptr_t)stack - stk_to_hw_shstk->stack_addr; + uintptr_t stack_index = stack_offset / stk_to_hw_shstk->stack_size; + uintptr_t addr; + + if (stack_index >= stk_to_hw_shstk->nmemb) { + LOG_ERR("Could not find shadow stack for thread %p, stack %p", + new_thread, stack); + k_panic(); + } + + addr = stk_to_hw_shstk->shstk_addr + + stk_to_hw_shstk->shstk_size * stack_index; + ret = k_thread_hw_shadow_stack_attach(new_thread, + (arch_thread_hw_shadow_stack_t *)addr, + stk_to_hw_shstk->shstk_size); + if (ret != 0) { + LOG_ERR("Could not set thread %p shadow stack 0x%lx, got error %d", + new_thread, stk_to_hw_shstk->shstk_addr, ret); + k_panic(); + } + break; + } + } + + if (ret == -ENOENT) { + LOG_ERR("Could not find shadow stack for thread %p, stack %p", + new_thread, stack); + k_panic(); + } +} +#endif + /* * The provided stack_size value is presumed to be either the result of * K_THREAD_STACK_SIZEOF(stack), or the size value passed to the instance @@ -547,6 +611,10 @@ char *z_setup_new_thread(struct k_thread *new_thread, z_init_thread_base(&new_thread->base, prio, _THREAD_SLEEPING, options); stack_ptr = setup_thread_stack(new_thread, stack, stack_size); +#ifdef CONFIG_HW_SHADOW_STACK + setup_shadow_stack(new_thread, stack); +#endif + #ifdef CONFIG_KERNEL_COHERENCE /* Check that the thread object is safe, but that the stack is * still cached! diff --git a/kernel/userspace.c b/kernel/userspace.c index 7a2ea5c45fd80..61e00afcbc4c7 100644 --- a/kernel/userspace.c +++ b/kernel/userspace.c @@ -591,11 +591,6 @@ static void unref_check(struct k_object *ko, uintptr_t index) * specifically needs to happen depends on the object type. */ switch (ko->type) { -#ifdef CONFIG_PIPES - case K_OBJ_PIPE: - k_pipe_cleanup((struct k_pipe *)ko->name); - break; -#endif /* CONFIG_PIPES */ case K_OBJ_MSGQ: k_msgq_cleanup((struct k_msgq *)ko->name); break; diff --git a/lib/CMakeLists.txt b/lib/CMakeLists.txt index 49acdf7ed8ae0..b9c1d9cebddf3 100644 --- a/lib/CMakeLists.txt +++ b/lib/CMakeLists.txt @@ -3,7 +3,6 @@ # FIXME: SHADOW_VARS: Remove this once we have enabled -Wshadow globally. add_compile_options($) -add_subdirectory(crc) add_subdirectory(libc) if(NOT CONFIG_NATIVE_LIBC) add_subdirectory(posix) diff --git a/lib/Kconfig b/lib/Kconfig index 626bec379dde8..ada7fe79ff92b 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -7,8 +7,6 @@ source "lib/libc/Kconfig" source "lib/cpp/Kconfig" -source "lib/crc/Kconfig" - menu "Additional libraries" source "lib/hash/Kconfig" diff --git a/lib/crc/CMakeLists.txt b/lib/crc/CMakeLists.txt deleted file mode 100644 index 6a6b35ea18ad1..0000000000000 --- a/lib/crc/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_CRC - crc32k_4_2_sw.c - crc32c_sw.c - crc32_sw.c - crc24_sw.c - crc16_sw.c - crc8_sw.c - crc7_sw.c - crc4_sw.c - ) -zephyr_sources_ifdef(CONFIG_CRC_SHELL crc_shell.c) diff --git a/lib/crc/Kconfig b/lib/crc/Kconfig deleted file mode 100644 index eb2ced63db26e..0000000000000 --- a/lib/crc/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2016,2023 Intel Corporation -# Copyright (c) 2024 Intercreate, Inc. -# SPDX-License-Identifier: Apache-2.0 -# -config CRC - bool "Cyclic redundancy check (CRC) Support" - help - Enable use of CRC. - -if CRC -config CRC_SHELL - bool "CRC Shell" - depends on SHELL - select POSIX_C_LIB_EXT - help - Enable CRC checking for memory regions from the shell. - -config CRC32_K_4_2_TABLE_256 - bool "Use 256-length table for CRC32-K/4.2" - help - Enable the 256-length instead of 16-length table for CRC32-K/4.2. - -endif # CRC diff --git a/lib/heap/heap.h b/lib/heap/heap.h index 8a3b893a658a6..d053a6db88392 100644 --- a/lib/heap/heap.h +++ b/lib/heap/heap.h @@ -74,7 +74,7 @@ struct z_heap { size_t allocated_bytes; size_t max_allocated_bytes; #endif - struct z_heap_bucket buckets[0]; + struct z_heap_bucket buckets[]; }; static inline bool big_heap_chunks(chunksz_t chunks) diff --git a/lib/libc/arcmwdt/include/limits.h b/lib/libc/arcmwdt/include/limits.h index 822e66f24d283..2e9a4d3fb4c68 100644 --- a/lib/libc/arcmwdt/include/limits.h +++ b/lib/libc/arcmwdt/include/limits.h @@ -8,15 +8,10 @@ #define LIB_LIBC_ARCMWDT_INCLUDE_LIMITS_H_ #include_next +#include -#ifdef __cplusplus -extern "C" { -#endif - +#ifndef PATH_MAX #define PATH_MAX 256 - -#ifdef __cplusplus -} #endif -#endif /* LIB_LIBC_ARCMWDT_INCLUDE_LIMITS_H_ */ +#endif /* LIB_LIBC_ARCMWDT_INCLUDE_LIMITS_H_ */ diff --git a/lib/libc/armstdc/include/limits.h b/lib/libc/armstdc/include/limits.h index 37aad4cf9bb8b..54dabd8fdaa4a 100644 --- a/lib/libc/armstdc/include/limits.h +++ b/lib/libc/armstdc/include/limits.h @@ -8,15 +8,10 @@ #define ZEPHYR_LIB_LIBC_ARMSTDC_INCLUDE_LIMITS_H_ #include_next +#include -#ifdef __cplusplus -extern "C" { -#endif - +#ifndef PATH_MAX #define PATH_MAX 256 - -#ifdef __cplusplus -} #endif #endif /* ZEPHYR_LIB_LIBC_ARMSTDC_INCLUDE_LIMITS_H_ */ diff --git a/lib/libc/iar/include/limits.h b/lib/libc/iar/include/limits.h index 50decad13ad18..010f0509649e7 100644 --- a/lib/libc/iar/include/limits.h +++ b/lib/libc/iar/include/limits.h @@ -8,15 +8,10 @@ #define ZEPHYR_LIB_LIBC_IAR_INCLUDE_LIMITS_H_ #include_next +#include -#ifdef __cplusplus -extern "C" { -#endif - +#ifndef PATH_MAX #define PATH_MAX 256 - -#ifdef __cplusplus -} #endif #endif /* ZEPHYR_LIB_LIBC_IAR_INCLUDE_LIMITS_H_ */ diff --git a/lib/libc/minimal/include/limits.h b/lib/libc/minimal/include/limits.h index 7b9a986465683..3a25ed16b1f83 100644 --- a/lib/libc/minimal/include/limits.h +++ b/lib/libc/minimal/include/limits.h @@ -80,8 +80,16 @@ extern "C" { #error "unexpected __SIZEOF_LONG_LONG__ value" #endif +#if defined(_POSIX_C_SOURCE) || defined(__DOXYGEN__) + +#include + +#else + #define PATH_MAX 256 +#endif + #ifdef __cplusplus } #endif diff --git a/lib/libc/minimal/include/stdbool.h b/lib/libc/minimal/include/stdbool.h index 0bfccdcd713e9..2c672600aee69 100644 --- a/lib/libc/minimal/include/stdbool.h +++ b/lib/libc/minimal/include/stdbool.h @@ -9,7 +9,7 @@ #ifndef ZEPHYR_LIB_LIBC_MINIMAL_INCLUDE_STDBOOL_H_ #define ZEPHYR_LIB_LIBC_MINIMAL_INCLUDE_STDBOOL_H_ -#ifndef __cplusplus +#if !defined(__cplusplus) && __STDC_VERSION__ < 202311L #define bool _Bool #define true 1 #define false 0 diff --git a/lib/libc/newlib/include/limits.h b/lib/libc/newlib/include/limits.h new file mode 100644 index 0000000000000..81f9bbd406611 --- /dev/null +++ b/lib/libc/newlib/include/limits.h @@ -0,0 +1,13 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_LIB_LIBC_NEWLIB_INCLUDE_LIMITS_H_ +#define ZEPHYR_LIB_LIBC_NEWLIB_INCLUDE_LIMITS_H_ + +#include_next +#include + +#endif /* ZEPHYR_LIB_LIBC_NEWLIB_INCLUDE_LIMITS_H_ */ diff --git a/lib/os/assert.c b/lib/os/assert.c index 1fee487bff64e..4f37f62d031b7 100644 --- a/lib/os/assert.c +++ b/lib/os/assert.c @@ -44,7 +44,17 @@ __weak void assert_post_action(const char *file, unsigned int line) } EXPORT_SYMBOL(assert_post_action); -void assert_print(const char *fmt, ...) +/** + * @brief Assert Print Handler + * + * This routine implements printing the assertion message. + * + * System designers may wish to substitute this implementation to store the + * assertion, or otherwise change the behavior of the assertion print + * + * @param N/A + */ +__weak void assert_print(const char *fmt, ...) { va_list ap; diff --git a/lib/os/clock.c b/lib/os/clock.c index ad7e00a0ff02c..0d5813f49fef9 100644 --- a/lib/os/clock.c +++ b/lib/os/clock.c @@ -192,7 +192,7 @@ int z_impl_sys_clock_nanosleep(int clock_id, int flags, const struct timespec *r (void)timespec_add(&duration, &rem); } - timeout = timespec_to_timeout(&duration); + timeout = timespec_to_timeout(&duration, NULL); end = sys_timepoint_calc(timeout); do { (void)k_sleep(timeout); diff --git a/lib/posix/options/fs.c b/lib/posix/options/fs.c index 45028248608f7..23d4cf669f6b8 100644 --- a/lib/posix/options/fs.c +++ b/lib/posix/options/fs.c @@ -154,6 +154,35 @@ static int fs_ioctl_vmeth(void *obj, unsigned int request, va_list args) struct posix_fs_desc *ptr = obj; switch (request) { + case ZFD_IOCTL_STAT: { + struct stat *buf = va_arg(args, struct stat *); + long offset = fs_tell(&ptr->file); + long current; + + if (offset < 0) { + return offset; + } + + memset(buf, 0, sizeof(struct stat)); + + rc = fs_seek(&ptr->file, 0, FS_SEEK_END); + if (rc < 0) { + return rc; + } + + current = fs_tell(&ptr->file); + if (current >= 0) { + buf->st_size = current; + buf->st_mode = ptr->is_dir ? S_IFDIR : S_IFREG; + } + + rc = fs_seek(&ptr->file, offset, FS_SEEK_SET); + + if (current < 0) { + rc = current; + } + break; + } case ZFD_IOCTL_FSYNC: { rc = fs_sync(&ptr->file); break; diff --git a/lib/posix/options/grp.c b/lib/posix/options/grp.c index 32c840e10164f..af395c88fa00c 100644 --- a/lib/posix/options/grp.c +++ b/lib/posix/options/grp.c @@ -9,8 +9,6 @@ #include #include -#ifdef CONFIG_POSIX_THREAD_SAFE_FUNCTIONS - int getgrnam_r(const char *name, struct group *grp, char *buffer, size_t bufsize, struct group **result) { @@ -33,5 +31,3 @@ int getgrgid_r(gid_t gid, struct group *grp, char *buffer, size_t bufsize, struc return ENOSYS; } - -#endif /* CONFIG_POSIX_THREAD_SAFE_FUNCTIONS */ diff --git a/lib/posix/options/pwd.c b/lib/posix/options/pwd.c index f806767f3df90..5cafbb0a3a94a 100644 --- a/lib/posix/options/pwd.c +++ b/lib/posix/options/pwd.c @@ -9,8 +9,6 @@ #include #include -#ifdef CONFIG_POSIX_THREAD_SAFE_FUNCTIONS - int getpwnam_r(const char *nam, struct passwd *pwd, char *buffer, size_t bufsize, struct passwd **result) { @@ -33,5 +31,3 @@ int getpwuid_r(uid_t uid, struct passwd *pwd, char *buffer, size_t bufsize, stru return ENOSYS; } - -#endif /* CONFIG_POSIX_THREAD_SAFE_FUNCTIONS */ diff --git a/lib/utils/CMakeLists.txt b/lib/utils/CMakeLists.txt index aca2e69776d4a..f6ab864d4640e 100644 --- a/lib/utils/CMakeLists.txt +++ b/lib/utils/CMakeLists.txt @@ -8,6 +8,7 @@ zephyr_sources( rb.c timeutil.c bitarray.c + bitmask.c ) zephyr_sources_ifdef(CONFIG_ONOFF onoff.c) diff --git a/lib/utils/bitarray.c b/lib/utils/bitarray.c index 07f22e0c94bad..e359ce230f3df 100644 --- a/lib/utils/bitarray.c +++ b/lib/utils/bitarray.c @@ -513,6 +513,20 @@ int sys_bitarray_alloc(sys_bitarray_t *bitarray, size_t num_bits, goto out; } + if (bitarray->num_bits <= 32) { + int off; + + off = bitmask_find_gap(bitarray->bundles[0], num_bits, bitarray->num_bits, false); + if (off < 0) { + ret = -ENOSPC; + } else { + bitarray->bundles[0] |= BIT_MASK(num_bits) << off; + *offset = off; + ret = 0; + } + goto out; + } + bit_idx = 0; /* Find the first non-allocated bit by looking at bundles @@ -660,7 +674,16 @@ int sys_bitarray_free(sys_bitarray_t *bitarray, size_t num_bits, * (offset to offset + num_bits) are all allocated before we clear * them. */ - if (match_region(bitarray, offset, num_bits, true, &bd, NULL)) { + if (bitarray->num_bits <= 32) { + uint32_t mask = BIT_MASK(num_bits) << offset; + + if ((mask & bitarray->bundles[0]) != mask) { + ret = -EFAULT; + } else { + bitarray->bundles[0] &= ~mask; + ret = 0; + } + } else if (match_region(bitarray, offset, num_bits, true, &bd, NULL)) { set_region(bitarray, offset, num_bits, false, &bd); ret = 0; } else { diff --git a/lib/utils/bitmask.c b/lib/utils/bitmask.c new file mode 100644 index 0000000000000..f62671b8908c2 --- /dev/null +++ b/lib/utils/bitmask.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +int bitmask_find_gap(uint32_t mask, size_t num_bits, size_t total_bits, bool first_match) +{ + uint32_t max = UINT32_MAX; + int max_loc = -1; + + if (total_bits < 32) { + mask |= ~BIT_MASK(total_bits); + } + + mask = ~mask; + while (mask != 0U) { + uint32_t block_size; + uint32_t loc; + int nidx; + uint32_t idx = 31 - u32_count_leading_zeros(mask); + uint32_t rmask = ~BIT_MASK(idx); + + rmask |= mask; + rmask = ~rmask; + if (rmask != 0U) { + nidx = 31 - u32_count_leading_zeros(rmask); + block_size = idx - nidx; + loc = nidx + 1; + mask &= BIT_MASK(nidx); + } else { + mask = 0; + block_size = idx + 1; + loc = 0; + } + + if ((block_size == num_bits) || (first_match && block_size > num_bits)) { + max_loc = loc; + max = block_size; + break; + } else if (block_size >= num_bits && block_size < max) { + max_loc = loc; + max = block_size; + } + } + + return max_loc; +} diff --git a/lib/utils/utf8.c b/lib/utils/utf8.c index f44ca27c0da92..cbe0eae7100c4 100644 --- a/lib/utils/utf8.c +++ b/lib/utils/utf8.c @@ -7,12 +7,15 @@ #include #include #include +#include +#include #define ASCII_CHAR 0x7F #define SEQUENCE_FIRST_MASK 0xC0 #define SEQUENCE_LEN_2_BYTE 0xC0 #define SEQUENCE_LEN_3_BYTE 0xE0 #define SEQUENCE_LEN_4_BYTE 0xF0 +#define MSB_SET 0x80 char *utf8_trunc(char *utf8_str) { @@ -79,3 +82,45 @@ char *utf8_lcpy(char *dst, const char *src, size_t n) return dst; } + +int utf8_count_chars(const char *s) +{ + int count = 0; + const char *p = s; /* getting a pointer to increment */ + + while (*p != '\0') { + if ((*p & MSB_SET) == 0) { /* 1-byte character: 0xxxxxxx */ + p += 1; + } else if ((*p & SEQUENCE_LEN_3_BYTE) == SEQUENCE_FIRST_MASK) { + /* 2-byte character: 110xxxxx */ + if ((p[1] & SEQUENCE_FIRST_MASK) != MSB_SET) { + /* invalid continuation */ + return -EINVAL; + } + p += 2; + } else if ((*p & SEQUENCE_LEN_4_BYTE) == SEQUENCE_LEN_3_BYTE) { + /* 3-byte character: 1110xxxx */ + if ((p[1] & SEQUENCE_FIRST_MASK) != MSB_SET + || (p[2] & SEQUENCE_FIRST_MASK) != MSB_SET) { + /* invalid continuation */ + return -EINVAL; + } + p += 3; + } else if ((*p & 0xF8) == SEQUENCE_LEN_4_BYTE) { + /* 4-byte character: 11110xxx */ + if ((p[1] & SEQUENCE_FIRST_MASK) != MSB_SET + || (p[2] & SEQUENCE_FIRST_MASK) != MSB_SET + || (p[3] & SEQUENCE_FIRST_MASK) != MSB_SET) { + /* invalid continuation */ + return -EINVAL; + } + p += 4; + } else { + /* Invalid UTF-8 byte (return) */ + return -EINVAL; + } + count++; + } + + return count; +} diff --git a/modules/Kconfig b/modules/Kconfig index acc77f8dce7b4..b66955981fa04 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -101,6 +101,9 @@ comment "Lz4 module not available." comment "loramac-node module not available." depends on !ZEPHYR_LORAMAC_NODE_MODULE +comment "LoRa Basics Modem module not available." + depends on !ZEPHYR_LORA_BASICS_MODEM_MODULE + comment "CANopenNode module not available." depends on !ZEPHYR_CANOPENNODE_MODULE diff --git a/modules/Kconfig.mcuboot b/modules/Kconfig.mcuboot index 34d9f75798528..7bf1536616ccf 100644 --- a/modules/Kconfig.mcuboot +++ b/modules/Kconfig.mcuboot @@ -60,7 +60,9 @@ config MCUBOOT_SIGNATURE_KEY_FILE config option can be a relative path from the MCUboot repository root.) - If left empty, you must sign the Zephyr binaries manually. + If left empty and MCUBOOT_GENERATE_UNSIGNED_IMAGE is not set, you + must sign and prepare the Zephyr binaries manually to be bootable + from MCUboot. config MCUBOOT_ENCRYPTION_KEY_FILE string "Path to the mcuboot encryption key file" @@ -120,6 +122,40 @@ config MCUBOOT_IMGTOOL_OVERWRITE_ONLY If enabled, --overwrite-only option passed to imgtool to avoid adding the swap status area size when calculating overflow. +config MCUBOOT_IMGTOOL_UUID_VID + bool "Append vendor unique identifier TLV" + help + If enabled, --vid option passed to imgtool with the value set by + the MCUBOOT_IMGTOOL_UUID_VID_NAME option. + +config MCUBOOT_IMGTOOL_UUID_VID_NAME + string "Vendor UUID" + depends on MCUBOOT_IMGTOOL_UUID_VID + help + The vendor unique identifier. + The following formats are supported: + - Domain name (i.e. amce.corp) + - Raw UUID (i.e. 12345678-1234-5678-1234-567812345678) + - Raw HEX UUID (i.e. 12345678123456781234567812345678) + +config MCUBOOT_IMGTOOL_UUID_CID + bool "Append image class unique identifier TLV" + help + If enabled, --cid option passed to imgtool with the value set by + the MCUBOOT_IMGTOOL_UUID_CID_NAME option. + +config MCUBOOT_IMGTOOL_UUID_CID_NAME + string "Image class UUID" + depends on MCUBOOT_IMGTOOL_UUID_CID + help + The image class unique identifier. + The following formats are supported: + - Image class name (i.e. nRF5340_door_lock_btperipheral). + This format requires MCUBOOT_IMGTOOL_UUID_VID_NAME to be defined + as the VID UUID is used as the namespace for image class UUID. + - Raw UUID (i.e. 12345678-1234-5678-1234-567812345678) + - Raw HEX UUID (i.e. 12345678123456781234567812345678) + config MCUBOOT_EXTRA_IMGTOOL_ARGS string "Extra arguments to pass to imgtool when signing" default "" @@ -133,7 +169,9 @@ config MCUBOOT_GENERATE_UNSIGNED_IMAGE help Enabling this configuration allows automatic unsigned binary image generation when MCUboot signing key is not provided, - i.e., MCUBOOT_SIGNATURE_KEY_FILE is left empty. + i.e., MCUBOOT_SIGNATURE_KEY_FILE is left empty. A hash of the + image will be generated and included in the unsigned image, instead + of a signature. config MCUBOOT_GENERATE_CONFIRMED_IMAGE bool "Also generate a padded, confirmed image" @@ -151,7 +189,7 @@ menu "On board MCUboot operation mode" choice MCUBOOT_BOOTLOADER_MODE prompt "Application assumed MCUboot mode of operation" # Should be removed if board dts is updated - default MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE if SOC_FAMILY_STM32 + default MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE if SOC_FAMILY_STM32 || SOC_FAMILY_ESPRESSIF_ESP32 default MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET help Informs application build on assumed MCUboot mode of operation. @@ -238,7 +276,7 @@ config MCUBOOT_BOOTLOADER_MODE_RAM_LOAD_WITH_REVERT will select the image with the higher version number, copy it to RAM and begin execution from there. The image must be linked to execute from RAM, the address that it is copied to is specified using the load-addr argument when running imgtool. - This option automatically selectes MCUBOOT_BOOTLOADER_NO_DOWNGRADE as + This option automatically selects MCUBOOT_BOOTLOADER_NO_DOWNGRADE as MCUBoot will automatically select the highest revision of the application to boot. Note however that MCUBoot will select an older revision of the application if the booted revision does not mark itself as confirmed. diff --git a/modules/Kconfig.mspm0 b/modules/Kconfig.mspm0 index 7125ff4919672..8781c02ecb9d3 100644 --- a/modules/Kconfig.mspm0 +++ b/modules/Kconfig.mspm0 @@ -9,6 +9,9 @@ config HAS_MSPM0_SDK config USE_MSPM0_DL_GPIO bool +config USE_MSPM0_DL_AES + bool + config USE_MSPM0_DL_UART bool diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 11fea132c319d..d4ac8f3087784 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -159,6 +159,11 @@ config USE_RA_FSP_SDHI help Enable RA FSP SDHI driver +config USE_RA_FSP_CRC + bool + help + Enable RA FSP CRC driver + config USE_RA_FSP_DAC bool help @@ -218,6 +223,11 @@ config USE_RA_FSP_TOUCH help Enable RA FSP TOUCH library +config USE_RA_FSP_QSPI_NOR_FLASH + bool + help + Enable RA FSP Quad-SPI driver + endif # HAS_RENESAS_RA_FSP if HAS_RENESAS_RZ_FSP @@ -237,6 +247,11 @@ config USE_RZ_FSP_SCIF_UART help Enable RZ FSP SCIF UART driver +config USE_RZ_FSP_IIC_MASTER + bool + help + Enable RZ FSP IIC MASTER driver + config USE_RZ_FSP_RIIC_MASTER bool help diff --git a/modules/cmsis_6/cmsis_core_m_defaults.h b/modules/cmsis_6/cmsis_core_m_defaults.h index b210d5c0d6851..919b078fc3cc0 100644 --- a/modules/cmsis_6/cmsis_core_m_defaults.h +++ b/modules/cmsis_6/cmsis_core_m_defaults.h @@ -147,4 +147,10 @@ typedef enum { #error "Unknown Cortex-M device" #endif +#ifdef CONFIG_ARM_PAC +/* This provides apis to set/get PAC keys */ +#define __ARM_FEATURE_PAUTH 1 +#include +#endif + #endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_ */ diff --git a/modules/hal_ethos_u/Kconfig b/modules/hal_ethos_u/Kconfig index d54f77f531b21..e1a4d97b656f3 100644 --- a/modules/hal_ethos_u/Kconfig +++ b/modules/hal_ethos_u/Kconfig @@ -61,7 +61,7 @@ config ETHOS_U_NPU_NAME choice "ETHOS_U_LOG_LEVEL_CHOICE" prompt "Max compiled-in log level for ETHOS_U" default ETHOS_U_LOG_LEVEL_WRN - depends on STDOUT_CONSOLE + depends on LOG config ETHOS_U_LOG_LEVEL_NONE bool "None" @@ -85,7 +85,9 @@ endchoice config ETHOS_U_LOG_LEVEL int - depends on STDOUT_CONSOLE + # Always define the symbol so C compiles cleanly even if LOG/console is off. + # When LOG is off, fall back to NONE (0). + default 0 if !LOG default 0 if ETHOS_U_LOG_LEVEL_NONE default 1 if ETHOS_U_LOG_LEVEL_ERR default 2 if ETHOS_U_LOG_LEVEL_WRN diff --git a/modules/hal_nxp/mcux/Kconfig.mcux b/modules/hal_nxp/mcux/Kconfig.mcux index 39e84efe6ad88..85dcbab084359 100644 --- a/modules/hal_nxp/mcux/Kconfig.mcux +++ b/modules/hal_nxp/mcux/Kconfig.mcux @@ -52,12 +52,6 @@ config HAS_MCUX_RCM Set if the Reset Control Module (RCM) module is present in the SoC. -config HAS_MCUX_MCX_CMC - bool - help - Set if the Core Mode Controller (CMC) module is present in - the SoC. - config HAS_MCUX_XCACHE bool help diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake index 658bebf1bbae8..5d9adce7125fa 100644 --- a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake +++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake @@ -51,6 +51,7 @@ set_variable_ifdef(CONFIG_ADC_MCUX_ADC16 CONFIG_MCUX_COMPONENT_driver.adc set_variable_ifdef(CONFIG_CAN_MCUX_FLEXCAN CONFIG_MCUX_COMPONENT_driver.flexcan) set_variable_ifdef(CONFIG_CAN_MCUX_FLEXCAN_FD CONFIG_MCUX_COMPONENT_driver.flexcan) set_variable_ifdef(CONFIG_COUNTER_NXP_PIT CONFIG_MCUX_COMPONENT_driver.pit) +set_variable_ifdef(CONFIG_COUNTER_MCUX_FTM CONFIG_MCUX_COMPONENT_driver.ftm) set_variable_ifdef(CONFIG_COUNTER_MCUX_RTC CONFIG_MCUX_COMPONENT_driver.rtc) set_variable_ifdef(CONFIG_DAC_MCUX_DAC CONFIG_MCUX_COMPONENT_driver.dac) set_variable_ifdef(CONFIG_DAC_MCUX_DAC12 CONFIG_MCUX_COMPONENT_driver.dac12) @@ -135,6 +136,7 @@ set_variable_ifdef(CONFIG_TRDC_MCUX_TRDC_1 CONFIG_MCUX_COMPONENT_driver.trd set_variable_ifdef(CONFIG_S3MU_MCUX_S3MU CONFIG_MCUX_COMPONENT_driver.s3mu) set_variable_ifdef(CONFIG_DAI_NXP_MICFIL CONFIG_MCUX_COMPONENT_driver.pdm) set_variable_ifdef(CONFIG_PINCTRL_NXP_PORT CONFIG_MCUX_COMPONENT_driver.port) +set_variable_ifdef(CONFIG_INPUT_MCUX_KPP CONFIG_MCUX_COMPONENT_driver.kpp) set_variable_ifdef(CONFIG_DMA_NXP_EDMA CONFIG_MCUX_COMPONENT_driver.edma_soc_rev2) set_variable_ifdef(CONFIG_COUNTER_MCUX_SNVS_SRTC CONFIG_MCUX_COMPONENT_driver.snvs_lp) set_variable_ifdef(CONFIG_DISPLAY_MCUX_DCNANO_LCDIF CONFIG_MCUX_COMPONENT_driver.lcdif) diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/usb_host_config.h b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/usb_host_config.h index bf5f058abebd5..16a5f19beeef1 100644 --- a/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/usb_host_config.h +++ b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/usb_host_config.h @@ -16,10 +16,10 @@ #ifdef CONFIG_UHC_NXP_EHCI #define USB_HOST_CONFIG_EHCI (2U) #define USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE (1024U) -#define USB_HOST_CONFIG_EHCI_MAX_QH (8U) -#define USB_HOST_CONFIG_EHCI_MAX_QTD (8U) -#define USB_HOST_CONFIG_EHCI_MAX_ITD (0U) -#define USB_HOST_CONFIG_EHCI_MAX_SITD (0U) +#define USB_HOST_CONFIG_EHCI_MAX_QH (16U) +#define USB_HOST_CONFIG_EHCI_MAX_QTD (16U) +#define USB_HOST_CONFIG_EHCI_MAX_ITD (16U) +#define USB_HOST_CONFIG_EHCI_MAX_SITD (16U) #else #define USB_HOST_CONFIG_EHCI (0U) #endif /* CONFIG_USB_DC_NXP_EHCI */ diff --git a/modules/hal_rpi_pico/bootloader/CMakeLists.txt b/modules/hal_rpi_pico/bootloader/CMakeLists.txt index 7e8d39d8951fb..241ba3c23c305 100644 --- a/modules/hal_rpi_pico/bootloader/CMakeLists.txt +++ b/modules/hal_rpi_pico/bootloader/CMakeLists.txt @@ -45,8 +45,8 @@ target_include_directories(boot_stage2 PUBLIC target_link_options(boot_stage2 PRIVATE "-nostartfiles" - "--specs=nosys.specs" - "LINKER:--script=${boot_stage_dir}/boot_stage2.ld" + "--specs=picolibc.specs" + "-T${boot_stage_dir}/boot_stage2.ld" ) # The second stage bootloader is compiled without kconfig definitions. diff --git a/modules/hal_silabs/simplicity_sdk/CMakeLists.txt b/modules/hal_silabs/simplicity_sdk/CMakeLists.txt index b606212864e03..4d45bff3d248a 100644 --- a/modules/hal_silabs/simplicity_sdk/CMakeLists.txt +++ b/modules/hal_silabs/simplicity_sdk/CMakeLists.txt @@ -145,6 +145,8 @@ zephyr_include_directories( ${COMMON_DIR}/config ${COMMON_DIR}/inc ${DRIVER_DIR}/gpio/inc + ${DRIVER_DIR}/i2c/inc + ${DRIVER_DIR}/i2c/src ${EMDRV_DIR}/common/inc ${EMDRV_DIR}/dmadrv/config/s2_8ch/ ${EMDRV_DIR}/dmadrv/inc @@ -165,6 +167,7 @@ zephyr_include_directories( ${SERVICE_DIR}/sleeptimer/config ${SERVICE_DIR}/sleeptimer/inc ${SERVICE_DIR}/sleeptimer/src + ${SERVICE_DIR}/udelay/inc ${SECURITY_DIR}/sl_component/sl_protocol_crypto/src ${SECURITY_DIR}/sl_component/sli_crypto/inc ${BOARD_DIR} @@ -286,6 +289,14 @@ if(CONFIG_SILABS_SISDK_GPIO) ) endif() +if(CONFIG_SILABS_SISDK_I2C) + zephyr_library_sources( + ${DRIVER_DIR}/i2c/src/sl_i2c.c + ${SERVICE_DIR}/udelay/src/sl_udelay.c + ${PERIPHERAL_DIR}/src/sl_hal_i2c.c + ) +endif() + zephyr_library_sources_ifdef(CONFIG_SILABS_SISDK_LETIMER ${PERIPHERAL_DIR}/src/sl_hal_letimer.c) zephyr_library_sources_ifdef(CONFIG_SILABS_SISDK_TIMER ${PERIPHERAL_DIR}/src/sl_hal_timer.c) zephyr_library_sources_ifdef(CONFIG_SILABS_SISDK_VDAC ${PERIPHERAL_DIR}/src/sl_hal_vdac.c) diff --git a/modules/hal_silabs/simplicity_sdk/Kconfig b/modules/hal_silabs/simplicity_sdk/Kconfig index 0c96efb92e274..2fcaa9666f11d 100644 --- a/modules/hal_silabs/simplicity_sdk/Kconfig +++ b/modules/hal_silabs/simplicity_sdk/Kconfig @@ -7,6 +7,9 @@ menu "SiSDK configuration" config SILABS_SISDK_GPIO bool "Peripheral HAL for GPIO" +config SILABS_SISDK_I2C + bool "Peripheral HAL for I2C" + config SILABS_SISDK_LETIMER bool "Peripheral HAL for LETIMER" diff --git a/modules/hal_silabs/simplicity_sdk/config/ll/sl_btctrl_config.h b/modules/hal_silabs/simplicity_sdk/config/ll/sl_btctrl_config.h index a08ff1fb87ebb..49352caf88155 100644 --- a/modules/hal_silabs/simplicity_sdk/config/ll/sl_btctrl_config.h +++ b/modules/hal_silabs/simplicity_sdk/config/ll/sl_btctrl_config.h @@ -60,6 +60,7 @@ #ifdef CONFIG_BT_EXT_ADV #define SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_SCANNER_PRESENT #endif #ifdef CONFIG_BT_PER_ADV_SYNC_TRANSFER_RECEIVER diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 5b40834d0b843..8ae45d6db2af3 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -408,6 +408,8 @@ enum wifi_security_type wpas_key_mgmt_to_zephyr(bool is_hapd, void *config, int return WIFI_SECURITY_TYPE_SAE_HNP; } case WPA_KEY_MGMT_SAE | WPA_KEY_MGMT_PSK: + case WPA_KEY_MGMT_SAE | WPA_KEY_MGMT_PSK_SHA256: + case WPA_KEY_MGMT_SAE | WPA_KEY_MGMT_PSK_SHA256 | WPA_KEY_MGMT_PSK: return WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL; case WPA_KEY_MGMT_FT_PSK: return WIFI_SECURITY_TYPE_FT_PSK; @@ -799,23 +801,27 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, resp.network_id)) { goto out; } - } else { - if (!wpa_cli_cmd_v("set_network %d group CCMP", resp.network_id)) { - goto out; - } - - if (!wpa_cli_cmd_v("set_network %d pairwise CCMP", - resp.network_id)) { - goto out; - } } - } else if (params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) { - if (!wpa_cli_cmd_v("set_network %d psk \"%s\"", resp.network_id, - psk_null_terminated)) { + + if (!wpa_cli_cmd_v("set_network %d group TKIP CCMP", resp.network_id)) { goto out; } + if (!wpa_cli_cmd_v("set_network %d pairwise TKIP CCMP", resp.network_id)) { + goto out; + } + } else if (params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) { if (params->sae_password) { + if ((params->sae_password_length < WIFI_PSK_MIN_LEN) || + (params->sae_password_length > WIFI_SAE_PSWD_MAX_LEN)) { + wpa_printf(MSG_ERROR, + "Passphrase should be in range (%d-%d) characters", + WIFI_PSK_MIN_LEN, WIFI_SAE_PSWD_MAX_LEN); + goto out; + } + strncpy(sae_null_terminated, params->sae_password, + WIFI_SAE_PSWD_MAX_LEN); + sae_null_terminated[params->sae_password_length] = '\0'; if (!wpa_cli_cmd_v("set_network %d sae_password \"%s\"", resp.network_id, sae_null_terminated)) { goto out; @@ -827,20 +833,29 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s, } } + if (!wpa_cli_cmd_v("set_network %d psk \"%s\"", resp.network_id, + psk_null_terminated)) { + goto out; + } + if (!wpa_cli_cmd_v("set sae_pwe 2")) { goto out; } - if (!wpa_cli_cmd_v("set_network %d key_mgmt WPA-PSK SAE", + if (!wpa_cli_cmd_v("set_network %d key_mgmt WPA-PSK WPA-PSK-SHA256 SAE", resp.network_id)) { goto out; } - if (!wpa_cli_cmd_v("set_network %d group CCMP", resp.network_id)) { + if (!wpa_cli_cmd_v("set_network %d proto WPA RSN", resp.network_id)) { goto out; } - if (!wpa_cli_cmd_v("set_network %d pairwise CCMP", resp.network_id)) { + if (!wpa_cli_cmd_v("set_network %d group TKIP CCMP", resp.network_id)) { + goto out; + } + + if (!wpa_cli_cmd_v("set_network %d pairwise TKIP CCMP", resp.network_id)) { goto out; } #ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE @@ -1908,6 +1923,11 @@ int supplicant_btm_query(const struct device *dev, uint8_t reason) goto out; } + /* Flush all unused BSS entries */ + if (!wpa_cli_cmd_v("bss_flush")) { + goto out; + } + if (!wpa_cli_cmd_v("wnm_bss_query %d", reason)) { goto out; } diff --git a/modules/lora-basics-modem/CMakeLists.txt b/modules/lora-basics-modem/CMakeLists.txt new file mode 100644 index 0000000000000..0e9cab498dd54 --- /dev/null +++ b/modules/lora-basics-modem/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2025 Embeint Inc +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_USE_LORA_BASICS_MODEM_DRIVERS) + + set(LORA_BASICS_MODEM_DIR ${ZEPHYR_CURRENT_MODULE_DIR}) + set(LBM_LIB_DIR ${LORA_BASICS_MODEM_DIR}/lbm_lib) + set(LBM_SMTC_MODEM_CORE_DIR ${LBM_LIB_DIR}/smtc_modem_core) + set(LBM_RADIO_DRIVERS_DIR ${LBM_LIB_DIR}/smtc_modem_core/radio_drivers) + + if(TARGET lora_basics_modem) + set(ZEPHYR_CURRENT_LIBRARY lora_basics_modem) + else() + zephyr_library_named(lora_basics_modem) + endif() + + zephyr_library_include_directories(${LBM_SMTC_MODEM_CORE_DIR}/smtc_ral/src) + zephyr_library_include_directories(${LBM_SMTC_MODEM_CORE_DIR}/smtc_ralf/src) + + if(CONFIG_LORA_SX126X) + include(sx126x.cmake) + elseif(CONFIG_LORA_SX127X) + include(sx127x.cmake) + endif() +endif() diff --git a/modules/lora-basics-modem/Kconfig b/modules/lora-basics-modem/Kconfig new file mode 100644 index 0000000000000..ce4382c247f70 --- /dev/null +++ b/modules/lora-basics-modem/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Semtech Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Top-level configuration file for LoRa Basics Modem containing LoRa +# transceiver drivers and LBM LoRaWAN stack + +config ZEPHYR_LORA_BASICS_MODEM_MODULE + bool + +config USE_LORA_BASICS_MODEM_DRIVERS + bool diff --git a/modules/lora-basics-modem/sx126x.cmake b/modules/lora-basics-modem/sx126x.cmake new file mode 100644 index 0000000000000..021f047711dc0 --- /dev/null +++ b/modules/lora-basics-modem/sx126x.cmake @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Semtech Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Used by LBM +zephyr_library_compile_definitions(SX126X) +zephyr_library_compile_definitions(SX126X_TRANSCEIVER) + +# Allow modem options +set(ALLOW_CSMA_BUILD true) + +set(LBM_SX126X_LIB_DIR ${LBM_RADIO_DRIVERS_DIR}/sx126x_driver/src) +zephyr_include_directories(${LBM_SX126X_LIB_DIR}) + +#----------------------------------------------------------------------------- +# Radio specific sources +#----------------------------------------------------------------------------- +zephyr_library_sources( + ${LBM_SX126X_LIB_DIR}/lr_fhss_mac.c + ${LBM_SX126X_LIB_DIR}/sx126x.c + ${LBM_SX126X_LIB_DIR}/sx126x_driver_version.c + ${LBM_SX126X_LIB_DIR}/sx126x_lr_fhss.c + ${LBM_SMTC_MODEM_CORE_DIR}/smtc_ral/src/ral_sx126x.c + ${LBM_SMTC_MODEM_CORE_DIR}/smtc_ralf/src/ralf_sx126x.c +) diff --git a/modules/lora-basics-modem/sx127x.cmake b/modules/lora-basics-modem/sx127x.cmake new file mode 100644 index 0000000000000..512114520d209 --- /dev/null +++ b/modules/lora-basics-modem/sx127x.cmake @@ -0,0 +1,28 @@ +# Copyright (c) 2024 Semtech Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Used by LBM +zephyr_library_compile_definitions(SX127X) +zephyr_library_compile_definitions(SX127X_TRANSCEIVER) + +if(CONFIG_DT_HAS_SEMTECH_SX1272_ENABLED) + zephyr_library_compile_definitions(SX1272) +endif() +if(CONFIG_DT_HAS_SEMTECH_SX1276_ENABLED) + zephyr_library_compile_definitions(SX1276) +endif() + +# Allow modem options +set(ALLOW_CSMA_BUILD true) + +set(LBM_SX127X_LIB_DIR ${LBM_RADIO_DRIVERS_DIR}/sx127x_driver/src) +zephyr_include_directories(${LBM_SX127X_LIB_DIR}) + +#----------------------------------------------------------------------------- +# Radio specific sources +#----------------------------------------------------------------------------- +zephyr_library_sources( + ${LBM_SX127X_LIB_DIR}/sx127x.c + ${LBM_SMTC_MODEM_CORE_DIR}/smtc_ral/src/ral_sx127x.c + ${LBM_SMTC_MODEM_CORE_DIR}/smtc_ralf/src/ralf_sx127x.c +) diff --git a/modules/loramac-node/Kconfig b/modules/loramac-node/Kconfig index cce6c98067790..0cd70c000d4b0 100644 --- a/modules/loramac-node/Kconfig +++ b/modules/loramac-node/Kconfig @@ -14,15 +14,15 @@ config HAS_SEMTECH_RADIO_DRIVERS config HAS_SEMTECH_SX1272 bool - select HAS_SEMTECH_RADIO_DRIVERS + select HAS_SEMTECH_RADIO_DRIVERS if LORA_MODULE_BACKEND_LORAMAC_NODE config HAS_SEMTECH_SX1276 bool - select HAS_SEMTECH_RADIO_DRIVERS + select HAS_SEMTECH_RADIO_DRIVERS if LORA_MODULE_BACKEND_LORAMAC_NODE config HAS_SEMTECH_SX126X bool - select HAS_SEMTECH_RADIO_DRIVERS + select HAS_SEMTECH_RADIO_DRIVERS if LORA_MODULE_BACKEND_LORAMAC_NODE config HAS_SEMTECH_LORAMAC bool "Semtech LoRaMac Stack" diff --git a/modules/mbedtls/Kconfig.mbedtls b/modules/mbedtls/Kconfig.mbedtls index 9a2576559f006..4a71ec4961421 100644 --- a/modules/mbedtls/Kconfig.mbedtls +++ b/modules/mbedtls/Kconfig.mbedtls @@ -453,7 +453,7 @@ config MBEDTLS_ENTROPY_POLL_ZEPHYR config MBEDTLS_OPENTHREAD_OPTIMIZATIONS_ENABLED bool "MbedTLS optimizations for OpenThread" - depends on NET_L2_OPENTHREAD + depends on OPENTHREAD default y if !NET_SOCKETS_SOCKOPT_TLS help Enable some OpenThread specific mbedTLS optimizations that allows to diff --git a/modules/openthread/openthread.c b/modules/openthread/openthread.c index 15cbefd26fe1f..b1ccd97576ee0 100644 --- a/modules/openthread/openthread.c +++ b/modules/openthread/openthread.c @@ -166,6 +166,22 @@ static void ot_joiner_start_handler(otError error, void *context) } } +static void ot_configure_instance(void) +{ +#ifndef CONFIG_OPENTHREAD_COPROCESSOR_RCP + /* Configure Child Supervision and MLE Child timeouts. */ + otChildSupervisionSetInterval(openthread_instance, + CONFIG_OPENTHREAD_CHILD_SUPERVISION_INTERVAL); + otChildSupervisionSetCheckTimeout(openthread_instance, + CONFIG_OPENTHREAD_CHILD_SUPERVISION_CHECK_TIMEOUT); + otThreadSetChildTimeout(openthread_instance, CONFIG_OPENTHREAD_MLE_CHILD_TIMEOUT); + + if (IS_ENABLED(CONFIG_OPENTHREAD_ROUTER_SELECTION_JITTER_OVERRIDE)) { + otThreadSetRouterSelectionJitter(openthread_instance, OT_ROUTER_SELECTION_JITTER); + } +#endif +} + static bool ot_setup_default_configuration(void) { otExtendedPanId xpanid = {0}; @@ -355,10 +371,7 @@ int openthread_init(void) } } - if (IS_ENABLED(CONFIG_OPENTHREAD_ROUTER_SELECTION_JITTER_OVERRIDE)) { - otThreadSetRouterSelectionJitter(openthread_instance, OT_ROUTER_SELECTION_JITTER); - } - + ot_configure_instance(); openthread_mutex_unlock(); (void)k_work_submit_to_queue(&openthread_work_q, &openthread_work); @@ -406,13 +419,6 @@ int openthread_run(void) } } - /* Configure Child Supervision and MLE Child timeouts. */ - otChildSupervisionSetInterval(openthread_instance, - CONFIG_OPENTHREAD_CHILD_SUPERVISION_INTERVAL); - otChildSupervisionSetCheckTimeout(openthread_instance, - CONFIG_OPENTHREAD_CHILD_SUPERVISION_CHECK_TIMEOUT); - otThreadSetChildTimeout(openthread_instance, CONFIG_OPENTHREAD_MLE_CHILD_TIMEOUT); - if (otDatasetIsCommissioned(openthread_instance)) { /* OpenThread already has dataset stored - skip the * configuration. diff --git a/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 98d67e2ad082b..789c47d3a4731 100644 --- a/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -2,11 +2,16 @@ status = "okay"; }; +&gpio6 { + status = "okay"; +}; + +&exmif { + status = "okay"; +}; + &mx25uw63 { - read-command = <0xEC13>; - command-length = "INSTR_2_BYTE"; - address-length = "ADDR_4_BYTE"; - rx-dummy = <20>; + status = "okay"; xip-config = <1 0 0x20000000 0>; }; diff --git a/samples/application_development/code_relocation_nocopy/sample.yaml b/samples/application_development/code_relocation_nocopy/sample.yaml index 37e009bc98711..62929419c5342 100644 --- a/samples/application_development/code_relocation_nocopy/sample.yaml +++ b/samples/application_development/code_relocation_nocopy/sample.yaml @@ -6,6 +6,7 @@ tests: platform_allow: - qemu_cortex_m3 - nrf5340dk/nrf5340/cpuapp + - nrf54h20dk/nrf54h20/cpuapp - stm32f769i_disco - stm32h7b3i_dk - stm32h573i_dk diff --git a/samples/basic/blinky_pwm/boards/cyw920829m2evk_02.overlay b/samples/basic/blinky_pwm/boards/cyw920829m2evk_02.overlay index 26dd161b1cfe3..5bffc1596cbeb 100644 --- a/samples/basic/blinky_pwm/boards/cyw920829m2evk_02.overlay +++ b/samples/basic/blinky_pwm/boards/cyw920829m2evk_02.overlay @@ -6,7 +6,7 @@ */ #include -#include +#include / { aliases { @@ -22,15 +22,18 @@ }; }; -&pwm0_0 { - status = "okay"; - pinctrl-0 = <&p1_1_pwm0_0>; - pinctrl-names = "default"; - divider-type = ; - divider-sel = <1>; - divider-val = <9599>; -}; +&tcpwm0_0 { + status = "okay"; + divider-type = ; + divider-sel = <1>; + divider-val = <9599>; + pwm0_0: pwm0_0 { + status = "okay"; + pinctrl-0 = <&p1_1_pwm0_0>; + pinctrl-names = "default"; + }; +}; &pinctrl { p1_1_pwm0_0: p1_1_pwm0_0 { diff --git a/samples/basic/blinky_pwm/boards/esp32c3_supermini.overlay b/samples/basic/blinky_pwm/boards/esp32c3_supermini.overlay index ed2fc7c1b7b50..0af08beb7cbca 100644 --- a/samples/basic/blinky_pwm/boards/esp32c3_supermini.overlay +++ b/samples/basic/blinky_pwm/boards/esp32c3_supermini.overlay @@ -5,7 +5,7 @@ * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. */ - #include +#include / { aliases { diff --git a/samples/basic/blinky_pwm/boards/mimxrt685_evk_mimxrt685s_cm33.overlay b/samples/basic/blinky_pwm/boards/mimxrt685_evk_mimxrt685s_cm33.overlay index 959295256517a..8ecc90d48186d 100644 --- a/samples/basic/blinky_pwm/boards/mimxrt685_evk_mimxrt685s_cm33.overlay +++ b/samples/basic/blinky_pwm/boards/mimxrt685_evk_mimxrt685s_cm33.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &leds { status = "disabled"; }; diff --git a/samples/basic/blinky_pwm/boards/nucleo_l476rg.overlay b/samples/basic/blinky_pwm/boards/nucleo_l476rg.overlay index 278d6c1130d15..6e1b199b4ad24 100644 --- a/samples/basic/blinky_pwm/boards/nucleo_l476rg.overlay +++ b/samples/basic/blinky_pwm/boards/nucleo_l476rg.overlay @@ -4,7 +4,6 @@ * Copyright (c) 2022 STMicroelectronics */ - / { pwmleds: pwmleds { compatible = "pwm-leds"; @@ -18,7 +17,6 @@ aliases { pwm-led0 = &green_pwm_led; }; - }; &pwm2 { diff --git a/samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay b/samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay index 13afe08848cda..4bf4546016887 100644 --- a/samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay +++ b/samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay @@ -17,7 +17,6 @@ pwm-led0 = &pwm_led_0; pwm-0 = &pwm0; }; - }; &pwm0 { diff --git a/samples/basic/blinky_pwm/boards/wio_terminal.overlay b/samples/basic/blinky_pwm/boards/wio_terminal.overlay index cf60fe058b7b7..c112979ca64aa 100644 --- a/samples/basic/blinky_pwm/boards/wio_terminal.overlay +++ b/samples/basic/blinky_pwm/boards/wio_terminal.overlay @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { aliases { pwm-led0 = &pwm_led0; }; diff --git a/samples/basic/button/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/basic/button/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index 3c8c3537e39eb..89a6820cb9fc5 100644 --- a/samples/basic/button/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/samples/basic/button/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -3,10 +3,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -&gpio{ +&gpio { status = "okay"; }; -&gpio18{ +&gpio18 { irqs = <0 16>; }; diff --git a/samples/basic/fade_led/boards/cyw920829m2evk_02.overlay b/samples/basic/fade_led/boards/cyw920829m2evk_02.overlay index 26dd161b1cfe3..a1bbaebfa67ff 100644 --- a/samples/basic/fade_led/boards/cyw920829m2evk_02.overlay +++ b/samples/basic/fade_led/boards/cyw920829m2evk_02.overlay @@ -6,11 +6,12 @@ */ #include -#include +#include / { aliases { pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; }; pwmleds { @@ -19,21 +20,46 @@ pwms = <&pwm0_0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; label = "PWM MB1"; }; + + pwm_led1: pwm_led_1 { + pwms = <&pwm1_5 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM MB2"; + }; }; }; -&pwm0_0 { - status = "okay"; - pinctrl-0 = <&p1_1_pwm0_0>; - pinctrl-names = "default"; - divider-type = ; - divider-sel = <1>; - divider-val = <9599>; +&tcpwm0_0 { + status = "okay"; + divider-type = ; + divider-sel = <1>; + divider-val = <9599>; + + pwm0_0: pwm0_0 { + status = "okay"; + pinctrl-0 = <&p1_1_pwm0_0>; + pinctrl-names = "default"; + }; }; +&tcpwm1_5 { + status = "okay"; + divider-type = ; + divider-sel = <1>; + divider-val = <9599>; + + pwm1_5: pwm1_5 { + status = "okay"; + pinctrl-0 = <&p5_2_pwm1_5>; + pinctrl-names = "default"; + }; +}; &pinctrl { p1_1_pwm0_0: p1_1_pwm0_0 { drive-push-pull; }; + + p5_2_pwm1_5: p5_2_pwm1_5 { + drive-push-pull; + }; }; diff --git a/samples/basic/hash_map/README.rst b/samples/basic/hash_map/README.rst index 0c5d91a3dae77..2b7f1cc3d2b3a 100644 --- a/samples/basic/hash_map/README.rst +++ b/samples/basic/hash_map/README.rst @@ -16,7 +16,7 @@ This is a simple example that repeatedly: Building ******** -This application can be built on :ref:`native_sim ` as follows: +This application can be built on :zephyr:board:`native_sim ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/basic/hash_map diff --git a/samples/basic/servo_motor/boards/mimxrt1062_fmurt6.overlay b/samples/basic/servo_motor/boards/mimxrt1062_fmurt6.overlay index d5d6d4cf6d41a..d45b2457d4d69 100644 --- a/samples/basic/servo_motor/boards/mimxrt1062_fmurt6.overlay +++ b/samples/basic/servo_motor/boards/mimxrt1062_fmurt6.overlay @@ -4,13 +4,13 @@ servo: servo { compatible = "pwm-servo"; pwms = <&flexpwm2_pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; /* FMU_CH1 */ - /* <&flexpwm2_pwm1 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH2 */ - /* <&flexpwm2_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH3 */ - /* <&flexpwm2_pwm3 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH4 */ - /* <&flexpwm3_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>,*/ /* FMU_CH5 */ - /* <&flexpwm3_pwm0 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH6 */ - /* <&flexpwm4_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH7 */ - /* <&flexpwm4_pwm0 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH8 */ + /* <&flexpwm2_pwm1 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH2 */ + /* <&flexpwm2_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH3 */ + /* <&flexpwm2_pwm3 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH4 */ + /* <&flexpwm3_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>,*/ /* FMU_CH5 */ + /* <&flexpwm3_pwm0 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH6 */ + /* <&flexpwm4_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH7 */ + /* <&flexpwm4_pwm0 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH8 */ min-pulse = ; max-pulse = ; }; diff --git a/samples/basic/servo_motor/boards/rddrone_fmuk66.overlay b/samples/basic/servo_motor/boards/rddrone_fmuk66.overlay index a42305941fd54..801d2b90aaebf 100644 --- a/samples/basic/servo_motor/boards/rddrone_fmuk66.overlay +++ b/samples/basic/servo_motor/boards/rddrone_fmuk66.overlay @@ -3,11 +3,11 @@ servo: servo { compatible = "pwm-servo"; pwms = <&ftm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; /* FMU_CH1 */ - /* <&ftm0 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>,*/ /* FMU_CH2 */ - /* <&ftm0 4 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH3 */ - /* <&ftm0 5 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH4 */ - /* <&ftm3 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>,*/ /* FMU_CH5 */ - /* <&ftm3 7 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH6 */ + /* <&ftm0 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>,*/ /* FMU_CH2 */ + /* <&ftm0 4 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH3 */ + /* <&ftm0 5 PWM_MSEC(20) PWM_POLARITY_NORMAL>, */ /* FMU_CH4 */ + /* <&ftm3 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>,*/ /* FMU_CH5 */ + /* <&ftm3 7 PWM_MSEC(20) PWM_POLARITY_NORMAL>; */ /* FMU_CH6 */ min-pulse = ; max-pulse = ; }; diff --git a/samples/basic/sys_heap/README.rst b/samples/basic/sys_heap/README.rst index e6d6a11e6fb7a..57e6738622a96 100644 --- a/samples/basic/sys_heap/README.rst +++ b/samples/basic/sys_heap/README.rst @@ -12,7 +12,7 @@ prints system heap usage to the console. Building ******** -This application can be built on :ref:`native_sim ` as follows: +This application can be built on :zephyr:board:`native_sim ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/basic/sys_heap diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay index d35e19ce79b0d..b7fb113423058 100644 --- a/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay +++ b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay @@ -9,17 +9,17 @@ nrf21540-gpio-if { gpios = <&arduino_header 11 0>, /* tx-en-gpios */ - <&arduino_header 9 0>, /* rx-en-gpios */ + <&arduino_header 9 0>, /* rx-en-gpios */ <&arduino_header 15 0>, /* pdn-gpios */ <&arduino_header 10 0>, /* ant-sel-gpios */ - <&arduino_header 8 0>; /* mode-gpios */ + <&arduino_header 8 0>; /* mode-gpios */ }; nrf21540-spi-if { gpios = <&arduino_header 16 0>, /* cs-gpios */ - <&gpio0 8 0>, /* SPIM_SCK */ - <&gpio0 10 0>, /* SPIM_MISO */ - <&gpio0 9 0>; /* SPIM_MOSI */ + <&gpio0 8 0>, /* SPIM_SCK */ + <&gpio0 10 0>, /* SPIM_MISO */ + <&gpio0 9 0>; /* SPIM_MOSI */ }; }; }; diff --git a/samples/bluetooth/bap_unicast_server/CMakeLists.txt b/samples/bluetooth/bap_unicast_server/CMakeLists.txt index 66649d87a33c8..91e5bf5ed7afe 100644 --- a/samples/bluetooth/bap_unicast_server/CMakeLists.txt +++ b/samples/bluetooth/bap_unicast_server/CMakeLists.txt @@ -8,4 +8,7 @@ target_sources(app PRIVATE src/main.c ) +zephyr_sources_ifdef(CONFIG_LIBLC3 src/stream_lc3.c) +zephyr_sources_ifdef(CONFIG_BT_AUDIO_TX src/stream_tx.c) + zephyr_library_include_directories(${ZEPHYR_BASE}/samples/bluetooth) diff --git a/samples/bluetooth/bap_unicast_server/src/main.c b/samples/bluetooth/bap_unicast_server/src/main.c index 85a80e07a204a..741a84db353c9 100644 --- a/samples/bluetooth/bap_unicast_server/src/main.c +++ b/samples/bluetooth/bap_unicast_server/src/main.c @@ -32,6 +32,8 @@ #include #include +#include "stream_tx.h" + #define AVAILABLE_SINK_CONTEXT (BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED | \ BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | \ BT_AUDIO_CONTEXT_TYPE_MEDIA | \ @@ -53,7 +55,6 @@ static const struct bt_audio_codec_cap lc3_codec_cap = BT_AUDIO_CODEC_CAP_LC3( (BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | BT_AUDIO_CONTEXT_TYPE_MEDIA)); static struct bt_conn *default_conn; -static struct k_work_delayable audio_send_work; static struct audio_sink { struct bt_bap_stream stream; size_t recv_cnt; @@ -86,33 +87,6 @@ static const struct bt_data ad[] = { BT_DATA(BT_DATA_NAME_COMPLETE, CONFIG_BT_DEVICE_NAME, sizeof(CONFIG_BT_DEVICE_NAME) - 1), }; -#define AUDIO_DATA_TIMEOUT_US 1000000UL /* Send data every 1 second */ -#define SDU_INTERVAL_US 10000UL /* 10 ms SDU interval */ - -static uint16_t get_and_incr_seq_num(const struct bt_bap_stream *stream) -{ - for (size_t i = 0U; i < configured_source_stream_count; i++) { - if (stream == &source_streams[i].stream) { - uint16_t seq_num; - - seq_num = source_streams[i].seq_num; - - if (IS_ENABLED(CONFIG_LIBLC3)) { - source_streams[i].seq_num++; - } else { - source_streams[i].seq_num += (AUDIO_DATA_TIMEOUT_US / - SDU_INTERVAL_US); - } - - return seq_num; - } - } - - printk("Could not find endpoint from stream %p\n", stream); - - return 0; -} - #if defined(CONFIG_LIBLC3) #include "lc3.h" @@ -121,7 +95,6 @@ static uint16_t get_and_incr_seq_num(const struct bt_bap_stream *stream) #define MAX_FRAME_DURATION_US 10000 #define MAX_NUM_SAMPLES ((MAX_FRAME_DURATION_US * MAX_SAMPLE_RATE) / USEC_PER_SEC) -static int16_t audio_buf[MAX_NUM_SAMPLES]; static lc3_decoder_t lc3_decoder; static lc3_decoder_mem_48k_t lc3_decoder_mem; static int frames_per_sdu; @@ -194,76 +167,6 @@ static void print_qos(const struct bt_bap_qos_cfg *qos) qos->rtn, qos->latency, qos->pd); } -/** - * @brief Send audio data on timeout - * - * This will send an increasing amount of audio data, starting from 1 octet. - * The data is just mock data, and does not actually represent any audio. - * - * First iteration : 0x00 - * Second iteration: 0x00 0x01 - * Third iteration : 0x00 0x01 0x02 - * - * And so on, until it wraps around the configured MTU (CONFIG_BT_ISO_TX_MTU) - * - * @param work Pointer to the work structure - */ -static void audio_timer_timeout(struct k_work *work) -{ - int ret; - static uint8_t buf_data[CONFIG_BT_ISO_TX_MTU]; - static bool data_initialized; - struct net_buf *buf; - - if (!data_initialized) { - /* TODO: Actually encode some audio data */ - for (size_t i = 0U; i < ARRAY_SIZE(buf_data); i++) { - buf_data[i] = (uint8_t)i; - } - - data_initialized = true; - } - - /* We configured the sink streams to be first in `streams`, so that - * we can use `stream[i]` to select sink streams (i.e. streams with - * data going to the server) - */ - for (size_t i = 0; i < configured_source_stream_count; i++) { - struct bt_bap_stream *stream = &source_streams[i].stream; - - buf = net_buf_alloc(&tx_pool, K_NO_WAIT); - if (buf == NULL) { - printk("Failed to allocate TX buffer\n"); - /* Break and retry later */ - break; - } - net_buf_reserve(buf, BT_ISO_CHAN_SEND_RESERVE); - - net_buf_add_mem(buf, buf_data, stream->qos->sdu); - - ret = bt_bap_stream_send(stream, buf, get_and_incr_seq_num(stream)); - if (ret < 0) { - printk("Failed to send audio data on streams[%zu] (%p): (%d)\n", - i, stream, ret); - net_buf_unref(buf); - } else { - source_streams[i].send_cnt++; - - if (CONFIG_INFO_REPORTING_INTERVAL > 0 && - (source_streams[i].send_cnt % CONFIG_INFO_REPORTING_INTERVAL) == 0U) { - printk("Stream %p: Sent %u total SDUs of size %u\n", stream, - source_streams[i].send_cnt, stream->qos->sdu); - } - } - } - -#if defined(CONFIG_LIBLC3) - k_work_schedule(&audio_send_work, K_USEC(MAX_FRAME_DURATION_US)); -#else - k_work_schedule(&audio_send_work, K_USEC(AUDIO_DATA_TIMEOUT_US)); -#endif -} - static enum bt_audio_dir stream_dir(const struct bt_bap_stream *stream) { for (size_t i = 0U; i < ARRAY_SIZE(source_streams); i++) { @@ -428,13 +331,6 @@ static int lc3_start(struct bt_bap_stream *stream, struct bt_bap_ascs_rsp *rsp) } } - if (configured_source_stream_count > 0 && - !k_work_delayable_is_pending(&audio_send_work)) { - - /* Start send timer */ - k_work_schedule(&audio_send_work, K_MSEC(0)); - } - return 0; } @@ -504,6 +400,8 @@ static void stream_recv_lc3_codec(struct bt_bap_stream *stream, const struct bt_iso_recv_info *info, struct net_buf *buf) { + static int16_t audio_buf[MAX_NUM_SAMPLES]; + struct audio_sink *sink_stream = CONTAINER_OF(stream, struct audio_sink, stream); const bool valid_data = (info->flags & BT_ISO_FLAGS_VALID) != 0; const int octets_per_frame = buf->len / frames_per_sdu; @@ -563,8 +461,13 @@ static void stream_stopped(struct bt_bap_stream *stream, uint8_t reason) { printk("Audio Stream %p stopped with reason 0x%02X\n", stream, reason); - /* Stop send timer */ - k_work_cancel_delayable(&audio_send_work); + if (IS_ENABLED(CONFIG_BT_AUDIO_TX) && stream_dir(stream) == BT_AUDIO_DIR_SOURCE) { + const int err = stream_tx_unregister(stream); + + if (err != 0) { + printk("Failed to register stream %p for TX: %d\n", stream, err); + } + } } static void stream_started(struct bt_bap_stream *stream) @@ -582,6 +485,12 @@ static void stream_started(struct bt_bap_stream *stream) struct audio_sink *sink_stream = CONTAINER_OF(stream, struct audio_sink, stream); sink_stream->recv_cnt = 0U; + } else if (IS_ENABLED(CONFIG_BT_AUDIO_TX)) { + const int err = stream_tx_register(stream); + + if (err != 0) { + printk("Failed to register stream %p for TX: %d\n", stream, err); + } } } @@ -769,6 +678,10 @@ int main(void) return 0; } + if (IS_ENABLED(CONFIG_BT_AUDIO_TX)) { + stream_tx_init(); + } + bt_bap_unicast_server_register(¶m); bt_bap_unicast_server_register_cb(&unicast_server_cb); @@ -813,8 +726,6 @@ int main(void) } while (true) { - struct k_work_sync sync; - err = bt_le_ext_adv_start(adv, BT_LE_EXT_ADV_START_DEFAULT); if (err) { printk("Failed to start advertising set (err %d)\n", err); @@ -823,11 +734,6 @@ int main(void) printk("Advertising successfully started\n"); - if (CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT > 0) { - /* Start send timer */ - k_work_init_delayable(&audio_send_work, audio_timer_timeout); - } - err = k_sem_take(&sem_disconnected, K_FOREVER); if (err != 0) { printk("failed to take sem_disconnected (err %d)\n", err); @@ -836,8 +742,6 @@ int main(void) /* reset data */ configured_source_stream_count = 0U; - k_work_cancel_delayable_sync(&audio_send_work, &sync); - } return 0; } diff --git a/samples/bluetooth/bap_unicast_server/src/stream_lc3.c b/samples/bluetooth/bap_unicast_server/src/stream_lc3.c new file mode 100644 index 0000000000000..c87764a58d516 --- /dev/null +++ b/samples/bluetooth/bap_unicast_server/src/stream_lc3.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2024-2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "stream_lc3.h" +#include "stream_tx.h" + +LOG_MODULE_REGISTER(lc3, LOG_LEVEL_INF); + +#define LC3_MAX_SAMPLE_RATE 48000U +#define LC3_MAX_FRAME_DURATION_US 10000U +#define LC3_MAX_NUM_SAMPLES ((LC3_MAX_FRAME_DURATION_US * LC3_MAX_SAMPLE_RATE) / USEC_PER_SEC) +/* codec does clipping above INT16_MAX - 3000 */ +#define AUDIO_VOLUME (INT16_MAX - 3000) +#define AUDIO_TONE_FREQUENCY_HZ 400 + +static int16_t audio_buf[LC3_MAX_NUM_SAMPLES]; +/** + * Use the math lib to generate a sine-wave using 16 bit samples into a buffer. + * + * @param stream The TX stream to generate and fill the sine wave for + */ +static void fill_audio_buf_sin(struct tx_stream *stream) +{ + const unsigned int num_samples = + (stream->lc3_tx.frame_duration_us * stream->lc3_tx.freq_hz) / USEC_PER_SEC; + const int sine_period_samples = stream->lc3_tx.freq_hz / AUDIO_TONE_FREQUENCY_HZ; + const float step = 2 * 3.1415f / sine_period_samples; + + for (unsigned int i = 0; i < num_samples; i++) { + const float sample = sinf(i * step); + + audio_buf[i] = (int16_t)(AUDIO_VOLUME * sample); + } +} + +static int extract_lc3_config(struct tx_stream *stream) +{ + const struct bt_audio_codec_cfg *codec_cfg = stream->bap_stream->codec_cfg; + struct stream_lc3_tx *lc3_tx = &stream->lc3_tx; + int ret; + + LOG_INF("Extracting LC3 configuration values"); + + ret = bt_audio_codec_cfg_get_freq(codec_cfg); + if (ret >= 0) { + ret = bt_audio_codec_cfg_freq_to_freq_hz(ret); + if (ret > 0) { + if (LC3_CHECK_SR_HZ(ret)) { + lc3_tx->freq_hz = (uint32_t)ret; + } else { + LOG_ERR("Unsupported sampling frequency for LC3: %d", ret); + + return ret; + } + } else { + LOG_ERR("Invalid frequency: %d", ret); + + return ret; + } + } else { + LOG_ERR("Could not get frequency: %d", ret); + + return ret; + } + + ret = bt_audio_codec_cfg_get_frame_dur(codec_cfg); + if (ret >= 0) { + ret = bt_audio_codec_cfg_frame_dur_to_frame_dur_us(ret); + if (ret > 0) { + if (LC3_CHECK_DT_US(ret)) { + lc3_tx->frame_duration_us = (uint32_t)ret; + } else { + LOG_ERR("Unsupported frame duration for LC3: %d", ret); + + return ret; + } + } else { + LOG_ERR("Invalid frame duration: %d", ret); + + return ret; + } + } else { + LOG_ERR("Could not get frame duration: %d", ret); + + return ret; + } + + ret = bt_audio_codec_cfg_get_chan_allocation(codec_cfg, &lc3_tx->chan_allocation, false); + if (ret != 0) { + LOG_DBG("Could not get channel allocation: %d", ret); + lc3_tx->chan_allocation = BT_AUDIO_LOCATION_MONO_AUDIO; + } + + lc3_tx->chan_cnt = bt_audio_get_chan_count(lc3_tx->chan_allocation); + + ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(codec_cfg, true); + if (ret >= 0) { + lc3_tx->frame_blocks_per_sdu = (uint8_t)ret; + } + + ret = bt_audio_codec_cfg_get_octets_per_frame(codec_cfg); + if (ret >= 0) { + lc3_tx->octets_per_frame = (uint16_t)ret; + } else { + LOG_ERR("Could not get octets per frame: %d", ret); + + return ret; + } + + return 0; +} + +static bool encode_frame(struct tx_stream *stream, uint8_t index, struct net_buf *out_buf) +{ + const uint16_t octets_per_frame = stream->lc3_tx.octets_per_frame; + int lc3_ret; + + /* Generate sine wave */ + fill_audio_buf_sin(stream); + + lc3_ret = lc3_encode(stream->lc3_tx.encoder, LC3_PCM_FORMAT_S16, audio_buf, 1, + octets_per_frame, net_buf_tail(out_buf)); + if (lc3_ret < 0) { + LOG_ERR("LC3 encoder failed - wrong parameters?: %d", lc3_ret); + + return false; + } + + out_buf->len += octets_per_frame; + + return true; +} + +static bool encode_frame_block(struct tx_stream *stream, struct net_buf *out_buf) +{ + for (uint8_t i = 0U; i < stream->lc3_tx.chan_cnt; i++) { + /* We provide the total number of decoded frames to `decode_frame` for logging + * purposes + */ + if (!encode_frame(stream, i, out_buf)) { + LOG_WRN("Failed to encode frame %u", i); + return false; + } + } + + return true; +} + +void stream_lc3_add_data(struct tx_stream *stream, struct net_buf *buf) +{ + for (uint8_t i = 0U; i < stream->lc3_tx.frame_blocks_per_sdu; i++) { + if (!encode_frame_block(stream, buf)) { + LOG_WRN("Failed to encode frame block %u", i); + break; + } + } +} + +int stream_lc3_init(struct tx_stream *stream) +{ + int err; + + err = extract_lc3_config(stream); + if (err != 0) { + memset(&stream->lc3_tx, 0, sizeof(stream->lc3_tx)); + + return err; + } + + /* Fill audio buffer with Sine wave only once and repeat encoding the same tone frame */ + LOG_INF("Initializing sine wave data"); + fill_audio_buf_sin(stream); + + LOG_INF("Setting up LC3 encoder"); + stream->lc3_tx.encoder = + lc3_setup_encoder(stream->lc3_tx.frame_duration_us, stream->lc3_tx.freq_hz, 0, + &stream->lc3_tx.encoder_mem); + + if (stream->lc3_tx.encoder == NULL) { + LOG_ERR("Failed to setup LC3 encoder"); + + memset(&stream->lc3_tx, 0, sizeof(stream->lc3_tx)); + + return -ENOEXEC; + } + + return 0; +} diff --git a/samples/bluetooth/bap_unicast_server/src/stream_lc3.h b/samples/bluetooth/bap_unicast_server/src/stream_lc3.h new file mode 100644 index 0000000000000..c323372c3298a --- /dev/null +++ b/samples/bluetooth/bap_unicast_server/src/stream_lc3.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef STREAM_LC3_H +#define STREAM_LC3_H + +#include + +#include +#include +#include + +/* Since the lc3.h header file is not available when CONFIG_LIBLC3=n, we need to guard the include + * and use of it + */ +#if defined(CONFIG_LIBLC3) +/* Header file for the liblc3 */ +#include + +struct stream_lc3_tx { + uint32_t freq_hz; + uint32_t frame_duration_us; + uint16_t octets_per_frame; + uint8_t frame_blocks_per_sdu; + uint8_t chan_cnt; + enum bt_audio_location chan_allocation; + lc3_encoder_t encoder; + lc3_encoder_mem_48k_t encoder_mem; +}; +#endif /* CONFIG_LIBLC3 */ + +/* Opaque definition to avoid including stream_tx.h */ +struct tx_stream; + +/* + * @brief Initialize LC3 encoder for a stream + * + * This will initialize the encoder for the provided TX stream + */ +int stream_lc3_init(struct tx_stream *stream); + +/** + * Add LC3 encoded data to the provided buffer from the provided stream + * + * @param stream The TX stream to add data from + * @param buf The buffer to store the encoded audio data in + */ +void stream_lc3_add_data(struct tx_stream *stream, struct net_buf *buf); + +#endif /* STREAM_LC3_H */ diff --git a/samples/bluetooth/bap_unicast_server/src/stream_tx.c b/samples/bluetooth/bap_unicast_server/src/stream_tx.c new file mode 100644 index 0000000000000..9950e45596f66 --- /dev/null +++ b/samples/bluetooth/bap_unicast_server/src/stream_tx.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2024-2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stream_lc3.h" +#include "stream_tx.h" + +LOG_MODULE_REGISTER(stream_tx, LOG_LEVEL_INF); + +static struct tx_stream tx_streams[CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT]; + +static bool stream_is_streaming(const struct bt_bap_stream *bap_stream) +{ + struct bt_bap_ep_info ep_info; + int err; + + if (bap_stream == NULL) { + return false; + } + + /* No-op if stream is not configured */ + if (bap_stream->ep == NULL) { + return false; + } + + err = bt_bap_ep_get_info(bap_stream->ep, &ep_info); + if (err != 0) { + return false; + } + + return ep_info.state == BT_BAP_EP_STATE_STREAMING; +} + +static void tx_thread_func(void *arg1, void *arg2, void *arg3) +{ + NET_BUF_POOL_FIXED_DEFINE(tx_pool, CONFIG_BT_ISO_TX_BUF_COUNT, + BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_TX_MTU), + CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL); + static uint8_t mock_data[CONFIG_BT_ISO_TX_MTU]; + + for (size_t i = 0U; i < ARRAY_SIZE(mock_data); i++) { + mock_data[i] = (uint8_t)i; + } + + /* This loop will attempt to send on all streams in the streaming state in a round robin + * fashion. + * The TX is controlled by the number of buffers configured, and increasing + * CONFIG_BT_ISO_TX_BUF_COUNT will allow for more streams in parallel, or to submit more + * buffers per stream. + * Once a buffer has been freed by the stack, it triggers the next TX. + */ + while (true) { + int err = -ENOEXEC; + + for (size_t i = 0U; i < ARRAY_SIZE(tx_streams); i++) { + struct bt_bap_stream *bap_stream = tx_streams[i].bap_stream; + + if (stream_is_streaming(bap_stream)) { + uint16_t sdu_len; + struct net_buf *buf; + + buf = net_buf_alloc(&tx_pool, K_FOREVER); + net_buf_reserve(buf, BT_ISO_CHAN_SEND_RESERVE); + + if (IS_ENABLED(CONFIG_LIBLC3) && + bap_stream->codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) { + stream_lc3_add_data(&tx_streams[i], buf); + } else { + __ASSERT(bap_stream->qos->sdu <= ARRAY_SIZE(mock_data), + "Configured codec SDU len %u does not match mock " + "data size %zu", + bap_stream->qos->sdu, ARRAY_SIZE(mock_data)); + net_buf_add_mem(buf, mock_data, bap_stream->qos->sdu); + } + + sdu_len = buf->len; + + err = bt_bap_stream_send(bap_stream, buf, tx_streams[i].seq_num); + if (err == 0) { + tx_streams[i].seq_num++; + + if (CONFIG_INFO_REPORTING_INTERVAL > 0 && + (tx_streams[i].seq_num % + CONFIG_INFO_REPORTING_INTERVAL) == 0U) { + LOG_INF("Stream %p: Sent %u total SDUs of size %u", + bap_stream, tx_streams[i].seq_num, sdu_len); + } + } else { + LOG_ERR("Unable to send: %d", err); + net_buf_unref(buf); + } + } /* No-op if stream is not streaming */ + } + + if (err != 0) { + /* In case of any errors, retry with a delay */ + k_sleep(K_MSEC(10)); + } + } +} + +int stream_tx_register(struct bt_bap_stream *bap_stream) +{ + if (bap_stream == NULL) { + return -EINVAL; + } + + for (size_t i = 0U; i < ARRAY_SIZE(tx_streams); i++) { + if (tx_streams[i].bap_stream == NULL) { + tx_streams[i].bap_stream = bap_stream; + tx_streams[i].seq_num = 0U; + + if (IS_ENABLED(CONFIG_LIBLC3) && + bap_stream->codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) { + const int err = stream_lc3_init(&tx_streams[i]); + + if (err != 0) { + tx_streams[i].bap_stream = NULL; + + return err; + } + } + + LOG_INF("Registered %p for TX", bap_stream); + if (bap_stream->qos->sdu > CONFIG_BT_ISO_TX_MTU) { + LOG_WRN("Stream configured for SDUs larger (%u) than " + "CONFIG_BT_ISO_TX_MTU (%d)", + bap_stream->qos->sdu, CONFIG_BT_ISO_TX_MTU); + } + + return 0; + } + } + + return -ENOMEM; +} + +int stream_tx_unregister(struct bt_bap_stream *bap_stream) +{ + if (bap_stream == NULL) { + return -EINVAL; + } + + for (size_t i = 0U; i < ARRAY_SIZE(tx_streams); i++) { + if (tx_streams[i].bap_stream == bap_stream) { + tx_streams[i].bap_stream = NULL; + + LOG_INF("Unregistered %p for TX", bap_stream); + + return 0; + } + } + + return -ENODATA; +} + +void stream_tx_init(void) +{ + static bool thread_started; + + if (!thread_started) { + static K_KERNEL_STACK_DEFINE(tx_thread_stack, + IS_ENABLED(CONFIG_LIBLC3) ? 4096U : 1024U); + const int tx_thread_prio = K_PRIO_PREEMPT(5); + static struct k_thread tx_thread; + + k_thread_create(&tx_thread, tx_thread_stack, K_KERNEL_STACK_SIZEOF(tx_thread_stack), + tx_thread_func, NULL, NULL, NULL, tx_thread_prio, 0, K_NO_WAIT); + k_thread_name_set(&tx_thread, "TX thread"); + thread_started = true; + } +} diff --git a/samples/bluetooth/bap_unicast_server/src/stream_tx.h b/samples/bluetooth/bap_unicast_server/src/stream_tx.h new file mode 100644 index 0000000000000..0f43d71e958a2 --- /dev/null +++ b/samples/bluetooth/bap_unicast_server/src/stream_tx.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef STREAM_TX_H +#define STREAM_TX_H + +#include + +#include +#include +#include +#include + +#include "stream_lc3.h" + +struct tx_stream { + struct bt_bap_stream *bap_stream; + uint16_t seq_num; + +#if defined(CONFIG_LIBLC3) + struct stream_lc3_tx lc3_tx; +#endif /* CONFIG_LIBLC3 */ +}; + +/** + * @brief Initialize TX + * + * This will initialize TX if not already initialized. This creates and starts a thread that + * will attempt to send data on all streams registered with stream_tx_register(). + */ +void stream_tx_init(void); + +/** + * @brief Register a stream for TX + * + * This will add it to the list of streams the TX thread will attempt to send on. + * + * @retval 0 on success + * @retval -EINVAL if @p bap_stream is NULL + * @retval -EINVAL if @p bap_stream.codec_cfg contains invalid values + * @retval -ENOEXEC if the LC3 encoder failed to initialize + * @retval -ENOMEM if not more streams can be registered + */ +int stream_tx_register(struct bt_bap_stream *bap_stream); + +/** + * @brief Unregister a stream for TX + * + * This will remove it to the list of streams the TX thread will attempt to send on. + * + * @retval 0 on success + * @retval -EINVAL if @p bap_stream is NULL + * @retval -EALREADY if the stream is currently not registered + */ +int stream_tx_unregister(struct bt_bap_stream *bap_stream); + +#endif /* STREAM_TX_H */ diff --git a/samples/bluetooth/beacon/boards/nrf52840dk_nrf52840.overlay b/samples/bluetooth/beacon/boards/nrf52840dk_nrf52840.overlay index be9115fc1096e..3fdcfdb1228aa 100644 --- a/samples/bluetooth/beacon/boards/nrf52840dk_nrf52840.overlay +++ b/samples/bluetooth/beacon/boards/nrf52840dk_nrf52840.overlay @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { coex_gpio: coex { compatible = "gpio-radio-coex"; grant-gpios = <&gpio1 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; diff --git a/samples/bluetooth/bluetooth.rst b/samples/bluetooth/bluetooth.rst index 0c3b7a21f2f4a..69848d183a097 100644 --- a/samples/bluetooth/bluetooth.rst +++ b/samples/bluetooth/bluetooth.rst @@ -6,7 +6,7 @@ To build any of the Bluetooth samples, follow the same steps as building any other Zephyr application. Refer to :ref:`bluetooth-dev` for more information. -Many Bluetooth samples can be run on QEMU or :ref:`native_sim ` with support for +Many Bluetooth samples can be run on QEMU or :zephyr:board:`native_sim ` with support for external Bluetooth Controllers. Refer to the :ref:`bluetooth-hw-setup` section for further details. diff --git a/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c b/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c index 00bce2ad435d2..215c1e857e627 100644 --- a/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c +++ b/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c @@ -1,7 +1,7 @@ /** @file * @brief Bluetooth Common Audio Profile (CAP) Acceptor broadcast. * - * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2024-2025 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -459,7 +459,8 @@ static int bis_sync_req_cb(struct bt_conn *conn, LOG_INF("BIS sync request received for %p: 0x%08x", recv_state, bis_sync_req[0]); - if (new_bis_sync_req != BT_BAP_BIS_SYNC_NO_PREF && POPCOUNT(new_bis_sync_req) > 1U) { + if (new_bis_sync_req != BT_BAP_BIS_SYNC_NO_PREF && + sys_count_bits(&new_bis_sync_req, sizeof(new_bis_sync_req)) > 1U) { LOG_WRN("Rejecting BIS sync request for 0x%08X as we do not support that", new_bis_sync_req); diff --git a/samples/bluetooth/central_gatt_write/Kconfig b/samples/bluetooth/central_gatt_write/Kconfig new file mode 100644 index 0000000000000..f4d630ef8a513 --- /dev/null +++ b/samples/bluetooth/central_gatt_write/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +source "samples/bluetooth/central_gatt_write/Kconfig.gatt_write" +source "Kconfig.zephyr" diff --git a/samples/bluetooth/central_gatt_write/Kconfig.gatt_write b/samples/bluetooth/central_gatt_write/Kconfig.gatt_write new file mode 100644 index 0000000000000..7e1d9db3e0cfd --- /dev/null +++ b/samples/bluetooth/central_gatt_write/Kconfig.gatt_write @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config USE_VARIABLE_LENGTH_DATA + bool "Use variable length data in GATT Write without Response" + help + Use increasing and decreasing length data in GATT Write without + Response. + +config USE_CONN_UPDATE_ITERATION_ONCE + bool "Test Connection Update" + help + Perform Connection Update for a single iteration. + +config USE_PHY_UPDATE_ITERATION_ONCE + bool "Test PHY Update" + depends on BT_USER_PHY_UPDATE + help + Perform PHY Update for a single iteration. diff --git a/samples/bluetooth/central_gatt_write/src/central_gatt_write.c b/samples/bluetooth/central_gatt_write/src/central_gatt_write.c index 28071dbc05df0..cf2d4df3814e5 100644 --- a/samples/bluetooth/central_gatt_write/src/central_gatt_write.c +++ b/samples/bluetooth/central_gatt_write/src/central_gatt_write.c @@ -16,6 +16,7 @@ extern int mtu_exchange(struct bt_conn *conn); extern int write_cmd(struct bt_conn *conn); extern struct bt_conn *conn_connected; extern uint32_t last_write_rate; +extern uint32_t *write_countdown; extern void (*start_scan_func)(void); static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, @@ -94,6 +95,13 @@ uint32_t central_gatt_write(uint32_t count) conn_connected = NULL; last_write_rate = 0U; + write_countdown = &count; + + if (count != 0U) { + printk("GATT Write countdown %u on connection.\n", count); + } else { + printk("GATT Write forever on connection.\n"); + } #if defined(CONFIG_BT_USER_PHY_UPDATE) err = bt_conn_le_set_default_phy(BT_GAP_LE_PHY_1M, BT_GAP_LE_PHY_1M); @@ -122,7 +130,14 @@ uint32_t central_gatt_write(uint32_t count) (void)write_cmd(conn); bt_conn_unref(conn); + /* Passing `0` will not use GATT Write Cmd countdown. + * Below code block will be optimized out by the linker. + */ if (count) { + if ((count % 1000U) == 0U) { + printk("GATT Write countdown %u\n", count); + } + count--; if (!count) { break; diff --git a/samples/bluetooth/central_gatt_write/src/gatt_write_common.c b/samples/bluetooth/central_gatt_write/src/gatt_write_common.c index 99d2e830aea90..3f5d3436053a9 100644 --- a/samples/bluetooth/central_gatt_write/src/gatt_write_common.c +++ b/samples/bluetooth/central_gatt_write/src/gatt_write_common.c @@ -12,11 +12,52 @@ #include #include +/* Count down number of write commands after all PHY and connection updates */ +#define COUNT_THROUGHPUT 1000U + /* Count down number of metrics intervals before performing a PHY update */ -#define PHY_UPDATE_COUNTDOWN 3U +#define PHY_UPDATE_COUNTDOWN 5U static uint32_t phy_update_countdown; + +/* Current index of the parameters array to initiate PHY Update */ static uint8_t phy_param_idx; +/* Count down number of metrics intervals before performing a param update */ +#define PARAM_UPDATE_COUNTDOWN PHY_UPDATE_COUNTDOWN +static uint32_t param_update_countdown; + +/* Current index of the parameters array to initiate Connection Update */ +static uint8_t param_update_idx; + +/* If testing PHY Update then perform one iteration of Connection Updates otherwise when testing + * Connection Updates perform 20 iterations. + */ +#define PARAM_UPDATE_ITERATION_MAX COND_CODE_1(CONFIG_USE_PHY_UPDATE_ITERATION_ONCE, (1U), (20U)) +static uint32_t param_update_iteration; + +/* Total number of Connection Updates performed + * + * Used for logging purposes only + */ +static uint32_t param_update_count; + +/* Calculate the Supervision Timeout to a Rounded up 10 ms unit + * + * Conform to required BT Specifiction defined minimum Supervision Timeout of 100 ms + */ +#define CONN_TIMEOUT(_timeout) \ + BT_GAP_US_TO_CONN_TIMEOUT(DIV_ROUND_UP(MAX(100U * USEC_PER_MSEC, (_timeout)), \ + 10U * USEC_PER_MSEC) * 10U * USEC_PER_MSEC) + +/* Relaxed number of Connection Interval to set the Supervision Timeout. + * Shall be >= 2U. + * + * Refer to BT Spec v6.1, Vol 6, Part B, Section 4.5.2 Supervision timeout + * + * `(1 + connPeripheralLatency) × connSubrateFactor × connInterval × 2` + */ +#define CONN_INTERVAL_MULTIPLIER (6U) + static void phy_update_iterate(struct bt_conn *conn) { const struct bt_conn_le_phy_param phy_param[] = { @@ -95,11 +136,16 @@ static void phy_update_iterate(struct bt_conn *conn) phy_update_countdown = PHY_UPDATE_COUNTDOWN; - phy_param_idx++; if (phy_param_idx >= ARRAY_SIZE(phy_param)) { - /* No more PHY updates, stay at the last index */ - phy_param_idx = ARRAY_SIZE(phy_param); - return; + if (IS_ENABLED(CONFIG_USE_PHY_UPDATE_ITERATION_ONCE)) { + /* No more PHY updates, stay at the last index */ + return; + } + + /* Test PHY Update not enabled, lets continue with connection update iterations + * forever. + */ + phy_param_idx = 0U; } struct bt_conn_info conn_info; @@ -132,6 +178,8 @@ static void phy_update_iterate(struct bt_conn *conn) printk("Failed to update PHY (%d).\n", err); return; } + + phy_param_idx++; } /* Interval between storing the measured write rate */ @@ -143,8 +191,16 @@ static uint32_t write_len; static uint32_t write_rate; /* Globals, reused by central_gatt_write and peripheral_gatt_write samples */ +/* Connection context used by the Write Cmd calls */ struct bt_conn *conn_connected; +/* Stores the latest calculated write rate, bits per second */ uint32_t last_write_rate; +/* Number of Write Commands used to record the latest write rate. + * Has to be large enough to be transmitting packets for METRICS_INTERVAL duration. + * Assign 0 to continue calculating latest write rate, forever or until disconnection. + */ +uint32_t *write_countdown; +/* Function pointer used to restart scanning on ACL disconnect */ void (*start_scan_func)(void); static void write_cmd_cb(struct bt_conn *conn, void *user_data) @@ -178,6 +234,122 @@ static void write_cmd_cb(struct bt_conn *conn, void *user_data) phy_update_iterate(conn); } + /* NOTE: Though minimum connection timeout permitted is 100 ms, to avoid supervision + * timeout when observer role is enabled in the sample, keep the timeout for + * smaller connection interval be large enough due to repeated overlaps by the + * scan window. + */ + const struct bt_le_conn_param update_params[] = {{ + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(51250U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(51250U), + .latency = 0, + .timeout = CONN_TIMEOUT(51250U * CONN_INTERVAL_MULTIPLIER), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(50000U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(50000U), + .latency = 0, + .timeout = CONN_TIMEOUT(50000U * CONN_INTERVAL_MULTIPLIER), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(8750U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(8750U), + .latency = 0, + .timeout = CONN_TIMEOUT(720000U), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(7500U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(7500U), + .latency = 0, + .timeout = CONN_TIMEOUT(720000U), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(50000U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(50000U), + .latency = 0, + .timeout = CONN_TIMEOUT(50000U * CONN_INTERVAL_MULTIPLIER), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(51250U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(51250U), + .latency = 0, + .timeout = CONN_TIMEOUT(51250U * CONN_INTERVAL_MULTIPLIER), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(7500U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(7500U), + .latency = 0, + .timeout = CONN_TIMEOUT(720000U), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(8750U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(8750U), + .latency = 0, + .timeout = CONN_TIMEOUT(720000U), + }, { + .interval_min = BT_GAP_US_TO_CONN_INTERVAL(50000U), + .interval_max = BT_GAP_US_TO_CONN_INTERVAL(50000U), + .latency = 0, + .timeout = CONN_TIMEOUT(50000U * CONN_INTERVAL_MULTIPLIER), + }, + }; + int err; + + if ((param_update_countdown--) != 0U) { + return; + } + + param_update_countdown = PARAM_UPDATE_COUNTDOWN; + + if (param_update_idx >= ARRAY_SIZE(update_params)) { + if (IS_ENABLED(CONFIG_USE_CONN_UPDATE_ITERATION_ONCE) && + (--param_update_iteration == 0U)) { + /* No more conn updates, stay at the last index */ + param_update_iteration = 1U; + + /* As this function is re-used by the peripheral; on target, users + * can enable simultaneous (background) scanning but by default do + * not have the scanning enabled. + * If both Central plus Peripheral role is built together then + * Peripheral is scanning (on 1M and Coded PHY windows) while there + * is simultaneous Write Commands. + * + * We stop scanning if we are stopping after one iteration of + * Connection Updates. + */ + if (IS_ENABLED(CONFIG_BT_OBSERVER) && + !IS_ENABLED(CONFIG_USE_PHY_UPDATE_ITERATION_ONCE)) { + /* Stop scanning. We will keep calling on every complete + * countdown. This is ok, for implementation simplicity, + * i.e. not adding addition design. + */ + err = bt_le_scan_stop(); + if (err != 0) { + printk("Failed to stop scanning (%d).\n", err); + } + + printk("Scanning stopped.\n"); + + *write_countdown = COUNT_THROUGHPUT; + } + + return; + } + + /* Test Connection Update not enabled, lets continue with connection update + * iterations forever. + */ + param_update_idx = 0U; + } + + param_update_count++; + + printk("Parameter Update Count: %u. %u: 0x%x 0x%x %u %u\n", param_update_count, + param_update_idx, + update_params[param_update_idx].interval_min, + update_params[param_update_idx].interval_max, + update_params[param_update_idx].latency, + update_params[param_update_idx].timeout); + err = bt_conn_le_param_update(conn, &update_params[param_update_idx]); + if (err != 0) { + printk("Parameter update failed (err %d)\n", err); + } + + param_update_idx++; + } else { uint16_t len; @@ -226,7 +398,7 @@ static void connected(struct bt_conn *conn, uint8_t conn_err) bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr)); if (conn_err) { - printk("%s: Failed to connect to %s (%u)\n", __func__, addr, + printk("%s: Failed to connect to %s (0x%02x)\n", __func__, addr, conn_err); return; } @@ -256,6 +428,17 @@ static void connected(struct bt_conn *conn, uint8_t conn_err) phy_update_countdown = PHY_UPDATE_COUNTDOWN; phy_param_idx = 0U; } + + /* Every 1 second the acknowledged total GATT Write without Response data size is used for + * the throughput calculation. + * PHY update is performed in reference to this calculation interval, and connection update + * is offset by 1 of this interval so that connection update is initiated one such interval + * after PHY update was requested. + */ + param_update_countdown = PARAM_UPDATE_COUNTDOWN + 1U; + param_update_iteration = PARAM_UPDATE_ITERATION_MAX; + param_update_count = 0U; + param_update_idx = 0U; } static void disconnected(struct bt_conn *conn, uint8_t reason) @@ -272,7 +455,7 @@ static void disconnected(struct bt_conn *conn, uint8_t reason) return; } - printk("%s: %s role %u, reason %u %s\n", __func__, addr, conn_info.role, + printk("%s: %s role %u, reason 0x%02x %s\n", __func__, addr, conn_info.role, reason, bt_hci_err_to_str(reason)); conn_connected = NULL; @@ -366,28 +549,28 @@ int write_cmd(struct bt_conn *conn) data_len_max = BT_ATT_MAX_ATTRIBUTE_LEN; } -#if TEST_FRAGMENTATION_WITH_VARIABLE_LENGTH_DATA - /* Use incremental length data for every write command */ - /* TODO: Include test case in BabbleSim tests */ - static bool decrement; - - if (decrement) { - data_len--; - if (data_len <= 1) { - data_len = 1; - decrement = false; + if (IS_ENABLED(CONFIG_USE_VARIABLE_LENGTH_DATA)) { + /* Use incremental length data for every write command */ + /* TODO: Include test case in BabbleSim tests */ + static bool decrement; + + if (decrement) { + data_len--; + if (data_len <= 1) { + data_len = 1; + decrement = false; + } + } else { + data_len++; + if (data_len >= data_len_max) { + data_len = data_len_max; + decrement = true; + } } } else { - data_len++; - if (data_len >= data_len_max) { - data_len = data_len_max; - decrement = true; - } + /* Use fixed length data for every write command */ + data_len = data_len_max; } -#else - /* Use fixed length data for every write command */ - data_len = data_len_max; -#endif /* Pass the 16-bit data length value (instead of reference) in * user_data so that unique value is pass for each write callback. diff --git a/samples/bluetooth/channel_sounding/src/connected_cs_initiator.c b/samples/bluetooth/channel_sounding/src/connected_cs_initiator.c index 98ddbcceede82..0cfae46926ad7 100644 --- a/samples/bluetooth/channel_sounding/src/connected_cs_initiator.c +++ b/samples/bluetooth/channel_sounding/src/connected_cs_initiator.c @@ -29,6 +29,7 @@ static ssize_t on_attr_write_cb(struct bt_conn *conn, const struct bt_gatt_attr static struct bt_conn *connection; static uint8_t n_ap; static uint8_t latest_num_steps_reported; +static uint16_t latest_procedure_counter = UINT16_MAX; static uint16_t latest_step_data_len; static uint8_t latest_local_steps[STEP_DATA_BUF_LEN]; static uint8_t latest_peer_steps[STEP_DATA_BUF_LEN]; @@ -72,6 +73,13 @@ static void subevent_result_cb(struct bt_conn *conn, struct bt_conn_le_cs_subeve latest_num_steps_reported = result->header.num_steps_reported; n_ap = result->header.num_antenna_paths; + if (result->header.procedure_counter == latest_procedure_counter) { + printk("The sample does not handle CS procedures with multiple CS subevents.\n"); + latest_procedure_counter = result->header.procedure_counter; + return; + } + latest_procedure_counter = result->header.procedure_counter; + if (result->step_data_buf) { if (result->step_data_buf->len <= STEP_DATA_BUF_LEN) { memcpy(latest_local_steps, result->step_data_buf->data, @@ -241,6 +249,47 @@ static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, } } +struct bt_le_cs_create_config_params get_cs_config_params(void) +{ + /* Create config parameters that result in a limited number of CS steps per CS procedure. + * This is achieved by setting channel_map_repetition = 1 and only enabling a limited set + * of channels in the channel_map. This is required due to a limitation in the sample: + * The reflector uses a single GATT write operation to transfer all of the step data + * from one CS procedure to the initiator. This limits the amount of CS step data per + * CS procedure that will allow the sample to function to 512 bytes. + * This method for limiting the amount of CS steps per CS procedure is chosen because it + * will result in the same number of CS steps regardless of controller capabilities. + * Other possible methods such as limiting the max_procedure_len in the procedure params + * would yield different number of CS steps per CS procedure depending on the + * timing parameters supported by the local and peer controller. + */ + struct bt_le_cs_create_config_params config_params = { + .id = CS_CONFIG_ID, + .mode = BT_CONN_LE_CS_MAIN_MODE_2_SUB_MODE_1, + .min_main_mode_steps = 2, + .max_main_mode_steps = 10, + .main_mode_repetition = 0, + .mode_0_steps = NUM_MODE_0_STEPS, + .role = BT_CONN_LE_CS_ROLE_INITIATOR, + .rtt_type = BT_CONN_LE_CS_RTT_TYPE_AA_ONLY, + .cs_sync_phy = BT_CONN_LE_CS_SYNC_1M_PHY, + .channel_map_repetition = 1, + .channel_selection_type = BT_CONN_LE_CS_CHSEL_TYPE_3B, + .ch3c_shape = BT_CONN_LE_CS_CH3C_SHAPE_HAT, + .ch3c_jump = 2, + }; + + memset(config_params.channel_map, 0, 10); + /* Enable 32 consecutive CS channels. + * Start at i = 26 since channels 23, 24 and 25 are disallowed by spec. + */ + for (uint8_t i = 26; i < 62; i++) { + BT_LE_CS_CHANNEL_BIT_SET_VAL(config_params.channel_map, i, 1); + } + + return config_params; +} + BT_CONN_CB_DEFINE(conn_cb) = { .connected = connected_cb, .disconnected = disconnected_cb, @@ -307,26 +356,11 @@ int main(void) k_sem_take(&sem_remote_capabilities_obtained, K_FOREVER); - struct bt_le_cs_create_config_params config_params = { - .id = CS_CONFIG_ID, - .mode = BT_CONN_LE_CS_MAIN_MODE_2_SUB_MODE_1, - .min_main_mode_steps = 2, - .max_main_mode_steps = 10, - .main_mode_repetition = 0, - .mode_0_steps = NUM_MODE_0_STEPS, - .role = BT_CONN_LE_CS_ROLE_INITIATOR, - .rtt_type = BT_CONN_LE_CS_RTT_TYPE_AA_ONLY, - .cs_sync_phy = BT_CONN_LE_CS_SYNC_1M_PHY, - .channel_map_repetition = 1, - .channel_selection_type = BT_CONN_LE_CS_CHSEL_TYPE_3B, - .ch3c_shape = BT_CONN_LE_CS_CH3C_SHAPE_HAT, - .ch3c_jump = 2, - }; - - bt_le_cs_set_valid_chmap_bits(config_params.channel_map); + struct bt_le_cs_create_config_params config_params = get_cs_config_params(); err = bt_le_cs_create_config(connection, &config_params, BT_LE_CS_CREATE_CONFIG_CONTEXT_LOCAL_AND_REMOTE); + if (err) { printk("Failed to create CS config (err %d)\n", err); return 0; @@ -341,15 +375,20 @@ int main(void) } k_sem_take(&sem_cs_security_enabled, K_FOREVER); - const struct bt_le_cs_set_procedure_parameters_param procedure_params = { .config_id = CS_CONFIG_ID, - .max_procedure_len = 12, + .max_procedure_len = 0xffff, .min_procedure_interval = 100, .max_procedure_interval = 100, .max_procedure_count = 0, - .min_subevent_len = 6750, - .max_subevent_len = 6750, + /* Use a relatively large subevent_len to make sure the CS procedure + * will terminate due to running out of unused channels in the channel map + * (and channel map repetitions) in the first CS subevent of the CS procedure. + * This will limit the number of CS subevents per CS procedure to 1, which is + * required by the design of the sample. + */ + .min_subevent_len = 50000, + .max_subevent_len = 50000, .tone_antenna_config_selection = BT_LE_CS_TONE_ANTENNA_CONFIGURATION_A1_B1, .phy = BT_LE_CS_PROCEDURE_PHY_1M, .tx_power_delta = 0x80, diff --git a/samples/bluetooth/channel_sounding/src/connected_cs_reflector.c b/samples/bluetooth/channel_sounding/src/connected_cs_reflector.c index 404ee1ad4e347..b50aa728d5f80 100644 --- a/samples/bluetooth/channel_sounding/src/connected_cs_reflector.c +++ b/samples/bluetooth/channel_sounding/src/connected_cs_reflector.c @@ -25,6 +25,7 @@ static K_SEM_DEFINE(sem_written, 0, 1); static uint16_t step_data_attr_handle; static struct bt_conn *connection; +static uint16_t latest_procedure_counter = UINT16_MAX; static uint8_t latest_local_steps[STEP_DATA_BUF_LEN]; static const char sample_str[] = "CS Sample"; @@ -34,6 +35,13 @@ static const struct bt_data ad[] = { static void subevent_result_cb(struct bt_conn *conn, struct bt_conn_le_cs_subevent_result *result) { + if (result->header.procedure_counter == latest_procedure_counter) { + printk("The sample does not handle CS procedures with multiple CS subevents.\n"); + latest_procedure_counter = result->header.procedure_counter; + return; + } + latest_procedure_counter = result->header.procedure_counter; + if (result->step_data_buf) { if (result->step_data_buf->len <= STEP_DATA_BUF_LEN) { memcpy(latest_local_steps, result->step_data_buf->data, diff --git a/samples/bluetooth/direct_adv/sample.yaml b/samples/bluetooth/direct_adv/sample.yaml index c6c2463203e03..0987aac4750c1 100644 --- a/samples/bluetooth/direct_adv/sample.yaml +++ b/samples/bluetooth/direct_adv/sample.yaml @@ -1,5 +1,5 @@ sample: - name: Bluetooh Direct Advertising + name: Bluetooth Direct Advertising tests: sample.bluetooth.direct_adv: harness: bluetooth diff --git a/samples/bluetooth/direction_finding_central/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/bluetooth/direction_finding_central/boards/nrf5340dk_nrf5340_cpuapp.overlay index f0a45c81f9613..5b12a99271280 100644 --- a/samples/bluetooth/direction_finding_central/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/bluetooth/direction_finding_central/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -4,17 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* Enable pin forwarding to network core. The selected pins will be used by - * Radio Direction Finding Extension for antenna switching purposes. - * - * Note: Pay attention to assign the same GPIO pins as those provided in - * network core DTS overlay. - */ +/* Enable pin forwarding to network core. The selected pins will be used by + * Radio Direction Finding Extension for antenna switching purposes. + * + * Note: Pay attention to assign the same GPIO pins as those provided in + * network core DTS overlay. + */ &gpio_fwd { dfe-gpio-if { gpios = <&gpio0 4 0>, <&gpio0 5 0>, <&gpio0 6 0>, <&gpio0 7 0>; - }; + }; }; diff --git a/samples/bluetooth/direction_finding_connectionless_rx/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/bluetooth/direction_finding_connectionless_rx/boards/nrf5340dk_nrf5340_cpuapp.overlay index f0a45c81f9613..5b12a99271280 100644 --- a/samples/bluetooth/direction_finding_connectionless_rx/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/bluetooth/direction_finding_connectionless_rx/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -4,17 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* Enable pin forwarding to network core. The selected pins will be used by - * Radio Direction Finding Extension for antenna switching purposes. - * - * Note: Pay attention to assign the same GPIO pins as those provided in - * network core DTS overlay. - */ +/* Enable pin forwarding to network core. The selected pins will be used by + * Radio Direction Finding Extension for antenna switching purposes. + * + * Note: Pay attention to assign the same GPIO pins as those provided in + * network core DTS overlay. + */ &gpio_fwd { dfe-gpio-if { gpios = <&gpio0 4 0>, <&gpio0 5 0>, <&gpio0 6 0>, <&gpio0 7 0>; - }; + }; }; diff --git a/samples/bluetooth/direction_finding_connectionless_tx/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/bluetooth/direction_finding_connectionless_tx/boards/nrf5340dk_nrf5340_cpuapp.overlay index f0a45c81f9613..5b12a99271280 100644 --- a/samples/bluetooth/direction_finding_connectionless_tx/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/bluetooth/direction_finding_connectionless_tx/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -4,17 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* Enable pin forwarding to network core. The selected pins will be used by - * Radio Direction Finding Extension for antenna switching purposes. - * - * Note: Pay attention to assign the same GPIO pins as those provided in - * network core DTS overlay. - */ +/* Enable pin forwarding to network core. The selected pins will be used by + * Radio Direction Finding Extension for antenna switching purposes. + * + * Note: Pay attention to assign the same GPIO pins as those provided in + * network core DTS overlay. + */ &gpio_fwd { dfe-gpio-if { gpios = <&gpio0 4 0>, <&gpio0 5 0>, <&gpio0 6 0>, <&gpio0 7 0>; - }; + }; }; diff --git a/samples/bluetooth/direction_finding_peripheral/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/bluetooth/direction_finding_peripheral/boards/nrf5340dk_nrf5340_cpuapp.overlay index f0a45c81f9613..5b12a99271280 100644 --- a/samples/bluetooth/direction_finding_peripheral/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/bluetooth/direction_finding_peripheral/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -4,17 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* Enable pin forwarding to network core. The selected pins will be used by - * Radio Direction Finding Extension for antenna switching purposes. - * - * Note: Pay attention to assign the same GPIO pins as those provided in - * network core DTS overlay. - */ +/* Enable pin forwarding to network core. The selected pins will be used by + * Radio Direction Finding Extension for antenna switching purposes. + * + * Note: Pay attention to assign the same GPIO pins as those provided in + * network core DTS overlay. + */ &gpio_fwd { dfe-gpio-if { gpios = <&gpio0 4 0>, <&gpio0 5 0>, <&gpio0 6 0>, <&gpio0 7 0>; - }; + }; }; diff --git a/samples/bluetooth/hci_ipc/boards/nrf5340_audio_dk_nrf5340_cpunet_nrf21540_ek.overlay b/samples/bluetooth/hci_ipc/boards/nrf5340_audio_dk_nrf5340_cpunet_nrf21540_ek.overlay index 82e6b8cf84856..bf1dc14b772b4 100644 --- a/samples/bluetooth/hci_ipc/boards/nrf5340_audio_dk_nrf5340_cpunet_nrf21540_ek.overlay +++ b/samples/bluetooth/hci_ipc/boards/nrf5340_audio_dk_nrf5340_cpunet_nrf21540_ek.overlay @@ -1,11 +1,11 @@ / { nrf_radio_fem: nrf21540_fem { - compatible = "nordic,nrf21540-fem"; - tx-en-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 */ - rx-en-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; /* D3 */ - pdn-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ - ant-sel-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 */ - mode-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; /* D2 */ + compatible = "nordic,nrf21540-fem"; + tx-en-gpios = <&arduino_header 11 GPIO_ACTIVE_HIGH>; /* D5 */ + rx-en-gpios = <&arduino_header 9 GPIO_ACTIVE_HIGH>; /* D3 */ + pdn-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */ + ant-sel-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 */ + mode-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; /* D2 */ supply-voltage-mv = <3000>; }; }; diff --git a/samples/bluetooth/hci_uart/README.rst b/samples/bluetooth/hci_uart/README.rst index 2260c7e0d29b6..4511cff98e4dd 100644 --- a/samples/bluetooth/hci_uart/README.rst +++ b/samples/bluetooth/hci_uart/README.rst @@ -59,7 +59,7 @@ For example, to build for the nRF52832 Development Kit: Using the controller with QEMU or native_sim ============================================ -In order to use the HCI UART controller with QEMU or :ref:`native_sim ` you will need +In order to use the HCI UART controller with QEMU or :zephyr:board:`native_sim ` you will need to attach it to the Linux Host first. To do so simply build the sample and connect the UART to the Linux machine, and then attach it with this command: diff --git a/samples/bluetooth/hci_uart/boards/esp32_devkitc_procpu.overlay b/samples/bluetooth/hci_uart/boards/esp32_devkitc_procpu.overlay index c962a4ad4b44c..c7498e89786b4 100644 --- a/samples/bluetooth/hci_uart/boards/esp32_devkitc_procpu.overlay +++ b/samples/bluetooth/hci_uart/boards/esp32_devkitc_procpu.overlay @@ -23,7 +23,6 @@ bias-pull-up; }; }; - }; &uart1 { diff --git a/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833.overlay b/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833.overlay index 1dd3aea1b3ac9..cdb18400cb05e 100644 --- a/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833.overlay +++ b/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &uart0 { +&uart0 { compatible = "nordic,nrf-uarte"; current-speed = <1000000>; status = "okay"; diff --git a/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833_df.overlay b/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833_df.overlay index 50d31f0f1312b..5bfcee4c10f63 100644 --- a/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833_df.overlay +++ b/samples/bluetooth/hci_uart/boards/nrf52833dk_nrf52833_df.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &uart0 { +&uart0 { compatible = "nordic,nrf-uarte"; current-speed = <1000000>; status = "okay"; diff --git a/samples/bluetooth/hci_uart/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay b/samples/bluetooth/hci_uart/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay index a8ed2063e9d82..fd0b63651c624 100644 --- a/samples/bluetooth/hci_uart/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay +++ b/samples/bluetooth/hci_uart/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay @@ -7,17 +7,17 @@ nrf21540-gpio-if { gpios = <&arduino_header 11 0>, /* tx-en-gpios */ - <&arduino_header 9 0>, /* rx-en-gpios */ + <&arduino_header 9 0>, /* rx-en-gpios */ <&arduino_header 15 0>, /* pdn-gpios */ <&arduino_header 10 0>, /* ant-sel-gpios */ - <&arduino_header 8 0>; /* mode-gpios */ + <&arduino_header 8 0>; /* mode-gpios */ }; nrf21540-spi-if { gpios = <&arduino_header 16 0>, /* cs-gpios */ - <&gpio0 8 0>, /* SPIM_SCK */ - <&gpio0 10 0>, /* SPIM_MISO */ - <&gpio0 9 0>; /* SPIM_MOSI */ + <&gpio0 8 0>, /* SPIM_SCK */ + <&gpio0 10 0>, /* SPIM_MISO */ + <&gpio0 9 0>; /* SPIM_MOSI */ }; }; }; diff --git a/samples/bluetooth/hci_uart/boards/nrf5340dk_nrf5340_cpunet_df.overlay b/samples/bluetooth/hci_uart/boards/nrf5340dk_nrf5340_cpunet_df.overlay index fdef6321f72c9..4d7ffd859c680 100644 --- a/samples/bluetooth/hci_uart/boards/nrf5340dk_nrf5340_cpunet_df.overlay +++ b/samples/bluetooth/hci_uart/boards/nrf5340dk_nrf5340_cpunet_df.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &uart0 { +&uart0 { compatible = "nordic,nrf-uarte"; current-speed = <1000000>; status = "okay"; diff --git a/samples/bluetooth/hci_uart/boards/nrf9160dk_nrf52840.overlay b/samples/bluetooth/hci_uart/boards/nrf9160dk_nrf52840.overlay index 8ec74170f94eb..24e85e9726863 100644 --- a/samples/bluetooth/hci_uart/boards/nrf9160dk_nrf52840.overlay +++ b/samples/bluetooth/hci_uart/boards/nrf9160dk_nrf52840.overlay @@ -15,6 +15,6 @@ / { chosen { - zephyr,bt-c2h-uart=&uart1; + zephyr,bt-c2h-uart = &uart1; }; }; diff --git a/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp.overlay b/samples/bluetooth/hci_uart/boards/panb611evb_nrf54l15_cpuapp.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp.overlay rename to samples/bluetooth/hci_uart/boards/panb611evb_nrf54l15_cpuapp.overlay diff --git a/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp_df.overlay b/samples/bluetooth/hci_uart/boards/panb611evb_nrf54l15_cpuapp_df.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp_df.overlay rename to samples/bluetooth/hci_uart/boards/panb611evb_nrf54l15_cpuapp_df.overlay diff --git a/samples/bluetooth/hci_uart/boards/yd_esp32_procpu.overlay b/samples/bluetooth/hci_uart/boards/yd_esp32_procpu.overlay index c962a4ad4b44c..c7498e89786b4 100644 --- a/samples/bluetooth/hci_uart/boards/yd_esp32_procpu.overlay +++ b/samples/bluetooth/hci_uart/boards/yd_esp32_procpu.overlay @@ -23,7 +23,6 @@ bias-pull-up; }; }; - }; &uart1 { diff --git a/samples/bluetooth/hci_uart_3wire/README.rst b/samples/bluetooth/hci_uart_3wire/README.rst index b846c9892fd8f..5d6bff699a4a6 100644 --- a/samples/bluetooth/hci_uart_3wire/README.rst +++ b/samples/bluetooth/hci_uart_3wire/README.rst @@ -59,7 +59,7 @@ For example, to build for the nRF52840 Development Kit: Using the controller with QEMU or native_sim ============================================ -In order to use the HCI UART H:5 controller with QEMU or :ref:`native_sim ` you will +In order to use the HCI UART H:5 controller with QEMU or :zephyr:board:`native_sim ` you will need to attach it to the Linux Host first. To do so simply build the sample and connect the UART to the Linux machine, and then attach it with this command: diff --git a/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833.overlay b/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833.overlay index 4763dc348cc99..cdcbd872bd064 100644 --- a/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833.overlay +++ b/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &uart0 { +&uart0 { compatible = "nordic,nrf-uarte"; current-speed = <1000000>; status = "okay"; diff --git a/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833_df.overlay b/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833_df.overlay index 5bfb3a2a4b1ab..2b42b6424dbc7 100644 --- a/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833_df.overlay +++ b/samples/bluetooth/hci_uart_3wire/boards/nrf52833dk_nrf52833_df.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &uart0 { +&uart0 { compatible = "nordic,nrf-uarte"; current-speed = <1000000>; status = "okay"; diff --git a/samples/bluetooth/hci_uart_3wire/boards/nrf5340dk_nrf5340_cpunet_df.overlay b/samples/bluetooth/hci_uart_3wire/boards/nrf5340dk_nrf5340_cpunet_df.overlay index b065708f0b6bc..65014cb53bed8 100644 --- a/samples/bluetooth/hci_uart_3wire/boards/nrf5340dk_nrf5340_cpunet_df.overlay +++ b/samples/bluetooth/hci_uart_3wire/boards/nrf5340dk_nrf5340_cpunet_df.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &uart0 { +&uart0 { compatible = "nordic,nrf-uarte"; current-speed = <1000000>; status = "okay"; diff --git a/samples/bluetooth/hci_uart_3wire/boards/nrf9160dk_nrf52840.overlay b/samples/bluetooth/hci_uart_3wire/boards/nrf9160dk_nrf52840.overlay index b8ad454a58a76..2deb9bc9bb795 100644 --- a/samples/bluetooth/hci_uart_3wire/boards/nrf9160dk_nrf52840.overlay +++ b/samples/bluetooth/hci_uart_3wire/boards/nrf9160dk_nrf52840.overlay @@ -14,6 +14,6 @@ / { chosen { - zephyr,bt-c2h-uart=&uart1; + zephyr,bt-c2h-uart = &uart1; }; }; diff --git a/samples/bluetooth/hci_uart_async/README.rst b/samples/bluetooth/hci_uart_async/README.rst index 7787741683302..13143399fa46a 100644 --- a/samples/bluetooth/hci_uart_async/README.rst +++ b/samples/bluetooth/hci_uart_async/README.rst @@ -59,7 +59,7 @@ For example, to build for the nRF52832 Development Kit: Using the controller with QEMU or native_sim ============================================ -In order to use the HCI UART controller with QEMU or :ref:`native_sim ` you will need +In order to use the HCI UART controller with QEMU or :zephyr:board:`native_sim ` you will need to attach it to the Linux Host first. To do so simply build the sample and connect the UART to the Linux machine, and then attach it with this command: diff --git a/samples/bluetooth/hci_usb/prj.conf b/samples/bluetooth/hci_usb/prj.conf index f3ee01fd7e4cf..0415cb8f63d48 100644 --- a/samples/bluetooth/hci_usb/prj.conf +++ b/samples/bluetooth/hci_usb/prj.conf @@ -5,6 +5,7 @@ CONFIG_CONSOLE=n CONFIG_UART_CONSOLE=n CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_SAMPLE_USBD_PID=0x000B CONFIG_SAMPLE_USBD_PRODUCT="Zephyr USBD BT HCI" CONFIG_USBD_BT_HCI=y diff --git a/samples/bluetooth/observer/README.rst b/samples/bluetooth/observer/README.rst index 6ef62f3870eb5..32b4a0d9eac45 100644 --- a/samples/bluetooth/observer/README.rst +++ b/samples/bluetooth/observer/README.rst @@ -16,6 +16,23 @@ If the used Bluetooth Low Energy Controller supports Extended Scanning, you may enable :kconfig:option:`CONFIG_BT_EXT_ADV` in the project configuration file. Refer to the project configuration file for further details. +Building Extended Scanning support for BBC Micro Bit board +********************************************************** + +.. code-block:: console + + west build -b bbc_microbit . -- -DCONF_FILE='prj_extended.conf' -DEXTRA_CONF_FILE='overlay_bbc_microbit-bt_ll_sw_split.conf' + +Thread Analysis for BBC Micro Bit board +*************************************** + +Due to resource constraints on the BBC Micro Bit board, thread analysis can be enabled to profile +the RAM usage and thread stack sizes be updated to successfully build and run the sample. + +.. code-block:: console + + west build -b bbc_microbit . -- -DCONF_FILE='prj_extended.conf' -DEXTRA_CONF_FILE='debug.conf;overlay_bbc_microbit-bt_ll_sw_split.conf' + Requirements ************ diff --git a/samples/bluetooth/observer/debug.conf b/samples/bluetooth/observer/debug.conf new file mode 100644 index 0000000000000..11690a66f19bf --- /dev/null +++ b/samples/bluetooth/observer/debug.conf @@ -0,0 +1,5 @@ +# Enable thread analysis +CONFIG_THREAD_ANALYZER=y +CONFIG_THREAD_ANALYZER_AUTO=y +CONFIG_THREAD_ANALYZER_AUTO_INTERVAL=5 +CONFIG_THREAD_NAME=y diff --git a/samples/bluetooth/observer/dts/arm/nordic/override.dtsi b/samples/bluetooth/observer/dts/arm/nordic/override.dtsi new file mode 100644 index 0000000000000..882f70755d59d --- /dev/null +++ b/samples/bluetooth/observer/dts/arm/nordic/override.dtsi @@ -0,0 +1,7 @@ +/* Keep default IRQ priority low for peripherals to reduce Radio ISR latency. + * ARM Cortex-M4 lowest priority value of 5, i.e. considering Zephyr reserved 2 + * levels for Exceptions and ZLI (if enabled). + * ARM Cortex-M0 lowest priority value of 3, i.e. we use it as Zephyr has no + * support for ZLI on Cortex-M0. + */ +#define NRF_DEFAULT_IRQ_PRIORITY 3 diff --git a/samples/bluetooth/observer/overlay_bbc_microbit-bt_ll_sw_split.conf b/samples/bluetooth/observer/overlay_bbc_microbit-bt_ll_sw_split.conf new file mode 100644 index 0000000000000..1df1d076ef5fb --- /dev/null +++ b/samples/bluetooth/observer/overlay_bbc_microbit-bt_ll_sw_split.conf @@ -0,0 +1,53 @@ +# Adjust Stack Sizes for reduce RAM usage +CONFIG_MAIN_STACK_SIZE=1024 +CONFIG_IDLE_STACK_SIZE=128 +CONFIG_ISR_STACK_SIZE=1024 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=1024 + +# Enable Extended Scanning +# CONFIG_BT_EXT_ADV=y + +# Set maximum scan data length for Extended Scanning +CONFIG_BT_EXT_SCAN_BUF_SIZE=192 + +# Zephyr Bluetooth LE Controller needs 16 event buffers to generate Extended +# Advertising Report for receiving the complete 1650 bytes of data. +# Use 4 to be able to receive a minimal extended advertising with chains. +CONFIG_BT_BUF_EVT_RX_COUNT=4 + +# Use Zephyr Bluetooth Low Energy Controller implementation +CONFIG_BT_LL_SW_SPLIT=y + +# Set maximum scan data length for Extended Scanning in Bluetooth LE Controller. +CONFIG_BT_CTLR_SCAN_DATA_LEN_MAX=192 + +# Increase Zephyr Bluetooth LE Controller Rx buffer to receive complete chain +# of PDUs. Need 9 for maximum of 1650 bytes, but we use 3 as minimum to receive +# at least a primary PDU, an auxiliary PDU and a chain PDU. +CONFIG_BT_CTLR_RX_BUFFERS=3 + +# Enable advanced features +CONFIG_BT_CTLR_ADVANCED_FEATURES=y + +# Adjust execution context priorities to achieve lower Radio ISR latencies +CONFIG_BT_CTLR_LLL_PRIO=0 +CONFIG_BT_CTLR_ULL_HIGH_PRIO=1 +CONFIG_BT_CTLR_ULL_LOW_PRIO=1 + +# Use just-in-time collision resolution in ticker and LLL pipeline +CONFIG_BT_CTLR_LOW_LAT=n +CONFIG_BT_CTLR_LOW_LAT_ULL_DONE=n +CONFIG_BT_TICKER_LOW_LAT=n + +# Increase the below to receive interleaved advertising chains +CONFIG_BT_CTLR_SCAN_AUX_SET=3 +CONFIG_BT_CTLR_LOW_LAT_ULL=y +# CONFIG_BT_CTLR_SCAN_AUX_USE_CHAINS=y +# CONFIG_BT_CTLR_SCAN_AUX_CHAIN_COUNT=3 + +# Use unreserved timespace scanning +CONFIG_BT_CTLR_SCAN_UNRESERVED=y + +# Code size reduction +CONFIG_ISR_TABLES_LOCAL_DECLARATION=y +CONFIG_LTO=y diff --git a/samples/bluetooth/observer/sample.yaml b/samples/bluetooth/observer/sample.yaml index b60ccc9fe8ed3..c568dc74e7f8c 100644 --- a/samples/bluetooth/observer/sample.yaml +++ b/samples/bluetooth/observer/sample.yaml @@ -3,20 +3,33 @@ sample: tests: sample.bluetooth.observer: harness: bluetooth + tags: bluetooth platform_allow: - qemu_cortex_m3 - qemu_x86 - nrf52840dk/nrf52840 integration_platforms: - qemu_cortex_m3 - tags: bluetooth + - nrf52840dk/nrf52840 sample.bluetooth.observer.extended: harness: bluetooth - extra_args: CONF_FILE="prj_extended.conf" + tags: bluetooth + extra_args: + - CONF_FILE="prj_extended.conf" platform_allow: - qemu_cortex_m3 - qemu_x86 - nrf52840dk/nrf52840 - tags: bluetooth integration_platforms: - qemu_cortex_m3 + - nrf52840dk/nrf52840 + sample.bluetooth.observer.extended.bbc_microbit.bt_ll_sw_split: + harness: bluetooth + tags: bluetooth + extra_args: + - CONF_FILE="prj_extended.conf" + - EXTRA_CONF_FILE="debug.conf;overlay_bbc_microbit-bt_ll_sw_split.conf" + platform_allow: + - bbc_microbit + integration_platforms: + - bbc_microbit diff --git a/samples/bluetooth/observer/src/observer.c b/samples/bluetooth/observer/src/observer.c index 12a6c5781b320..ac9a857e1ef7a 100644 --- a/samples/bluetooth/observer/src/observer.c +++ b/samples/bluetooth/observer/src/observer.c @@ -88,10 +88,11 @@ static struct bt_le_scan_cb scan_callbacks = { int observer_start(void) { + /* 30 ms continuous active scanning with duplicate filtering. */ struct bt_le_scan_param scan_param = { - .type = BT_LE_SCAN_TYPE_PASSIVE, + .type = BT_LE_SCAN_TYPE_ACTIVE, .options = BT_LE_SCAN_OPT_FILTER_DUPLICATE, - .interval = BT_GAP_SCAN_FAST_INTERVAL, + .interval = BT_GAP_SCAN_FAST_INTERVAL_MIN, .window = BT_GAP_SCAN_FAST_WINDOW, }; int err; diff --git a/samples/bluetooth/periodic_adv_rsp/src/main.c b/samples/bluetooth/periodic_adv_rsp/src/main.c index da665cde34a67..ec34e4e0686d5 100644 --- a/samples/bluetooth/periodic_adv_rsp/src/main.c +++ b/samples/bluetooth/periodic_adv_rsp/src/main.c @@ -377,7 +377,7 @@ int main(void) printk("PAwR config written to sync %d, disconnecting\n", num_synced - 1); disconnect: - /* Adding delay (2ms * interval value, using 2ms intead of the 1.25ms + /* Adding delay (2ms * interval value, using 2ms instead of the 1.25ms * used by controller) to ensure sync is established before * disconnection. */ diff --git a/samples/bluetooth/peripheral_accept_list/sample.yaml b/samples/bluetooth/peripheral_accept_list/sample.yaml index 2aa0f00c49867..50985ad99e6a6 100644 --- a/samples/bluetooth/peripheral_accept_list/sample.yaml +++ b/samples/bluetooth/peripheral_accept_list/sample.yaml @@ -1,5 +1,5 @@ sample: - name: Bluetooh Peripheral Accept List + name: Bluetooth Peripheral Accept List tests: sample.bluetooth.peripheral_accept_list: harness: bluetooth diff --git a/samples/bluetooth/peripheral_gatt_write/Kconfig b/samples/bluetooth/peripheral_gatt_write/Kconfig new file mode 100644 index 0000000000000..f4d630ef8a513 --- /dev/null +++ b/samples/bluetooth/peripheral_gatt_write/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +source "samples/bluetooth/central_gatt_write/Kconfig.gatt_write" +source "Kconfig.zephyr" diff --git a/samples/bluetooth/peripheral_gatt_write/src/peripheral_gatt_write.c b/samples/bluetooth/peripheral_gatt_write/src/peripheral_gatt_write.c index 0823d90b27741..8fb2f8392fafc 100644 --- a/samples/bluetooth/peripheral_gatt_write/src/peripheral_gatt_write.c +++ b/samples/bluetooth/peripheral_gatt_write/src/peripheral_gatt_write.c @@ -16,6 +16,7 @@ extern int mtu_exchange(struct bt_conn *conn); extern int write_cmd(struct bt_conn *conn); extern struct bt_conn *conn_connected; extern uint32_t last_write_rate; +extern uint32_t *write_countdown; static const struct bt_data ad[] = { BT_DATA_BYTES(BT_DATA_FLAGS, (BT_LE_AD_GENERAL | BT_LE_AD_NO_BREDR)), @@ -49,6 +50,21 @@ static struct bt_gatt_cb gatt_callbacks = { .att_mtu_updated = mtu_updated }; +#define BT_LE_SCAN_PASSIVE_ALLOW_DUPILCATES \ + BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_PASSIVE, \ + BT_LE_SCAN_OPT_NONE, \ + BT_GAP_SCAN_FAST_INTERVAL_MIN, \ + BT_GAP_SCAN_FAST_INTERVAL_MIN) + +static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, + struct net_buf_simple *ad) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + + bt_addr_le_to_str(addr, addr_str, sizeof(addr_str)); + printk("Device found: %s (RSSI %d)\n", addr_str, rssi); +} + uint32_t peripheral_gatt_write(uint32_t count) { int err; @@ -63,6 +79,23 @@ uint32_t peripheral_gatt_write(uint32_t count) bt_gatt_cb_register(&gatt_callbacks); + /* On target, users can enable simultaneous (background) scanning but by default do not have + * the scanning enabled. + * If both Central plus Peripheral role is built together then + * Peripheral is scanning (on 1M and Coded PHY windows) while there + * is simultaneous Write Commands. + */ + if (IS_ENABLED(CONFIG_BT_OBSERVER) && !IS_ENABLED(CONFIG_USE_PHY_UPDATE_ITERATION_ONCE)) { + printk("Start continuous passive scanning..."); + err = bt_le_scan_start(BT_LE_SCAN_PASSIVE_ALLOW_DUPILCATES, + device_found); + if (err != 0) { + printk("Scan start failed (%d).\n", err); + return err; + } + printk("success.\n"); + } + #if defined(CONFIG_BT_SMP) (void)bt_conn_auth_cb_register(&auth_callbacks); #endif /* CONFIG_BT_SMP */ @@ -85,6 +118,13 @@ uint32_t peripheral_gatt_write(uint32_t count) conn_connected = NULL; last_write_rate = 0U; + write_countdown = &count; + + if (count != 0U) { + printk("GATT Write countdown %u on connection.\n", count); + } else { + printk("GATT Write forever on connection.\n"); + } while (true) { struct bt_conn *conn = NULL; @@ -103,6 +143,10 @@ uint32_t peripheral_gatt_write(uint32_t count) bt_conn_unref(conn); if (count) { + if ((count % 1000U) == 0U) { + printk("GATT Write countdown %u\n", count); + } + count--; if (!count) { break; diff --git a/samples/bluetooth/peripheral_hr/boards/stm32wba_stdby.overlay b/samples/bluetooth/peripheral_hr/boards/stm32wba_stdby.overlay new file mode 100644 index 0000000000000..89ff4c0e3facb --- /dev/null +++ b/samples/bluetooth/peripheral_hr/boards/stm32wba_stdby.overlay @@ -0,0 +1,23 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2025 STMicroelectronics + */ +/ { + /* Change min residency time to ease power consumption measurement */ + cpus { + cpu0: cpu@0 { + cpu-power-states = <&stop0 &stop1 &standby>; + }; + + power-states { + standby: state2 { + exit-latency-us = <500>; + }; + }; + }; +}; + +&lptim1 { + status = "okay"; +}; diff --git a/samples/boards/arc_secure_services/nsim_sem_normal.dts b/samples/boards/arc_secure_services/nsim_sem_normal.dts index 0d5d584da657a..f17e6a02b4f9e 100644 --- a/samples/boards/arc_secure_services/nsim_sem_normal.dts +++ b/samples/boards/arc_secure_services/nsim_sem_normal.dts @@ -24,5 +24,4 @@ chosen { zephyr,sram = &dccm0; }; - }; diff --git a/samples/boards/microchip/mec15xxevb_assy6853/power_management/mec15xxevb_assy6853.overlay b/samples/boards/microchip/mec15xxevb_assy6853/power_management/mec15xxevb_assy6853.overlay index a4fe1432e3060..22319a12ede89 100644 --- a/samples/boards/microchip/mec15xxevb_assy6853/power_management/mec15xxevb_assy6853.overlay +++ b/samples/boards/microchip/mec15xxevb_assy6853/power_management/mec15xxevb_assy6853.overlay @@ -6,8 +6,7 @@ #include -/ { -}; +/ {}; &pcr { status = "okay"; pll-32k-src = ; diff --git a/samples/boards/microchip/mec172xevb_assy6906/qmspi_ldma/mec172xevb_assy6906.overlay b/samples/boards/microchip/mec172xevb_assy6906/qmspi_ldma/mec172xevb_assy6906.overlay index e77990da51a5b..97bd8478a882d 100644 --- a/samples/boards/microchip/mec172xevb_assy6906/qmspi_ldma/mec172xevb_assy6906.overlay +++ b/samples/boards/microchip/mec172xevb_assy6906/qmspi_ldma/mec172xevb_assy6906.overlay @@ -4,53 +4,52 @@ * SPDX-License-Identifier: Apache-2.0 */ -/ { -}; +/ {}; &pinctrl { shd_cs0_n_gpio055_sleep: shd_cs0_n_gpio055_sleep { - pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF2) >; + pinmux = ; low-power-enable; }; shd_clk_gpio056_sleep: shd_clk_gpio056_sleep { - pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF2) >; + pinmux = ; low-power-enable; }; shd_io0_gpio223_sleep: shd_io0_gpio223_sleep { - pinmux = < MCHP_XEC_PINMUX(0223, MCHP_AF1) >; + pinmux = ; low-power-enable; }; shd_io1_gpio224_sleep: shd_io1_gpio224_sleep { - pinmux = < MCHP_XEC_PINMUX(0224, MCHP_AF2) >; + pinmux = ; low-power-enable; }; shd_io2_gpio227_sleep: shd_io2_gpio227_sleep { - pinmux = < MCHP_XEC_PINMUX(0227, MCHP_AF1) >; + pinmux = ; low-power-enable; }; shd_io3_gpio016_sleep: shd_io3_gpio016_sleep { - pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF2) >; + pinmux = ; low-power-enable; }; gpio_off_gpio116: gpio_gpio116 { - pinmux = < MCHP_XEC_PINMUX(0116, MCHP_GPIO) >; + pinmux = ; low-power-enable; }; gpio_off_gpio117: gpio_gpio117 { - pinmux = < MCHP_XEC_PINMUX(0117, MCHP_GPIO) >; + pinmux = ; low-power-enable; }; gpio_off_gpio074: gpio_gpio074 { - pinmux = < MCHP_XEC_PINMUX(074, MCHP_GPIO) >; + pinmux = ; low-power-enable; }; gpio_off_gpio075: gpio_gpio075 { - pinmux = < MCHP_XEC_PINMUX(075, MCHP_GPIO) >; + pinmux = ; low-power-enable; }; gpio_off_gpio076: gpio_gpio076 { - pinmux = < MCHP_XEC_PINMUX(076, MCHP_GPIO) >; + pinmux = ; low-power-enable; }; }; @@ -65,10 +64,10 @@ compatible = "microchip,xec-qmspi-ldma"; status = "okay"; - pinctrl-0 = < &shd_cs0_n_gpio055 - &shd_clk_gpio056 - &shd_io0_gpio223 - &shd_io1_gpio224 - &shd_io2_gpio227 - &shd_io3_gpio016 >; + pinctrl-0 = <&shd_cs0_n_gpio055 + &shd_clk_gpio056 + &shd_io0_gpio223 + &shd_io1_gpio224 + &shd_io2_gpio227 + &shd_io3_gpio016>; }; diff --git a/samples/boards/microchip/mec172xevb_assy6906/rom_api/mec172xevb_assy6906.overlay b/samples/boards/microchip/mec172xevb_assy6906/rom_api/mec172xevb_assy6906.overlay index 7c05de31d3d69..64c933906f516 100644 --- a/samples/boards/microchip/mec172xevb_assy6906/rom_api/mec172xevb_assy6906.overlay +++ b/samples/boards/microchip/mec172xevb_assy6906/rom_api/mec172xevb_assy6906.overlay @@ -4,8 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/ { -}; +/ {}; &symcr { status = "okay"; diff --git a/samples/boards/nordic/clock_control/configs/audiopll.overlay b/samples/boards/nordic/clock_control/configs/audiopll.overlay index 3e99bbdbeb88d..062300a9c235f 100644 --- a/samples/boards/nordic/clock_control/configs/audiopll.overlay +++ b/samples/boards/nordic/clock_control/configs/audiopll.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { aliases { sample-clock = &audiopll; }; diff --git a/samples/boards/nordic/clock_control/configs/cpuapp_hsfll.overlay b/samples/boards/nordic/clock_control/configs/cpuapp_hsfll.overlay index 651f8567b7acc..0d46dfbda451b 100644 --- a/samples/boards/nordic/clock_control/configs/cpuapp_hsfll.overlay +++ b/samples/boards/nordic/clock_control/configs/cpuapp_hsfll.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { aliases { sample-clock = &cpuapp_hsfll; }; diff --git a/samples/boards/nordic/clock_control/configs/fll16m.overlay b/samples/boards/nordic/clock_control/configs/fll16m.overlay index 0169c5a257474..e6484259ce4f3 100644 --- a/samples/boards/nordic/clock_control/configs/fll16m.overlay +++ b/samples/boards/nordic/clock_control/configs/fll16m.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { aliases { sample-clock = &fll16m; }; diff --git a/samples/boards/nordic/clock_control/configs/global_hsfll.overlay b/samples/boards/nordic/clock_control/configs/global_hsfll.overlay index 24585f5a5c668..c7e67b9c4e854 100644 --- a/samples/boards/nordic/clock_control/configs/global_hsfll.overlay +++ b/samples/boards/nordic/clock_control/configs/global_hsfll.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { aliases { sample-clock = &hsfll120; }; diff --git a/samples/boards/nordic/clock_control/configs/lfclk.overlay b/samples/boards/nordic/clock_control/configs/lfclk.overlay index 6a04c2de706b0..db48e5f7705d6 100644 --- a/samples/boards/nordic/clock_control/configs/lfclk.overlay +++ b/samples/boards/nordic/clock_control/configs/lfclk.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { aliases { sample-clock = &lfclk; }; diff --git a/samples/boards/nordic/clock_control/configs/uart135.overlay b/samples/boards/nordic/clock_control/configs/uart135.overlay index 51f8f5102c03d..547145fa91de5 100644 --- a/samples/boards/nordic/clock_control/configs/uart135.overlay +++ b/samples/boards/nordic/clock_control/configs/uart135.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { aliases { sample-device = &uart135; }; diff --git a/samples/boards/nordic/nrf_ironside/update/src/main.c b/samples/boards/nordic/nrf_ironside/update/src/main.c index 11fb882451906..29d058ca139cd 100644 --- a/samples/boards/nordic/nrf_ironside/update/src/main.c +++ b/samples/boards/nordic/nrf_ironside/update/src/main.c @@ -18,12 +18,21 @@ int main(void) err = ironside_boot_report_get(&report); LOG_INF("ironside_boot_report_get err: %d", err); - LOG_INF("version: %d.%d.%d-%s+%d", report->ironside_se_version.major, - report->ironside_se_version.minor, report->ironside_se_version.patch, - report->ironside_se_version.extraversion, report->ironside_se_version.seqnum); - LOG_INF("recovery version: %d.%d.%d-%s+%d", report->ironside_se_version.major, - report->ironside_se_version.minor, report->ironside_se_version.patch, - report->ironside_se_version.extraversion, report->ironside_se_version.seqnum); + /* Extract version components from packed 32-bit integer (8-bit MAJOR.MINOR.PATCH.SEQNUM) */ + uint8_t se_major = (report->ironside_se_version_int >> 24) & 0xFF; + uint8_t se_minor = (report->ironside_se_version_int >> 16) & 0xFF; + uint8_t se_patch = (report->ironside_se_version_int >> 8) & 0xFF; + uint8_t se_seqnum = report->ironside_se_version_int & 0xFF; + + uint8_t recovery_major = (report->ironside_se_recovery_version_int >> 24) & 0xFF; + uint8_t recovery_minor = (report->ironside_se_recovery_version_int >> 16) & 0xFF; + uint8_t recovery_patch = (report->ironside_se_recovery_version_int >> 8) & 0xFF; + uint8_t recovery_seqnum = report->ironside_se_recovery_version_int & 0xFF; + + LOG_INF("version: %d.%d.%d-%s+%d", se_major, se_minor, se_patch, + report->ironside_se_extraversion, se_seqnum); + LOG_INF("recovery version: %d.%d.%d-%s+%d", recovery_major, recovery_minor, recovery_patch, + report->ironside_se_recovery_extraversion, recovery_seqnum); LOG_INF("update status: 0x%x", report->ironside_update_status); LOG_HEXDUMP_INF((void *)report->random_data, sizeof(report->random_data), "random data"); diff --git a/samples/boards/nordic/nrfx_prs/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/boards/nordic/nrfx_prs/boards/nrf5340dk_nrf5340_cpuapp.overlay index 4bbf47524a804..8c93c1985ccf3 100644 --- a/samples/boards/nordic/nrfx_prs/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/boards/nordic/nrfx_prs/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -25,7 +25,7 @@ ; }; group2 { - psels = ; + psels = ; bias-pull-down; }; }; diff --git a/samples/boards/nordic/spis_wakeup/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/boards/nordic/spis_wakeup/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 40b2ae3d64b95..ae3c8b6c81fc6 100644 --- a/samples/boards/nordic/spis_wakeup/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/samples/boards/nordic/spis_wakeup/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -57,8 +57,8 @@ pinctrl-names = "default", "sleep"; wake-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; memory-regions = <&cpuapp_dma_region>; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; &uart136 { diff --git a/samples/boards/nxp/s32/netc/README.rst b/samples/boards/nxp/s32/netc/README.rst index d9d2c50123312..4fba6c4d3e5a0 100644 --- a/samples/boards/nxp/s32/netc/README.rst +++ b/samples/boards/nxp/s32/netc/README.rst @@ -111,7 +111,7 @@ a Windows host, this can be done with the following commands: netsh interface ipv6 add route ::/0 "Ethernet" :: .. note:: - The above commands must be run as priviledged user. + The above commands must be run as privileged user. If everything is configured correctly, you will be able to successfully execute the following commands from the Zephyr shell: diff --git a/samples/boards/raspberrypi/rpi_pico/uart_pio/boards/rpi_pico.overlay b/samples/boards/raspberrypi/rpi_pico/uart_pio/boards/rpi_pico.overlay index 3b18c49d56cda..d9d9952daa888 100644 --- a/samples/boards/raspberrypi/rpi_pico/uart_pio/boards/rpi_pico.overlay +++ b/samples/boards/raspberrypi/rpi_pico/uart_pio/boards/rpi_pico.overlay @@ -23,7 +23,7 @@ }; &pio1 { - status = "okay"; + status = "okay"; pio1_uart0: uart0 { pinctrl-0 = <&pio1_uart0_default>; diff --git a/samples/boards/renesas/elc/boards/ek_ra2a1.overlay b/samples/boards/renesas/elc/boards/ek_ra2a1.overlay index 7fe8d8d40686f..220d8dafb8547 100644 --- a/samples/boards/renesas/elc/boards/ek_ra2a1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra2a1.overlay @@ -35,7 +35,7 @@ &pwm0 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra4c1.overlay b/samples/boards/renesas/elc/boards/ek_ra4c1.overlay index 1eb51154b859d..c4a450a4732f4 100644 --- a/samples/boards/renesas/elc/boards/ek_ra4c1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra4c1.overlay @@ -34,7 +34,7 @@ &pwm0 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra4e2.overlay b/samples/boards/renesas/elc/boards/ek_ra4e2.overlay index 88e6464a09cd8..b981a3dc9a4f7 100644 --- a/samples/boards/renesas/elc/boards/ek_ra4e2.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra4e2.overlay @@ -36,7 +36,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra4l1.overlay b/samples/boards/renesas/elc/boards/ek_ra4l1.overlay index 78cb6c85cd0ac..01233945599ff 100644 --- a/samples/boards/renesas/elc/boards/ek_ra4l1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra4l1.overlay @@ -34,7 +34,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra4m1.overlay b/samples/boards/renesas/elc/boards/ek_ra4m1.overlay index a36fc154be07a..e599126b3dd5d 100644 --- a/samples/boards/renesas/elc/boards/ek_ra4m1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra4m1.overlay @@ -34,7 +34,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra4m2.overlay b/samples/boards/renesas/elc/boards/ek_ra4m2.overlay index 65847b9cde38a..4bce4b73993d4 100644 --- a/samples/boards/renesas/elc/boards/ek_ra4m2.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra4m2.overlay @@ -35,7 +35,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra4m3.overlay b/samples/boards/renesas/elc/boards/ek_ra4m3.overlay index 65847b9cde38a..4bce4b73993d4 100644 --- a/samples/boards/renesas/elc/boards/ek_ra4m3.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra4m3.overlay @@ -35,7 +35,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra4w1.overlay b/samples/boards/renesas/elc/boards/ek_ra4w1.overlay index b48b8e9712d21..0b555a48d33a7 100644 --- a/samples/boards/renesas/elc/boards/ek_ra4w1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra4w1.overlay @@ -35,7 +35,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra6e2.overlay b/samples/boards/renesas/elc/boards/ek_ra6e2.overlay index 7e41ebc1d1902..9bb83c82de033 100644 --- a/samples/boards/renesas/elc/boards/ek_ra6e2.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra6e2.overlay @@ -36,7 +36,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra6m1.overlay b/samples/boards/renesas/elc/boards/ek_ra6m1.overlay index 65847b9cde38a..4bce4b73993d4 100644 --- a/samples/boards/renesas/elc/boards/ek_ra6m1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra6m1.overlay @@ -35,7 +35,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra6m2.overlay b/samples/boards/renesas/elc/boards/ek_ra6m2.overlay index 65847b9cde38a..4bce4b73993d4 100644 --- a/samples/boards/renesas/elc/boards/ek_ra6m2.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra6m2.overlay @@ -35,7 +35,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra6m3.overlay b/samples/boards/renesas/elc/boards/ek_ra6m3.overlay index c0a12ebcde08f..38bdaf4f1d035 100644 --- a/samples/boards/renesas/elc/boards/ek_ra6m3.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra6m3.overlay @@ -35,7 +35,7 @@ &pwm0 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra6m4.overlay b/samples/boards/renesas/elc/boards/ek_ra6m4.overlay index 65847b9cde38a..38bdaf4f1d035 100644 --- a/samples/boards/renesas/elc/boards/ek_ra6m4.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra6m4.overlay @@ -9,7 +9,7 @@ / { aliases { - pwm-gen = &pwm1; + pwm-gen = &pwm0; pwm-cap = &pwm4; elc-link = &elc; }; @@ -33,9 +33,9 @@ status = "okay"; }; -&pwm1 { +&pwm0 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra6m5.overlay b/samples/boards/renesas/elc/boards/ek_ra6m5.overlay index 65847b9cde38a..38bdaf4f1d035 100644 --- a/samples/boards/renesas/elc/boards/ek_ra6m5.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra6m5.overlay @@ -9,7 +9,7 @@ / { aliases { - pwm-gen = &pwm1; + pwm-gen = &pwm0; pwm-cap = &pwm4; elc-link = &elc; }; @@ -33,9 +33,9 @@ status = "okay"; }; -&pwm1 { +&pwm0 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra8d1.overlay b/samples/boards/renesas/elc/boards/ek_ra8d1.overlay index 417d28c7337c9..3bfdd37611f6b 100644 --- a/samples/boards/renesas/elc/boards/ek_ra8d1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra8d1.overlay @@ -38,7 +38,7 @@ &pwm7 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/ek_ra8m1.overlay b/samples/boards/renesas/elc/boards/ek_ra8m1.overlay index c59477cd6b893..c4829ec991a48 100644 --- a/samples/boards/renesas/elc/boards/ek_ra8m1.overlay +++ b/samples/boards/renesas/elc/boards/ek_ra8m1.overlay @@ -38,7 +38,7 @@ &pwm7 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/fpb_ra4e1.overlay b/samples/boards/renesas/elc/boards/fpb_ra4e1.overlay index f2dcaf9257fc1..7a961513ccb6b 100644 --- a/samples/boards/renesas/elc/boards/fpb_ra4e1.overlay +++ b/samples/boards/renesas/elc/boards/fpb_ra4e1.overlay @@ -34,7 +34,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/fpb_ra6e1.overlay b/samples/boards/renesas/elc/boards/fpb_ra6e1.overlay index 65847b9cde38a..4bce4b73993d4 100644 --- a/samples/boards/renesas/elc/boards/fpb_ra6e1.overlay +++ b/samples/boards/renesas/elc/boards/fpb_ra6e1.overlay @@ -35,7 +35,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/fpb_ra6e2.overlay b/samples/boards/renesas/elc/boards/fpb_ra6e2.overlay index 7e41ebc1d1902..9bb83c82de033 100644 --- a/samples/boards/renesas/elc/boards/fpb_ra6e2.overlay +++ b/samples/boards/renesas/elc/boards/fpb_ra6e2.overlay @@ -36,7 +36,7 @@ &pwm1 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/mck_ra8t1.overlay b/samples/boards/renesas/elc/boards/mck_ra8t1.overlay index 1205339ae457a..9f21f475d0965 100644 --- a/samples/boards/renesas/elc/boards/mck_ra8t1.overlay +++ b/samples/boards/renesas/elc/boards/mck_ra8t1.overlay @@ -38,7 +38,7 @@ &pwm2 { renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/elc/boards/voice_ra4e1.overlay b/samples/boards/renesas/elc/boards/voice_ra4e1.overlay index 536ff3ad2d373..2be428e368375 100644 --- a/samples/boards/renesas/elc/boards/voice_ra4e1.overlay +++ b/samples/boards/renesas/elc/boards/voice_ra4e1.overlay @@ -38,7 +38,7 @@ interrupts = <95 1>, <94 1>; interrupt-names = "gtioca", "overflow"; renesas-elcs = <&elc RA_ELC_PERIPHERAL_GPT_A RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0>, - <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; + <&elc RA_ELC_PERIPHERAL_GPT_B RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1>; renesas-elc-names = "start", "stop"; start-source = "GPT_SOURCE_GPT_A"; stop-source = "GPT_SOURCE_GPT_B"; diff --git a/samples/boards/renesas/openamp_linux_zephyr/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/boards/renesas/openamp_linux_zephyr/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index 4c78b84427dcf..cc545f79b7e56 100644 --- a/samples/boards/renesas/openamp_linux_zephyr/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/samples/boards/renesas/openamp_linux_zephyr/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -18,7 +18,7 @@ compatible = "zephyr,memory-region"; reg = <0x62F00000 0x600000>; zephyr,memory-region = "openamp_memory"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-attr = ; }; }; @@ -72,7 +72,6 @@ mboxes = <&mbox1 1>, <&mbox1 0>; mbox-names = "tx", "rx"; }; - }; &mbox1 { diff --git a/samples/boards/st/backup_sram/boards/b_u585i_iot02a.overlay b/samples/boards/st/backup_sram/boards/b_u585i_iot02a.overlay index 1e1c45a00e21a..4290b47291bcc 100644 --- a/samples/boards/st/backup_sram/boards/b_u585i_iot02a.overlay +++ b/samples/boards/st/backup_sram/boards/b_u585i_iot02a.overlay @@ -4,6 +4,6 @@ * Copyright (c) 2023 STMicroelectronics */ -&backup_sram{ +&backup_sram { status = "okay"; }; diff --git a/samples/boards/st/backup_sram/boards/nucleo_h563zi.overlay b/samples/boards/st/backup_sram/boards/nucleo_h563zi.overlay index 377726bbd4ccf..d11651156a3ad 100644 --- a/samples/boards/st/backup_sram/boards/nucleo_h563zi.overlay +++ b/samples/boards/st/backup_sram/boards/nucleo_h563zi.overlay @@ -4,6 +4,6 @@ * Copyright (c) 2024 Thorsten Spätling */ -&backup_sram{ +&backup_sram { status = "okay"; }; diff --git a/samples/boards/st/backup_sram/boards/nucleo_u575zi_q.overlay b/samples/boards/st/backup_sram/boards/nucleo_u575zi_q.overlay index 1e1c45a00e21a..4290b47291bcc 100644 --- a/samples/boards/st/backup_sram/boards/nucleo_u575zi_q.overlay +++ b/samples/boards/st/backup_sram/boards/nucleo_u575zi_q.overlay @@ -4,6 +4,6 @@ * Copyright (c) 2023 STMicroelectronics */ -&backup_sram{ +&backup_sram { status = "okay"; }; diff --git a/samples/boards/st/index.rst b/samples/boards/st/index.rst index 2fbf890669dea..10efcfc53f568 100644 --- a/samples/boards/st/index.rst +++ b/samples/boards/st/index.rst @@ -1,6 +1,6 @@ .. zephyr:code-sample-category:: st :name: STMicroelectronics :show-listing: - :glob: **/* + :glob: */* Samples that demonstrate some board-specific features on STM32 boards. diff --git a/samples/boards/st/mco/boards/nucleo_f411re.overlay b/samples/boards/st/mco/boards/nucleo_f411re.overlay index 7c83914b2c068..b3ee1b9df28c3 100644 --- a/samples/boards/st/mco/boards/nucleo_f411re.overlay +++ b/samples/boards/st/mco/boards/nucleo_f411re.overlay @@ -17,9 +17,9 @@ &mco1 { /* Select One of the line below for clock source */ clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; -/* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */ -/* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */ -/* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>; */ + /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */ + /* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */ + /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>; */ prescaler = ; pinctrl-0 = <&rcc_mco_1_pa8>; pinctrl-names = "default"; diff --git a/samples/boards/st/mco/boards/nucleo_f429zi.overlay b/samples/boards/st/mco/boards/nucleo_f429zi.overlay index b6f4ebabd3d3a..51e1b34605710 100644 --- a/samples/boards/st/mco/boards/nucleo_f429zi.overlay +++ b/samples/boards/st/mco/boards/nucleo_f429zi.overlay @@ -21,7 +21,6 @@ pinctrl-names = "default"; }; - &mco2 { status = "okay"; clocks = <&rcc STM32_SRC_HSE MCO2_SEL(MCO_SEL_HSE)>; diff --git a/samples/boards/st/mco/boards/nucleo_f446ze.overlay b/samples/boards/st/mco/boards/nucleo_f446ze.overlay index 4a1713ba49daa..19c340e52ac33 100644 --- a/samples/boards/st/mco/boards/nucleo_f446ze.overlay +++ b/samples/boards/st/mco/boards/nucleo_f446ze.overlay @@ -11,10 +11,10 @@ /* see RefMan RM0390 */ &mco1 { /* Select One of the line below for clock source */ -/* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */ -/* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */ + /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */ + /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */ clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; -/* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/ + /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/ prescaler = ; pinctrl-0 = <&rcc_mco_1_pa8>; pinctrl-names = "default"; diff --git a/samples/boards/st/power_mgmt/blinky/sample.yaml b/samples/boards/st/power_mgmt/blinky/sample.yaml index 0405426822896..1c072b504b253 100644 --- a/samples/boards/st/power_mgmt/blinky/sample.yaml +++ b/samples/boards/st/power_mgmt/blinky/sample.yaml @@ -18,3 +18,4 @@ tests: integration_platforms: - nucleo_wb55rg - nucleo_f429zi + - nucleo_c071rb diff --git a/samples/boards/st/power_mgmt/serial_wakeup/boards/b_u585i_iot02a.overlay b/samples/boards/st/power_mgmt/serial_wakeup/boards/b_u585i_iot02a.overlay index 35fe8ebb9eaf4..917fcb5c6d8d9 100644 --- a/samples/boards/st/power_mgmt/serial_wakeup/boards/b_u585i_iot02a.overlay +++ b/samples/boards/st/power_mgmt/serial_wakeup/boards/b_u585i_iot02a.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -&cpu0{ +&cpu0 { /* USART Wakeup requires automatic HSI16 switch on in deepsleep mode * which isn't possible in Stop Mode 2. * Remove Stop Mode 2 from supported modes diff --git a/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wb55rg.overlay b/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wb55rg.overlay index 49880565e0a8b..0be7cde75ad46 100644 --- a/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wb55rg.overlay +++ b/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wb55rg.overlay @@ -5,7 +5,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -&cpu0{ +&cpu0 { /* USART Wakeup requires automatic HSI16 switch on in deepsleep mode * which isn't possible in Stop Mode 2. * Remove Stop Mode 2 from supported modes diff --git a/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wl55jc.overlay b/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wl55jc.overlay index 7637f2a62b85c..65134b2751f22 100644 --- a/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wl55jc.overlay +++ b/samples/boards/st/power_mgmt/serial_wakeup/boards/nucleo_wl55jc.overlay @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ - &lpuart1 { /* Set domain clock to LSE to allow wakeup from Stop mode */ clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>, - <&rcc STM32_SRC_LSE LPUART1_SEL(3)>; + <&rcc STM32_SRC_LSE LPUART1_SEL(3)>; /* LPUART1 clock source on LSE : set console at 9600 */ current-speed = <9600>; diff --git a/samples/boards/st/power_mgmt/stop3/boards/nucleo_u575zi_q.overlay b/samples/boards/st/power_mgmt/stop3/boards/nucleo_u575zi_q.overlay index 63818b6cff1cf..03ab17b270723 100644 --- a/samples/boards/st/power_mgmt/stop3/boards/nucleo_u575zi_q.overlay +++ b/samples/boards/st/power_mgmt/stop3/boards/nucleo_u575zi_q.overlay @@ -17,6 +17,6 @@ &rtc { status = "okay"; clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>, - <&rcc STM32_SRC_LSI RTC_SEL(2)>; + <&rcc STM32_SRC_LSI RTC_SEL(2)>; prescaler = <32768>; }; diff --git a/samples/boards/st/power_mgmt/wkup_pins/boards/nucleo_wba55cg.overlay b/samples/boards/st/power_mgmt/wkup_pins/boards/nucleo_wba55cg.overlay index d4d0cca1806c8..66b94ab492161 100644 --- a/samples/boards/st/power_mgmt/wkup_pins/boards/nucleo_wba55cg.overlay +++ b/samples/boards/st/power_mgmt/wkup_pins/boards/nucleo_wba55cg.overlay @@ -6,7 +6,7 @@ / { aliases { - wkup-src = &button_0; + wkup-src = &user_button_1; }; }; diff --git a/samples/boards/st/sensortile_box_pro/index.rst b/samples/boards/st/sensortile_box_pro/index.rst new file mode 100644 index 0000000000000..6dcca7cfd4ffc --- /dev/null +++ b/samples/boards/st/sensortile_box_pro/index.rst @@ -0,0 +1,6 @@ +.. zephyr:code-sample-category:: sensortile_box_pro + :name: SensorTile.box Pro + :show-listing: + :glob: */* + + Samples that demonstrate some board-specific features on SensorTile.box Pro boards. diff --git a/samples/boards/st/steval_stwinbx1/index.rst b/samples/boards/st/steval_stwinbx1/index.rst new file mode 100644 index 0000000000000..7ae625a2a9172 --- /dev/null +++ b/samples/boards/st/steval_stwinbx1/index.rst @@ -0,0 +1,6 @@ +.. zephyr:code-sample-category:: stwinbx1 + :name: STWIN.box + :show-listing: + :glob: */* + + Samples that demonstrate some board-specific features on STWIN.box boards. diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_c031c6.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_c031c6.overlay index 8171267eebd50..606f1adb90423 100644 --- a/samples/boards/st/uart/circular_dma/boards/nucleo_c031c6.overlay +++ b/samples/boards/st/uart/circular_dma/boards/nucleo_c031c6.overlay @@ -5,8 +5,8 @@ */ &usart2 { - dmas = <&dmamux1 0 53 (STM32_DMA_PERIPH_TX)>, - <&dmamux1 2 52 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>; + dmas = <&dmamux1 0 53 STM32_DMA_PERIPH_TX>, + <&dmamux1 2 52 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>; dma-names = "tx", "rx"; fifo-enable; }; diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_f091rc.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_f091rc.overlay index 274b8d1d5b733..e4430f3d62a1e 100644 --- a/samples/boards/st/uart/circular_dma/boards/nucleo_f091rc.overlay +++ b/samples/boards/st/uart/circular_dma/boards/nucleo_f091rc.overlay @@ -5,8 +5,8 @@ */ &usart2 { - dmas = <&dma1 4 (STM32_DMA_PERIPH_TX)>, - <&dma1 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>; + dmas = <&dma1 4 STM32_DMA_PERIPH_TX>, + <&dma1 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>; dma-names = "tx", "rx"; fifo-enable; }; diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_g071rb.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_g071rb.overlay index de7d0772e510d..a782d9e249c63 100644 --- a/samples/boards/st/uart/circular_dma/boards/nucleo_g071rb.overlay +++ b/samples/boards/st/uart/circular_dma/boards/nucleo_g071rb.overlay @@ -5,8 +5,8 @@ */ &usart2 { - dmas = <&dmamux1 0 53 (STM32_DMA_PERIPH_TX)>, - <&dmamux1 3 52 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>; + dmas = <&dmamux1 0 53 STM32_DMA_PERIPH_TX>, + <&dmamux1 3 52 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>; dma-names = "tx", "rx"; fifo-enable; }; diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_u575zi_q.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_u575zi_q.overlay index 370cf3def478e..b057ed8e06d57 100644 --- a/samples/boards/st/uart/circular_dma/boards/nucleo_u575zi_q.overlay +++ b/samples/boards/st/uart/circular_dma/boards/nucleo_u575zi_q.overlay @@ -5,7 +5,7 @@ */ &usart1 { - dmas = <&gpdma1 0 25 (STM32_DMA_PERIPH_TX) + dmas = <&gpdma1 0 25 STM32_DMA_PERIPH_TX &gpdma1 1 24 (STM32_DMA_MODE_CYCLIC | STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS)>; dma-names = "tx", "rx"; fifo-enable; diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_wba55cg.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_wba55cg.overlay index 751836f855452..ca34ef2f993b4 100644 --- a/samples/boards/st/uart/circular_dma/boards/nucleo_wba55cg.overlay +++ b/samples/boards/st/uart/circular_dma/boards/nucleo_wba55cg.overlay @@ -5,7 +5,7 @@ */ &usart1 { - dmas = <&gpdma1 0 12 (STM32_DMA_PERIPH_TX) + dmas = <&gpdma1 0 12 STM32_DMA_PERIPH_TX &gpdma1 1 11 (STM32_DMA_MODE_CYCLIC | STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS)>; dma-names = "tx", "rx"; fifo-enable; diff --git a/samples/boards/st/uart/index.rst b/samples/boards/st/uart/index.rst new file mode 100644 index 0000000000000..9716e1a990b05 --- /dev/null +++ b/samples/boards/st/uart/index.rst @@ -0,0 +1,5 @@ +.. zephyr:code-sample-category:: stm32_uart + :name: UART + :show-listing: + + Samples that demonstrate the use of UART on STM32 boards. diff --git a/samples/boards/st/uart/single_wire/boards/nucleo_wba55cg.overlay b/samples/boards/st/uart/single_wire/boards/nucleo_wba55cg.overlay index 375d125fbaa5f..789a21da187e1 100644 --- a/samples/boards/st/uart/single_wire/boards/nucleo_wba55cg.overlay +++ b/samples/boards/st/uart/single_wire/boards/nucleo_wba55cg.overlay @@ -30,7 +30,7 @@ / { aliases { - single-line-uart1 = &usart2; - single-line-uart2 = &lpuart1; + single-line-uart1 = &usart2; + single-line-uart2 = &lpuart1; }; }; diff --git a/samples/boards/st/uart/single_wire/boards/stm32f3_disco.overlay b/samples/boards/st/uart/single_wire/boards/stm32f3_disco.overlay index 5d07b989a9335..5c57c9f9753f5 100644 --- a/samples/boards/st/uart/single_wire/boards/stm32f3_disco.overlay +++ b/samples/boards/st/uart/single_wire/boards/stm32f3_disco.overlay @@ -5,7 +5,7 @@ */ / { - aliases { + aliases { single-line-uart1 = &usart2; single-line-uart2 = &uart4; }; diff --git a/samples/drivers/adc/adc_dt/boards/arduino_opta_stm32h747xx_m7.overlay b/samples/drivers/adc/adc_dt/boards/arduino_opta_stm32h747xx_m7.overlay index 098deab62759f..85c55527962a3 100644 --- a/samples/drivers/adc/adc_dt/boards/arduino_opta_stm32h747xx_m7.overlay +++ b/samples/drivers/adc/adc_dt/boards/arduino_opta_stm32h747xx_m7.overlay @@ -7,24 +7,23 @@ / { zephyr,user { - io-channels = - <&adc1 0>, /* I1 */ - <&adc3 0>, /* I2 */ - <&adc1 6>, /* I3 */ - <&adc2 9>, /* I4 */ - <&adc3 6>, /* I5 */ - <&adc3 7>, /* I6 */ - <&adc3 8>, /* I7 */ - <&adc3 9>; /* I8 */ + io-channels = <&adc1 0>, /* I1 */ + <&adc3 0>, /* I2 */ + <&adc1 6>, /* I3 */ + <&adc2 9>, /* I4 */ + <&adc3 6>, /* I5 */ + <&adc3 7>, /* I6 */ + <&adc3 8>, /* I7 */ + <&adc3 9>; /* I8 */ }; }; &adc1 { - status ="okay"; + status = "okay"; }; &adc2 { - status ="okay"; + status = "okay"; }; &adc3 { diff --git a/samples/drivers/adc/adc_dt/boards/mec15xxevb_assy6853.overlay b/samples/drivers/adc/adc_dt/boards/mec15xxevb_assy6853.overlay index 3307849fdaaf1..02f3aac6cac0d 100644 --- a/samples/drivers/adc/adc_dt/boards/mec15xxevb_assy6853.overlay +++ b/samples/drivers/adc/adc_dt/boards/mec15xxevb_assy6853.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>; + io-channels = <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>; }; }; &adc0 { diff --git a/samples/drivers/adc/adc_dt/boards/mec172xevb_assy6906.overlay b/samples/drivers/adc/adc_dt/boards/mec172xevb_assy6906.overlay index cbf77d9164efe..c66f5c948c71b 100644 --- a/samples/drivers/adc/adc_dt/boards/mec172xevb_assy6906.overlay +++ b/samples/drivers/adc/adc_dt/boards/mec172xevb_assy6906.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc0 0>, <&adc0 3>, <&adc0 4>, <&adc0 5>; + io-channels = <&adc0 0>, <&adc0 3>, <&adc0 4>, <&adc0 5>; }; }; &adc0 { diff --git a/samples/drivers/adc/adc_dt/boards/mr_canhubk3.overlay b/samples/drivers/adc/adc_dt/boards/mr_canhubk3.overlay index 3f60c3c465c07..148c09a766a4c 100644 --- a/samples/drivers/adc/adc_dt/boards/mr_canhubk3.overlay +++ b/samples/drivers/adc/adc_dt/boards/mr_canhubk3.overlay @@ -41,10 +41,8 @@ zephyr,acquisition-time = ; zephyr,resolution = <14>; }; - }; - &adc2 { group-channel = "precision"; status = "okay"; diff --git a/samples/drivers/adc/adc_dt/boards/nrf51dk_nrf51822.overlay b/samples/drivers/adc/adc_dt/boards/nrf51dk_nrf51822.overlay index 9b6d5301ad106..7c6361d9a1da6 100644 --- a/samples/drivers/adc/adc_dt/boards/nrf51dk_nrf51822.overlay +++ b/samples/drivers/adc/adc_dt/boards/nrf51dk_nrf51822.overlay @@ -4,7 +4,6 @@ * Copyright (c) 2022 Nordic Semiconductor ASA */ - / { zephyr,user { io-channels = <&adc 0>; diff --git a/samples/drivers/adc/adc_dt/boards/nrf52840dk_nrf52840.overlay b/samples/drivers/adc/adc_dt/boards/nrf52840dk_nrf52840.overlay index 9a7b0a0482073..3678b50379b5e 100644 --- a/samples/drivers/adc/adc_dt/boards/nrf52840dk_nrf52840.overlay +++ b/samples/drivers/adc/adc_dt/boards/nrf52840dk_nrf52840.overlay @@ -4,7 +4,6 @@ * Copyright (c) 2022 Nordic Semiconductor ASA */ - / { zephyr,user { io-channels = <&adc 0>, <&adc 1>, <&adc 7>; diff --git a/samples/drivers/adc/adc_dt/boards/nucleo_h7a3zi_q.overlay b/samples/drivers/adc/adc_dt/boards/nucleo_h7a3zi_q.overlay index 984f0bc002eb0..6f26146c9d36f 100644 --- a/samples/drivers/adc/adc_dt/boards/nucleo_h7a3zi_q.overlay +++ b/samples/drivers/adc/adc_dt/boards/nucleo_h7a3zi_q.overlay @@ -1,5 +1,6 @@ /* Copyright (c) 2021 STMicroelectronics - SPDX-License-Identifier: Apache-2.0 */ + * SPDX-License-Identifier: Apache-2.0 + */ / { zephyr,user { diff --git a/samples/drivers/adc/adc_dt/boards/nucleo_u575zi_q.overlay b/samples/drivers/adc/adc_dt/boards/nucleo_u575zi_q.overlay index 307e7c1341edf..6edf2b1dd74eb 100644 --- a/samples/drivers/adc/adc_dt/boards/nucleo_u575zi_q.overlay +++ b/samples/drivers/adc/adc_dt/boards/nucleo_u575zi_q.overlay @@ -1,5 +1,6 @@ /* Copyright (c) 2022 STMicroelectronics - SPDX-License-Identifier: Apache-2.0 */ + * SPDX-License-Identifier: Apache-2.0 + */ / { zephyr,user { diff --git a/samples/drivers/adc/adc_dt/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/drivers/adc/adc_dt/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index 1d80e7ce4219a..18d10855a22bb 100644 --- a/samples/drivers/adc/adc_dt/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/samples/drivers/adc/adc_dt/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc 0>, <&adc 2>; diff --git a/samples/drivers/adc/adc_dt/boards/s32z2xxdc2_s32z270_rtu0.overlay b/samples/drivers/adc/adc_dt/boards/s32z2xxdc2_s32z270_rtu0.overlay index c0d37a3ba298a..4e2f239170e6c 100644 --- a/samples/drivers/adc/adc_dt/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/samples/drivers/adc/adc_dt/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -9,7 +9,7 @@ / { zephyr,user { io-channels = <&sar_adc0 2>, <&sar_adc0 3>, <&sar_adc0 4>, <&sar_adc0 5>, - <&sar_adc1 3>, <&sar_adc1 4>, <&sar_adc1 5>, <&sar_adc1 6>; + <&sar_adc1 3>, <&sar_adc1 4>, <&sar_adc1 5>, <&sar_adc1 6>; }; }; @@ -52,7 +52,6 @@ zephyr,acquisition-time = ; zephyr,resolution = <12>; }; - }; &sar_adc1 { diff --git a/samples/drivers/adc/adc_dt/boards/sam4s_xplained.overlay b/samples/drivers/adc/adc_dt/boards/sam4s_xplained.overlay index cc255805b4105..d1b0c75729185 100644 --- a/samples/drivers/adc/adc_dt/boards/sam4s_xplained.overlay +++ b/samples/drivers/adc/adc_dt/boards/sam4s_xplained.overlay @@ -17,21 +17,21 @@ /* External ADC(+) */ channel@5 { - reg = <5>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_EXTERNAL0"; + reg = <5>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_EXTERNAL0"; zephyr,acquisition-time = ; - zephyr,input-positive = <5>; + zephyr,input-positive = <5>; zephyr,resolution = <12>; }; /* Internal temperature sensor */ channel@f { - reg = <15>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_EXTERNAL0"; + reg = <15>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_EXTERNAL0"; zephyr,acquisition-time = ; - zephyr,input-positive = <15>; + zephyr,input-positive = <15>; zephyr,resolution = <12>; }; }; diff --git a/samples/drivers/adc/adc_dt/boards/stm32f0_disco.overlay b/samples/drivers/adc/adc_dt/boards/stm32f0_disco.overlay index fc83d6e93bd9f..895d9cd1b489f 100644 --- a/samples/drivers/adc/adc_dt/boards/stm32f0_disco.overlay +++ b/samples/drivers/adc/adc_dt/boards/stm32f0_disco.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { zephyr,user { io-channels = <&adc1 0>, <&adc1 1>; }; diff --git a/samples/drivers/adc/adc_dt/boards/stm32f4_disco.overlay b/samples/drivers/adc/adc_dt/boards/stm32f4_disco.overlay index 42eb2e4f68ab1..d3747ed096705 100644 --- a/samples/drivers/adc/adc_dt/boards/stm32f4_disco.overlay +++ b/samples/drivers/adc/adc_dt/boards/stm32f4_disco.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { zephyr,user { io-channels = <&adc1 1>, <&adc1 6>; }; diff --git a/samples/drivers/adc/adc_dt/boards/stm32h735g_disco.overlay b/samples/drivers/adc/adc_dt/boards/stm32h735g_disco.overlay index 5d30effcf6136..a7e6ca5bef909 100644 --- a/samples/drivers/adc/adc_dt/boards/stm32h735g_disco.overlay +++ b/samples/drivers/adc/adc_dt/boards/stm32h735g_disco.overlay @@ -1,5 +1,6 @@ /* Copyright (c) 2021 STMicroelectronics - SPDX-License-Identifier: Apache-2.0 */ + * SPDX-License-Identifier: Apache-2.0 + */ / { zephyr,user { diff --git a/samples/drivers/adc/adc_dt/boards/stm32l496g_disco.overlay b/samples/drivers/adc/adc_dt/boards/stm32l496g_disco.overlay index 5870758e55729..5d70af5fa9041 100644 --- a/samples/drivers/adc/adc_dt/boards/stm32l496g_disco.overlay +++ b/samples/drivers/adc/adc_dt/boards/stm32l496g_disco.overlay @@ -1,5 +1,6 @@ /* Copyright (c) 2021 STMicroelectronics - SPDX-License-Identifier: Apache-2.0 */ + * SPDX-License-Identifier: Apache-2.0 + */ / { zephyr,user { diff --git a/samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay b/samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay index 720a26a5688cb..93ff3ab1dd52f 100644 --- a/samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay +++ b/samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay @@ -16,8 +16,8 @@ &pinctrl { adc0_default: adc0_default { group0 { - /* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */ - silabs,analog-bus = ; + /* Allocate odd bus 0 on GPIO port C/D to IADC for access to pin PD3 */ + silabs,analog-bus = ; }; }; }; diff --git a/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.overlay b/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.overlay index 7b171fe759c2b..f0d441512f009 100644 --- a/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.overlay +++ b/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.overlay @@ -26,9 +26,8 @@ #size-cells = <0>; /* INPUTx mapping bits [9:0] for CH0 to CH15 */ - map-inputs = <0x10 0x30 0x50 0x70 0x90 0xB0 0xD0 0xF0 0x110 \ - 0x130 0x150 0x170 0x190 0x1B0 0x1D0 0x1F0>; - + map-inputs = <0x10 0x30 0x50 0x70 0x90 0xB0 0xD0 0xF0 0x110 + 0x130 0x150 0x170 0x190 0x1B0 0x1D0 0x1F0>; channel@0 { reg = <0x0>; diff --git a/samples/drivers/auxdisplay/boards/esp_wrover_kit.overlay b/samples/drivers/auxdisplay/boards/esp_wrover_kit.overlay index f34539044caa0..5ef53ceec21a6 100644 --- a/samples/drivers/auxdisplay/boards/esp_wrover_kit.overlay +++ b/samples/drivers/auxdisplay/boards/esp_wrover_kit.overlay @@ -21,14 +21,14 @@ boot-delay-ms = <100>; enable-line-rise-delay-us = <1000>; enable-line-fall-delay-us = <500>; - register-select-gpios = <&aux_display_gpio 0 (GPIO_ACTIVE_HIGH)>; - read-write-gpios = <&aux_display_gpio 1 (GPIO_ACTIVE_HIGH)>; - enable-gpios = <&aux_display_gpio 2 (GPIO_ACTIVE_HIGH)>; - backlight-gpios = <&aux_display_gpio 3 (GPIO_ACTIVE_HIGH)>; - data-bus-gpios = <0>, <0>, <0>, <0>, - <&aux_display_gpio 4 (GPIO_ACTIVE_HIGH)>, - <&aux_display_gpio 5 (GPIO_ACTIVE_HIGH)>, - <&aux_display_gpio 6 (GPIO_ACTIVE_HIGH)>, - <&aux_display_gpio 7 (GPIO_ACTIVE_HIGH)>; + register-select-gpios = <&aux_display_gpio 0 GPIO_ACTIVE_HIGH>; + read-write-gpios = <&aux_display_gpio 1 GPIO_ACTIVE_HIGH>; + enable-gpios = <&aux_display_gpio 2 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&aux_display_gpio 3 GPIO_ACTIVE_HIGH>; + data-bus-gpios = <0>, <0>, <0>, <0>, + <&aux_display_gpio 4 GPIO_ACTIVE_HIGH>, + <&aux_display_gpio 5 GPIO_ACTIVE_HIGH>, + <&aux_display_gpio 6 GPIO_ACTIVE_HIGH>, + <&aux_display_gpio 7 GPIO_ACTIVE_HIGH>; }; }; diff --git a/samples/drivers/auxdisplay/boards/nucleo_f746zg.overlay b/samples/drivers/auxdisplay/boards/nucleo_f746zg.overlay index f4f7f4d9c8f37..f83187030af28 100644 --- a/samples/drivers/auxdisplay/boards/nucleo_f746zg.overlay +++ b/samples/drivers/auxdisplay/boards/nucleo_f746zg.overlay @@ -11,13 +11,13 @@ columns = <20>; rows = <4>; mode = <4>; - register-select-gpios = <&gpiob 8 (GPIO_ACTIVE_HIGH)>; - enable-gpios = <&gpiob 9 (GPIO_ACTIVE_HIGH)>; + register-select-gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>; data-bus-gpios = <0>, <0>, <0>, <0>, - <&gpioa 5 (GPIO_ACTIVE_HIGH)>, - <&gpioa 6 (GPIO_ACTIVE_HIGH)>, - <&gpioa 7 (GPIO_ACTIVE_HIGH)>, - <&gpiod 14 (GPIO_ACTIVE_HIGH)>; + <&gpioa 5 GPIO_ACTIVE_HIGH>, + <&gpioa 6 GPIO_ACTIVE_HIGH>, + <&gpioa 7 GPIO_ACTIVE_HIGH>, + <&gpiod 14 GPIO_ACTIVE_HIGH>; }; }; diff --git a/samples/drivers/auxdisplay_digits/boards/native_sim.overlay b/samples/drivers/auxdisplay_digits/boards/native_sim.overlay index 2579b2c513027..803d1c441590d 100644 --- a/samples/drivers/auxdisplay_digits/boards/native_sim.overlay +++ b/samples/drivers/auxdisplay_digits/boards/native_sim.overlay @@ -22,8 +22,8 @@ <&gpio0 5 0>, /* F */ <&gpio0 6 0>, /* G */ <&gpio0 7 0>; /* DP */ - digit-gpios = <&gpio0 8 0>, /* DIG1 */ - <&gpio0 9 0>, /* DIG2 */ + digit-gpios = <&gpio0 8 0>, /* DIG1 */ + <&gpio0 9 0>, /* DIG2 */ <&gpio0 10 0>; /* DIG3 */ refresh-period-ms = <1>; }; diff --git a/samples/drivers/can/babbling/README.rst b/samples/drivers/can/babbling/README.rst index 8a0f6e55ac7e1..68e55227b397f 100644 --- a/samples/drivers/can/babbling/README.rst +++ b/samples/drivers/can/babbling/README.rst @@ -1,6 +1,6 @@ .. zephyr:code-sample:: can-babbling :name: Controller Area Network (CAN) babbling node - :relevant-api: can_interface + :relevant-api: can_controller Simulate a babbling CAN node. diff --git a/samples/drivers/can/counter/README.rst b/samples/drivers/can/counter/README.rst index 3b66661a714e3..db07d554e2877 100644 --- a/samples/drivers/can/counter/README.rst +++ b/samples/drivers/can/counter/README.rst @@ -1,6 +1,6 @@ .. zephyr:code-sample:: can-counter :name: Controller Area Network (CAN) counter - :relevant-api: can_interface + :relevant-api: can_controller Send and receive CAN messages. diff --git a/samples/drivers/clock_control_xec/boards/mec1501modular_assy6885.overlay b/samples/drivers/clock_control_xec/boards/mec1501modular_assy6885.overlay index fba1d5c4a5fec..494c2312aa439 100644 --- a/samples/drivers/clock_control_xec/boards/mec1501modular_assy6885.overlay +++ b/samples/drivers/clock_control_xec/boards/mec1501modular_assy6885.overlay @@ -6,8 +6,7 @@ #include -/ { -}; +/ {}; &pcr { status = "okay"; pll-32k-src = ; @@ -23,8 +22,8 @@ /* 32KHZ_IN is a clock source with debug */ /* pinctrl-0 = <&clk_32khz_in_gpio165 - &tst_clk_out_gpio060 - &clk_32khz_out_gpio221>; - */ + * &tst_clk_out_gpio060 + * &clk_32khz_out_gpio221>; + */ pinctrl-names = "default"; }; diff --git a/samples/drivers/clock_control_xec/boards/mec15xxevb_assy6853.overlay b/samples/drivers/clock_control_xec/boards/mec15xxevb_assy6853.overlay index fba1d5c4a5fec..494c2312aa439 100644 --- a/samples/drivers/clock_control_xec/boards/mec15xxevb_assy6853.overlay +++ b/samples/drivers/clock_control_xec/boards/mec15xxevb_assy6853.overlay @@ -6,8 +6,7 @@ #include -/ { -}; +/ {}; &pcr { status = "okay"; pll-32k-src = ; @@ -23,8 +22,8 @@ /* 32KHZ_IN is a clock source with debug */ /* pinctrl-0 = <&clk_32khz_in_gpio165 - &tst_clk_out_gpio060 - &clk_32khz_out_gpio221>; - */ + * &tst_clk_out_gpio060 + * &clk_32khz_out_gpio221>; + */ pinctrl-names = "default"; }; diff --git a/samples/drivers/clock_control_xec/boards/mec172xevb_assy6906.overlay b/samples/drivers/clock_control_xec/boards/mec172xevb_assy6906.overlay index fba1d5c4a5fec..494c2312aa439 100644 --- a/samples/drivers/clock_control_xec/boards/mec172xevb_assy6906.overlay +++ b/samples/drivers/clock_control_xec/boards/mec172xevb_assy6906.overlay @@ -6,8 +6,7 @@ #include -/ { -}; +/ {}; &pcr { status = "okay"; pll-32k-src = ; @@ -23,8 +22,8 @@ /* 32KHZ_IN is a clock source with debug */ /* pinctrl-0 = <&clk_32khz_in_gpio165 - &tst_clk_out_gpio060 - &clk_32khz_out_gpio221>; - */ + * &tst_clk_out_gpio060 + * &clk_32khz_out_gpio221>; + */ pinctrl-names = "default"; }; diff --git a/samples/drivers/counter/alarm/boards/lp_mspm0g3507.overlay b/samples/drivers/counter/alarm/boards/lp_mspm0g3507.overlay index 2682d27ec3dfa..70246889422b1 100644 --- a/samples/drivers/counter/alarm/boards/lp_mspm0g3507.overlay +++ b/samples/drivers/counter/alarm/boards/lp_mspm0g3507.overlay @@ -6,13 +6,13 @@ / { aliases { - counter = &counter0; + counter = &counterg0; }; }; &timg0 { status = "okay"; - counter0: counter { + counterg0: counterg0 { status = "okay"; }; }; diff --git a/samples/drivers/counter/maxim_ds3231/README.rst b/samples/drivers/counter/maxim_ds3231/README.rst index b0534c806c55f..452cd409a9a57 100644 --- a/samples/drivers/counter/maxim_ds3231/README.rst +++ b/samples/drivers/counter/maxim_ds3231/README.rst @@ -7,6 +7,12 @@ Overview ******** +.. warning:: + + The DS3231 driver demonstrated in this sample predates the introduction of + the RTC subsystem and is deprecated. RTC functionality for the DS3231 should + now be enabled by means of the :dtcompatible:`maxim,ds3231-rtc` compatible. + The `DS3231`_ temperature-compensated real-time clock is a high-precision (2 ppm) battery backed clock that maintains civil time and supports alarms. The `Chronodot`_ breakout board can be used to diff --git a/samples/drivers/crc/CMakeLists.txt b/samples/drivers/crc/CMakeLists.txt new file mode 100644 index 0000000000000..710a2cf5c4dbb --- /dev/null +++ b/samples/drivers/crc/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(driver_crc_example) + +target_sources(app PRIVATE src/main.c) diff --git a/samples/drivers/crc/README.rst b/samples/drivers/crc/README.rst new file mode 100644 index 0000000000000..109e779c51550 --- /dev/null +++ b/samples/drivers/crc/README.rst @@ -0,0 +1,44 @@ +.. zephyr:code-sample:: crc_drivers + :name: Cyclic Redundancy Check Drivers (CRC) + :relevant-api: crc_interface + + Compute and verify a CRC checksum using the CRC driver API. + +Overview +******** + +This sample demonstrates how to use the :ref:`CRC driver API `. + +Building and Running +******************** + +Building and Running for Renesas RA8M1 +====================================== + +The sample can be built and executed for the +:zephyr:board:`ek_ra8m1` as follows: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/crc + :board: ek_ra8m1 + :goals: build flash + :compact: + +To build for another board, change "ek_ra8m1" above to that board's name. + +Sample Output +============= + +.. code-block:: console + + crc_example: CRC verification succeed. + +.. note:: If the CRC is not supported, the output will be an error message. + +Expected Behavior +***************** + +When the sample runs, it should: + +1. Compute the CRC8 values of predefined data. +2. Verify the CRC result. diff --git a/samples/drivers/crc/prj.conf b/samples/drivers/crc/prj.conf new file mode 100644 index 0000000000000..411e4bf848c5e --- /dev/null +++ b/samples/drivers/crc/prj.conf @@ -0,0 +1,2 @@ +CONFIG_CRC=y +CONFIG_LOG=y diff --git a/samples/drivers/crc/sample.yaml b/samples/drivers/crc/sample.yaml new file mode 100644 index 0000000000000..7fa3242a2dd1a --- /dev/null +++ b/samples/drivers/crc/sample.yaml @@ -0,0 +1,13 @@ +sample: + name: CRC Sample +tests: + sample.drivers.crc: + depends_on: crc + tags: + - drivers + - crc + harness: console + harness_config: + type: one_line + regex: + - "CRC verification succeeded" diff --git a/samples/drivers/crc/src/main.c b/samples/drivers/crc/src/main.c new file mode 100644 index 0000000000000..2ed7260e13428 --- /dev/null +++ b/samples/drivers/crc/src/main.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(crc_example, CONFIG_LOG_DEFAULT_LEVEL); + +#include +#include + +/* The devicetree node identifier for the "crc" */ +#define CRC_NODE DT_CHOSEN(zephyr_crc) + +/* + * A build error on this line means your board is unsupported. + * See the sample documentation for information on how to fix this. + */ + +int main(void) +{ + static const struct device *const dev = DEVICE_DT_GET(CRC_NODE); + /* Define the data to compute CRC */ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + int ret; + + if (!device_is_ready(dev)) { + LOG_ERR("Device is not ready"); + return -ENODEV; + } + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + /* Start CRC computation */ + ret = crc_begin(dev, &ctx); + + if (ret != 0) { + LOG_ERR("Failed to begin CRC: %d", ret); + return ret; + } + + /* Update CRC computation */ + ret = crc_update(dev, &ctx, data, 8); + + if (ret != 0) { + LOG_ERR("Failed to update CRC: %d", ret); + return ret; + } + + /* Finish CRC computation */ + ret = crc_finish(dev, &ctx); + + if (ret != 0) { + LOG_ERR("Failed to finish CRC: %d", ret); + return ret; + } + /* Verify CRC computation + * (example expected value: 0xB2 with LSB, 0x4D with MSB bit order) + */ + if (ctx.reversed != (CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT)) { + ret = crc_verify(&ctx, 0x4D); + + if (ret != 0) { + LOG_ERR("CRC verification failed: %d", ret); + return ret; + } + } else { /* Reversed is no reversed output */ + ret = crc_verify(&ctx, 0xB2); + + if (ret != 0) { + LOG_ERR("CRC verification failed: %d", ret); + return ret; + } + } + + LOG_INF("CRC verification succeeded"); + + return 0; +} diff --git a/samples/drivers/crypto/boards/lp_mspm0g3507.overlay b/samples/drivers/crypto/boards/lp_mspm0g3507.overlay new file mode 100644 index 0000000000000..5234644d159b3 --- /dev/null +++ b/samples/drivers/crypto/boards/lp_mspm0g3507.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Linumiz GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&aes { + status = "okay"; +}; diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c index dbc280b4654fd..fcece2f072e1f 100644 --- a/samples/drivers/crypto/src/main.c +++ b/samples/drivers/crypto/src/main.c @@ -32,6 +32,8 @@ LOG_MODULE_REGISTER(main); #define CRYPTO_DEV_COMPAT ti_cc23x0_aes #elif CONFIG_CRYPTO_SI32 #define CRYPTO_DEV_COMPAT silabs_si32_aes +#elif CONFIG_CRYPTO_MSPM0_AES +#define CRYPTO_DEV_COMPAT ti_mspm0_aes #else #error "You need to enable one crypto device" #endif @@ -282,6 +284,171 @@ void cbc_mode(const struct device *dev) cipher_free_session(dev, &ini); } +static const uint8_t cfb_ciphertext[64] = { + 0x3b, 0x3f, 0xd9, 0x2e, 0xb7, 0x2d, 0xad, 0x20, 0x33, 0x34, 0x49, 0xf8, + 0xe8, 0x3c, 0xfb, 0x4a, 0xc8, 0xa6, 0x45, 0x37, 0xa0, 0xb3, 0xa9, 0x3f, + 0xcd, 0xe3, 0xcd, 0xad, 0x9f, 0x1c, 0xe5, 0x8b, 0x26, 0x75, 0x1f, 0x67, + 0xa3, 0xcb, 0xb1, 0x40, 0xb1, 0x80, 0x8c, 0xf1, 0x87, 0xa4, 0xf4, 0xdf, + 0xc0, 0x4b, 0x05, 0x35, 0x7c, 0x5d, 0x1c, 0x0e, 0xea, 0xc4, 0xc6, 0x6f, + 0x9f, 0xf7, 0xf2, 0xe6 +}; + +void cfb_mode(const struct device *dev) +{ + uint8_t encrypted[64] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t decrypted[64] __aligned(IO_ALIGNMENT_BYTES) = {0}; + struct cipher_ctx ini = { + .keylen = sizeof(key), + .key.bit_stream = key, + .flags = cap_flags, + }; + struct cipher_pkt encrypt = { + .in_buf = plaintext, + .in_len = sizeof(plaintext), + .out_buf_max = sizeof(encrypted), + .out_buf = encrypted, + }; + struct cipher_pkt decrypt = { + .in_buf = encrypt.out_buf, + .in_len = sizeof(encrypted), + .out_buf = decrypted, + .out_buf_max = sizeof(decrypted), + }; + + static uint8_t iv[16] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f + }; + + if (cipher_begin_session(dev, &ini, CRYPTO_CIPHER_ALGO_AES, CRYPTO_CIPHER_MODE_CFB, + CRYPTO_CIPHER_OP_ENCRYPT)) { + return; + } + + if (cipher_cfb_op(&ini, &encrypt, iv)) { + LOG_ERR("CFB mode ENCRYPT - Failed"); + goto out; + } + + LOG_INF("Output length (encryption): %d", encrypt.out_len); + + if (memcmp(encrypt.out_buf, cfb_ciphertext, sizeof(cfb_ciphertext))) { + LOG_ERR("CFB mode ENCRYPT - Mismatch between expected and " + "returned cipher text"); + print_buffer_comparison(cfb_ciphertext, encrypt.out_buf, + sizeof(cfb_ciphertext)); + goto out; + } + + LOG_INF("CFB mode ENCRYPT - Match"); + cipher_free_session(dev, &ini); + + if (cipher_begin_session(dev, &ini, CRYPTO_CIPHER_ALGO_AES, CRYPTO_CIPHER_MODE_CFB, + CRYPTO_CIPHER_OP_DECRYPT)) { + return; + } + + if (cipher_cfb_op(&ini, &decrypt, iv)) { + LOG_ERR("CFB mode DECRYPT - Failed"); + goto out; + } + + LOG_INF("Output length (decryption): %d", decrypt.out_len); + + if (memcmp(decrypt.out_buf, plaintext, sizeof(plaintext))) { + LOG_ERR("CFB mode DECRYPT - Mismatch between plaintext and " + "decrypted cipher text"); + print_buffer_comparison(plaintext, decrypt.out_buf, sizeof(plaintext)); + goto out; + } + + LOG_INF("CFB mode DECRYPT - Match"); +out: + cipher_free_session(dev, &ini); +} + +static const uint8_t ofb_ciphertext[64] = { + 0x3b, 0x3f, 0xd9, 0x2e, 0xb7, 0x2d, 0xad, 0x20, 0x33, 0x34, 0x49, 0xf8, + 0xe8, 0x3c, 0xfb, 0x4a, 0x77, 0x89, 0x50, 0x8d, 0x16, 0x91, 0x8f, 0x03, + 0xf5, 0x3c, 0x52, 0xda, 0xc5, 0x4e, 0xd8, 0x25, 0x97, 0x40, 0x05, 0x1e, + 0x9c, 0x5f, 0xec, 0xf6, 0x43, 0x44, 0xf7, 0xa8, 0x22, 0x60, 0xed, 0xcc, + 0x30, 0x4c, 0x65, 0x28, 0xf6, 0x59, 0xc7, 0x78, 0x66, 0xa5, 0x10, 0xd9, + 0xc1, 0xd6, 0xae, 0x5e +}; + +void ofb_mode(const struct device *dev) +{ + uint8_t encrypted[64] __aligned(IO_ALIGNMENT_BYTES) = {0}; + uint8_t decrypted[64] __aligned(IO_ALIGNMENT_BYTES) = {0}; + struct cipher_ctx ini = { + .keylen = sizeof(key), + .key.bit_stream = key, + .flags = cap_flags, + }; + struct cipher_pkt encrypt = { + .in_buf = plaintext, + .in_len = sizeof(plaintext), + .out_buf_max = sizeof(encrypted), + .out_buf = encrypted, + }; + struct cipher_pkt decrypt = { + .in_buf = encrypt.out_buf, + .in_len = sizeof(encrypted), + .out_buf = decrypted, + .out_buf_max = sizeof(decrypted), + }; + + static uint8_t iv[16] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f + }; + + if (cipher_begin_session(dev, &ini, CRYPTO_CIPHER_ALGO_AES, CRYPTO_CIPHER_MODE_OFB, + CRYPTO_CIPHER_OP_ENCRYPT)) { + return; + } + + if (cipher_ofb_op(&ini, &encrypt, iv)) { + LOG_ERR("OFB mode ENCRYPT - Failed"); + goto out; + } + + LOG_INF("Output length (encryption): %d", encrypt.out_len); + + if (memcmp(encrypt.out_buf, ofb_ciphertext, sizeof(ofb_ciphertext))) { + LOG_ERR("OFB mode ENCRYPT - Mismatch between expected and " + "returned cipher text"); + print_buffer_comparison(ofb_ciphertext, encrypt.out_buf, sizeof(ofb_ciphertext)); + goto out; + } + + LOG_INF("OFB mode ENCRYPT - Match"); + cipher_free_session(dev, &ini); + + if (cipher_begin_session(dev, &ini, CRYPTO_CIPHER_ALGO_AES, CRYPTO_CIPHER_MODE_OFB, + CRYPTO_CIPHER_OP_DECRYPT)) { + return; + } + + if (cipher_ofb_op(&ini, &decrypt, iv)) { + LOG_ERR("OFB mode DECRYPT - Failed"); + goto out; + } + + LOG_INF("Output length (decryption): %d", decrypt.out_len); + + if (memcmp(decrypt.out_buf, plaintext, sizeof(plaintext))) { + LOG_ERR("OFB mode DECRYPT - Mismatch between plaintext and " + "decrypted cipher text"); + print_buffer_comparison(plaintext, decrypt.out_buf, sizeof(plaintext)); + goto out; + } + + LOG_INF("OFB mode DECRYPT - Match"); +out: + cipher_free_session(dev, &ini); +} + static const uint8_t ctr_ciphertext[64] = { 0x22, 0xe5, 0x2f, 0xb1, 0x77, 0xd8, 0x65, 0xb2, 0xf7, 0xc6, 0xb5, 0x12, 0x69, 0x2d, 0x11, 0x4d, @@ -606,6 +773,8 @@ int main(void) const struct mode_test modes[] = { { .mode = "ECB Mode", .mode_func = ecb_mode }, { .mode = "CBC Mode", .mode_func = cbc_mode }, + { .mode = "CFB Mode", .mode_func = cfb_mode }, + { .mode = "OFB Mode", .mode_func = ofb_mode }, { .mode = "CTR Mode", .mode_func = ctr_mode }, { .mode = "CCM Mode", .mode_func = ccm_mode }, { .mode = "GCM Mode", .mode_func = gcm_mode }, diff --git a/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay index dad493e5f043e..490ac4ba7dcec 100644 --- a/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay +++ b/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay @@ -6,14 +6,14 @@ }; }; -&dacc{ +&dacc { status = "okay"; pinctrl-0 = <&dac_default>; pinctrl-names = "default"; }; -&pinctrl{ - dac_default: dac_default{ +&pinctrl { + dac_default: dac_default { group1 { pinmux = ; }; diff --git a/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay index dad493e5f043e..490ac4ba7dcec 100644 --- a/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay +++ b/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay @@ -6,14 +6,14 @@ }; }; -&dacc{ +&dacc { status = "okay"; pinctrl-0 = <&dac_default>; pinctrl-names = "default"; }; -&pinctrl{ - dac_default: dac_default{ +&pinctrl { + dac_default: dac_default { group1 { pinmux = ; }; diff --git a/samples/drivers/display/README.rst b/samples/drivers/display/README.rst index a0d3616dd3ef0..b91cf39057e05 100644 --- a/samples/drivers/display/README.rst +++ b/samples/drivers/display/README.rst @@ -41,7 +41,7 @@ Below is an example on how to build for a :zephyr:board:`nrf52840dk` board with :shield: adafruit_2_8_tft_touch_v2 :compact: -For testing purpose without the need of any hardware, the :ref:`native_sim ` +For testing purpose without the need of any hardware, the :zephyr:board:`native_sim ` board is also supported and can be built as follows; .. zephyr-app-commands:: diff --git a/samples/drivers/eeprom/README.rst b/samples/drivers/eeprom/README.rst index 6596b0fbc2bf4..8207abd424f38 100644 --- a/samples/drivers/eeprom/README.rst +++ b/samples/drivers/eeprom/README.rst @@ -15,7 +15,7 @@ Building and Running In case the target board has defined an EEPROM with alias ``eeprom-0`` the sample can be built without further ado. This applies for example to the -:ref:`native_sim` board: +:zephyr:board:`native_sim` board: .. zephyr-app-commands:: :zephyr-app: samples/drivers/eeprom diff --git a/samples/drivers/eeprom/sample.yaml b/samples/drivers/eeprom/sample.yaml index b3eec0f461884..0f0d4a7d9d878 100644 --- a/samples/drivers/eeprom/sample.yaml +++ b/samples/drivers/eeprom/sample.yaml @@ -8,8 +8,11 @@ tests: - gd32f450i_eval - native_sim - native_sim/native/64 + - adafruit_qt_py_rp2040/rp2040 integration_platforms: - native_sim/native/64 + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_24lc32" harness: console harness_config: type: one_line diff --git a/samples/drivers/espi/boards/mec1501modular_assy6885.overlay b/samples/drivers/espi/boards/mec1501modular_assy6885.overlay index a9be143174833..7c2b5cd7c461b 100644 --- a/samples/drivers/espi/boards/mec1501modular_assy6885.overlay +++ b/samples/drivers/espi/boards/mec1501modular_assy6885.overlay @@ -19,11 +19,11 @@ port-sel = <0>; chip-select = <0>; lines = <4>; - pinctrl-0 = < &shd_cs0_n_gpio055 - &shd_clk_gpio056 - &shd_io0_gpio223 - &shd_io1_gpio224 - &shd_io2_gpio227 - &shd_io3_gpio016 >; + pinctrl-0 = <&shd_cs0_n_gpio055 + &shd_clk_gpio056 + &shd_io0_gpio223 + &shd_io1_gpio224 + &shd_io2_gpio227 + &shd_io3_gpio016>; pinctrl-names = "default"; }; diff --git a/samples/drivers/espi/boards/mec172xmodular_assy6930.overlay b/samples/drivers/espi/boards/mec172xmodular_assy6930.overlay index f5b7e5483f20e..daa910e5acba3 100644 --- a/samples/drivers/espi/boards/mec172xmodular_assy6930.overlay +++ b/samples/drivers/espi/boards/mec172xmodular_assy6930.overlay @@ -14,7 +14,6 @@ }; }; - /* Enable Target to Controller Virtual Wires GPIO 0 - 3 */ &vw_t2c_gpio_0 { status = "okay"; diff --git a/samples/drivers/ethernet/eth_ivshmem/boards/qemu_cortex_a53.overlay b/samples/drivers/ethernet/eth_ivshmem/boards/qemu_cortex_a53.overlay index fc49be702dfaf..775ffa3b48f18 100644 --- a/samples/drivers/ethernet/eth_ivshmem/boards/qemu_cortex_a53.overlay +++ b/samples/drivers/ethernet/eth_ivshmem/boards/qemu_cortex_a53.overlay @@ -24,11 +24,14 @@ ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; #interrupt-cells = <0x01>; interrupt-map-mask = <0x00 0x00 0x00 0x07>; - interrupt-map = < - 0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 108 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 109 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 110 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 111 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; + interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 108 + IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 109 + IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 110 + IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 111 + IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; bus-range = <0x00 0x00>; }; }; diff --git a/samples/drivers/fuel_gauge/boards/adafruit_feather_esp32s2_C.overlay b/samples/drivers/fuel_gauge/boards/adafruit_feather_esp32s2_C.overlay index 0d37a8063ffd3..dd0efca99d06b 100644 --- a/samples/drivers/fuel_gauge/boards/adafruit_feather_esp32s2_C.overlay +++ b/samples/drivers/fuel_gauge/boards/adafruit_feather_esp32s2_C.overlay @@ -14,7 +14,7 @@ max17048: max17048@36 { compatible = "maxim,max17048"; status = "okay"; - reg = <0x36 >; + reg = <0x36>; power-domains = <&i2c_reg>; }; }; diff --git a/samples/drivers/fuel_gauge/boards/nrf52840dk_nrf52840.overlay b/samples/drivers/fuel_gauge/boards/nrf52840dk_nrf52840.overlay index e166affe1c260..7cb3bf3497770 100644 --- a/samples/drivers/fuel_gauge/boards/nrf52840dk_nrf52840.overlay +++ b/samples/drivers/fuel_gauge/boards/nrf52840dk_nrf52840.overlay @@ -16,9 +16,9 @@ pinctrl-0 = <&i2c0_default>; pinctrl-1 = <&i2c0_sleep>; pinctrl-names = "default", "sleep"; - max17048:max17048@36 { + max17048: max17048@36 { compatible = "maxim,max17048"; status = "ok"; - reg = <0x36 >; + reg = <0x36>; }; }; diff --git a/samples/drivers/haptics/drv2605/sample.yaml b/samples/drivers/haptics/drv2605/sample.yaml new file mode 100644 index 0000000000000..62ff71c04cc72 --- /dev/null +++ b/samples/drivers/haptics/drv2605/sample.yaml @@ -0,0 +1,10 @@ +sample: + name: DRV2605 Haptic Driver sample +tests: + sample.haptics.drv2605: + build_only: true + tags: haptics + platform_allow: + - adafruit_qt_py_rp2040/rp2040 + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_drv2605l" diff --git a/samples/drivers/ht16k33/sample.yaml b/samples/drivers/ht16k33/sample.yaml index 3bb0107b60b06..7bbc1ba4eb1cb 100644 --- a/samples/drivers/ht16k33/sample.yaml +++ b/samples/drivers/ht16k33/sample.yaml @@ -3,6 +3,10 @@ sample: name: HT16K33 sample tests: sample.drivers.ht16k33: - platform_allow: nrf52840dk/nrf52840 + platform_allow: + - nrf52840dk/nrf52840 + - adafruit_qt_py_rp2040/rp2040 + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_ht16k33" harness: TBD tags: LED diff --git a/samples/drivers/i2c/rtio_loopback/Kconfig b/samples/drivers/i2c/rtio_loopback/Kconfig new file mode 100644 index 0000000000000..079f4a735f3a1 --- /dev/null +++ b/samples/drivers/i2c/rtio_loopback/Kconfig @@ -0,0 +1,14 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "I2C RTIO Loopback Test" + +config I2C_RTIO_LOOPBACK_DATA_READ_MAX_SIZE + int "Max data size used for testing I2C read transfers" + default 2 + +config I2C_RTIO_LOOPBACK_DATA_WRITE_MAX_SIZE + int "Max data size used for testing I2C write transfers" + default 6 + +source "Kconfig.zephyr" diff --git a/samples/drivers/i2c/rtio_loopback/README.rst b/samples/drivers/i2c/rtio_loopback/README.rst index 29599173d73ea..787f2a959419c 100644 --- a/samples/drivers/i2c/rtio_loopback/README.rst +++ b/samples/drivers/i2c/rtio_loopback/README.rst @@ -48,3 +48,10 @@ If necessary, add any board specific configs to the board specific overlay: .. code-block:: cfg CONFIG_I2C_TARGET_BUFFER_MODE=y + +Transferred data sizes +********************** + +One can tune the number of data bytes echanged during the tests using +configuration options ``CONFIG_I2C_RTIO_LOOPBACK_DATA_READ_MAX_SIZE`` +and ``CONFIG_I2C_RTIO_LOOPBACK_DATA_WRITE_MAX_SIZE``. diff --git a/samples/drivers/i2c/rtio_loopback/src/main.c b/samples/drivers/i2c/rtio_loopback/src/main.c index ef2a17dd47aed..27ea4c3f0a786 100644 --- a/samples/drivers/i2c/rtio_loopback/src/main.c +++ b/samples/drivers/i2c/rtio_loopback/src/main.c @@ -22,12 +22,12 @@ static const struct device *sample_i2c_controller = I2C_CONTROLLER_DEVICE_GET; static const struct device *sample_i2c_controller_target = I2C_CONTROLLER_TARGET_DEVICE_GET; /* Data to write and buffer to store write in */ -static uint8_t sample_write_data[] = {0x0A, 0x0B}; +static uint8_t sample_write_data[CONFIG_I2C_RTIO_LOOPBACK_DATA_WRITE_MAX_SIZE]; static uint8_t sample_write_buf[sizeof(sample_write_data)]; static uint32_t sample_write_buf_pos; /* Data to read and buffer to store read in */ -static uint8_t sample_read_data[] = {0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5}; +static uint8_t sample_read_data[CONFIG_I2C_RTIO_LOOPBACK_DATA_READ_MAX_SIZE]; static uint32_t sample_read_data_pos; static uint8_t sample_read_buf[sizeof(sample_read_data)]; @@ -94,6 +94,7 @@ static int sample_target_read_processed(struct i2c_target_config *target_config, return 0; } +#ifdef CONFIG_I2C_TARGET_BUFFER_MODE static void sample_target_buf_write_received(struct i2c_target_config *target_config, uint8_t *data, uint32_t size) @@ -110,6 +111,7 @@ static int sample_target_buf_read_requested(struct i2c_target_config *target_con *size = sizeof(sample_read_data); return 0; } +#endif /* CONFIG_I2C_TARGET_BUFFER_MODE */ static int sample_target_stop(struct i2c_target_config *config) { @@ -122,8 +124,10 @@ static const struct i2c_target_callbacks sample_target_callbacks = { .read_requested = sample_target_read_requested, .write_received = sample_target_write_received, .read_processed = sample_target_read_processed, +#ifdef CONFIG_I2C_TARGET_BUFFER_MODE .buf_write_received = sample_target_buf_write_received, .buf_read_requested = sample_target_buf_read_requested, +#endif .stop = sample_target_stop, }; @@ -172,16 +176,30 @@ static int sample_validate_write_read(void) int ret; if (sample_write_buf_pos != sizeof(sample_write_data)) { + printk("Posittion error: %zu != %zu\n", + sample_write_buf_pos, sizeof(sample_write_data)); return -EIO; } ret = memcmp(sample_write_buf, sample_write_data, sizeof(sample_write_data)); if (ret) { + for (int n = 0; n < sizeof(sample_write_data); n++) { + if (sample_write_buf[n] != sample_write_data[n]) { + printk("Write at offset %u: %02x != %02x\n", + n, sample_write_buf[n], sample_write_data[n]); + } + } return -EIO; } ret = memcmp(sample_read_buf, sample_read_data, sizeof(sample_read_data)); if (ret) { + for (int n = 0; n < sizeof(sample_read_data); n++) { + if (sample_read_buf[n] != sample_read_data[n]) { + printk("Read at offset %u: %02x != %02x\n", + n, sample_read_buf[n], sample_read_data[n]); + } + } return -EIO; } @@ -356,7 +374,15 @@ static int sample_rtio_write_read_async(void) int main(void) { - int ret; + int ret, n; + + for (n = 0; n < sizeof(sample_write_data); n++) { + sample_write_data[n] = (0xFF - n) % 0xFF; + } + + for (n = 0; n < sizeof(sample_read_data); n++) { + sample_read_data[n] = n % 0xFF; + } printk("%s %s\n", "init_i2c_target", "running"); ret = sample_init_i2c_target(); diff --git a/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z.overlay b/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z.overlay index 00c857669bd31..cf9b430e35fe5 100644 --- a/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z.overlay +++ b/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z.overlay @@ -13,4 +13,4 @@ }; }; -target_eeprom: &eeprom0{}; +target_eeprom: &eeprom0 {}; diff --git a/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z512.overlay b/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z512.overlay index 00c857669bd31..cf9b430e35fe5 100644 --- a/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z512.overlay +++ b/samples/drivers/i2c/target_eeprom/boards/frdm_ke17z512.overlay @@ -13,4 +13,4 @@ }; }; -target_eeprom: &eeprom0{}; +target_eeprom: &eeprom0 {}; diff --git a/samples/drivers/i2s/echo/boards/esp32_devkitc_wrover_procpu.overlay b/samples/drivers/i2s/echo/boards/esp32_devkitc_wrover_procpu.overlay index a0eb2eb24cc69..c336dbe8f97f5 100644 --- a/samples/drivers/i2s/echo/boards/esp32_devkitc_wrover_procpu.overlay +++ b/samples/drivers/i2s/echo/boards/esp32_devkitc_wrover_procpu.overlay @@ -7,10 +7,10 @@ &i2s0_default { group1 { pinmux = , - , - , - , - ; + , + , + , + ; output-enable; }; group2 { @@ -23,7 +23,6 @@ i2s_rxtx: &i2s0 { status = "okay"; interrupts = , - ; + ; interrupt-names = "tx", "rx"; - }; diff --git a/samples/drivers/i2s/echo/boards/esp32s2_devkitc.overlay b/samples/drivers/i2s/echo/boards/esp32s2_devkitc.overlay index fca91d46bd570..7e81372d2046d 100644 --- a/samples/drivers/i2s/echo/boards/esp32s2_devkitc.overlay +++ b/samples/drivers/i2s/echo/boards/esp32s2_devkitc.overlay @@ -7,10 +7,10 @@ &i2s0_default { group1 { pinmux = , - , - , - , - ; + , + , + , + ; output-enable; }; group2 { @@ -23,7 +23,6 @@ i2s_rxtx: &i2s0 { status = "okay"; interrupts = , - ; + ; interrupt-names = "tx", "rx"; - }; diff --git a/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay b/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay index de41dcb08d279..5c51f7abc42ff 100644 --- a/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay +++ b/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay @@ -7,9 +7,9 @@ &i2s0_default { group1 { pinmux = , - , - , - ; + , + , + ; output-enable; }; group2 { diff --git a/samples/drivers/i2s/i2s_codec/Kconfig b/samples/drivers/i2s/i2s_codec/Kconfig index 08b66934a0290..f5edd389f1bba 100644 --- a/samples/drivers/i2s/i2s_codec/Kconfig +++ b/samples/drivers/i2s/i2s_codec/Kconfig @@ -5,7 +5,7 @@ source "Kconfig.zephyr" config I2S_INIT_BUFFERS int "Initial count of audio data blocks" - default 2 + default 4 help Controls the initial count of audio data blocks, which are (optionally) filled by data from the DMIC peripheral and played back by the I2S @@ -13,10 +13,18 @@ config I2S_INIT_BUFFERS config SAMPLE_FREQ int "Sample rate" - default 48000 + default 16000 help Sample frequency of the system. +config USE_CODEC_CLOCK + bool "I2S BCK is generated by a selected codec device" + help + If selected, the I2S selected peripheral will be configured to consume + (receive) the I2S BCK and WS signals and the codec will be configured + to generate those. If not selected, the I2S peripheral will generate + them and the codec will be expected to consume them. + config USE_DMIC bool "Use DMIC as an audio input" diff --git a/samples/drivers/i2s/i2s_codec/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf b/samples/drivers/i2s/i2s_codec/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf index 9e510b56da57a..53f0b7dc69cd4 100644 --- a/samples/drivers/i2s/i2s_codec/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf +++ b/samples/drivers/i2s/i2s_codec/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf @@ -4,8 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_HEAP_MEM_POOL_SIZE=81920 -CONFIG_AUDIO_CODEC=y CONFIG_DMA_TCD_QUEUE_SIZE=4 -CONFIG_SAMPLE_FREQ=16000 CONFIG_USE_DMIC=n diff --git a/samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7.conf b/samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7.conf index 9e510b56da57a..53f0b7dc69cd4 100644 --- a/samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7.conf +++ b/samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7.conf @@ -4,8 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_HEAP_MEM_POOL_SIZE=81920 -CONFIG_AUDIO_CODEC=y CONFIG_DMA_TCD_QUEUE_SIZE=4 -CONFIG_SAMPLE_FREQ=16000 CONFIG_USE_DMIC=n diff --git a/samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay similarity index 100% rename from samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay rename to samples/drivers/i2s/i2s_codec/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay diff --git a/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.conf b/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.conf index 7af9fce92a432..2dac479916bca 100644 --- a/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.conf +++ b/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.conf @@ -1,16 +1,9 @@ # -# Copyright 2024 NXP +# Copyright 2024, 2025 NXP # # SPDX-License-Identifier: Apache-2.0 # -CONFIG_DMA=y -CONFIG_I2S_MCUX_FLEXCOMM=y CONFIG_I3C=y -CONFIG_HEAP_MEM_POOL_SIZE=81920 -CONFIG_AUDIO=y -CONFIG_AUDIO_CODEC=y -CONFIG_AUDIO_CODEC_WM8904=y -CONFIG_I2S_INIT_BUFFERS=4 -CONFIG_SAMPLE_FREQ=16000 CONFIG_USE_DMIC=y +CONFIG_USE_CODEC_CLOCK=y diff --git a/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.overlay b/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.overlay index 022fff64aaab6..acee8d8110353 100644 --- a/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.overlay +++ b/samples/drivers/i2s/i2s_codec/boards/mimxrt595_evk_mimxrt595s_cm33.overlay @@ -1,3 +1,9 @@ +/* + * Copyright 2024, 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + / { aliases { i2s-codec-rx = &i2s0; diff --git a/samples/drivers/i2s/i2s_codec/boards/mimxrt685_evk_mimxrt685s_cm33.conf b/samples/drivers/i2s/i2s_codec/boards/mimxrt685_evk_mimxrt685s_cm33.conf index 7af9fce92a432..2dac479916bca 100644 --- a/samples/drivers/i2s/i2s_codec/boards/mimxrt685_evk_mimxrt685s_cm33.conf +++ b/samples/drivers/i2s/i2s_codec/boards/mimxrt685_evk_mimxrt685s_cm33.conf @@ -1,16 +1,9 @@ # -# Copyright 2024 NXP +# Copyright 2024, 2025 NXP # # SPDX-License-Identifier: Apache-2.0 # -CONFIG_DMA=y -CONFIG_I2S_MCUX_FLEXCOMM=y CONFIG_I3C=y -CONFIG_HEAP_MEM_POOL_SIZE=81920 -CONFIG_AUDIO=y -CONFIG_AUDIO_CODEC=y -CONFIG_AUDIO_CODEC_WM8904=y -CONFIG_I2S_INIT_BUFFERS=4 -CONFIG_SAMPLE_FREQ=16000 CONFIG_USE_DMIC=y +CONFIG_USE_CODEC_CLOCK=y diff --git a/samples/drivers/i2s/i2s_codec/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/samples/drivers/i2s/i2s_codec/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf index 9e510b56da57a..53f0b7dc69cd4 100644 --- a/samples/drivers/i2s/i2s_codec/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf +++ b/samples/drivers/i2s/i2s_codec/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf @@ -4,8 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_HEAP_MEM_POOL_SIZE=81920 -CONFIG_AUDIO_CODEC=y CONFIG_DMA_TCD_QUEUE_SIZE=4 -CONFIG_SAMPLE_FREQ=16000 CONFIG_USE_DMIC=n diff --git a/samples/drivers/i2s/i2s_codec/prj.conf b/samples/drivers/i2s/i2s_codec/prj.conf index 683caf4f58709..3ae0329c89d22 100644 --- a/samples/drivers/i2s/i2s_codec/prj.conf +++ b/samples/drivers/i2s/i2s_codec/prj.conf @@ -1,3 +1,4 @@ CONFIG_I2S=y CONFIG_AUDIO=y CONFIG_AUDIO_DMIC=y +CONFIG_AUDIO_CODEC=y diff --git a/samples/drivers/i2s/i2s_codec/src/main.c b/samples/drivers/i2s/i2s_codec/src/main.c index 272ae92c009c1..edef0c9f07994 100644 --- a/samples/drivers/i2s/i2s_codec/src/main.c +++ b/samples/drivers/i2s/i2s_codec/src/main.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #ifndef CONFIG_USE_DMIC @@ -32,7 +33,8 @@ #define BLOCK_SIZE (BYTES_PER_SAMPLE * SAMPLES_PER_BLOCK) #define BLOCK_COUNT (INITIAL_BLOCKS + 32) -K_MEM_SLAB_DEFINE_STATIC(mem_slab, BLOCK_SIZE, BLOCK_COUNT, 4); + +K_MEM_SLAB_DEFINE_IN_SECT_STATIC(mem_slab, __nocache, BLOCK_SIZE, BLOCK_COUNT, 4); static bool configure_tx_streams(const struct device *i2s_dev, struct i2s_config *config) { @@ -116,7 +118,11 @@ int main(void) audio_cfg.dai_cfg.i2s.word_size = SAMPLE_BIT_WIDTH; audio_cfg.dai_cfg.i2s.channels = 2; audio_cfg.dai_cfg.i2s.format = I2S_FMT_DATA_FORMAT_I2S; - audio_cfg.dai_cfg.i2s.options = I2S_OPT_FRAME_CLK_MASTER; +#ifdef CONFIG_USE_CODEC_CLOCK + audio_cfg.dai_cfg.i2s.options = I2S_OPT_FRAME_CLK_MASTER | I2S_OPT_BIT_CLK_MASTER; +#else + audio_cfg.dai_cfg.i2s.options = I2S_OPT_FRAME_CLK_SLAVE | I2S_OPT_BIT_CLK_SLAVE; +#endif audio_cfg.dai_cfg.i2s.frame_clk_freq = SAMPLE_FREQUENCY; audio_cfg.dai_cfg.i2s.mem_slab = &mem_slab; audio_cfg.dai_cfg.i2s.block_size = BLOCK_SIZE; @@ -126,7 +132,7 @@ int main(void) #if CONFIG_USE_DMIC cfg.channel.req_num_chan = 2; cfg.channel.req_chan_map_lo = dmic_build_channel_map(0, 0, PDM_CHAN_LEFT) | - dmic_build_channel_map(1, 0, PDM_CHAN_RIGHT); + dmic_build_channel_map(1, 1, PDM_CHAN_RIGHT); cfg.streams[0].pcm_rate = SAMPLE_FREQUENCY; cfg.streams[0].block_size = BLOCK_SIZE; @@ -143,7 +149,11 @@ int main(void) config.word_size = SAMPLE_BIT_WIDTH; config.channels = NUMBER_OF_CHANNELS; config.format = I2S_FMT_DATA_FORMAT_I2S; +#ifdef CONFIG_USE_CODEC_CLOCK + config.options = I2S_OPT_BIT_CLK_SLAVE | I2S_OPT_FRAME_CLK_SLAVE; +#else config.options = I2S_OPT_BIT_CLK_MASTER | I2S_OPT_FRAME_CLK_MASTER; +#endif config.frame_clk_freq = SAMPLE_FREQUENCY; config.mem_slab = &mem_slab; config.block_size = BLOCK_SIZE; @@ -168,7 +178,7 @@ int main(void) uint32_t block_size = BLOCK_SIZE; int i; - for (i = 0; i < 2; i++) { + for (i = 0; i < CONFIG_I2S_INIT_BUFFERS; i++) { #if CONFIG_USE_DMIC /* If using DMIC, use a buffer (memory slab) from dmic_read */ ret = dmic_read(dmic_dev, 0, &mem_block, &block_size, TIMEOUT); @@ -180,8 +190,12 @@ int main(void) ret = i2s_write(i2s_dev_codec, mem_block, block_size); #else /* If not using DMIC, play a sine wave 440Hz */ + + BUILD_ASSERT( + BLOCK_SIZE <= __16kHz16bit_stereo_sine_pcm_len, + "BLOCK_SIZE is bigger than test sine wave buffer size." + ); mem_block = (void *)&__16kHz16bit_stereo_sine_pcm; - block_size = __16kHz16bit_stereo_sine_pcm_len; ret = i2s_buf_write(i2s_dev_codec, mem_block, block_size); #endif diff --git a/samples/drivers/i2s/i2s_codec/src/sine.h b/samples/drivers/i2s/i2s_codec/src/sine.h index 467b8177a4c16..99dfd1d0e90fe 100644 --- a/samples/drivers/i2s/i2s_codec/src/sine.h +++ b/samples/drivers/i2s/i2s_codec/src/sine.h @@ -444,6 +444,6 @@ unsigned char __16kHz16bit_stereo_sine_pcm[] = { 0xa3, 0xc0, 0xa3, 0xc0, 0xdb, 0xbf, 0xdb, 0xbf, 0xfc, 0xc0, 0xfc, 0xc0, 0xfd, 0xc3, 0xfd, 0xc3, 0xc8, 0xc8, 0xc8, 0xc8, 0x38, 0xcf, 0x38, 0xcf, 0x1c, 0xd7, 0x1c, 0xd7, 0x37, 0xe0, 0x37, 0xe0, 0x45, 0xea, 0x45, 0xea, 0xf8, 0xf4, 0xf8, 0xf4}; -unsigned int __16kHz16bit_stereo_sine_pcm_len = 6400; +const unsigned int __16kHz16bit_stereo_sine_pcm_len = sizeof(__16kHz16bit_stereo_sine_pcm); #endif /* SINE_H_ */ diff --git a/samples/drivers/i2s/output/boards/ek_ra4l1.overlay b/samples/drivers/i2s/output/boards/ek_ra4l1.overlay index 368494deedfb9..1defb4623979f 100644 --- a/samples/drivers/i2s/output/boards/ek_ra4l1.overlay +++ b/samples/drivers/i2s/output/boards/ek_ra4l1.overlay @@ -17,9 +17,9 @@ group1 { /* SSI_BCK SSI_LRCK SSI_TX SSI_RX */ psels = , - , - , - ; + , + , + ; drive-strength = "high"; }; }; diff --git a/samples/drivers/i2s/output/boards/esp32_devkitc_wrover_procpu.overlay b/samples/drivers/i2s/output/boards/esp32_devkitc_wrover_procpu.overlay index ee5fa6e31d570..fd9aa4c1959f2 100644 --- a/samples/drivers/i2s/output/boards/esp32_devkitc_wrover_procpu.overlay +++ b/samples/drivers/i2s/output/boards/esp32_devkitc_wrover_procpu.overlay @@ -13,8 +13,8 @@ &i2s0_default { group1 { pinmux = , - , - ; + , + ; output-enable; }; group2 { diff --git a/samples/drivers/i2s/output/boards/nucleo_h563zi.overlay b/samples/drivers/i2s/output/boards/nucleo_h563zi.overlay index 561db541c6ee2..339b44179f8fd 100644 --- a/samples/drivers/i2s/output/boards/nucleo_h563zi.overlay +++ b/samples/drivers/i2s/output/boards/nucleo_h563zi.overlay @@ -24,7 +24,7 @@ &sai1_a { pinctrl-0 = <&sai1_mclk_a_pe2 &sai1_sd_a_pe6 - &sai1_fs_a_pe4 &sai1_sck_a_pe5>; + &sai1_fs_a_pe4 &sai1_sck_a_pe5>; pinctrl-names = "default"; status = "okay"; mclk-enable; diff --git a/samples/drivers/i2s/output/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay b/samples/drivers/i2s/output/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay index 0821cd243d697..779a173f05b18 100644 --- a/samples/drivers/i2s/output/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay +++ b/samples/drivers/i2s/output/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay @@ -24,7 +24,7 @@ &sai1_b { pinctrl-0 = <&sai1_mclk_b_pf7 &sai1_sd_b_pe3 - &sai1_fs_b_pf9 &sai1_sck_b_pf8>; + &sai1_fs_b_pf9 &sai1_sck_b_pf8>; pinctrl-names = "default"; status = "okay"; mclk-enable; @@ -32,10 +32,10 @@ dma-names = "tx"; }; -&dmamux1{ +&dmamux1 { status = "okay"; }; -&dma1{ +&dma1 { status = "okay"; }; diff --git a/samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay b/samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay index 02547dcf5c8b2..7fcc6200eb527 100644 --- a/samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay +++ b/samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay @@ -26,7 +26,7 @@ &sai1_a { pinctrl-0 = <&sai1_mclk_a_pg7 &sai1_sd_a_pc1 - &sai1_fs_a_pe4 &sai1_sck_a_pe5>; + &sai1_fs_a_pe4 &sai1_sck_a_pe5>; pinctrl-names = "default"; status = "okay"; mclk-enable; diff --git a/samples/drivers/i2s/output/boards/nucleo_l432kc.conf b/samples/drivers/i2s/output/boards/nucleo_l432kc.conf new file mode 100644 index 0000000000000..4f3f73a1e06a5 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_l432kc.conf @@ -0,0 +1 @@ +CONFIG_HEAP_MEM_POOL_SIZE=4192 diff --git a/samples/drivers/i2s/output/boards/nucleo_l432kc.overlay b/samples/drivers/i2s/output/boards/nucleo_l432kc.overlay new file mode 100644 index 0000000000000..994083d1ad7b7 --- /dev/null +++ b/samples/drivers/i2s/output/boards/nucleo_l432kc.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2s-tx = &sai1_a; + }; +}; + +/* 44.27KHz (0.38% Error) */ +&pllsai1 { + div-m = <1>; + mul-n = <17>; + div-r = <2>; + div-q = <2>; + div-p = <12>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&sai1_a { + pinctrl-0 = <&sai1_mclk_a_pa3 &sai1_sd_a_pa10 + &sai1_fs_a_pa9 &sai1_sck_a_pa8>; + pinctrl-names = "default"; + status = "okay"; + mclk-enable; + mclk-divider = "div-256"; + dma-names = "tx"; +}; + +/* USART1 TX conflicts with SAI1_A FS */ +&usart1 { + status = "disabled"; +}; diff --git a/samples/drivers/i2s/output/boards/nucleo_u385rg_q.overlay b/samples/drivers/i2s/output/boards/nucleo_u385rg_q.overlay index 5a582a004957d..942ad61f623bb 100644 --- a/samples/drivers/i2s/output/boards/nucleo_u385rg_q.overlay +++ b/samples/drivers/i2s/output/boards/nucleo_u385rg_q.overlay @@ -19,7 +19,7 @@ /* 46.875KHz (6.29% Error) */ &sai1_a { pinctrl-0 = <&sai1_mclk_a_pb8 &sai1_sd_a_pc1 - &sai1_fs_a_pa9 &sai1_sck_a_pb10>; + &sai1_fs_a_pa9 &sai1_sck_a_pb10>; pinctrl-names = "default"; status = "okay"; mclk-enable; @@ -31,7 +31,7 @@ status = "okay"; }; -&clk_msik{ +&clk_msik { status = "okay"; }; diff --git a/samples/drivers/i2s/output/boards/nucleo_u575zi_q.overlay b/samples/drivers/i2s/output/boards/nucleo_u575zi_q.overlay index 2171362dce639..3a3a9e6e77f27 100644 --- a/samples/drivers/i2s/output/boards/nucleo_u575zi_q.overlay +++ b/samples/drivers/i2s/output/boards/nucleo_u575zi_q.overlay @@ -24,7 +24,7 @@ &sai1_a { pinctrl-0 = <&sai1_mclk_a_pe2 &sai1_sd_a_pe6 - &sai1_fs_a_pe4 &sai1_sck_a_pe5>; + &sai1_fs_a_pe4 &sai1_sck_a_pe5>; pinctrl-names = "default"; status = "okay"; mclk-enable; diff --git a/samples/drivers/i2s/output/boards/siwx917_dk2605a.overlay b/samples/drivers/i2s/output/boards/siwx917_dk2605a.overlay index e62a1478d97ea..b02fd845a9c58 100644 --- a/samples/drivers/i2s/output/boards/siwx917_dk2605a.overlay +++ b/samples/drivers/i2s/output/boards/siwx917_dk2605a.overlay @@ -28,7 +28,7 @@ pinctrl-0 = <&i2s0_default>; pinctrl-names = "default"; - dmas = <&dma0 15>, <&dma0 14>; + dmas = <&dma0 15>, <&dma0 14>; dma-names = "tx", "rx"; }; diff --git a/samples/drivers/i2s/output/boards/siwx917_rb4338a.overlay b/samples/drivers/i2s/output/boards/siwx917_rb4338a.overlay index 2de71dd555843..e9c1561bcfa38 100644 --- a/samples/drivers/i2s/output/boards/siwx917_rb4338a.overlay +++ b/samples/drivers/i2s/output/boards/siwx917_rb4338a.overlay @@ -28,7 +28,7 @@ pinctrl-0 = <&i2s0_default>; pinctrl-names = "default"; - dmas = <&dma0 15>, <&dma0 14>; + dmas = <&dma0 15>, <&dma0 14>; dma-names = "tx", "rx"; }; diff --git a/samples/drivers/ipm/ipm_ivshmem/boards/qemu_cortex_a53.overlay b/samples/drivers/ipm/ipm_ivshmem/boards/qemu_cortex_a53.overlay index fbf15043fe07c..adf646ed0f590 100644 --- a/samples/drivers/ipm/ipm_ivshmem/boards/qemu_cortex_a53.overlay +++ b/samples/drivers/ipm/ipm_ivshmem/boards/qemu_cortex_a53.overlay @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ - #include "pcie_ivshmem.dtsi" +#include "pcie_ivshmem.dtsi" / { ipm_ivshmem0: ipm_ivshmem { diff --git a/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay b/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay index e9bbc3fbf379a..baec87ef83a6d 100644 --- a/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay +++ b/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay @@ -24,7 +24,7 @@ pinctrl-0 = <&spi2_default>; pinctrl-1 = <&spi2_sleep>; pinctrl-names = "default", "sleep"; - mx25r64: mx25r6435f@0 { + mx25r64: mx25r6435f@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <8000000>; diff --git a/samples/drivers/jesd216/src/main.c b/samples/drivers/jesd216/src/main.c index 9d5374ed1ed22..4b6e4cf5c1fcc 100644 --- a/samples/drivers/jesd216/src/main.c +++ b/samples/drivers/jesd216/src/main.c @@ -32,6 +32,8 @@ #define FLASH_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_imx_flexspi_nor) #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_ospi_b_nor) #define FLASH_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_ospi_b_nor) +#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_qspi_nor) +#define FLASH_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_qspi_nor) #else #error Unsupported flash driver #define FLASH_NODE DT_INVALID_NODE diff --git a/samples/drivers/led/led_strip/boards/adafruit_feather_esp32_procpu.conf b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32_procpu.conf new file mode 100644 index 0000000000000..8230eb9896b4f --- /dev/null +++ b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32_procpu.conf @@ -0,0 +1,2 @@ +CONFIG_GPIO=y +CONFIG_GPIO_HOGS=y diff --git a/samples/drivers/led/led_strip/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/drivers/led/led_strip/boards/nrf5340dk_nrf5340_cpuapp.overlay index a20d535bbab71..328bf6f48634e 100644 --- a/samples/drivers/led/led_strip/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/drivers/led/led_strip/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -23,8 +23,8 @@ i2s_led: &i2s0 { reg = <0>; chain-length = <42>; /* arbitrary; change at will */ color-mapping = ; + LED_COLOR_ID_RED + LED_COLOR_ID_BLUE>; reset-delay = <500>; }; }; diff --git a/samples/drivers/led/led_strip/boards/nucleo_f070rb.overlay b/samples/drivers/led/led_strip/boards/nucleo_f070rb.overlay index 7fa4a1e2b2db0..012aced7bdfc0 100644 --- a/samples/drivers/led/led_strip/boards/nucleo_f070rb.overlay +++ b/samples/drivers/led/led_strip/boards/nucleo_f070rb.overlay @@ -10,7 +10,7 @@ &spi1 { /* MOSI on PA7 */ dmas = <&dma1 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>, - <&dma1 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; + <&dma1 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; led_strip: b1414@0 { diff --git a/samples/drivers/led/led_strip/boards/thingy52_nrf52832.overlay b/samples/drivers/led/led_strip/boards/thingy52_nrf52832.overlay index 28c28be60c7ef..67ee1ccd40b8c 100644 --- a/samples/drivers/led/led_strip/boards/thingy52_nrf52832.overlay +++ b/samples/drivers/led/led_strip/boards/thingy52_nrf52832.overlay @@ -28,8 +28,8 @@ i2s_led: &i2s0 { reg = <0>; chain-length = <10>; /* arbitrary; change at will */ color-mapping = ; + LED_COLOR_ID_RED + LED_COLOR_ID_BLUE>; out-active-low; reset-delay = <120>; }; diff --git a/samples/drivers/led/lp50xx/boards/lpcxpresso11u68.overlay b/samples/drivers/led/lp50xx/boards/lpcxpresso11u68.overlay index 8a081efdc41e1..2dcb814d99eae 100644 --- a/samples/drivers/led/lp50xx/boards/lpcxpresso11u68.overlay +++ b/samples/drivers/led/lp50xx/boards/lpcxpresso11u68.overlay @@ -16,82 +16,72 @@ led_0 { label = "LED LP5030 0"; index = <0>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_1 { label = "LED LP5030 1"; index = <1>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_2 { label = "LED LP5030 2"; index = <2>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_3 { label = "LED LP5030 3"; index = <3>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_4 { label = "LED LP5030 4"; index = <4>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_5 { label = "LED LP5030 5"; index = <5>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_6 { label = "LED LP5030 6"; index = <6>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_7 { label = "LED LP5030 7"; index = <7>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_8 { label = "LED LP5030 8"; index = <8>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; led_9 { label = "LED LP5030 9"; index = <9>; - color-mapping = - , - , - ; + color-mapping = , + , + ; }; }; }; diff --git a/samples/drivers/lora/receive/README.rst b/samples/drivers/lora/receive/README.rst index 1a2bcf6cd4776..9acc3a262d20b 100644 --- a/samples/drivers/lora/receive/README.rst +++ b/samples/drivers/lora/receive/README.rst @@ -1,6 +1,6 @@ .. zephyr:code-sample:: lora-receive :name: LoRa receive - :relevant-api: lora_api + :relevant-api: lora_interface Receive packets in both synchronous and asynchronous mode using the LoRa radio. diff --git a/samples/drivers/lora/receive/sample.yaml b/samples/drivers/lora/receive/sample.yaml index 93e070db46ca5..c4f115312ab56 100644 --- a/samples/drivers/lora/receive/sample.yaml +++ b/samples/drivers/lora/receive/sample.yaml @@ -1,15 +1,25 @@ common: tags: lora depends_on: lora + harness: console + harness_config: + type: one_line + regex: + - " lora_receive: Synchronous reception" sample: description: Demonstration of LoRa Receive functionality name: LoRa Receive Sample tests: sample.driver.lora.receive: - harness: console - harness_config: - type: one_line - regex: - - " lora_receive: Synchronous reception" integration_platforms: - b_l072z_lrwan1 + sample.driver.lora.receive.lbm: + filter: dt_compat_enabled("semtech,sx1261") or + dt_compat_enabled("semtech,sx1262") or + dt_compat_enabled("semtech,sx1272") or + dt_compat_enabled("semtech,sx1276") + integration_platforms: + - b_l072z_lrwan1 + - rak11720 + extra_configs: + - CONFIG_LORA_MODULE_BACKEND_LORA_BASICS_MODEM=y diff --git a/samples/drivers/lora/send/README.rst b/samples/drivers/lora/send/README.rst index ef48a215d6880..69865b046f88d 100644 --- a/samples/drivers/lora/send/README.rst +++ b/samples/drivers/lora/send/README.rst @@ -1,6 +1,6 @@ .. zephyr:code-sample:: lora-send :name: LoRa send - :relevant-api: lora_api + :relevant-api: lora_interface Transmit a preconfigured payload every second using the LoRa radio. diff --git a/samples/drivers/lora/send/sample.yaml b/samples/drivers/lora/send/sample.yaml index 871143405bf47..a4af9b7405f14 100644 --- a/samples/drivers/lora/send/sample.yaml +++ b/samples/drivers/lora/send/sample.yaml @@ -1,15 +1,25 @@ common: tags: lora depends_on: lora + harness: console + harness_config: + type: one_line + regex: + - " lora_send: Data sent 0!" sample: description: Demonstration of LoRa Send functionality name: LoRa Send Sample tests: sample.driver.lora.send: - harness: console - harness_config: - type: one_line - regex: - - " lora_send: Data sent 0!" integration_platforms: - b_l072z_lrwan1 + sample.driver.lora.send.lbm: + filter: dt_compat_enabled("semtech,sx1261") or + dt_compat_enabled("semtech,sx1262") or + dt_compat_enabled("semtech,sx1272") or + dt_compat_enabled("semtech,sx1276") + integration_platforms: + - b_l072z_lrwan1 + - rak11720 + extra_configs: + - CONFIG_LORA_MODULE_BACKEND_LORA_BASICS_MODEM=y diff --git a/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index dea949213a5d3..e02fb726cb9a6 100644 --- a/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mailbox0@5008b000 { + mbox: mailbox0@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; diff --git a/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 5113882e1bc2d..3190ae476df42 100644 --- a/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay index 5113882e1bc2d..3190ae476df42 100644 --- a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay +++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay index 689cf0e39775a..6c40b6b4e2868 100644 --- a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay +++ b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay @@ -19,7 +19,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mbox@5008b000 { + mbox: mbox@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 0d15908a63c14..488f7bbe244a1 100644 --- a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 0d15908a63c14..488f7bbe244a1 100644 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 56d26cc1b598e..488f7bbe244a1 100644 --- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; @@ -46,7 +46,6 @@ mboxes = <&mbox 0>, <&mbox 1>; mbox-names = "tx", "rx"; }; - }; /* Disable primary GPT timer */ diff --git a/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index eafeeb83cbaa1..df5656467da2b 100644 --- a/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mailbox0@5008b000 { + mbox: mailbox0@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; diff --git a/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 0ed27fea4f30a..871c5f6cdbd00 100644 --- a/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay index 0ed27fea4f30a..871c5f6cdbd00 100644 --- a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay +++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay index 5f623200d9e09..2b183cbb148a0 100644 --- a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay +++ b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mbox@5008b000 { + mbox: mbox@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index cb93c8b88cb5f..5600e90343f06 100644 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index cb93c8b88cb5f..5600e90343f06 100644 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index cb93c8b88cb5f..5600e90343f06 100644 --- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/drivers/memc/boards/apollo3p_evb.overlay b/samples/drivers/memc/boards/apollo3p_evb.overlay index 7f4aa712d3dda..5328d6af2dfd3 100644 --- a/samples/drivers/memc/boards/apollo3p_evb.overlay +++ b/samples/drivers/memc/boards/apollo3p_evb.overlay @@ -23,7 +23,7 @@ pinctrl-0 = <&mspi1_default>; pinctrl-1 = <&mspi1_sleep>; pinctrl-2 = <&mspi1_psram>; - pinctrl-names = "default","sleep","psram"; + pinctrl-names = "default", "sleep", "psram"; status = "okay"; ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>, @@ -52,12 +52,11 @@ ambiq,timing-config-mask = <3>; ambiq,timing-config = <0 6 0 0 0 0 0 0>; }; - }; &pinctrl { - mspi1_sleep: mspi1_sleep{ + mspi1_sleep: mspi1_sleep { group1 { pinmux = , @@ -72,10 +71,9 @@ , ; }; - }; - mspi1_psram: mspi1_psram{ + mspi1_psram: mspi1_psram { group1 { pinmux = , diff --git a/samples/drivers/memc/boards/frdm_rw612.overlay b/samples/drivers/memc/boards/frdm_rw612.overlay index 88b2498e592fa..e5ad779997a51 100644 --- a/samples/drivers/memc/boards/frdm_rw612.overlay +++ b/samples/drivers/memc/boards/frdm_rw612.overlay @@ -26,11 +26,11 @@ pinmux_flexspi_safe: pinmux-flexspi-safe { group0 { pinmux = ; + IO_MUX_QUAD_SPI_PSRAM_IO36 + IO_MUX_QUAD_SPI_PSRAM_IO38 + IO_MUX_QUAD_SPI_PSRAM_IO39 + IO_MUX_QUAD_SPI_PSRAM_IO40 + IO_MUX_QUAD_SPI_PSRAM_IO41>; slew-rate = "normal"; }; diff --git a/samples/drivers/memc/boards/rd_rw612_bga.overlay b/samples/drivers/memc/boards/rd_rw612_bga.overlay index e32be713e3b88..affdcb0b265bd 100644 --- a/samples/drivers/memc/boards/rd_rw612_bga.overlay +++ b/samples/drivers/memc/boards/rd_rw612_bga.overlay @@ -18,11 +18,11 @@ pinmux_flexspi_safe: pinmux-flexspi-safe { group0 { pinmux = ; + IO_MUX_QUAD_SPI_PSRAM_IO36 + IO_MUX_QUAD_SPI_PSRAM_IO38 + IO_MUX_QUAD_SPI_PSRAM_IO39 + IO_MUX_QUAD_SPI_PSRAM_IO40 + IO_MUX_QUAD_SPI_PSRAM_IO41>; slew-rate = "normal"; }; diff --git a/samples/drivers/mspi/mspi_async/boards/apollo3p_evb.overlay b/samples/drivers/mspi/mspi_async/boards/apollo3p_evb.overlay index 9f0aebd4ddb2f..daaa13dd24a66 100644 --- a/samples/drivers/mspi/mspi_async/boards/apollo3p_evb.overlay +++ b/samples/drivers/mspi/mspi_async/boards/apollo3p_evb.overlay @@ -23,7 +23,7 @@ pinctrl-0 = <&mspi1_default>; pinctrl-1 = <&mspi1_sleep>; pinctrl-2 = <&mspi1_psram>; - pinctrl-names = "default","sleep","psram"; + pinctrl-names = "default", "sleep", "psram"; status = "okay"; ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>, @@ -52,12 +52,11 @@ ambiq,timing-config-mask = <3>; ambiq,timing-config = <0 6 0 0 0 0 0 0>; }; - }; &pinctrl { - mspi1_sleep: mspi1_sleep{ + mspi1_sleep: mspi1_sleep { group1 { pinmux = , @@ -72,10 +71,9 @@ , ; }; - }; - mspi1_psram: mspi1_psram{ + mspi1_psram: mspi1_psram { group1 { pinmux = , diff --git a/samples/drivers/mspi/mspi_flash/boards/apollo3p_evb.overlay b/samples/drivers/mspi/mspi_flash/boards/apollo3p_evb.overlay index 0602c4be679dd..73235869a3106 100644 --- a/samples/drivers/mspi/mspi_flash/boards/apollo3p_evb.overlay +++ b/samples/drivers/mspi/mspi_flash/boards/apollo3p_evb.overlay @@ -24,7 +24,7 @@ pinctrl-1 = <&mspi1_sleep>; pinctrl-2 = <&mspi1_psram>; pinctrl-3 = <&mspi1_flash>; - pinctrl-names = "default","sleep","psram","flash"; + pinctrl-names = "default", "sleep", "psram", "flash"; status = "okay"; ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>, @@ -74,12 +74,11 @@ ambiq,timing-config-mask = <3>; ambiq,timing-config = <0 8 0 0 0 0 0 0>; }; - }; &pinctrl { - mspi1_sleep: mspi1_sleep{ + mspi1_sleep: mspi1_sleep { group1 { pinmux = , @@ -94,10 +93,9 @@ , ; }; - }; - mspi1_psram: mspi1_psram{ + mspi1_psram: mspi1_psram { group1 { pinmux = , @@ -130,20 +128,19 @@ group4 { pinmux = ; }; - }; - mspi1_flash: mspi1_flash{ + mspi1_flash: mspi1_flash { group1 { pinmux = , - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; drive-strength = "0.75"; ambiq,iom-mspi = <0>; ambiq,iom-num = <1>; @@ -166,6 +163,5 @@ group4 { pinmux = ; }; - }; }; diff --git a/samples/drivers/rtc/sample.yaml b/samples/drivers/rtc/sample.yaml index 2d57ba0fff0e3..26b3397a6b116 100644 --- a/samples/drivers/rtc/sample.yaml +++ b/samples/drivers/rtc/sample.yaml @@ -6,8 +6,11 @@ tests: - stm32f3_disco - mimxrt700_evk/mimxrt798s/cm33_cpu0 - mimxrt700_evk/mimxrt798s/cm33_cpu1 + - adafruit_qt_py_rp2040/rp2040 integration_platforms: - stm32f3_disco + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="sparkfun_rv8803" tags: - samples - rtc diff --git a/samples/drivers/spi_bitbang/boards/nrf52840dk_nrf52840.overlay b/samples/drivers/spi_bitbang/boards/nrf52840dk_nrf52840.overlay index 33d6ca513595b..3a3a729bbf6da 100644 --- a/samples/drivers/spi_bitbang/boards/nrf52840dk_nrf52840.overlay +++ b/samples/drivers/spi_bitbang/boards/nrf52840dk_nrf52840.overlay @@ -7,7 +7,7 @@ / { spibb0: spibb0 { compatible = "zephyr,spi-bitbang"; - status="okay"; + status = "okay"; #address-cells = <1>; #size-cells = <0>; clk-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; diff --git a/samples/drivers/spi_bitbang/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/drivers/spi_bitbang/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 255834ffd9a5f..6d05985d1d9bb 100644 --- a/samples/drivers/spi_bitbang/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/samples/drivers/spi_bitbang/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -12,7 +12,7 @@ / { spibb0: spibb0 { compatible = "zephyr,spi-bitbang"; - status="okay"; + status = "okay"; #address-cells = <1>; #size-cells = <0>; clk-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; diff --git a/samples/drivers/spi_bitbang/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/samples/drivers/spi_bitbang/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index 6a35bb70f9ec4..0595c5a15bde6 100644 --- a/samples/drivers/spi_bitbang/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/samples/drivers/spi_bitbang/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -12,7 +12,7 @@ / { spibb0: spibb0 { compatible = "zephyr,spi-bitbang"; - status="okay"; + status = "okay"; #address-cells = <1>; #size-cells = <0>; clk-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; diff --git a/samples/drivers/spi_bitbang/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay b/samples/drivers/spi_bitbang/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay index 9a27384fc40d5..6afc29a382abe 100644 --- a/samples/drivers/spi_bitbang/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay +++ b/samples/drivers/spi_bitbang/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay @@ -12,7 +12,7 @@ / { spibb0: spibb0 { compatible = "zephyr,spi-bitbang"; - status="okay"; + status = "okay"; #address-cells = <1>; #size-cells = <0>; clk-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; diff --git a/samples/drivers/spi_flash/boards/blackpill_f411ce.overlay b/samples/drivers/spi_flash/boards/blackpill_f411ce.overlay index d4c0e4c1482e9..37aa6d9ca91c3 100644 --- a/samples/drivers/spi_flash/boards/blackpill_f411ce.overlay +++ b/samples/drivers/spi_flash/boards/blackpill_f411ce.overlay @@ -12,7 +12,7 @@ */ &spi1 { - pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pb4 &spi1_mosi_pa7>; + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pb4 &spi1_mosi_pa7>; pinctrl-names = "default"; cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; diff --git a/samples/drivers/spi_flash/boards/mec172xevb_assy6906.overlay b/samples/drivers/spi_flash/boards/mec172xevb_assy6906.overlay index 54f2957791cc3..24e403df376a8 100644 --- a/samples/drivers/spi_flash/boards/mec172xevb_assy6906.overlay +++ b/samples/drivers/spi_flash/boards/mec172xevb_assy6906.overlay @@ -11,12 +11,12 @@ lines = <4>; chip-select = <0>; - pinctrl-0 = < &shd_cs0_n_gpio055 - &shd_clk_gpio056 - &shd_io0_gpio223 - &shd_io1_gpio224 - &shd_io2_gpio227 - &shd_io3_gpio016 >; + pinctrl-0 = <&shd_cs0_n_gpio055 + &shd_clk_gpio056 + &shd_io0_gpio223 + &shd_io1_gpio224 + &shd_io2_gpio227 + &shd_io3_gpio016>; pinctrl-names = "default"; spi1_cs0_flash: w25q128@0 { diff --git a/samples/drivers/spi_flash/boards/stm32h573i_dk.conf b/samples/drivers/spi_flash/boards/stm32h573i_dk.conf index fbb60e6627f02..fd939e48e605d 100644 --- a/samples/drivers/spi_flash/boards/stm32h573i_dk.conf +++ b/samples/drivers/spi_flash/boards/stm32h573i_dk.conf @@ -1,2 +1,2 @@ CONFIG_LOG=y -CONFIG_STM32_MEMMAP=y +CONFIG_FLASH_LOG_LEVEL_INF=y diff --git a/samples/drivers/spi_flash/sample.yaml b/samples/drivers/spi_flash/sample.yaml index 39d94c905da1c..d17972e95899c 100644 --- a/samples/drivers/spi_flash/sample.yaml +++ b/samples/drivers/spi_flash/sample.yaml @@ -24,6 +24,24 @@ tests: - "Test 2: Flash write" - "Attempting to write 4 bytes" - "Data read matches data written. Good!!" + sample.drivers.spi.flash.stm32.memmap: + filter: dt_compat_enabled("st,stm32-qspi-nor") + or dt_compat_enabled("st,stm32-ospi-nor") + or dt_compat_enabled("st,stm32-xspi-nor") + integration_platforms: + - stm32h573i_dk + extra_configs: + - CONFIG_STM32_MEMMAP=y + harness: console + harness_config: + type: multi_line + ordered: true + regex: + - "Test 1: Flash erase" + - "Flash erase succeeded!" + - "Test 2: Flash write" + - "Attempting to write 4 bytes" + - "Data read matches data written. Good!!" sample.drivers.spi.flash.nrf54lm20: platform_allow: - nrf54lm20dk/nrf54lm20a/cpuapp diff --git a/samples/drivers/spi_flash/src/main.c b/samples/drivers/spi_flash/src/main.c index fd6a09bfacb20..07adf7739becc 100644 --- a/samples/drivers/spi_flash/src/main.c +++ b/samples/drivers/spi_flash/src/main.c @@ -37,8 +37,8 @@ #endif #if defined(CONFIG_FLASH_STM32_OSPI) || defined(CONFIG_FLASH_STM32_QSPI) || \ - defined(CONFIG_FLASH_STM32_XSPI) || defined(CONFIG_FLASH_RENESAS_RA_OSPI_B) - + defined(CONFIG_FLASH_STM32_XSPI) || defined(CONFIG_FLASH_RENESAS_RA_OSPI_B) || \ + defined(CONFIG_FLASH_RENESAS_RA_QSPI) #define SPI_FLASH_MULTI_SECTOR_TEST #endif @@ -56,6 +56,8 @@ #define SPI_FLASH_COMPAT nordic_qspi_nor #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_ospi_b_nor) #define SPI_FLASH_COMPAT renesas_ra_ospi_b_nor +#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_qspi_nor) +#define SPI_FLASH_COMPAT renesas_ra_qspi_nor #else #define SPI_FLASH_COMPAT invalid #endif diff --git a/samples/drivers/stepper/tmc50xx/boards/nucleo_g071rb.overlay b/samples/drivers/stepper/tmc50xx/boards/nucleo_g071rb.overlay index e3b70a3553140..f30c659d44415 100644 --- a/samples/drivers/stepper/tmc50xx/boards/nucleo_g071rb.overlay +++ b/samples/drivers/stepper/tmc50xx/boards/nucleo_g071rb.overlay @@ -28,9 +28,9 @@ /* ADI TMC stallguard settings specific to TMC50XX */ activate-stallguard2; - stallguard-velocity-check-interval-ms=<1000>; - stallguard2-threshold=<30>; - stallguard-threshold-velocity=<200000>; + stallguard-velocity-check-interval-ms = <1000>; + stallguard2-threshold = <30>; + stallguard-threshold-velocity = <200000>; /* ADI TMC ramp generator as well as current settings */ vstart = <1000>; diff --git a/samples/drivers/uart/async_api/boards/cy8cproto_062_4343w.overlay b/samples/drivers/uart/async_api/boards/cy8cproto_062_4343w.overlay index 8ebe004565462..8ddba811bca9c 100644 --- a/samples/drivers/uart/async_api/boards/cy8cproto_062_4343w.overlay +++ b/samples/drivers/uart/async_api/boards/cy8cproto_062_4343w.overlay @@ -13,7 +13,6 @@ input-enable; }; - dut: &scb3 { compatible = "infineon,cat1-uart"; status = "okay"; diff --git a/samples/drivers/uart/async_api/boards/intel_btl_s_crb.overlay b/samples/drivers/uart/async_api/boards/intel_btl_s_crb.overlay index b87bf528edbc6..18214bb6f7c67 100644 --- a/samples/drivers/uart/async_api/boards/intel_btl_s_crb.overlay +++ b/samples/drivers/uart/async_api/boards/intel_btl_s_crb.overlay @@ -4,13 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -&uart0{ +&uart0 { status = "okay"; }; -&uart0_dma{ - status ="okay"; +&uart0_dma { + status = "okay"; }; -/{ +/ { chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; diff --git a/samples/drivers/uart/native_tty/README.rst b/samples/drivers/uart/native_tty/README.rst index b9d938f4089fb..aa3aae3e96990 100644 --- a/samples/drivers/uart/native_tty/README.rst +++ b/samples/drivers/uart/native_tty/README.rst @@ -34,7 +34,7 @@ Requirements Building and Running ******************** -This application can be built and executed on :ref:`native_sim ` as follows: +This application can be built and executed on :zephyr:board:`native_sim ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/uart/native_tty diff --git a/samples/drivers/w1/scanner/boards/max32655evkit_max32655_m4.overlay b/samples/drivers/w1/scanner/boards/max32655evkit_max32655_m4.overlay index b39b6bfd394d3..b8be20635ee41 100644 --- a/samples/drivers/w1/scanner/boards/max32655evkit_max32655_m4.overlay +++ b/samples/drivers/w1/scanner/boards/max32655evkit_max32655_m4.overlay @@ -5,11 +5,11 @@ */ &owm_io_p0_6 { - power-source=; + power-source = ; }; &owm_pe_p0_7 { - power-source=; + power-source = ; }; &w1 { diff --git a/samples/drivers/w1/scanner/boards/max32666evkit_max32666_cpu0.overlay b/samples/drivers/w1/scanner/boards/max32666evkit_max32666_cpu0.overlay index eee8e0fc933f4..728ea5e6b9017 100644 --- a/samples/drivers/w1/scanner/boards/max32666evkit_max32666_cpu0.overlay +++ b/samples/drivers/w1/scanner/boards/max32666evkit_max32666_cpu0.overlay @@ -5,11 +5,11 @@ */ &owm_io_p0_4 { - power-source=; + power-source = ; }; &owm_pe_p0_5 { - power-source=; + power-source = ; }; &w1 { diff --git a/samples/drivers/w1/scanner/boards/max32666fthr_max32666_cpu0.overlay b/samples/drivers/w1/scanner/boards/max32666fthr_max32666_cpu0.overlay index 9060237897645..765f534473bf9 100644 --- a/samples/drivers/w1/scanner/boards/max32666fthr_max32666_cpu0.overlay +++ b/samples/drivers/w1/scanner/boards/max32666fthr_max32666_cpu0.overlay @@ -5,11 +5,11 @@ */ &owm_io_p0_12 { - power-source=; + power-source = ; }; &owm_pe_p0_13 { - power-source=; + power-source = ; }; &w1 { diff --git a/samples/drivers/w1/scanner/boards/max32690evkit_max32690_m4.overlay b/samples/drivers/w1/scanner/boards/max32690evkit_max32690_m4.overlay index 31b91be77b7f1..8c5884de7048b 100644 --- a/samples/drivers/w1/scanner/boards/max32690evkit_max32690_m4.overlay +++ b/samples/drivers/w1/scanner/boards/max32690evkit_max32690_m4.overlay @@ -5,11 +5,11 @@ */ &owm_io_p0_8 { - power-source=; + power-source = ; }; &owm_pe_p0_7 { - power-source=; + power-source = ; }; &w1 { diff --git a/samples/drivers/w1/scanner/boards/max78000evkit_max78000_m4.overlay b/samples/drivers/w1/scanner/boards/max78000evkit_max78000_m4.overlay index 933dd2f3de9f3..d88eeb81b2cf0 100644 --- a/samples/drivers/w1/scanner/boards/max78000evkit_max78000_m4.overlay +++ b/samples/drivers/w1/scanner/boards/max78000evkit_max78000_m4.overlay @@ -5,11 +5,11 @@ */ &owm_io_p0_18 { - power-source=; + power-source = ; }; &owm_pe_p0_19 { - power-source=; + power-source = ; }; &w1 { diff --git a/samples/drivers/w1/scanner/boards/max78000fthr_max78000_m4.overlay b/samples/drivers/w1/scanner/boards/max78000fthr_max78000_m4.overlay index 933dd2f3de9f3..d88eeb81b2cf0 100644 --- a/samples/drivers/w1/scanner/boards/max78000fthr_max78000_m4.overlay +++ b/samples/drivers/w1/scanner/boards/max78000fthr_max78000_m4.overlay @@ -5,11 +5,11 @@ */ &owm_io_p0_18 { - power-source=; + power-source = ; }; &owm_pe_p0_19 { - power-source=; + power-source = ; }; &w1 { diff --git a/samples/drivers/w1/scanner/boards/max78002evkit_max78002_m4.overlay b/samples/drivers/w1/scanner/boards/max78002evkit_max78002_m4.overlay index b39b6bfd394d3..b8be20635ee41 100644 --- a/samples/drivers/w1/scanner/boards/max78002evkit_max78002_m4.overlay +++ b/samples/drivers/w1/scanner/boards/max78002evkit_max78002_m4.overlay @@ -5,11 +5,11 @@ */ &owm_io_p0_6 { - power-source=; + power-source = ; }; &owm_pe_p0_7 { - power-source=; + power-source = ; }; &w1 { diff --git a/samples/drivers/watchdog/boards/intel_socfpga_agilex5_socdk.overlay b/samples/drivers/watchdog/boards/intel_socfpga_agilex5_socdk.overlay index 6bcb1dc5909d3..f169aae94618f 100644 --- a/samples/drivers/watchdog/boards/intel_socfpga_agilex5_socdk.overlay +++ b/samples/drivers/watchdog/boards/intel_socfpga_agilex5_socdk.overlay @@ -13,6 +13,6 @@ &watchdog0 { interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; status = "okay"; }; diff --git a/samples/drivers/watchdog/boards/intel_socfpga_agilex_socdk.overlay b/samples/drivers/watchdog/boards/intel_socfpga_agilex_socdk.overlay index 6bcb1dc5909d3..f169aae94618f 100644 --- a/samples/drivers/watchdog/boards/intel_socfpga_agilex_socdk.overlay +++ b/samples/drivers/watchdog/boards/intel_socfpga_agilex_socdk.overlay @@ -13,6 +13,6 @@ &watchdog0 { interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; status = "okay"; }; diff --git a/samples/drivers/watchdog/sample.yaml b/samples/drivers/watchdog/sample.yaml index 75b9f45977892..a1069108fb058 100644 --- a/samples/drivers/watchdog/sample.yaml +++ b/samples/drivers/watchdog/sample.yaml @@ -22,10 +22,10 @@ tests: - s32z2xxdc2/s32z270/rtu1 - s32z2xxdc2@D/s32z270/rtu0 - s32z2xxdc2@D/s32z270/rtu1 - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip + - panb611evb/nrf54l15/cpuapp + - panb611evb/nrf54l15/cpuapp/ns + - panb611evb/nrf54l15/cpuflpr + - panb611evb/nrf54l15/cpuflpr/xip - nrf54l15dk/nrf54l15/cpuapp/ns - nrf54l15dk/nrf54l10/cpuapp/ns - bl54l15_dvk/nrf54l10/cpuapp/ns diff --git a/samples/kernel/condition_variables/condvar/README.rst b/samples/kernel/condition_variables/condvar/README.rst index bd84d54854a7c..2ac48d3a0d8a7 100644 --- a/samples/kernel/condition_variables/condvar/README.rst +++ b/samples/kernel/condition_variables/condvar/README.rst @@ -20,7 +20,7 @@ the console. Building and Running ******************** -This application can be built and executed on :ref:`native_sim ` as follows: +This application can be built and executed on :zephyr:board:`native_sim ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/kernel/condition_variables/condvar diff --git a/samples/kernel/condition_variables/simple/README.rst b/samples/kernel/condition_variables/simple/README.rst index b3db950dd5892..2389b2ba7cd5d 100644 --- a/samples/kernel/condition_variables/simple/README.rst +++ b/samples/kernel/condition_variables/simple/README.rst @@ -21,7 +21,7 @@ the console. Building and Running ******************** -This application can be built and executed on :ref:`native_sim ` as follows: +This application can be built and executed on :zephyr:board:`native_sim ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/kernel/condition_variables/simple diff --git a/samples/modules/pmci/mctp/endpoint/boards/nrf52840dk_nrf52840.overlay b/samples/modules/pmci/mctp/endpoint/boards/nrf52840dk_nrf52840.overlay index 48c7f840dcab6..bb051b47dcfd1 100644 --- a/samples/modules/pmci/mctp/endpoint/boards/nrf52840dk_nrf52840.overlay +++ b/samples/modules/pmci/mctp/endpoint/boards/nrf52840dk_nrf52840.overlay @@ -1,3 +1,3 @@ -&arduino_serial{ +&arduino_serial { status = "okay"; }; diff --git a/samples/modules/pmci/mctp/host/boards/nrf52840dk_nrf52840.overlay b/samples/modules/pmci/mctp/host/boards/nrf52840dk_nrf52840.overlay index 48c7f840dcab6..bb051b47dcfd1 100644 --- a/samples/modules/pmci/mctp/host/boards/nrf52840dk_nrf52840.overlay +++ b/samples/modules/pmci/mctp/host/boards/nrf52840dk_nrf52840.overlay @@ -1,3 +1,3 @@ -&arduino_serial{ +&arduino_serial { status = "okay"; }; diff --git a/samples/modules/pmci/mctp/i2c_gpio_bus_endpoint/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/samples/modules/pmci/mctp/i2c_gpio_bus_endpoint/boards/frdm_mcxn947_mcxn947_cpu0.overlay index 348370b719d5e..02da1e40b719a 100644 --- a/samples/modules/pmci/mctp/i2c_gpio_bus_endpoint/boards/frdm_mcxn947_mcxn947_cpu0.overlay +++ b/samples/modules/pmci/mctp/i2c_gpio_bus_endpoint/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -2,7 +2,6 @@ /* Sets up I2C and a GPIO on JP8 to use as our i2c bus for MCTP */ - &nxp_lcd_8080_connector { status = "disabled"; }; @@ -24,7 +23,6 @@ clock-frequency = ; }; - / { mctp_i2c: mctp_i2c { compatible = "zephyr,mctp-i2c-gpio-target"; diff --git a/samples/modules/tflite-micro/magic_wand/boards/litex_vexriscv.overlay b/samples/modules/tflite-micro/magic_wand/boards/litex_vexriscv.overlay index 7deedc5550264..af375e6f35afd 100644 --- a/samples/modules/tflite-micro/magic_wand/boards/litex_vexriscv.overlay +++ b/samples/modules/tflite-micro/magic_wand/boards/litex_vexriscv.overlay @@ -1,17 +1,18 @@ /* Copyright 2019 The TensorFlow Authors. All Rights Reserved. -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * ============================================================================== + */ &i2c0 { reg = <0xe0003000 0x4 0xe0003004 0x4>; @@ -20,7 +21,6 @@ limitations under the License. compatible = "adi,adxl345"; reg = <0x1d>; }; - }; &pwm0 { diff --git a/samples/modules/thrift/hello/README.rst b/samples/modules/thrift/hello/README.rst index 8451d3df96a8b..92193f8e1acab 100644 --- a/samples/modules/thrift/hello/README.rst +++ b/samples/modules/thrift/hello/README.rst @@ -196,7 +196,7 @@ host OS: $ ./hello_server_ssl 0.0.0.0 ../native-cert.pem ../native-key.pem ../qemu-cert.pem -Then, in annother terminal, run the corresponding ``hello/client`` sample: +Then, in another terminal, run the corresponding ``hello/client`` sample: .. zephyr-app-commands:: :zephyr-app: samples/modules/thrift/hello/client diff --git a/samples/net/cloud/aws_iot_mqtt/README.rst b/samples/net/cloud/aws_iot_mqtt/README.rst index 6bb6d872dc7fd..1024c90e0cd86 100644 --- a/samples/net/cloud/aws_iot_mqtt/README.rst +++ b/samples/net/cloud/aws_iot_mqtt/README.rst @@ -57,7 +57,7 @@ Core region, thing, and device advisor configuration: Refer to the `AWS IoT Core Documentation `_ for more information. -Additionnaly, it is possible to tune the firmware to pass the AWS DQP test +Additionally, it is possible to tune the firmware to pass the AWS DQP test suite, to do set Kconfig option :kconfig:option:`CONFIG_AWS_TEST_SUITE_DQP` to ``y``. More information about the AWS device advisor can be found here: diff --git a/samples/net/dhcpv4_client/README.rst b/samples/net/dhcpv4_client/README.rst index 54e77cfd97d9e..05d9df3c95640 100644 --- a/samples/net/dhcpv4_client/README.rst +++ b/samples/net/dhcpv4_client/README.rst @@ -195,7 +195,7 @@ an ip address by typing: Arm FVP ======== -* :ref:`fvp_baser_aemv8r` +* :zephyr:board:`fvp_baser_aemv8r` * :ref:`fvp_base_revc_2xaemv8a` This sample application running on Arm FVP board can negotiate IP diff --git a/samples/net/dsa/boards/imx943_evk_mimx94398_a55.conf b/samples/net/dsa/boards/imx943_evk_mimx94398_a55.conf new file mode 100644 index 0000000000000..b56da8d10db29 --- /dev/null +++ b/samples/net/dsa/boards/imx943_evk_mimx94398_a55.conf @@ -0,0 +1,2 @@ +CONFIG_NET_SAMPLE_DSA_LLDP=n +CONFIG_HEAP_MEM_POOL_SIZE=851968 diff --git a/samples/net/dsa/boards/imx943_evk_mimx94398_a55.overlay b/samples/net/dsa/boards/imx943_evk_mimx94398_a55.overlay new file mode 100644 index 0000000000000..a146ae971c2a0 --- /dev/null +++ b/samples/net/dsa/boards/imx943_evk_mimx94398_a55.overlay @@ -0,0 +1,39 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&emdio { + status = "okay"; + + phy0: phy@2 { + status = "okay"; + }; + + phy1: phy@3 { + status = "okay"; + }; +}; + +/* Internal port */ +&enetc_psi3 { + status = "okay"; +}; + +&netc_switch { + status = "okay"; + + switch_port0: switch_port@0 { + status = "okay"; + }; + + switch_port1: switch_port@1 { + status = "okay"; + }; + + /* Internal port */ + switch_port3: switch_port@3 { + status = "okay"; + }; +}; diff --git a/samples/net/dsa/sample.yaml b/samples/net/dsa/sample.yaml index dc89f0d97e873..0429a8e537e4d 100644 --- a/samples/net/dsa/sample.yaml +++ b/samples/net/dsa/sample.yaml @@ -14,4 +14,5 @@ tests: - mimxrt1180_evk/mimxrt1189/cm33 - mimxrt1180_evk/mimxrt1189/cm7 - imx943_evk/mimx94398/m33/ddr + - imx943_evk/mimx94398/a55 depends_on: eth diff --git a/samples/net/latmon/README.rst b/samples/net/latmon/README.rst index b945bdac6b035..d04a772d05886 100644 --- a/samples/net/latmon/README.rst +++ b/samples/net/latmon/README.rst @@ -101,7 +101,7 @@ Setup and Usage - **Run Latmus on the SUT** Request the appropriate options with `Latmus `_. Users - can for example modify the sampling period with the ``-p`` option or generate historgram data for + can for example modify the sampling period with the ``-p`` option or generate histogram data for postprocessing with the ``-g`` option, - **Monitor results from the SUT** diff --git a/samples/net/mqtt_sn_publisher/compose/mosquitto.conf b/samples/net/mqtt_sn_publisher/compose/mosquitto.conf index 329ae66524102..2ed6a62cb6a66 100644 --- a/samples/net/mqtt_sn_publisher/compose/mosquitto.conf +++ b/samples/net/mqtt_sn_publisher/compose/mosquitto.conf @@ -571,7 +571,7 @@ allow_anonymous true # not given then the access is read/write. can contain the + or # # wildcards as in subscriptions. # -# The "deny" option can used to explicity deny access to a topic that would +# The "deny" option can used to explicitly deny access to a topic that would # otherwise be granted by a broader read/write/readwrite statement. Any "deny" # topics are handled before topics that grant read/write access. # diff --git a/samples/net/ocpp/src/main.c b/samples/net/ocpp/src/main.c index 548e4c780a57c..5e8b8d0079454 100644 --- a/samples/net/ocpp/src/main.c +++ b/samples/net/ocpp/src/main.c @@ -339,7 +339,7 @@ int main(void) k_sleep(K_SECONDS(1)); } - /* User could trigger remote start/stop transcation from CS server */ + /* User could trigger remote start/stop transaction from CS server */ k_sleep(K_SECONDS(1200)); return 0; diff --git a/samples/net/openthread/coap/README.rst b/samples/net/openthread/coap/README.rst index 7a9c6ad1511f7..2980f182efc07 100644 --- a/samples/net/openthread/coap/README.rst +++ b/samples/net/openthread/coap/README.rst @@ -26,7 +26,7 @@ The source code for this sample application can be found at: This sample uses the OpenThread CoAP API whereas Zephyr has its own CoAP API. So, why are we using the OpenThread CoAP API here ? - * OpenThread uses it internaly to implement many of its services. + * OpenThread uses it internally to implement many of its services. * OpenThread CoAP API has a more direct access to radio. So by using OpenThread CoAP API instead of Zephyr one, diff --git a/samples/net/sockets/echo_client/boards/frdm_mcxw71.overlay b/samples/net/sockets/echo_client/boards/frdm_mcxw71.overlay index 71da6a25089fd..7e8f5b13f8c6d 100644 --- a/samples/net/sockets/echo_client/boards/frdm_mcxw71.overlay +++ b/samples/net/sockets/echo_client/boards/frdm_mcxw71.overlay @@ -8,7 +8,7 @@ ranges = <0x0 0x30000000 DT_SIZE_K(112)>; stcm1: system_memory@1a000 { - compatible = "zephyr,memory-region","mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x1a000 DT_SIZE_K(4)>; zephyr,memory-region = "RetainedMem"; }; diff --git a/samples/net/sockets/echo_client/boards/intel_socfpga_agilex5_socdk.overlay b/samples/net/sockets/echo_client/boards/intel_socfpga_agilex5_socdk.overlay index e0778eab9cbdd..947a9cc79ede2 100644 --- a/samples/net/sockets/echo_client/boards/intel_socfpga_agilex5_socdk.overlay +++ b/samples/net/sockets/echo_client/boards/intel_socfpga_agilex5_socdk.overlay @@ -13,7 +13,7 @@ local-mac-address = [06 00 00 00 00 01]; }; -&mdio0 { +&mdio0 { status = "okay"; phy0: phy@0 { diff --git a/samples/net/sockets/echo_client/boards/mimxrt1020_evk.overlay b/samples/net/sockets/echo_client/boards/mimxrt1020_evk.overlay index 09743d6d61880..4cdb73e98bec1 100644 --- a/samples/net/sockets/echo_client/boards/mimxrt1020_evk.overlay +++ b/samples/net/sockets/echo_client/boards/mimxrt1020_evk.overlay @@ -27,7 +27,7 @@ }; hdlc_rcp_if: hdlc_rcp_if { - compatible = "uart,hdlc-rcp-if"; + compatible = "uart,hdlc-rcp-if"; }; }; @@ -53,9 +53,9 @@ pinmux_lpuart2_flowcontrol: pinmux_lpuart2_flowcontrol { group0 { pinmux = <&iomuxc_gpio_ad_b1_09_lpuart2_rx>, - <&iomuxc_gpio_ad_b1_08_lpuart2_tx>, - <&iomuxc_gpio_ad_b1_06_lpuart2_cts_b>, - <&iomuxc_gpio_ad_b1_07_lpuart2_rts_b>; + <&iomuxc_gpio_ad_b1_08_lpuart2_tx>, + <&iomuxc_gpio_ad_b1_06_lpuart2_cts_b>, + <&iomuxc_gpio_ad_b1_07_lpuart2_rts_b>; drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "100-mhz"; diff --git a/samples/net/sockets/echo_server/boards/frdm_mcxw71.overlay b/samples/net/sockets/echo_server/boards/frdm_mcxw71.overlay index 71da6a25089fd..7e8f5b13f8c6d 100644 --- a/samples/net/sockets/echo_server/boards/frdm_mcxw71.overlay +++ b/samples/net/sockets/echo_server/boards/frdm_mcxw71.overlay @@ -8,7 +8,7 @@ ranges = <0x0 0x30000000 DT_SIZE_K(112)>; stcm1: system_memory@1a000 { - compatible = "zephyr,memory-region","mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x1a000 DT_SIZE_K(4)>; zephyr,memory-region = "RetainedMem"; }; diff --git a/samples/net/sockets/echo_server/boards/intel_socfpga_agilex5_socdk.overlay b/samples/net/sockets/echo_server/boards/intel_socfpga_agilex5_socdk.overlay index c44e3452c6c9e..299c11d132124 100644 --- a/samples/net/sockets/echo_server/boards/intel_socfpga_agilex5_socdk.overlay +++ b/samples/net/sockets/echo_server/boards/intel_socfpga_agilex5_socdk.overlay @@ -13,7 +13,7 @@ local-mac-address = [06 00 00 00 00 02]; }; -&mdio0 { +&mdio0 { status = "okay"; phy0: phy@0 { diff --git a/samples/net/sockets/echo_server/overlay-usbd.conf b/samples/net/sockets/echo_server/overlay-usbd.conf index 8f04cb281865a..9d72348c96b10 100644 --- a/samples/net/sockets/echo_server/overlay-usbd.conf +++ b/samples/net/sockets/echo_server/overlay-usbd.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_LOG=y CONFIG_USBD_LOG_LEVEL_WRN=y diff --git a/samples/net/sockets/http_server/overlay-usbd.conf b/samples/net/sockets/http_server/overlay-usbd.conf index 20abbfb4fc2cf..c5f6f044fe84c 100644 --- a/samples/net/sockets/http_server/overlay-usbd.conf +++ b/samples/net/sockets/http_server/overlay-usbd.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_LOG=y CONFIG_USBD_LOG_LEVEL_WRN=y diff --git a/samples/net/tftp_client/README.rst b/samples/net/tftp_client/README.rst index 989e1f3428b7e..9407b750645b7 100644 --- a/samples/net/tftp_client/README.rst +++ b/samples/net/tftp_client/README.rst @@ -44,7 +44,7 @@ The easiest way to setup this sample application is to build and run it as a native_sim application or as a QEMU target using the default configuration :file:`prj.conf`. This requires a small amount of setup described in :ref:`networking_with_eth_qemu`, :ref:`networking_with_qemu` and :ref:`networking_with_native_sim`. -Build the tftp-client sample application for :ref:`native_sim ` like this: +Build the tftp-client sample application for :zephyr:board:`native_sim ` like this: .. zephyr-app-commands:: :zephyr-app: samples/net/tftp_client @@ -74,8 +74,8 @@ configurations in ``prj.conf``: Sample output ================================== -This sample can be run on :ref:`native_sim` while running a TFTP server on the host -machine. +This sample can be run on :zephyr:board:`native_sim` while running a TFTP server on the +host machine. Launch :command:`net-setup.sh` in net-tools: diff --git a/samples/net/vlan/boards/imx943_evk_mimx94398_m33_ddr.conf b/samples/net/vlan/boards/imx943_evk_mimx94398_m33_ddr.conf new file mode 100644 index 0000000000000..d862c64353b75 --- /dev/null +++ b/samples/net/vlan/boards/imx943_evk_mimx94398_m33_ddr.conf @@ -0,0 +1 @@ +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/samples/net/vlan/boards/imx943_evk_mimx94398_m33_ddr.overlay b/samples/net/vlan/boards/imx943_evk_mimx94398_m33_ddr.overlay new file mode 100644 index 0000000000000..40c5e69a4d09f --- /dev/null +++ b/samples/net/vlan/boards/imx943_evk_mimx94398_m33_ddr.overlay @@ -0,0 +1,17 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&emdio { + status = "okay"; + + phy2: phy@5 { + status = "okay"; + }; +}; + +&enetc_psi0 { + status = "okay"; +}; diff --git a/samples/net/vlan/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/samples/net/vlan/boards/mimxrt1180_evk_mimxrt1189_cm33.conf new file mode 100644 index 0000000000000..d862c64353b75 --- /dev/null +++ b/samples/net/vlan/boards/mimxrt1180_evk_mimxrt1189_cm33.conf @@ -0,0 +1 @@ +CONFIG_MAIN_STACK_SIZE=2048 diff --git a/samples/net/vlan/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/net/vlan/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay new file mode 100644 index 0000000000000..08d5fcfe7326d --- /dev/null +++ b/samples/net/vlan/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay @@ -0,0 +1,10 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Disable enetc_psi1 leaving only enetc_psi0 */ +&enetc_psi1 { + status = "disabled"; +}; diff --git a/samples/net/wifi/apsta_mode/Kconfig b/samples/net/wifi/apsta_mode/Kconfig new file mode 100644 index 0000000000000..4f98d27922617 --- /dev/null +++ b/samples/net/wifi/apsta_mode/Kconfig @@ -0,0 +1,63 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "Network Wi-Fi apsta_mode application" + +config WIFI_SAMPLE_AP_SSID + string "SSID of soft AP" + help + SSID of the soft AP created by the sample. + Fox example: "SOFT-AP" + +config WIFI_SAMPLE_AP_PSK + string "Pre-shared key for soft AP" + help + WPA2 password used by the soft AP for client authentication. + For example: "PSK" + +config WIFI_SAMPLE_SSID + string "SSID of the target AP" + help + SSID of the access point to connect to in station mode. + For example: "TARGET-AP" + +config WIFI_SAMPLE_PSK + string "Pre-shared key for target AP" + help + WPA2 password used to connect to the target AP. + For example: "PSK" + +config WIFI_SAMPLE_DHCPV4_START + bool "Start DHCPv4 server in application layer." + default y + help + Enable this option to start the DHCPv4 server from the application layer, + typically before the Soft AP is initialized. + + When disabled, the DHCPv4 server startup timing is determined by the vendor's + implementation. In some cases, the server may be started after the AP is up, + using the vendor's default IP address, gateway, subnet mask. + + +if WIFI_SAMPLE_DHCPV4_START + +# Some vendors start the DHCPv4 server after Soft AP initialization, +# using default IP address and subnet mask. In such cases, manual +# configuration of gateway and netmask may not be necessary. +# The following options are used only if the DHCPv4 server is started +# by the application. + +config WIFI_SAMPLE_AP_IP_ADDRESS + string "IP address of soft AP" + help + IP address assigned to the soft AP interface. + For example: "192.168.4.1" + +config WIFI_SAMPLE_AP_NETMASK + string "Netmask of soft AP" + help + Subnet mask for the soft AP interface. + For example: "255.255.255.0" +endif # WIFI_SAMPLE_DHCPV4_START + +source "Kconfig.zephyr" diff --git a/samples/net/wifi/apsta_mode/boards/frdm_rw612.conf b/samples/net/wifi/apsta_mode/boards/frdm_rw612.conf new file mode 100644 index 0000000000000..25fbbb10a3e43 --- /dev/null +++ b/samples/net/wifi/apsta_mode/boards/frdm_rw612.conf @@ -0,0 +1,13 @@ +CONFIG_WIFI_NXP=y +CONFIG_NXP_RW610=y +CONFIG_ETH_DRIVER=n +CONFIG_WIFI_NM=y +CONFIG_NXP_WIFI_SOFTAP_SUPPORT=y + +# stack size +CONFIG_SHELL_STACK_SIZE=6144 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_NET_MGMT_EVENT_STACK_SIZE=4608 +CONFIG_NET_TCP_WORKQ_STACK_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=4096 +CONFIG_IDLE_STACK_SIZE=1024 diff --git a/samples/net/wifi/apsta_mode/boards/rd_rw612_bga.conf b/samples/net/wifi/apsta_mode/boards/rd_rw612_bga.conf new file mode 100644 index 0000000000000..cf6f2c13cccc4 --- /dev/null +++ b/samples/net/wifi/apsta_mode/boards/rd_rw612_bga.conf @@ -0,0 +1,12 @@ +CONFIG_WIFI_NXP=y +CONFIG_NXP_RW610=y +CONFIG_WIFI_NM=y +CONFIG_NXP_WIFI_SOFTAP_SUPPORT=y + +# stack size +CONFIG_SHELL_STACK_SIZE=6144 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_NET_MGMT_EVENT_STACK_SIZE=4608 +CONFIG_NET_TCP_WORKQ_STACK_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=4096 +CONFIG_IDLE_STACK_SIZE=1024 diff --git a/samples/net/wifi/apsta_mode/nxp/overlay_rw612.conf b/samples/net/wifi/apsta_mode/nxp/overlay_rw612.conf new file mode 100644 index 0000000000000..30e5d4b9d1b81 --- /dev/null +++ b/samples/net/wifi/apsta_mode/nxp/overlay_rw612.conf @@ -0,0 +1,6 @@ +# apsta_mode configuration +CONFIG_WIFI_SAMPLE_AP_SSID="RW612_AP" +CONFIG_WIFI_SAMPLE_AP_PSK="" +CONFIG_WIFI_SAMPLE_SSID="TEST_AP" +CONFIG_WIFI_SAMPLE_PSK="PASSWORD" +CONFIG_WIFI_SAMPLE_DHCPV4_START=n diff --git a/samples/net/wifi/apsta_mode/socs/esp32_procpu.conf b/samples/net/wifi/apsta_mode/socs/esp32_procpu.conf index 84dd51b0e3592..076db08484590 100644 --- a/samples/net/wifi/apsta_mode/socs/esp32_procpu.conf +++ b/samples/net/wifi/apsta_mode/socs/esp32_procpu.conf @@ -3,3 +3,12 @@ CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y CONFIG_ESP32_WIFI_AP_STA_MODE=y CONFIG_WIFI_NM=y CONFIG_WIFI_NM_MAX_MANAGED_INTERFACES=2 + +# apsta_mode configuration +CONFIG_WIFI_SAMPLE_AP_SSID="ESP32-AP" +CONFIG_WIFI_SAMPLE_AP_PSK="" +CONFIG_WIFI_SAMPLE_SSID="SSID" +CONFIG_WIFI_SAMPLE_PSK="PASSWORD" +CONFIG_WIFI_SAMPLE_DHCPV4_START=y +CONFIG_WIFI_SAMPLE_AP_IP_ADDRESS="192.168.4.1" +CONFIG_WIFI_SAMPLE_AP_NETMASK="255.255.255.0" diff --git a/samples/net/wifi/apsta_mode/src/main.c b/samples/net/wifi/apsta_mode/src/main.c index aa0d0cb28cbb8..38f1635104117 100644 --- a/samples/net/wifi/apsta_mode/src/main.c +++ b/samples/net/wifi/apsta_mode/src/main.c @@ -18,16 +18,6 @@ LOG_MODULE_REGISTER(MAIN); NET_EVENT_WIFI_AP_ENABLE_RESULT | NET_EVENT_WIFI_AP_DISABLE_RESULT | \ NET_EVENT_WIFI_AP_STA_CONNECTED | NET_EVENT_WIFI_AP_STA_DISCONNECTED) -/* AP Mode Configuration */ -#define WIFI_AP_SSID "ESP32-AP" -#define WIFI_AP_PSK "" -#define WIFI_AP_IP_ADDRESS "192.168.4.1" -#define WIFI_AP_NETMASK "255.255.255.0" - -/* STA Mode Configuration */ -#define WIFI_SSID "SSID" /* Replace `SSID` with WiFi ssid. */ -#define WIFI_PSK "PASSWORD" /* Replace `PASSWORD` with Router password. */ - static struct net_if *ap_iface; static struct net_if *sta_iface; @@ -36,16 +26,33 @@ static struct wifi_connect_req_params sta_config; static struct net_mgmt_event_callback cb; +/* Check necessary definitions */ + +BUILD_ASSERT(sizeof(CONFIG_WIFI_SAMPLE_AP_SSID) > 1, + "CONFIG_WIFI_SAMPLE_AP_SSID is empty. Please set it in conf file."); + +BUILD_ASSERT(sizeof(CONFIG_WIFI_SAMPLE_SSID) > 1, + "CONFIG_WIFI_SAMPLE_SSID is empty. Please set it in conf file."); + +#if WIFI_SAMPLE_DHCPV4_START +BUILD_ASSERT(sizeof(CONFIG_WIFI_SAMPLE_AP_IP_ADDRESS) > 1, + "CONFIG_WIFI_SAMPLE_AP_IP_ADDRESS is empty. Please set it in conf file."); + +BUILD_ASSERT(sizeof(CONFIG_WIFI_SAMPLE_AP_NETMASK) > 1, + "CONFIG_WIFI_SAMPLE_AP_NETMASK is empty. Please set it in conf file."); + +#endif + static void wifi_event_handler(struct net_mgmt_event_callback *cb, uint64_t mgmt_event, struct net_if *iface) { switch (mgmt_event) { case NET_EVENT_WIFI_CONNECT_RESULT: { - LOG_INF("Connected to %s", WIFI_SSID); + LOG_INF("Connected to %s", CONFIG_WIFI_SAMPLE_SSID); break; } case NET_EVENT_WIFI_DISCONNECT_RESULT: { - LOG_INF("Disconnected from %s", WIFI_SSID); + LOG_INF("Disconnected from %s", CONFIG_WIFI_SAMPLE_SSID); break; } case NET_EVENT_WIFI_AP_ENABLE_RESULT: { @@ -75,18 +82,19 @@ static void wifi_event_handler(struct net_mgmt_event_callback *cb, uint64_t mgmt } } +#if CONFIG_WIFI_SAMPLE_DHCPV4_START static void enable_dhcpv4_server(void) { static struct in_addr addr; static struct in_addr netmaskAddr; - if (net_addr_pton(AF_INET, WIFI_AP_IP_ADDRESS, &addr)) { - LOG_ERR("Invalid address: %s", WIFI_AP_IP_ADDRESS); + if (net_addr_pton(AF_INET, CONFIG_WIFI_SAMPLE_AP_IP_ADDRESS, &addr)) { + LOG_ERR("Invalid address: %s", CONFIG_WIFI_SAMPLE_AP_IP_ADDRESS); return; } - if (net_addr_pton(AF_INET, WIFI_AP_NETMASK, &netmaskAddr)) { - LOG_ERR("Invalid netmask: %s", WIFI_AP_NETMASK); + if (net_addr_pton(AF_INET, CONFIG_WIFI_SAMPLE_AP_NETMASK, &netmaskAddr)) { + LOG_ERR("Invalid netmask: %s", CONFIG_WIFI_SAMPLE_AP_NETMASK); return; } @@ -97,7 +105,8 @@ static void enable_dhcpv4_server(void) } if (!net_if_ipv4_set_netmask_by_addr(ap_iface, &addr, &netmaskAddr)) { - LOG_ERR("Unable to set netmask for AP interface: %s", WIFI_AP_NETMASK); + LOG_ERR("Unable to set netmask for AP interface: %s", + CONFIG_WIFI_SAMPLE_AP_NETMASK); } addr.s4_addr[3] += 10; /* Starting IPv4 address for DHCPv4 address pool. */ @@ -109,6 +118,7 @@ static void enable_dhcpv4_server(void) LOG_INF("DHCPv4 server started...\n"); } +#endif static int enable_ap_mode(void) { @@ -118,21 +128,23 @@ static int enable_ap_mode(void) } LOG_INF("Turning on AP Mode"); - ap_config.ssid = (const uint8_t *)WIFI_AP_SSID; - ap_config.ssid_length = strlen(WIFI_AP_SSID); - ap_config.psk = (const uint8_t *)WIFI_AP_PSK; - ap_config.psk_length = strlen(WIFI_AP_PSK); + ap_config.ssid = (const uint8_t *)CONFIG_WIFI_SAMPLE_AP_SSID; + ap_config.ssid_length = sizeof(CONFIG_WIFI_SAMPLE_AP_SSID) - 1; + ap_config.psk = (const uint8_t *)CONFIG_WIFI_SAMPLE_AP_PSK; + ap_config.psk_length = sizeof(CONFIG_WIFI_SAMPLE_AP_PSK) - 1; ap_config.channel = WIFI_CHANNEL_ANY; ap_config.band = WIFI_FREQ_BAND_2_4_GHZ; - if (strlen(WIFI_AP_PSK) == 0) { + if (sizeof(CONFIG_WIFI_SAMPLE_AP_PSK) == 1) { ap_config.security = WIFI_SECURITY_TYPE_NONE; } else { ap_config.security = WIFI_SECURITY_TYPE_PSK; } +#if CONFIG_WIFI_SAMPLE_DHCPV4_START enable_dhcpv4_server(); +#endif int ret = net_mgmt(NET_REQUEST_WIFI_AP_ENABLE, ap_iface, &ap_config, sizeof(struct wifi_connect_req_params)); @@ -150,10 +162,10 @@ static int connect_to_wifi(void) return -EIO; } - sta_config.ssid = (const uint8_t *)WIFI_SSID; - sta_config.ssid_length = strlen(WIFI_SSID); - sta_config.psk = (const uint8_t *)WIFI_PSK; - sta_config.psk_length = strlen(WIFI_PSK); + sta_config.ssid = (const uint8_t *)CONFIG_WIFI_SAMPLE_SSID; + sta_config.ssid_length = sizeof(CONFIG_WIFI_SAMPLE_SSID) - 1; + sta_config.psk = (const uint8_t *)CONFIG_WIFI_SAMPLE_PSK; + sta_config.psk_length = sizeof(CONFIG_WIFI_SAMPLE_PSK) - 1; sta_config.security = WIFI_SECURITY_TYPE_PSK; sta_config.channel = WIFI_CHANNEL_ANY; sta_config.band = WIFI_FREQ_BAND_2_4_GHZ; @@ -163,7 +175,7 @@ static int connect_to_wifi(void) int ret = net_mgmt(NET_REQUEST_WIFI_CONNECT, sta_iface, &sta_config, sizeof(struct wifi_connect_req_params)); if (ret) { - LOG_ERR("Unable to Connect to (%s)", WIFI_SSID); + LOG_ERR("Unable to Connect to (%s)", CONFIG_WIFI_SAMPLE_SSID); } return ret; diff --git a/samples/net/wifi/shell/boards/reel_board.overlay b/samples/net/wifi/shell/boards/reel_board.overlay index ff215ca341c42..13addf7ece561 100644 --- a/samples/net/wifi/shell/boards/reel_board.overlay +++ b/samples/net/wifi/shell/boards/reel_board.overlay @@ -38,6 +38,5 @@ irq-gpios = <&gpio1 7 1>; reset-gpios = <&gpio1 8 1>; enable-gpios = <&gpio1 12 0>; - }; }; diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/ca.pem b/samples/net/wifi/test_certs/rsa2k_no_des/ca.pem new file mode 100644 index 0000000000000..2b872d2e30da3 --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/ca.pem @@ -0,0 +1,24 @@ +-----BEGIN CERTIFICATE----- +MIIEBzCCAu+gAwIBAgIUK8+d+8IOzeX+DP3VSvdF3lHiCdcwDQYJKoZIhvcNAQEL +BQAwgZIxCzAJBgNVBAYTAkZSMQ8wDQYDVQQIDAZSYWRpdXMxEjAQBgNVBAcMCVNv +bWV3aGVyZTEUMBIGA1UECgwLRXhhbXBsZSBJbmMxJjAkBgNVBAMMHUV4YW1wbGUg +Q2VydGlmaWNhdGUgQXV0aG9yaXR5MSAwHgYJKoZIhvcNAQkBFhFhZG1pbkBleGFt +cGxlLm9yZzAeFw0yNDEwMDgxMDI0MDZaFw0zNDEwMDYxMDI0MDZaMIGSMQswCQYD +VQQGEwJGUjEPMA0GA1UECAwGUmFkaXVzMRIwEAYDVQQHDAlTb21ld2hlcmUxFDAS +BgNVBAoMC0V4YW1wbGUgSW5jMSYwJAYDVQQDDB1FeGFtcGxlIENlcnRpZmljYXRl +IEF1dGhvcml0eTEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5vcmcwggEi +MA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCWKIwjdRIp9IrpZELN/ZsN13Xj +qQI6n086PNJ7BZfLi0+tD164rmxFk2eukNNksFCPhvMkqUxouGhc4mJjeivvrZxR +oT3cblOQIkkdEci6iTKC2E1a20W/Ur7cTXoIsnKwjiUjXk+cujkrZu4fcHX+O4vy +wTd5tEbhmifT/4u5nN8U2vBcEZqkGHOCp30VZSxtlGwqp4lc+tVziF3uFViW9MXk +3bVt+s1E7ztwG7+WBgVlLYe3CNSWkMxfyYBafH/l7iep6AFjoTn1z3AAjYi7IUNN +0JkW8MTgafRQIu4QsV5luq/Tiar2vwAm/GNgUJdSzUKARsfQzb/XTIgnLQqtAgMB +AAGjUzBRMB0GA1UdDgQWBBSijSC03/Thi6EOdM91V33zsbQpgzAfBgNVHSMEGDAW +gBSijSC03/Thi6EOdM91V33zsbQpgzAPBgNVHRMBAf8EBTADAQH/MA0GCSqGSIb3 +DQEBCwUAA4IBAQAvKEfmCDoMTKC6bfP6DSs+MSAGc5tCr6w6cz2AKNJ2fOMhkq55 +JF47oBBGm9SdTB6Jqo6c109Ps69/+LMtEEGwvzL0RL0WAuTYGo6sudm9hj/jDHZh +pAqi/2BQQeVgTa6oW0jtNPFe+/cobXo9TJ7wECGrhvVbmfl5ZPc0YVOIjjR0/LhL +q7lqPAlJ5vx0WvsX+QReN97we8vD0x1D3mCySJTi3Irh+grE0yJOSN2fa7cyqi9+ +vSiNUB1eUgQwrO+S8ZazYNvAZXC2Xf4WB4SOifJD73pYPAdwOejc0FA+zfEKa/6/ +vTUs8cIhlmDWO+BEoc9wygMKMmhT5s7/T5Bv +-----END CERTIFICATE----- diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/ca2.pem b/samples/net/wifi/test_certs/rsa2k_no_des/ca2.pem new file mode 100644 index 0000000000000..2b872d2e30da3 --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/ca2.pem @@ -0,0 +1,24 @@ +-----BEGIN CERTIFICATE----- +MIIEBzCCAu+gAwIBAgIUK8+d+8IOzeX+DP3VSvdF3lHiCdcwDQYJKoZIhvcNAQEL +BQAwgZIxCzAJBgNVBAYTAkZSMQ8wDQYDVQQIDAZSYWRpdXMxEjAQBgNVBAcMCVNv +bWV3aGVyZTEUMBIGA1UECgwLRXhhbXBsZSBJbmMxJjAkBgNVBAMMHUV4YW1wbGUg +Q2VydGlmaWNhdGUgQXV0aG9yaXR5MSAwHgYJKoZIhvcNAQkBFhFhZG1pbkBleGFt +cGxlLm9yZzAeFw0yNDEwMDgxMDI0MDZaFw0zNDEwMDYxMDI0MDZaMIGSMQswCQYD +VQQGEwJGUjEPMA0GA1UECAwGUmFkaXVzMRIwEAYDVQQHDAlTb21ld2hlcmUxFDAS +BgNVBAoMC0V4YW1wbGUgSW5jMSYwJAYDVQQDDB1FeGFtcGxlIENlcnRpZmljYXRl +IEF1dGhvcml0eTEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5vcmcwggEi +MA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCWKIwjdRIp9IrpZELN/ZsN13Xj +qQI6n086PNJ7BZfLi0+tD164rmxFk2eukNNksFCPhvMkqUxouGhc4mJjeivvrZxR +oT3cblOQIkkdEci6iTKC2E1a20W/Ur7cTXoIsnKwjiUjXk+cujkrZu4fcHX+O4vy +wTd5tEbhmifT/4u5nN8U2vBcEZqkGHOCp30VZSxtlGwqp4lc+tVziF3uFViW9MXk +3bVt+s1E7ztwG7+WBgVlLYe3CNSWkMxfyYBafH/l7iep6AFjoTn1z3AAjYi7IUNN +0JkW8MTgafRQIu4QsV5luq/Tiar2vwAm/GNgUJdSzUKARsfQzb/XTIgnLQqtAgMB +AAGjUzBRMB0GA1UdDgQWBBSijSC03/Thi6EOdM91V33zsbQpgzAfBgNVHSMEGDAW +gBSijSC03/Thi6EOdM91V33zsbQpgzAPBgNVHRMBAf8EBTADAQH/MA0GCSqGSIb3 +DQEBCwUAA4IBAQAvKEfmCDoMTKC6bfP6DSs+MSAGc5tCr6w6cz2AKNJ2fOMhkq55 +JF47oBBGm9SdTB6Jqo6c109Ps69/+LMtEEGwvzL0RL0WAuTYGo6sudm9hj/jDHZh +pAqi/2BQQeVgTa6oW0jtNPFe+/cobXo9TJ7wECGrhvVbmfl5ZPc0YVOIjjR0/LhL +q7lqPAlJ5vx0WvsX+QReN97we8vD0x1D3mCySJTi3Irh+grE0yJOSN2fa7cyqi9+ +vSiNUB1eUgQwrO+S8ZazYNvAZXC2Xf4WB4SOifJD73pYPAdwOejc0FA+zfEKa/6/ +vTUs8cIhlmDWO+BEoc9wygMKMmhT5s7/T5Bv +-----END CERTIFICATE----- diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/client-key.pem b/samples/net/wifi/test_certs/rsa2k_no_des/client-key.pem new file mode 100644 index 0000000000000..6ab70da245241 --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/client-key.pem @@ -0,0 +1,30 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQILVdWyEWhWU0CAggA +MAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBDMFReIusCg7gSkoUQZV2flBIIE +0BIFQH7+0dc7wHIQQ1y0ao90rrK3ExtCABH6xp4OAHUNPR1549zSEak/9Ba6WLBp +YE0m/lpLz4oUJE4Kd3rg4ekSZk4mapZoW7g5ax4qAEblmM6rqmyjiU0Q6tsAb8n1 +x+RyjUILlgTH1HDmeNA53QNMCw++xIMIJPN29SvFN6vkU2Fd2f74/TuZRSaCEPLO +LKtNMwWCMTrlv0UewEryOvZegPQuEF/Ewmmw/9l5VfkPp6zAtZKzWsfk4jUo5tv2 +5dPoHR+RKjNNVwetnCq59QYMS2My6KLqX4Vzqnbu8K1nlbm85ZHnvLGi8cDn8EB7 +QtRL+Ev5IwcwYJgV5AMojouJLQdR655jeITWI1Gsohz28YG8c1qYX4ZN6albSd1G +fd1tMOWkeu4uEzJ7ijLDfnCzrklnLuAZx8yLzyrOa7i9AwwJmdgUEdbWWsru3L6C +zDJ45rpA0FobdlTem4kpoE9yiyHkIhf3wmI3X+0aodC11pdbHP260KIC8E1K9FUh +s/IoEQCYrBp8UltNTlezwq/E5uOuIu4EpfjEgH1Z3+hSDbnmMAXNX4DbL234x7iy +3Y256DtOeHSElnRz3kDnZVNtM1Kd5fgEYJ1ptYRPYaWyJka7/hC/0UObuM9w+QeO +OlG0QgumQFloyhDa9anPBK4sYJp4g1fK8golUDW4AdpFPNOJvvgOvQUzhPpHjr+N +lpZ75Y6I3JSSKJ/UMlSCOqjak8oZtMtJNMfbx1lgwwDtgjDSJvSdl735gI9VmXXH +qnlGEtyiQ7k1Z1a4HxiY2/CiDHvkymClir/Ik8gt+wmyT9c/9BcehLRf6PxMsDVy +PCkty1LlzN+5tSZJtJnOiTlgsRn/w49Ohp74ITheSdb30/6PnFI+o8rcJHmrjN4d +t3z/bCyWAeC8mS7m0wtXlyBeG9xvdyT8dDHAFOnqxX30dEwEbjNj58kWGAgRf9i3 +HlOAP8yRy7LAV7A4HEPnEzXBxYpsROUw/8d3Jtmr2nAp2hfKP339DYZPHZpRLjJr +WQlJasHHLxHKKjSsuM06WsCO+Tt2FTSgGJuU6nFVK75fssmmJYzj9qMHVM6YSjfY +sT0ZIWRgO9NLFx5O3QxY1wgMLhhv1FREy9NVnMU0W3A1u0F7dwHywZGha2IqEXgu ++UyWIJnePMvluV/s66AN/OpIxKU48c0B4l7XzXkHHd43tDUG3ztfRuPbWCHipuRO +eo+vHGD01iBLSE1ZhrYLHKQhJvIKx/PIEaqJHP/Vy35AD/2/GH09TiIBHzX9aXie +TiKFs30FQv7SpLNHNE7jUxsYGNUbYa70S/Vgn3wkKATcXpCc749XQV4OUbFoqkDm +vuZOjkIOlm/OtZkUuDWmk96mgoVG/gWSEJPynJHUpmWdu/BCdYOgxBk/bmPa1leS +Z5NbO0fGMnNhDMXYA5rqmVzABcNSYhgYw5aciWpBlgYHEYrPxZvCxWftIyb24oEk +wdHEaFbIYbOoVZqo7Ym2hrvVrJb8Qdukf1BmUgfSSSc7BFoSrBUO4SNFtZI55NOB +OM4rnkqfoYR0IpnxzPIpxpsWljG9QsgnTaffStDgIGXiAtBWJFy+44f1IS4EoC6B ++we1Q6atPwYSyPtG8mn4Ce0BNxLDUoFDLMQ7Bt8QBMeX +-----END ENCRYPTED PRIVATE KEY----- diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/client-key2.pem b/samples/net/wifi/test_certs/rsa2k_no_des/client-key2.pem new file mode 100644 index 0000000000000..6ab70da245241 --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/client-key2.pem @@ -0,0 +1,30 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQILVdWyEWhWU0CAggA +MAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBDMFReIusCg7gSkoUQZV2flBIIE +0BIFQH7+0dc7wHIQQ1y0ao90rrK3ExtCABH6xp4OAHUNPR1549zSEak/9Ba6WLBp +YE0m/lpLz4oUJE4Kd3rg4ekSZk4mapZoW7g5ax4qAEblmM6rqmyjiU0Q6tsAb8n1 +x+RyjUILlgTH1HDmeNA53QNMCw++xIMIJPN29SvFN6vkU2Fd2f74/TuZRSaCEPLO +LKtNMwWCMTrlv0UewEryOvZegPQuEF/Ewmmw/9l5VfkPp6zAtZKzWsfk4jUo5tv2 +5dPoHR+RKjNNVwetnCq59QYMS2My6KLqX4Vzqnbu8K1nlbm85ZHnvLGi8cDn8EB7 +QtRL+Ev5IwcwYJgV5AMojouJLQdR655jeITWI1Gsohz28YG8c1qYX4ZN6albSd1G +fd1tMOWkeu4uEzJ7ijLDfnCzrklnLuAZx8yLzyrOa7i9AwwJmdgUEdbWWsru3L6C +zDJ45rpA0FobdlTem4kpoE9yiyHkIhf3wmI3X+0aodC11pdbHP260KIC8E1K9FUh +s/IoEQCYrBp8UltNTlezwq/E5uOuIu4EpfjEgH1Z3+hSDbnmMAXNX4DbL234x7iy +3Y256DtOeHSElnRz3kDnZVNtM1Kd5fgEYJ1ptYRPYaWyJka7/hC/0UObuM9w+QeO +OlG0QgumQFloyhDa9anPBK4sYJp4g1fK8golUDW4AdpFPNOJvvgOvQUzhPpHjr+N +lpZ75Y6I3JSSKJ/UMlSCOqjak8oZtMtJNMfbx1lgwwDtgjDSJvSdl735gI9VmXXH +qnlGEtyiQ7k1Z1a4HxiY2/CiDHvkymClir/Ik8gt+wmyT9c/9BcehLRf6PxMsDVy +PCkty1LlzN+5tSZJtJnOiTlgsRn/w49Ohp74ITheSdb30/6PnFI+o8rcJHmrjN4d +t3z/bCyWAeC8mS7m0wtXlyBeG9xvdyT8dDHAFOnqxX30dEwEbjNj58kWGAgRf9i3 +HlOAP8yRy7LAV7A4HEPnEzXBxYpsROUw/8d3Jtmr2nAp2hfKP339DYZPHZpRLjJr +WQlJasHHLxHKKjSsuM06WsCO+Tt2FTSgGJuU6nFVK75fssmmJYzj9qMHVM6YSjfY +sT0ZIWRgO9NLFx5O3QxY1wgMLhhv1FREy9NVnMU0W3A1u0F7dwHywZGha2IqEXgu ++UyWIJnePMvluV/s66AN/OpIxKU48c0B4l7XzXkHHd43tDUG3ztfRuPbWCHipuRO +eo+vHGD01iBLSE1ZhrYLHKQhJvIKx/PIEaqJHP/Vy35AD/2/GH09TiIBHzX9aXie +TiKFs30FQv7SpLNHNE7jUxsYGNUbYa70S/Vgn3wkKATcXpCc749XQV4OUbFoqkDm +vuZOjkIOlm/OtZkUuDWmk96mgoVG/gWSEJPynJHUpmWdu/BCdYOgxBk/bmPa1leS +Z5NbO0fGMnNhDMXYA5rqmVzABcNSYhgYw5aciWpBlgYHEYrPxZvCxWftIyb24oEk +wdHEaFbIYbOoVZqo7Ym2hrvVrJb8Qdukf1BmUgfSSSc7BFoSrBUO4SNFtZI55NOB +OM4rnkqfoYR0IpnxzPIpxpsWljG9QsgnTaffStDgIGXiAtBWJFy+44f1IS4EoC6B ++we1Q6atPwYSyPtG8mn4Ce0BNxLDUoFDLMQ7Bt8QBMeX +-----END ENCRYPTED PRIVATE KEY----- diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/client.pem b/samples/net/wifi/test_certs/rsa2k_no_des/client.pem new file mode 100644 index 0000000000000..9e815474cd8de --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/client.pem @@ -0,0 +1,22 @@ +-----BEGIN CERTIFICATE----- +MIIDojCCAooCFGZ4UJXBKG70aewILFtsy4mbvaYZMA0GCSqGSIb3DQEBCwUAMIGS +MQswCQYDVQQGEwJGUjEPMA0GA1UECAwGUmFkaXVzMRIwEAYDVQQHDAlTb21ld2hl +cmUxFDASBgNVBAoMC0V4YW1wbGUgSW5jMSYwJAYDVQQDDB1FeGFtcGxlIENlcnRp +ZmljYXRlIEF1dGhvcml0eTEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5v +cmcwHhcNMjQxMDA4MTAyNjI1WhcNMzQxMDA2MTAyNjI1WjCBhzELMAkGA1UEBhMC +RlIxDzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQwEgYDVQQK +DAtFeGFtcGxlIEluYzEbMBkGA1UEAwwSY2xpZW50LmV4YW1wbGUub3JnMSAwHgYJ +KoZIhvcNAQkBFhFhZG1pbkBleGFtcGxlLm9yZzCCASIwDQYJKoZIhvcNAQEBBQAD +ggEPADCCAQoCggEBAMu3HXJvi2Q4hQnLL4v/sCyEr5x+ZtBcSi2yETMViaf2EStW +UOs1A1pmCQbO7nadLQcWaX4tzefQCRrs1X4hIQuDIqRPNi6h6G1g5HEtqBWZhvwu +hDbmFiX8/Vtw/P0/9sox2DzyLG0mjJUAYAbKtyC1kQalybVBtrSaazyyAyh6oOuU +chAb7SmmNDsRB959TWM/mp+6yCcFGzCDKNBwlwthB6Uw92d3SfOyXEnZm8rPf0hV +4ICL5iB+xEYBv1LKmznFK/4UAyKpxAygc5fxKVWwlSsq8MrES5ak0n6H71wViaXK +BrH5yh9jEkK9XSeaUwg8C9eOOexyx/5JDY3TTE8CAwEAATANBgkqhkiG9w0BAQsF +AAOCAQEAUNddNiRUlJH0acJJv8ztXNWjNewd17tAk1BBHp6yyGAD8b52p6QbDAdS +xO3WsSc2bqSy599jp4GshO27TMQsBRMfoggCG21Aj6sIs0Hd4shTE4T0GUBEBxC2 +/HReuD+cGIzzKMYlvK8RPSaGLPvPw5SryvmOnjD368V0KCHwT04Z14i4sMxlkd5q +wB7fxTkVla9MR4uWObX62mJykmqT86chScJpldtBpRh8wrEa3Gt9FZoi/eqP0De8 +oCxmCZDrozGTZ4IIaNzchx3Ensh1RQwvvxd6ATerYdUjq4V2TlTksDRdCXtj+uNJ +FnB32sUHiIouxudAsqDf8UL9/99RCw== +-----END CERTIFICATE----- diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/client2.pem b/samples/net/wifi/test_certs/rsa2k_no_des/client2.pem new file mode 100644 index 0000000000000..9e815474cd8de --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/client2.pem @@ -0,0 +1,22 @@ +-----BEGIN CERTIFICATE----- +MIIDojCCAooCFGZ4UJXBKG70aewILFtsy4mbvaYZMA0GCSqGSIb3DQEBCwUAMIGS +MQswCQYDVQQGEwJGUjEPMA0GA1UECAwGUmFkaXVzMRIwEAYDVQQHDAlTb21ld2hl +cmUxFDASBgNVBAoMC0V4YW1wbGUgSW5jMSYwJAYDVQQDDB1FeGFtcGxlIENlcnRp +ZmljYXRlIEF1dGhvcml0eTEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5v +cmcwHhcNMjQxMDA4MTAyNjI1WhcNMzQxMDA2MTAyNjI1WjCBhzELMAkGA1UEBhMC +RlIxDzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQwEgYDVQQK +DAtFeGFtcGxlIEluYzEbMBkGA1UEAwwSY2xpZW50LmV4YW1wbGUub3JnMSAwHgYJ +KoZIhvcNAQkBFhFhZG1pbkBleGFtcGxlLm9yZzCCASIwDQYJKoZIhvcNAQEBBQAD +ggEPADCCAQoCggEBAMu3HXJvi2Q4hQnLL4v/sCyEr5x+ZtBcSi2yETMViaf2EStW +UOs1A1pmCQbO7nadLQcWaX4tzefQCRrs1X4hIQuDIqRPNi6h6G1g5HEtqBWZhvwu +hDbmFiX8/Vtw/P0/9sox2DzyLG0mjJUAYAbKtyC1kQalybVBtrSaazyyAyh6oOuU +chAb7SmmNDsRB959TWM/mp+6yCcFGzCDKNBwlwthB6Uw92d3SfOyXEnZm8rPf0hV +4ICL5iB+xEYBv1LKmznFK/4UAyKpxAygc5fxKVWwlSsq8MrES5ak0n6H71wViaXK +BrH5yh9jEkK9XSeaUwg8C9eOOexyx/5JDY3TTE8CAwEAATANBgkqhkiG9w0BAQsF +AAOCAQEAUNddNiRUlJH0acJJv8ztXNWjNewd17tAk1BBHp6yyGAD8b52p6QbDAdS +xO3WsSc2bqSy599jp4GshO27TMQsBRMfoggCG21Aj6sIs0Hd4shTE4T0GUBEBxC2 +/HReuD+cGIzzKMYlvK8RPSaGLPvPw5SryvmOnjD368V0KCHwT04Z14i4sMxlkd5q +wB7fxTkVla9MR4uWObX62mJykmqT86chScJpldtBpRh8wrEa3Gt9FZoi/eqP0De8 +oCxmCZDrozGTZ4IIaNzchx3Ensh1RQwvvxd6ATerYdUjq4V2TlTksDRdCXtj+uNJ +FnB32sUHiIouxudAsqDf8UL9/99RCw== +-----END CERTIFICATE----- diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/server-key.pem b/samples/net/wifi/test_certs/rsa2k_no_des/server-key.pem new file mode 100644 index 0000000000000..5f032cad701d3 --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/server-key.pem @@ -0,0 +1,30 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQIjI78fcZSH7oCAggA +MAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBDfF676hRrL290F0MgMDZiuBIIE +0Hkz7skRV8Ox0SoX5N8GsOPfN4PS1cLyHgokY6dUhJPU5vUzOn9iSiGQSEzSguQ7 +11mssjRC2T45wB/95VK2EPtRw1f/6VOUR6RJnnGb0PV1Rydp/x5TZ6vzcXpakqly +eljJR/20fIJClsZzhw0iu5la9fkF6G8WYFEkqex5jALSiN4qVLvkiqcTnh5+amem +8+OCKgvgooKD2ids4/0GGfJRQSC6DFf3kuxNl+MMvmDXmz/vrD85ONnyXzKXDA3N +3vRgL/YT6GzwIXb+7/c/tIMpnacxPAdbNOs3DY5ss4xcK68L5PwpM2BljzBa5dGw +Smgf2VRaYRVzmrte5j280QjfrlHRU2cHaxm0GCu2AOTGwMXcSNYMXfDNuxc57oQJ +vHXMeZD4K5lACbhYdZ5lJNFvv29YI7dZ7QOGu6nXlAuhZfbdc/cgT0som7eG8xpT +pERllhQ5ych9sP9nAccN6VUsWgmlF73lbSptBek1ccYkp9LIYCteJUPl2qPcz6zl +A7zrZ54f3Lg0fOm2pCtg+qKBiw1nd3MR/YbRCgyvudyZE2cCN/ZspWqxsavbGYOz +JOfIFNnyAcOYtEv1n1BGLfMa1THW2bDV8XmHVHUtM0k4z250QAmLygWLY2166iUF +qotBkvctKKdulzGdT4nVer1UEKTqcxhDf0dRiHN5spZtFrOee0uGIoQWHt2oecaK +pJovW+i0qO/1DG5spfU2m1bz6jR2u6nxi340oRrMSoe1ELVg3l1/wmM8yzh07GuK +pshzxwqAG/FnaKCvcKGUG2EfnAvOcbMgSa2w3GvyRkcDPn00arvX9nuXj0gkRDBi +eoVMkKKTeeYSGQ4ik+ja3xkgHcxh5W8aoezLvBbmUq206cmhLwfnYMhnvFTs6EBK +E0ENpCHwF/qoVBIzRCijG/eeCuf3a1YkJsWlvEeVrPeOmDFeDft3SSGOzHxE2A/7 +HWmHbWTm7dPOfgsU4zf+HglnBjN3kYU7StyM0EGxmB4lfB2BiWiL/3R13ERHQZfa +oOqa4/hOFXOXfTQk6ufXtBx8L9BemBqh36zbs2xVvIizJKeRMruoRblWZkHhUKR8 +K5GA7FYkU9ZPPP0UPKsO94xzwfbevi+7nWeUZoqcqAUy8Jt5aD2QpvFVbPBBOz17 +PGaubeVn/Ry8swPvkpddtmJ4mgF+3SVctmzY+EE/oN1XS8wa+XeuaThzk89Lvrfa +606nRWrNw3PSKjYoEEtRLhPeJCi9uOVenbOjtclio9mV5Sugwurolczvq8DAGpMG +W4WgALgOWDjQAudiNH5dtcMGkBONbYywkJc7cT2OZFmzkCbchPPWlKGopuaFGAoU +SPj7C9SenHmOWAFRX5jJrOZAuVqkdKN3ShWZUL+cDkOCCQlZ0E31u0m9yozY1MeO +Sx42GtZaSGff37FGYeMZM2ztlutw2zmv2B1g52SBHTjCqQU/ud2Q6/U0kUzjbsdF +/0KQY9wgZRdOvbnA2lBirN1rXzLWPdduOZ5QImfHfvToN+oOlEqVvvWG12DdA4e5 +y4Dumx00lfKEsGutjF3oKgE6jsjwqAwCoYEAFHTtsvA0hKPisQwNHZmpjGARvR56 +yMEmXynKvgyVGvVP2a9VdqBXSpstL24HfDIu+nlyEWGQ +-----END ENCRYPTED PRIVATE KEY----- diff --git a/samples/net/wifi/test_certs/rsa2k_no_des/server.pem b/samples/net/wifi/test_certs/rsa2k_no_des/server.pem new file mode 100644 index 0000000000000..d8f82faf6dd3c --- /dev/null +++ b/samples/net/wifi/test_certs/rsa2k_no_des/server.pem @@ -0,0 +1,22 @@ +-----BEGIN CERTIFICATE----- +MIIDojCCAooCFCPQcj7ej5jhr6/mLlAoLYgfgsYcMA0GCSqGSIb3DQEBCwUAMIGS +MQswCQYDVQQGEwJGUjEPMA0GA1UECAwGUmFkaXVzMRIwEAYDVQQHDAlTb21ld2hl +cmUxFDASBgNVBAoMC0V4YW1wbGUgSW5jMSYwJAYDVQQDDB1FeGFtcGxlIENlcnRp +ZmljYXRlIEF1dGhvcml0eTEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5v +cmcwHhcNMjQxMDA4MTAyNTI5WhcNMzQxMDA2MTAyNTI5WjCBhzELMAkGA1UEBhMC +RlIxDzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQwEgYDVQQK +DAtFeGFtcGxlIEluYzEbMBkGA1UEAwwSc2VydmVyLmV4YW1wbGUub3JnMSAwHgYJ +KoZIhvcNAQkBFhFhZG1pbkBleGFtcGxlLm9yZzCCASIwDQYJKoZIhvcNAQEBBQAD +ggEPADCCAQoCggEBANcE/OPHQK/y1b6UsIktNK7WIZB528HECY7Bz18EGba0uHod +91RbzHSJ1qI3iQyldI1UW/kY5oYjBW3lhLH0BkD/EsqvNYCV+3YzAM3ITtdOdEU9 +CqjgXttehQHfXvc7jQlF8Q2gYPUz2dDLo/gcTkz1d+mCr6nQUjT8Kq/nG54T0NnD +k8udchjUlNaQsvx/WVs3TUYxMbWzQRtpJIbv99rAWq7YgQbkNZnSYC1VgrU/BiuQ +0KrP6rfkxvBCGwIh2JXIL3FV4N8AsgGZvjXQ3zXKXwuPhxWdSmjKWlioVM3mha2A +/1e1gX6nFY/uk46D60XWxcJ6tHGHoafU7EtN3zMCAwEAATANBgkqhkiG9w0BAQsF +AAOCAQEAWwdTMphD0jxLtYO0iq/+fMtq2R96ZUN9wprZ7qg1evUNQjqLR4jKX306 +ZJX5uw+6r5Ve/k368qvcSF/sSfvBm8yd3JcegTl5t8T2/Aks8o3sfyuS0uyJC1rS +zTrd7FmJG9YMosU1BqYobda64MXq7g+6MyrQoZ6fVdPvC6Sox3+a4fl9xjdm4CTY +MsWqBJMe26LptvRIJ01/B6PjVTvsn/fxxj7rHmnJ/j63AIiBntm0vV/85cwYy/4o +HlPH/Qjvn3hZjUlBcveiYat998F+s9gH2usvCkG3kly/n1/667LLCymmCHxtH8ka +7tF3siO1EANureFY8qj6ZvlKeTkZ6g== +-----END CERTIFICATE----- diff --git a/samples/net/zperf/boards/imx943_evk_mimx94398_a55.conf b/samples/net/zperf/boards/imx943_evk_mimx94398_a55.conf new file mode 100644 index 0000000000000..66e54e9780cee --- /dev/null +++ b/samples/net/zperf/boards/imx943_evk_mimx94398_a55.conf @@ -0,0 +1 @@ +CONFIG_HEAP_MEM_POOL_SIZE=851968 diff --git a/samples/net/zperf/overlay-usbd.conf b/samples/net/zperf/overlay-usbd.conf index 6451b7e0566ec..cb305ed53a20a 100644 --- a/samples/net/zperf/overlay-usbd.conf +++ b/samples/net/zperf/overlay-usbd.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_LOG=y CONFIG_USBD_LOG_LEVEL_WRN=y diff --git a/samples/net/zperf/prj.conf b/samples/net/zperf/prj.conf index 59bfa7adb8bf7..129260a113ac7 100644 --- a/samples/net/zperf/prj.conf +++ b/samples/net/zperf/prj.conf @@ -44,3 +44,6 @@ CONFIG_SHELL_CMDS_RESIZE=n CONFIG_CACHE_MANAGEMENT=y CONFIG_SPEED_OPTIMIZATIONS=y CONFIG_TIMESLICING=n + +# For speed optimizations +CONFIG_PICOLIBC_USE_MODULE=y diff --git a/samples/psa/its/sample.yaml b/samples/psa/its/sample.yaml index 8d67cddd15731..d3e7b7e10c9b0 100644 --- a/samples/psa/its/sample.yaml +++ b/samples/psa/its/sample.yaml @@ -2,6 +2,8 @@ sample: name: PSA ITS API sample description: Demonstration of PSA Internal Trusted Storage (ITS) API usage. common: + integration_platforms: + - native_sim tags: - psa.secure_storage timeout: 10 diff --git a/samples/psa/persistent_key/sample.yaml b/samples/psa/persistent_key/sample.yaml index 490f2ea8f156d..7c5b9d8030043 100644 --- a/samples/psa/persistent_key/sample.yaml +++ b/samples/psa/persistent_key/sample.yaml @@ -2,6 +2,8 @@ sample: name: PSA Crypto persistent key sample description: Demonstration of persistent key usage in the PSA Crypto API. common: + integration_platforms: + - native_sim tags: - psa.secure_storage timeout: 10 diff --git a/samples/sensor/accel_trig/boards/mimxrt1040_evk.overlay b/samples/sensor/accel_trig/boards/mimxrt1040_evk.overlay index 56ec2a98c5b18..ac6eb648e0d85 100644 --- a/samples/sensor/accel_trig/boards/mimxrt1040_evk.overlay +++ b/samples/sensor/accel_trig/boards/mimxrt1040_evk.overlay @@ -4,7 +4,6 @@ * Copyright 2025 NXP */ - &fxls8974 { status = "okay"; int1-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; diff --git a/samples/sensor/accel_trig/sample.yaml b/samples/sensor/accel_trig/sample.yaml index 170635fc15f94..497f2f95c89e8 100644 --- a/samples/sensor/accel_trig/sample.yaml +++ b/samples/sensor/accel_trig/sample.yaml @@ -18,7 +18,8 @@ tests: \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$" fixture: fixture_sensor_accel_int integration_platforms: - - frdm_k64f # fxos8700 + - frdm_k64f # fxos8700 + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm # mikroe_lsm6dsl_click shield platform_exclude: - sensortile_box - stm32f3_disco @@ -27,6 +28,8 @@ tests: - disco_l475_iot1 - stm32l562e_dk - stm32wb5mm_dk + extra_args: + - platform:mikroe_clicker_ra4m1/r7fa4m1ab3cfm:SHIELD="mikroe_lsm6dsl_click" sample.sensor.accel_trig.adxl345-trigger: extra_args: - SHIELD=pmod_acl diff --git a/samples/sensor/accel_trig/x_nucleo_iks01a3.overlay b/samples/sensor/accel_trig/x_nucleo_iks01a3.overlay index f33cce2022116..9f7b652a21333 100644 --- a/samples/sensor/accel_trig/x_nucleo_iks01a3.overlay +++ b/samples/sensor/accel_trig/x_nucleo_iks01a3.overlay @@ -16,5 +16,5 @@ tap-shock = <0x03>; tap-quiet = <0x03>; tap-latency = <0x03>; - irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ + irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ }; diff --git a/samples/sensor/apds9960/sample.yaml b/samples/sensor/apds9960/sample.yaml index c90d85487bda8..e25b6ee90d03b 100644 --- a/samples/sensor/apds9960/sample.yaml +++ b/samples/sensor/apds9960/sample.yaml @@ -3,10 +3,14 @@ sample: tests: sample.sensor.apds9960: harness: console - platform_allow: reel_board + platform_allow: + - adafruit_qt_py_rp2040/rp2040 + - reel_board integration_platforms: - reel_board tags: sensors + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_apds9960" depends_on: - i2c - gpio @@ -19,15 +23,20 @@ tests: fixture: fixture_i2c_apds9960 sample.sensor.apds9960.trigger: harness: console - platform_allow: reel_board + platform_allow: + - reel_board + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm # mikroe_ir_gesture_click shield integration_platforms: - reel_board + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm tags: sensors depends_on: - i2c - gpio extra_configs: - CONFIG_APDS9960_TRIGGER_GLOBAL_THREAD=y + extra_args: + - platform:mikroe_clicker_ra4m1/r7fa4m1ab3cfm:SHIELD="mikroe_ir_gesture_click" harness_config: type: multi_line ordered: true diff --git a/samples/sensor/bme280/sample.yaml b/samples/sensor/bme280/sample.yaml index 94b7ebf4afacb..a46fd505b7c1f 100644 --- a/samples/sensor/bme280/sample.yaml +++ b/samples/sensor/bme280/sample.yaml @@ -11,8 +11,11 @@ tests: platform_allow: - adafruit_feather_m0_basic_proto - rpi_pico + - adafruit_qt_py_rp2040/rp2040 integration_platforms: - adafruit_feather_m0_basic_proto + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="sparkfun_environmental_combo" harness_config: type: one_line regex: diff --git a/samples/sensor/ccs811/sample.yaml b/samples/sensor/ccs811/sample.yaml index 755a9648ddc61..272d22ecb65d9 100644 --- a/samples/sensor/ccs811/sample.yaml +++ b/samples/sensor/ccs811/sample.yaml @@ -14,6 +14,10 @@ tests: platform_allow: - thingy52/nrf52832 - sltb004a + - mikroe_clicker_ra4m1 integration_platforms: - sltb004a + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm + extra_args: + - platform:mikroe_clicker_ra4m1/r7fa4m1ab3cfm:SHIELD="mikroe_air_quality_3_click" depends_on: i2c diff --git a/samples/sensor/dht_polling/boards/nucleo_f401re.overlay b/samples/sensor/dht_polling/boards/nucleo_f401re.overlay index cb381b5ba3a0f..1b41139bb5d0d 100644 --- a/samples/sensor/dht_polling/boards/nucleo_f401re.overlay +++ b/samples/sensor/dht_polling/boards/nucleo_f401re.overlay @@ -10,7 +10,7 @@ }; }; - &i2c1 { +&i2c1 { status = "okay"; hs300x: hs300x@44 { diff --git a/samples/sensor/dht_polling/sample.yaml b/samples/sensor/dht_polling/sample.yaml index 50cf2ef6d7ce6..38da487dd1d45 100644 --- a/samples/sensor/dht_polling/sample.yaml +++ b/samples/sensor/dht_polling/sample.yaml @@ -13,6 +13,13 @@ tests: filter: dt_alias_exists("dht0") integration_platforms: - nucleo_f401re + platform_allow: + - adafruit_qt_py_rp2040/rp2040 + - adafruit_feather_canbus_rp2040/rp2040 + - nucleo_f401re + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_aht20" + - platform:adafruit_feather_canbus_rp2040/rp2040:SHIELD="sparkfun_shtc3" harness: console harness_config: fixture: fixture_i2c_hs300x diff --git a/samples/sensor/fdc2x1x/boards/nrf9160dk_nrf9160.overlay b/samples/sensor/fdc2x1x/boards/nrf9160dk_nrf9160.overlay index 6f88622c690e9..0b20c9a8538e8 100644 --- a/samples/sensor/fdc2x1x/boards/nrf9160dk_nrf9160.overlay +++ b/samples/sensor/fdc2x1x/boards/nrf9160dk_nrf9160.overlay @@ -22,7 +22,7 @@ fref-divider = <1>; idrive = <10>; fin-sel = <2>; - inductance = < 18 >; + inductance = <18>; }; channel_1 { diff --git a/samples/sensor/grow_r502a/boards/esp32_devkitc_procpu.overlay b/samples/sensor/grow_r502a/boards/esp32_devkitc_procpu.overlay index 7add14e5350cb..4b37f71173c91 100644 --- a/samples/sensor/grow_r502a/boards/esp32_devkitc_procpu.overlay +++ b/samples/sensor/grow_r502a/boards/esp32_devkitc_procpu.overlay @@ -17,8 +17,8 @@ pinctrl-names = "default"; fps { - #address-cells=<1>; - #size-cells=<0>; + #address-cells = <1>; + #size-cells = <0>; grow_r502a@ffffffff { compatible = "hzgrow,r502a"; reg = <0xffffffff>; diff --git a/samples/sensor/grow_r502a/boards/yd_esp32_procpu.overlay b/samples/sensor/grow_r502a/boards/yd_esp32_procpu.overlay index 2fa0bb3197f77..ebbb4de6e64dd 100644 --- a/samples/sensor/grow_r502a/boards/yd_esp32_procpu.overlay +++ b/samples/sensor/grow_r502a/boards/yd_esp32_procpu.overlay @@ -17,8 +17,8 @@ pinctrl-names = "default"; fps { - #address-cells=<1>; - #size-cells=<0>; + #address-cells = <1>; + #size-cells = <0>; grow_r502a@ffffffff { compatible = "hzgrow,r502a"; reg = <0xffffffff>; diff --git a/samples/sensor/heart_rate/boards/nrf52840dk_nrf52840.overlay b/samples/sensor/heart_rate/boards/nrf52840dk_nrf52840.overlay index 3fc88daf1d2b6..8fc90f458b951 100644 --- a/samples/sensor/heart_rate/boards/nrf52840dk_nrf52840.overlay +++ b/samples/sensor/heart_rate/boards/nrf52840dk_nrf52840.overlay @@ -19,6 +19,6 @@ bh1790: bh1790@5b { compatible = "rohm,bh1790"; - reg=<0x5b>; + reg = <0x5b>; }; }; diff --git a/samples/sensor/ina219/sample.yaml b/samples/sensor/ina219/sample.yaml index 548a0e4cc408e..2b8c41db50878 100644 --- a/samples/sensor/ina219/sample.yaml +++ b/samples/sensor/ina219/sample.yaml @@ -10,5 +10,9 @@ sample: tests: sample.drivers.ina219: build_only: true - platform_allow: blackpill_f411ce + platform_allow: + - blackpill_f411ce + - adafruit_qt_py_rp2040/rp2040 + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_ina219" tags: sensors diff --git a/samples/sensor/jc42/sample.yaml b/samples/sensor/jc42/sample.yaml index 2552a24885ca8..ca87d8837a297 100644 --- a/samples/sensor/jc42/sample.yaml +++ b/samples/sensor/jc42/sample.yaml @@ -7,6 +7,10 @@ tests: min_ram: 8 depends_on: i2c filter: dt_compat_enabled("jedec,jc-42.4-temp") - platform_allow: nucleo_l053r8 + platform_allow: + - adafruit_qt_py_rp2040/rp2040 + - nucleo_l053r8 integration_platforms: - nucleo_l053r8 + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_mcp9808" diff --git a/samples/sensor/light_polling/README.rst b/samples/sensor/light_polling/README.rst index ef6aecf794cc7..50180cf338a98 100644 --- a/samples/sensor/light_polling/README.rst +++ b/samples/sensor/light_polling/README.rst @@ -31,7 +31,7 @@ Build and flash the sample as follows, changing ``nrf52dk/nrf52832`` to your boa .. zephyr-app-commands:: :zephyr-app: samples/sensor/light_polling - :board: nrf52dk/nrf52832 + :board: mikroe_clicker_ra4m1 :goals: build flash :compact: diff --git a/samples/sensor/light_polling/sample.yaml b/samples/sensor/light_polling/sample.yaml index ddfecfd0feb4e..5917d4eac1f38 100644 --- a/samples/sensor/light_polling/sample.yaml +++ b/samples/sensor/light_polling/sample.yaml @@ -15,14 +15,17 @@ tests: - nrf52dk/nrf52832 harness: grove depends_on: adc - sample.sensor.light_polling.als_pt19: + sample.sensor.light_polling: tags: - drivers - sensor - light - platform_allow: - - frdm_mcxw71/mcxw716c integration_platforms: - frdm_mcxw71/mcxw716c - depends_on: - - adc + - adafruit_qt_py_rp2040/rp2040 # adafruit_tsl2591 shield + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm # mikroe_ambient_2_click shield + - mikroe_quail/stm32f427xx # mikroe_illuminance_click shield + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_tsl2591" + - platform:mikroe_clicker_ra4m1/r7fa4m1ab3cfm:SHIELD="mikroe_ambient_2_click" + - platform:mikroe_quail/stm32f427xx:SHIELD="mikroe_illuminance_click" diff --git a/samples/sensor/magn_polling/boards/rpi_pico.overlay b/samples/sensor/magn_polling/boards/rpi_pico.overlay index e2cf9fe377024..e3399caad936f 100644 --- a/samples/sensor/magn_polling/boards/rpi_pico.overlay +++ b/samples/sensor/magn_polling/boards/rpi_pico.overlay @@ -15,7 +15,6 @@ input-enable; }; }; - }; &pio0 { diff --git a/samples/sensor/magn_polling/sample.yaml b/samples/sensor/magn_polling/sample.yaml index 8c44c0c74ddae..25e6310b75dd3 100644 --- a/samples/sensor/magn_polling/sample.yaml +++ b/samples/sensor/magn_polling/sample.yaml @@ -11,3 +11,10 @@ tests: - sensortile_box # lis2mdl - stm32f411e_disco # lsm303agr_magn - stm32f3_disco # lsm303dlhc_magn + sample.sensor.magn_polling.shields: + platform_allow: + - adafruit_qt_py_rp2040/rp2040 # adafruit_lis2mdl shield + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm # mikroe_3d_hall_3_click shield + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_lis2mdl" + - platform:mikroe_clicker_ra4m1/r7fa4m1ab3cfm:SHIELD="mikroe_3d_hall_3_click" diff --git a/samples/sensor/magn_trig/boards/twr_ke18f.overlay b/samples/sensor/magn_trig/boards/twr_ke18f.overlay index c35b67ae86dc5..4f82667c80b69 100644 --- a/samples/sensor/magn_trig/boards/twr_ke18f.overlay +++ b/samples/sensor/magn_trig/boards/twr_ke18f.overlay @@ -4,7 +4,6 @@ * Copyright 2025 NXP */ - &fxos8700 { status = "okay"; int1-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; diff --git a/samples/sensor/paj7620_gesture/boards/nucleo_f334r8.overlay b/samples/sensor/paj7620_gesture/boards/nucleo_f334r8.overlay index 0e67fa6a052bf..e69886c4e7e63 100644 --- a/samples/sensor/paj7620_gesture/boards/nucleo_f334r8.overlay +++ b/samples/sensor/paj7620_gesture/boards/nucleo_f334r8.overlay @@ -8,6 +8,6 @@ paj7620: paj7620@73 { compatible = "pixart,paj7620"; reg = <0x73>; - int-gpios = <&gpioa 9 (GPIO_PULL_UP)>; + int-gpios = <&gpioa 9 GPIO_PULL_UP>; }; }; diff --git a/samples/sensor/pressure_interrupt/README.rst b/samples/sensor/pressure_interrupt/README.rst index d59dce60fbd14..bab6bb8a1bd65 100644 --- a/samples/sensor/pressure_interrupt/README.rst +++ b/samples/sensor/pressure_interrupt/README.rst @@ -69,5 +69,5 @@ Sample Output [00:00:09.819,061] PRESS_INT_SAMPLE: PRESSURE CHANGE INTERRUPT - + [00:00:09.859,039] PRESS_INT_SAMPLE: PRESSURE THRESHOLD INTERRUPT diff --git a/samples/sensor/pressure_polling/README.rst b/samples/sensor/pressure_polling/README.rst index d4c26310ef32c..cee29753e1b79 100644 --- a/samples/sensor/pressure_polling/README.rst +++ b/samples/sensor/pressure_polling/README.rst @@ -45,8 +45,6 @@ Sample Output .. code-block:: console -## Default configuration - Found device "icp101xx@63", getting sensor data Starting pressure and altitude polling sample. temp 25.49 Cel, pressure 96.271438 kPa, altitude 447.208465 m diff --git a/samples/sensor/pressure_polling/sample.yaml b/samples/sensor/pressure_polling/sample.yaml index 1fae99115af9f..c063b12562c1b 100644 --- a/samples/sensor/pressure_polling/sample.yaml +++ b/samples/sensor/pressure_polling/sample.yaml @@ -7,3 +7,8 @@ tests: filter: dt_alias_exists("pressure-sensor") integration_platforms: - nrf52dk/nrf52832 + - adafruit_qt_py_rp2040/rp2040 # adafruit_dps310 shield + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm # mikroe_pressure_3_click shield + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_dps310" + - platform:mikroe_clicker_ra4m1/r7fa4m1ab3cfm:SHIELD="mikroe_pressure_3_click" diff --git a/samples/sensor/proximity_polling/sample.yaml b/samples/sensor/proximity_polling/sample.yaml index 35ef1647b22d2..26476289ae206 100644 --- a/samples/sensor/proximity_polling/sample.yaml +++ b/samples/sensor/proximity_polling/sample.yaml @@ -9,3 +9,6 @@ tests: filter: dt_alias_exists("prox-sensor0") integration_platforms: - nrf52840dk/nrf52840 + - mikroe_clicker_ra4m1/r7fa4m1ab3cfm # mikroe_proximity_9_click shield + extra_args: + - platform:mikroe_clicker_ra4m1/r7fa4m1ab3cfm:SHIELD="mikroe_proximity_9_click" diff --git a/samples/sensor/qdec/boards/esp32c6_devkitc_hpcore.overlay b/samples/sensor/qdec/boards/esp32c6_devkitc_hpcore.overlay index 0500e9e1a228c..3f7af8fad3b68 100644 --- a/samples/sensor/qdec/boards/esp32c6_devkitc_hpcore.overlay +++ b/samples/sensor/qdec/boards/esp32c6_devkitc_hpcore.overlay @@ -14,7 +14,7 @@ pcnt_default: pcnt_default { group1 { pinmux = , - ; + ; bias-pull-up; }; }; diff --git a/samples/sensor/qdec/boards/esp32s3_devkitm_procpu.overlay b/samples/sensor/qdec/boards/esp32s3_devkitm_procpu.overlay index 4562dd868bbc6..c4e9fba562a33 100644 --- a/samples/sensor/qdec/boards/esp32s3_devkitm_procpu.overlay +++ b/samples/sensor/qdec/boards/esp32s3_devkitm_procpu.overlay @@ -14,7 +14,7 @@ pcnt_default: pcnt_default { group1 { pinmux = , - ; + ; bias-pull-up; }; }; diff --git a/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu.overlay b/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu.overlay index 4562dd868bbc6..c4e9fba562a33 100644 --- a/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu.overlay +++ b/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu.overlay @@ -14,7 +14,7 @@ pcnt_default: pcnt_default { group1 { pinmux = , - ; + ; bias-pull-up; }; }; diff --git a/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu_usb.overlay b/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu_usb.overlay index 4562dd868bbc6..c4e9fba562a33 100644 --- a/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu_usb.overlay +++ b/samples/sensor/qdec/boards/esp32s3_luatos_core_procpu_usb.overlay @@ -14,7 +14,7 @@ pcnt_default: pcnt_default { group1 { pinmux = , - ; + ; bias-pull-up; }; }; diff --git a/samples/sensor/qdec/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/samples/sensor/qdec/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay index 6daf4bfe310fd..08be3028152f5 100644 --- a/samples/sensor/qdec/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay +++ b/samples/sensor/qdec/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay @@ -41,12 +41,15 @@ status = "okay"; pinctrl-0 = <&pinmux_qdec1>; pinctrl-names = "default"; - counts-per-revolution = < 120 >; - xbar = < &xbar1 >; + counts-per-revolution = <120>; + xbar = <&xbar1>; }; &xbar1 { status = "okay"; - xbar-maps = < (21|0x100) (66|0x100) >, /* kXBARA1_InputIomuxXbarIn21 <-> kXBARA1_OutputEnc1PhaseAInput */ - < (22|0x100) (67|0x100) >; /* kXBARA1_InputIomuxXbarIn22 <-> kXBARA1_OutputEnc1PhaseBInput */ + xbar-maps = + /* kXBARA1_InputIomuxXbarIn21 <-> kXBARA1_OutputEnc1PhaseAInput */ + <(21 | 0x100) (66 | 0x100)>, + /* kXBARA1_InputIomuxXbarIn22 <-> kXBARA1_OutputEnc1PhaseBInput */ + <(22 | 0x100) (67 | 0x100)>; }; diff --git a/samples/sensor/qdec/boards/nrf52840dk_nrf52840.overlay b/samples/sensor/qdec/boards/nrf52840dk_nrf52840.overlay index accd81383f00f..5d3ce694dfe78 100644 --- a/samples/sensor/qdec/boards/nrf52840dk_nrf52840.overlay +++ b/samples/sensor/qdec/boards/nrf52840dk_nrf52840.overlay @@ -21,7 +21,6 @@ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; - }; &pinctrl { @@ -37,6 +36,6 @@ status = "okay"; pinctrl-0 = <&qdec_pinctrl>; pinctrl-names = "default"; - steps = < 120 >; - led-pre = < 500 >; + steps = <120>; + led-pre = <500>; }; diff --git a/samples/sensor/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/sensor/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay index cd36e22ab9333..099e45ea4ef84 100644 --- a/samples/sensor/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/sensor/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -36,6 +36,6 @@ status = "okay"; pinctrl-0 = <&qdec_pinctrl>; pinctrl-names = "default"; - steps = < 120 >; - led-pre = < 500 >; + steps = <120>; + led-pre = <500>; }; diff --git a/samples/sensor/sensor_shell/sample.yaml b/samples/sensor/sensor_shell/sample.yaml index ee22ada3284b4..1a0a681307f70 100644 --- a/samples/sensor/sensor_shell/sample.yaml +++ b/samples/sensor/sensor_shell/sample.yaml @@ -26,3 +26,8 @@ tests: extra_args: DTC_OVERLAY_FILE=fake_sensor.overlay integration_platforms: - native_sim + sample.sensor.shell.shields: + platform_allow: + - adafruit_qt_py_rp2040/rp2040 + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_ina237" diff --git a/samples/sensor/sht3xd/boards/nucleo_l476rg.overlay b/samples/sensor/sht3xd/boards/nucleo_l476rg.overlay index 7f2492361cf09..2eb9194e2aa86 100644 --- a/samples/sensor/sht3xd/boards/nucleo_l476rg.overlay +++ b/samples/sensor/sht3xd/boards/nucleo_l476rg.overlay @@ -5,7 +5,7 @@ */ &i2c1 { /* SDA CN5.9=PB9, SCL CN5.10=PB8, ALERT CN5.1=D8=PA9 */ -/* &i2c3 { * SDA CN7.36=PC1, SCL CN7.38=PC0, ALERT CN7.34=PB0 */ + /* &i2c3 { * SDA CN7.36=PC1, SCL CN7.38=PC0, ALERT CN7.34=PB0 */ sht3xd@44 { compatible = "sensirion,sht3xd"; reg = <0x44>; diff --git a/samples/sensor/stream_drdy/boards/nucleo_f401re.overlay b/samples/sensor/stream_drdy/boards/nucleo_f401re.overlay index 0ae04ca70ce8c..012cf89d9a8c4 100644 --- a/samples/sensor/stream_drdy/boards/nucleo_f401re.overlay +++ b/samples/sensor/stream_drdy/boards/nucleo_f401re.overlay @@ -5,7 +5,6 @@ */ #include - /* * Nucleo F401RE board + shield iks4a1 * @@ -25,7 +24,7 @@ reg = <0x6b>; accel-odr = ; accel-range = ; - int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ + int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ drdy-pin = <2>; drdy-pulsed; }; diff --git a/samples/sensor/stream_drdy/boards/nucleo_h503rb.overlay b/samples/sensor/stream_drdy/boards/nucleo_h503rb.overlay index 0ae04ca70ce8c..012cf89d9a8c4 100644 --- a/samples/sensor/stream_drdy/boards/nucleo_h503rb.overlay +++ b/samples/sensor/stream_drdy/boards/nucleo_h503rb.overlay @@ -5,7 +5,6 @@ */ #include - /* * Nucleo F401RE board + shield iks4a1 * @@ -25,7 +24,7 @@ reg = <0x6b>; accel-odr = ; accel-range = ; - int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ + int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ drdy-pin = <2>; drdy-pulsed; }; diff --git a/samples/sensor/stream_drdy/boards/sensortile_box_pro.overlay b/samples/sensor/stream_drdy/boards/sensortile_box_pro.overlay index 2235a25711295..c2464d8d37065 100644 --- a/samples/sensor/stream_drdy/boards/sensortile_box_pro.overlay +++ b/samples/sensor/stream_drdy/boards/sensortile_box_pro.overlay @@ -5,7 +5,6 @@ */ #include - /* * This devicetree overlay file will be automatically picked by the Zephyr * build system when building the sample for the sensortile_box_pro board. diff --git a/samples/sensor/stream_fifo/boards/nucleo_f401re.overlay b/samples/sensor/stream_fifo/boards/nucleo_f401re.overlay index a428b585ed569..4387131a04941 100644 --- a/samples/sensor/stream_fifo/boards/nucleo_f401re.overlay +++ b/samples/sensor/stream_fifo/boards/nucleo_f401re.overlay @@ -5,7 +5,6 @@ */ #include - /* * Nucleo F401RE board + shield iks4a1 * @@ -31,7 +30,7 @@ accel-fifo-batch-rate = ; gyro-fifo-batch-rate = ; temp-fifo-batch-rate = ; - int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ + int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ drdy-pin = <2>; drdy-pulsed; }; diff --git a/samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay b/samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay index 95fbcacd48d9f..28fbe5d791de6 100644 --- a/samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay +++ b/samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay @@ -5,7 +5,6 @@ */ #include - /* * Nucleo F401RE board + shield iks4a1 * @@ -34,7 +33,7 @@ sflp-odr = ; sflp-fifo-enable = ; - int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ + int2-gpios = <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */ drdy-pin = <2>; drdy-pulsed; }; diff --git a/samples/sensor/stream_fifo/boards/sensortile_box_pro.overlay b/samples/sensor/stream_fifo/boards/sensortile_box_pro.overlay index 4ed5566a47bcb..5f5864e6ca3e2 100644 --- a/samples/sensor/stream_fifo/boards/sensortile_box_pro.overlay +++ b/samples/sensor/stream_fifo/boards/sensortile_box_pro.overlay @@ -5,7 +5,6 @@ */ #include - /* * This devicetree overlay file will be automatically picked by the Zephyr * build system when building the sample for the sensortile_box_pro board. diff --git a/samples/sensor/thermometer/boards/nrf52840dk_nrf52840.overlay b/samples/sensor/thermometer/boards/nrf52840dk_nrf52840.overlay index 1ebc6ce70fefc..6580426577757 100644 --- a/samples/sensor/thermometer/boards/nrf52840dk_nrf52840.overlay +++ b/samples/sensor/thermometer/boards/nrf52840dk_nrf52840.overlay @@ -19,7 +19,7 @@ reg = <7>; zephyr,gain = "ADC_GAIN_1_3"; zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; + zephyr,acquisition-time = ; zephyr,input-positive = ; zephyr,resolution = <12>; /* 0.055C per ADC step */ zephyr,oversampling = <2>; /* x4 */ diff --git a/samples/sensor/tmp11x/boards/nucleo_f401re.overlay b/samples/sensor/tmp11x/boards/nucleo_f401re.overlay index ba29a788befa3..9f9dcf5fb46b2 100644 --- a/samples/sensor/tmp11x/boards/nucleo_f401re.overlay +++ b/samples/sensor/tmp11x/boards/nucleo_f401re.overlay @@ -18,5 +18,4 @@ read-only; }; }; - }; diff --git a/samples/sensor/vcnl4040/sample.yaml b/samples/sensor/vcnl4040/sample.yaml index 4bfaf2dc12d3b..15044638cbcbd 100644 --- a/samples/sensor/vcnl4040/sample.yaml +++ b/samples/sensor/vcnl4040/sample.yaml @@ -3,8 +3,12 @@ sample: tests: sample.sensor.vcnl4040: harness: sensor - platform_allow: adafruit_feather_stm32f405 + platform_allow: + - adafruit_feather_stm32f405 + - adafruit_qt_py_rp2040/rp2040 integration_platforms: - adafruit_feather_stm32f405 + extra_args: + - platform:adafruit_qt_py_rp2040/rp2040:SHIELD="adafruit_vcnl4040" tags: sensors filter: dt_compat_enabled("vishay,vcnl4040") diff --git a/samples/sensor/veaa_x_3/boards/nucleo_h563zi.overlay b/samples/sensor/veaa_x_3/boards/nucleo_h563zi.overlay index 37e2e54a017b2..1e2ee8003f94b 100644 --- a/samples/sensor/veaa_x_3/boards/nucleo_h563zi.overlay +++ b/samples/sensor/veaa_x_3/boards/nucleo_h563zi.overlay @@ -17,7 +17,6 @@ dac-resolution = <12>; pressure-range-type = "D2"; }; - }; &adc1 { @@ -31,5 +30,4 @@ zephyr,acquisition-time = ; zephyr,resolution = <12>; }; - }; diff --git a/samples/sensor/veml6031/boards/olimex_stm32_e407.overlay b/samples/sensor/veml6031/boards/olimex_stm32_e407.overlay index d6b785d083921..c78379ba68b0e 100644 --- a/samples/sensor/veml6031/boards/olimex_stm32_e407.overlay +++ b/samples/sensor/veml6031/boards/olimex_stm32_e407.overlay @@ -6,19 +6,19 @@ &pinctrl { i2c2_sda_pf0: i2c2_sda_pf0 { - pinmux = < 0xa04 >; + pinmux = <0xa04>; bias-pull-up; drive-open-drain; }; i2c2_scl_pf1: i2c2_scl_pf1 { - pinmux = < 0xa24 >; + pinmux = <0xa24>; bias-pull-up; drive-open-drain; }; }; &i2c2 { - pinctrl-0 = < &i2c2_scl_pf1 &i2c2_sda_pf0 >; + pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>; pinctrl-names = "default"; status = "okay"; light: light@29 { diff --git a/samples/shields/npm13xx_ek/doc/index.rst b/samples/shields/npm13xx_ek/index.rst similarity index 100% rename from samples/shields/npm13xx_ek/doc/index.rst rename to samples/shields/npm13xx_ek/index.rst diff --git a/samples/shields/npm2100_ek/doc/index.rst b/samples/shields/npm2100_ek/index.rst similarity index 100% rename from samples/shields/npm2100_ek/doc/index.rst rename to samples/shields/npm2100_ek/index.rst diff --git a/samples/shields/npm6001_ek/doc/index.rst b/samples/shields/npm6001_ek/index.rst similarity index 99% rename from samples/shields/npm6001_ek/doc/index.rst rename to samples/shields/npm6001_ek/index.rst index 394adb2c56b7a..b3c9c2b207c84 100644 --- a/samples/shields/npm6001_ek/doc/index.rst +++ b/samples/shields/npm6001_ek/index.rst @@ -20,7 +20,7 @@ Requirements The shield needs to be wired to a host board supporting the Arduino connector. Below you can find a wiring example for the nRF52840 DK: -.. figure:: nrf52840dk_wiring.jpg +.. figure:: doc/nrf52840dk_wiring.jpg :alt: nRF52840DK + nPM6001-EK wiring example :align: center diff --git a/samples/shields/rtk0eg0019b01002bj/CMakeLists.txt b/samples/shields/rtk0eg0019b01002bj/CMakeLists.txt new file mode 100644 index 0000000000000..d5f0ae5608398 --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(rtk0eg0019b01002bj) + +target_sources(app PRIVATE src/main.c) + +if(CONFIG_INPUT_RENESAS_RA_QE_TOUCH_CFG) + zephyr_include_directories(src) + zephyr_sources(src/qe_touch_config.c) +endif() diff --git a/samples/shields/rtk0eg0019b01002bj/README.rst b/samples/shields/rtk0eg0019b01002bj/README.rst new file mode 100644 index 0000000000000..9bd72e670b1df --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/README.rst @@ -0,0 +1,116 @@ +.. zephyr:code-sample:: rtk0eg0019b01002bj + :name: RTK0EG0019B01002BJ Capacitive Touch Application Shield + :relevant-api: input_interface renesas_ra_ctsu_interface + + Interact with the Capacitive Touch Sensor and LED matrix on the RTK0EG0019B01002BJ shield + +Overview +******** + +This sample demonstrates the usage of the Capacitive Touch Sensor using the +:ref:`rtk0eg0019b01002bj` with `Renesas Capacitive Touch Sensor Solutions`_. + +Requirements +************ + +A Renesas Capacitive Touch Evaluation Kit is needed to run this sample. It includes: + +- A MCU board which support CTSU driver (for example: RSSK-RA2L1). +- A RTK0EG0019B01002BJ Touch Application board. + +Building and Running +******************** + +Build and flash with default settings for shield +================================================ +The :ref:`rtk0eg0019b01002bj` comes with a default DTS configuration that is tuned in advance to +make it ready for development. + +Build and flash as follows, changing ``rssk_ra2l1`` for your board: + +.. zephyr-app-commands:: + :zephyr-app: samples/shields/rtk0eg0019b01002bj + :board: rssk_ra2l1 + :shield: rtk0eg0019b01002bj + :goals: build flash + :compact: + +After startup, all LEDs on the shield will blink 5 times to indicate that the +application has started. + +You can monitor input events through the console output. Additionally, the LED +corresponding to the touched sensor will turn on when you touch it. + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-6697-gdc27367ff627 *** + rtk0eg0019b01002bj sample started + I: input event: dev=button1 type= 1 code= 11 value=0 + I: input event: dev=wheel type= 3 code= 8 value=61 + I: input event: dev=wheel type= 3 code= 8 value=67 + I: input event: dev=wheel type= 3 code= 8 value=82 + I: input event: dev=wheel type= 3 code= 8 value=111 + I: input event: dev=wheel type= 3 code= 8 value=124 + I: input event: dev=wheel type= 3 code= 8 value=134 + I: input event: dev=slider type= 3 code= 6 value=0 + I: input event: dev=slider type= 3 code= 6 value=2 + I: input event: dev=slider type= 3 code= 6 value=4 + I: input event: dev=slider type= 3 code= 6 value=6 + I: input event: dev=slider type= 3 code= 6 value=10 + I: input event: dev=slider type= 3 code= 6 value=23 + I: input event: dev=slider type= 3 code= 6 value=26 + I: input event: dev=slider type= 3 code= 6 value=27 + I: input event: dev=slider type= 3 code= 6 value=28 + +(Advanced) Using Configuration Output Generated by Renesas QE Capacitive Touch Workflow +======================================================================================= +This section is for advanced users who do not want to use the default configuration for the Cap +Touch shield and would like to tune configuration parameters manually themselves using the +`Renesas Development Assistance Tool for Capacitive Touch Sensors`_. + +Requirements +------------ + +- `e² studio`_ with Renesas QE Capacitive Touch plugin installed: recommended 2025-04.1 version +- `RA Flexible Software Package`_: recommended FSP v5.8.0 or newer + +Building and flashing with generated tuning code +------------------------------------------------ + + 1. Follow steps 6.1 to 6.5 of `Using QE and FSP to Develop Capacitive Touch Applications`_. + + 2. At step 8 in 6.5 Tuning the Capacitive Touch Interface Using QE for Capacitive Touch Plug-in, + select 'Specify an output folder' and choose this application's subfolder. + + 3. Update the include path to qe_touch_config.h and qe_touch_define.h, and add qe_touch_config.c + to the build sources in your application's CMake. + + 4. Build and flash the application with the command below: + +.. zephyr-app-commands:: + :zephyr-app: samples/shields/rtk0eg0019b01002bj + :board: rssk_ra2l1 + :shield: rtk0eg0019b01002bj + :gen-args: -DCONFIG_INPUT_RENESAS_RA_QE_TOUCH_CFG=y + :goals: build flash + :compact: + +References +********** +- `Renesas Capacitive Touch Sensor Solutions`_ +- `Renesas Development Assistance Tool for Capacitive Touch Sensors`_ + +.. _Renesas Capacitive Touch Sensor Solutions: + https://www.renesas.com/en/key-technologies/hmi/capacitive-touch-sensor-solutions + +.. _Renesas Development Assistance Tool for Capacitive Touch Sensors: + https://www.renesas.com/en/software-tool/qe-capacitive-touch-development-assistance-tool-capacitive-touch-sensors + +.. _Using QE and FSP to Develop Capacitive Touch Applications: + https://www.renesas.com/en/document/apn/using-qe-and-fsp-develop-capacitive-touch-applications?r=1170071 + +.. _e² studio: + https://www.renesas.com/en/software-tool/e-studio + +.. _RA Flexible Software Package: + https://www.renesas.com/en/software-tool/flexible-software-package diff --git a/samples/shields/rtk0eg0019b01002bj/prj.conf b/samples/shields/rtk0eg0019b01002bj/prj.conf new file mode 100644 index 0000000000000..12b75f7b1df0b --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/prj.conf @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y + +CONFIG_INPUT=y +CONFIG_INPUT_EVENT_DUMP=y +CONFIG_GPIO=y diff --git a/samples/shields/rtk0eg0019b01002bj/sample.yaml b/samples/shields/rtk0eg0019b01002bj/sample.yaml new file mode 100644 index 0000000000000..3b6911e20ccff --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/sample.yaml @@ -0,0 +1,9 @@ +sample: + name: RTK0EG0019B01002BJ Capacitive Touch Application Shield +tests: + sample.shields.rtk0eg0019b01002bj: + harness: shield + tags: shield + platform_allow: + - rssk_ra2l1 + extra_args: SHIELD=rtk0eg0019b01002bj diff --git a/samples/shields/rtk0eg0019b01002bj/src/main.c b/samples/shields/rtk0eg0019b01002bj/src/main.c new file mode 100644 index 0000000000000..de9356fdeac72 --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/src/main.c @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_INPUT_RENESAS_RA_QE_TOUCH_CFG +#include "qe_touch_config.h" +#endif /* CONFIG_INPUT_RENESAS_RA_QE_TOUCH_CFG*/ + +#define BUTTON1 DT_NODELABEL(rtk0eg0019b01002bj_bt1) +#define BUTTON2 DT_NODELABEL(rtk0eg0019b01002bj_bt2) +#define BUTTON3 DT_NODELABEL(rtk0eg0019b01002bj_bt3) +#define SLIDER DT_NODELABEL(rtk0eg0019b01002bj_slider) +#define WHEEL DT_NODELABEL(rtk0eg0019b01002bj_wheel) + +#define QE_TOUCH_CFG1 DT_CHILD(DT_NODELABEL(rtk0eg0019b01002bj_ctsu), group1) +#define QE_TOUCH_CFG2 DT_CHILD(DT_NODELABEL(rtk0eg0019b01002bj_ctsu), group2) +#define QE_TOUCH_CFG3 DT_CHILD(DT_NODELABEL(rtk0eg0019b01002bj_ctsu), group3) + +#define NUM_ROWS DT_PROP_LEN(DT_PATH(zephyr_user), rtk0eg0019b01002bj_led_row_gpios) +#define NUM_COLS DT_PROP_LEN(DT_PATH(zephyr_user), rtk0eg0019b01002bj_led_col_gpios) + +#define LED_MATRIX_ROWS(idx, nodeid) \ + GPIO_DT_SPEC_GET_BY_IDX(nodeid, rtk0eg0019b01002bj_led_row_gpios, idx) +#define LED_MATRIX_COLS(idx, nodeid) \ + GPIO_DT_SPEC_GET_BY_IDX(nodeid, rtk0eg0019b01002bj_led_col_gpios, idx) + +#define BUTTON_LED_NUM (3U) + +#define SLIDER_LED_NUM (5U) +#define SLIDER_RESOLUTION (100) + +#define WHEEL_LED_NUM (8U) +#define WHEEL_RESOLUTION_DEGREE (360) + +static const struct gpio_dt_spec led_row[NUM_ROWS] = { + LISTIFY(NUM_ROWS, LED_MATRIX_ROWS, (,), DT_PATH(zephyr_user)), +}; + +static const struct gpio_dt_spec led_col[NUM_COLS] = { + LISTIFY(NUM_COLS, LED_MATRIX_COLS, (,), DT_PATH(zephyr_user)), +}; + +static const unsigned int wheel_leds_lut[WHEEL_LED_NUM] = {0, 1, 2, 3, 4, 5, 6, 7}; +static const unsigned int slider_leds_lut[SLIDER_LED_NUM] = {8, 9, 10, 11, 12}; +static const unsigned int button_leds_lut[BUTTON_LED_NUM] = {13, 14, 15}; + +static void rtk0eg0019b01002bj_led_output(unsigned int led_idx, bool on) +{ + /* Refer to RTK0EG0022S01001BJ - Design Package for the Touch Application board layout */ + static const unsigned int led_map[NUM_ROWS * NUM_COLS][2] = { + {0, 0}, {1, 0}, {2, 0}, {3, 0}, {0, 1}, {1, 1}, {2, 1}, {3, 1}, + {0, 3}, {1, 3}, {2, 3}, {3, 3}, {0, 2}, {1, 2}, {2, 2}, {3, 2}, + }; + const struct gpio_dt_spec *p_led_row = &led_row[led_map[led_idx][0]]; + const struct gpio_dt_spec *p_led_col = &led_col[led_map[led_idx][1]]; + + gpio_pin_set_dt(p_led_row, on ? 1 : 0); + gpio_pin_set_dt(p_led_col, on ? 1 : 0); +} + +static void rtk0eg0019b01002bj_led_init(void) +{ + for (int i = 0; i < NUM_ROWS; i++) { + gpio_pin_configure_dt(&led_row[i], GPIO_OUTPUT_INACTIVE); + } + + for (int i = 0; i < NUM_COLS; i++) { + gpio_pin_configure_dt(&led_col[i], GPIO_OUTPUT_INACTIVE); + } +} + +static void blink_leds(unsigned int duration_ms) +{ + for (int i = 0; i < 5; i++) { + /* Turn all LEDs ON */ + for (int j = 0; j < NUM_ROWS * NUM_COLS; j++) { + rtk0eg0019b01002bj_led_output(j, true); + } + k_msleep(duration_ms); + + /* Turn all LEDs OFF */ + for (int j = 0; j < NUM_ROWS * NUM_COLS; j++) { + rtk0eg0019b01002bj_led_output(j, false); + } + k_msleep(duration_ms); + } +} + +static inline unsigned int wheel_get_current_step(unsigned int value) +{ + return (value * WHEEL_LED_NUM) / WHEEL_RESOLUTION_DEGREE; +} + +static inline unsigned int slider_get_current_step(unsigned int value) +{ + return (value * SLIDER_LED_NUM) / SLIDER_RESOLUTION; +} + +static void rtk0eg0019b01002bj_evt_handler(struct input_event *evt, void *user_data) +{ + unsigned int led_idx; + + /* Set all LEDs to OFF */ + for (int i = 0; i < NUM_ROWS * NUM_COLS; i++) { + rtk0eg0019b01002bj_led_output(i, false); + } + + switch (evt->code) { + case INPUT_KEY_0: { + led_idx = button_leds_lut[0]; + break; + } + case INPUT_KEY_1: { + led_idx = button_leds_lut[1]; + break; + } + case INPUT_KEY_2: { + led_idx = button_leds_lut[2]; + break; + } + case INPUT_ABS_WHEEL: { + led_idx = wheel_get_current_step(evt->value) + wheel_leds_lut[0]; + break; + } + case INPUT_ABS_THROTTLE: { + led_idx = slider_get_current_step(evt->value) + slider_leds_lut[0]; + break; + } + default: + /* Unexpected event */ + return; + } + + rtk0eg0019b01002bj_led_output(led_idx, true); +} + +INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(BUTTON1), rtk0eg0019b01002bj_evt_handler, NULL, button1); +INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(BUTTON2), rtk0eg0019b01002bj_evt_handler, NULL, button2); +INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(BUTTON3), rtk0eg0019b01002bj_evt_handler, NULL, button3); +INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(SLIDER), rtk0eg0019b01002bj_evt_handler, NULL, slider); +INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(WHEEL), rtk0eg0019b01002bj_evt_handler, NULL, wheel); + +int main(void) +{ +#ifdef CONFIG_INPUT_RENESAS_RA_QE_TOUCH_CFG + const struct device *qe_touch_cfg1 = DEVICE_DT_GET(QE_TOUCH_CFG1); + const struct device *qe_touch_cfg2 = DEVICE_DT_GET(QE_TOUCH_CFG2); + const struct device *qe_touch_cfg3 = DEVICE_DT_GET(QE_TOUCH_CFG3); + int ret; +#endif + rtk0eg0019b01002bj_led_init(); + + /* Blink all leds 5 times, each time is 200ms */ + blink_leds(200); + +#ifdef CONFIG_INPUT_RENESAS_RA_QE_TOUCH_CFG + ret = renesas_ra_ctsu_group_configure( + qe_touch_cfg1, (struct renesas_ra_ctsu_touch_cfg *)&g_qe_touch_instance_config01); + if (ret < 0) { + printk("Failed to configure QE Touch Group 1: %d\n", ret); + return ret; + } + + ret = renesas_ra_ctsu_group_configure( + qe_touch_cfg2, (struct renesas_ra_ctsu_touch_cfg *)&g_qe_touch_instance_config02); + if (ret < 0) { + printk("Failed to configure QE Touch Group 2: %d\n", ret); + return ret; + } + + ret = renesas_ra_ctsu_group_configure( + qe_touch_cfg3, (struct renesas_ra_ctsu_touch_cfg *)&g_qe_touch_instance_config03); + if (ret < 0) { + printk("Failed to configure QE Touch Group 3: %d\n", ret); + return ret; + } +#endif + + printk("rtk0eg0019b01002bj sample started\n"); + return 0; +} diff --git a/samples/shields/rtk0eg0019b01002bj/src/qe_touch_config.c b/samples/shields/rtk0eg0019b01002bj/src/qe_touch_config.c new file mode 100644 index 0000000000000..0dc0eff0c5d19 --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/src/qe_touch_config.c @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Generated content from Renesas QE Capacitive Touch */ + +#include "qe_touch_config.h" + +volatile uint8_t g_qe_touch_flag; +volatile ctsu_event_t g_qe_ctsu_event; + +void qe_touch_callback(touch_callback_args_t *p_args) +{ + g_qe_touch_flag = 1; + g_qe_ctsu_event = p_args->event; +} + +/* CTSU Related Information for [CONFIG01] configuration. */ + +const ctsu_element_cfg_t g_qe_ctsu_element_cfg_config01[] = { + {.ssdiv = CTSU_SSDIV_4000, .so = 0x000, .snum = 0x07, .sdpa = 0x1F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x00F, .snum = 0x07, .sdpa = 0x1F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x007, .snum = 0x07, .sdpa = 0x1F}, +}; + +const ctsu_cfg_t g_qe_ctsu_cfg_config01 = { + .cap = CTSU_CAP_SOFTWARE, + + .txvsel = CTSU_TXVSEL_INTERNAL_POWER, + .txvsel2 = CTSU_TXVSEL_MODE, + + .atune12 = CTSU_ATUNE12_40UA, + .md = CTSU_MODE_SELF_MULTI_SCAN, + .posel = CTSU_POSEL_SAME_PULSE, + + .ctsuchac0 = 0x01, /* ch0-ch7 enable mask */ + .ctsuchac1 = 0x0E, /* ch8-ch15 enable mask */ + .ctsuchac2 = 0x00, /* ch16-ch23 enable mask */ + .ctsuchac3 = 0x00, /* ch24-ch31 enable mask */ + .ctsuchac4 = 0x00, /* ch32-ch39 enable mask */ + .ctsuchtrc0 = 0x01, /* ch0-ch7 mutual tx mask */ + .ctsuchtrc1 = 0x00, /* ch8-ch15 mutual tx mask */ + .ctsuchtrc2 = 0x00, /* ch16-ch23 mutual tx mask */ + .ctsuchtrc3 = 0x00, /* ch24-ch31 mutual tx mask */ + .ctsuchtrc4 = 0x00, /* ch32-ch39 mutual tx mask */ + .num_rx = 3, + .num_tx = 0, + .p_elements = g_qe_ctsu_element_cfg_config01, + +#if (CTSU_TARGET_VALUE_CONFIG_SUPPORT == 1) + .tuning_self_target_value = 4608, + .tuning_mutual_target_value = 10240, +#endif + + .num_moving_average = 4, + .p_callback = &qe_touch_callback, +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + .p_transfer_tx = &g_transfer0, + .p_transfer_rx = &g_transfer1, +#else + .p_transfer_tx = NULL, + .p_transfer_rx = NULL, +#endif + + .write_irq = CTSU_WRITE_IRQn, + .read_irq = CTSU_READ_IRQn, + .end_irq = CTSU_END_IRQn, + +}; + +ctsu_instance_ctrl_t g_qe_ctsu_ctrl_config01; + +const ctsu_instance_t g_qe_ctsu_instance_config01 = { + .p_ctrl = &g_qe_ctsu_ctrl_config01, + .p_cfg = &g_qe_ctsu_cfg_config01, + .p_api = &g_ctsu_on_ctsu, +}; + +/* Touch Related Information for [CONFIG01] configuration. */ + +#define QE_TOUCH_CONFIG01_NUM_BUTTONS (3) +#define QE_TOUCH_CONFIG01_NUM_SLIDERS (0) +#define QE_TOUCH_CONFIG01_NUM_WHEELS (0) +#define QE_TOUCH_CONFIG01_NUM_TOUCH_PADS (0) + +#if (QE_TOUCH_CONFIG01_NUM_BUTTONS != 0) +const touch_button_cfg_t g_qe_touch_button_cfg_config01[] = { + { + .elem_index = 2, + .threshold = 261, + .hysteresis = 13, + }, + { + .elem_index = 1, + .threshold = 226, + .hysteresis = 11, + }, + { + .elem_index = 0, + .threshold = 306, + .hysteresis = 15, + }, +}; +#endif + +#if (QE_TOUCH_CONFIG01_NUM_SLIDERS != 0) +const touch_slider_cfg_t g_qe_touch_slider_cfg_config01[] = {NULL}; +#endif + +#if (QE_TOUCH_CONFIG01_NUM_WHEELS != 0) +const touch_wheel_cfg_t g_qe_touch_wheel_cfg_config01[] = {NULL}; +#endif + +#if (QE_TOUCH_CONFIG01_NUM_TOUCH_PADS != 0) +const touch_pad_cfg_t g_qe_touch_touch_pad_cfg_config01 = {NULL}; +#endif + +const touch_cfg_t g_qe_touch_cfg_config01 = { + .p_buttons = g_qe_touch_button_cfg_config01, + .p_sliders = NULL, + .p_wheels = NULL, +#if (TOUCH_CFG_PAD_ENABLE != 0) + .p_pad = NULL, +#endif + .num_buttons = QE_TOUCH_CONFIG01_NUM_BUTTONS, + .num_sliders = QE_TOUCH_CONFIG01_NUM_SLIDERS, + .num_wheels = QE_TOUCH_CONFIG01_NUM_WHEELS, + + .number = 0, +#if ((TOUCH_CFG_UART_MONITOR_SUPPORT == 1) || (TOUCH_CFG_UART_TUNING_SUPPORT == 1)) + .p_uart_instance = &g_uart_qe, +#else + .p_uart_instance = NULL, +#endif + + .on_freq = 3, + .off_freq = 3, + .drift_freq = 255, + .cancel_freq = 0, + + .p_ctsu_instance = &g_qe_ctsu_instance_config01, +}; + +touch_instance_ctrl_t g_qe_touch_ctrl_config01; + +const touch_instance_t g_qe_touch_instance_config01 = { + .p_ctrl = &g_qe_touch_ctrl_config01, + .p_cfg = &g_qe_touch_cfg_config01, + .p_api = &g_touch_on_ctsu, +}; + +/* CTSU Related Information for [CONFIG02] configuration. */ + +const ctsu_element_cfg_t g_qe_ctsu_element_cfg_config02[] = { + {.ssdiv = CTSU_SSDIV_4000, .so = 0x021, .snum = 0x07, .sdpa = 0x0F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x032, .snum = 0x07, .sdpa = 0x0F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x02C, .snum = 0x07, .sdpa = 0x0F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x034, .snum = 0x07, .sdpa = 0x0F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x032, .snum = 0x07, .sdpa = 0x0F}, +}; + +const ctsu_cfg_t g_qe_ctsu_cfg_config02 = { + .cap = CTSU_CAP_SOFTWARE, + + .txvsel = CTSU_TXVSEL_INTERNAL_POWER, + .txvsel2 = CTSU_TXVSEL_MODE, + + .atune12 = CTSU_ATUNE12_40UA, + .md = CTSU_MODE_SELF_MULTI_SCAN, + .posel = CTSU_POSEL_SAME_PULSE, + + .ctsuchac0 = 0xF4, /* ch0-ch7 enable mask */ + .ctsuchac1 = 0x01, /* ch8-ch15 enable mask */ + .ctsuchac2 = 0x00, /* ch16-ch23 enable mask */ + .ctsuchac3 = 0x00, /* ch24-ch31 enable mask */ + .ctsuchac4 = 0x00, /* ch32-ch39 enable mask */ + .ctsuchtrc0 = 0x00, /* ch0-ch7 mutual tx mask */ + .ctsuchtrc1 = 0x01, /* ch8-ch15 mutual tx mask */ + .ctsuchtrc2 = 0x00, /* ch16-ch23 mutual tx mask */ + .ctsuchtrc3 = 0x00, /* ch24-ch31 mutual tx mask */ + .ctsuchtrc4 = 0x00, /* ch32-ch39 mutual tx mask */ + .num_rx = 5, + .num_tx = 0, + .p_elements = g_qe_ctsu_element_cfg_config02, + +#if (CTSU_TARGET_VALUE_CONFIG_SUPPORT == 1) + .tuning_self_target_value = 4608, + .tuning_mutual_target_value = 10240, +#endif + + .num_moving_average = 4, + .p_callback = &qe_touch_callback, +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + .p_transfer_tx = &g_transfer0, + .p_transfer_rx = &g_transfer1, +#else + .p_transfer_tx = NULL, + .p_transfer_rx = NULL, +#endif + + .write_irq = CTSU_WRITE_IRQn, + .read_irq = CTSU_READ_IRQn, + .end_irq = CTSU_END_IRQn, + +}; + +ctsu_instance_ctrl_t g_qe_ctsu_ctrl_config02; + +const ctsu_instance_t g_qe_ctsu_instance_config02 = { + .p_ctrl = &g_qe_ctsu_ctrl_config02, + .p_cfg = &g_qe_ctsu_cfg_config02, + .p_api = &g_ctsu_on_ctsu, +}; + +/* Touch Related Information for [CONFIG02] configuration. */ + +#define QE_TOUCH_CONFIG02_NUM_BUTTONS (0) +#define QE_TOUCH_CONFIG02_NUM_SLIDERS (1) +#define QE_TOUCH_CONFIG02_NUM_WHEELS (0) +#define QE_TOUCH_CONFIG02_NUM_TOUCH_PADS (0) + +#if (QE_TOUCH_CONFIG02_NUM_BUTTONS != 0) +const touch_button_cfg_t g_qe_touch_button_cfg_config02[] = {NULL}; +#endif + +const uint8_t g_qe_touch_elem_slider_config02_slider00[] = {1, 0, 2, 4, 3}; + +#if (QE_TOUCH_CONFIG02_NUM_SLIDERS != 0) +const touch_slider_cfg_t g_qe_touch_slider_cfg_config02[] = { + { + .p_elem_index = g_qe_touch_elem_slider_config02_slider00, + .num_elements = 5, + .threshold = 570, + }, +}; +#endif + +#if (QE_TOUCH_CONFIG02_NUM_WHEELS != 0) +const touch_wheel_cfg_t g_qe_touch_wheel_cfg_config02[] = {NULL}; +#endif + +#if (QE_TOUCH_CONFIG02_NUM_TOUCH_PADS != 0) +const touch_pad_cfg_t g_qe_touch_touch_pad_cfg_config02 = {NULL}; +#endif + +const touch_cfg_t g_qe_touch_cfg_config02 = { + .p_buttons = NULL, + .p_sliders = g_qe_touch_slider_cfg_config02, + .p_wheels = NULL, +#if (TOUCH_CFG_PAD_ENABLE != 0) + .p_pad = NULL, +#endif + .num_buttons = QE_TOUCH_CONFIG02_NUM_BUTTONS, + .num_sliders = QE_TOUCH_CONFIG02_NUM_SLIDERS, + .num_wheels = QE_TOUCH_CONFIG02_NUM_WHEELS, + + .number = 1, +#if ((TOUCH_CFG_UART_MONITOR_SUPPORT == 1) || (TOUCH_CFG_UART_TUNING_SUPPORT == 1)) + .p_uart_instance = &g_uart_qe, +#else + .p_uart_instance = NULL, +#endif + + .on_freq = 3, + .off_freq = 3, + .drift_freq = 255, + .cancel_freq = 0, + + .p_ctsu_instance = &g_qe_ctsu_instance_config02, +}; + +touch_instance_ctrl_t g_qe_touch_ctrl_config02; + +const touch_instance_t g_qe_touch_instance_config02 = { + .p_ctrl = &g_qe_touch_ctrl_config02, + .p_cfg = &g_qe_touch_cfg_config02, + .p_api = &g_touch_on_ctsu, +}; + +/* CTSU Related Information for [CONFIG03] configuration. */ + +const ctsu_element_cfg_t g_qe_ctsu_element_cfg_config03[] = { + {.ssdiv = CTSU_SSDIV_4000, .so = 0x03F, .snum = 0x07, .sdpa = 0x0F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x03D, .snum = 0x07, .sdpa = 0x0F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x041, .snum = 0x07, .sdpa = 0x0F}, + {.ssdiv = CTSU_SSDIV_4000, .so = 0x037, .snum = 0x07, .sdpa = 0x0F}, +}; + +const ctsu_cfg_t g_qe_ctsu_cfg_config03 = { + .cap = CTSU_CAP_SOFTWARE, + + .txvsel = CTSU_TXVSEL_INTERNAL_POWER, + .txvsel2 = CTSU_TXVSEL_MODE, + + .atune12 = CTSU_ATUNE12_40UA, + .md = CTSU_MODE_SELF_MULTI_SCAN, + .posel = CTSU_POSEL_SAME_PULSE, + + .ctsuchac0 = 0x00, /* ch0-ch7 enable mask */ + .ctsuchac1 = 0x40, /* ch8-ch15 enable mask */ + .ctsuchac2 = 0xA4, /* ch16-ch23 enable mask */ + .ctsuchac3 = 0x00, /* ch24-ch31 enable mask */ + .ctsuchac4 = 0x01, /* ch32-ch39 enable mask */ + .ctsuchtrc0 = 0x00, /* ch0-ch7 mutual tx mask */ + .ctsuchtrc1 = 0x40, /* ch8-ch15 mutual tx mask */ + .ctsuchtrc2 = 0x00, /* ch16-ch23 mutual tx mask */ + .ctsuchtrc3 = 0x00, /* ch24-ch31 mutual tx mask */ + .ctsuchtrc4 = 0x00, /* ch32-ch39 mutual tx mask */ + .num_rx = 4, + .num_tx = 0, + .p_elements = g_qe_ctsu_element_cfg_config03, + +#if (CTSU_TARGET_VALUE_CONFIG_SUPPORT == 1) + .tuning_self_target_value = 4608, + .tuning_mutual_target_value = 10240, +#endif + + .num_moving_average = 4, + .p_callback = &qe_touch_callback, +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + .p_transfer_tx = &g_transfer0, + .p_transfer_rx = &g_transfer1, +#else + .p_transfer_tx = NULL, + .p_transfer_rx = NULL, +#endif + + .write_irq = CTSU_WRITE_IRQn, + .read_irq = CTSU_READ_IRQn, + .end_irq = CTSU_END_IRQn, + +}; + +ctsu_instance_ctrl_t g_qe_ctsu_ctrl_config03; + +const ctsu_instance_t g_qe_ctsu_instance_config03 = { + .p_ctrl = &g_qe_ctsu_ctrl_config03, + .p_cfg = &g_qe_ctsu_cfg_config03, + .p_api = &g_ctsu_on_ctsu, +}; + +/* Touch Related Information for [CONFIG03] configuration. */ + +#define QE_TOUCH_CONFIG03_NUM_BUTTONS (0) +#define QE_TOUCH_CONFIG03_NUM_SLIDERS (0) +#define QE_TOUCH_CONFIG03_NUM_WHEELS (1) +#define QE_TOUCH_CONFIG03_NUM_TOUCH_PADS (0) + +#if (QE_TOUCH_CONFIG03_NUM_BUTTONS != 0) +const touch_button_cfg_t g_qe_touch_button_cfg_config03[] = {NULL}; +#endif + +#if (QE_TOUCH_CONFIG03_NUM_SLIDERS != 0) +const touch_slider_cfg_t g_qe_touch_slider_cfg_config03[] = {NULL}; +#endif + +const uint8_t g_qe_touch_elem_wheel_config03_wheel00[] = {0, 1, 2, 3}; + +#if (QE_TOUCH_CONFIG03_NUM_WHEELS != 0) +const touch_wheel_cfg_t g_qe_touch_wheel_cfg_config03[] = { + { + .p_elem_index = g_qe_touch_elem_wheel_config03_wheel00, + .num_elements = 4, + .threshold = 585, + }, +}; +#endif + +#if (QE_TOUCH_CONFIG03_NUM_TOUCH_PADS != 0) +const touch_pad_cfg_t g_qe_touch_touch_pad_cfg_config03 = {NULL}; +#endif + +const touch_cfg_t g_qe_touch_cfg_config03 = { + .p_buttons = NULL, + .p_sliders = NULL, + .p_wheels = g_qe_touch_wheel_cfg_config03, +#if (TOUCH_CFG_PAD_ENABLE != 0) + .p_pad = NULL, +#endif + .num_buttons = QE_TOUCH_CONFIG03_NUM_BUTTONS, + .num_sliders = QE_TOUCH_CONFIG03_NUM_SLIDERS, + .num_wheels = QE_TOUCH_CONFIG03_NUM_WHEELS, + + .number = 2, +#if ((TOUCH_CFG_UART_MONITOR_SUPPORT == 1) || (TOUCH_CFG_UART_TUNING_SUPPORT == 1)) + .p_uart_instance = &g_uart_qe, +#else + .p_uart_instance = NULL, +#endif + + .on_freq = 3, + .off_freq = 3, + .drift_freq = 255, + .cancel_freq = 0, + + .p_ctsu_instance = &g_qe_ctsu_instance_config03, +}; + +touch_instance_ctrl_t g_qe_touch_ctrl_config03; + +const touch_instance_t g_qe_touch_instance_config03 = { + .p_ctrl = &g_qe_touch_ctrl_config03, + .p_cfg = &g_qe_touch_cfg_config03, + .p_api = &g_touch_on_ctsu, +}; diff --git a/samples/shields/rtk0eg0019b01002bj/src/qe_touch_config.h b/samples/shields/rtk0eg0019b01002bj/src/qe_touch_config.h new file mode 100644 index 0000000000000..943c478b8f777 --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/src/qe_touch_config.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef QE_TOUCH_CONFIG_H +#define QE_TOUCH_CONFIG_H + +/* Generated content from Renesas QE Capacitive Touch */ + +#include "hal_data.h" +#include "qe_touch_define.h" + +extern const ctsu_instance_t g_qe_ctsu_instance_config01; +extern const ctsu_instance_t g_qe_ctsu_instance_config02; +extern const ctsu_instance_t g_qe_ctsu_instance_config03; +extern const touch_instance_t g_qe_touch_instance_config01; +extern const touch_instance_t g_qe_touch_instance_config02; +extern const touch_instance_t g_qe_touch_instance_config03; + +extern volatile uint8_t g_qe_touch_flag; +extern volatile ctsu_event_t g_qe_ctsu_event; + +extern void qe_touch_callback(touch_callback_args_t *p_args); + +#endif /* QE_TOUCH_CONFIG_H */ diff --git a/samples/shields/rtk0eg0019b01002bj/src/qe_touch_define.h b/samples/shields/rtk0eg0019b01002bj/src/qe_touch_define.h new file mode 100644 index 0000000000000..acc40851ce262 --- /dev/null +++ b/samples/shields/rtk0eg0019b01002bj/src/qe_touch_define.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef QE_TOUCH_DEFINE_H +#define QE_TOUCH_DEFINE_H + +/* Generated content from Renesas QE Capacitive Touch */ + +#define QE_TOUCH_VERSION (0x0410) + +#define CTSU_CFG_NUM_SELF_ELEMENTS (12) + +#define CTSU_CFG_NUM_MUTUAL_ELEMENTS (0) +#define CTSU_CFG_NUM_CFC (0) +#define CTSU_CFG_NUM_CFC_TX (0) + +#define TOUCH_CFG_MONITOR_ENABLE (1) +#define TOUCH_CFG_NUM_BUTTONS (3) +#define TOUCH_CFG_NUM_SLIDERS (1) +#define TOUCH_CFG_NUM_WHEELS (1) +#define TOUCH_CFG_PAD_ENABLE (0) + +#define QE_TOUCH_MACRO_CTSU_IP_KIND (2) + +#define CTSU_CFG_VCC_MV (5000) +#define CTSU_CFG_LOW_VOLTAGE_MODE (0) + +#define CTSU_CFG_PCLK_DIVISION (0) + +#define CTSU_CFG_TSCAP_PORT (0x010C) + +#define CTSU_CFG_NUM_SUMULTI (3) +#define CTSU_CFG_SUMULTI0 (0x3F) +#define CTSU_CFG_SUMULTI1 (0x36) +#define CTSU_CFG_SUMULTI2 (0x48) + +#define CTSU_CFG_CALIB_RTRIM_SUPPORT (0) +#define CTSU_CFG_TEMP_CORRECTION_SUPPORT (0) +#define CTSU_CFG_TEMP_CORRECTION_TS (0) +#define CTSU_CFG_TEMP_CORRECTION_TIME (0) + +#define CTSU_CFG_TARGET_VALUE_QE_SUPPORT (1) + +#define CTSU_CFG_MAJORITY_MODE (1) +#define CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS (0) +#define CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS (0) + +#define CONFIG01_INDEX_BUTTON00 (2) +#define CONFIG01_MASK_BUTTON00 (1ULL << CONFIG01_INDEX_BUTTON00) +#define CONFIG01_INDEX_BUTTON01 (1) +#define CONFIG01_MASK_BUTTON01 (1ULL << CONFIG01_INDEX_BUTTON01) +#define CONFIG01_INDEX_BUTTON02 (0) +#define CONFIG01_MASK_BUTTON02 (1ULL << CONFIG01_INDEX_BUTTON02) + +#endif /* QE_TOUCH_DEFINE_H */ diff --git a/samples/shields/shields.rst b/samples/shields/shields.rst index f1cea031eeb77..c901ebf1eb767 100644 --- a/samples/shields/shields.rst +++ b/samples/shields/shields.rst @@ -1,6 +1,6 @@ .. zephyr:code-sample-category:: shields :name: Shields :show-listing: - :glob: **/* + :glob: */* Samples that demonstrate the use of shields in Zephyr. diff --git a/samples/shields/x_nucleo_iks01a3/standard/app.overlay b/samples/shields/x_nucleo_iks01a3/standard/app.overlay index 86abf4f60f4e0..3603e4b75dffb 100644 --- a/samples/shields/x_nucleo_iks01a3/standard/app.overlay +++ b/samples/shields/x_nucleo_iks01a3/standard/app.overlay @@ -13,7 +13,6 @@ lis2de18_18_x_nucleo_iks01a3: lis2de12@18 { compatible = "st,lis2de12"; reg = <0x18>; - int1-gpios = <&arduino_header 5 GPIO_ACTIVE_HIGH>; /* A5 */ + int1-gpios = <&arduino_header 5 GPIO_ACTIVE_HIGH>; /* A5 */ }; - }; diff --git a/samples/subsys/canbus/canbus.rst b/samples/subsys/canbus/canbus.rst index cfc8c75756ab8..3deddf38e7859 100644 --- a/samples/subsys/canbus/canbus.rst +++ b/samples/subsys/canbus/canbus.rst @@ -1,15 +1,3 @@ -.. _canbus-samples: - -Controller Area Network (CAN) Bus Samples -######################################### - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* - - .. zephyr:code-sample-category:: canbus :name: Controller Area Network (CAN) Bus :show-listing: diff --git a/samples/subsys/cpu_freq/cpu_freq.rst b/samples/subsys/cpu_freq/cpu_freq.rst new file mode 100644 index 0000000000000..10df55ed78517 --- /dev/null +++ b/samples/subsys/cpu_freq/cpu_freq.rst @@ -0,0 +1,5 @@ +.. zephyr:code-sample-category:: cpu_freq + :name: CPU Freq + :show-listing: + + These samples demonstrate the :ref:`CPU Freq ` subsystem. diff --git a/samples/subsys/cpu_freq/on_demand/CMakeLists.txt b/samples/subsys/cpu_freq/on_demand/CMakeLists.txt new file mode 100644 index 0000000000000..e49dea6d87f38 --- /dev/null +++ b/samples/subsys/cpu_freq/on_demand/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(cpu_freq_sample) + +target_sources(app PRIVATE src/main.c) diff --git a/samples/subsys/cpu_freq/on_demand/README.rst b/samples/subsys/cpu_freq/on_demand/README.rst new file mode 100644 index 0000000000000..a89d5ec0cc54d --- /dev/null +++ b/samples/subsys/cpu_freq/on_demand/README.rst @@ -0,0 +1,13 @@ +.. zephyr:code-sample:: cpu_freq_on_demand + :name: On-demand CPU frequency scaling + + Dynamically scale CPU frequency using the on-demand policy. + +Overview +******** + +This sample demonstrates the :ref:`CPU frequency subsystem's ` on-demand policy. The +sample will print debug information like CPU load and CPU frequency subsystem logs to the +console for visibility into the subsystem. + +The example will iterate through some simulated CPU processing scenarios in the main application. diff --git a/samples/subsys/cpu_freq/on_demand/prj.conf b/samples/subsys/cpu_freq/on_demand/prj.conf new file mode 100644 index 0000000000000..334b33e10bf48 --- /dev/null +++ b/samples/subsys/cpu_freq/on_demand/prj.conf @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_LOG=y + +# CPU Frequency Subsystem Configuration +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_LOG_LEVEL_DBG=y +CONFIG_CPU_LOAD_LOG_LEVEL_DBG=y +CONFIG_CPU_FREQ_POLICY_ON_DEMAND=y +CONFIG_CPU_FREQ_INTERVAL_MS=500 diff --git a/samples/subsys/cpu_freq/on_demand/sample.yaml b/samples/subsys/cpu_freq/on_demand/sample.yaml new file mode 100644 index 0000000000000..0d872cdadecf0 --- /dev/null +++ b/samples/subsys/cpu_freq/on_demand/sample.yaml @@ -0,0 +1,23 @@ +sample: + description: CPU frequency scaling sample + name: CPU Freq Sample +common: + integration_platforms: + - native_sim + - native_sim/native/64 + tags: cpu_freq +tests: + sample.cpu_freq: + platform_allow: + - native_sim + - native_sim/native/64 + harness: console + harness_config: + type: multi_line + regex: + - "^.* cpu_freq_sample: Starting CPU Freq Subsystem Sample!" + - "^.* cpu_load_metric: cpu_load_get: Execution cycles: [0-9]+, Total cycles: [0-9]+" + - "^.* cpu_freq_policy_on_demand: cpu_freq_policy_select_pstate: Current CPU Load: \ + [0-9]+%" + - "^.* cpu_freq_policy_on_demand: cpu_freq_policy_select_pstate: On-Demand Policy: \ + Selected P-state [0-9]+ with load_threshold=[0-9]+%" diff --git a/samples/subsys/cpu_freq/on_demand/src/main.c b/samples/subsys/cpu_freq/on_demand/src/main.c new file mode 100644 index 0000000000000..dad87a300c0b2 --- /dev/null +++ b/samples/subsys/cpu_freq/on_demand/src/main.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +LOG_MODULE_REGISTER(cpu_freq_sample, LOG_LEVEL_INF); + +#define MS_TO_US(x) ((x) * 1000) +#define PERCENT_SLEEP_MS (CONFIG_CPU_FREQ_INTERVAL_MS / 100) + +typedef enum { + CPU_SCENARIO_0, + CPU_SCENARIO_1, + CPU_SCENARIO_2, + CPU_SCENARIO_3, + CPU_SCENARIO_4, + CPU_SCENARIO_COUNT +} cpu_scenario_t; + +static int curr_work_time_ms; +static cpu_scenario_t cpu_scenario = CPU_SCENARIO_0; + +static void update_sleep_time(struct k_timer *timer_id) +{ + cpu_scenario = (cpu_scenario + 1) % CPU_SCENARIO_COUNT; + + switch (cpu_scenario) { + case CPU_SCENARIO_0: + /* CPU is always in sleep */ + curr_work_time_ms = 0; + break; + case CPU_SCENARIO_1: + /* CPU doing some intermittent processing */ + curr_work_time_ms = PERCENT_SLEEP_MS * 10; + break; + case CPU_SCENARIO_2: + /* CPU doing some more intense processing */ + curr_work_time_ms = PERCENT_SLEEP_MS * 25; + break; + case CPU_SCENARIO_3: + /* CPU doing some more intense processing */ + curr_work_time_ms = PERCENT_SLEEP_MS * 50; + break; + case CPU_SCENARIO_4: + /* CPU doing lots of calculations */ + curr_work_time_ms = PERCENT_SLEEP_MS * 100; + break; + default: + LOG_ERR("Unknown CPU scenario: %d", cpu_scenario); + } +} + +K_TIMER_DEFINE(timer, update_sleep_time, NULL); + +int main(void) +{ + LOG_INF("Starting CPU Freq Subsystem Sample!"); + + curr_work_time_ms = 0; + + /* Set timer to change cpu scenario periodically */ + k_timer_start(&timer, K_MSEC(CONFIG_CPU_FREQ_INTERVAL_MS), + K_MSEC(CONFIG_CPU_FREQ_INTERVAL_MS)); + + while (1) { + k_busy_wait(MS_TO_US(curr_work_time_ms)); + k_msleep(CONFIG_CPU_FREQ_INTERVAL_MS - curr_work_time_ms); + } +} diff --git a/samples/subsys/crc/CMakeLists.txt b/samples/subsys/crc/CMakeLists.txt new file mode 100644 index 0000000000000..ba3b28b077e75 --- /dev/null +++ b/samples/subsys/crc/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(subsys_crc_example) + +target_sources(app PRIVATE src/main.c) diff --git a/samples/subsys/crc/README.rst b/samples/subsys/crc/README.rst new file mode 100644 index 0000000000000..f4402c02be7a3 --- /dev/null +++ b/samples/subsys/crc/README.rst @@ -0,0 +1,57 @@ +.. zephyr:code-sample:: crc_subsys + :name: Cyclic Redundancy Check Subsystem (CRC Subsys) + + Compute and verify a CRC computation using the CRC subsys API. + +Overview +******** + +This sample demonstrates how to use the Cyclic Redundancy Check Subsystem + +Configuration Options +********************* + +This sample uses the following Kconfig options: + +- ``CONFIG_CRC``: Enable CRC functionality. +- ``CONFIG_CRC*``: Use software-based CRC if a chosen node is present; otherwise, hardware acceleration is used. + +These options can be modified in the project's ``prj.conf`` file or passed via CMake arguments. + +Building and Running +******************** + +Building and Running for Renesas RA8M1 +====================================== + +The sample can be built and executed for the +:zephyr:board:`ek_ra8m1` as follows: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/crc + :board: ek_ra8m1 + :goals: build flash + :compact: + +To build for another board, change "ek_ra8m1" above to that board's name. + +Sample Output +============= + +.. code-block:: console + + subsys_crc_example: Result of CRC32 IEEE: 0xCEA4A6C2 + subsys_crc_example: Result of CRC8 CCITT: 0x96 + subsys_crc_example: CRC computation completed successfully + +.. note:: + If the board does not support a hardware CRC driver, the computation will fall + back to a software-based implementation. + +Expected Behavior +***************** + +When the sample runs, it should: + +1. Compute the CRC32 and CRC8 values of predefined data. +2. Print the computed CRC values. diff --git a/samples/subsys/crc/prj.conf b/samples/subsys/crc/prj.conf new file mode 100644 index 0000000000000..411e4bf848c5e --- /dev/null +++ b/samples/subsys/crc/prj.conf @@ -0,0 +1,2 @@ +CONFIG_CRC=y +CONFIG_LOG=y diff --git a/samples/subsys/crc/sample.yaml b/samples/subsys/crc/sample.yaml new file mode 100644 index 0000000000000..106b3cc611d65 --- /dev/null +++ b/samples/subsys/crc/sample.yaml @@ -0,0 +1,13 @@ +sample: + name: CRC Subsystem +tests: + samples.subsys.crc: + depends_on: crc + tags: + - subsys + - crc + harness: console + harness_config: + type: one_line + regex: + - "CRC computation completed successfully" diff --git a/samples/subsys/crc/src/main.c b/samples/subsys/crc/src/main.c new file mode 100644 index 0000000000000..c677508146e09 --- /dev/null +++ b/samples/subsys/crc/src/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(subsys_crc_example, CONFIG_LOG_DEFAULT_LEVEL); + +#include + +int main(void) +{ + uint32_t result; + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + /* CRC computation */ + result = crc32_ieee(data, sizeof(data)); + LOG_INF("Result of CRC32 IEEE: 0x%08X", result); + + /* CRC computation */ + result = (uint8_t)crc8_ccitt(0xFF, data, sizeof(data)); + LOG_INF("Result of CRC8 CCITT: 0x%02X", result & 0xFF); + + LOG_INF("CRC computation completed successfully"); + + return 0; +} diff --git a/samples/subsys/dap/prj.conf b/samples/subsys/dap/prj.conf index 062bec175698d..23cdef69a6a3a 100644 --- a/samples/subsys/dap/prj.conf +++ b/samples/subsys/dap/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_SAMPLE_USBD_PRODUCT="Zephyr CMSIS-DAP" CONFIG_SAMPLE_USBD_PID=0x0204 CONFIG_SAMPLE_USBD_20_EXTENSION_DESC=y diff --git a/samples/subsys/display/lvgl/README.rst b/samples/subsys/display/lvgl/README.rst index 080c5f33a3313..cc58c4728ad9a 100644 --- a/samples/subsys/display/lvgl/README.rst +++ b/samples/subsys/display/lvgl/README.rst @@ -48,9 +48,9 @@ or a board with an integrated display: - :zephyr:board:`esp_wrover_kit` - :zephyr:board:`adafruit_feather_esp32s3_tft` -or a simulated display environment in a :ref:`native_sim ` application: +or a simulated display environment in a :zephyr:board:`native_sim ` application: -- :ref:`native_sim` +- :zephyr:board:`native_sim` - `SDL2`_ or @@ -74,7 +74,7 @@ Example building for :zephyr:board:`nrf52840dk`: :shield: adafruit_2_8_tft_touch_v2 :goals: build flash -Example building for :ref:`native_sim `: +Example building for :zephyr:board:`native_sim `: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl diff --git a/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay b/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay index 1be2cffc5a7bf..021935c2aa224 100644 --- a/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay +++ b/samples/subsys/display/lvgl/boards/st25dv_mb1283_disco.overlay @@ -17,7 +17,9 @@ keypad { compatible = "zephyr,lvgl-keypad-input"; input = <&buttons>; - input-codes = ; - lvgl-codes = ; + input-codes = ; + lvgl-codes = ; }; }; diff --git a/samples/subsys/edac/README.rst b/samples/subsys/edac/README.rst index fb556b1c07b5b..0f15d544b6999 100644 --- a/samples/subsys/edac/README.rst +++ b/samples/subsys/edac/README.rst @@ -1,6 +1,6 @@ .. zephyr:code-sample:: edac :name: EDAC shell - :relevant-api: edac + :relevant-api: edac_interface Test error detection and correction (EDAC) using shell commands. diff --git a/samples/subsys/fs/fs_sample/boards/arduino_opta_stm32h747xx_m7.overlay b/samples/subsys/fs/fs_sample/boards/arduino_opta_stm32h747xx_m7.overlay index 0e881395b9585..2a51f28c451d3 100644 --- a/samples/subsys/fs/fs_sample/boards/arduino_opta_stm32h747xx_m7.overlay +++ b/samples/subsys/fs/fs_sample/boards/arduino_opta_stm32h747xx_m7.overlay @@ -6,7 +6,7 @@ / { flash_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,flash-disk"; partition = <&wlan_partition>; disk-name = "SD"; diff --git a/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index 5a063e3b862fa..a23dec3dd55a5 100644 --- a/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -36,7 +36,7 @@ / { msc_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,flash-disk"; partition = <&storage_partition>; disk-name = "SD"; diff --git a/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index 5a063e3b862fa..a23dec3dd55a5 100644 --- a/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -36,7 +36,7 @@ / { msc_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,flash-disk"; partition = <&storage_partition>; disk-name = "SD"; diff --git a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840.overlay b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840.overlay index 44f7dc1ea05cc..c678b865e8f4c 100644 --- a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840.overlay +++ b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840.overlay @@ -38,7 +38,7 @@ / { msc_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,flash-disk"; partition = <&storage_partition>; disk-name = "SD"; diff --git a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_qspi.overlay b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_qspi.overlay index 64107833fd697..c7291e24a9ae0 100644 --- a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_qspi.overlay +++ b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_qspi.overlay @@ -25,7 +25,7 @@ / { msc_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,flash-disk"; partition = <&external_partition>; disk-name = "SD"; diff --git a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk.overlay b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk.overlay index 99ad12dadb0a9..3f701dd5bb2b9 100644 --- a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk.overlay +++ b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk.overlay @@ -6,7 +6,7 @@ / { msc_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,ram-disk"; /* Sample, to make things easier, mounts all FAT * systems at "SD". diff --git a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk_region.overlay b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk_region.overlay index 63ec667505b47..288702db7f9de 100644 --- a/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk_region.overlay +++ b/samples/subsys/fs/fs_sample/boards/nrf52840dk_nrf52840_ram_disk_region.overlay @@ -36,7 +36,7 @@ }; msc_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,ram-disk"; /* Sample, to make things easier, mounts all FAT * systems at "SD". diff --git a/samples/subsys/fs/fs_sample/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/samples/subsys/fs/fs_sample/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index b754482189334..ceead62cb6f8c 100644 --- a/samples/subsys/fs/fs_sample/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/samples/subsys/fs/fs_sample/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -35,7 +35,7 @@ / { msc_disk0 { - status="okay"; + status = "okay"; compatible = "zephyr,flash-disk"; partition = <&storage_partition>; disk-name = "SD"; diff --git a/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay b/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay index 8cb06841754b2..63d5db9e2622c 100644 --- a/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay +++ b/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay @@ -29,12 +29,10 @@ reg = <0>; spi-max-frequency = <8000000>; jedec-id = [c2 28 17]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; + sfdp-bfp = [e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; size = <67108864>; has-dpd; t-enter-dpd = <10000>; diff --git a/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay b/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay index 95dd5d3940327..41050ef6afa1f 100644 --- a/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay +++ b/samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay @@ -54,14 +54,14 @@ status = "okay"; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - storage_partition: partition@0 { - label = "storage"; - reg = <0 DT_SIZE_M(8)>; - }; + storage_partition: partition@0 { + label = "storage"; + reg = <0 DT_SIZE_M(8)>; + }; }; }; }; diff --git a/samples/subsys/fs/zms/README.rst b/samples/subsys/fs/zms/README.rst index 98deead06d8e8..6dcd5c2c07abb 100644 --- a/samples/subsys/fs/zms/README.rst +++ b/samples/subsys/fs/zms/README.rst @@ -43,7 +43,7 @@ on native_sim target :compact: After running the generated image on a native_sim target, the output on the console shows the -multiple Iterations of read/write/delete exectuted. +multiple Iterations of read/write/delete executed. Sample Output ============= diff --git a/samples/subsys/input/draw_touch_events/README.rst b/samples/subsys/input/draw_touch_events/README.rst index 393651d57875e..aadace9081125 100644 --- a/samples/subsys/input/draw_touch_events/README.rst +++ b/samples/subsys/input/draw_touch_events/README.rst @@ -22,7 +22,7 @@ Below is an example on how to build the sample for :zephyr:board:`stm32f746g_dis :goals: build :compact: -For testing purposes without the need of any hardware, the :ref:`native_sim ` +For testing purposes without the need of any hardware, the :zephyr:board:`native_sim ` board is also supported and can be built as follows: .. zephyr-app-commands:: diff --git a/samples/subsys/input/input_dump/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/subsys/input/input_dump/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay new file mode 100644 index 0000000000000..2fe4739c5b43a --- /dev/null +++ b/samples/subsys/input/input_dump/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay @@ -0,0 +1,31 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + kpp = &kpp; + }; +}; + +&pinctrl { + kpp_default: kpp_default { + group0 { + pinmux = <&iomuxc_gpio_sd_b1_00_kpp_row7 + &iomuxc_gpio_sd_b1_01_kpp_col7 + &iomuxc_gpio_sd_b1_02_kpp_row6 + &iomuxc_gpio_sd_b1_03_kpp_col6>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; +}; + +&kpp { + pinctrl-0 = <&kpp_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/samples/subsys/input/input_dump/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/samples/subsys/input/input_dump/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay new file mode 100644 index 0000000000000..2fe4739c5b43a --- /dev/null +++ b/samples/subsys/input/input_dump/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay @@ -0,0 +1,31 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + kpp = &kpp; + }; +}; + +&pinctrl { + kpp_default: kpp_default { + group0 { + pinmux = <&iomuxc_gpio_sd_b1_00_kpp_row7 + &iomuxc_gpio_sd_b1_01_kpp_col7 + &iomuxc_gpio_sd_b1_02_kpp_row6 + &iomuxc_gpio_sd_b1_03_kpp_col6>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; +}; + +&kpp { + pinctrl-0 = <&kpp_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/stm32h747i_disco_stm32h747xx_m7.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/stm32h747i_disco_stm32h747xx_m7.overlay index 52a2facb9bf3a..839d3ab58751e 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/boards/stm32h747i_disco_stm32h747xx_m7.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/boards/stm32h747i_disco_stm32h747xx_m7.overlay @@ -13,18 +13,18 @@ /delete-node/ memory@38000000; sram_tx: memory@38000000 { - zephyr,memory-region = "SRAM_TX"; - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x38000000 0x08000>; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; - }; + zephyr,memory-region = "SRAM_TX"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x38000000 0x08000>; + zephyr,memory-attr = ; + }; sram_rx: memory@38008000 { - zephyr,memory-region = "SRAM_RX"; - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x38008000 0x08000>; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; - }; + zephyr,memory-region = "SRAM_RX"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x38008000 0x08000>; + zephyr,memory-attr = ; + }; ipc0: ipc0 { compatible = "zephyr,ipc-icmsg"; diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/stm32h747i_disco_stm32h747xx_m4.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/stm32h747i_disco_stm32h747xx_m4.overlay index 4b8d6f59f4f53..35a8a45297ab6 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/stm32h747i_disco_stm32h747xx_m4.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/stm32h747i_disco_stm32h747xx_m4.overlay @@ -16,18 +16,18 @@ /delete-node/ memory@38000000; sram_rx: memory@38000000 { - zephyr,memory-region = "SRAM_RX"; - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x38000000 0x08000>; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; - }; + zephyr,memory-region = "SRAM_RX"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x38000000 0x08000>; + zephyr,memory-attr = ; + }; sram_tx: memory@38008000 { - zephyr,memory-region = "SRAM_TX"; - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x38008000 0x08000>; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; - }; + zephyr,memory-region = "SRAM_TX"; + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x38008000 0x08000>; + zephyr,memory-attr = ; + }; ipc0: ipc0 { compatible = "zephyr,ipc-icmsg"; diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 1698d7a800d4b..812f3bdb1e124 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -1,7 +1,7 @@ / { reserved-memory { - /delete-node/ memory@2f0bf000; - /delete-node/ memory@2f0bf800; + /delete-node/ memory@2f0bf000; + /delete-node/ memory@2f0bf800; cpuapp_cpurad_ipc_shm_a: memory@2f0bf000 { reg = <0x2f0bf000 DT_SIZE_K(1)>; @@ -26,7 +26,7 @@ dcache-alignment = <32>; status = "okay"; mboxes = <&cpuapp_bellboard 20>, - <&cpurad_bellboard 14>; + <&cpurad_bellboard 14>; }; }; }; diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay index 26ef0518b8b5e..74ffd9ab56e11 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -26,7 +26,7 @@ dcache-alignment = <32>; status = "okay"; mboxes = <&cpuapp_bellboard 20>, - <&cpurad_bellboard 14>; + <&cpurad_bellboard 14>; }; }; }; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.overlay index 19bbe1e16d79a..fcdd3a33c851f 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -11,18 +11,18 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - sram1_ipc0: memory@20060000{ + sram1_ipc0: memory@20060000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20060000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC0"; + zephyr,memory-attr = ; }; - sram1_ipc1: memory@20064000{ + sram1_ipc1: memory@20064000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20064000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC1"; + zephyr,memory-attr = ; }; ipc { diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index 282c868cd1499..45f164e26df15 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -19,18 +19,18 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - sram4_ipc0: memory@20040000{ + sram4_ipc0: memory@20040000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20040000 DT_SIZE_K(8)>; - zephyr,memory-region="SRAM4_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM4_IPC0"; + zephyr,memory-attr = ; }; - sram4_ipc1: memory@20042000{ + sram4_ipc1: memory@20042000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20042000 DT_SIZE_K(8)>; - zephyr,memory-region="SRAM4_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM4_IPC1"; + zephyr,memory-attr = ; }; soc { @@ -38,7 +38,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mailbox0@5008b000 { + mbox: mailbox0@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; @@ -46,7 +46,7 @@ #mbox-cells = <1>; status = "okay"; }; - }; + }; ipc { /delete-node/ ipc0; @@ -69,6 +69,6 @@ zephyr,priority = <1 PRIO_COOP>; zephyr,buffer-size = <128>; status = "okay"; - }; - }; - }; + }; + }; +}; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay index 19bbe1e16d79a..fcdd3a33c851f 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay @@ -11,18 +11,18 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - sram1_ipc0: memory@20060000{ + sram1_ipc0: memory@20060000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20060000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC0"; + zephyr,memory-attr = ; }; - sram1_ipc1: memory@20064000{ + sram1_ipc1: memory@20064000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20064000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC1"; + zephyr,memory-attr = ; }; ipc { diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 35cf8f60649b6..208d43f46c9a5 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -22,17 +22,17 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - ocram2_ipc0: memory@202c0000{ + ocram2_ipc0: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC0"; + zephyr,memory-attr = ; }; - ocram2_ipc1: memory@202c8000{ + ocram2_ipc1: memory@202c8000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c8000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC1"; + zephyr,memory-attr = ; }; soc { @@ -40,7 +40,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay index 13f89c250e230..208d43f46c9a5 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -22,17 +22,17 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - ocram2_ipc0: memory@202c0000{ + ocram2_ipc0: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC0"; + zephyr,memory-attr = ; }; - ocram2_ipc1: memory@202c8000{ + ocram2_ipc1: memory@202c8000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c8000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC1"; + zephyr,memory-attr = ; }; soc { @@ -40,7 +40,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay index 2bcb576660516..ec3d51afcd429 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay @@ -12,15 +12,15 @@ ocram2_ipc0: memory@20500000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20500000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_IPC0"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC0"; + zephyr,memory-attr = ; }; ocram2_ipc1: memory@20504000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20504000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_IPC1"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC1"; + zephyr,memory-attr = ; }; ipc { diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay index 4960c98561609..717e5bda07514 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay @@ -11,18 +11,18 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - sram1_ipc0: memory@20060000{ + sram1_ipc0: memory@20060000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20060000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC0"; + zephyr,memory-attr = ; }; - sram1_ipc1: memory@20064000{ + sram1_ipc1: memory@20064000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20064000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC1"; + zephyr,memory-attr = ; }; ipc { diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay index 2fba21fb1e411..513a78be77111 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay @@ -19,18 +19,18 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - sram4_ipc0: memory@20040000{ + sram4_ipc0: memory@20040000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20040000 DT_SIZE_K(8)>; - zephyr,memory-region="SRAM4_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM4_IPC0"; + zephyr,memory-attr = ; }; - sram4_ipc1: memory@20042000{ + sram4_ipc1: memory@20042000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20042000 DT_SIZE_K(8)>; - zephyr,memory-region="SRAM4_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM4_IPC1"; + zephyr,memory-attr = ; }; soc { @@ -38,7 +38,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mailbox0@5008b000 { + mbox: mailbox0@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay index 4960c98561609..717e5bda07514 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay @@ -11,18 +11,18 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - sram1_ipc0: memory@20060000{ + sram1_ipc0: memory@20060000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20060000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC0"; + zephyr,memory-attr = ; }; - sram1_ipc1: memory@20064000{ + sram1_ipc1: memory@20064000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20064000 DT_SIZE_K(16)>; - zephyr,memory-region="SRAM1_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "SRAM1_IPC1"; + zephyr,memory-attr = ; }; ipc { diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 8ba9d176fd3ae..398e5fbc2e8fd 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -23,24 +23,24 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - ocram2_ipc0: memory@202c0000{ + ocram2_ipc0: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC0"; + zephyr,memory-attr = ; }; - ocram2_ipc1: memory@202c8000{ + ocram2_ipc1: memory@202c8000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c8000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC1"; + zephyr,memory-attr = ; }; soc { /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -51,7 +51,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 8ba9d176fd3ae..398e5fbc2e8fd 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -23,24 +23,24 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - ocram2_ipc0: memory@202c0000{ + ocram2_ipc0: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC0"; + zephyr,memory-attr = ; }; - ocram2_ipc1: memory@202c8000{ + ocram2_ipc1: memory@202c8000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c8000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC1"; + zephyr,memory-attr = ; }; soc { /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -51,7 +51,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 8ba9d176fd3ae..398e5fbc2e8fd 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -23,24 +23,24 @@ /* Define memory regions for IPC * Note that shared memory must have specific MPU attributes set. */ - ocram2_ipc0: memory@202c0000{ + ocram2_ipc0: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC0"; + zephyr,memory-attr = ; }; - ocram2_ipc1: memory@202c8000{ + ocram2_ipc1: memory@202c8000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c8000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_IPC1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC1"; + zephyr,memory-attr = ; }; soc { /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -51,7 +51,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay index d6958308790ea..b0a8702d4a528 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay +++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay @@ -12,15 +12,15 @@ ocram2_ipc0: memory@20500000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20500000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_IPC0"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC0"; + zephyr,memory-attr = ; }; ocram2_ipc1: memory@20504000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20504000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_IPC1"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_IPC1"; + zephyr,memory-attr = ; }; ipc { diff --git a/samples/subsys/ipc/openamp/Kconfig.sysbuild b/samples/subsys/ipc/openamp/Kconfig.sysbuild index 2aca97534edd0..b0548a0a0cf09 100644 --- a/samples/subsys/ipc/openamp/Kconfig.sysbuild +++ b/samples/subsys/ipc/openamp/Kconfig.sysbuild @@ -16,8 +16,5 @@ string default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947" default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk" default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk" - default "esp32s3_devkitm/esp32s3/appcpu" if $(BOARD) = "esp32s3_devkitm" default "esp32s3_devkitc/esp32s3/appcpu" if $(BOARD) = "esp32s3_devkitc" default "esp32_devkitc/esp32/appcpu" if $(BOARD) = "esp32_devkitc" - default "esp_wrover_kit/esp32/appcpu" if $(BOARD) = "esp_wrover_kit" - default "esp32_ethernet_kit/esp32/appcpu" if $(BOARD) = "esp32_ethernet_kit" diff --git a/samples/subsys/ipc/openamp/README.rst b/samples/subsys/ipc/openamp/README.rst index 9f3416ade7f84..9d6ae7aa7a7a1 100644 --- a/samples/subsys/ipc/openamp/README.rst +++ b/samples/subsys/ipc/openamp/README.rst @@ -9,16 +9,21 @@ Overview This application demonstrates how to use OpenAMP with Zephyr. It is designed to demonstrate how to integrate OpenAMP with Zephyr both from a build perspective -and code. Note that the remote and primary core images can be flashed +and code. + +Note that the remote and primary core images can be flashed independently, but sysbuild must be used in order to build the images. +Both cores must be flashed prior to using ``west debug`` on either core. +It is suggested to use ``west flash`` to do this as shown below. + Building the application for lpcxpresso54114_m4 *********************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp :board: lpcxpresso54114/lpc54114/m4 - :goals: debug + :goals: flash :west-args: --sysbuild Building the application for lpcxpresso55s69/lpc55s69/cpu0 @@ -27,7 +32,7 @@ Building the application for lpcxpresso55s69/lpc55s69/cpu0 .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp :board: lpcxpresso55s69/lpc55s69/cpu0 - :goals: debug + :goals: flash :west-args: --sysbuild Building the application for mps2/an521/cpu0 @@ -36,7 +41,7 @@ Building the application for mps2/an521/cpu0 .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp :board: mps2/an521/cpu0 - :goals: debug + :goals: flash :west-args: --sysbuild Building the application for v2m_musca_b1/musca_b1 @@ -45,7 +50,7 @@ Building the application for v2m_musca_b1/musca_b1 .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp :board: v2m_musca_b1/musca_b1 - :goals: debug + :goals: flash :west-args: --sysbuild Building the application for mimxrt1170_evk_cm7 @@ -54,7 +59,7 @@ Building the application for mimxrt1170_evk_cm7 .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp :board: mimxrt1170_evk_cm7 - :goals: debug + :goals: flash :west-args: --sysbuild Building the application for frdm_mcxn947/mcxn947/cpu0 @@ -63,7 +68,7 @@ Building the application for frdm_mcxn947/mcxn947/cpu0 .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp :board: frdm_mcxn947/mcxn947/cpu0 - :goals: debug + :goals: flash :west-args: --sysbuild Open a serial terminal (minicom, putty, etc.) and connect the board with the diff --git a/samples/subsys/ipc/openamp/remote/socs/esp32_appcpu.overlay b/samples/subsys/ipc/openamp/boards/esp32_devkitc_procpu.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/socs/esp32_appcpu.overlay rename to samples/subsys/ipc/openamp/boards/esp32_devkitc_procpu.overlay diff --git a/samples/subsys/ipc/openamp/remote/socs/esp32s3_appcpu.overlay b/samples/subsys/ipc/openamp/boards/esp32s3_devkitc_procpu.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/socs/esp32s3_appcpu.overlay rename to samples/subsys/ipc/openamp/boards/esp32s3_devkitc_procpu.overlay diff --git a/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.overlay index f2436532b8c15..a4996166d069e 100644 --- a/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.overlay +++ b/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -17,7 +17,7 @@ /* Delete MBOX Driver node */ /delete-node/ mbox@b2000; soc { - mailbox0:mailbox@400b2000 { + mailbox0: mailbox@400b2000 { compatible = "nxp,lpc-mailbox"; reg = <0x400b2000 0xEC>; interrupts = <54 0>; diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay b/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay index 61e3476ecb4ff..ffde319190651 100644 --- a/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay +++ b/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay @@ -13,7 +13,7 @@ zephyr,ipc = &mailbox0; }; - sramx1:memory@4000000{ + sramx1: memory@4000000 { compatible = "mmio-sram"; reg = <0x4000000 0x8000>; }; diff --git a/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay index f2436532b8c15..a4996166d069e 100644 --- a/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay +++ b/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay @@ -17,7 +17,7 @@ /* Delete MBOX Driver node */ /delete-node/ mbox@b2000; soc { - mailbox0:mailbox@400b2000 { + mailbox0: mailbox@400b2000 { compatible = "nxp,lpc-mailbox"; reg = <0x400b2000 0xEC>; interrupts = <54 0>; diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 7facea692cbea..cd3666e766621 100644 --- a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -15,10 +15,10 @@ * Define a subset of the OCRAM2 region for demo to use * Note that shared memory must have specific MPU attributes set. */ - ocram2_overlay: memory@202c0000{ + ocram2_overlay: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-region = "OCRAM2_OVERLAY"; + zephyr,memory-attr = ; }; }; diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay index 584538a14f799..1d28cbe0dcc6a 100644 --- a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -15,10 +15,10 @@ * Define a subset of the OCRAM2 region for demo to use * Note that shared memory must have specific MPU attributes set. */ - ocram2_overlay: memory@202c0000{ + ocram2_overlay: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-region = "OCRAM2_OVERLAY"; + zephyr,memory-attr = ; }; }; diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay index 582c4271c5d67..58a670bc69cf9 100644 --- a/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay +++ b/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay @@ -21,8 +21,8 @@ ocram2_sh_mem: memory@20500000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20500000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_SH_MEM"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_SH_MEM"; + zephyr,memory-attr = ; }; mailbox_a: ipm-mbox { diff --git a/samples/subsys/ipc/openamp/socs/esp32_procpu.overlay b/samples/subsys/ipc/openamp/remote/boards/esp32_devkitc_appcpu.overlay similarity index 100% rename from samples/subsys/ipc/openamp/socs/esp32_procpu.overlay rename to samples/subsys/ipc/openamp/remote/boards/esp32_devkitc_appcpu.overlay diff --git a/samples/subsys/ipc/openamp/socs/esp32s3_procpu.overlay b/samples/subsys/ipc/openamp/remote/boards/esp32s3_devkitc_appcpu.overlay similarity index 100% rename from samples/subsys/ipc/openamp/socs/esp32s3_procpu.overlay rename to samples/subsys/ipc/openamp/remote/boards/esp32s3_devkitc_appcpu.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay b/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay index f2436532b8c15..a4996166d069e 100644 --- a/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay @@ -17,7 +17,7 @@ /* Delete MBOX Driver node */ /delete-node/ mbox@b2000; soc { - mailbox0:mailbox@400b2000 { + mailbox0: mailbox@400b2000 { compatible = "nxp,lpc-mailbox"; reg = <0x400b2000 0xEC>; interrupts = <54 0>; diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay index 61e3476ecb4ff..ffde319190651 100644 --- a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay @@ -13,7 +13,7 @@ zephyr,ipc = &mailbox0; }; - sramx1:memory@4000000{ + sramx1: memory@4000000 { compatible = "mmio-sram"; reg = <0x4000000 0x8000>; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay b/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay index f2436532b8c15..a4996166d069e 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay @@ -17,7 +17,7 @@ /* Delete MBOX Driver node */ /delete-node/ mbox@b2000; soc { - mailbox0:mailbox@400b2000 { + mailbox0: mailbox@400b2000 { compatible = "nxp,lpc-mailbox"; reg = <0x400b2000 0xEC>; interrupts = <54 0>; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 87159192cf249..e6d8f03eba39d 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -19,7 +19,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -34,8 +34,8 @@ ocram2_overlay: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-region = "OCRAM2_OVERLAY"; + zephyr,memory-attr = ; }; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 87159192cf249..e6d8f03eba39d 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -19,7 +19,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -34,8 +34,8 @@ ocram2_overlay: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-region = "OCRAM2_OVERLAY"; + zephyr,memory-attr = ; }; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 72510d261664a..032da64c84966 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -17,7 +17,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -32,8 +32,8 @@ ocram2_overlay: memory@202c0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; - zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-region = "OCRAM2_OVERLAY"; + zephyr,memory-attr = ; }; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay index 80831a425fc9e..1cdc4c91c8df5 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay @@ -21,8 +21,8 @@ ocram2_sh_mem: memory@20500000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20500000 DT_SIZE_K(32)>; - zephyr,memory-region="OCRAM2_SH_MEM"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; + zephyr,memory-region = "OCRAM2_SH_MEM"; + zephyr,memory-attr = ; }; mailbox_b: ipm-mbox { diff --git a/samples/subsys/logging/dictionary/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/subsys/logging/dictionary/boards/nrf5340dk_nrf5340_cpuapp.overlay index 7a8ed4a444f9c..2d0a05f34a84e 100644 --- a/samples/subsys/logging/dictionary/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/subsys/logging/dictionary/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -3,7 +3,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { chosen { diff --git a/samples/subsys/logging/logger/arm_itm_swo.overlay b/samples/subsys/logging/logger/arm_itm_swo.overlay new file mode 100644 index 0000000000000..278ffb3ff70db --- /dev/null +++ b/samples/subsys/logging/logger/arm_itm_swo.overlay @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +&itm { + status = "okay"; +}; diff --git a/samples/subsys/logging/logger/boards/stm32h750b_dk.overlay b/samples/subsys/logging/logger/boards/stm32h750b_dk.overlay index 357e98e42f2e4..a44953886cce9 100644 --- a/samples/subsys/logging/logger/boards/stm32h750b_dk.overlay +++ b/samples/subsys/logging/logger/boards/stm32h750b_dk.overlay @@ -5,7 +5,7 @@ /* console UART */ &usart3 { dmas = <&dmamux1 2 46 STM32_DMA_PERIPH_TX>, - <&dmamux1 3 45 STM32_DMA_PERIPH_RX>; + <&dmamux1 3 45 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; status = "okay"; }; diff --git a/samples/subsys/logging/logger/sample.yaml b/samples/subsys/logging/logger/sample.yaml index 38c9402639470..1ce9f53496eca 100644 --- a/samples/subsys/logging/logger/sample.yaml +++ b/samples/subsys/logging/logger/sample.yaml @@ -65,3 +65,18 @@ tests: harness: keyboard extra_configs: - CONFIG_USERSPACE=y + + sample.logger.swo: + arch_allow: arm + platform_allow: + - apollo3_evb + - apollo3p_evb + integration_platforms: + - apollo3_evb + - apollo3p_evb + tags: + - logging + filter: CONFIG_HAS_SWO + extra_args: + - EXTRA_CONF_FILE="arm_itm_swo.conf" + - DTC_OVERLAY_FILE="arm_itm_swo.overlay" diff --git a/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay index 75e9f1b57442f..c0a84fcb827bf 100644 --- a/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/subsys/logging/multidomain/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -36,8 +36,8 @@ status = "okay"; bt_hci_ipc0: bt_hci_ipc0 { - status = "okay"; - compatible = "zephyr,bt-hci-ipc"; + status = "okay"; + compatible = "zephyr,bt-hci-ipc"; }; }; diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/boards/mimxrt1050_evk_hyperflash_ram_load.overlay b/samples/subsys/mgmt/mcumgr/smp_svr/boards/mimxrt1050_evk_hyperflash_ram_load.overlay index b8dc44b78fb5a..7e78f22e078c3 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/boards/mimxrt1050_evk_hyperflash_ram_load.overlay +++ b/samples/subsys/mgmt/mcumgr/smp_svr/boards/mimxrt1050_evk_hyperflash_ram_load.overlay @@ -44,7 +44,6 @@ sdram_split: sdram_split@80008000 { reg = <0x80008000 (0x2000000 - DT_SIZE_K(32))>; }; - }; /* Reduce size of slot 0 to match slot 1 */ diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/prj.conf b/samples/subsys/mgmt/mcumgr/smp_svr/prj.conf index 06a27644bacb2..925ac0c93a27e 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/prj.conf +++ b/samples/subsys/mgmt/mcumgr/smp_svr/prj.conf @@ -8,7 +8,7 @@ CONFIG_FLASH_MAP=y # Some command handlers require a large stack. CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2304 -CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=2176 # Ensure an MCUboot-compatible binary is generated. CONFIG_BOOTLOADER_MCUBOOT=y diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index 605007c630ecc..0a3685fc087b1 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -97,9 +97,9 @@ tests: # transport. Transport does not affect flags so it does not really matter which is selected, # flags should affect any transport the same way. sample.mcumgr.smp_svr.mcuboot_flags.direct_xip_withrevert: - extra_args: EXTRA_CONF_FILE="overlay-serial.conf" - extra_configs: - - CONFIG_MCUBOOT_BOOTLOADER_MODE_DIRECT_XIP_WITH_REVERT=y + extra_args: + - EXTRA_CONF_FILE="overlay-serial.conf" + - SB_CONFIG_MCUBOOT_MODE_DIRECT_XIP_WITH_REVERT=y platform_allow: - nrf52840dk/nrf52840 - pinnacle_100_dvk diff --git a/samples/subsys/modbus/rtu_server/cdc-acm.overlay b/samples/subsys/modbus/rtu_server/cdc-acm.overlay index 471a3d4da81ec..7b30c68aec26d 100644 --- a/samples/subsys/modbus/rtu_server/cdc-acm.overlay +++ b/samples/subsys/modbus/rtu_server/cdc-acm.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &zephyr_udc0 { cdc_acm_uart0: cdc_acm_uart0 { compatible = "zephyr,cdc-acm-uart"; diff --git a/samples/subsys/nvs/boards/disco_l475_iot1.overlay b/samples/subsys/nvs/boards/disco_l475_iot1.overlay index 786a8ff489a10..8397a9ad2930d 100644 --- a/samples/subsys/nvs/boards/disco_l475_iot1.overlay +++ b/samples/subsys/nvs/boards/disco_l475_iot1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - /delete-node/ &storage_partition; / { diff --git a/samples/subsys/sensing/simple/README.rst b/samples/subsys/sensing/simple/README.rst index f8ff0857b315b..ef3f07be53be5 100644 --- a/samples/subsys/sensing/simple/README.rst +++ b/samples/subsys/sensing/simple/README.rst @@ -26,7 +26,7 @@ The program runs in the following sequence: Building and Running ******************** -This application can be built and executed on :ref:`native_sim ` as follows: +This application can be built and executed on :zephyr:board:`native_sim ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/sensing/simple diff --git a/samples/subsys/sensing/simple/app.overlay b/samples/subsys/sensing/simple/app.overlay index f9892f42a56a1..5699236ceb2ce 100644 --- a/samples/subsys/sensing/simple/app.overlay +++ b/samples/subsys/sensing/simple/app.overlay @@ -10,7 +10,6 @@ * (and be extended to test) real hardware. */ - / { sensing: sensing-node { compatible = "zephyr,sensing"; diff --git a/samples/subsys/settings/src/main.c b/samples/subsys/settings/src/main.c index 761c911827338..e1fb1cf299f38 100644 --- a/samples/subsys/settings/src/main.c +++ b/samples/subsys/settings/src/main.c @@ -418,7 +418,7 @@ static void example_without_handler(void) } } -static void example_initialization(void) +static int example_initialization(void) { int rc; @@ -450,7 +450,7 @@ static void example_initialization(void) rc = settings_subsys_init(); if (rc) { printk("settings subsys initialization: fail (err %d)\n", rc); - return; + return rc; } printk("settings subsys initialization: OK.\n"); @@ -459,10 +459,13 @@ static void example_initialization(void) if (rc) { printk("subtree <%s> handler registered: fail (err %d)\n", alpha_handler.name, rc); + return rc; } printk("subtree <%s> handler registered: OK\n", alpha_handler.name); printk("subtree has static handler\n"); + + return 0; } static void example_delete(void) @@ -542,7 +545,9 @@ int main(void) printk("\n*** Settings usage example ***\n\n"); /* settings initialization */ - example_initialization(); + if (example_initialization() != 0) { + return 0; + } for (i = 0; i < 6; i++) { printk("\n##############\n"); diff --git a/samples/subsys/shell/fs/README.rst b/samples/subsys/shell/fs/README.rst index f3d860832255a..eb2cacd07dc62 100644 --- a/samples/subsys/shell/fs/README.rst +++ b/samples/subsys/shell/fs/README.rst @@ -20,7 +20,7 @@ Building native_sim ========== -You can build this sample for :ref:`native_sim ` with: +You can build this sample for :zephyr:board:`native_sim ` with: .. zephyr-app-commands:: :zephyr-app: samples/subsys/shell/fs @@ -42,7 +42,7 @@ to the UART. With FUSE access in the host filesystem --------------------------------------- -If you enable the :ref:`host FUSE filsystem access ` +If you enable the :ref:`host FUSE filesystem access ` you will also have the flash filesystem mounted and accessible from your Linux host filesystem. Before starting a build, make sure that the i386 pkgconfig directory is in your @@ -223,8 +223,8 @@ Remove a file or directory Flash Host Access ================= -For the :ref:`native sim board ` the flash partitions can be accessed from the host -Linux system. +For the :zephyr:board:`native sim board ` the flash partitions can be accessed from the +host Linux system. By default the flash partitions are accessible through the directory *flash* relative to the directory where the build is started. diff --git a/samples/subsys/smf/smf_calculator/README.rst b/samples/subsys/smf/smf_calculator/README.rst index ae67a316984c3..3a635430ef20b 100644 --- a/samples/subsys/smf/smf_calculator/README.rst +++ b/samples/subsys/smf/smf_calculator/README.rst @@ -69,7 +69,7 @@ a :ref:`adafruit_2_8_tft_touch_v2`. :shield: adafruit_2_8_tft_touch_v2 :compact: -For testing purpose without the need of any hardware, the :ref:`native_sim ` +For testing purpose without the need of any hardware, the :zephyr:board:`native_sim ` board is also supported and can be built as follows; .. zephyr-app-commands:: diff --git a/samples/subsys/tracing/gpio.overlay b/samples/subsys/tracing/gpio.overlay index 2879430bab4ae..181cd0c8cb4bf 100644 --- a/samples/subsys/tracing/gpio.overlay +++ b/samples/subsys/tracing/gpio.overlay @@ -13,7 +13,7 @@ high-level; low-level; gpio-controller; - #gpio-cells = < 0x2 >; - phandle = < 0x1 >; + #gpio-cells = <0x2>; + phandle = <0x1>; }; }; diff --git a/samples/subsys/tracing/prj_usb_ctf.conf b/samples/subsys/tracing/prj_usb_ctf.conf index d1de19087b241..d2141aad2f6f2 100644 --- a/samples/subsys/tracing/prj_usb_ctf.conf +++ b/samples/subsys/tracing/prj_usb_ctf.conf @@ -1,5 +1,6 @@ CONFIG_GPIO=y CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_TRACING=y CONFIG_TRACING_CTF=y diff --git a/samples/subsys/usb/cdc_acm/prj.conf b/samples/subsys/usb/cdc_acm/prj.conf index e0012027ec6aa..9a52c07728a32 100644 --- a/samples/subsys/usb/cdc_acm/prj.conf +++ b/samples/subsys/usb/cdc_acm/prj.conf @@ -4,11 +4,12 @@ CONFIG_STDOUT_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_LINE_CTRL=y CONFIG_USBD_CDC_ACM_CLASS=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_LOG=y CONFIG_USBD_LOG_LEVEL_ERR=y CONFIG_UDC_DRIVER_LOG_LEVEL_ERR=y -CONFIG_USBD_CDC_ACM_LOG_LEVEL_ERR=y +CONFIG_USBD_CDC_ACM_LOG_LEVEL_OFF=y CONFIG_SAMPLE_USBD_PID=0x0001 CONFIG_SAMPLE_USBD_PRODUCT="USBD CDC ACM sample" diff --git a/samples/subsys/usb/cdc_acm_bridge/app.overlay b/samples/subsys/usb/cdc_acm_bridge/app.overlay index ede7539223c6a..e29977b5f4e11 100644 --- a/samples/subsys/usb/cdc_acm_bridge/app.overlay +++ b/samples/subsys/usb/cdc_acm_bridge/app.overlay @@ -9,7 +9,6 @@ compatible = "zephyr,uart-bridge"; peers = <&cdc_acm_uart0 &arduino_serial>; }; - }; &arduino_serial { diff --git a/samples/subsys/usb/cdc_acm_bridge/prj.conf b/samples/subsys/usb/cdc_acm_bridge/prj.conf index e9aa6fc7d2a92..9142082353f2e 100644 --- a/samples/subsys/usb/cdc_acm_bridge/prj.conf +++ b/samples/subsys/usb/cdc_acm_bridge/prj.conf @@ -6,6 +6,7 @@ CONFIG_SERIAL=y CONFIG_UART_LINE_CTRL=y CONFIG_UART_USE_RUNTIME_CONFIGURE=y CONFIG_USBD_CDC_ACM_CLASS=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_SAMPLE_USBD_PID=0x0001 CONFIG_SAMPLE_USBD_PRODUCT="USBD CDC ACM bridge sample" diff --git a/samples/subsys/usb/dfu/prj.conf b/samples/subsys/usb/dfu/prj.conf index 4ac6e6dd8d2ee..2a32656bc41d0 100644 --- a/samples/subsys/usb/dfu/prj.conf +++ b/samples/subsys/usb/dfu/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_DFU=y CONFIG_LOG=y diff --git a/samples/subsys/usb/hid-keyboard/Kconfig b/samples/subsys/usb/hid-keyboard/Kconfig index 96c5455894806..cd1158d776d4c 100644 --- a/samples/subsys/usb/hid-keyboard/Kconfig +++ b/samples/subsys/usb/hid-keyboard/Kconfig @@ -1,6 +1,9 @@ # Copyright (c) 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 +config SAMPLE_USBD_REMOTE_WAKEUP + default y + # Source common USB sample options used to initialize new experimental USB # device stack. The scope of these options is limited to USB samples in project # tree, you cannot use them in your own application. diff --git a/samples/subsys/usb/hid-keyboard/prj.conf b/samples/subsys/usb/hid-keyboard/prj.conf index a854a502f0683..debd9e3abef60 100644 --- a/samples/subsys/usb/hid-keyboard/prj.conf +++ b/samples/subsys/usb/hid-keyboard/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_HID_SUPPORT=y CONFIG_LOG=y @@ -6,7 +7,6 @@ CONFIG_USBD_LOG_LEVEL_WRN=y CONFIG_USBD_HID_LOG_LEVEL_WRN=y CONFIG_UDC_DRIVER_LOG_LEVEL_WRN=y CONFIG_SAMPLE_USBD_PID=0x0007 -CONFIG_SAMPLE_USBD_REMOTE_WAKEUP=y CONFIG_GPIO=y CONFIG_INPUT=y diff --git a/samples/subsys/usb/hid-keyboard/sample.yaml b/samples/subsys/usb/hid-keyboard/sample.yaml index 6161ff90c2cf0..f53ae514f97c6 100644 --- a/samples/subsys/usb/hid-keyboard/sample.yaml +++ b/samples/subsys/usb/hid-keyboard/sample.yaml @@ -1,11 +1,17 @@ sample: name: USB HID keyboard sample common: - harness: button filter: dt_alias_exists("sw0") and dt_alias_exists("led0") depends_on: - usbd - gpio + tags: usb + timeout: 15 + harness: console + harness_config: + type: one_line + regex: + - "HID keyboard sample is initialized" integration_platforms: - nrf52840dk/nrf52840 - nrf54h20dk/nrf54h20/cpuapp @@ -17,17 +23,13 @@ common: - samd21_xpro - same54_xpro tests: - sample.usbd.hid-keyboard: - tags: usb + sample.usbd.hid-keyboard: {} sample.usbd.hid-keyboard.out-report: - tags: usb extra_args: - EXTRA_DTC_OVERLAY_FILE="out_report.overlay" sample.usbd.hid-keyboard.large-report: - tags: usb extra_args: - EXTRA_DTC_OVERLAY_FILE="large_in_report.overlay" sample.usbd.hid-keyboard.large-out-report: - tags: usb extra_args: - EXTRA_DTC_OVERLAY_FILE="large_out_report.overlay" diff --git a/samples/subsys/usb/hid-keyboard/src/main.c b/samples/subsys/usb/hid-keyboard/src/main.c index c02072d3f5df9..45580c95a845f 100644 --- a/samples/subsys/usb/hid-keyboard/src/main.c +++ b/samples/subsys/usb/hid-keyboard/src/main.c @@ -279,7 +279,8 @@ int main(void) continue; } - if (usbd_is_suspended(sample_usbd)) { + if (IS_ENABLED(CONFIG_SAMPLE_USBD_REMOTE_WAKEUP) && + usbd_is_suspended(sample_usbd)) { /* on a press of any button, send wakeup request */ if (kb_evt.value) { ret = usbd_wakeup_request(sample_usbd); diff --git a/samples/subsys/usb/hid-mouse/prj.conf b/samples/subsys/usb/hid-mouse/prj.conf index 9c8894b2126c6..396728521b9b1 100644 --- a/samples/subsys/usb/hid-mouse/prj.conf +++ b/samples/subsys/usb/hid-mouse/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_HID_SUPPORT=y CONFIG_LOG=y diff --git a/samples/subsys/usb/legacy/audio_headphones_microphone/prj.conf b/samples/subsys/usb/legacy/audio_headphones_microphone/prj.conf index a532f9cb731f2..b8ac1e218f9e6 100644 --- a/samples/subsys/usb/legacy/audio_headphones_microphone/prj.conf +++ b/samples/subsys/usb/legacy/audio_headphones_microphone/prj.conf @@ -5,6 +5,7 @@ CONFIG_USB_DEVICE_STACK=y CONFIG_DEPRECATION_TEST=y CONFIG_USB_DEVICE_PRODUCT="Zephyr USB audio sample" CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n #LOG subsystem related configs CONFIG_LOG=y diff --git a/samples/subsys/usb/legacy/audio_headset/prj.conf b/samples/subsys/usb/legacy/audio_headset/prj.conf index a532f9cb731f2..b8ac1e218f9e6 100644 --- a/samples/subsys/usb/legacy/audio_headset/prj.conf +++ b/samples/subsys/usb/legacy/audio_headset/prj.conf @@ -5,6 +5,7 @@ CONFIG_USB_DEVICE_STACK=y CONFIG_DEPRECATION_TEST=y CONFIG_USB_DEVICE_PRODUCT="Zephyr USB audio sample" CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n #LOG subsystem related configs CONFIG_LOG=y diff --git a/samples/subsys/usb/legacy/cdc_acm/prj.conf b/samples/subsys/usb/legacy/cdc_acm/prj.conf index 1bc7989fb2865..3673d1e2b3616 100644 --- a/samples/subsys/usb/legacy/cdc_acm/prj.conf +++ b/samples/subsys/usb/legacy/cdc_acm/prj.conf @@ -10,3 +10,4 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_LINE_CTRL=y CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n diff --git a/samples/subsys/usb/legacy/console/prj.conf b/samples/subsys/usb/legacy/console/prj.conf index 485142c696bca..796f062848ed3 100644 --- a/samples/subsys/usb/legacy/console/prj.conf +++ b/samples/subsys/usb/legacy/console/prj.conf @@ -3,6 +3,7 @@ CONFIG_DEPRECATION_TEST=y CONFIG_USB_DEVICE_PRODUCT="Zephyr USB console sample" CONFIG_USB_DEVICE_PID=0x0004 CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/samples/subsys/usb/legacy/dfu/prj.conf b/samples/subsys/usb/legacy/dfu/prj.conf index 34eb8ff8b1c26..9a9820e129614 100644 --- a/samples/subsys/usb/legacy/dfu/prj.conf +++ b/samples/subsys/usb/legacy/dfu/prj.conf @@ -15,3 +15,4 @@ CONFIG_USB_DRIVER_LOG_LEVEL_ERR=y CONFIG_USB_DEVICE_LOG_LEVEL_ERR=y CONFIG_BOOTLOADER_MCUBOOT=y CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n diff --git a/samples/subsys/usb/legacy/hci_usb/prj.conf b/samples/subsys/usb/legacy/hci_usb/prj.conf index 9268d21c5ef1f..9e484982cab35 100644 --- a/samples/subsys/usb/legacy/hci_usb/prj.conf +++ b/samples/subsys/usb/legacy/hci_usb/prj.conf @@ -6,6 +6,7 @@ CONFIG_DEPRECATION_TEST=y CONFIG_USB_DEVICE_PID=0x000B CONFIG_USB_DEVICE_BLUETOOTH=y CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n # We dont want any console or CDC ACM that may cause BlueZ to not detect hci_usb CONFIG_SERIAL=n diff --git a/samples/subsys/usb/legacy/hid-mouse/prj.conf b/samples/subsys/usb/legacy/hid-mouse/prj.conf index 068701a0a3530..e43ef0d6b8b26 100644 --- a/samples/subsys/usb/legacy/hid-mouse/prj.conf +++ b/samples/subsys/usb/legacy/hid-mouse/prj.conf @@ -4,6 +4,7 @@ CONFIG_USB_DEVICE_HID=y CONFIG_USB_DEVICE_PRODUCT="Zephyr HID mouse sample" CONFIG_USB_DEVICE_PID=0x0007 CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n CONFIG_LOG=y CONFIG_USB_DRIVER_LOG_LEVEL_ERR=y diff --git a/samples/subsys/usb/legacy/mass/prj.conf b/samples/subsys/usb/legacy/mass/prj.conf index ddb8934c8dacd..134a003355fe9 100644 --- a/samples/subsys/usb/legacy/mass/prj.conf +++ b/samples/subsys/usb/legacy/mass/prj.conf @@ -11,5 +11,6 @@ CONFIG_USB_MASS_STORAGE=y CONFIG_USB_DEVICE_LOG_LEVEL_ERR=y CONFIG_USB_MASS_STORAGE_LOG_LEVEL_ERR=y CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n CONFIG_MAIN_STACK_SIZE=1536 diff --git a/samples/subsys/usb/legacy/netusb/prj.conf b/samples/subsys/usb/legacy/netusb/prj.conf index dd6dfb9ca231e..239322da2fac7 100644 --- a/samples/subsys/usb/legacy/netusb/prj.conf +++ b/samples/subsys/usb/legacy/netusb/prj.conf @@ -32,3 +32,4 @@ CONFIG_USB_DEVICE_STACK=y CONFIG_DEPRECATION_TEST=y CONFIG_USB_DEVICE_NETWORK_ECM=y CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n diff --git a/samples/subsys/usb/legacy/webusb/prj.conf b/samples/subsys/usb/legacy/webusb/prj.conf index 93aab862650f7..03fc4cbca43b7 100644 --- a/samples/subsys/usb/legacy/webusb/prj.conf +++ b/samples/subsys/usb/legacy/webusb/prj.conf @@ -8,6 +8,7 @@ CONFIG_USB_DEVICE_PID=0x000A CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_LINE_CTRL=y CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n +CONFIG_USB_DEVICE_STACK_NEXT=n CONFIG_LOG=y CONFIG_USB_DRIVER_LOG_LEVEL_ERR=y diff --git a/samples/subsys/usb/mass/README.rst b/samples/subsys/usb/mass/README.rst index 910c34e7c1ecd..210fbfd75f709 100644 --- a/samples/subsys/usb/mass/README.rst +++ b/samples/subsys/usb/mass/README.rst @@ -43,9 +43,7 @@ for testing USB mass storage class implementation. FAT FS Example ============== -If more than 96KiB are available, FAT files system can be used -with a RAM-disk. Alternatively it is possible with the FLASH-based disk. -In this example we will build the sample with a RAM-based disk: +If more than 96KiB RAM are available, FAT files system can be used with a RAM-disk. .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass @@ -54,10 +52,22 @@ In this example we will build the sample with a RAM-based disk: :goals: build :compact: +Alternatively, FAT file system can be used on the SoC internal flash when the +storage partition is large enough. -In this example we will build the sample with a FLASH-based disk and FAT -file system for Adafruit Feather nRF52840 Express. This board configures -to use the external 16 MiBi QSPI flash chip with a 2 MiBy FAT partition. +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/usb/mass + :board: frdm_k64f + :gen-args: -DEXTRA_DTC_OVERLAY_FILE="flashdisk.overlay" -DCONFIG_APP_MSC_STORAGE_FLASH_FATFS=y -DCONFIG_DISK_DRIVER_SDMMC=n + :goals: build + :compact: + +The internal flash storage partition on the SoC may be too small for the FAT +file system. If the board has an external flash device, however, it can be used +for the FAT file system. The sample includes a few board overlay files for +configuring an external flash device. For example, there is an overlay file for +Adafruit Feather nRF52840 Express that allows you to use an external 16 MiBy +QSPI flash chip with a 2 MiBy FAT partition. .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass @@ -156,9 +166,20 @@ the transfer speed over SPI is very slow. LittleFS Example ================ -This board configures to use the external 64 MiBi QSPI flash chip with a -128 KiBy `littlefs`_ partition compatible with the one produced by the -:zephyr:code-sample:`littlefs` sample. +The sample can be built for any board that has a storage partition defined. + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/usb/mass + :board: reel_board + :gen-args: -DEXTRA_DTC_OVERLAY_FILE="flashdisk.overlay" -DCONFIG_APP_MSC_STORAGE_FLASH_LITTLEFS=y + :goals: build + :compact: + +If more storage space is needed, the board can be configured to use an external +flash device. This can be done using the same approach as in the FAT file +system example. In this example, the nRF52840DK board is configured to use an +external 64 MiB QSPI flash chip with a 128 KiBy `littlefs`_ partition +compatible with the one produced by the :zephyr:code-sample:`littlefs` sample. .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass diff --git a/samples/subsys/usb/mass/boards/adafruit_feather_nrf52840_sense.overlay b/samples/subsys/usb/mass/boards/adafruit_feather_nrf52840_sense.overlay index 5112c025af316..e6b0422856352 100644 --- a/samples/subsys/usb/mass/boards/adafruit_feather_nrf52840_sense.overlay +++ b/samples/subsys/usb/mass/boards/adafruit_feather_nrf52840_sense.overlay @@ -19,11 +19,4 @@ }; }; -/ { - msc_disk0 { - compatible = "zephyr,flash-disk"; - partition = <&storage_partition>; - disk-name = "NAND"; - cache-size = <4096>; - }; -}; +#include "../flashdisk.overlay" diff --git a/samples/subsys/usb/mass/boards/nrf52840dk_nrf52840.overlay b/samples/subsys/usb/mass/boards/nrf52840dk_nrf52840.overlay index fce982fff44ac..e672580cdb1ed 100644 --- a/samples/subsys/usb/mass/boards/nrf52840dk_nrf52840.overlay +++ b/samples/subsys/usb/mass/boards/nrf52840dk_nrf52840.overlay @@ -19,11 +19,4 @@ }; }; -/ { - msc_disk0 { - compatible = "zephyr,flash-disk"; - partition = <&storage_partition>; - disk-name = "NAND"; - cache-size = <4096>; - }; -}; +#include "../flashdisk.overlay" diff --git a/samples/subsys/usb/mass/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/subsys/usb/mass/boards/nrf5340dk_nrf5340_cpuapp.overlay index e529ffe970544..7ef6bc74015ad 100644 --- a/samples/subsys/usb/mass/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/samples/subsys/usb/mass/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -19,11 +19,4 @@ }; }; -/ { - msc_disk0 { - compatible = "zephyr,flash-disk"; - partition = <&storage_partition>; - disk-name = "NAND"; - cache-size = <4096>; - }; -}; +#include "../flashdisk.overlay" diff --git a/samples/subsys/usb/mass/boards/rpi_pico.overlay b/samples/subsys/usb/mass/boards/rpi_pico.overlay index bdafdd3c25966..98a7b8ae3be25 100644 --- a/samples/subsys/usb/mass/boards/rpi_pico.overlay +++ b/samples/subsys/usb/mass/boards/rpi_pico.overlay @@ -24,16 +24,9 @@ storage_partition: partition@100000 { label = "storage"; - reg = <0x100000 DT_SIZE_M(1)>; + reg = <0x100000 DT_SIZE_M(1)>; }; }; }; -/ { - msc_disk0 { - compatible = "zephyr,flash-disk"; - partition = <&storage_partition>; - disk-name = "NAND"; - cache-size = <4096>; - }; -}; +#include "../flashdisk.overlay" diff --git a/samples/subsys/usb/mass/flashdisk.overlay b/samples/subsys/usb/mass/flashdisk.overlay new file mode 100644 index 0000000000000..08d991d05e9c8 --- /dev/null +++ b/samples/subsys/usb/mass/flashdisk.overlay @@ -0,0 +1,14 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + msc_disk0 { + compatible = "zephyr,flash-disk"; + partition = <&storage_partition>; + disk-name = "NAND"; + cache-size = <4096>; + }; +}; diff --git a/samples/subsys/usb/mass/prj.conf b/samples/subsys/usb/mass/prj.conf index dd9d784070de5..5ff15b40f6c20 100644 --- a/samples/subsys/usb/mass/prj.conf +++ b/samples/subsys/usb/mass/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_STDOUT_CONSOLE=y CONFIG_SERIAL=y diff --git a/samples/subsys/usb/midi/prj.conf b/samples/subsys/usb/midi/prj.conf index fdc77affb2302..02e2d52c7edd3 100644 --- a/samples/subsys/usb/midi/prj.conf +++ b/samples/subsys/usb/midi/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_MIDI2_CLASS=y CONFIG_SAMPLE_USBD_PRODUCT="USBD MIDI Sample" diff --git a/samples/subsys/usb/shell/README.rst b/samples/subsys/usb/shell/README.rst index 5e5437b56dc35..5fb42f2c3095e 100644 --- a/samples/subsys/usb/shell/README.rst +++ b/samples/subsys/usb/shell/README.rst @@ -50,37 +50,37 @@ Sample shell interaction .. code-block:: console - uart:~$ usbd defaults - dev: USB descriptors initialized - uart:~$ usbd config add 1 - uart:~$ usbd class add foobaz 1 - dev: added USB class foobaz to configuration 1 - uart:~$ usbd init + *** Booting Zephyr OS build v4.2.0-1588-g83f1bd7341de *** + uart:~$ usbd defcfg + dev: added default string descriptors + dev: register FS loopback_0 + dev: register HS loopback_0 dev: USB initialized uart:~$ usbh init host: USB host initialized uart:~$ usbh enable host: USB host enabled - [611:00:28.620,000] usbd_core: VBUS detected event uart:~$ usbh bus resume host: USB bus resumed uart:~$ usbd enable - host: USB device connected dev: USB enabled - uart:~$ usbh device descriptor device 0 - host: transfer finished 0x20006250, err 0 - 00000000: 80 06 00 01 00 00 12 00 |........ | - bLength 18 - bDescriptorType 1 - bcdUSB 200 - bDeviceClass 239 - bDeviceSubClass 2 - bDeviceProtocol 1 - bMaxPacketSize0 64 - idVendor 2fe3 - idProduct ffff - bcdDevice 301 - iManufacturer 1 - iProduct 2 - iSerial 3 - bNumConfigurations 1 + [160:04:13.870,000] usb_loopback: Enable loopback_0 + uart:~$ usbh device list + 1 + uart:~$ usbh device descriptor device 1 + host: USB device with address 1 + bLength 18 + bDescriptorType 1 + bcdUSB 200 + bDeviceClass 239 + bDeviceSubClass 2 + bDeviceProtocol 1 + bMaxPacketSize0 64 + idVendor 2fe3 + idProduct ffff + bcdDevice 402 + iManufacturer 1 + iProduct 2 + iSerial 3 + bNumConfigurations 1 + uart:~$ diff --git a/samples/subsys/usb/shell/prj.conf b/samples/subsys/usb/shell/prj.conf index 03d6eb8f1bbec..905c6bff9fe95 100644 --- a/samples/subsys/usb/shell/prj.conf +++ b/samples/subsys/usb/shell/prj.conf @@ -1,5 +1,6 @@ CONFIG_SHELL=y CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_SHELL=y CONFIG_USBD_LOOPBACK_CLASS=y CONFIG_UDC_BUF_POOL_SIZE=4096 diff --git a/samples/subsys/usb/testusb/prj.conf b/samples/subsys/usb/testusb/prj.conf index fcbf19c62e8d8..252faabe900db 100644 --- a/samples/subsys/usb/testusb/prj.conf +++ b/samples/subsys/usb/testusb/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_LOOPBACK_CLASS=y CONFIG_UDC_BUF_POOL_SIZE=4096 diff --git a/samples/subsys/usb/uac2_explicit_feedback/README.rst b/samples/subsys/usb/uac2_explicit_feedback/README.rst index d0ea63c5acf82..c0fa1898e4b65 100644 --- a/samples/subsys/usb/uac2_explicit_feedback/README.rst +++ b/samples/subsys/usb/uac2_explicit_feedback/README.rst @@ -39,8 +39,8 @@ nominal number of samples every frame. Theoretically it should be possible to obtain the timing information based on I2S and USB interrupts, but currently neither subsystem provides the necessary timestamp information. -Explcit Feedback on nRF5340 -*************************** +Explicit Feedback on nRF5340 +**************************** The nRF5340 is capable of counting both edges of I2S LRCLK relative to USB SOF with the use of DPPI, TIMER and GPIOTE input. Alternatively, if the GPIOTE input diff --git a/samples/subsys/usb/uac2_explicit_feedback/prj.conf b/samples/subsys/usb/uac2_explicit_feedback/prj.conf index 3979a5190e6c1..a0426650c030c 100644 --- a/samples/subsys/usb/uac2_explicit_feedback/prj.conf +++ b/samples/subsys/usb/uac2_explicit_feedback/prj.conf @@ -2,6 +2,7 @@ CONFIG_I2S=y #USB related configs CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_AUDIO2_CLASS=y CONFIG_SAMPLE_USBD_PID=0x000E CONFIG_SAMPLE_USBD_PRODUCT="UAC2 explicit feedback sample" diff --git a/samples/subsys/usb/uac2_implicit_feedback/prj.conf b/samples/subsys/usb/uac2_implicit_feedback/prj.conf index 61d654a3b3ad2..110ae08914007 100644 --- a/samples/subsys/usb/uac2_implicit_feedback/prj.conf +++ b/samples/subsys/usb/uac2_implicit_feedback/prj.conf @@ -2,6 +2,7 @@ CONFIG_I2S=y #USB related configs CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_USBD_AUDIO2_CLASS=y CONFIG_SAMPLE_USBD_PID=0x000F CONFIG_SAMPLE_USBD_PRODUCT="UAC2 implicit feedback sample" diff --git a/samples/subsys/usb/uvc/prj.conf b/samples/subsys/usb/uvc/prj.conf index e6da900d7d1c9..96fcda5182b77 100644 --- a/samples/subsys/usb/uvc/prj.conf +++ b/samples/subsys/usb/uvc/prj.conf @@ -8,6 +8,7 @@ CONFIG_USBD_LOG_LEVEL_WRN=y CONFIG_USBD_VIDEO_CLASS=y CONFIG_USBD_VIDEO_LOG_LEVEL_WRN=y CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_VIDEO=y CONFIG_VIDEO_BUFFER_POOL_NUM_MAX=2 CONFIG_VIDEO_BUFFER_POOL_SZ_MAX=24576 diff --git a/samples/subsys/usb/webusb/prj.conf b/samples/subsys/usb/webusb/prj.conf index 1c730a0ec56a3..d2b65dc7fae7d 100644 --- a/samples/subsys/usb/webusb/prj.conf +++ b/samples/subsys/usb/webusb/prj.conf @@ -1,4 +1,5 @@ CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_CDC_ACM_SERIAL_INITIALIZE_AT_BOOT=n CONFIG_LOG=y CONFIG_USBD_LOG_LEVEL_WRN=y diff --git a/samples/subsys/zbus/remote_mock/README.rst b/samples/subsys/zbus/remote_mock/README.rst index f599783e0fa32..b24408d62831f 100644 --- a/samples/subsys/zbus/remote_mock/README.rst +++ b/samples/subsys/zbus/remote_mock/README.rst @@ -16,7 +16,7 @@ Building and Running ******************** This project outputs to the console. It can be built and executed -on :ref:`native_sim ` as follows: +on :zephyr:board:`native_sim ` as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/zbus/remote_mock @@ -64,7 +64,7 @@ The :file:`remote_mock.py` script can be executed using the following command: Note the run command above prints the value of pts port because it is running in -:ref:`native_sim `. +:zephyr:board:`native_sim `. Look at the line indicating ``uart_1 connected to pseudotty: /dev/pts/2``. It can be different in your case. If you are using a board, read the documentation to get the correct port destination (in Linux is something like ``/dev/tty...`` or in Windows ``COM...``). diff --git a/samples/subsys/zbus/uart_bridge/README.rst b/samples/subsys/zbus/uart_bridge/README.rst index a0101fa45b24c..c33f597fd19af 100644 --- a/samples/subsys/zbus/uart_bridge/README.rst +++ b/samples/subsys/zbus/uart_bridge/README.rst @@ -69,7 +69,7 @@ The :file:`decoder.py` script can be executed using the following command: Note the run command above prints the value of pts port because it is running in -:ref:`native_sim `. +:zephyr:board:`native_sim `. Look at the line indicating ``uart_1 connected to pseudotty: /dev/pts/2``. It can be different in your case. If you are using a board, read the documentation to get the correct port destination (in Linux is something like ``/dev/tty...`` or in Windows ``COM...``). diff --git a/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay b/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay index 7d1e21d17393d..607796d06e9fb 100644 --- a/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay +++ b/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay @@ -4,12 +4,11 @@ * SPDX-License-Identifier: Apache-2.0 */ - - /* This partition table could be used along with TFM configuration: - * - TEST_S=ON (REGRESSION) - * - TFM_PSA_API=ON (IPC) - * - */ +/* This partition table could be used along with TFM configuration: + * - TEST_S=ON (REGRESSION) + * - TFM_PSA_API=ON (IPC) + * + */ / { chosen { @@ -17,7 +16,6 @@ }; }; - /delete-node/ &slot1_partition; /delete-node/ &slot1_ns_partition; diff --git a/scripts/build/gen_kobject_list.py b/scripts/build/gen_kobject_list.py index 1d60c0df0fc9d..300c41319e668 100755 --- a/scripts/build/gen_kobject_list.py +++ b/scripts/build/gen_kobject_list.py @@ -114,6 +114,7 @@ ("ztest_test_rule", ("CONFIG_ZTEST", True, False)), ("rtio", ("CONFIG_RTIO", False, False)), ("rtio_iodev", ("CONFIG_RTIO", False, False)), + ("rtio_pool", ("CONFIG_RTIO", False, False)), ("sensor_decoder_api", ("CONFIG_SENSOR_ASYNC_API", True, False)) ]) diff --git a/scripts/build/gen_relocate_app.py b/scripts/build/gen_relocate_app.py index 2f071ea3efc2f..49b91edec4c96 100755 --- a/scripts/build/gen_relocate_app.py +++ b/scripts/build/gen_relocate_app.py @@ -180,6 +180,7 @@ class OutputSection(NamedTuple): #include #include #include +#include """ EXTERN_LINKER_VAR_DECLARATION = """ @@ -204,13 +205,13 @@ class OutputSection(NamedTuple): """ MEMCPY_TEMPLATE = """ - z_early_memcpy(&__{mem}_{kind}_reloc_start, &__{mem}_{kind}_rom_start, + arch_early_memcpy(&__{mem}_{kind}_reloc_start, &__{mem}_{kind}_rom_start, (size_t) &__{mem}_{kind}_reloc_size); """ MEMSET_TEMPLATE = """ - z_early_memset(&__{mem}_bss_reloc_start, 0, + arch_early_memset(&__{mem}_bss_reloc_start, 0, (size_t) &__{mem}_bss_reloc_size); """ diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 4fcae2e6b1faf..a600004aae7a9 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -345,15 +345,24 @@ def check_board_file(self, file, vendor_prefixes): def run(self): path = resolve_path_hint(self.path_hint) + module_ymls = [path / "zephyr" / "module.yml", path / "zephyr" / "module.yaml"] vendor_prefixes = {"others"} # add vendor prefixes from the main zephyr repo vendor_prefixes |= get_vendor_prefixes(ZEPHYR_BASE / "dts" / "bindings" / "vendor-prefixes.txt", self.error) - # add vendor prefixes from the current repo - dts_roots = get_module_setting_root('dts', path / "zephyr" / "module.yml") - for dts_root in dts_roots: - vendor_prefix_file = dts_root / "dts" / "bindings" / "vendor-prefixes.txt" + dts_root = None + for module_yml in module_ymls: + if module_yml.is_file(): + with module_yml.open('r', encoding='utf-8') as f: + meta = yaml.load(f.read(), Loader=SafeLoader) + section = meta.get('build', dict()) + build_settings = section.get('settings', None) + if build_settings: + dts_root = build_settings.get('dts_root', None) + + if dts_root: + vendor_prefix_file = Path(dts_root) / "dts" / "bindings" / "vendor-prefixes.txt" if vendor_prefix_file.exists(): vendor_prefixes |= get_vendor_prefixes(vendor_prefix_file, self.error) @@ -506,7 +515,7 @@ def run(self): self.check_no_undef_outside_kconfig(kconf) self.check_disallowed_defconfigs(kconf) - def get_modules(self, modules_file, sysbuild_modules_file, settings_file): + def get_modules(self, _module_dirs_file, modules_file, sysbuild_modules_file, settings_file): """ Get a list of modules and put them in a file that is parsed by Kconfig @@ -691,13 +700,15 @@ def parse_kconfig(self): os.environ["KCONFIG_BINARY_DIR"] = kconfiglib_dir os.environ['DEVICETREE_CONF'] = "dummy" os.environ['TOOLCHAIN_HAS_NEWLIB'] = "y" + os.environ['KCONFIG_ENV_FILE'] = os.path.join(kconfiglib_dir, "kconfig_module_dirs.env") # Older name for DEVICETREE_CONF, for compatibility with older Zephyr # versions that don't have the renaming os.environ["GENERATED_DTS_BOARD_CONF"] = "dummy" # For multi repo support - self.get_modules(os.path.join(kconfiglib_dir, "Kconfig.modules"), + self.get_modules(os.environ['KCONFIG_ENV_FILE'], + os.path.join(kconfiglib_dir, "Kconfig.modules"), os.path.join(kconfiglib_dir, "Kconfig.sysbuild.modules"), os.path.join(kconfiglib_dir, "settings_file.txt")) # For Kconfig.dts support @@ -1200,6 +1211,8 @@ def check_no_undef_outside_kconfig(self, kconf): "BOOT_DIRECT_XIP", # Used in sysbuild for MCUboot configuration "BOOT_DIRECT_XIP_REVERT", # Used in sysbuild for MCUboot configuration "BOOT_ENCRYPTION_KEY_FILE", # Used in sysbuild + "BOOT_ENCRYPT_ALG_AES_128", # Used in sysbuild + "BOOT_ENCRYPT_ALG_AES_256", # Used in sysbuild "BOOT_ENCRYPT_IMAGE", # Used in sysbuild "BOOT_FIRMWARE_LOADER", # Used in sysbuild for MCUboot configuration "BOOT_FIRMWARE_LOADER_BOOT_MODE", # Used in sysbuild for MCUboot configuration @@ -1250,6 +1263,9 @@ def check_no_undef_outside_kconfig(self, kconf): "FOO_LOG_LEVEL", "FOO_SETTING_1", "FOO_SETTING_2", + "GEN_UICR_GENERATE_PERIPHCONF", # Used in specialized build tool, not part of main Kconfig + "GEN_UICR_SECONDARY", # Used in specialized build tool, not part of main Kconfig + "GEN_UICR_SECONDARY_GENERATE_PERIPHCONF", # Used in specialized build tool, not part of main Kconfig "HEAP_MEM_POOL_ADD_SIZE_", # Used as an option matching prefix "HUGETLBFS", # Linux, in boards/xtensa/intel_adsp_cavs25/doc "IAR_BUFFERED_WRITE", @@ -1353,13 +1369,17 @@ class KconfigBasicNoModulesCheck(KconfigBasicCheck): """ name = "KconfigBasicNoModules" path_hint = "" + EMPTY_FILE_CONTENTS = "# Empty\n" + + def get_modules(self, module_dirs_file, modules_file, sysbuild_modules_file, settings_file): + with open(module_dirs_file, 'w') as fp_module_file: + fp_module_file.write(self.EMPTY_FILE_CONTENTS) - def get_modules(self, modules_file, sysbuild_modules_file, settings_file): with open(modules_file, 'w') as fp_module_file: - fp_module_file.write("# Empty\n") + fp_module_file.write(self.EMPTY_FILE_CONTENTS) with open(sysbuild_modules_file, 'w') as fp_module_file: - fp_module_file.write("# Empty\n") + fp_module_file.write(self.EMPTY_FILE_CONTENTS) class KconfigHWMv2Check(KconfigBasicCheck): @@ -1394,10 +1414,6 @@ class SysbuildKconfigCheck(KconfigCheck): "OTHER_APP_IMAGE_NAME", # Used in sysbuild documentation as example "OTHER_APP_IMAGE_PATH", # Used in sysbuild documentation as example "SECOND_SAMPLE", # Used in sysbuild documentation - "SUIT_ENVELOPE", # Used by nRF runners to program provisioning data - "SUIT_MPI_APP_AREA_PATH", # Used by nRF runners to program provisioning data - "SUIT_MPI_GENERATE", # Used by nRF runners to program provisioning data - "SUIT_MPI_RAD_AREA_PATH", # Used by nRF runners to program provisioning data # zephyr-keep-sorted-stop } @@ -2288,6 +2304,7 @@ def _main(args): xml.write(args.output, pretty=True) failed_cases = [] + warning_cases = [] name2doc = {testcase.name: testcase.doc for testcase in inheritors(ComplianceTest)} @@ -2296,19 +2313,31 @@ def _main(args): if case.is_skipped: logging.warning(f"Skipped {case.name}") else: - failed_cases.append(case) + if any(res.type in ('error', 'failure') for res in case.result): + failed_cases.append(case) + else: + warning_cases.append(case) else: # Some checks can produce no .result logging.info(f"No JUnit result for {case.name}") n_fails = len(failed_cases) + n_warnings = len(warning_cases) + + if n_fails or n_warnings: + if n_fails: + print(f"{n_fails} check(s) failed") + if n_warnings: + print(f"{n_warnings} check(s) with warnings only") - if n_fails: - print(f"{n_fails} checks failed") - for case in failed_cases: + for case in failed_cases + warning_cases: for res in case.result: errmsg = res.text.strip() - logging.error(f"Test {case.name} failed: \n{errmsg}") + if res.type in ('error', 'failure'): + logging.error(f"Test {case.name} failed: \n{errmsg}") + else: + logging.warning(f"Test {case.name} warning: \n{errmsg}") + if args.no_case_output: continue with open(f"{case.name}.txt", "w") as f: diff --git a/scripts/ci/check_maintainer_changes.py b/scripts/ci/check_maintainer_changes.py index 748eb4430f73b..fdb69989be9f6 100644 --- a/scripts/ci/check_maintainer_changes.py +++ b/scripts/ci/check_maintainer_changes.py @@ -30,8 +30,8 @@ def check_github_access(usernames, repo_fullname, token): missing_access = set() for username in usernames: try: - collab = repo.get_collaborator_permission(username) - # Permissions: admin, maintain, write, triage, read + collab = repo.get_collaborator_role_name(username) + # Roles: admin, maintain, write, triage, read if collab not in ("admin", "maintain", "write", "triage"): missing_access.add(username) except Exception: diff --git a/scripts/ci/do_not_merge.py b/scripts/ci/do_not_merge.py index d35aed8cbc819..89bd7d4efc9fd 100755 --- a/scripts/ci/do_not_merge.py +++ b/scripts/ci/do_not_merge.py @@ -29,6 +29,8 @@ def parse_args(argv): ) parser.add_argument("-p", "--pull-request", required=True, type=int, help="The PR number") + parser.add_argument("-o", "--org", default="zephyrproject-rtos", help="Github organization") + parser.add_argument("-r", "--repo", default="zephyr", help="Github repository") return parser.parse_args(argv) @@ -46,7 +48,7 @@ def workflow_delay(repo, pr): completed = set() for run in runs: print(f"{run.name}: {run.status} {run.conclusion} {run.html_url}") - if run.status == "completed" and run.conclusion == "success": + if run.status == "completed": completed.add(run.name) if WAIT_FOR_WORKFLOWS.issubset(completed): @@ -63,9 +65,9 @@ def main(argv): token = os.environ.get('GITHUB_TOKEN', None) gh = github.Github(token) - print_rate_limit(gh, "zephyrproject-rtos") + print_rate_limit(gh, args.org) - repo = gh.get_repo("zephyrproject-rtos/zephyr") + repo = gh.get_repo(f"{args.org}/{args.repo}") pr = repo.get_pull(args.pull_request) workflow_delay(repo, pr) diff --git a/scripts/dts/gen_defines.py b/scripts/dts/gen_defines.py index 93c4c3a635b24..e3913dd585b79 100755 --- a/scripts/dts/gen_defines.py +++ b/scripts/dts/gen_defines.py @@ -569,7 +569,7 @@ def write_gpio_hogs(node: edtlib.Node) -> None: macro = f"{node.z_path_id}_GPIO_HOGS" macro2val = {} for i, entry in enumerate(node.gpio_hogs): - macro2val.update(controller_and_data_macros(entry, i, macro)) + macro2val.update(controller_and_data_macros(entry, i, macro, "")) if macro2val: out_comment("GPIO hog properties:") @@ -835,12 +835,12 @@ def phandle_macros(prop: edtlib.Property, macro: str) -> dict: ret[f"{macro}_IDX_{i}_EXISTS"] = 0 continue - ret.update(controller_and_data_macros(entry, i, macro)) + ret.update(controller_and_data_macros(entry, i, macro, prop.name)) return ret -def controller_and_data_macros(entry: edtlib.ControllerAndData, i: int, macro: str): +def controller_and_data_macros(entry: edtlib.ControllerAndData, i: int, macro: str, pname: str): # Helper procedure used by phandle_macros(). # # Its purpose is to write the "controller" (i.e. label property of @@ -849,6 +849,8 @@ def controller_and_data_macros(entry: edtlib.ControllerAndData, i: int, macro: s ret = {} data = entry.data + node = entry.node + pname = edtlib.str_as_token(str2ident(pname)) # DT_N__P__IDX__EXISTS ret[f"{macro}_IDX_{i}_EXISTS"] = 1 @@ -858,13 +860,40 @@ def controller_and_data_macros(entry: edtlib.ControllerAndData, i: int, macro: s for cell, val in data.items(): ret[f"{macro}_IDX_{i}_VAL_{str2ident(cell)}"] = val ret[f"{macro}_IDX_{i}_VAL_{str2ident(cell)}_EXISTS"] = 1 + # DT_N__P__IDX__EXISTS + ret[f"{macro}_IDX_{i}_EXISTS"] = 1 + # DT_N__P__IDX__FOREACH_CELL + ret[f"{macro}_IDX_{i}_FOREACH_CELL(fn)"] = ( + ' \\\n\t'.join(f'fn(DT_{node.z_path_id}, {pname}, {i}, {cell})' + for cell in data)) + # DT_N__P__IDX__FOREACH_CELL_SEP + ret[f"{macro}_IDX_{i}_FOREACH_CELL_SEP(fn, sep)"] = ( + ' DT_DEBRACKET_INTERNAL sep \\\n\t'.join( + f'fn(DT_{node.z_path_id}, {pname}, {i}, {cell})' + for cell in data)) + # DT_N__P__IDX__NUM_CELLS + ret[f"{macro}_IDX_{i}_NUM_CELLS"] = len(data) if not entry.name: return ret name = str2ident(entry.name) - # DT_N__P__IDX__EXISTS - ret[f"{macro}_IDX_{i}_EXISTS"] = 1 + + # DT_N__P__IDX__NAME + ret[f"{macro}_IDX_{i}_NAME"] = edtlib.str_as_token(name) + # DT_N__P__NAME__IDX + ret[f"{macro}_NAME_{name}_IDX"] = i + # DT_N__P__NAME__FOREACH_CELL + ret[f"{macro}_NAME_{name}_FOREACH_CELL(fn)"] = ( + ' \\\n\t'.join(f'fn(DT_{node.z_path_id}, {pname}, {name}, {cell})' + for cell in data)) + # DT_N__P__NAME__FOREACH_CELL_SEP + ret[f"{macro}_NAME_{name}_FOREACH_CELL_SEP(fn, sep)"] = ( + ' DT_DEBRACKET_INTERNAL sep \\\n\t'.join( + f'fn(DT_{node.z_path_id}, {pname}, {name}, {cell})' + for cell in data)) + # DT_N__P__NAME__NUM_CELLS + ret[f"{macro}_NAME_{name}_NUM_CELLS"] = len(data) # DT_N__P__IDX__NAME ret[f"{macro}_IDX_{i}_NAME"] = quote_str(entry.name) # DT_N__P__NAME__PH diff --git a/scripts/dts/python-devicetree/src/devicetree/edtlib.py b/scripts/dts/python-devicetree/src/devicetree/edtlib.py index 2192911734ab4..916cdc230d236 100644 --- a/scripts/dts/python-devicetree/src/devicetree/edtlib.py +++ b/scripts/dts/python-devicetree/src/devicetree/edtlib.py @@ -855,7 +855,7 @@ class ControllerAndData: *-names property basename: - Basename for the controller when supporting named cells + Basename for the controller when supporting named cells. AKA, the specifier space. """ node: 'Node' controller: 'Node' diff --git a/scripts/footprint/plot.py b/scripts/footprint/plot.py new file mode 100755 index 0000000000000..9a278bbc1140d --- /dev/null +++ b/scripts/footprint/plot.py @@ -0,0 +1,114 @@ +#!/usr/bin/env python3 +# Copyright (c) 2025 Basalte bv +# +# SPDX-License-Identifier: Apache-2.0 + +""" +A script to plot data in a sunburst chart generated by size_report. +When you call the ram_report or rom_report targets you end up +with a json file in the build directory that can be used as input +for this script. + +Example: + ./scripts/footprint/plot.py build/ram.json + +Requires plotly to be installed, for example with pip: + pip install plotly +""" + +import argparse +import json +import sys + + +def parse_args(): + parser = argparse.ArgumentParser( + description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter, + allow_abbrev=False, + ) + + parser.add_argument('input', help='Input json file') + parser.add_argument('--html', help='Output html file') + parser.add_argument( + '--depth', + help='Maximum render depth, pass -1 to render all levels. Defaults to 4', + type=int, + default=4, + ) + + return parser.parse_args() + + +def main(): + args = parse_args() + + try: + import plotly.graph_objects as go + except ImportError: + sys.exit("Missing dependency: You need to install plotly.") + + with open(args.input) as f: + data = json.load(f) + + totalsize = data.get('total_size') + ids = [] + labels = [] + parents = [] + values = [] + hovertext = [] + + def iter_node(node: dict, parent=''): + identifier = node.get('identifier') + if identifier is None: + return + + if identifier in ids: + # Identifiers aren't unique, add a suffix to make them unique + idx = 0 + while f'{identifier}_{idx}' in ids: + idx += 1 + identifier = f'{identifier}_{idx}' + + ids.append(identifier) + labels.append(node.get('name', '')) + parents.append(parent) + values.append(node.get('size', 0)) + + details = [f'percentage: {node.get("size") / totalsize:.2%}'] + if 'address' in node: + details.append(f'address: 0x{node.get("address"):08x}') + if 'section' in node: + details.append(f'section: {node.get("section")}') + + hovertext.append("
".join(details)) + + for child in node.get('children', ()): + iter_node(child, identifier) + + iter_node(data.get('symbols', {})) + + fig = go.Figure( + go.Sunburst( + ids=ids, + labels=labels, + parents=parents, + values=values, + hovertext=hovertext, + branchvalues='total', + maxdepth=args.depth, + ), + skip_invalid=True, + ) + fig.update_layout(margin={'t': 0, 'l': 0, 'r': 0, 'b': 0}) + + if args.html: + fig.write_html(args.html, auto_open=False) + return + + print("Opening the default browser to render the generated plot.") + fig.show(renderer="browser") + + +if __name__ == "__main__": + main() diff --git a/scripts/kconfig/hardenconfig.py b/scripts/kconfig/hardenconfig.py index 07912e3e53f0b..9ef231d43bbcf 100755 --- a/scripts/kconfig/hardenconfig.py +++ b/scripts/kconfig/hardenconfig.py @@ -7,13 +7,15 @@ import os from kconfiglib import standard_kconfig +from tabulate import tabulate def hardenconfig(kconf): kconf.load_config() - hardened_kconf_filename = os.path.join(os.environ['ZEPHYR_BASE'], - 'scripts', 'kconfig', 'hardened.csv') + hardened_kconf_filename = os.path.join( + os.environ['ZEPHYR_BASE'], 'scripts', 'kconfig', 'hardened.csv' + ) options = compare_with_hardened_conf(kconf, hardened_kconf_filename) @@ -21,7 +23,6 @@ def hardenconfig(kconf): class Option: - def __init__(self, name, recommended, current=None, symbol=None): self.name = name self.recommended = recommended @@ -51,29 +52,40 @@ def compare_with_hardened_conf(kconf, hardened_kconf_filename): except KeyError: symbol = None current = None - options.append(Option(name=name, current=current, - recommended=recommended, symbol=symbol)) + options.append( + Option(name=name, current=current, recommended=recommended, symbol=symbol) + ) for node in kconf.node_iter(): for select in node.selects: - if kconf.syms["EXPERIMENTAL"] in select or kconf.syms["DEPRECATED"] in select or kconf.syms["NOT_SECURE"] in select: - options.append(Option(name=node.item.name, current=node.item.str_value, recommended='n', symbol=node.item)) + if ( + kconf.syms["EXPERIMENTAL"] in select + or kconf.syms["DEPRECATED"] in select + or kconf.syms["NOT_SECURE"] in select + ): + options.append( + Option( + name=node.item.name, + current=node.item.str_value, + recommended='n', + symbol=node.item, + ) + ) return options def display_results(options): - # header - print('{:^50}|{:^13}|{:^20}'.format('name', 'current', 'recommended'), end='') - print('||{:^28}\n'.format('check result'), end='') - print('=' * 116) + table_data = [] + headers = ['Name', 'Current', 'Recommended', 'Check result'] # results, only printing options that have failed for now. It simplify the readability. # TODO: add command line option to show all results for opt in options: if opt.result == 'FAIL' and opt.symbol.visibility != 0: - print('CONFIG_{:<43}|{:^13}|{:^20}'.format( - opt.name, opt.current, opt.recommended), end='') - print('||{:^28}\n'.format(opt.result), end='') + table_data.append([f'CONFIG_{opt.name}', opt.current, opt.recommended, opt.result]) + + if table_data: + print(tabulate(table_data, headers=headers, tablefmt='grid')) print() diff --git a/scripts/logging/dictionary/live_log_parser.py b/scripts/logging/dictionary/live_log_parser.py index fc881cdb8d3c3..25f9d4bead543 100755 --- a/scripts/logging/dictionary/live_log_parser.py +++ b/scripts/logging/dictionary/live_log_parser.py @@ -18,10 +18,18 @@ import os import select import sys +import time import parserlib import serial +try: + # Pylink is an optional dependency for RTT reading, which requires it's own installation. + # Don't fail, unless the user tries to use RTT reading. + import pylink +except ImportError: + pylink = None + LOGGER_FORMAT = "%(message)s" logger = logging.getLogger("parser") @@ -78,12 +86,80 @@ def read_non_blocking(self): return self.file.read(1024) +class JLinkRTTReader: + """Class to read data from JLink's RTT""" + + @staticmethod + def _create_jlink_connection(lib_path): + if pylink is None: + raise ImportError( + "pylink module is required for RTT reading. " + "Please install it using 'pip install pylink-square'." + ) + + if lib_path is not None: + lib = pylink.Library(lib_path, True) + jlink = pylink.JLink(lib) + else: + jlink = pylink.JLink() + + return jlink + + @contextlib.contextmanager + def open(self): + try: + self.jlink.open() + self.jlink.set_tif(pylink.enums.JLinkInterfaces.SWD) + if self.speed != 0: + self.jlink.connect(self.target_device, self.speed) + else: + self.jlink.connect(self.target_device) + + self.jlink.rtt_start(self.block_address) + + # Wait for the JLINK RTT buffers to be initialized. + up_down_initialized = False + while not up_down_initialized: + try: + _ = self.jlink.rtt_get_num_up_buffers() + _ = self.jlink.rtt_get_num_down_buffers() + up_down_initialized = True + except pylink.errors.JLinkRTTException: + time.sleep(0.1) + + yield + + finally: + self.close() + + def __init__(self, target_device, block_address, channel, speed, lib_path): + self.target_device = target_device + self.block_address = block_address + self.speed = speed + self.channel = channel + + self.jlink = self._create_jlink_connection(lib_path) + + def close(self): + # JLink closes the connection through the __del__ method. + del self.jlink + + def read_non_blocking(self): + return bytes(self.jlink.rtt_read(self.channel, 1024)) + + def parse_args(): """Parse command line arguments""" parser = argparse.ArgumentParser(allow_abbrev=False) parser.add_argument("dbfile", help="Dictionary Logging Database file") parser.add_argument("--debug", action="store_true", help="Print extra debugging information") + parser.add_argument( + "--polling-interval", + type=float, + default=0.1, + help="Interval for polling input source, if it does not support 'select'", + ) # Create subparsers for different input modes subparsers = parser.add_subparsers(dest="mode", required=True, help="Input source mode") @@ -99,6 +175,18 @@ def parse_args(): "filepath", nargs="?", default=None, help="Input file path, leave empty for stdin" ) + # RTT subparser + jlink_rtt_parser = subparsers.add_parser("jlink-rtt", help="Read from RTT") + jlink_rtt_parser.add_argument( + "target_device", help="Device Name (see https://www.segger.com/supported-devices/jlink/)" + ) + jlink_rtt_parser.add_argument( + "--block-address", help="RTT block address in hex", type=lambda x: int(x, 16) + ) + jlink_rtt_parser.add_argument("--channel", type=int, help="RTT channel number", default=0) + jlink_rtt_parser.add_argument("--speed", type=int, help="Reading speed", default='0') + jlink_rtt_parser.add_argument("--lib-path", help="Path to libjlinkarm.so library") + return parser.parse_args() @@ -125,16 +213,22 @@ def main(): reader = SerialReader(args.port, args.baudrate) elif args.mode == "file": reader = FileReader(args.filepath) + elif args.mode == "jlink-rtt": + reader = JLinkRTTReader( + args.target_device, args.block_address, args.channel, args.speed, args.lib_path + ) else: raise ValueError("Invalid mode selected. Use 'serial' or 'file'.") with reader.open(): while True: - ready, _, _ = select.select([reader], [], []) - if ready: - data += reader.read_non_blocking() - parsed_data_offset = parserlib.parser(data, log_parser, logger) - data = data[parsed_data_offset:] + if hasattr(reader, 'fileno'): + _, _, _ = select.select([reader], [], []) + else: + time.sleep(args.polling_interval) + data += reader.read_non_blocking() + parsed_data_offset = parserlib.parser(data, log_parser, logger) + data = data[parsed_data_offset:] if __name__ == "__main__": diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py index 37751f69d86dc..d0d200d6225ff 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py @@ -38,8 +38,23 @@ def __init__(self, device_config: DeviceConfig) -> None: self.device_log_path: Path = device_config.build_dir / 'device.log' self._log_files.append(self.device_log_path) + def _generate_flash_command(self) -> None: + command = [self.device_config.flash_command[0]] + command.extend(['--build-dir', str(self.device_config.build_dir)]) + + if self.device_config.id: + command.extend(['--board-id', self.device_config.id]) + + command.extend(self.device_config.flash_command[1:]) + + self.command = command + def generate_command(self) -> None: """Return command to flash.""" + if self.device_config.flash_command: + self._generate_flash_command() + return + command = [ self.west, 'flash', @@ -91,7 +106,7 @@ def _prepare_runner_args(self) -> tuple[list[str], list[str]]: elif runner == 'jlink': base_args.append('--dev-id') base_args.append(board_id) - elif runner == 'stm32cubeprogrammer': + elif runner == 'stm32cubeprogrammer' and self.device_config.product != "BOOT-SERIAL": base_args.append(f'--tool-opt=sn={board_id}') elif runner == 'linkserver': base_args.append(f'--probe={board_id}') diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py index d53d74b1be1d9..621b0defd71a1 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py @@ -4,7 +4,7 @@ import logging from pathlib import Path -from typing import Generator, Type +from typing import Generator, Type, Callable import pytest import time @@ -15,6 +15,7 @@ from twister_harness.helpers.shell import Shell from twister_harness.helpers.mcumgr import MCUmgr, MCUmgrBle from twister_harness.helpers.utils import find_in_config +from twister_harness.helpers.config_reader import ConfigReader logger = logging.getLogger(__name__) @@ -117,3 +118,27 @@ def mcumgr_ble(device_object: DeviceAdapter) -> Generator[MCUmgrBle, None, None] ) or 'Zephyr' yield MCUmgrBle.create_for_ble(hci_index, peer_name) + + +@pytest.fixture +def config_reader() -> Callable[[str | Path], ConfigReader]: + """ + Pytest fixture that provides a ConfigReader instance for reading configuration files. + + This fixture allows tests to easily create a ConfigReader object by passing + the path to a configuration file. The ConfigReader reads the file and + provides a method to access the configuration data. + + Returns: + Callable[[str, Path], ConfigReader]: A function that takes a file path + (as a string or Path object) and returns an instance of ConfigReader. + + Example: + def test_config_value(config_reader): + config = config_reader("build_dir/zephyr/.config") + assert config.read("some_key") == "expected_value" + """ + def inner(file): + return ConfigReader(file) + + return inner diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/config_reader.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/config_reader.py new file mode 100644 index 0000000000000..701a83982f0d1 --- /dev/null +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/config_reader.py @@ -0,0 +1,103 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +"""Implementation for a configuration file reader.""" + +import logging +import os +import re +from pathlib import Path +from typing import Any + +__tracebackhide__ = True + +logger = logging.getLogger(__name__) + + +class ConfigReader: + """Reads configuration from a config file.""" + + def __init__(self, config_file: Path | str) -> None: + """Initialize. + + :param config_file: path to a configuration file + """ + assert os.path.exists(config_file), f"Path does not exist: {config_file}" + assert os.path.isfile(config_file), f"It is not a file: {config_file}" + self.config_file = config_file + self.config: dict[str, str] = {} + self.parse() + + def parse(self) -> dict[str, str]: + """Parse a config file.""" + pattern = re.compile(r"^(?P.+)=(?P.+)$") + with open(self.config_file) as file: + for line in file: + if match := pattern.match(line): + key, value = match.group("key"), match.group("value") + self.config[key] = value.strip("\"'") + return self.config + + def read(self, config_key: str, default: Any = None, *, silent=False) -> str | None: + """Find key in config file. + + :param config_key: key to read + :param default: default value to return if key not found + :param silent: do not raise an exception when key not found + :raises ValueError: if key not found + """ + try: + value = self.config[config_key] + except KeyError: + if default is not None: + return default + logger.debug("Not found key: %s", config_key) + if silent: + return None + raise ValueError(f"Could not find key: {config_key}") from None + logger.debug("Found matching key: %s=%s", config_key, value) + return value + + def read_int(self, config_key: str, default: int | None = None) -> int: + """Find key in config file and return int. + + :param config_key: key to read + :param default: default value to return if key not found + """ + if default is not None and not isinstance(default, int): + raise TypeError(f"default value must be type of int, but was {type(default)}") + if default is not None: + default = hex(default) # type: ignore + if value := self.read(config_key, default): + try: + return int(value) + except ValueError: + return int(value, 16) + raise Exception("Non reachable code") # pragma: no cover + + def read_bool(self, config_key: str, default: bool | None = None) -> bool: + """Find key in config file and return bool. + + :param config_key: key to read + :param default: default value to return if key not found + """ + value = self.read(config_key, default) + if isinstance(value, str): + if value.lower() == "y": + return True + if value.lower() == "n": + return False + return bool(value) + + def read_hex(self, config_key: str, default: int | None = None) -> str: + """Find key in config file and return hex. + + :param config_key: key to read + :param default: default value to return if key not found + :return: hex value as string + """ + if default is not None and not isinstance(default, int): + raise TypeError(f"default value must be type of int, but was {type(default)}") + value = self.read_int(config_key, default) + return hex(value) diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/utils.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/utils.py index 076b5dd194038..914f95b079b0f 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/utils.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/utils.py @@ -27,11 +27,15 @@ def find_in_config(config_file: Path | str, config_key: str) -> str: def match_lines(output_lines: list[str], searched_lines: list[str]) -> None: """Check all lines exist in the output""" - for sl in searched_lines: - assert any(sl in line for line in output_lines) + __tracebackhide__ = True # pylint: disable=unused-variable + missing_lines = [sl for sl in searched_lines if not any(sl in line for line in output_lines)] + if missing_lines: + raise AssertionError(f"Missing lines: {missing_lines}") def match_no_lines(output_lines: list[str], searched_lines: list[str]) -> None: """Check lines not found in the output""" - for sl in searched_lines: - assert all(sl not in line for line in output_lines) + __tracebackhide__ = True # pylint: disable=unused-variable + found_lines = [sl for sl in searched_lines if any(sl in line for line in output_lines)] + if found_lines: + raise AssertionError(f"Found lines that should not be present: {found_lines}") diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py index ec212db98bde6..eecbf6bde9226 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py @@ -102,6 +102,10 @@ def pytest_addoption(parser: pytest.Parser): 'E.g. --west-flash-extra-args="--board-id=foobar,--erase" ' 'will translate to "west flash -- --board-id=foobar --erase".' ) + twister_harness_group.addoption( + '--flash-command', + help='Use a custom flash command for flashing.' + ) twister_harness_group.addoption( '--pre-script', metavar='PATH', diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/twister_harness_config.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/twister_harness_config.py index 65aa87d8635bd..807b72f10ff6c 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/twister_harness_config.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/twister_harness_config.py @@ -4,6 +4,7 @@ from __future__ import annotations +import csv import logging from dataclasses import dataclass, field from pathlib import Path @@ -30,6 +31,7 @@ class DeviceConfig: serial_pty: str = '' flash_before: bool = False west_flash_extra_args: list[str] = field(default_factory=list, repr=False) + flash_command: str = '' name: str = '' pre_script: Path | None = None post_script: Path | None = None @@ -59,7 +61,10 @@ def create(cls, config: pytest.Config) -> TwisterHarnessConfig: west_flash_extra_args: list[str] = [] if config.option.west_flash_extra_args: - west_flash_extra_args = [w.strip() for w in config.option.west_flash_extra_args.split(',')] + west_flash_extra_args = [w.strip() for w in next(csv.reader([config.option.west_flash_extra_args]))] + flash_command: list[str] = [] + if config.option.flash_command: + flash_command = [w.strip() for w in next(csv.reader([config.option.flash_command]))] runner_params: list[str] = [] if config.option.runner_params: runner_params = [w.strip() for w in config.option.runner_params] @@ -78,6 +83,7 @@ def create(cls, config: pytest.Config) -> TwisterHarnessConfig: serial_pty=config.option.device_serial_pty, flash_before=bool(config.option.flash_before), west_flash_extra_args=west_flash_extra_args, + flash_command=flash_command, pre_script=_cast_to_path(config.option.pre_script), post_script=_cast_to_path(config.option.post_script), post_flash_script=_cast_to_path(config.option.post_flash_script), diff --git a/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py b/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py index 589124f7c22c4..eac79478074b9 100644 --- a/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py +++ b/scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py @@ -25,6 +25,7 @@ def fixture_adapter(tmp_path) -> HardwareAdapter: platform='platform', id='p_id', base_timeout=5.0, + flash_command='', ) return HardwareAdapter(device_config) @@ -181,6 +182,14 @@ def test_if_get_command_returns_proper_string_with_west_flash_extra_args( ] +def test_if_get_command_flash_command(device: HardwareAdapter) -> None: + device.device_config.build_dir = Path('build') + device.device_config.flash_command = ['flash_command', '--with-arg'] + device.generate_command() + assert isinstance(device.command, list) + assert device.command == ['flash_command', '--build-dir', 'build', '--board-id', 'p_id', '--with-arg'] + + def test_if_hardware_adapter_raises_exception_empty_command(device: HardwareAdapter) -> None: device.command = [] exception_msg = 'Flash command is empty, please verify if it was generated properly.' diff --git a/scripts/pylib/pytest-twister-harness/tests/helpers/test_config_reader.py b/scripts/pylib/pytest-twister-harness/tests/helpers/test_config_reader.py new file mode 100644 index 0000000000000..81046b77b5702 --- /dev/null +++ b/scripts/pylib/pytest-twister-harness/tests/helpers/test_config_reader.py @@ -0,0 +1,81 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +import textwrap + +import pytest +from twister_harness.helpers.config_reader import ConfigReader + +CONFIG: str = textwrap.dedent(""" + # comment + X_PM_MCUBOOT_OFFSET=0x0 + X_PM_MCUBOOT_END_ADDRESS=0xd800 + + X_PM_MCUBOOT_NAME=mcuboot + X_PM_MCUBOOT_ID=0 + X_CONFIG_BOOL_TRUE=y + X_CONFIG_BOOL_FALSE=n +""") + + +@pytest.fixture +def config_reader(tmp_path) -> ConfigReader: + config_file = tmp_path / "config" + config_file.write_text(CONFIG) + reader = ConfigReader(config_file) + return reader + + +def test_if_raises_exception_path_is_directory(tmp_path): + build_dir = tmp_path / "build" + build_dir.mkdir() + with pytest.raises(AssertionError, match=f"It is not a file: {build_dir}"): + ConfigReader(build_dir) + + +def test_if_raises_exception_when_path_does_not_exist(tmp_path): + build_dir = tmp_path / "build" + build_dir.mkdir() + config_file = build_dir / "file_does_not_exist" + with pytest.raises(AssertionError, match=f"Path does not exist: {config_file}"): + ConfigReader(config_file) + + +def test_if_can_read_values_from_config_file(config_reader): + assert config_reader.config, "Config is empty" + assert config_reader.read("X_PM_MCUBOOT_NAME") == "mcuboot" + assert config_reader.read("X_CONFIG_BOOL_TRUE") == "y" + assert config_reader.read_bool("X_CONFIG_BOOL_TRUE") is True + assert config_reader.read_bool("X_CONFIG_BOOL_FALSE") is False + assert config_reader.read_hex("X_PM_MCUBOOT_END_ADDRESS") == "0xd800" + assert config_reader.read_int("X_PM_MCUBOOT_END_ADDRESS") == 0xD800 + + +def test_if_raises_value_error_when_key_does_not_exist(config_reader): + with pytest.raises(ValueError, match="Could not find key: DO_NOT_EXIST"): + config_reader.read("DO_NOT_EXIST") + + with pytest.raises(ValueError, match="Could not find key: DO_NOT_EXIST"): + config_reader.read_int("DO_NOT_EXIST") + + +def test_if_raises_value_error_when_default_value_is_not_proper(config_reader): + with pytest.raises(TypeError, match="default value must be type of int, but was .*"): + config_reader.read_hex("X_PM_MCUBOOT_OFFSET", "0x10") + with pytest.raises(TypeError, match="default value must be type of int, but was .*"): + config_reader.read_int("X_PM_MCUBOOT_OFFSET", "0x10") + + +def test_if_returns_default_value_when_key_does_not_exist(config_reader): + assert config_reader.read("DO_NOT_EXIST", "default") == "default" + assert config_reader.read_int("DO_NOT_EXIST", 10) == 10 + assert config_reader.read_hex("DO_NOT_EXIST", 0x20) == "0x20" + assert config_reader.read_bool("DO_NOT_EXIST", True) is True + assert config_reader.read_bool("DO_NOT_EXIST", False) is False + assert config_reader.read_bool("DO_NOT_EXIST", 1) is True + assert config_reader.read_bool("DO_NOT_EXIST", "1") is True + + +def test_if_does_not_raise_exception_in_silent_mode_for_key_not_found(config_reader): + assert config_reader.read("DO_NOT_EXIST", silent=True) is None diff --git a/scripts/pylib/pytest-twister-harness/tests/helpers/utils_test.py b/scripts/pylib/pytest-twister-harness/tests/helpers/utils_test.py new file mode 100644 index 0000000000000..569cd047cad4a --- /dev/null +++ b/scripts/pylib/pytest-twister-harness/tests/helpers/utils_test.py @@ -0,0 +1,84 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +import textwrap + +import pytest +from twister_harness.helpers.utils import match_lines, match_no_lines + +OUTPUT_LINES = textwrap.dedent("""\ + The Zen of Python, by Tim Peters + Beautiful is better than ugly. + Explicit is better than implicit. + Simple is better than complex.\ +""").split('\n') + + +CHECK_LINES = textwrap.dedent("""\ + Although never is often better than right now. + If the implementation is hard to explain, it's a bad idea. + If the implementation is easy to explain, it may be a good idea. + Namespaces are one honking great idea -- let's do more of those!\ +""").split('\n') + + +@pytest.fixture +def output_lines() -> list[str]: + return OUTPUT_LINES + + +@pytest.mark.parametrize( + "expected", + [ + OUTPUT_LINES[0:1], # one line + OUTPUT_LINES[0:2], # two lines + OUTPUT_LINES[-1:], # last line + [OUTPUT_LINES[0][2:-2]], # check partial of a text + ], +) +def test_match_lines_positive(expected, output_lines): + match_lines(output_lines, expected) + + +@pytest.mark.parametrize( + "not_expected", + [ + CHECK_LINES[0:1], + CHECK_LINES[0:2], + CHECK_LINES[-1:], + [CHECK_LINES[-1][2:-2]], + [CHECK_LINES[0], OUTPUT_LINES[0]], # one line match, one not + CHECK_LINES[::-1], # reverted order + ], +) +def test_match_lines_negative(not_expected, output_lines): + with pytest.raises(AssertionError, match="Missing lines.*"): + match_lines(output_lines, not_expected) + + +@pytest.mark.parametrize( + "not_expected", + [ + OUTPUT_LINES[0:1], + OUTPUT_LINES[1:3], + OUTPUT_LINES[-1:], + [CHECK_LINES[0], OUTPUT_LINES[0]], # one line match, one not + OUTPUT_LINES[::-1], # reverted order + ], +) +def test_match_no_lines_negative(not_expected, output_lines): + with pytest.raises(AssertionError, match="Found lines that should not be present.*"): + match_no_lines(output_lines, not_expected) + + +@pytest.mark.parametrize( + "expected", + [ + CHECK_LINES[0:1], + CHECK_LINES[3:5], + CHECK_LINES[-1:], + ], +) +def test_match_no_lines_positive(expected, output_lines): + match_no_lines(output_lines, expected) diff --git a/scripts/pylib/twister/twisterlib/coverage.py b/scripts/pylib/twister/twisterlib/coverage.py index 272aa3c7c1be4..9354d0519c5d2 100644 --- a/scripts/pylib/twister/twisterlib/coverage.py +++ b/scripts/pylib/twister/twisterlib/coverage.py @@ -414,8 +414,9 @@ def collect_coverage(self, outdir, coverage_file, ztest_file, coveragelog): cmd = ["gcovr", "-r", self.base_dir, "--gcov-ignore-parse-errors=negative_hits.warn_once_per_file", "--gcov-executable", self.gcov_tool, - "--gcov-object-directory", outdir, "-e", "tests/*"] + if self.version >= "7.0": + cmd += ["--gcov-object-directory", outdir] cmd += excludes + self.options + ["--json", "-o", coverage_file, outdir] cmd_str = " ".join(cmd) logger.debug(f"Running: {cmd_str}") @@ -428,9 +429,11 @@ def collect_coverage(self, outdir, coverage_file, ztest_file, coveragelog): cmd = ["gcovr", "-r", self.base_dir] + self.options cmd += ["--gcov-executable", self.gcov_tool, - "--gcov-object-directory", outdir, "-f", "tests/ztest", "-e", "tests/ztest/test/*", "--json", "-o", ztest_file, outdir] + if self.version >= "7.0": + cmd += ["--gcov-object-directory", outdir] + cmd_str = " ".join(cmd) logger.debug(f"Running: {cmd_str}") coveragelog.write(f"Running: {cmd_str}\n") diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py index 9b9c142377f90..47942ba1cd139 100644 --- a/scripts/pylib/twister/twisterlib/environment.py +++ b/scripts/pylib/twister/twisterlib/environment.py @@ -836,6 +836,15 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser: will translate to "west flash --runner pyocd" """ ) + parser.add_argument( + "--flash-command", + help="""Instead of 'west flash', uses a custom flash command to flash + when running with --device-testing. Supports comma-separated + argument list, the script is also passed a --build-dir flag with + the build directory as an argument, and a --board-id flag with the + board or probe id if available. + """ + ) parser.add_argument( "-X", "--fixture", action="append", default=[], diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 9cf0cc348c2d8..51784bf8a454b 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -9,6 +9,7 @@ import argparse import contextlib +import csv import logging import math import os @@ -21,6 +22,7 @@ import threading import time from contextlib import contextmanager +from enum import Enum from pathlib import Path from queue import Empty, Queue @@ -40,6 +42,7 @@ try: import pty + except ImportError as capture_error: if os.name == "nt": # "nt" means that program is running on Windows OS pass # "--device-serial-pty" option is not supported on Windows OS @@ -69,6 +72,11 @@ def terminate_process(proc): class Handler: + class FailureType(Enum): + TIMEOUT = "Timeout" + CRASH = "Crash" + FLASH = "Flash Error" + NONE = "None" def __init__(self, instance, type_str: str, options: argparse.Namespace, generator_cmd: str | None = None, suite_name_check: bool = True): """Constructor @@ -91,6 +99,9 @@ def __init__(self, instance, type_str: str, options: argparse.Namespace, self.generator_cmd = generator_cmd self.suite_name_check = suite_name_check self.ready = False + self.ignore_crash = False + self.ignore_unexpected_eof = False + self.execution_time = 0 self.args = [] self.terminated = False @@ -104,7 +115,7 @@ def terminate(self, proc): terminate_process(proc) self.terminated = True - def _verify_ztest_suite_name(self, harness_status, detected_suite_names, handler_time): + def _verify_ztest_suite_name(self, harness_status, detected_suite_names): """ If test suite names was found in test's C source code, then verify if detected suite names from output correspond to expected suite names @@ -117,7 +128,7 @@ def _verify_ztest_suite_name(self, harness_status, detected_suite_names, handler harness_status != TwisterStatus.PASS: return if not detected_suite_names: - self._missing_suite_name(expected_suite_names, handler_time) + self._missing_suite_name(expected_suite_names) return # compare the expect and detect from end one by one without order _d_suite = detected_suite_names[-len(expected_suite_names):] @@ -125,15 +136,15 @@ def _verify_ztest_suite_name(self, harness_status, detected_suite_names, handler set(_d_suite) != set(expected_suite_names) and not set(_d_suite).issubset(set(expected_suite_names)) ): - self._missing_suite_name(expected_suite_names, handler_time) + self._missing_suite_name(expected_suite_names) - def _missing_suite_name(self, expected_suite_names, handler_time): + def _missing_suite_name(self, expected_suite_names): """ Change result of performed test if problem with missing or unpropper suite name was occurred. """ self.instance.status = TwisterStatus.FAIL - self.instance.execution_time = handler_time + self.instance.execution_time = self.execution_time for tc in self.instance.testcases: tc.status = TwisterStatus.FAIL self.instance.reason = "Testsuite mismatch" @@ -142,21 +153,20 @@ def _missing_suite_name(self, expected_suite_names, handler_time): f" do not correspond with expected: {str(expected_suite_names)}", ) - def _final_handle_actions(self, harness, handler_time): + def _final_handle_actions(self, harness): # only for Ztest tests: harness_class_name = type(harness).__name__ if self.suite_name_check and harness_class_name == "Test": self._verify_ztest_suite_name( harness.status, - harness.detected_suite_names, - handler_time - ) + harness.detected_suite_names + ) if self.instance.status == TwisterStatus.FAIL: return if not harness.matched_run_id and harness.run_id_exists: self.instance.status = TwisterStatus.FAIL - self.instance.execution_time = handler_time + self.instance.execution_time = self.execution_time self.instance.reason = "RunID mismatch" for tc in self.instance.testcases: tc.status = TwisterStatus.FAIL @@ -176,6 +186,38 @@ def get_default_domain_build_dir(self): build_dir = self.build_dir return build_dir + def _update_instance_info(self, harness, failure_type=FailureType.NONE): + self.instance.execution_time = self.execution_time + if (not self.terminated and self.returncode != 0 and not self.ignore_crash) or \ + harness.status == TwisterStatus.NONE: + + # In case of a crash, we set the status to Fail + self.instance.status = TwisterStatus.FAIL + + # Depending on the failure type, we set the reason + if self.options.enable_valgrind and self.returncode == 2: + self.instance.reason = "Valgrind error" + elif failure_type == self.FailureType.TIMEOUT: + self.instance.reason = "Timeout" + elif failure_type == self.FailureType.FLASH: + self.instance.reason = "Timeout during flashing" + + # In case none of the above applies, we set a generic error + if not self.instance.reason and self.returncode != 0: + self.instance.reason = f"Exited with {self.returncode}" + else: + self.instance.reason = self.instance.reason or "Unknown Error" + elif harness.status != TwisterStatus.NONE: + self.instance.status = harness.status + if harness.status in [TwisterStatus.FAIL, TwisterStatus.ERROR]: + self.instance.reason = harness.reason + elif failure_type in [self.FailureType.TIMEOUT]: + self.instance.reason = "Timeout" + else: + self.instance.reason = "Unknown Error" + + if self.instance.status in [TwisterStatus.ERROR, TwisterStatus.FAIL]: + self.instance.add_missing_case_status(TwisterStatus.BLOCK, self.instance.reason) class BinaryHandler(Handler): def __init__( @@ -317,27 +359,6 @@ def _create_env(self): return env - def _update_instance_info(self, harness, handler_time): - self.instance.execution_time = handler_time - if not self.terminated and self.returncode != 0: - self.instance.status = TwisterStatus.FAIL - if self.options.enable_valgrind and self.returncode == 2: - self.instance.reason = "Valgrind error" - else: - # When a process is killed, the default handler returns 128 + SIGTERM - # so in that case the return code itself is not meaningful - self.instance.reason = f"Failed (rc={self.returncode})" - self.instance.add_missing_case_status(TwisterStatus.BLOCK) - elif harness.status != TwisterStatus.NONE: - self.instance.status = harness.status - if harness.status == TwisterStatus.FAIL: - self.instance.reason = f"Failed harness:'{harness.reason}'" - self.instance.add_missing_case_status(TwisterStatus.BLOCK) - else: - self.instance.status = TwisterStatus.FAIL - self.instance.reason = "Timeout" - self.instance.add_missing_case_status(TwisterStatus.BLOCK, "Timeout") - def handle(self, harness): robot_test = getattr(harness, "is_robot_test", False) @@ -370,19 +391,19 @@ def handle(self, harness): self.returncode = proc.returncode if proc.returncode != 0: self.instance.status = TwisterStatus.ERROR - self.instance.reason = f"BinaryHandler returned {proc.returncode}" + self.instance.reason = f"rc={proc.returncode}" self.try_kill_process_by_pid() - handler_time = time.time() - start_time + self.execution_time = time.time() - start_time # FIXME: This is needed when killing the simulator, the console is # garbled and needs to be reset. Did not find a better way to do that. if sys.stdout.isatty(): subprocess.call(["stty", "sane"], stdin=sys.stdout) - self._update_instance_info(harness, handler_time) + self._update_instance_info(harness) - self._final_handle_actions(harness, handler_time) + self._final_handle_actions(harness) class SimulationHandler(BinaryHandler): @@ -544,7 +565,24 @@ def run_custom_script(script, timeout): proc.communicate() logger.error(f"{script} timed out") + def _create_flash_command(self, hardware): + flash_command = next(csv.reader([self.options.flash_command])) + + command = [flash_command[0]] + command.extend(['--build-dir', self.build_dir]) + + board_id = hardware.probe_id or hardware.id + if board_id: + command.extend(['--board-id', board_id]) + + command.extend(flash_command[1:]) + + return command + def _create_command(self, runner, hardware): + if self.options.flash_command: + return self._create_flash_command(hardware) + command = ["west", "flash", "--skip-rebuild", "-d", self.build_dir] command_extra_args = [] @@ -556,7 +594,7 @@ def _create_command(self, runner, hardware): # 3) Multiple values: --west-flash="--board-id=42,--erase" # This results in options.west_flash == "--board-id=42 --erase" if self.options.west_flash and self.options.west_flash != []: - command_extra_args.extend(self.options.west_flash.split(',')) + command_extra_args.extend(next(csv.reader([self.options.west_flash]))) if runner: command.append("--runner") @@ -607,20 +645,6 @@ def _create_command(self, runner, hardware): return command - def _update_instance_info(self, harness, handler_time, flash_error): - self.instance.execution_time = handler_time - if harness.status != TwisterStatus.NONE: - self.instance.status = harness.status - if harness.status == TwisterStatus.FAIL: - self.instance.reason = f"Failed harness:'{harness.reason}'" - self.instance.add_missing_case_status(TwisterStatus.BLOCK, harness.status) - elif not flash_error: - self.instance.status = TwisterStatus.FAIL - self.instance.reason = "Timeout" - - if self.instance.status in [TwisterStatus.ERROR, TwisterStatus.FAIL]: - self.instance.add_missing_case_status(TwisterStatus.BLOCK, self.instance.reason) - def _terminate_pty(self, ser_pty, ser_pty_process): logger.debug(f"Terminating serial-pty:'{ser_pty}'") terminate_process(ser_pty_process) @@ -679,28 +703,21 @@ def get_hardware(self): logger.error(self.instance.reason) return hardware - def _get_serial_device(self, serial_pty, hardware_serial): + def _start_serial_pty(self, serial_pty, serial_pty_master): ser_pty_process = None - if serial_pty: - master, slave = pty.openpty() - try: - ser_pty_process = subprocess.Popen( - re.split('[, ]', serial_pty), - stdout=master, - stdin=master, - stderr=master - ) - except subprocess.CalledProcessError as error: - logger.error( - f"Failed to run subprocess {serial_pty}, error {error.output}" - ) - return - - serial_device = os.ttyname(slave) - else: - serial_device = hardware_serial + try: + ser_pty_process = subprocess.Popen( + re.split('[, ]', serial_pty), + stdout=serial_pty_master, + stdin=serial_pty_master, + stderr=serial_pty_master + ) + except subprocess.CalledProcessError as error: + logger.error( + f"Failed to run subprocess {serial_pty}, error {error.output}" + ) - return serial_device, ser_pty_process + return ser_pty_process def handle(self, harness): runner = None @@ -713,7 +730,11 @@ def handle(self, harness): runner = hardware.runner or self.options.west_runner serial_pty = hardware.serial_pty - serial_device, ser_pty_process = self._get_serial_device(serial_pty, hardware.serial) + if not serial_pty: + serial_device = hardware.serial + else: + ser_pty_master, slave = pty.openpty() + serial_device = os.ttyname(slave) logger.debug(f"Using serial device {serial_device} @ {hardware.baud} baud") @@ -735,7 +756,10 @@ def handle(self, harness): flash_timeout += self.get_test_timeout() serial_port = None + ser_pty_process = None if hardware.flash_before is False: + if serial_pty: + ser_pty_process = self._start_serial_pty(serial_pty, ser_pty_master) serial_port = serial_device try: @@ -759,7 +783,7 @@ def handle(self, harness): d_log = f"{self.instance.build_dir}/device.log" logger.debug(f'Flash command: {command}', ) - flash_error = False + failure_type = Handler.FailureType.NONE try: stdout = stderr = None with subprocess.Popen(command, stderr=subprocess.PIPE, stdout=subprocess.PIPE) as proc: @@ -771,7 +795,7 @@ def handle(self, harness): if proc.returncode != 0: self.instance.status = TwisterStatus.ERROR self.instance.reason = "Device issue (Flash error?)" - flash_error = True + failure_type = Handler.FailureType.FLASH with open(d_log, "w") as dlog_fp: dlog_fp.write(stderr.decode()) halt_monitor_evt.set() @@ -781,7 +805,7 @@ def handle(self, harness): (stdout, stderr) = proc.communicate() self.instance.status = TwisterStatus.ERROR self.instance.reason = "Device issue (Timeout)" - flash_error = True + failure_type = Handler.FailureType.FLASH with open(d_log, "w") as dlog_fp: dlog_fp.write(stderr.decode()) @@ -790,7 +814,7 @@ def handle(self, harness): halt_monitor_evt.set() self.instance.status = TwisterStatus.ERROR self.instance.reason = "Device issue (Flash error)" - flash_error = True + failure_type = Handler.FailureType.FLASH if post_flash_script: timeout = 30 @@ -801,14 +825,36 @@ def handle(self, harness): # Connect to device after flashing it if hardware.flash_before: try: + if serial_pty: + ser_pty_process = self._start_serial_pty(serial_pty, ser_pty_master) logger.debug(f"Attach serial device {serial_device} @ {hardware.baud} baud") ser.port = serial_device - ser.open() + + # Apply ESP32-specific RTS/DTR reset logic + if runner == "esp32": + logger.debug("Applying ESP32 RTS/DTR reset sequence") + + # Prepare: IO0=HIGH (DTR=True), EN=HIGH (RTS=False) + ser.dtr = True + ser.rts = False + + ser.open() + + # Reset pulse: IO0=LOW (DTR=False), EN=LOW (RTS=True) + ser.dtr = False + ser.rts = True + time.sleep(0.01) + + # Return to normal boot + ser.rts = False + else: + ser.open() + except serial.SerialException as e: self._handle_serial_exception(e, hardware, serial_pty, ser_pty_process) return - if not flash_error: + if failure_type != Handler.FailureType.FLASH: # Always wait at most the test timeout here after flashing. t.join(self.get_test_timeout()) else: @@ -830,11 +876,11 @@ def handle(self, harness): if serial_pty: self._terminate_pty(serial_pty, ser_pty_process) - handler_time = time.time() - start_time + self.execution_time = time.time() - start_time - self._update_instance_info(harness, handler_time, flash_error) + self._update_instance_info(harness, failure_type=failure_type) - self._final_handle_actions(harness, handler_time) + self._final_handle_actions(harness) if post_script: timeout = 30 @@ -877,10 +923,10 @@ def __init__( self.stderr_fn = os.path.join(instance.build_dir, "qemu.stderr") if instance.testsuite.ignore_qemu_crash: - self.ignore_qemu_crash = True + self.ignore_crash = True self.ignore_unexpected_eof = True else: - self.ignore_qemu_crash = False + self.ignore_crash = False self.ignore_unexpected_eof = False @staticmethod @@ -903,13 +949,13 @@ def _thread_get_fifo_names(fifo_fn): return fifo_in, fifo_out @staticmethod - def _thread_update_instance_info(handler, handler_time, status, reason): - handler.instance.execution_time = handler_time + def _thread_update_instance_info(handler, status, reason): + handler.instance.execution_time = handler.execution_time handler.instance.status = status if reason: handler.instance.reason = reason else: - handler.instance.reason = "Unknown" + handler.instance.reason = "Unknown Error" @staticmethod def _thread(handler, timeout, outdir, logfile, fifo_fn, pid_fn, @@ -1025,12 +1071,13 @@ def _thread(handler, timeout, outdir, logfile, fifo_fn, pid_fn, timeout_time = time.time() + 2 line = "" - handler_time = time.time() - start_time + handler.execution_time = time.time() - start_time logger.debug( - f"QEMU ({pid}) complete with {_status} ({_reason}) after {handler_time} seconds" + f"QEMU ({pid}) complete with {_status} ({_reason}) " + f"after {handler.execution_time} seconds" ) - QEMUHandler._thread_update_instance_info(handler, handler_time, _status, _reason) + QEMUHandler._thread_update_instance_info(handler, _status, _reason) if pid: # Oh well, as long as it's dead! User probably sent Ctrl-C @@ -1059,17 +1106,6 @@ def _create_command(self, sysbuild_build_dir): return command - def _update_instance_info(self, harness, is_timeout): - if (self.returncode != 0 and not self.ignore_qemu_crash) or \ - harness.status == TwisterStatus.NONE: - self.instance.status = TwisterStatus.FAIL - if is_timeout: - self.instance.reason = "Timeout" - else: - if not self.instance.reason: - self.instance.reason = f"Exited with {self.returncode}" - self.instance.add_missing_case_status(TwisterStatus.BLOCK) - def handle(self, harness): self.run = True @@ -1094,7 +1130,7 @@ def handle(self, harness): logger.debug(f"Running {self.name} ({self.type_str})") - is_timeout = False + failure_type = self.FailureType.NONE qemu_pid = None with open(self.stdout_fn, "w") as stdout_fp, \ @@ -1113,7 +1149,7 @@ def handle(self, harness): # in that case kill -9 QEMU process directly and leave # twister to judge testing result by console output - is_timeout = True + failure_type = self.FailureType.TIMEOUT self.terminate(proc) if harness.status == TwisterStatus.PASS: self.returncode = 0 @@ -1139,9 +1175,9 @@ def handle(self, harness): logger.debug(f"return code from QEMU ({qemu_pid}): {self.returncode}") - self._update_instance_info(harness, is_timeout) + self._update_instance_info(harness, failure_type=failure_type) - self._final_handle_actions(harness, 0) + self._final_handle_actions(harness) def get_fifo(self): return self.fifo_fn @@ -1217,13 +1253,13 @@ def _stop_qemu_process(pid): pass @staticmethod - def _monitor_update_instance_info(handler, handler_time, status, reason): - handler.instance.execution_time = handler_time + def _monitor_update_instance_info(handler, status, reason): + handler.instance.execution_time = handler.execution_time handler.instance.status = status if reason: handler.instance.reason = reason else: - handler.instance.reason = "Unknown" + handler.instance.reason = "Unknown Error" def _set_qemu_filenames(self, sysbuild_build_dir): # PID file will be created in the main sysbuild app's build dir @@ -1240,17 +1276,6 @@ def _create_command(self, sysbuild_build_dir): return command - def _update_instance_info(self, harness, is_timeout): - if (self.returncode != 0 and not self.ignore_qemu_crash) or \ - harness.status == TwisterStatus.NONE: - self.instance.status = TwisterStatus.FAIL - if is_timeout: - self.instance.reason = "Timeout" - else: - if not self.instance.reason: - self.instance.reason = f"Exited with {self.returncode}" - self.instance.add_missing_case_status(TwisterStatus.BLOCK) - def _enqueue_char(self, queue): while not self.stop_thread: if not self.pipe_handle: @@ -1371,11 +1396,12 @@ def _monitor_output( self.stop_thread = True - handler_time = time.time() - start_time + self.execution_time = time.time() - start_time logger.debug( - f"QEMU ({self.pid}) complete with {_status} ({_reason}) after {handler_time} seconds" + f"QEMU ({self.pid}) complete with {_status} ({_reason}) " + f"after {self.execution_time} seconds" ) - self._monitor_update_instance_info(self, handler_time, _status, _reason) + self._monitor_update_instance_info(self, _status, _reason) self._close_log_file(log_out_fp) self._stop_qemu_process(self.pid) @@ -1387,7 +1413,7 @@ def handle(self, harness): self._set_qemu_filenames(domain_build_dir) logger.debug(f"Running {self.name} ({self.type_str})") - is_timeout = False + failure_type = self.FailureType.NONE self.stop_thread = False queue = Queue() @@ -1406,6 +1432,7 @@ def handle(self, harness): if (thread_max_time - time.time()) < 0: logger.debug("Timed out while monitoring QEMU output") + failure_type = self.FailureType.TIMEOUT proc.terminate() # sleep for a while before attempting to kill time.sleep(0.5) @@ -1424,9 +1451,9 @@ def handle(self, harness): os.close(self.pipe_handle) self.pipe_handle = None - self._update_instance_info(harness, is_timeout) + self._update_instance_info(harness, failure_type=failure_type) - self._final_handle_actions(harness, 0) + self._final_handle_actions(harness) def get_fifo(self): return self.fifo_fn diff --git a/scripts/pylib/twister/twisterlib/harness.py b/scripts/pylib/twister/twisterlib/harness.py index 0e9d27cf0ddd4..ebc1152d2e41b 100644 --- a/scripts/pylib/twister/twisterlib/harness.py +++ b/scripts/pylib/twister/twisterlib/harness.py @@ -479,6 +479,9 @@ def _generate_parameters_for_hardware(self, handler: Handler): if options.west_flash and options.west_flash != []: command.append(f'--west-flash-extra-args={options.west_flash}') + if options.flash_command: + command.append(f'--flash-command={options.flash_command}') + if board_id := hardware.probe_id or hardware.id: command.append(f'--device-id={board_id}') diff --git a/scripts/pylib/twister/twisterlib/testinstance.py b/scripts/pylib/twister/twisterlib/testinstance.py index 793b6bbdc750a..8b36c8e7f9686 100644 --- a/scripts/pylib/twister/twisterlib/testinstance.py +++ b/scripts/pylib/twister/twisterlib/testinstance.py @@ -55,7 +55,7 @@ def __init__(self, testsuite, platform, toolchain, outdir): self.platform: Platform = platform self._status = TwisterStatus.NONE - self.reason = "Unknown" + self.reason = None self.metrics = dict() self.handler = None self.recording = None diff --git a/scripts/pylib/twister/twisterlib/twister_main.py b/scripts/pylib/twister/twisterlib/twister_main.py index 5e3cf1ef464b9..8e47c538510c0 100644 --- a/scripts/pylib/twister/twisterlib/twister_main.py +++ b/scripts/pylib/twister/twisterlib/twister_main.py @@ -9,11 +9,17 @@ import shutil import sys import time +from collections.abc import Sequence import colorama from colorama import Fore from twisterlib.coverage import run_coverage -from twisterlib.environment import TwisterEnv +from twisterlib.environment import ( + TwisterEnv, + add_parse_arguments, + parse_arguments, + python_version_guard, +) from twisterlib.hardwaremap import HardwareMap from twisterlib.log_helper import close_logging, setup_logging from twisterlib.package import Artifacts @@ -27,7 +33,7 @@ def init_color(colorama_strip): colorama.init(strip=colorama_strip) -def twister(options: argparse.Namespace, default_options: argparse.Namespace): +def twister(options: argparse.Namespace, default_options: argparse.Namespace) -> int: start_time = time.time() # Configure color output @@ -230,9 +236,17 @@ def twister(options: argparse.Namespace, default_options: argparse.Namespace): return 0 -def main(options: argparse.Namespace, default_options: argparse.Namespace): +def main(argv: Sequence[str] | None = None) -> int: + """Main function to run twister.""" try: - return_code = twister(options, default_options) + python_version_guard() + + parser = add_parse_arguments() + options = parse_arguments(parser, argv) + default_options = parse_arguments(parser, [], on_init=False) + return twister(options, default_options) finally: close_logging() - return return_code + if (os.name != "nt") and os.isatty(1): + # (OS is not Windows) and (stdout is interactive) + os.system("stty sane <&1") diff --git a/scripts/release/list_backports.py b/scripts/release/list_backports.py index 0b20364356b73..08efcf833e6e7 100755 --- a/scripts/release/list_backports.py +++ b/scripts/release/list_backports.py @@ -68,7 +68,7 @@ def parse_args(): parser.add_argument('-e', '--end', dest='end', help='end date (YYYY-mm-dd)', metavar='END_DATE', type=valid_date_type) parser.add_argument("-o", "--org", default="zephyrproject-rtos", - help="Github organisation") + help="Github organization") parser.add_argument('-p', '--include-pull', dest='includes', help='include pull request (can be specified multiple times)', metavar='PR', type=int, action='append', default=[]) diff --git a/scripts/requirements-actions.in b/scripts/requirements-actions.in index 492a1a4fa84f8..997afed387128 100644 --- a/scripts/requirements-actions.in +++ b/scripts/requirements-actions.in @@ -17,7 +17,7 @@ natsort ply>=3.10 psutil>=5.6.6 pyelftools>=0.29 -pygithub +pygithub>=2.7.0 pykwalify pylint>=3 pyserial diff --git a/scripts/requirements-actions.txt b/scripts/requirements-actions.txt index 4a987e9f0dedd..8c28b2d22f776 100644 --- a/scripts/requirements-actions.txt +++ b/scripts/requirements-actions.txt @@ -302,10 +302,6 @@ cryptography==45.0.5 \ --hash=sha256:e74d30ec9c7cb2f404af331d5b4099a9b322a8a6b25c4632755c8757345baac5 \ --hash=sha256:f3562c2f23c612f2e4a6964a61d942f891d29ee320edb62ff48ffb99f3de9ae8 # via pyjwt -deprecated==1.2.18 \ - --hash=sha256:422b6f6d859da6f2ef57857761bfb392480502a64c3028ca9bbe86085d72115d \ - --hash=sha256:bd5011788200372a32418f888e326a09ff80d0214bd961147cfed01b5c018eec - # via pygithub dill==0.4.0 \ --hash=sha256:0633f1d2df477324f53a895b02c901fb961bdbf65a17122586ea7019292cbcf0 \ --hash=sha256:44f54bf6412c2c8464c14e8243eb163690a9800dbe2c367330883b19c7561049 @@ -816,9 +812,9 @@ pyelftools==0.32 \ --hash=sha256:013df952a006db5e138b1edf6d8a68ecc50630adbd0d83a2d41e7f846163d738 \ --hash=sha256:6de90ee7b8263e740c8715a925382d4099b354f29ac48ea40d840cf7aa14ace5 # via -r requirements-actions.in -pygithub==2.6.1 \ - --hash=sha256:6f2fa6d076ccae475f9fc392cc6cdbd54db985d4f69b8833a28397de75ed6ca3 \ - --hash=sha256:b5c035392991cca63959e9453286b41b54d83bf2de2daa7d7ff7e4312cebf3bf +pygithub==2.8.1 \ + --hash=sha256:23a0a5bca93baef082e03411bf0ce27204c32be8bfa7abc92fe4a3e132936df0 \ + --hash=sha256:341b7c78521cb07324ff670afd1baa2bf5c286f8d9fd302c1798ba594a5400c9 # via -r requirements-actions.in pygments==2.19.2 \ --hash=sha256:636cb2477cec7f8952536970bc533bc43743542f70392ae026374600add5b887 \ @@ -1344,9 +1340,7 @@ wrapt==1.17.2 \ --hash=sha256:f917c1180fdb8623c2b75a99192f4025e412597c50b2ac870f156de8fb101119 \ --hash=sha256:fc78a84e2dfbc27afe4b2bd7c80c8db9bca75cc5b85df52bfe634596a1da846b \ --hash=sha256:ff04ef6eec3eee8a5efef2401495967a916feaa353643defcc03fc74fe213b58 - # via - # deprecated - # python-can + # via python-can xlsxwriter==3.2.5 \ --hash=sha256:4f4824234e1eaf9d95df9a8fe974585ff91d0f5e3d3f12ace5b71e443c1c6abd \ --hash=sha256:7e88469d607cdc920151c0ab3ce9cf1a83992d4b7bc730c5ffdd1a12115a7dbe diff --git a/scripts/requirements-extras.txt b/scripts/requirements-extras.txt index 772f59b0ddc43..59f2eb3ff9866 100644 --- a/scripts/requirements-extras.txt +++ b/scripts/requirements-extras.txt @@ -6,6 +6,9 @@ anytree # to use in ./scripts for memory footprint, code coverage, etc. gitpython>=3.1.41 +# used by scripts/footprint/plot.py for generating plots of size reports +plotly + # helper for developers - check git commit messages gitlint diff --git a/scripts/tests/twister/test_handlers.py b/scripts/tests/twister/test_handlers.py index d0f62cccf6ebd..e38172210515d 100644 --- a/scripts/tests/twister/test_handlers.py +++ b/scripts/tests/twister/test_handlers.py @@ -60,7 +60,7 @@ def mocked_instance(tmp_path): ) instance.status = TwisterStatus.NONE - instance.reason = 'Unknown' + instance.reason = None return instance @@ -137,18 +137,15 @@ def test_handler_final_handle_actions(mocked_instance): harness.run_id_exists = True harness.recording = mock.Mock() - handler_time = mock.Mock() - - handler._final_handle_actions(harness, handler_time) + handler._final_handle_actions(harness) assert handler.instance.status == TwisterStatus.FAIL - assert handler.instance.execution_time == handler_time assert handler.instance.reason == 'RunID mismatch' assert all(testcase.status == TwisterStatus.FAIL for \ testcase in handler.instance.testcases) handler.instance.reason = 'This reason shan\'t be changed.' - handler._final_handle_actions(harness, handler_time) + handler._final_handle_actions(harness) instance.assert_has_calls([mock.call.record(harness.recording)]) @@ -176,14 +173,11 @@ def test_handler_verify_ztest_suite_name( harness_status = TwisterStatus.PASS - handler_time = mock.Mock() - with mock.patch.object(Handler, '_missing_suite_name') as _missing_mocked: handler = Handler(instance, 'build', mock.Mock()) handler._verify_ztest_suite_name( harness_status, detected_suite_names, - handler_time ) if should_be_called: @@ -201,12 +195,9 @@ def test_handler_missing_suite_name(mocked_instance): expected_suite_names = ['dummy_testsuite_name'] - handler_time = mock.Mock() - - handler._missing_suite_name(expected_suite_names, handler_time) + handler._missing_suite_name(expected_suite_names) assert handler.instance.status == TwisterStatus.FAIL - assert handler.instance.execution_time == handler_time assert handler.instance.reason == 'Testsuite mismatch' assert all( testcase.status == TwisterStatus.FAIL for testcase in handler.instance.testcases @@ -510,10 +501,10 @@ def test_binaryhandler_create_env( TESTDATA_6 = [ (TwisterStatus.NONE, False, 2, True, TwisterStatus.FAIL, 'Valgrind error', False), - (TwisterStatus.NONE, False, 1, False, TwisterStatus.FAIL, 'Failed (rc=1)', False), - (TwisterStatus.FAIL, False, 0, False, TwisterStatus.FAIL, "Failed harness:'foobar'", False), - ('success', False, 0, False, 'success', 'Unknown', False), - (TwisterStatus.NONE, True, 1, True, TwisterStatus.FAIL, 'Timeout', True), + (TwisterStatus.NONE, False, 1, False, TwisterStatus.FAIL, 'Exited with 1', False), + (TwisterStatus.FAIL, False, 0, False, TwisterStatus.FAIL, "foobar", False), + ('success', False, 0, False, 'success', None, False), + (TwisterStatus.NONE, True, 1, True, TwisterStatus.FAIL, 'Exited with 1', True), ] @pytest.mark.parametrize( @@ -535,16 +526,13 @@ def test_binaryhandler_update_instance_info( handler = BinaryHandler(mocked_instance, 'build', mock.Mock( enable_valgrind=enable_valgrind )) - handler_time = 59 handler.terminated = terminated handler.returncode = returncode missing_mock = mock.Mock() handler.instance.add_missing_case_status = missing_mock mocked_harness = mock.Mock(status=harness_status, reason="foobar") - handler._update_instance_info(mocked_harness, handler_time) - - assert handler.instance.execution_time == handler_time + handler._update_instance_info(mocked_harness) assert handler.instance.status == expected_status assert handler.instance.reason == expected_reason @@ -1061,33 +1049,38 @@ def mock_availability(handler, instance, no=num_of_failures): None, None, None, + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir'] ), ( [], None, None, + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir'] ), ( '--dummy', None, None, + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--', '--dummy'] ), ( - '--dummy1,--dummy2', + '--dummy1,--dummy2,"--dummy, 3"', + None, None, None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', - '--', '--dummy1', '--dummy2'] + '--', '--dummy1', '--dummy2', '--dummy, 3'] ), ( None, 'runner', 'product', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'runner', 'param1', 'param2'] ), @@ -1096,6 +1089,7 @@ def mock_availability(handler, instance, no=num_of_failures): None, 'pyocd', 'product', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'pyocd', 'param1', 'param2', '--', '--dev-id', 12345] ), @@ -1103,6 +1097,7 @@ def mock_availability(handler, instance, no=num_of_failures): None, 'nrfjprog', 'product', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'nrfjprog', 'param1', 'param2', '--', '--dev-id', 12345] ), @@ -1110,6 +1105,7 @@ def mock_availability(handler, instance, no=num_of_failures): None, 'openocd', 'STM32 STLink', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'openocd', 'param1', 'param2', '--', '--cmd-pre-init', 'hla_serial 12345'] @@ -1118,6 +1114,7 @@ def mock_availability(handler, instance, no=num_of_failures): None, 'openocd', 'STLINK-V3', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'openocd', 'param1', 'param2', '--', '--cmd-pre-init', 'hla_serial 12345'] @@ -1126,6 +1123,7 @@ def mock_availability(handler, instance, no=num_of_failures): None, 'openocd', 'EDBG CMSIS-DAP', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'openocd', 'param1', 'param2', '--', '--cmd-pre-init', 'cmsis_dap_serial 12345'] @@ -1134,6 +1132,7 @@ def mock_availability(handler, instance, no=num_of_failures): None, 'jlink', 'product', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'jlink', '--dev-id', 12345, 'param1', 'param2'] @@ -1142,23 +1141,39 @@ def mock_availability(handler, instance, no=num_of_failures): None, 'stm32cubeprogrammer', 'product', + None, ['west', 'flash', '--skip-rebuild', '-d', '$build_dir', '--runner', 'stm32cubeprogrammer', '--tool-opt=sn=12345', 'param1', 'param2'] ), - + ( + None, + None, + None, + 'flash_command', + ['flash_command', '--build-dir', '$build_dir', '--board-id', 12345] + ), + ( + None, + None, + None, + 'path to/flash_command,with,args,"1, 2, 3",4', + ['path to/flash_command', '--build-dir', '$build_dir', '--board-id', + 12345, 'with', 'args', '1, 2, 3', '4'] + ), ] TESTDATA_13_2 = [(True), (False)] @pytest.mark.parametrize( 'self_west_flash, runner,' \ - ' hardware_product_name, expected', + ' hardware_product_name, self_flash_command, expected', TESTDATA_13, ids=['default', '--west-flash', 'one west flash value', 'multiple west flash values', 'generic runner', 'pyocd', 'nrfjprog', 'openocd, STM32 STLink', 'openocd, STLINK-v3', - 'openocd, EDBG CMSIS-DAP', 'jlink', 'stm32cubeprogrammer'] + 'openocd, EDBG CMSIS-DAP', 'jlink', 'stm32cubeprogrammer', + 'flash_command', 'flash_command with args'] ) @pytest.mark.parametrize('hardware_probe', TESTDATA_13_2, ids=['probe', 'id']) def test_devicehandler_create_command( @@ -1167,10 +1182,12 @@ def test_devicehandler_create_command( runner, hardware_probe, hardware_product_name, + self_flash_command, expected ): handler = DeviceHandler(mocked_instance, 'build', mock.Mock()) - handler.options = mock.Mock(west_flash=self_west_flash) + handler.options = mock.Mock(west_flash=self_west_flash, + flash_command=self_flash_command) handler.generator_cmd = 'generator_cmd' expected = [handler.build_dir if val == '$build_dir' else \ @@ -1189,36 +1206,34 @@ def test_devicehandler_create_command( TESTDATA_14 = [ - ('success', False, 'success', 'Unknown', False), - (TwisterStatus.FAIL, False, TwisterStatus.FAIL, "Failed harness:'foobar'", True), - (TwisterStatus.ERROR, False, TwisterStatus.ERROR, 'Unknown', True), - (TwisterStatus.NONE, True, TwisterStatus.NONE, 'Unknown', False), - (TwisterStatus.NONE, False, TwisterStatus.FAIL, 'Timeout', True), + ('success', Handler.FailureType.NONE, 'success', None, False), + (TwisterStatus.FAIL, Handler.FailureType.NONE, TwisterStatus.FAIL, + "foobar", True), + (TwisterStatus.ERROR, Handler.FailureType.NONE, TwisterStatus.ERROR, 'foobar', True), + (TwisterStatus.NONE, Handler.FailureType.NONE, TwisterStatus.FAIL, 'Unknown Error', True), ] @pytest.mark.parametrize( - 'harness_status, flash_error,' \ + 'harness_status, failure_type,' \ ' expected_status, expected_reason, do_add_missing', TESTDATA_14, - ids=['custom success', 'failed', 'error', 'flash error', 'no status'] + ids=['custom success', 'failed', 'error', 'no status'] ) def test_devicehandler_update_instance_info( mocked_instance, harness_status, - flash_error, + failure_type, expected_status, expected_reason, do_add_missing ): handler = DeviceHandler(mocked_instance, 'build', mock.Mock()) - handler_time = 59 missing_mock = mock.Mock() handler.instance.add_missing_case_status = missing_mock mocked_harness = mock.Mock(status=harness_status, reason="foobar") - handler._update_instance_info(mocked_harness, handler_time, flash_error) + handler._update_instance_info(mocked_harness, failure_type=failure_type) - assert handler.instance.execution_time == handler_time assert handler.instance.status == expected_status assert handler.instance.reason == expected_reason @@ -1308,21 +1323,19 @@ def mock_serial(*args, **kwargs): TESTDATA_16 = [ - ('dummy1 dummy2', None, 'slave name'), - ('dummy1,dummy2', CalledProcessError, None), - (None, None, 'dummy hardware serial'), + ('dummy1 dummy2', None), + ('dummy1,dummy2', CalledProcessError), ] @pytest.mark.parametrize( - 'serial_pty, popen_exception, expected_device', + 'serial_pty, popen_exception', TESTDATA_16, - ids=['pty', 'pty process error', 'no pty'] + ids=['pty', 'pty process error'] ) -def test_devicehandler_get_serial_device( +def test_devicehandler_start_serial_pty( mocked_instance, serial_pty, - popen_exception, - expected_device + popen_exception ): def mock_popen(command, *args, **kwargs): assert command == ['dummy1', 'dummy2'] @@ -1331,21 +1344,16 @@ def mock_popen(command, *args, **kwargs): return mock.Mock() handler = DeviceHandler(mocked_instance, 'build', mock.Mock()) - hardware_serial = 'dummy hardware serial' popen_mock = mock.Mock(side_effect=mock_popen) - openpty_mock = mock.Mock(return_value=('master', 'slave')) - ttyname_mock = mock.Mock(side_effect=lambda x: x + ' name') - with mock.patch('subprocess.Popen', popen_mock), \ - mock.patch('pty.openpty', openpty_mock), \ - mock.patch('os.ttyname', ttyname_mock): - result = handler._get_serial_device(serial_pty, hardware_serial) + with mock.patch('subprocess.Popen', popen_mock): + result = handler._start_serial_pty(serial_pty, 'master') if popen_exception: assert result is None else: - assert result[0] == expected_device + assert result is not None TESTDATA_17 = [ (False, False, False, False, None, False, False, @@ -1387,16 +1395,13 @@ def test_devicehandler_handle( expected_reason, expected_logs ): - def mock_get_serial(serial_pty, hardware_serial): - if serial_pty: - serial_pty_process = mock.Mock( - name='dummy serial PTY process', - communicate=mock.Mock( - return_value=('', '') - ) + def mock_start_serial_pty(serial_pty, serial_pty_master): + return mock.Mock( + name='dummy serial PTY process', + communicate=mock.Mock( + return_value=('', '') ) - return 'dummy serial PTY device', serial_pty_process - return 'dummy serial device', None + ) def mock_create_serial(*args, **kwargs): if raise_create_serial: @@ -1450,7 +1455,7 @@ def mock_popen(command, *args, **kwargs): west_flash=None, west_runner=None ) - handler._get_serial_device = mock.Mock(side_effect=mock_get_serial) + handler._start_serial_pty = mock.Mock(side_effect=mock_start_serial_pty) handler._create_command = mock.Mock(return_value=['dummy', 'command']) handler.run_custom_script = mock.Mock() handler._create_serial_connection = mock.Mock( @@ -1466,10 +1471,15 @@ def mock_popen(command, *args, **kwargs): harness = mock.Mock() + openpty_mock = mock.Mock(return_value=('master', 'slave')) + ttyname_mock = mock.Mock(side_effect=lambda x: x + ' name') + with mock.patch('builtins.open', mock.mock_open(read_data='')), \ mock.patch('subprocess.Popen', side_effect=mock_popen), \ mock.patch('threading.Event', mock.Mock()), \ - mock.patch('threading.Thread', side_effect=mock_thread): + mock.patch('threading.Thread', side_effect=mock_thread), \ + mock.patch('pty.openpty', openpty_mock), \ + mock.patch('os.ttyname', ttyname_mock): handler.handle(harness) handler.get_hardware.assert_called_once() @@ -1521,7 +1531,7 @@ def test_qemuhandler_init( handler = QEMUHandler(mocked_instance, 'build', mock.Mock()) - assert handler.ignore_qemu_crash == expected_ignore_crash + assert handler.ignore_crash == expected_ignore_crash assert handler.ignore_unexpected_eof == expected_ignore_unexpected_eof @@ -1650,20 +1660,20 @@ def test_qemuhandler_create_command(mocked_instance): 0, False, None, - 'good dummy status', - False, - TwisterStatus.NONE, - None, + TwisterStatus.FAIL, + Handler.FailureType.NONE, + TwisterStatus.FAIL, + "foobar", False ), ( 1, True, None, - 'good dummy status', - False, - TwisterStatus.NONE, - None, + TwisterStatus.FAIL, + Handler.FailureType.NONE, + TwisterStatus.FAIL, + "foobar", False ), ( @@ -1671,7 +1681,7 @@ def test_qemuhandler_create_command(mocked_instance): False, None, TwisterStatus.NONE, - True, + Handler.FailureType.TIMEOUT, TwisterStatus.FAIL, 'Timeout', True @@ -1681,7 +1691,7 @@ def test_qemuhandler_create_command(mocked_instance): False, None, TwisterStatus.NONE, - False, + Handler.FailureType.NONE, TwisterStatus.FAIL, 'Exited with 1', True @@ -1691,7 +1701,7 @@ def test_qemuhandler_create_command(mocked_instance): False, 'preexisting reason', 'good dummy status', - False, + Handler.FailureType.NONE, TwisterStatus.FAIL, 'preexisting reason', True @@ -1700,7 +1710,7 @@ def test_qemuhandler_create_command(mocked_instance): @pytest.mark.parametrize( 'self_returncode, self_ignore_qemu_crash,' \ - ' self_instance_reason, harness_status, is_timeout,' \ + ' self_instance_reason, harness_status, failure_type,' \ ' expected_status, expected_reason, expected_called_missing_case', TESTDATA_21, ids=['not failed', 'qemu ignore', 'timeout', 'bad returncode', 'other fail'] @@ -1711,7 +1721,7 @@ def test_qemuhandler_update_instance_info( self_ignore_qemu_crash, self_instance_reason, harness_status, - is_timeout, + failure_type, expected_status, expected_reason, expected_called_missing_case @@ -1722,16 +1732,16 @@ def test_qemuhandler_update_instance_info( handler = QEMUHandler(mocked_instance, 'build', mock.Mock()) handler.returncode = self_returncode - handler.ignore_qemu_crash = self_ignore_qemu_crash + handler.ignore_crash = self_ignore_qemu_crash - handler._update_instance_info(mocked_harness, is_timeout) + handler._update_instance_info(mocked_harness, failure_type) assert handler.instance.status == expected_status assert handler.instance.reason == expected_reason if expected_called_missing_case: mocked_instance.add_missing_case_status.assert_called_once_with( - TwisterStatus.BLOCK + TwisterStatus.BLOCK, expected_reason ) @@ -1749,7 +1759,7 @@ def test_qemuhandler_thread_get_fifo_names(): (TwisterStatus.FAIL, 'Execution error', TwisterStatus.FAIL, 'Execution error'), (TwisterStatus.FAIL, 'unexpected eof', TwisterStatus.FAIL, 'unexpected eof'), (TwisterStatus.FAIL, 'unexpected byte', TwisterStatus.FAIL, 'unexpected byte'), - (TwisterStatus.NONE, None, TwisterStatus.NONE, 'Unknown'), + (TwisterStatus.NONE, None, TwisterStatus.NONE, 'Unknown Error'), ] @pytest.mark.parametrize( @@ -1765,11 +1775,8 @@ def test_qemuhandler_thread_update_instance_info( expected_reason ): handler = QEMUHandler(mocked_instance, 'build', mock.Mock()) - handler_time = 59 - - QEMUHandler._thread_update_instance_info(handler, handler_time, _status, _reason) - assert handler.instance.execution_time == handler_time + QEMUHandler._thread_update_instance_info(handler, _status, _reason) assert handler.instance.status == expected_status assert handler.instance.reason == expected_reason @@ -1951,7 +1958,6 @@ def mocked_open(filename, *args, **kwargs): mock_thread_update_instance_info.assert_called_once_with( handler, - mock.ANY, expected_status, mock.ANY ) diff --git a/scripts/tests/twister/test_harness.py b/scripts/tests/twister/test_harness.py index edc2a96c8a139..f1da77fa72a66 100644 --- a/scripts/tests/twister/test_harness.py +++ b/scripts/tests/twister/test_harness.py @@ -564,6 +564,7 @@ def test_pytest__generate_parameters_for_hardware(tmp_path, pty_value, hardware_ options = handler.options options.west_flash = "args" + options.flash_command = "flash_command" hardware.probe_id = "123" hardware.product = "product" @@ -597,6 +598,7 @@ def test_pytest__generate_parameters_for_hardware(tmp_path, pty_value, hardware_ assert "--runner-params=--runner-param1" in command assert "--runner-params=runner-param2" in command assert "--west-flash-extra-args=args" in command + assert "--flash-command=flash_command" in command assert "--device-id=123" in command assert "--device-product=product" in command assert "--pre-script=pre_script" in command diff --git a/scripts/tests/twister_blackbox/conftest.py b/scripts/tests/twister_blackbox/conftest.py index 615e2f986b773..82897c4fa1cf3 100644 --- a/scripts/tests/twister_blackbox/conftest.py +++ b/scripts/tests/twister_blackbox/conftest.py @@ -24,7 +24,7 @@ sample_filename_mock = mock.PropertyMock(return_value='test_sample.yaml') -testsuite_filename_mock = mock.PropertyMock(return_value='test_data.yaml') +suite_filename_mock = mock.PropertyMock(return_value='test_data.yaml') sample_filename_mock = mock.PropertyMock(return_value='test_sample.yaml') def pytest_configure(config): diff --git a/scripts/tests/twister_blackbox/test_addon.py b/scripts/tests/twister_blackbox/test_addon.py index bb7fe84b6b88e..2ac6ea947b46f 100644 --- a/scripts/tests/twister_blackbox/test_addon.py +++ b/scripts/tests/twister_blackbox/test_addon.py @@ -17,7 +17,7 @@ import sys # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, suite_filename_mock from twisterlib.testplan import TestPlan @@ -43,7 +43,7 @@ def teardown_class(cls): ], ids=['no sanitiser', 'ubsan'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_enable_ubsan(self, out_path, ubsan_flags, expected_exit_value): test_platforms = ['native_sim'] test_path = os.path.join(TEST_DATA, 'tests', 'san', 'ubsan') @@ -70,7 +70,7 @@ def test_enable_ubsan(self, out_path, ubsan_flags, expected_exit_value): ], ids=['no sanitiser', 'lsan'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_enable_lsan(self, out_path, lsan_flags, expected_exit_value): test_platforms = ['native_sim'] test_path = os.path.join(TEST_DATA, 'tests', 'san', 'lsan') @@ -103,7 +103,7 @@ def test_enable_lsan(self, out_path, lsan_flags, expected_exit_value): 'asan' ] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_enable_asan(self, capfd, out_path, asan_flags, expected_exit_value, expect_asan): test_platforms = ['native_sim'] test_path = os.path.join(TEST_DATA, 'tests', 'san', 'asan') @@ -127,7 +127,7 @@ def test_enable_asan(self, capfd, out_path, asan_flags, expected_exit_value, exp asan_template = r'^==\d+==ERROR:\s+AddressSanitizer:' assert expect_asan == bool(re.search(asan_template, err, re.MULTILINE)) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_extra_test_args(self, capfd, out_path): test_platforms = ['native_sim'] test_path = os.path.join(TEST_DATA, 'tests', 'params', 'dummy') @@ -158,7 +158,7 @@ def test_extra_test_args(self, capfd, out_path): ] assert all([testname in err for testname in expected_test_names]) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_extra_args(self, caplog, out_path): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2') @@ -293,7 +293,7 @@ def refresh_plugin_installed_variable(): assert all([log in caplog.text for log in expected_logs]) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_pytest_args(self, out_path): test_platforms = ['native_sim'] test_path = os.path.join(TEST_DATA, 'tests', 'pytest') @@ -322,7 +322,7 @@ def test_pytest_args(self, out_path): ], ids=['no valgrind', 'valgrind'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_enable_valgrind(self, capfd, out_path, valgrind_flags, expected_exit_value): test_platforms = ['native_sim'] test_path = os.path.join(TEST_DATA, 'tests', 'san', 'val') diff --git a/scripts/tests/twister_blackbox/test_config.py b/scripts/tests/twister_blackbox/test_config.py index 1b34e637ff47b..e392788275e56 100644 --- a/scripts/tests/twister_blackbox/test_config.py +++ b/scripts/tests/twister_blackbox/test_config.py @@ -14,7 +14,7 @@ import json # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan @@ -30,7 +30,7 @@ def setup_class(cls): def teardown_class(cls): pass - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_alt_config_root(self, out_path): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy') @@ -66,7 +66,7 @@ def test_alt_config_root(self, out_path): ], ids=['smoke', 'acceptance'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_level(self, out_path, level, expected_tests): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy') diff --git a/scripts/tests/twister_blackbox/test_coverage.py b/scripts/tests/twister_blackbox/test_coverage.py index c1f85c05057bb..54c96d8a22dcd 100644 --- a/scripts/tests/twister_blackbox/test_coverage.py +++ b/scripts/tests/twister_blackbox/test_coverage.py @@ -14,11 +14,11 @@ import json # pylint: disable=duplicate-code, disable=no-name-in-module -from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock, clear_log_in_test +from conftest import TEST_DATA, ZEPHYR_BASE, suite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestCoverage: TESTDATA_1 = [ ( diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/prj.conf b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/prj.conf index 9467c2926896d..d25c9c7d100a2 100644 --- a/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/prj.conf +++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/prj.conf @@ -1 +1,2 @@ CONFIG_ZTEST=y +CONFIG_ENTROPY_GENERATOR=y diff --git a/scripts/tests/twister_blackbox/test_device.py b/scripts/tests/twister_blackbox/test_device.py index c35daa337e49a..95f9848920251 100644 --- a/scripts/tests/twister_blackbox/test_device.py +++ b/scripts/tests/twister_blackbox/test_device.py @@ -6,7 +6,6 @@ Blackbox tests for twister's command line functions related to test filtering. """ -import importlib from unittest import mock import os import pytest @@ -14,63 +13,35 @@ import re # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan +from twisterlib.twister_main import main as twister_main class TestDevice: - TESTDATA_1 = [ - ( - 1234, - ), - ( - 4321, - ), - ( - 1324, - ) - ] - - @classmethod - def setup_class(cls): - apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') - cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) - cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) - cls.twister_module = importlib.util.module_from_spec(cls.spec) - - @classmethod - def teardown_class(cls): - pass @pytest.mark.parametrize( 'seed', - TESTDATA_1, - ids=[ - 'seed 1234', - 'seed 4321', - 'seed 1324' - ], + [1234, 4321, 1324], ) - - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_seed(self, capfd, out_path, seed): test_platforms = ['native_sim'] path = os.path.join(TEST_DATA, 'tests', 'seed_native_sim') - args = ['--outdir', out_path, '-i', '-T', path, '-vv',] + \ - ['--seed', f'{seed[0]}'] + \ - [val for pair in zip( - ['-p'] * len(test_platforms), test_platforms - ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) + args = [ + '--no-detailed-test-id', '--outdir', out_path, '-i', '-T', path, '-vv', + '--seed', f'{seed}', + *[val for pair in zip(['-p'] * len(test_platforms), test_platforms) for val in pair] + ] + + return_value = twister_main(args) out, err = capfd.readouterr() sys.stdout.write(out) sys.stderr.write(err) - assert str(sys_exit.value) == '1' + assert return_value == 1 - expected_line = r'seed_native_sim.dummy FAILED Failed \(rc=1\) \(native (\d+\.\d+)s/seed: {} \)'.format(seed[0]) - assert re.search(expected_line, err) + expected_line = r'seed_native_sim.dummy\s+FAILED rc=1 \(native (\d+\.\d+)s/seed: {} \)'.format(seed) + assert re.search(expected_line, err), f'Regex not found: r"{expected_line}"' diff --git a/scripts/tests/twister_blackbox/test_disable.py b/scripts/tests/twister_blackbox/test_disable.py index 3cbc7d314289f..48f2ce41d2660 100644 --- a/scripts/tests/twister_blackbox/test_disable.py +++ b/scripts/tests/twister_blackbox/test_disable.py @@ -6,7 +6,6 @@ Blackbox tests for twister's command line functions related to disable features. """ -import importlib import pytest from unittest import mock import os @@ -14,11 +13,12 @@ import re # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan +from twisterlib.twister_main import main as twister_main -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestDisable: TESTDATA_1 = [ ( @@ -41,30 +41,17 @@ class TestDisable: os.path.join(TEST_DATA, 'tests', 'always_warning'), ['qemu_x86'], '--disable-warnings-as-errors', - '0' + 0 ), ( os.path.join(TEST_DATA, 'tests', 'always_warning'), ['qemu_x86'], '-v', - '1' + 1 ), ] - @classmethod - def setup_class(cls): - apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') - cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) - cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) - cls.twister_module = importlib.util.module_from_spec(cls.spec) - - - @classmethod - def teardown_class(cls): - pass - - @pytest.mark.parametrize( 'test_path, test_platforms, flag, expected, expected_none', TESTDATA_1, @@ -82,15 +69,14 @@ def test_disable_suite_name_check(self, capfd, out_path, test_path, test_platfor ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) + + return_value = twister_main(args) out, err = capfd.readouterr() sys.stdout.write(out) sys.stderr.write(err) - assert str(sys_exit.value) == '0' + assert return_value == 0 if expected_none: assert re.search(expected[0], err) is None, f"Not expected string in log: {expected[0]}" assert re.search(expected[1], err) is None, f"Not expected: {expected[1]}" @@ -117,13 +103,12 @@ def test_disable_warnings_as_errors(self, capfd, out_path, test_path, test_platf ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) + + return_value = twister_main(args) out, err = capfd.readouterr() sys.stdout.write(out) sys.stderr.write(err) - assert str(sys_exit.value) == expected_exit_code, \ - f"Twister return not expected ({expected_exit_code}) exit code: ({sys_exit.value})" + assert return_value == expected_exit_code, \ + f"Twister return not expected ({expected_exit_code}) exit code: ({return_value})" diff --git a/scripts/tests/twister_blackbox/test_error.py b/scripts/tests/twister_blackbox/test_error.py index 93d589fefdfce..a15b3b5129cf9 100644 --- a/scripts/tests/twister_blackbox/test_error.py +++ b/scripts/tests/twister_blackbox/test_error.py @@ -14,7 +14,7 @@ import re # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan from twisterlib.error import TwisterRuntimeError @@ -66,13 +66,13 @@ def teardown_class(cls): TESTDATA_1, ids=['valid', 'invalid', 'valid'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_test(self, out_path, testroot, test, expected_exception): test_platforms = ['qemu_x86', 'intel_adl_crb'] args = [] if testroot: args = ['-T', testroot] - args += ['-i', '--outdir', out_path, '--test', test, '-y'] + \ + args += ['--detailed-test-id', '-i', '--outdir', out_path, '--test', test, '-y'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] @@ -94,11 +94,11 @@ def test_test(self, out_path, testroot, test, expected_exception): ], ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_overflow_as_errors(self, capfd, out_path, switch, expected): path = os.path.join(TEST_DATA, 'tests', 'qemu_overflow') test_platforms = ['qemu_x86'] - args = ['--outdir', out_path, '-T', path, '-vv'] + \ + args = ['--detailed-test-id', '--outdir', out_path, '-T', path, '-vv'] + \ ['--build-only'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms diff --git a/scripts/tests/twister_blackbox/test_filter.py b/scripts/tests/twister_blackbox/test_filter.py index c65dda1604c32..acc3910547783 100644 --- a/scripts/tests/twister_blackbox/test_filter.py +++ b/scripts/tests/twister_blackbox/test_filter.py @@ -15,7 +15,7 @@ import re # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan @@ -95,7 +95,7 @@ def teardown_class(cls): ], ids=['no device, no cpp', 'no agnostic'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_exclude_tag(self, out_path, tags, expected_test_count): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy') @@ -123,7 +123,7 @@ def test_exclude_tag(self, out_path, tags, expected_test_count): assert str(sys_exit.value) == '0' - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_enable_slow(self, out_path): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic') @@ -151,7 +151,7 @@ def test_enable_slow(self, out_path): assert len(filtered_j) == 6 - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_enable_slow_only(self, out_path): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic') @@ -189,7 +189,7 @@ def test_enable_slow_only(self, out_path): ], ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_arch(self, capfd, out_path, arch, expected): path = os.path.join(TEST_DATA, 'tests', 'no_filter') test_platforms = ['qemu_x86', 'hsdk', 'intel_adl_crb', 'it8xxx2_evb'] @@ -223,7 +223,7 @@ def test_arch(self, capfd, out_path, arch, expected): ], ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_vendor(self, capfd, out_path, vendor, expected): path = os.path.join(TEST_DATA, 'tests', 'no_filter') test_platforms = ['qemu_x86', 'hsdk', 'intel_adl_crb', 'it8xxx2_evb'] @@ -254,7 +254,7 @@ def test_vendor(self, capfd, out_path, vendor, expected): ], ids=['ignore_platform_key', 'without ignore_platform_key'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_ignore_platform_key(self, out_path, flag, expected_test_count): test_platforms = ['qemu_x86', 'qemu_x86_64'] path = os.path.join(TEST_DATA, 'tests', 'platform_key') diff --git a/scripts/tests/twister_blackbox/test_footprint.py b/scripts/tests/twister_blackbox/test_footprint.py index b9e072a266617..863a139770352 100644 --- a/scripts/tests/twister_blackbox/test_footprint.py +++ b/scripts/tests/twister_blackbox/test_footprint.py @@ -15,12 +15,12 @@ import re # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock, clear_log_in_test from twisterlib.statuses import TwisterStatus from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestFootprint: # Log printed when entering delta calculations FOOTPRINT_LOG = 'running footprint_reports' diff --git a/scripts/tests/twister_blackbox/test_hardwaremap.py b/scripts/tests/twister_blackbox/test_hardwaremap.py index ce3493415a9dc..01bab62313e01 100644 --- a/scripts/tests/twister_blackbox/test_hardwaremap.py +++ b/scripts/tests/twister_blackbox/test_hardwaremap.py @@ -12,12 +12,12 @@ import sys # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, testsuite_filename_mock, clear_log_in_test +from conftest import ZEPHYR_BASE, suite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/twister/twisterlib")) -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestHardwaremap: TESTDATA_1 = [ ( diff --git a/scripts/tests/twister_blackbox/test_outfile.py b/scripts/tests/twister_blackbox/test_outfile.py index bdaa5d3291d85..8046db3b755e3 100644 --- a/scripts/tests/twister_blackbox/test_outfile.py +++ b/scripts/tests/twister_blackbox/test_outfile.py @@ -16,11 +16,11 @@ import tarfile # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, suite_filename_mock from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) @mock.patch.object(TestPlan, 'SAMPLE_FILENAME', sample_filename_mock) class TestOutfile: @classmethod @@ -207,7 +207,7 @@ def test_package_artifacts(self, out_path): path = os.path.join(TEST_DATA, 'samples', 'hello_world') package_name = 'PACKAGE' package_path = os.path.join(out_path, package_name) - args = ['-i', '--outdir', out_path, '-T', path] + \ + args = ['--detailed-test-id','-i', '--outdir', out_path, '-T', path] + \ ['--package-artifacts', package_path] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms @@ -242,7 +242,7 @@ def test_package_artifacts(self, out_path): for file_name in file_names: shutil.move(os.path.join(out_path, os.path.basename(out_path), file_name), out_path) - args = ['-i', '--outdir', out_path, '-T', path] + \ + args = ['--detailed-test-id', '-i', '--outdir', out_path, '-T', path] + \ ['--test-only'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms diff --git a/scripts/tests/twister_blackbox/test_output.py b/scripts/tests/twister_blackbox/test_output.py index c6a77020638ba..6535a342d749e 100644 --- a/scripts/tests/twister_blackbox/test_output.py +++ b/scripts/tests/twister_blackbox/test_output.py @@ -15,11 +15,11 @@ import json # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestOutput: TESTDATA_1 = [ ([]), diff --git a/scripts/tests/twister_blackbox/test_platform.py b/scripts/tests/twister_blackbox/test_platform.py index 33239d5fcc02e..d06598b6aacd8 100644 --- a/scripts/tests/twister_blackbox/test_platform.py +++ b/scripts/tests/twister_blackbox/test_platform.py @@ -15,11 +15,11 @@ import json # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestPlatform: TESTDATA_1 = [ ( diff --git a/scripts/tests/twister_blackbox/test_printouts.py b/scripts/tests/twister_blackbox/test_printouts.py index f383fe09744c2..cf35c4683bdf9 100644 --- a/scripts/tests/twister_blackbox/test_printouts.py +++ b/scripts/tests/twister_blackbox/test_printouts.py @@ -19,12 +19,12 @@ ZEPHYR_BASE, clear_log_in_test, sample_filename_mock, - testsuite_filename_mock + suite_filename_mock ) from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestPrintOuts: TESTDATA_1 = [ ( diff --git a/scripts/tests/twister_blackbox/test_quarantine.py b/scripts/tests/twister_blackbox/test_quarantine.py index c2b6a183266c6..b01688baeaa83 100644 --- a/scripts/tests/twister_blackbox/test_quarantine.py +++ b/scripts/tests/twister_blackbox/test_quarantine.py @@ -16,7 +16,7 @@ # pylint: disable=duplicate-code # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan @@ -32,7 +32,7 @@ def setup_class(cls): def teardown_class(cls): pass - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_quarantine_verify(self, out_path): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy') @@ -78,9 +78,9 @@ def test_quarantine_verify(self, out_path): 'quarantine', ], ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_quarantine_list(self, capfd, out_path, test_path, test_platforms, quarantine_directory): - args = ['--outdir', out_path, '-T', test_path] +\ + args = ['--detailed-test-id', '--outdir', out_path, '-T', test_path] +\ ['--quarantine-list', quarantine_directory] + \ ['-vv', '-ll', 'DEBUG'] + \ [val for pair in zip( @@ -95,27 +95,22 @@ def test_quarantine_list(self, capfd, out_path, test_path, test_platforms, quara sys.stdout.write(out) sys.stderr.write(err) - board1_match1 = re.search('agnostic/group2/dummy.agnostic.group2 SKIPPED: Quarantine: test ' - 'intel_adl_crb', err) + board1_match1 = re.search('agnostic/group2/dummy.agnostic.group2 SKIPPED: Quarantined', + err) board1_match2 = re.search( - 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantine: test ' - 'intel_adl_crb', + 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantined', err) qemu_64_match = re.search( - 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantine: test ' - 'qemu_x86_64', + 'agnostic/group1/subgroup2/dummy.agnostic.group1.subgroup2 SKIPPED: Quarantined', err) all_platforms_match = re.search( - 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' - 'all platforms', + 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantined', err) all_platforms_match2 = re.search( - 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' - 'all platforms', + 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantined', err) all_platforms_match3 = re.search( - 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantine: test ' - 'all platforms', + 'agnostic/group1/subgroup1/dummy.agnostic.group1.subgroup1 SKIPPED: Quarantined', err) assert board1_match1 and board1_match2, 'platform quarantine not working properly' diff --git a/scripts/tests/twister_blackbox/test_report.py b/scripts/tests/twister_blackbox/test_report.py index 95f14d9b5ca26..c1e5d406a27f4 100644 --- a/scripts/tests/twister_blackbox/test_report.py +++ b/scripts/tests/twister_blackbox/test_report.py @@ -17,12 +17,12 @@ import xml.etree.ElementTree as etree # pylint: disable=no-name-in-module -from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock, clear_log_in_test +from conftest import TEST_DATA, ZEPHYR_BASE, suite_filename_mock, clear_log_in_test from twisterlib.statuses import TwisterStatus from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestReport: TESTDATA_1 = [ ( diff --git a/scripts/tests/twister_blackbox/test_runner.py b/scripts/tests/twister_blackbox/test_runner.py index 09286663475be..1d4dafee29d8c 100644 --- a/scripts/tests/twister_blackbox/test_runner.py +++ b/scripts/tests/twister_blackbox/test_runner.py @@ -16,11 +16,11 @@ import time # pylint: disable=no-name-in-module -from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock, clear_log_in_test +from conftest import TEST_DATA, ZEPHYR_BASE, suite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan -@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) +@mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) class TestRunner: TESTDATA_1 = [ ( @@ -573,7 +573,7 @@ def test_timeout_multiplier(self, capfd, out_path, test_path, test_platforms, ti ], ) def test_tag(self, capfd, out_path, test_path, test_platforms, tags, expected): - args = ['--outdir', out_path, '-T', test_path, '-vv', '-ll', 'DEBUG'] + \ + args = ['--detailed-test-id', '--outdir', out_path, '-T', test_path, '-vv', '-ll', 'DEBUG'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] + \ diff --git a/scripts/tests/twister_blackbox/test_shuffle.py b/scripts/tests/twister_blackbox/test_shuffle.py index ba19faf64b6e4..53454d41ef5fd 100644 --- a/scripts/tests/twister_blackbox/test_shuffle.py +++ b/scripts/tests/twister_blackbox/test_shuffle.py @@ -14,7 +14,7 @@ import json # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import ZEPHYR_BASE, TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan @@ -49,7 +49,7 @@ def teardown_class(cls): 'first third, 321', 'middle third, 321', 'last third, 321' ] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_shuffle_tests(self, out_path, seed, ratio, expected_order): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy') diff --git a/scripts/tests/twister_blackbox/test_testlist.py b/scripts/tests/twister_blackbox/test_testlist.py index 410c417e14cda..95cf675073123 100644 --- a/scripts/tests/twister_blackbox/test_testlist.py +++ b/scripts/tests/twister_blackbox/test_testlist.py @@ -6,31 +6,19 @@ Blackbox tests for twister's command line functions related to saving and loading a testlist. """ -import importlib from unittest import mock import os -import pytest -import sys import json # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock, clear_log_in_test +from conftest import TEST_DATA, suite_filename_mock, clear_log_in_test from twisterlib.testplan import TestPlan +from twisterlib.twister_main import main as twister_main class TestTestlist: - @classmethod - def setup_class(cls): - apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') - cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) - cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) - cls.twister_module = importlib.util.module_from_spec(cls.spec) - @classmethod - def teardown_class(cls): - pass - - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_save_tests(self, out_path): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic') @@ -42,11 +30,7 @@ def test_save_tests(self, out_path): ) for val in pair] # Save agnostics tests - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - assert str(sys_exit.value) == '0' + assert twister_main(args) == 0 clear_log_in_test() @@ -58,11 +42,7 @@ def test_save_tests(self, out_path): ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - assert str(sys_exit.value) == '0' + assert twister_main(args) == 0 with open(os.path.join(out_path, 'testplan.json')) as f: j = json.load(f) diff --git a/scripts/tests/twister_blackbox/test_testplan.py b/scripts/tests/twister_blackbox/test_testplan.py index 701acf94ddf21..442e91bfcf3af 100644 --- a/scripts/tests/twister_blackbox/test_testplan.py +++ b/scripts/tests/twister_blackbox/test_testplan.py @@ -6,22 +6,21 @@ Blackbox tests for twister's command line functions - those requiring testplan.json """ -import importlib from unittest import mock import os import pytest -import sys import json # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, testsuite_filename_mock +from conftest import TEST_DATA, suite_filename_mock from twisterlib.testplan import TestPlan from twisterlib.error import TwisterRuntimeError +from twisterlib.twister_main import main as twister_main class TestTestPlan: TESTDATA_1 = [ - ('dummy.agnostic.group2.a2_tests.assert1', SystemExit, 4), + ('dummy.agnostic.group2.a2_tests.assert1', None, 4), ( os.path.join('scripts', 'tests', 'twister_blackbox', 'test_data', 'tests', 'dummy', 'agnostic', 'group1', 'subgroup1', @@ -39,56 +38,43 @@ class TestTestPlan: (False, 7), ] - @classmethod - def setup_class(cls): - apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') - cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) - cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) - cls.twister_module = importlib.util.module_from_spec(cls.spec) - - @classmethod - def teardown_class(cls): - pass - @pytest.mark.parametrize( 'test, expected_exception, expected_subtest_count', TESTDATA_1, ids=['valid', 'not found'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_subtest(self, out_path, test, expected_exception, expected_subtest_count): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy') - args = ['-i', '--outdir', out_path, '-T', path, '--sub-test', test, '-y'] + \ + args = ['--detailed-test-id', + '-i', '--outdir', out_path, '-T', path, '--sub-test', test, '-y'] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(expected_exception) as exc: - self.loader.exec_module(self.twister_module) - - if expected_exception != SystemExit: - assert True - return - - with open(os.path.join(out_path, 'testplan.json')) as f: - j = json.load(f) - filtered_j = [ - (ts['platform'], ts['name'], tc['identifier']) \ - for ts in j['testsuites'] \ - for tc in ts['testcases'] if 'reason' not in tc - ] - - assert str(exc.value) == '0' - assert len(filtered_j) == expected_subtest_count + if expected_exception: + with pytest.raises(expected_exception): + twister_main(args) + else: + return_value = twister_main(args) + with open(os.path.join(out_path, 'testplan.json')) as f: + j = json.load(f) + filtered_j = [ + (ts['platform'], ts['name'], tc['identifier']) \ + for ts in j['testsuites'] \ + for tc in ts['testcases'] if 'reason' not in tc + ] + + assert return_value == 0 + assert len(filtered_j) == expected_subtest_count @pytest.mark.parametrize( 'filter, expected_count', TESTDATA_2, ids=['buildable', 'runnable'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_filter(self, out_path, filter, expected_count): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy') @@ -97,11 +83,8 @@ def test_filter(self, out_path, filter, expected_count): ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as exc: - self.loader.exec_module(self.twister_module) + assert twister_main(args) == 0 - assert str(exc.value) == '0' import pprint with open(os.path.join(out_path, 'testplan.json')) as f: j = json.load(f) @@ -120,7 +103,7 @@ def test_filter(self, out_path, filter, expected_count): TESTDATA_3, ids=['integration', 'no integration'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) @mock.patch.object(TestPlan, 'SAMPLE_FILENAME', '') def test_integration(self, out_path, integration, expected_count): test_platforms = ['qemu_x86', 'intel_adl_crb'] @@ -131,11 +114,7 @@ def test_integration(self, out_path, integration, expected_count): ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as exc: - self.loader.exec_module(self.twister_module) - - assert str(exc.value) == '0' + assert twister_main(args) == 0 with open(os.path.join(out_path, 'testplan.json')) as f: j = json.load(f) diff --git a/scripts/tests/twister_blackbox/test_tooling.py b/scripts/tests/twister_blackbox/test_tooling.py index d844ec824de0b..e372bdf9b2366 100644 --- a/scripts/tests/twister_blackbox/test_tooling.py +++ b/scripts/tests/twister_blackbox/test_tooling.py @@ -7,7 +7,6 @@ """ # pylint: disable=duplicate-code -import importlib from unittest import mock import os import pytest @@ -15,29 +14,20 @@ import json # pylint: disable=no-name-in-module -from conftest import ZEPHYR_BASE, TEST_DATA, sample_filename_mock, testsuite_filename_mock +from conftest import TEST_DATA, sample_filename_mock, suite_filename_mock from twisterlib.statuses import TwisterStatus from twisterlib.testplan import TestPlan +from twisterlib.twister_main import main as twister_main class TestTooling: - @classmethod - def setup_class(cls): - apath = os.path.join(ZEPHYR_BASE, 'scripts', 'twister') - cls.loader = importlib.machinery.SourceFileLoader('__main__', apath) - cls.spec = importlib.util.spec_from_loader(cls.loader.name, cls.loader) - cls.twister_module = importlib.util.module_from_spec(cls.spec) - - @classmethod - def teardown_class(cls): - pass @pytest.mark.parametrize( 'jobs', ['1', '2'], ids=['single job', 'two jobs'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_jobs(self, out_path, jobs): test_platforms = ['qemu_x86', 'intel_adl_crb'] path = os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2') @@ -47,15 +37,14 @@ def test_jobs(self, out_path, jobs): ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) + + return_value = twister_main(args) with open(os.path.join(out_path, 'twister.log')) as f: log = f.read() assert f'JOBS: {jobs}' in log - assert str(sys_exit.value) == '0' + assert return_value == 0 @mock.patch.object(TestPlan, 'SAMPLE_FILENAME', sample_filename_mock) def test_force_toolchain(self, out_path): @@ -69,11 +58,7 @@ def test_force_toolchain(self, out_path): ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) - - assert str(sys_exit.value) == '0' + return_value = twister_main(args) with open(os.path.join(out_path, 'testplan.json')) as f: j = json.load(f) @@ -87,6 +72,8 @@ def test_force_toolchain(self, out_path): assert len(filtered_j) == 1 assert filtered_j[0][3] != TwisterStatus.FILTER + assert return_value == 0 + @pytest.mark.parametrize( 'test_path, test_platforms', [ @@ -103,19 +90,17 @@ def test_force_toolchain(self, out_path): 'flag', ['--ninja', '-N'] ) - @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', testsuite_filename_mock) + @mock.patch.object(TestPlan, 'TESTSUITE_FILENAME', suite_filename_mock) def test_ninja(self, capfd, out_path, test_path, test_platforms, flag): args = ['--outdir', out_path, '-T', test_path, flag] + \ [val for pair in zip( ['-p'] * len(test_platforms), test_platforms ) for val in pair] - with mock.patch.object(sys, 'argv', [sys.argv[0]] + args), \ - pytest.raises(SystemExit) as sys_exit: - self.loader.exec_module(self.twister_module) + return_value = twister_main(args) out, err = capfd.readouterr() sys.stdout.write(out) sys.stderr.write(err) - assert str(sys_exit.value) == '0' + assert return_value == 0 diff --git a/scripts/twister b/scripts/twister index db692ceb1cdb8..b19cde98b4f73 100755 --- a/scripts/twister +++ b/scripts/twister @@ -186,7 +186,6 @@ import os import sys from pathlib import Path - ZEPHYR_BASE = os.getenv("ZEPHYR_BASE") if not ZEPHYR_BASE: # This file has been zephyr/scripts/twister for years, @@ -203,22 +202,7 @@ if not ZEPHYR_BASE: sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/twister/")) sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/build_helpers")) -from twisterlib.environment import add_parse_arguments, parse_arguments, python_version_guard -from twisterlib.twister_main import main - +from twisterlib.twister_main import main # noqa: E402 if __name__ == "__main__": - ret = 0 - try: - python_version_guard() - - parser = add_parse_arguments() - options = parse_arguments(parser, sys.argv[1:]) - default_options = parse_arguments(parser, [], on_init=False) - ret = main(options, default_options) - finally: - if (os.name != "nt") and os.isatty(1): - # (OS is not Windows) and (stdout is interactive) - os.system("stty sane <&1") - - sys.exit(ret) + sys.exit(main()) diff --git a/scripts/valgrind.supp b/scripts/valgrind.supp index 330ec51fefd73..46703150052e7 100644 --- a/scripts/valgrind.supp +++ b/scripts/valgrind.supp @@ -12,7 +12,8 @@ Memcheck:Leak match-leak-kinds: reachable,possible ... - fun:posix_new_thread + fun:nct_new_thread + ... fun:arch_new_thread } { diff --git a/scripts/west_commands/blobs.py b/scripts/west_commands/blobs.py index f0e7f1968dc1d..7723a45e555de 100644 --- a/scripts/west_commands/blobs.py +++ b/scripts/west_commands/blobs.py @@ -4,6 +4,7 @@ import argparse import os +import re import sys import textwrap from pathlib import Path @@ -78,6 +79,13 @@ def do_add_parser(self, parser_adder): see FORMAT STRINGS below''') group = parser.add_argument_group('west blobs fetch options') + group.add_argument( + '-l', + '--allow-regex', + help='''Regex pattern to apply to the blob local path. + Only local paths matching this regex will be fetched. + Note that local paths are relative to the module directory''', + ) group.add_argument('-a', '--auto-accept', action='store_true', help='''auto accept license if the fetching needs click-through''') @@ -127,7 +135,7 @@ def fetch_blob(self, url, path): # Compare the checksum of a file we've just downloaded # to the digest in blob metadata, warn user if they differ. def verify_blob(self, blob) -> bool: - self.dbg('Verifying blob {module}: {abspath}'.format(**blob)) + self.dbg(f"Verifying blob {blob['module']}: {blob['abspath']}") status = zephyr_module.get_blob_status(blob['abspath'], blob['sha256']) if status == zephyr_module.BLOB_OUTDATED: @@ -154,9 +162,17 @@ def fetch(self, args): blobs = self.get_blobs(args) for blob in blobs: if blob['status'] == zephyr_module.BLOB_PRESENT: - self.dbg('Blob {module}: {abspath} is up to date'.format(**blob)) + self.dbg(f"Blob {blob['module']}: {blob['abspath']} is up to date") continue - self.inf('Fetching blob {module}: {abspath}'.format(**blob)) + + # if args.allow_regex is set, use it to filter the blob by path + if args.allow_regex and not re.match(args.allow_regex, blob['path']): + self.dbg( + f"Blob {blob['module']}: {blob['abspath']} does not match regex " + f"'{args.allow_regex}', skipping" + ) + continue + self.inf(f"Fetching blob {blob['module']}: {blob['abspath']}") if blob['click-through'] and not args.auto_accept: while True: @@ -196,13 +212,13 @@ def clean(self, args): blobs = self.get_blobs(args) for blob in blobs: if blob['status'] == zephyr_module.BLOB_NOT_PRESENT: - self.dbg('Blob {module}: {abspath} not in filesystem'.format(**blob)) + self.dbg(f"Blob {blob['module']}: {blob['abspath']} not in filesystem") continue - self.inf('Deleting blob {module}: {status} {abspath}'.format(**blob)) + self.inf(f"Deleting blob {blob['module']}: {blob['status']} {blob['abspath']}") blob['abspath'].unlink() def do_run(self, args, _): - self.dbg(f'subcmd: \'{args.subcmd[0]}\' modules: {args.modules}') + self.dbg(f"subcmd: '{args.subcmd[0]}' modules: {args.modules}") subcmd = getattr(self, args.subcmd[0]) diff --git a/scripts/west_commands/build.py b/scripts/west_commands/build.py index 8cc3f69516948..fb3894944cd8e 100644 --- a/scripts/west_commands/build.py +++ b/scripts/west_commands/build.py @@ -193,21 +193,6 @@ def do_run(self, args, remainder): # Store legacy -s option locally source_dir = self.args.source_dir self._parse_remainder(remainder) - board, origin = self._find_board() - # Parse testcase.yaml or sample.yaml files for additional options. - if self.args.test_item: - # we get path + testitem - item = os.path.basename(self.args.test_item) - if self.args.source_dir: - test_path = self.args.source_dir - else: - test_path = os.path.dirname(self.args.test_item) - if test_path and os.path.exists(test_path): - self.args.source_dir = test_path - if not self._parse_test_item(item, board): - self.die("No test metadata found") - else: - self.die("test item path does not exist") if source_dir: if self.args.source_dir: @@ -264,6 +249,23 @@ def do_run(self, args, remainder): except Exception as e: self.wrn(f'Failed to create info file: {build_info_file},', e) + board, origin = self._find_board() + + # Parse testcase.yaml or sample.yaml files for additional options. + if self.args.test_item: + # we get path + testitem + item = os.path.basename(self.args.test_item) + if self.args.source_dir: + test_path = self.args.source_dir + else: + test_path = os.path.dirname(self.args.test_item) + if test_path and os.path.exists(test_path): + self.args.source_dir = test_path + if not self._parse_test_item(item, board): + self.die("No test metadata found") + else: + self.die("test item path does not exist") + self._run_cmake(board, origin, self.args.cmake_opts) if args.cmake_only: return diff --git a/scripts/west_commands/runners/nrf_common.py b/scripts/west_commands/runners/nrf_common.py index a7401084ef31e..afa4665d8f473 100644 --- a/scripts/west_commands/runners/nrf_common.py +++ b/scripts/west_commands/runners/nrf_common.py @@ -7,7 +7,6 @@ import abc import contextlib -import functools import os import shlex import subprocess @@ -16,10 +15,7 @@ from pathlib import Path from re import escape, fullmatch -from zephyr_ext_common import ZEPHYR_BASE - sys.path.append(os.fspath(Path(__file__).parent.parent.parent)) -import zephyr_module from runners.core import RunnerCaps, ZephyrBinaryRunner @@ -52,29 +48,6 @@ }, } -# Relative to the root of the hal_nordic module -SUIT_STARTER_PATH = Path('zephyr/blobs/suit/bin/suit_manifest_starter.hex') - -@functools.cache -def _get_suit_starter(): - path = None - modules = zephyr_module.parse_modules(ZEPHYR_BASE) - for m in modules: - if 'hal_nordic' in m.meta.get('name'): - path = Path(m.project) - break - - if not path: - raise RuntimeError("hal_nordic project missing in the manifest") - - suit_starter = path / SUIT_STARTER_PATH - if not suit_starter.exists(): - raise RuntimeError("Unable to find suit manifest starter file, " - "please make sure to run \'west blobs fetch " - "hal_nordic\'") - - return str(suit_starter.resolve()) - class NrfBinaryRunner(ZephyrBinaryRunner): '''Runner front-end base class for nrf tools.''' @@ -95,9 +68,6 @@ def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False, self.force = force self.recover = bool(recover) - # Only applicable for nrfutil - self.suit_starter = False - self.tool_opt = [] if tool_opt is not None: for opts in [shlex.split(opt) for opt in tool_opt]: @@ -384,75 +354,6 @@ def program_hex(self): self.exec_op('erase', core='Application', kind='all') self.exec_op('erase', core='Network', kind='all') - # Manage SUIT artifacts. - # This logic should be executed only once per build. - # Use sysbuild board qualifiers to select the context, - # with which the artifacts will be programmed. - if self.build_conf.get('CONFIG_BOARD_QUALIFIERS') == self.sysbuild_conf.get( - 'SB_CONFIG_BOARD_QUALIFIERS' - ): - mpi_hex_dir = Path(os.path.join(self.cfg.build_dir, 'zephyr')) - - # Handle Manifest Provisioning Information - if self.sysbuild_conf.getboolean('SB_CONFIG_SUIT_MPI_GENERATE'): - app_mpi_hex_file = os.fspath( - mpi_hex_dir / self.sysbuild_conf.get('SB_CONFIG_SUIT_MPI_APP_AREA_PATH')) - rad_mpi_hex_file = os.fspath( - mpi_hex_dir / self.sysbuild_conf.get('SB_CONFIG_SUIT_MPI_RAD_AREA_PATH') - ) - if os.path.exists(app_mpi_hex_file): - self.op_program( - app_mpi_hex_file, - 'ERASE_NONE', - None, - defer=True, - core='Application', - ) - if os.path.exists(rad_mpi_hex_file): - self.op_program( - rad_mpi_hex_file, - 'ERASE_NONE', - None, - defer=True, - core='Network', - ) - - # Handle SUIT root manifest if application manifests are not used. - # If an application firmware is built, the root envelope is merged - # with other application manifests as well as the output HEX file. - if core != 'Application' and self.sysbuild_conf.get('SB_CONFIG_SUIT_ENVELOPE'): - app_root_envelope_hex_file = os.fspath( - mpi_hex_dir / 'suit_installed_envelopes_application_merged.hex' - ) - if os.path.exists(app_root_envelope_hex_file): - self.op_program( - app_root_envelope_hex_file, - 'ERASE_NONE', - None, - defer=True, - core='Application', - ) - - if self.build_conf.getboolean("CONFIG_NRF_HALTIUM_GENERATE_UICR"): - zephyr_build_dir = Path(self.cfg.build_dir) / 'zephyr' - - self.op_program( - str(zephyr_build_dir / 'uicr.hex'), - 'ERASE_NONE', - None, - defer=True, - core='Application', - ) - - if self.build_conf.getboolean("CONFIG_NRF_HALTIUM_UICR_PERIPHCONF"): - self.op_program( - str(zephyr_build_dir / 'periphconf.hex'), - 'ERASE_NONE', - None, - defer=True, - core='Application', - ) - if not self.erase and regtool_generated_uicr: self.exec_op('erase', core=core, kind='uicr') else: @@ -518,18 +419,6 @@ def reset_target(self): def do_require(self): ''' Ensure the tool is installed ''' - def _check_suit_starter(self, op): - op = op['operation'] - if op['type'] not in ('erase', 'recover', 'program'): - return None - if op['type'] == 'program' and op['options']['chip_erase_mode'] != "ERASE_UICR": - return None - - file = _get_suit_starter() - self.logger.debug(f'suit starter: {file}') - - return file - def op_program(self, hex_file, erase, ext_mem_erase, defer=False, core=None): args = self._op_program(hex_file, erase, ext_mem_erase) self.exec_op('program', defer, core, **args) @@ -556,12 +445,6 @@ def _exec_op(op, defer=False, core=None, **kwargs): return op _op = _exec_op(op, defer, core, **kwargs) - # Check if the suit manifest starter needs programming - if self.suit_starter and self.family == 'nrf54h': - file = self._check_suit_starter(_op) - if file: - args = self._op_program(file, 'ERASE_NONE', None) - _exec_op('program', defer, core, **args) @abc.abstractmethod def do_exec_op(self, op, force=False): diff --git a/scripts/west_commands/runners/nrfutil.py b/scripts/west_commands/runners/nrfutil.py index f11d2a7ad1334..0490df29ca174 100644 --- a/scripts/west_commands/runners/nrfutil.py +++ b/scripts/west_commands/runners/nrfutil.py @@ -18,14 +18,13 @@ class NrfUtilBinaryRunner(NrfBinaryRunner): def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False, erase_mode=None, ext_erase_mode=None, reset=True, tool_opt=None, - force=False, recover=False, suit_starter=False, + force=False, recover=False, ext_mem_config_file=None): super().__init__(cfg, family, softreset, pinreset, dev_id, erase, erase_mode, ext_erase_mode, reset, tool_opt, force, recover) - self.suit_starter = suit_starter self.ext_mem_config_file = ext_mem_config_file self._ops = [] @@ -56,15 +55,11 @@ def do_create(cls, cfg, args): ext_erase_mode=args.ext_erase_mode, reset=args.reset, tool_opt=args.tool_opt, force=args.force, recover=args.recover, - suit_starter=args.suit_manifest_starter, ext_mem_config_file=args.ext_mem_config_file) @classmethod def do_add_parser(cls, parser): super().do_add_parser(parser) - parser.add_argument('--suit-manifest-starter', required=False, - action='store_true', - help='Use the SUIT manifest starter file') parser.add_argument('--ext-mem-config-file', required=False, dest='ext_mem_config_file', help='path to an JSON file with external memory configuration') diff --git a/scripts/west_commands/runners/nxp_s32dbg.py b/scripts/west_commands/runners/nxp_s32dbg.py index d8cee73fafecd..8568b0923660a 100644 --- a/scripts/west_commands/runners/nxp_s32dbg.py +++ b/scripts/west_commands/runners/nxp_s32dbg.py @@ -128,7 +128,7 @@ def find_usb_probes() -> list[str]: """Return a list of debug probe serial numbers connected via USB to this host.""" # use system's native commands to enumerate and retrieve the USB serial ID # to avoid bloating this runner with third-party dependencies that often - # require priviledged permissions to access the device info + # require privileged permissions to access the device info macaddr_pattern = r'(?:[0-9a-f]{2}[:]){5}[0-9a-f]{2}' if platform.system() == 'Windows': cmd = 'pnputil /enum-devices /connected' diff --git a/scripts/west_commands/runners/rfp.py b/scripts/west_commands/runners/rfp.py index 0e885b9805b58..940f24adbf9f6 100644 --- a/scripts/west_commands/runners/rfp.py +++ b/scripts/west_commands/runners/rfp.py @@ -12,7 +12,7 @@ from runners.core import RunnerCaps, ZephyrBinaryRunner -if platform.system() == 'Darwin' or 'Windows': +if platform.system() in {'Darwin', 'Windows'}: DEFAULT_RFP_PORT = None else: DEFAULT_RFP_PORT = '/dev/ttyACM0' @@ -46,6 +46,7 @@ def __init__( port=DEFAULT_RFP_PORT, tool=None, interface=None, + rpd_file=None, speed=None, ): super().__init__(cfg) @@ -57,6 +58,7 @@ def __init__( self.tool = tool self.interface = interface self.device = device + self.rpd_file = rpd_file self.speed = speed @classmethod @@ -88,6 +90,10 @@ def do_add_parser(cls, parser): '--interface', help='selects the communications interface (uart, swd)', ) + parser.add_argument( + '--rpd-file', + help='path to renesas partition data zephyr.rpd', + ) parser.add_argument('--device', help='Specify the device type to pass to rfp-cli') parser.add_argument('--verify', action='store_true', help='if given, verify after flash') parser.add_argument('--speed', help='Specify the serial port speed') @@ -101,6 +107,7 @@ def do_create(cls, cfg, args): port=args.port, tool=args.tool, interface=args.interface, + rpd_file=args.rpd_file, erase=args.erase, speed=args.speed, verify=args.verify, @@ -126,6 +133,9 @@ def default_rfp(): def do_run(self, command, **kwargs): if command == 'flash': + if self.rpd_file is not None: + self.do_partition(**kwargs) + self.do_flash(**kwargs) else: self.logger.error("Unsuppported command") @@ -165,3 +175,21 @@ def do_flash(self, **kwargs): cmd = self.rfp_cmd + connection + device + load_image self.check_call(cmd) + + def do_partition(self): + self.require(self.rfp_cmd[0]) + + rpd_path = self.rpd_file + + self.logger.info(f'Partition file: {rpd_path}') + + device = ['-device', self.device] + + connection = ['-tool', self.tool] + + flash_option = ['-fo'] + flash_option += ['boundary-file', rpd_path] + flash_option += ['-p'] + + cmd = self.rfp_cmd + device + connection + flash_option + self.check_call(cmd) diff --git a/scripts/west_commands/tests/test_rfp.py b/scripts/west_commands/tests/test_rfp.py index 9d27a5b1a8c27..3a2dd38147c4a 100644 --- a/scripts/west_commands/tests/test_rfp.py +++ b/scripts/west_commands/tests/test_rfp.py @@ -11,8 +11,11 @@ TEST_RFP_PORT = 'test-rfp-serial' TEST_RFP_PORT_SPEED = '115200' +TEST_RFP_TOOL = 'jlink' +TEST_RFP_INTERFACE = 'swd' TEST_RFP_DEVICE = 'RA' TEST_RFP_USR_LOCAL_RFP_CLI = '/usr/local/bin/rfp-cli' +TEST_RFP_RPD_FILE = 'test-zephyr.rpd' EXPECTED_COMMANDS = [ [ @@ -93,6 +96,37 @@ ], ] +EXPECTED_COMMANDS_WITH_JLINK_HARDWARE = [ + [ + TEST_RFP_USR_LOCAL_RFP_CLI, + '-tool', + TEST_RFP_TOOL, + '-interface', + TEST_RFP_INTERFACE, + '-device', + TEST_RFP_DEVICE, + '-run', + '-erase', + '-p', + '-file', + RC_KERNEL_HEX, + ], +] + +EXPECTED_COMMANDS_WITH_PARTITION_DATA = [ + [ + TEST_RFP_USR_LOCAL_RFP_CLI, + '-device', + TEST_RFP_DEVICE, + '-tool', + TEST_RFP_TOOL, + '-fo', + 'boundary-file', + TEST_RFP_RPD_FILE, + '-p', + ], +] + def require_patch(program): assert program in ['rfp', 'rfp-cli', TEST_RFP_USR_LOCAL_RFP_CLI] @@ -102,7 +136,7 @@ def require_patch(program): def os_path_isfile_patch(filename): - if filename == RC_KERNEL_HEX: + if filename == RC_KERNEL_HEX or TEST_RFP_RPD_FILE: return True return os_path_isfile(filename) @@ -260,3 +294,74 @@ def test_rfp_create_with_rfp_cli(dr, cc, req, runner_config, tmpdir): with patch('os.path.isfile', side_effect=os_path_isfile_patch): runner.run('flash') assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_WITH_RFP_CLI] + + +@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) +@patch('runners.core.ZephyrBinaryRunner.check_call') +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_create_with_jlink_hardware(dr, cc, req, runner_config, tmpdir): + """ + Test commands using a jlink hardware. + + Input: + --rfp-cli /usr/local/bin/rfp-cli + + Output: + /usr/local/bin/rfp-cli + """ + args = [ + '--device', + str(TEST_RFP_DEVICE), + '--tool', + str(TEST_RFP_TOOL), + '--interface', + str(TEST_RFP_INTERFACE), + '--erase', + '--rfp-cli', + str(TEST_RFP_USR_LOCAL_RFP_CLI), + ] + parser = argparse.ArgumentParser(allow_abbrev=False) + RfpBinaryRunner.add_parser(parser) + arg_namespace = parser.parse_args(args) + runner = RfpBinaryRunner.create(runner_config, arg_namespace) + with patch('os.path.isfile', side_effect=os_path_isfile_patch): + runner.run('flash') + assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_WITH_JLINK_HARDWARE] + + +@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) +@patch('runners.core.ZephyrBinaryRunner.check_call') +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_create_with_partition_data(dr, cc, req, runner_config, tmpdir): + """ + Test commands using reresas partition data. + + Input: + --rfp-cli /usr/local/bin/rfp-cli + + Output: + /usr/local/bin/rfp-cli + """ + args = [ + '--device', + str(TEST_RFP_DEVICE), + '--tool', + str(TEST_RFP_TOOL), + '--interface', + str(TEST_RFP_INTERFACE), + '--rpd-file', + str(TEST_RFP_RPD_FILE), + '--erase', + '--rfp-cli', + str(TEST_RFP_USR_LOCAL_RFP_CLI), + ] + parser = argparse.ArgumentParser(allow_abbrev=False) + RfpBinaryRunner.add_parser(parser) + arg_namespace = parser.parse_args(args) + print(runner_config) + runner = RfpBinaryRunner.create(runner_config, arg_namespace) + with patch('os.path.isfile', side_effect=os_path_isfile_patch): + runner.run('flash') + print(cc.call_args_list) + assert [cc.call_args_list[0]] == [call(x) for x in EXPECTED_COMMANDS_WITH_PARTITION_DATA] + assert [cc.call_args_list[1]] == [call(x) for x in EXPECTED_COMMANDS_WITH_JLINK_HARDWARE] diff --git a/scripts/west_commands/twister_cmd.py b/scripts/west_commands/twister_cmd.py index 603ea3536829a..b96ab1b37175d 100644 --- a/scripts/west_commands/twister_cmd.py +++ b/scripts/west_commands/twister_cmd.py @@ -18,7 +18,7 @@ sys.path.insert(0, str(twister_path / "pylib" / "twister")) from twisterlib.environment import add_parse_arguments, parse_arguments, python_version_guard -from twisterlib.twister_main import main +from twisterlib.twister_main import twister TWISTER_DESCRIPTION = """\ Convenience wrapper for twister. The below options are shared with the twister @@ -58,7 +58,7 @@ def do_run(self, args, remainder): options = parse_arguments(self.parser, args=remainder, options=args) default_options = parse_arguments(self.parser, args=[], on_init=False) - ret = main(options, default_options) + ret = twister(options, default_options) sys.exit(ret) def _parse_arguments(self, args, options): diff --git a/scripts/zephyr_module.py b/scripts/zephyr_module.py index 290fc5da48231..c214f51704c83 100755 --- a/scripts/zephyr_module.py +++ b/scripts/zephyr_module.py @@ -386,6 +386,12 @@ def kconfig_snippet(meta, path, kconfig_file=None, blobs=False, taint_blobs=Fals return '\n'.join(snippet) +def process_kconfig_module_dir(module, meta): + module_path = PurePath(module) + name_sanitized = meta['name-sanitized'] + return f'ZEPHYR_{name_sanitized.upper()}_MODULE_DIR={module_path.as_posix()}\n' + + def process_kconfig(module, meta): blobs = process_blobs(module, meta) taint_blobs = any(b['status'] != BLOB_NOT_PRESENT for b in blobs) @@ -393,11 +399,9 @@ def process_kconfig(module, meta): module_path = PurePath(module) module_yml = module_path.joinpath('zephyr/module.yml') kconfig_extern = section.get('kconfig-ext', False) - name_sanitized = meta['name-sanitized'] - snippet = f'ZEPHYR_{name_sanitized.upper()}_MODULE_DIR := {module_path.as_posix()}\n' if kconfig_extern: - return snippet + kconfig_snippet(meta, module_path, blobs=blobs, taint_blobs=taint_blobs) + return kconfig_snippet(meta, module_path, blobs=blobs, taint_blobs=taint_blobs) kconfig_setting = section.get('kconfig', None) if not validate_setting(kconfig_setting, module): @@ -407,10 +411,11 @@ def process_kconfig(module, meta): kconfig_file = os.path.join(module, kconfig_setting or 'zephyr/Kconfig') if os.path.isfile(kconfig_file): - return snippet + kconfig_snippet(meta, module_path, Path(kconfig_file), - blobs=blobs, taint_blobs=taint_blobs) + return kconfig_snippet(meta, module_path, Path(kconfig_file), + blobs=blobs, taint_blobs=taint_blobs) else: - return snippet + '\n'.join(kconfig_module_opts(name_sanitized, blobs, taint_blobs)) + '\n' + name_sanitized = meta['name-sanitized'] + return '\n'.join(kconfig_module_opts(name_sanitized, blobs, taint_blobs)) + '\n' def process_sysbuildkconfig(module, meta): @@ -419,10 +424,9 @@ def process_sysbuildkconfig(module, meta): module_yml = module_path.joinpath('zephyr/module.yml') kconfig_extern = section.get('sysbuild-kconfig-ext', False) name_sanitized = meta['name-sanitized'] - snippet = f'ZEPHYR_{name_sanitized.upper()}_MODULE_DIR := {module_path.as_posix()}\n' if kconfig_extern: - return snippet + kconfig_snippet(meta, module_path, sysbuild=True) + return kconfig_snippet(meta, module_path, sysbuild=True) kconfig_setting = section.get('sysbuild-kconfig', None) if not validate_setting(kconfig_setting, module): @@ -433,10 +437,9 @@ def process_sysbuildkconfig(module, meta): if kconfig_setting is not None: kconfig_file = os.path.join(module, kconfig_setting) if os.path.isfile(kconfig_file): - return snippet + kconfig_snippet(meta, module_path, Path(kconfig_file)) + return kconfig_snippet(meta, module_path, Path(kconfig_file)) - return snippet + \ - (f'config ZEPHYR_{name_sanitized.upper()}_MODULE\n' + return (f'config ZEPHYR_{name_sanitized.upper()}_MODULE\n' f' bool\n' f' default y\n') @@ -866,6 +869,7 @@ def main(): help='Path to zephyr repository') args = parser.parse_args() + kconfig_module_dirs = "" kconfig = "" cmake = "" sysbuild_kconfig = "" @@ -878,6 +882,7 @@ def main(): args.modules, args.extra_modules) for module in modules: + kconfig_module_dirs += process_kconfig_module_dir(module.project, module.meta) kconfig += process_kconfig(module.project, module.meta) cmake += process_cmake(module.project, module.meta) sysbuild_kconfig += process_sysbuildkconfig( @@ -886,6 +891,16 @@ def main(): settings += process_settings(module.project, module.meta) twister += process_twister(module.project, module.meta) + if args.kconfig_out or args.sysbuild_kconfig_out: + if args.kconfig_out: + kconfig_module_dirs_out = PurePath(args.kconfig_out).parent / 'kconfig_module_dirs.env' + elif args.sysbuild_kconfig_out: + kconfig_module_dirs_out = PurePath(args.sysbuild_kconfig_out).parent / \ + 'kconfig_module_dirs.env' + + with open(kconfig_module_dirs_out, 'w', encoding="utf-8") as fp: + fp.write(kconfig_module_dirs) + if args.kconfig_out: with open(args.kconfig_out, 'w', encoding="utf-8") as fp: fp.write(kconfig) diff --git a/share/sysbuild/Kconfig b/share/sysbuild/Kconfig index 5f689e07399a6..1a9f36ac77797 100644 --- a/share/sysbuild/Kconfig +++ b/share/sysbuild/Kconfig @@ -2,6 +2,8 @@ # # SPDX-License-Identifier: Apache-2.0 +source "$(KCONFIG_ENV_FILE)" + config BOARD string default "$(BOARD)" @@ -72,7 +74,7 @@ config WARN_DEPRECATED config NOT_SECURE bool help - Symbol to be selected by a feature to inidicate that feature is + Symbol to be selected by a feature to indicate that feature is not secure. rsource "images/Kconfig" diff --git a/share/sysbuild/images/bootloader/Kconfig b/share/sysbuild/images/bootloader/Kconfig index c8b776c1be064..785a52f2d65d3 100644 --- a/share/sysbuild/images/bootloader/Kconfig +++ b/share/sysbuild/images/bootloader/Kconfig @@ -33,7 +33,7 @@ if BOOTLOADER_MCUBOOT choice MCUBOOT_MODE prompt "Mode of operation" # Should be removed if board dts is updated - default MCUBOOT_MODE_SWAP_USING_MOVE if SOC_FAMILY_STM32 + default MCUBOOT_MODE_SWAP_USING_MOVE if SOC_FAMILY_STM32 || SOC_FAMILY_ESPRESSIF_ESP32 default MCUBOOT_MODE_SWAP_USING_OFFSET help The operating mode of MCUboot (which will also be propagated to the application). diff --git a/share/zephyr-package/cmake/zephyr_package_search.cmake b/share/zephyr-package/cmake/zephyr_package_search.cmake index bcd58217ba65a..be7c2cf5ba22f 100644 --- a/share/zephyr-package/cmake/zephyr_package_search.cmake +++ b/share/zephyr-package/cmake/zephyr_package_search.cmake @@ -49,10 +49,11 @@ endmacro() # - VERSION_CHECK : This is the version check stage by CMake find package # - CANDIDATES_PREFERENCE_LIST : List of candidate to be preferred, if installed macro(check_zephyr_package) - set(options CHECK_ONLY SEARCH_PARENTS VERSION_CHECK) - set(single_args WORKSPACE_DIR ZEPHYR_BASE) - set(list_args CANDIDATES_PREFERENCE_LIST) - cmake_parse_arguments(CHECK_ZEPHYR_PACKAGE "${options}" "${single_args}" "${list_args}" ${ARGN}) + set(zephyr_package_options CHECK_ONLY SEARCH_PARENTS VERSION_CHECK) + set(zephyr_package_single_args WORKSPACE_DIR ZEPHYR_BASE) + set(zephyr_package_list_args CANDIDATES_PREFERENCE_LIST) + cmake_parse_arguments(CHECK_ZEPHYR_PACKAGE "${zephyr_package_options}" + "${zephyr_package_single_args}" "${zephyr_package_list_args}" ${ARGN}) if(CHECK_ZEPHYR_PACKAGE_ZEPHYR_BASE) set(SEARCH_SETTINGS PATHS ${CHECK_ZEPHYR_PACKAGE_ZEPHYR_BASE} NO_DEFAULT_PATH) diff --git a/snippets/index.rst b/snippets/index.rst index f0604abfae43b..b81f3fc665de2 100644 --- a/snippets/index.rst +++ b/snippets/index.rst @@ -7,4 +7,4 @@ Built-in snippets :maxdepth: 1 :glob: - **/* + */* diff --git a/snippets/nordic/index.rst b/snippets/nordic/index.rst new file mode 100644 index 0000000000000..7addef3684d1d --- /dev/null +++ b/snippets/nordic/index.rst @@ -0,0 +1,10 @@ +.. _nordic-snippets: + +Nordic snippets +############### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/snippets/nordic-flpr-xip/README.rst b/snippets/nordic/nordic-flpr-xip/README.rst similarity index 100% rename from snippets/nordic-flpr-xip/README.rst rename to snippets/nordic/nordic-flpr-xip/README.rst diff --git a/snippets/nordic-flpr-xip/nordic-flpr-xip.overlay b/snippets/nordic/nordic-flpr-xip/nordic-flpr-xip.overlay similarity index 100% rename from snippets/nordic-flpr-xip/nordic-flpr-xip.overlay rename to snippets/nordic/nordic-flpr-xip/nordic-flpr-xip.overlay diff --git a/snippets/nordic-flpr-xip/snippet.yml b/snippets/nordic/nordic-flpr-xip/snippet.yml similarity index 100% rename from snippets/nordic-flpr-xip/snippet.yml rename to snippets/nordic/nordic-flpr-xip/snippet.yml diff --git a/snippets/nordic-flpr-xip/soc/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-flpr-xip/soc/nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-flpr-xip/soc/nrf54h20_cpuapp.overlay rename to snippets/nordic/nordic-flpr-xip/soc/nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-flpr-xip/soc/nrf54l15_cpuapp.overlay b/snippets/nordic/nordic-flpr-xip/soc/nrf54l15_cpuapp.overlay similarity index 100% rename from snippets/nordic-flpr-xip/soc/nrf54l15_cpuapp.overlay rename to snippets/nordic/nordic-flpr-xip/soc/nrf54l15_cpuapp.overlay diff --git a/snippets/nordic-flpr/README.rst b/snippets/nordic/nordic-flpr/README.rst similarity index 100% rename from snippets/nordic-flpr/README.rst rename to snippets/nordic/nordic-flpr/README.rst diff --git a/snippets/nordic-flpr/nordic-flpr.overlay b/snippets/nordic/nordic-flpr/nordic-flpr.overlay similarity index 100% rename from snippets/nordic-flpr/nordic-flpr.overlay rename to snippets/nordic/nordic-flpr/nordic-flpr.overlay diff --git a/snippets/nordic-flpr/snippet.yml b/snippets/nordic/nordic-flpr/snippet.yml similarity index 100% rename from snippets/nordic-flpr/snippet.yml rename to snippets/nordic/nordic-flpr/snippet.yml diff --git a/snippets/nordic-flpr/soc/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-flpr/soc/nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-flpr/soc/nrf54h20_cpuapp.overlay rename to snippets/nordic/nordic-flpr/soc/nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-flpr/soc/nrf54l15_cpuapp.overlay b/snippets/nordic/nordic-flpr/soc/nrf54l15_cpuapp.overlay similarity index 100% rename from snippets/nordic-flpr/soc/nrf54l15_cpuapp.overlay rename to snippets/nordic/nordic-flpr/soc/nrf54l15_cpuapp.overlay diff --git a/snippets/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay b/snippets/nordic/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay similarity index 100% rename from snippets/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay rename to snippets/nordic/nordic-flpr/soc/nrf54lm20a_cpuapp.overlay diff --git a/snippets/nordic-log-stm-dict/README.rst b/snippets/nordic/nordic-log-stm-dict/README.rst similarity index 100% rename from snippets/nordic-log-stm-dict/README.rst rename to snippets/nordic/nordic-log-stm-dict/README.rst diff --git a/snippets/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay rename to snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay b/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay similarity index 100% rename from snippets/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay rename to snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay diff --git a/snippets/nordic-log-stm-dict/log_stm_dict.conf b/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf similarity index 100% rename from snippets/nordic-log-stm-dict/log_stm_dict.conf rename to snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf diff --git a/snippets/nordic-log-stm-dict/snippet.yml b/snippets/nordic/nordic-log-stm-dict/snippet.yml similarity index 100% rename from snippets/nordic-log-stm-dict/snippet.yml rename to snippets/nordic/nordic-log-stm-dict/snippet.yml diff --git a/snippets/nordic-log-stm/README.rst b/snippets/nordic/nordic-log-stm/README.rst similarity index 100% rename from snippets/nordic-log-stm/README.rst rename to snippets/nordic/nordic-log-stm/README.rst diff --git a/snippets/nordic-log-stm/boards/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-log-stm/boards/nrf54h20_cpuapp.overlay rename to snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-log-stm/boards/nrf54h20_cpurad.overlay b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay similarity index 100% rename from snippets/nordic-log-stm/boards/nrf54h20_cpurad.overlay rename to snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay diff --git a/snippets/nordic-log-stm/log_stm.conf b/snippets/nordic/nordic-log-stm/log_stm.conf similarity index 100% rename from snippets/nordic-log-stm/log_stm.conf rename to snippets/nordic/nordic-log-stm/log_stm.conf diff --git a/snippets/nordic-log-stm/snippet.yml b/snippets/nordic/nordic-log-stm/snippet.yml similarity index 100% rename from snippets/nordic-log-stm/snippet.yml rename to snippets/nordic/nordic-log-stm/snippet.yml diff --git a/snippets/nordic-ppr-xip/README.rst b/snippets/nordic/nordic-ppr-xip/README.rst similarity index 100% rename from snippets/nordic-ppr-xip/README.rst rename to snippets/nordic/nordic-ppr-xip/README.rst diff --git a/snippets/nordic-ppr-xip/nordic-ppr-xip.overlay b/snippets/nordic/nordic-ppr-xip/nordic-ppr-xip.overlay similarity index 100% rename from snippets/nordic-ppr-xip/nordic-ppr-xip.overlay rename to snippets/nordic/nordic-ppr-xip/nordic-ppr-xip.overlay diff --git a/snippets/nordic-ppr-xip/snippet.yml b/snippets/nordic/nordic-ppr-xip/snippet.yml similarity index 100% rename from snippets/nordic-ppr-xip/snippet.yml rename to snippets/nordic/nordic-ppr-xip/snippet.yml diff --git a/snippets/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay rename to snippets/nordic/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-ppr-xip/soc/nrf9280_cpuapp.overlay b/snippets/nordic/nordic-ppr-xip/soc/nrf9280_cpuapp.overlay similarity index 100% rename from snippets/nordic-ppr-xip/soc/nrf9280_cpuapp.overlay rename to snippets/nordic/nordic-ppr-xip/soc/nrf9280_cpuapp.overlay diff --git a/snippets/nordic-ppr/README.rst b/snippets/nordic/nordic-ppr/README.rst similarity index 100% rename from snippets/nordic-ppr/README.rst rename to snippets/nordic/nordic-ppr/README.rst diff --git a/snippets/nordic-ppr/nordic-ppr.overlay b/snippets/nordic/nordic-ppr/nordic-ppr.overlay similarity index 100% rename from snippets/nordic-ppr/nordic-ppr.overlay rename to snippets/nordic/nordic-ppr/nordic-ppr.overlay diff --git a/snippets/nordic-ppr/snippet.yml b/snippets/nordic/nordic-ppr/snippet.yml similarity index 100% rename from snippets/nordic-ppr/snippet.yml rename to snippets/nordic/nordic-ppr/snippet.yml diff --git a/snippets/nordic-ppr/soc/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-ppr/soc/nrf54h20_cpuapp.overlay similarity index 100% rename from snippets/nordic-ppr/soc/nrf54h20_cpuapp.overlay rename to snippets/nordic/nordic-ppr/soc/nrf54h20_cpuapp.overlay diff --git a/snippets/nordic-ppr/soc/nrf9280_cpuapp.overlay b/snippets/nordic/nordic-ppr/soc/nrf9280_cpuapp.overlay similarity index 100% rename from snippets/nordic-ppr/soc/nrf9280_cpuapp.overlay rename to snippets/nordic/nordic-ppr/soc/nrf9280_cpuapp.overlay diff --git a/snippets/socketcan-native-sim/README.rst b/snippets/socketcan-native-sim/README.rst index 970ea6172ecea..f5b537fbf49b2 100644 --- a/snippets/socketcan-native-sim/README.rst +++ b/snippets/socketcan-native-sim/README.rst @@ -11,7 +11,7 @@ Overview ******** This snippet allows to configure Controller Area Network (CAN) samples with Linux SocketCAN support -on :ref:`native_sim`. +on :zephyr:board:`native_sim`. By default, the native simulator expects a SocketCAN network device called ``zcan0`` (specified in :zephyr_file:`boards/native/native_sim/native_sim.dts`). This name can be added as an alternative diff --git a/snippets/wifi-enterprise/snippet.yml b/snippets/wifi-enterprise/snippet.yml deleted file mode 100644 index 6a4f73d38b42e..0000000000000 --- a/snippets/wifi-enterprise/snippet.yml +++ /dev/null @@ -1,3 +0,0 @@ -name: wifi-enterprise -append: - EXTRA_CONF_FILE: wifi-enterprise.conf diff --git a/snippets/wifi/index.rst b/snippets/wifi/index.rst new file mode 100644 index 0000000000000..5a8ea017ba307 --- /dev/null +++ b/snippets/wifi/index.rst @@ -0,0 +1,10 @@ +.. _wifi-snippets: + +Wi-Fi snippets +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/snippets/wifi-credentials/README.rst b/snippets/wifi/wifi-credentials/README.rst similarity index 100% rename from snippets/wifi-credentials/README.rst rename to snippets/wifi/wifi-credentials/README.rst diff --git a/snippets/wifi-credentials/snippet.yml b/snippets/wifi/wifi-credentials/snippet.yml similarity index 100% rename from snippets/wifi-credentials/snippet.yml rename to snippets/wifi/wifi-credentials/snippet.yml diff --git a/snippets/wifi-credentials/wifi-credentials.conf b/snippets/wifi/wifi-credentials/wifi-credentials.conf similarity index 100% rename from snippets/wifi-credentials/wifi-credentials.conf rename to snippets/wifi/wifi-credentials/wifi-credentials.conf diff --git a/snippets/wifi-enterprise/README.rst b/snippets/wifi/wifi-enterprise/README.rst similarity index 100% rename from snippets/wifi-enterprise/README.rst rename to snippets/wifi/wifi-enterprise/README.rst diff --git a/snippets/wifi/wifi-enterprise/snippet.yml b/snippets/wifi/wifi-enterprise/snippet.yml new file mode 100644 index 0000000000000..ae2fbd2953b58 --- /dev/null +++ b/snippets/wifi/wifi-enterprise/snippet.yml @@ -0,0 +1,11 @@ +name: wifi-enterprise +append: + EXTRA_CONF_FILE: wifi-enterprise.conf + +boards: + /.*/nrf.*/cpuapp/: + append: + EXTRA_CONF_FILE: wifi-enterprise-nrf.conf + /.*/nrf.*/cpuapp/ns/: + append: + EXTRA_CONF_FILE: wifi-enterprise-nrf-ns.conf diff --git a/snippets/wifi/wifi-enterprise/wifi-enterprise-nrf-ns.conf b/snippets/wifi/wifi-enterprise/wifi-enterprise-nrf-ns.conf new file mode 100644 index 0000000000000..dd33192d180d7 --- /dev/null +++ b/snippets/wifi/wifi-enterprise/wifi-enterprise-nrf-ns.conf @@ -0,0 +1,8 @@ +# For TLS and X.509 processing MbedTLS needs large heap size and using separate heap +# for MbedTLS gives us more control over the heap size. +CONFIG_MBEDTLS_HEAP_SIZE=75000 +CONFIG_LTO=y +CONFIG_ISR_TABLES_LOCAL_DECLARATION=y +CONFIG_WIFI_CREDENTIALS_RUNTIME_CERTIFICATES=y +CONFIG_WIFI_SHELL_RUNTIME_CERTIFICATES=y +CONFIG_TLS_CREDENTIALS_BACKEND_PROTECTED_STORAGE=y diff --git a/snippets/wifi/wifi-enterprise/wifi-enterprise-nrf.conf b/snippets/wifi/wifi-enterprise/wifi-enterprise-nrf.conf new file mode 100644 index 0000000000000..a52390c1687cf --- /dev/null +++ b/snippets/wifi/wifi-enterprise/wifi-enterprise-nrf.conf @@ -0,0 +1,3 @@ +# For TLS and X.509 processing MbedTLS needs large heap size and using separate heap +# for MbedTLS gives us more control over the heap size. +CONFIG_MBEDTLS_HEAP_SIZE=75000 diff --git a/snippets/wifi-enterprise/wifi-enterprise.conf b/snippets/wifi/wifi-enterprise/wifi-enterprise.conf similarity index 100% rename from snippets/wifi-enterprise/wifi-enterprise.conf rename to snippets/wifi/wifi-enterprise/wifi-enterprise.conf diff --git a/snippets/wifi-ip/README.rst b/snippets/wifi/wifi-ip/README.rst similarity index 100% rename from snippets/wifi-ip/README.rst rename to snippets/wifi/wifi-ip/README.rst diff --git a/snippets/wifi-ip/snippet.yml b/snippets/wifi/wifi-ip/snippet.yml similarity index 100% rename from snippets/wifi-ip/snippet.yml rename to snippets/wifi/wifi-ip/snippet.yml diff --git a/snippets/wifi-ip/wifi-ip.conf b/snippets/wifi/wifi-ip/wifi-ip.conf similarity index 100% rename from snippets/wifi-ip/wifi-ip.conf rename to snippets/wifi/wifi-ip/wifi-ip.conf diff --git a/snippets/wifi-ipv4/README.rst b/snippets/wifi/wifi-ipv4/README.rst similarity index 100% rename from snippets/wifi-ipv4/README.rst rename to snippets/wifi/wifi-ipv4/README.rst diff --git a/snippets/wifi-ipv4/snippet.yml b/snippets/wifi/wifi-ipv4/snippet.yml similarity index 100% rename from snippets/wifi-ipv4/snippet.yml rename to snippets/wifi/wifi-ipv4/snippet.yml diff --git a/snippets/wifi-ipv4/wifi-ipv4.conf b/snippets/wifi/wifi-ipv4/wifi-ipv4.conf similarity index 100% rename from snippets/wifi-ipv4/wifi-ipv4.conf rename to snippets/wifi/wifi-ipv4/wifi-ipv4.conf diff --git a/snippets/wifi-ipv6/README.rst b/snippets/wifi/wifi-ipv6/README.rst similarity index 100% rename from snippets/wifi-ipv6/README.rst rename to snippets/wifi/wifi-ipv6/README.rst diff --git a/snippets/wifi-ipv6/snippet.yml b/snippets/wifi/wifi-ipv6/snippet.yml similarity index 100% rename from snippets/wifi-ipv6/snippet.yml rename to snippets/wifi/wifi-ipv6/snippet.yml diff --git a/snippets/wifi-ipv6/wifi-ipv6.conf b/snippets/wifi/wifi-ipv6/wifi-ipv6.conf similarity index 100% rename from snippets/wifi-ipv6/wifi-ipv6.conf rename to snippets/wifi/wifi-ipv6/wifi-ipv6.conf diff --git a/snippets/xiao-serial-console/README.rst b/snippets/xiao-serial-console/README.rst new file mode 100644 index 0000000000000..054338a018309 --- /dev/null +++ b/snippets/xiao-serial-console/README.rst @@ -0,0 +1,10 @@ +.. _snippet-xiao-serial-console: + +XIAO UART/Serial Console Snippet (xiao-serial-console) +###################################################### + +Overview +******** + +This snippet enables console output over the standard XIAO UART pins, setting ``zephyr,console`` to +``&xiao_serial``. diff --git a/snippets/xiao-serial-console/snippet.yml b/snippets/xiao-serial-console/snippet.yml new file mode 100644 index 0000000000000..ad5d8cd597bac --- /dev/null +++ b/snippets/xiao-serial-console/snippet.yml @@ -0,0 +1,4 @@ +name: xiao-serial-console +append: + EXTRA_CONF_FILE: xiao-serial-console.conf + EXTRA_DTC_OVERLAY_FILE: xiao-serial-console.overlay diff --git a/snippets/xiao-serial-console/xiao-serial-console.conf b/snippets/xiao-serial-console/xiao-serial-console.conf new file mode 100644 index 0000000000000..076ca5b7b16fd --- /dev/null +++ b/snippets/xiao-serial-console/xiao-serial-console.conf @@ -0,0 +1,3 @@ +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/snippets/xiao-serial-console/xiao-serial-console.overlay b/snippets/xiao-serial-console/xiao-serial-console.overlay new file mode 100644 index 0000000000000..ff4c1e7242b26 --- /dev/null +++ b/snippets/xiao-serial-console/xiao-serial-console.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Pete Johanson + * SPDX-License-Identifier: Apache-2.0 + */ + +&xiao_serial { + status = "okay"; +}; + +/ { + chosen { + zephyr,console = &xiao_serial; + zephyr,shell-uart = &xiao_serial; + }; +}; diff --git a/soc/ambiq/apollo5x/Kconfig b/soc/ambiq/apollo5x/Kconfig index e3d0980cf22df..0ab4443b4b296 100644 --- a/soc/ambiq/apollo5x/Kconfig +++ b/soc/ambiq/apollo5x/Kconfig @@ -43,3 +43,7 @@ config SOC_AMBIQ_DMA_BUFF_ALIGNMENT default 1 help This option specifies the DMA buffers' alignment + +config ARMV8_1_M_PMU_EVENTCNT + int + default 8 if SOC_APOLLO510 diff --git a/soc/ambiq/apollo5x/Kconfig.soc b/soc/ambiq/apollo5x/Kconfig.soc index 15fa794aa9cc9..8347846f2e36c 100644 --- a/soc/ambiq/apollo5x/Kconfig.soc +++ b/soc/ambiq/apollo5x/Kconfig.soc @@ -12,10 +12,6 @@ config SOC_APOLLO510 bool select SOC_SERIES_APOLLO5X -config ARMV8_1_M_PMU_EVENTCNT - int - default 8 - config SOC_SERIES default "apollo5x" if SOC_SERIES_APOLLO5X diff --git a/soc/bflb/bl60x/Kconfig b/soc/bflb/bl60x/Kconfig index d0a0f226365ce..b7f46c4040366 100644 --- a/soc/bflb/bl60x/Kconfig +++ b/soc/bflb/bl60x/Kconfig @@ -15,7 +15,6 @@ config SOC_SERIES_BL60X select RISCV select RISCV_HAS_CLIC select RISCV_MACHINE_TIMER - select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING select RISCV_PRIVILEGED select RISCV_ISA_RV32I select RISCV_ISA_EXT_M @@ -26,5 +25,6 @@ config SOC_SERIES_BL60X select RISCV_ISA_EXT_ZIFENCEI select RISCV_VECTORED_MODE select SOC_EARLY_INIT_HOOK + select SOC_PREP_HOOK select SYSCON select XIP diff --git a/soc/bflb/bl60x/soc.c b/soc/bflb/bl60x/soc.c index 852af2db7bde9..ecf4c3771cfb5 100644 --- a/soc/bflb/bl60x/soc.c +++ b/soc/bflb/bl60x/soc.c @@ -44,14 +44,10 @@ static void system_bor_init(void) void soc_early_init_hook(void) { - uint32_t key; uint32_t *p; uint32_t i = 0; uint32_t tmp = 0; - key = irq_lock(); - - /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */ tmp = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET); /* "BL_CLR_REG_BIT" */ @@ -98,6 +94,4 @@ GLB_JTAG_SWAP_SET_POS); /* init bor for all platform */ system_bor_init(); - - irq_unlock(key); } diff --git a/soc/bflb/bl61x/soc.c b/soc/bflb/bl61x/soc.c index 69d5274a1b8e6..3dbf109cbcf03 100644 --- a/soc/bflb/bl61x/soc.c +++ b/soc/bflb/bl61x/soc.c @@ -19,27 +19,92 @@ #include #include +#define SYSMAP_BASE 0xEFFFF000UL +#define SYSMAP_BASE_SHIFT (12) +#define SYSMAP_ATTR_STRONG_ORDER BIT(4) +#define SYSMAP_ATTR_CACHE_ABLE BIT(3) +#define SYSMAP_ATTR_BUFFER_ABLE BIT(2) +#define SYSMAP_ADDR_OFFSET 0x0 +#define SYSMAP_FLAGS_OFFSET 0x4 +#define SYSMAP_ENTRY_OFFSET 0x8 + +/* Initialize memory regions */ +void system_sysmap_init(void) +{ + uintptr_t sysmap_base = SYSMAP_BASE; + + /* 1. 0x00000000~0x62FC0000: Strong-Order, Non-Cacheable, Non-Bufferable */ + sys_write32(BL616_OCRAM_BUSREMAP_CACHEABLE_BASE >> SYSMAP_BASE_SHIFT, + (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_STRONG_ORDER, (sysmap_base + SYSMAP_FLAGS_OFFSET)); + sysmap_base += SYSMAP_ENTRY_OFFSET; + + /* 2. ocram 0x62FC0000~0x63010000: Weak-Order, Cacheable, Bufferable */ + sys_write32(BL616_WRAM_BUSREMAP_CACHEABLE_BASE >> SYSMAP_BASE_SHIFT, + (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_CACHE_ABLE | SYSMAP_ATTR_BUFFER_ABLE, + (sysmap_base + SYSMAP_FLAGS_OFFSET)); + sysmap_base += SYSMAP_ENTRY_OFFSET; + + /* 3. wram 0x63010000~0x63038000: Weak-Order, Cacheable, Bufferable */ + sys_write32(BL616_WRAM_BUSREMAP_CACHEABLE_END + >> SYSMAP_BASE_SHIFT, (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_CACHE_ABLE | SYSMAP_ATTR_BUFFER_ABLE, + (sysmap_base + SYSMAP_FLAGS_OFFSET)); + sysmap_base += SYSMAP_ENTRY_OFFSET; + + /* 4. rom/empty 0x63038000~0xA0000000: Strong-Order, Non-Cacheable, Non-Bufferable */ + sys_write32(BL616_FLASH_XIP_BASE >> SYSMAP_BASE_SHIFT, (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_STRONG_ORDER, (sysmap_base + SYSMAP_FLAGS_OFFSET)); + sysmap_base += SYSMAP_ENTRY_OFFSET; + + /* 5. flash(2x32M) 0xA0000000~0xA4000000: Weak-Order, Cacheable, Non-Bufferable */ + sys_write32(BL616_FLASH_XIP_BUSREMAP_END >> SYSMAP_BASE_SHIFT, + (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_CACHE_ABLE, (sysmap_base + SYSMAP_FLAGS_OFFSET)); + sysmap_base += SYSMAP_ENTRY_OFFSET; + + /* 6. empty 0xA2000000~0xA8000000: Strong-Order, Non-Cacheable, Non-Bufferable */ + sys_write32(BL616_PSRAM_BUSREMAP_BASE >> SYSMAP_BASE_SHIFT, + (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_STRONG_ORDER, (sysmap_base + SYSMAP_FLAGS_OFFSET)); + sysmap_base += SYSMAP_ENTRY_OFFSET; + + /* 7. psram(128M (4M)) 0xA8000000~0xB0000000(0xA8400000): + * Weak-Order, Cacheable, Bufferable + */ + sys_write32(BL616_PSRAM_BUSREMAP_END >> SYSMAP_BASE_SHIFT, + (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_CACHE_ABLE | SYSMAP_ATTR_BUFFER_ABLE, + (sysmap_base + SYSMAP_FLAGS_OFFSET)); + sysmap_base += SYSMAP_ENTRY_OFFSET; + + /* 8. others: Strong-Order, Non-Cacheable, Non-Bufferable */ + sys_write32(0xFFFFF000U >> SYSMAP_BASE_SHIFT, (sysmap_base + SYSMAP_ADDR_OFFSET)); + sys_write32(SYSMAP_ATTR_STRONG_ORDER, (sysmap_base + SYSMAP_FLAGS_OFFSET)); +} + /* brown out detection */ void system_BOD_init(void) { - uint32_t tmpVal = 0; + uint32_t tmp; /* disable BOD interrupt */ - tmpVal = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET); - tmpVal &= ~HBN_IRQ_BOR_EN_MSK; - sys_write32(tmpVal, HBN_BASE + HBN_IRQ_MODE_OFFSET); + tmp = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET); + tmp &= ~HBN_IRQ_BOR_EN_MSK; + sys_write32(tmp, HBN_BASE + HBN_IRQ_MODE_OFFSET); - tmpVal = sys_read32(HBN_BASE + HBN_BOR_CFG_OFFSET); + tmp = sys_read32(HBN_BASE + HBN_BOR_CFG_OFFSET); /* when brownout threshold, restart*/ - tmpVal |= HBN_BOD_SEL_MSK; + tmp |= HBN_BOD_SEL_MSK; /* set BOD threshold: * 0:2.05v,1:2.10v,2:2.15v....7:2.4v */ - tmpVal &= ~HBN_BOD_VTH_MSK; - tmpVal |= (7 << HBN_BOD_VTH_POS); + tmp &= ~HBN_BOD_VTH_MSK; + tmp |= (7 << HBN_BOD_VTH_POS); /* enable BOD */ - tmpVal |= HBN_PU_BOD_MSK; - sys_write32(tmpVal, HBN_BASE + HBN_BOR_CFG_OFFSET); + tmp |= HBN_PU_BOD_MSK; + sys_write32(tmp, HBN_BASE + HBN_BOR_CFG_OFFSET); } static void clean_dcache(void) @@ -66,7 +131,7 @@ static void clean_icache(void) static void enable_icache(void) { - uint32_t tmpVal = 0; + uint32_t tmp; __asm__ volatile ( "fence\n" @@ -76,12 +141,12 @@ static void enable_icache(void) ); __asm__ volatile( "csrr %0, 0x7C1" - : "=r"(tmpVal)); - tmpVal |= (1 << 0); + : "=r"(tmp)); + tmp |= (1 << 0); __asm__ volatile( "csrw 0x7C1, %0" : - : "r"(tmpVal)); + : "r"(tmp)); __asm__ volatile ( "fence\n" "fence.i\n" @@ -90,7 +155,7 @@ static void enable_icache(void) static void enable_dcache(void) { - uint32_t tmpVal = 0; + uint32_t tmp; __asm__ volatile ( "fence\n" @@ -100,12 +165,12 @@ static void enable_dcache(void) ); __asm__ volatile( "csrr %0, 0x7C1" - : "=r"(tmpVal)); - tmpVal |= (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4); + : "=r"(tmp)); + tmp |= (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4); __asm__ volatile( "csrw 0x7C1, %0" : - : "r"(tmpVal)); + : "r"(tmp)); __asm__ volatile ( "fence\n" "fence.i\n" @@ -114,7 +179,7 @@ static void enable_dcache(void) static void enable_branchpred(bool yes) { - uint32_t tmpVal = 0; + uint32_t tmp; __asm__ volatile ( "fence\n" @@ -122,16 +187,16 @@ static void enable_branchpred(bool yes) ); __asm__ volatile( "csrr %0, 0x7C1" - : "=r"(tmpVal)); + : "=r"(tmp)); if (yes) { - tmpVal |= (1 << 5) | (1 << 12); + tmp |= (1 << 5) | (1 << 12); } else { - tmpVal &= ~((1 << 5) | (1 << 12)); + tmp &= ~((1 << 5) | (1 << 12)); } __asm__ volatile( "csrw 0x7C1, %0" : - : "r"(tmpVal)); + : "r"(tmp)); __asm__ volatile ( "fence\n" "fence.i\n" @@ -140,48 +205,48 @@ static void enable_branchpred(bool yes) static void enable_thead_isa_ext(void) { - uint32_t tmpVal = 0; + uint32_t tmp; __asm__ volatile( "csrr %0, 0x7C0" - : "=r"(tmpVal)); - tmpVal |= (1 << 22); + : "=r"(tmp)); + tmp |= (1 << 22); __asm__ volatile( "csrw 0x7C0, %0" : - : "r"(tmpVal)); + : "r"(tmp)); } static void set_thead_enforce_aligned(bool enable) { - uint32_t tmpVal = 0; + uint32_t tmp; __asm__ volatile( "csrr %0, 0x7C0" - : "=r"(tmpVal)); + : "=r"(tmp)); if (enable) { - tmpVal &= ~(1 << 15); + tmp &= ~(1 << 15); } else { - tmpVal |= (1 << 15); + tmp |= (1 << 15); } __asm__ volatile( "csrw 0x7C0, %0" : - : "r"(tmpVal)); + : "r"(tmp)); } static void disable_interrupt_autostacking(void) { - uint32_t tmpVal = 0; + uint32_t tmp; __asm__ volatile( "csrr %0, 0x7E1" - : "=r"(tmpVal)); - tmpVal &= ~(0x3 << 16); + : "=r"(tmp)); + tmp &= ~(0x3 << 16); __asm__ volatile( "csrw 0x7E1, %0" : - : "r"(tmpVal)); + : "r"(tmp)); } @@ -192,6 +257,7 @@ void soc_early_init_hook(void) key = irq_lock(); + system_sysmap_init(); /* turn off USB power */ sys_write32((1 << 5), PDS_BASE + PDS_USB_CTL_OFFSET); diff --git a/soc/bflb/bl70x/Kconfig b/soc/bflb/bl70x/Kconfig index 3c191612cceb8..57ad2bb9d8981 100644 --- a/soc/bflb/bl70x/Kconfig +++ b/soc/bflb/bl70x/Kconfig @@ -14,7 +14,6 @@ config SOC_SERIES_BL70X select RISCV select RISCV_HAS_CLIC select RISCV_MACHINE_TIMER - select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING select RISCV_PRIVILEGED select RISCV_ISA_RV32I select RISCV_ISA_EXT_M @@ -25,5 +24,6 @@ config SOC_SERIES_BL70X select RISCV_ISA_EXT_ZIFENCEI select RISCV_VECTORED_MODE select SOC_EARLY_INIT_HOOK + select SOC_PREP_HOOK select SYSCON select XIP diff --git a/soc/bflb/bl70x/soc.c b/soc/bflb/bl70x/soc.c index 21756116406f2..7133313e39ac7 100644 --- a/soc/bflb/bl70x/soc.c +++ b/soc/bflb/bl70x/soc.c @@ -43,14 +43,10 @@ static void system_bor_init(void) void soc_early_init_hook(void) { - uint32_t key; uint32_t *p; uint32_t i = 0; uint32_t tmp; - key = irq_lock(); - - /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */ tmp = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET); /* "BL_CLR_REG_BIT" */ @@ -82,6 +78,4 @@ void soc_early_init_hook(void) /* init bor for all platform */ system_bor_init(); - - irq_unlock(key); } diff --git a/soc/bflb/common/CMakeLists.txt b/soc/bflb/common/CMakeLists.txt index 162490a3eede7..c23881ce62706 100644 --- a/soc/bflb/common/CMakeLists.txt +++ b/soc/bflb/common/CMakeLists.txt @@ -8,5 +8,6 @@ if(CONFIG_SOC_SERIES_BL60X OR CONFIG_SOC_SERIES_BL70X) zephyr_include_directories(e24) zephyr_sources( e24/soc_irq_privileged.c -e24/intc_clic.S) +e24/soc.c +) endif() diff --git a/soc/bflb/common/e24/clic.h b/soc/bflb/common/e24/clic.h index 5c1d8c38ae56f..7328a46257c65 100644 --- a/soc/bflb/common/e24/clic.h +++ b/soc/bflb/common/e24/clic.h @@ -23,12 +23,4 @@ #define CLIC_INTCFG 0x800 #define CLIC_CFG 0xc00 -/* CLIC relative CSR number */ -#define CSR_MTVT (0x307) -#define CSR_MNXTI (0x345) -#define CSR_MINTTHRESH (0x347) -#define CSR_MISELECT (0x350) -#define CSR_MIREG (0x351) -#define CSR_MIREG2 (0x352) - #endif /* _SIFIVE_CLIC_H */ diff --git a/soc/bflb/common/e24/intc_clic.S b/soc/bflb/common/e24/intc_clic.S deleted file mode 100644 index 418e332c67ab4..0000000000000 --- a/soc/bflb/common/e24/intc_clic.S +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2024 Baumer Electric AG - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief Assembler-hooks specific to RISC-V Core Local Interrupt Controller - */ - -#include -#include "clic.h" - - -/* register-wide load/store based on lw/sw (XLEN = 32) */ - -.macro lr, rd, mem -lw \rd, \mem -.endm - -.macro sr, rs, mem -sw \rs, \mem -.endm - - -GTEXT(__soc_handle_irq) -/* - * In an CLIC, pending interrupts don't have to be cleared by hand. - * In vectored mode, interrupts are cleared automatically. - * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in - * __soc_handle_all_irqs). - * Thus this function can directly return. - */ -SECTION_FUNC(exception.other, __soc_handle_irq) - ret - -GTEXT(__soc_handle_all_irqs) - -#ifdef CONFIG_TRACING -/* imports */ -GTEXT(sys_trace_isr_enter) -GTEXT(sys_trace_isr_exit) -#endif - -/* - * This function services and clears all pending interrupts for an CLIC in non-vectored mode. - */ -SECTION_FUNC(exception.other, __soc_handle_all_irqs) - addi sp, sp, -16 - sr ra, 0(sp) - - /* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return - * original interrupt if no others appear. */ - csrrci a0, CSR_MNXTI, MSTATUS_IEN - beqz a0, irq_done /* Check if original interrupt vanished. */ - -irq_loop: - -#ifdef CONFIG_TRACING_ISR - call sys_trace_isr_enter -#endif - - /* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with - * the mtvt, sw irq table is 2-pointer wide -> shift by one. */ - csrr t0, CSR_MTVT - sub a0, a0, t0 - la t0, _sw_isr_table - slli a0, a0, (1) - add t0, t0, a0 - - /* Load argument in a0 register */ - lr a0, 0(t0) - - /* Load ISR function address in register t1 */ - lr t1, RV_REGSIZE(t0) - - /* Call ISR function */ - jalr ra, t1, 0 - -#ifdef CONFIG_TRACING_ISR - call sys_trace_isr_exit -#endif - - /* Read and clear mnxti to get highest current interrupt and enable interrupts. */ - csrrci a0, CSR_MNXTI, MSTATUS_IEN - bnez a0, irq_loop - -irq_done: - lr ra, 0(sp) - addi sp, sp, 16 - ret diff --git a/soc/bflb/common/e24/soc.c b/soc/bflb/common/e24/soc.c new file mode 100644 index 0000000000000..0a6ba2fbff27d --- /dev/null +++ b/soc/bflb/common/e24/soc.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define MSTATUS_IEN (1UL << 3) + +void soc_prep_hook(void) +{ + int tmp; + /* Disable IRQs for init to avoid crash, idle thread will re-enable */ + __asm__ volatile ("csrrc %0, mstatus, %1" + : "=r" (tmp) + : "rK" (MSTATUS_IEN) + : "memory"); +} diff --git a/soc/espressif/common/Kconfig.defconfig b/soc/espressif/common/Kconfig.defconfig index 23924f8612133..337895ded15d7 100644 --- a/soc/espressif/common/Kconfig.defconfig +++ b/soc/espressif/common/Kconfig.defconfig @@ -1,7 +1,7 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 +if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 || SOC_SERIES_ESP32H2 config GEN_ISR_TABLES default y if !SOC_ESP32C6_LPCORE @@ -30,6 +30,7 @@ config XTAL_FREQ_HZ config SYS_CLOCK_HW_CYCLES_PER_SEC default 10400000 if XTAL_FREQ_HZ = 26000000 + default 16000000 if XTAL_FREQ_HZ = 32000000 default 16000000 if XTAL_FREQ_HZ = 40000000 config SYS_CLOCK_TICKS_PER_SEC @@ -51,7 +52,7 @@ config ROM_START_OFFSET endif # BOOTLOADER_MCUBOOT -endif # SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 +endif # SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 || SOC_SERIES_ESP32H2 if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 diff --git a/soc/espressif/common/Kconfig.esptool b/soc/espressif/common/Kconfig.esptool index c62fad44f0b8a..09684e3985c66 100644 --- a/soc/espressif/common/Kconfig.esptool +++ b/soc/espressif/common/Kconfig.esptool @@ -85,6 +85,7 @@ config ESPTOOLPY_FLASHMODE choice ESPTOOLPY_FLASHFREQ prompt "Flash SPI speed" default ESPTOOLPY_FLASHFREQ_40M if SOC_SERIES_ESP32 + default ESPTOOLPY_FLASHFREQ_48M if SOC_SERIES_ESP32H2 default ESPTOOLPY_FLASHFREQ_60M if SOC_SERIES_ESP32C2 default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT @@ -107,7 +108,8 @@ config ESPTOOLPY_FLASHFREQ_80M config ESPTOOLPY_FLASHFREQ_60M bool "60 MHz" - +config ESPTOOLPY_FLASHFREQ_48M + bool "48 MHz" config ESPTOOLPY_FLASHFREQ_40M bool "40 MHz" @@ -133,6 +135,7 @@ config ESPTOOLPY_FLASHFREQ default '80m' if ESPTOOLPY_FLASHFREQ_120M default '80m' if ESPTOOLPY_FLASHFREQ_80M default '60m' if ESPTOOLPY_FLASHFREQ_60M + default '48m' if ESPTOOLPY_FLASHFREQ_48M default '40m' if ESPTOOLPY_FLASHFREQ_40M default '26m' if ESPTOOLPY_FLASHFREQ_26M default '20m' if ESPTOOLPY_FLASHFREQ_20M diff --git a/soc/espressif/common/Kconfig.flash b/soc/espressif/common/Kconfig.flash index d38da38c79735..949d7f5d750ec 100644 --- a/soc/espressif/common/Kconfig.flash +++ b/soc/espressif/common/Kconfig.flash @@ -94,7 +94,7 @@ config BOOTLOADER_FLASH_XMC_SUPPORT choice BOOTLOADER_VDDSDIO_BOOST bool "VDDSDIO LDO voltage" default BOOTLOADER_VDDSDIO_BOOST_1_9V - depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6 + depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6 && !SOC_SERIES_ESP32H2 help If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse or MTDI bootstrapping pin), bootloader will change LDO settings to diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c index 625bfb3cc0ae9..d4a907ceda9a0 100644 --- a/soc/espressif/common/loader.c +++ b/soc/espressif/common/loader.c @@ -24,7 +24,7 @@ #include #include -#include +#include #if CONFIG_SOC_SERIES_ESP32C6 #include @@ -270,7 +270,7 @@ void __start(void) "la gp, __global_pointer$\n" ".option pop"); - z_bss_zero(); + arch_bss_zero(); #else /* xtensa */ @@ -279,7 +279,7 @@ void __start(void) /* Move the exception vector table to IRAM. */ __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); - z_bss_zero(); + arch_bss_zero(); __asm__ __volatile__("" : : "g"(&__bss_start) : "memory"); diff --git a/soc/espressif/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c index 74ebae29052e1..55bc5fd028e4f 100644 --- a/soc/espressif/esp32/esp32-mp.c +++ b/soc/espressif/esp32/esp32-mp.c @@ -22,7 +22,6 @@ #ifdef CONFIG_SMP #include -#include #ifndef CONFIG_SOC_ESP32_PROCPU static struct k_spinlock loglock; diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c index 6aacc61b0e1c6..11ced8dc95924 100644 --- a/soc/espressif/esp32/soc.c +++ b/soc/espressif/esp32/soc.c @@ -16,7 +16,7 @@ #include #include -extern void z_prep_c(void); +extern FUNC_NORETURN void z_prep_c(void); extern void esp_reset_reason_init(void); void IRAM_ATTR __esp_platform_app_start(void) diff --git a/soc/espressif/esp32/soc_appcpu.c b/soc/espressif/esp32/soc_appcpu.c index 32305009336fd..a682a87753c67 100644 --- a/soc/espressif/esp32/soc_appcpu.c +++ b/soc/espressif/esp32/soc_appcpu.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include @@ -38,7 +38,7 @@ void __appcpu_start(void); static HDR_ATTR void (*_entry_point)(void) = &__appcpu_start; -extern void z_prep_c(void); +extern FUNC_NORETURN void z_prep_c(void); static void core_intr_matrix_clear(void) { @@ -65,7 +65,7 @@ void IRAM_ATTR __appcpu_start(void) : "r"(&_init_start)); /* Zero out BSS. Clobber _bss_start to avoid memset() elision. */ - z_bss_zero(); + arch_bss_zero(); __asm__ __volatile__ ( "" diff --git a/soc/espressif/esp32c2/soc.c b/soc/espressif/esp32c2/soc.c index c20f02f3734bb..c552ae2169578 100644 --- a/soc/espressif/esp32c2/soc.c +++ b/soc/espressif/esp32c2/soc.c @@ -13,9 +13,10 @@ #include #include #include -#include +#include extern void esp_reset_reason_init(void); +extern FUNC_NORETURN void z_cstart(void); void IRAM_ATTR __esp_platform_app_start(void) { diff --git a/soc/espressif/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c index ee6227338a953..7e2546c243ba1 100644 --- a/soc/espressif/esp32c3/soc.c +++ b/soc/espressif/esp32c3/soc.c @@ -14,9 +14,10 @@ #include #include #include -#include +#include extern void esp_reset_reason_init(void); +extern FUNC_NORETURN void z_cstart(void); void IRAM_ATTR __esp_platform_app_start(void) { diff --git a/soc/espressif/esp32c6/soc.c b/soc/espressif/esp32c6/soc.c index 4fc7c10c0fa9d..f709351d6f0fb 100644 --- a/soc/espressif/esp32c6/soc.c +++ b/soc/espressif/esp32c6/soc.c @@ -13,9 +13,10 @@ #include #include #include -#include +#include extern void esp_reset_reason_init(void); +extern FUNC_NORETURN void z_cstart(void); void IRAM_ATTR __esp_platform_app_start(void) { diff --git a/soc/espressif/esp32c6/soc_lpcore.c b/soc/espressif/esp32c6/soc_lpcore.c index e2e5a5d2b53cf..a687d4af35d5f 100644 --- a/soc/espressif/esp32c6/soc_lpcore.c +++ b/soc/espressif/esp32c6/soc_lpcore.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "soc/soc_caps.h" #include "esp_rom_caps.h" #include "rom/ets_sys.h" @@ -12,9 +13,9 @@ #include "ulp_lp_core_memory_shared.h" #include "ulp_lp_core_print.h" #include -#include extern void main(void); +extern FUNC_NORETURN void z_cstart(void); /* Initialize lp core related system functions before calling user's main*/ void lp_core_startup(void) diff --git a/soc/espressif/esp32h2/CMakeLists.txt b/soc/espressif/esp32h2/CMakeLists.txt new file mode 100644 index 0000000000000..0248ccef51e47 --- /dev/null +++ b/soc/espressif/esp32h2/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + vectors.S + soc_irq.S + soc.c + ../common/loader.c + ) + +zephyr_include_directories(.) + +zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c) diff --git a/soc/espressif/esp32h2/Kconfig b/soc/espressif/esp32h2/Kconfig new file mode 100644 index 0000000000000..e5974e87a7923 --- /dev/null +++ b/soc/espressif/esp32h2/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32H2 + select RISCV + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING + select DYNAMIC_INTERRUPTS + select CLOCK_CONTROL + select PINCTRL + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select HAS_ESPRESSIF_HAL diff --git a/soc/espressif/esp32h2/Kconfig.defconfig b/soc/espressif/esp32h2/Kconfig.defconfig new file mode 100644 index 0000000000000..558dff5b6df9c --- /dev/null +++ b/soc/espressif/esp32h2/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32H2 + +config NUM_IRQS + default 32 + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +config MAIN_STACK_SIZE + default 2048 + +endif # SOC_SERIES_ESP32H2 diff --git a/soc/espressif/esp32h2/Kconfig.soc b/soc/espressif/esp32h2/Kconfig.soc new file mode 100644 index 0000000000000..c1f76ae06833d --- /dev/null +++ b/soc/espressif/esp32h2/Kconfig.soc @@ -0,0 +1,38 @@ +# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32H2 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + +config SOC_ESP32_H2_MINI_H2 + bool + select SOC_ESP32H2 + +config SOC_ESP32_H2_MINI_H4 + bool + select SOC_ESP32H2 + +config SOC_ESP32_H2_WROOM_02C_H2 + bool + select SOC_ESP32H2 + +config SOC_ESP32_H2_WROOM_02C_H4 + bool + select SOC_ESP32H2 + +config SOC_ESP32H2 + bool + select SOC_SERIES_ESP32H2 + +config SOC_SERIES + default "esp32h2" if SOC_SERIES_ESP32H2 + +config SOC + default "esp32h2" if SOC_ESP32H2 + +config SOC_PART_NUMBER + default "ESP32_H2_MINI_1_H2S" if SOC_ESP32_H2_MINI_H2 + default "ESP32_H2_MINI_1_H4S" if SOC_ESP32_H2_MINI_H4 + default "ESP32_H2_WROOM_02C_H2S" if SOC_ESP32_H2_WROOM_02C_H2 + default "ESP32_H2_WROOM_02C_H4S" if SOC_ESP32_H2_WROOM_02C_H4 diff --git a/soc/espressif/esp32h2/default.ld b/soc/espressif/esp32h2/default.ld new file mode 100644 index 0000000000000..c933a43425801 --- /dev/null +++ b/soc/espressif/esp32h2/default.ld @@ -0,0 +1,870 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include "memory.h" + +/* The "user_sram_end" represents the 2nd stage bootloader + * "iram_loader_seg" start address (that should not be overlapped). + * If no bootloader is used, we can extend it to gain more user ram. + */ +#ifdef CONFIG_ESP_SIMPLE_BOOT +user_sram_end = DRAM_BUFFERS_START; +#else +user_sram_end = BOOTLOADER_IRAM_LOADER_SEG_START; +#endif + +/* User available memory segments */ +user_sram_org = HPSRAM_START; +user_sram_size = (user_sram_end - user_sram_org); + +/* Aliases */ +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define RAMABLE_REGION sram0_0_seg +#define ROMABLE_REGION FLASH + +#undef GROUP_DATA_LINK_IN +#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion + +#undef GROUP_NOLOAD_LINK_IN +#define GROUP_NOLOAD_LINK_IN(vregion, lregion) > vregion + +/* Flash segments (rodata and text) should be mapped in the virtual address spaces. + * Executing directly from LMA is not possible. */ +#undef GROUP_ROM_LINK_IN +#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion + +/* Make sure new sections have consistent alignment between input and output sections */ +#undef SECTION_DATA_PROLOGUE +#define SECTION_DATA_PROLOGUE(name, options, align) name options : ALIGN_WITH_INPUT + +#undef SECTION_PROLOGUE +#define SECTION_PROLOGUE SECTION_DATA_PROLOGUE + +/* Global symbols required for espressif hal build */ +MEMORY +{ +#ifdef CONFIG_BOOTLOADER_MCUBOOT + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x60 + FLASH (R): org = 0x80, len = FLASH_SIZE - 0x80 +#else + /* Make safety margin in the FLASH memory size so the + * (esp_img_header + (n*esp_seg_headers)) would fit */ + FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 +#endif + + sram0_0_seg(RW): org = user_sram_org, len = user_sram_size + + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN + + lp_ram_seg(RW): org = LPSRAM_IRAM_START, + len = 0x4000 - CONFIG_RESERVE_RTC_MEM + + /* We reduced the size of lp_ram_seg by CONFIG_RESERVE_RTC_MEM value. + It reserves the amount of LP memory that we use for this memory segment. + This segment is intended for keeping: + - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on). + The aim of this is to keep data that will not be moved around and have a fixed address. + */ +#if (CONFIG_RESERVE_RTC_MEM > 0) + lp_reserved_seg(RW) : org = LPSRAM_IRAM_START + 0x4000 - CONFIG_RESERVE_RTC_MEM, + len = CONFIG_RESERVE_RTC_MEM +#endif + +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* The lines below define location alias for .rtc.data section + * H2 has no distinguished LP(RTC) fast and slow memory sections, + * instead, there is a unified LP_RAM section + * Thus, the following region segments are + * not configurable like on other targets + */ +REGION_ALIAS("rtc_iram_seg", lp_ram_seg ); +REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_data_location", rtc_iram_seg ); + +/* Default entry point: */ +ENTRY(CONFIG_KERNEL_ENTRY) + +/* Heap size calculations */ +_heap_sentry = DRAM_RESERVED_START; +_libc_heap_size = _heap_sentry - _end; + +SECTIONS +{ +#ifdef CONFIG_BOOTLOADER_MCUBOOT + /* Reserve space for MCUboot header in the binary */ + .mcuboot_header : + { + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + } > mcuboot_hdr + .metadata : + { + /* 0. Magic byte for load header */ + LONG(0xace637d3) + + /* 1. Application entry point address */ + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * 2. Destination address (VMA) for IRAM region + * 3. Flash offset (LMA) for start of IRAM region + * 4. Size of IRAM region + */ + LONG(ADDR(.iram0.text)) + LONG(LOADADDR(.iram0.text)) + LONG(LOADADDR(.iram0.data) - LOADADDR(.iram0.text)) + + /* DRAM metadata: + * 5. Destination address (VMA) for DRAM region + * 6. Flash offset (LMA) for start of DRAM region + * 7. Size of DRAM region + */ + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data)) + + /* LP_IRAM metadata: + * 8. Destination address (VMA) for LP_IRAM region + * 9. Flash offset (LMA) for start of LP_IRAM region + * 10. Size of LP_IRAM region + */ + LONG(ADDR(.rtc.text)) + LONG(LOADADDR(.rtc.text)) + LONG(SIZEOF(.rtc.text)) + + /* LP_DATA metadata: + * 11. Destination address (VMA) for LP_DRAM region + * 12. Flash offset (LMA) for start of LP_DRAM region + * 13. Size of LP_DRAM region + */ + LONG(ADDR(.rtc.data)) + LONG(LOADADDR(.rtc.data)) + LONG(SIZEOF(.rtc.data)) + + /* IROM metadata: + * 14. Destination address (VMA) for IROM region + * 15. Flash offset (LMA) for start of IROM region + * 16. Size of IROM region + */ + LONG(ADDR(.flash.text)) + LONG(LOADADDR(.flash.text)) + LONG(SIZEOF(.flash.text)) + + /* DROM metadata: + * 17. Destination address (VMA) for DROM region + * 18. Flash offset (LMA) for start of DROM region + * 19. Size of DROM region + */ + LONG(ADDR(.flash.rodata)) + LONG(LOADADDR(.flash.rodata)) + LONG(LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata)) + } > metadata +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ + + #include + +#ifdef CONFIG_LLEXT + #include +#endif + + /* --- START OF RTC --- */ + .rtc.text : + { + . = ALIGN(4); + _rtc_fast_start = ABSOLUTE(.); + _rtc_text_start = ABSOLUTE(.); + *(.rtc.entry.text) + *(.rtc.literal .rtc.literal.* .rtc.text .rtc.text.*) + . = ALIGN(4); + _rtc_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION) + + /* This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4); + _rtc_force_fast_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION) + + /* RTC data section holds data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data .rtc.data.*) + *(.rtc.rodata .rtc.rodata.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION) + + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *(.rtc.bss .rtc.bss.*) + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(lp_ram_seg) + + /* This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD) : + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } GROUP_LINK_IN(lp_ram_seg) + + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4); + _rtc_force_slow_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION) + + /** + * This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ +#if (CONFIG_RESERVE_RTC_MEM > 0) + .rtc_reserved (NOLOAD) : + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + _rtc_reserved_end = ABSOLUTE(.); + } GROUP_LINK_IN(lp_reserved_seg) +#endif + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + + /* --- END OF RTC --- */ + + /* --- START OF IRAM --- */ + + .iram0.text : ALIGN(4) + { + /* Vectors go to IRAM */ + _iram_start = ABSOLUTE(.); + _init_start = ABSOLUTE(.); + + KEEP(*(.exception_vectors.text)); + . = ALIGN(256); + + _invalid_pc_placeholder = ABSOLUTE(.); + + KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ + *(.exception.other*) + . = ALIGN(4); + + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN(4); + + _init_end = ABSOLUTE(.); + _iram_text_start = ABSOLUTE(.); + + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libzephyr.a:panic.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:soc_flash_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:console_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:soc_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:hw_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:soc_random.*(.literal .text .literal.* .text.*) + + *libarch__riscv__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:esp32h2_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_*.*(.literal .text .literal.* .text.*) + *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*) + *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libgcov.a:(.literal .text .literal.* .text.*) + *libphy.a:( .phyiram .phyiram.*) + *librtc.a:(.literal .text .literal.* .text.*) + + /* [mapping:hal] */ + *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) + *libzephyr.a:modem_clock_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:modem_clock.*(.literal .literal.* .text .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_ops.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:reset_reason.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:pmu_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:pmu_param.*(.literal .literal.* .text .text.*) + *libzephyr.a:pmu_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_crc.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_sys.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_uart.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_efuse.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_regi2c_esp32h2.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*) + + . = ALIGN(4) + 16; + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +#ifdef CONFIG_ESP_SIMPLE_BOOT + .loader.text : + { + . = ALIGN(4); + _loader_text_start = ABSOLUTE(.); + *libzephyr.a:bootloader_clock_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_wdt.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:bootloader_sha.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_ops.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_qio_mode.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_common.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_flash_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_flash_spi_init.*(.literal .text .literal.* .text.*) + + *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + + *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*) + + /* TODO: optimise */ + *libzephyr.a:esp_gpio_reserve.*(.literal .text .literal.* .text.*) + + . = ALIGN(4) + 16; + _loader_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + + .iram0.text_end (NOLOAD) : + { + /* H2 memprot requires 512 B alignment for split lines */ + . = ALIGN(16); + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + . = ALIGN(16) + 16; + } GROUP_LINK_IN(RAMABLE_REGION) + + /* --- END OF IRAM --- */ + + /* --- START OF DRAM --- */ + + .dram0.data : + { + . = ALIGN(4); + _data_start = ABSOLUTE(.); + __data_start = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + +#ifdef CONFIG_RISCV_GP + . = ALIGN(8); + __global_pointer$ = . + 0x800; +#endif /* CONFIG_RISCV_GP */ + + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + + /* All dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libkernel.a:fatal.*(.rodata .rodata.* .srodata .srodata.*) + *libkernel.a:init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.* .srodata .srodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.* .srodata .srodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:periph_ctrl.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:soc_flash_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:console_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:soc_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:hw_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:soc_random.*(.rodata .rodata.* .srodata .srodata.*) + + *libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:hal] */ + *libzephyr.a:efuse_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:modem_clock_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:modem_clock.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_ops.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:flash_qio_mode.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.* .srodata .srodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + *libzephyr.a:pmu_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:pmu_param.*(.rodata .rodata.* .srodata .srodata.*) + + /* [mapping:esp_system] */ + *libzephyr.a:reset_reason.*(.rodata .rodata.*) + *libzephyr.a:esp_err.*(.rodata .rodata.*) + *(.rodata.esp_system_abort) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_crc.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_rom_sys.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_rom_uart.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_rom_efuse.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_rom_regi2c_esp32h2.*(.rodata .rodata.* .srodata .srodata.*) + + *libphy.a:(.rodata .rodata.* .srodata .srodata.*) + + . = ALIGN(4); + #include + . = ALIGN(4); + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +#ifdef CONFIG_ESP_SIMPLE_BOOT + /* Secondary loader sections */ + .loader.data : + { + . = ALIGN(4); + _loader_data_start = ABSOLUTE(.); + *libzephyr.a:bootloader_clock_init.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_wdt.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_flash.*(.srodata .srodata.* .rodata .rodata.*) + *libzephyr.a:bootloader_clock_loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_common_loader.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:bootloader_panic.*(.rodata .rodata.* .srodata .srodata.*) + + *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_clk.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_mmap.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:flash_ops.*(.rodata .rodata.* .srodata .srodata.*) + + *libzephyr.a:esp_gpio_reserve.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_common.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .srodata .srodata.*) + *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .srodata .srodata.*) + + . = ALIGN(16); + _loader_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) +#endif /* CONFIG_ESP_SIMPLE_BOOT */ + + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + _data_end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + .dram0.noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + __bss_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (16); + __bss_end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Provide total SRAM usage, including IRAM and DRAM */ + _image_ram_start = _iram_start; + #include + + ASSERT(((_end - ORIGIN(sram0_0_seg)) <= LENGTH(sram0_0_seg)), "SRAM code/data does not fit.") + + /* --- END OF DRAM --- */ + + /* --- START OF .flash.text --- */ + + .flash.align_text (NOLOAD): + { + /* Subsequent segment lma align */ + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + /* Symbols used during the application memory mapping */ + _image_irom_start = LOADADDR(.flash.text); + _image_irom_size = SIZEOF(.flash.text); + _image_irom_vaddr = ADDR(.flash.text); + + .flash.text : ALIGN(0x10) + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + _text_start = ABSOLUTE(.); + _instruction_reserved_start = ABSOLUTE(.); + __text_region_start = ABSOLUTE(.); + __rom_region_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.*) + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + + *(.fini.literal) + *(.fini) + + *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _instruction_reserved_end = ABSOLUTE(.); + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); + __text_region_end = ABSOLUTE(.); + __rom_region_end = ABSOLUTE(.); + _etext = .; + + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + + /* --- END OF .flash.text --- */ + + /* --- START OF .rodata --- */ + + /* Align next section to 64k to allow mapping */ + .flash.align_rom (NOLOAD) : + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + /* Symbols used during the application memory mapping */ + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = _image_rodata_end - _image_rodata_start; + _image_drom_vaddr = ADDR(.flash.rodata); + + .flash.rodata : ALIGN(0x10) + { + _rodata_reserved_start = ABSOLUTE(.); + _image_rodata_start = ABSOLUTE(.); + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) + *(.rodata_custom_desc .rodata_custom_desc.*) + + __rodata_region_start = ABSOLUTE(.); + + . = ALIGN(4); + #include + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + __rodata_region_end = .; + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.srodata) + *(.srodata.*) + *(.rodata) + *(.rodata.*) + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + .flash.rodata_end : ALIGN(0x10) + { + . = ALIGN(4); + _rodata_reserved_end = ABSOLUTE(.); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + /* --- END OF .rodata --- */ + +#ifdef CONFIG_GEN_ISR_TABLES + #include +#endif + + #include + /DISCARD/ : { *(.note.GNU-stack) } + + SECTION_PROLOGUE(.riscv.attributes, 0,) + { + KEEP(*(.riscv.attributes)) + KEEP(*(.gnu.attributes)) + } +} diff --git a/soc/espressif/esp32h2/hw_init.c b/soc/espressif/esp32h2/hw_init.c new file mode 100644 index 0000000000000..3eaf036e68e77 --- /dev/null +++ b/soc/espressif/esp32h2/hw_init.c @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "hw_init.h" +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +const static char *TAG = "hw_init"; + +int hardware_init(void) +{ + int err = 0; + + soc_hw_init(); + + ana_reset_config(); + super_wdt_auto_feed(); + + /* By default, these access path filters are enable and allow the + * access to masters only if they are in TEE mode. Since all masters + * except HP CPU boots in REE mode, default setting of these filters + * will deny the access to all masters except HP CPU. + * So, at boot disabling these filters. They will enable as per the + * use case by TEE initialization code. + */ + REG_WRITE(LP_APM_FUNC_CTRL_REG, 0); + REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0); + REG_WRITE(HP_APM_FUNC_CTRL_REG, 0); + +#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE + esp_cpu_configure_region_protection(); +#endif + + bootloader_clock_configure(); + +#ifdef CONFIG_ESP_CONSOLE + /* initialize console, from now on, we can log */ + esp_console_init(); + print_banner(); +#endif /* CONFIG_ESP_CONSOLE */ + + cache_hal_init(); + mmu_hal_init(); + + flash_update_id(); + + err = bootloader_flash_xmc_startup(); + if (err != 0) { + ESP_EARLY_LOGE(TAG, "failed when running XMC startup flow, reboot!"); + return err; + } + + err = read_bootloader_header(); + if (err != 0) { + return err; + } + + err = check_bootloader_validity(); + if (err != 0) { + return err; + } + + err = init_spi_flash(); + if (err != 0) { + return err; + } + + check_wdt_reset(); + config_wdt(); + + soc_random_enable(); + + return 0; +} diff --git a/soc/espressif/esp32h2/mcuboot.ld b/soc/espressif/esp32h2/mcuboot.ld new file mode 100644 index 0000000000000..4856d6d3dac60 --- /dev/null +++ b/soc/espressif/esp32h2/mcuboot.ld @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include "memory.h" + +/* Disable all romable LMA */ +#undef GROUP_DATA_LINK_IN +#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion + +#define RAMABLE_REGION dram_seg +#define RODATA_REGION dram_seg +#define ROMABLE_REGION dram_seg + +/* Global symbols required for espressif hal build */ +MEMORY +{ + iram_seg (RX) : org = BOOTLOADER_IRAM_SEG_START, + len = BOOTLOADER_IRAM_SEG_LEN + iram_loader_seg (RX) : org = BOOTLOADER_IRAM_LOADER_SEG_START, + len = BOOTLOADER_IRAM_LOADER_SEG_LEN + dram_seg (RW) : org = BOOTLOADER_DRAM_SEG_START, + len = BOOTLOADER_DRAM_SEG_LEN + +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +ENTRY(CONFIG_KERNEL_ENTRY) + +SECTIONS +{ + .iram0.loader_text : + { + . = ALIGN (16); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + + *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*) + *libkernel.a:device.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*) + + *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*) + *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_system_abort .text.esp_system_abort) + + *(.fini.literal) + *(.fini) + *(.gnu.version) + _loader_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram0.text : + { + /* Vectors go to IRAM */ + _iram_start = ABSOLUTE(.); + _init_start = ABSOLUTE(.); + __text_region_start = ABSOLUTE(.); + + KEEP(*(.exception_vectors.text)); + . = ALIGN(256); + + _invalid_pc_placeholder = ABSOLUTE(.); + + _iram_text_start = ABSOLUTE(.); + + KEEP(*(.exception.entry*)); /* contains _isr_wrapper */ + *(.exception.other*) + . = ALIGN(4); + + *(.entry.text) + *(.init.literal) + *(.init) + . = ALIGN(4); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + + /* H2 memprot requires 512 B alignment for split lines */ + . = ALIGN (16); + _init_end = ABSOLUTE(.); + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + + *(.literal .text .literal.* .text.*) + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + __text_region_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } > iram_seg + + .dram0.data : + { + . = ALIGN(4); + __data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) +#ifdef CONFIG_RISCV_GP + __global_pointer$ = . + 0x800; +#endif /* CONFIG_RISCV_GP */ + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + + #include + . = ALIGN(4); + + *(.rodata_desc .rodata_desc.*) + *(.rodata_custom_desc .rodata_custom_desc.*) + + . = ALIGN(4); + #include + . = ALIGN(4); + + *(.rodata) + *(.rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + __rodata_region_end = .; + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + *(.srodata) + *(.srodata.*) + *(.rodata) + *(.rodata.*) + *(.rodata_wlog) + *(.rodata_wlog*) + _thread_local_end = ABSOLUTE(.); + /* _rodata_reserved_end = ABSOLUTE(.); */ + . = ALIGN(4); + } > dram_seg + + #include + #include + #include + #include + #include + + #include + #include + #include + #include + #include + #include + + #include + + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + } > dram_seg + + /* Shared RAM */ + .bss (NOLOAD): + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + __bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } > dram_seg + + /* linker rel sections*/ + #include + +#ifdef CONFIG_GEN_ISR_TABLES + #include +#endif + +#include + /DISCARD/ : { *(.note.GNU-stack) } + + SECTION_PROLOGUE(.riscv.attributes, 0,) + { + KEEP(*(.riscv.attributes)) + KEEP(*(.gnu.attributes)) + } +} diff --git a/soc/espressif/esp32h2/memory.h b/soc/espressif/esp32h2/memory.h new file mode 100644 index 0000000000000..61db5c3bfc126 --- /dev/null +++ b/soc/espressif/esp32h2/memory.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/* LP-SRAM (4kB) memory */ +#define LPSRAM_IRAM_START DT_REG_ADDR(DT_NODELABEL(sramlp)) +#define LPSRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sramlp)) + +/* HP-SRAM (320kB) memory */ +#define HPSRAM_START DT_REG_ADDR(DT_NODELABEL(sramhp)) +#define HPSRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sramhp)) +#define HPSRAM_DRAM_START HPSRAM_START +#define HPSRAM_IRAM_START HPSRAM_START +/* ICache size is fixed to 16KB on ESP32-H2 */ +#define ICACHE_SIZE 0x4000 + +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-H2 ROM static data usage is as follows: + * - 0x4083ba78 - 0x4084d380: Shared buffers, used in UART/USB/SPI download mode only + * - 0x4084d380 - 0x4084f380: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x4084f380 - 0x4084fee0: ROM .bss and .data (reclaimable) + * - 0x4084fee0 - 0x40850000: ROM .bss and .data (cannot be freed) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x4084d380). + */ + +#define DRAM_BUFFERS_START 0x4083ba78 +#define DRAM_BUFFERS_END 0x4084d380 +#define DRAM_STACK_START DRAM_BUFFERS_END +#define DRAM_ROM_BSS_DATA_START 0x4084f380 + +/* Set the limit for the application runtime dynamic allocations */ +#define DRAM_RESERVED_START DRAM_BUFFERS_END + +/* For safety margin between bootloader data section and startup stacks */ +#define BOOTLOADER_STACK_OVERHEAD 0x0 +/* These lengths can be adjusted, if necessary: FIXME: optimize ram usage */ +#define BOOTLOADER_DRAM_SEG_LEN 0xA000 +#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x3000 +#define BOOTLOADER_IRAM_SEG_LEN 0xC000 + +/* Base address used for calculating memory layout + * counted from Dbus backwards and back to the Ibus + */ +#define BOOTLOADER_USER_SRAM_END (DRAM_BUFFERS_START - BOOTLOADER_STACK_OVERHEAD) + +/* Start of the lower region is determined by region size and the end of the higher region */ +#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_USER_SRAM_END - BOOTLOADER_IRAM_LOADER_SEG_LEN) +#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) +#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN) + +/* Flash */ +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x400000 +#endif + +/* Cached memory */ +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#define DROM_SEG_ORG 0x42800000 +#define DROM_SEG_LEN FLASH_SIZE diff --git a/soc/espressif/esp32h2/pinctrl_soc.h b/soc/espressif/esp32h2/pinctrl_soc.h new file mode 100644 index 0000000000000..ac1bfba5b4b92 --- /dev/null +++ b/soc/espressif/esp32h2/pinctrl_soc.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * ESP32H2 SoC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_RISCV_ESP32H2_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RISCV_ESP32H2_PINCTRL_SOC_H_ + +#include +#include + +#include + +/** @cond INTERNAL_HIDDEN */ + +/** Type for ESP32 pin. */ +typedef struct pinctrl_soc_pin { + /** Pinmux settings (pin, direction and signal). */ + uint32_t pinmux; + /** Pincfg settings (bias). */ + uint32_t pincfg; +} pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize pinmux field in #pinctrl_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx) + +/** + * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_ESP32_PINCFG_INIT(node_id) \ + (((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \ + ((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \ + ((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \ + ((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \ + ((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \ + ((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \ + ((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \ + ((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \ + ((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT)) + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + {.pinmux = Z_PINCTRL_ESP32_PINMUX_INIT(node_id, prop, idx), \ + .pincfg = Z_PINCTRL_ESP32_PINCFG_INIT(node_id)}, + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +/** @endcond */ + +#endif /* ZEPHYR_SOC_RISCV_ESP32H2_PINCTRL_SOC_H_ */ diff --git a/soc/espressif/esp32h2/soc.c b/soc/espressif/esp32h2/soc.c new file mode 100644 index 0000000000000..c74e807f03909 --- /dev/null +++ b/soc/espressif/esp32h2/soc.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void esp_reset_reason_init(void); +extern FUNC_NORETURN void z_cstart(void); + +void IRAM_ATTR __esp_platform_app_start(void) +{ + esp_reset_reason_init(); + + esp_timer_early_init(); + + esp_flash_config(); + + esp_efuse_init_virtual(); + + /* Start Zephyr */ + z_cstart(); + + CODE_UNREACHABLE; +} + +void IRAM_ATTR __esp_platform_mcuboot_start(void) +{ + /* Start Zephyr */ + z_cstart(); + + CODE_UNREACHABLE; +} + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int IRAM_ATTR arch_printk_char_out(int c) +{ + if (c == '\n') { + esp_rom_uart_tx_one_char('\r'); + } + esp_rom_uart_tx_one_char(c); + return 0; +} + +void sys_arch_reboot(int type) +{ + esp_restart(); +} diff --git a/soc/espressif/esp32h2/soc.h b/soc/espressif/esp32h2/soc.h new file mode 100644 index 0000000000000..b7590d4c7d0e0 --- /dev/null +++ b/soc/espressif/esp32h2/soc.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __SOC_H__ +#define __SOC_H__ + +#ifndef _ASMLANGUAGE +#include +#include +#include +#include +#include +#include +#endif + +/* ECALL Exception numbers */ +#define SOC_MCAUSE_ECALL_EXP 11 /* Machine ECALL instruction */ +#define SOC_MCAUSE_USER_ECALL_EXP 8 /* User ECALL instruction */ + +/* Interrupt Mask */ +#define SOC_MCAUSE_IRQ_MASK (1 << 31) +/* Exception code Mask */ +#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF + +#ifndef _ASMLANGUAGE + +void __esp_platform_mcuboot_start(void); +void __esp_platform_app_start(void); + +static inline uint32_t esp_core_id(void) +{ + return 0; +} + +extern void esp_reset_reason_init(void); +extern void esp_rom_route_intr_matrix(int cpu_no, uint32_t model_num, uint32_t intr_num); +extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); +extern void esp_rom_uart_attach(void); +extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no); +extern int esp_rom_uart_tx_one_char(uint8_t chr); +extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, bool inverted); +extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index, bool out_inverted, + bool out_enabled_inverted); +extern void esp_rom_ets_set_user_start(uint32_t start); +extern void esprv_intc_int_set_threshold(int priority_threshold); +uint32_t soc_intr_get_next_source(void); +extern void esp_rom_Cache_Resume_ICache(uint32_t autoload); +extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size); +extern uint32_t esp_rom_Cache_Suspend_ICache(void); +extern void esp_rom_Cache_Invalidate_ICache_All(void); +extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, + uint32_t psize, uint32_t num, uint32_t fixed); +extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, + uint32_t psize, uint32_t num, uint32_t fixed); + +#endif /* _ASMLANGUAGE */ + +#endif /* __SOC_H__ */ diff --git a/soc/espressif/esp32h2/soc_irq.S b/soc/espressif/esp32h2/soc_irq.S new file mode 100644 index 0000000000000..90c016792fd31 --- /dev/null +++ b/soc/espressif/esp32h2/soc_irq.S @@ -0,0 +1,15 @@ +/* Copyright 2025 Espressif Systems (Shanghai) PTE LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* Exports */ +GTEXT(__soc_handle_irq) + +SECTION_FUNC(exception.other, __soc_handle_irq) + + /* int status clearing is done at ISR */ + ret diff --git a/soc/espressif/esp32h2/vectors.S b/soc/espressif/esp32h2/vectors.S new file mode 100644 index 0000000000000..1e1910ea602d2 --- /dev/null +++ b/soc/espressif/esp32h2/vectors.S @@ -0,0 +1,35 @@ +/* Copyright 2025 Espressif Systems (Shanghai) PTE LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "soc/interrupt_reg.h" +#include "riscv/rvruntime-frames.h" +#include "soc/soc_caps.h" +#include + +/* Imports */ +GTEXT(_isr_wrapper) + + /* This is the vector table. MTVEC points here. + * + * Use 4-byte intructions here. 1 instruction = 1 entry of the table. + * The CPU jumps to MTVEC (i.e. the first entry) in case of an exception, + * and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt. + * + * Note: for our CPU, we need to place this on a 256-byte boundary, as CPU + * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00). + */ + + .global _vector_table + .section .exception_vectors.text + .balign 0x100 + .type _vector_table, @function + +_vector_table: + .option push + .option norvc + .rept (32) + j _isr_wrapper /* 32 identical entries, all pointing to the interrupt handler */ + .endr diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c index 8f673a13096e8..3666d695dccb7 100644 --- a/soc/espressif/esp32s2/soc.c +++ b/soc/espressif/esp32s2/soc.c @@ -15,7 +15,7 @@ #include #include -extern void z_prep_c(void); +extern FUNC_NORETURN void z_prep_c(void); extern void esp_reset_reason_init(void); void IRAM_ATTR __esp_platform_app_start(void) diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c index 7aef841382d33..e01b4f8b04fd7 100644 --- a/soc/espressif/esp32s3/soc.c +++ b/soc/espressif/esp32s3/soc.c @@ -16,7 +16,7 @@ #include #include -extern void z_prep_c(void); +extern FUNC_NORETURN void z_prep_c(void); extern void esp_reset_reason_init(void); static void IRAM_ATTR esp_errata(void) diff --git a/soc/espressif/esp32s3/soc_appcpu.c b/soc/espressif/esp32s3/soc_appcpu.c index 517b1e187d753..4cb0e404857ef 100644 --- a/soc/espressif/esp32s3/soc_appcpu.c +++ b/soc/espressif/esp32s3/soc_appcpu.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include @@ -38,7 +38,7 @@ void __appcpu_start(void); static HDR_ATTR void (*_entry_point)(void) = &__appcpu_start; -extern void z_prep_c(void); +extern FUNC_NORETURN void z_prep_c(void); static void core_intr_matrix_clear(void) { @@ -57,7 +57,7 @@ void IRAM_ATTR __appcpu_start(void) __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); /* Zero out BSS. Clobber _bss_start to avoid memset() elision. */ - z_bss_zero(); + arch_bss_zero(); __asm__ __volatile__("" : : "g"(&__bss_start) : "memory"); diff --git a/soc/espressif/soc.yml b/soc/espressif/soc.yml index cd20df8a60b1c..a883b3b792810 100644 --- a/soc/espressif/soc.yml +++ b/soc/espressif/soc.yml @@ -28,3 +28,6 @@ family: cpuclusters: - name: hpcore - name: lpcore + - name: esp32h2 + socs: + - name: esp32h2 diff --git a/soc/intel/intel_adsp/ace/multiprocessing.c b/soc/intel/intel_adsp/ace/multiprocessing.c index 3616861ea0f45..bb39d0f5a855b 100644 --- a/soc/intel/intel_adsp/ace/multiprocessing.c +++ b/soc/intel/intel_adsp/ace/multiprocessing.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/soc/intel/intel_adsp/cavs/multiprocessing.c b/soc/intel/intel_adsp/cavs/multiprocessing.c index 0e837872ab96d..c3601ee7a0885 100644 --- a/soc/intel/intel_adsp/cavs/multiprocessing.c +++ b/soc/intel/intel_adsp/cavs/multiprocessing.c @@ -2,7 +2,6 @@ * SPDX-License-Identifier: Apache-2.0 */ #include -#include #include #include #include diff --git a/soc/ite/ec/it51xxx/chip_chipregs.h b/soc/ite/ec/it51xxx/chip_chipregs.h index 725a696e47443..54fcf65de79a4 100644 --- a/soc/ite/ec/it51xxx/chip_chipregs.h +++ b/soc/ite/ec/it51xxx/chip_chipregs.h @@ -91,8 +91,12 @@ struct smfi_it51xxx_regs { struct gpio_it51xxx_regs { /* 0x00: General Control */ volatile uint8_t GPIO_GCR; - /* 0x01-CF: Reserved_01_cf */ - volatile uint8_t reserved_01_cf[207]; + /* 0x01-C1: Reserved_01_c1 */ + volatile uint8_t reserved_01_c1[193]; + /* 0xC2: General Control 35 */ + volatile uint8_t GPIO_GCR35; + /* 0xC3-CF: Reserved_c3_cf */ + volatile uint8_t reserved_c3_cf[13]; /* 0xD0: General Control 31 */ volatile uint8_t GPIO_GCR31; /* 0xD1: General Control 32 */ @@ -194,6 +198,8 @@ struct gpio_it51xxx_regs { /* 0x00: General Control */ #define IT51XXX_GPIO_LPCRSTEN (BIT(2) | BIT(1)) #define ITE_EC_GPIO_LPCRSTEN IT51XXX_GPIO_LPCRSTEN +/* 0xC2: General Control 35 */ +#define IT51XXX_GPIO_USBPDEN BIT(5) /* 0xF0: General Control 1 */ #define IT51XXX_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2) #define IT51XXX_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0) @@ -333,6 +339,24 @@ struct gctrl_it51xxx_regs { #define gctrl_ite_ec_regs gctrl_it51xxx_regs #define GCTRL_ITE_EC_REGS_BASE GCTRL_IT51XXX_REGS_BASE +/** + * + * (22xxh) Battery-backed SRAM (BRAM) registers + * + */ +#ifndef __ASSEMBLER__ +/* Battery backed RAM indices. */ +#define BRAM_MAGIC_FIELD_OFFSET 0x7c + +enum bram_indices { + /* This field is used to indicate BRAM is valid or not. */ + BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET, + BRAM_IDX_VALID_FLAGS1, + BRAM_IDX_VALID_FLAGS2, + BRAM_IDX_VALID_FLAGS3 +}; +#endif /* !__ASSEMBLER__ */ + /** * * (42xxh) SMBus Interface for target (SMB) registers diff --git a/soc/ite/ec/it51xxx/soc.c b/soc/ite/ec/it51xxx/soc.c index cb1aa52bf7944..648e5cb39ce7e 100644 --- a/soc/ite/ec/it51xxx/soc.c +++ b/soc/ite/ec/it51xxx/soc.c @@ -117,6 +117,9 @@ void soc_prep_hook(void) struct gpio_ite_ec_regs *const gpio_regs = GPIO_ITE_EC_REGS_BASE; struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE; + /* USB pull down disable */ + gpio_regs->GPIO_GCR35 &= ~IT51XXX_GPIO_USBPDEN; + /* Set FSPI pins are tri-state */ sys_write8(sys_read8(IT51XXX_SMFI_FLHCTRL3R) | IT51XXX_SMFI_FFSPITRI, IT51XXX_SMFI_FLHCTRL3R); diff --git a/soc/native/inf_clock/CMakeLists.txt b/soc/native/inf_clock/CMakeLists.txt index 494ea4de774ba..199ca6d4a2e57 100644 --- a/soc/native/inf_clock/CMakeLists.txt +++ b/soc/native/inf_clock/CMakeLists.txt @@ -17,3 +17,5 @@ zephyr_library_include_directories( ) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/posix/linker.ld CACHE INTERNAL "") + +zephyr_library_sources_ifdef(CONFIG_CPU_FREQ cpu_freq.c) diff --git a/soc/native/inf_clock/Kconfig b/soc/native/inf_clock/Kconfig index fe452074fede8..4e86c8cd21bf8 100644 --- a/soc/native/inf_clock/Kconfig +++ b/soc/native/inf_clock/Kconfig @@ -4,6 +4,7 @@ config SOC_POSIX select ARCH_POSIX select CPU_HAS_FPU + select HAS_CPU_FREQ if SOC_POSIX diff --git a/soc/native/inf_clock/cpu_freq.c b/soc/native/inf_clock/cpu_freq.c new file mode 100644 index 0000000000000..30b1a9694a856 --- /dev/null +++ b/soc/native/inf_clock/cpu_freq.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(native_sim_cpu_freq, CONFIG_CPU_FREQ_LOG_LEVEL); + +struct native_sim_config { + int state_id; +}; + +int cpu_freq_pstate_set(const struct pstate *state) +{ + if (state == NULL) { + LOG_ERR("pstate is NULL"); + return -EINVAL; + } + + int state_id = ((const struct native_sim_config *)state->config)->state_id; + + LOG_DBG("Setting performance state: %d", state_id); + + switch (state_id) { + case 0: + LOG_DBG("Setting P-state 0: Nominal Mode"); + break; + case 1: + LOG_DBG("Setting P-state 1: Low Power Mode"); + break; + case 2: + LOG_DBG("Setting P-state 2: Ultra-low Power Mode"); + break; + default: + LOG_ERR("Unsupported P-state: %d", state_id); + return -1; + } + + return 0; +} + +#define DEFINE_NATIVE_SIM_CONFIG(node_id) \ + static const struct native_sim_config _CONCAT(native_sim_config_, node_id) = { \ + .state_id = DT_PROP(node_id, pstate_id), \ + }; \ + PSTATE_DT_DEFINE(node_id, &_CONCAT(native_sim_config_, node_id)) + +DT_FOREACH_CHILD_STATUS_OKAY(DT_PATH(performance_states), DEFINE_NATIVE_SIM_CONFIG) diff --git a/soc/native/inf_clock/posix_soc.h b/soc/native/inf_clock/posix_soc.h index 8c0c16f5952ff..c1eb2f54b6980 100644 --- a/soc/native/inf_clock/posix_soc.h +++ b/soc/native/inf_clock/posix_soc.h @@ -7,6 +7,7 @@ #ifndef _POSIX_POSIX_SOC_INF_CLOCK_H #define _POSIX_POSIX_SOC_INF_CLOCK_H +#include #include #ifdef __cplusplus diff --git a/soc/nordic/Kconfig.sysbuild b/soc/nordic/Kconfig.sysbuild index a726d20c464be..040a04203bf11 100644 --- a/soc/nordic/Kconfig.sysbuild +++ b/soc/nordic/Kconfig.sysbuild @@ -4,5 +4,6 @@ config HAS_NORDIC_VPR_LAUNCHER_IMAGE bool +rsource "common/uicr/Kconfig.sysbuild" rsource "common/vpr/Kconfig.sysbuild" orsource "*/Kconfig.sysbuild" diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt index 825be4842fb72..04f0c1a3219c4 100644 --- a/soc/nordic/common/CMakeLists.txt +++ b/soc/nordic/common/CMakeLists.txt @@ -3,9 +3,7 @@ add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) -if(CONFIG_NRF_PERIPHCONF_SECTION OR CONFIG_NRF_HALTIUM_GENERATE_UICR) - add_subdirectory(uicr) -endif() +add_subdirectory(uicr) # Let SystemInit() be called in place of soc_reset_hook() by default. zephyr_linker_symbol(SYMBOL soc_reset_hook EXPR "@SystemInit@") diff --git a/soc/nordic/common/uicr/CMakeLists.txt b/soc/nordic/common/uicr/CMakeLists.txt index 0bde6b47f5766..1ec3a35c56658 100644 --- a/soc/nordic/common/uicr/CMakeLists.txt +++ b/soc/nordic/common/uicr/CMakeLists.txt @@ -4,33 +4,3 @@ if(CONFIG_NRF_PERIPHCONF_SECTION) zephyr_linker_sources(SECTIONS uicr.ld) endif() - -if(CONFIG_NRF_HALTIUM_GENERATE_UICR) - if(CONFIG_NRF_PERIPHCONF_SECTION) - set(in_periphconf_elf_arg - --in-periphconf-elf $ - ) - endif() - - if(CONFIG_NRF_HALTIUM_UICR_PERIPHCONF) - set(periphconf_hex_file ${PROJECT_BINARY_DIR}/periphconf.hex) - set(out_periphconf_hex_arg - --out-periphconf-hex ${periphconf_hex_file} - ) - list(APPEND optional_byproducts ${periphconf_hex_file}) - endif() - - set(uicr_hex_file ${PROJECT_BINARY_DIR}/uicr.hex) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${CMAKE_COMMAND} -E env PYTHONPATH=${ZEPHYR_BASE}/scripts/dts/python-devicetree/src - ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_LIST_DIR}/gen_uicr.py - --in-config ${DOTCONFIG} - --in-edt-pickle ${EDT_PICKLE} - ${in_periphconf_elf_arg} - ${out_periphconf_hex_arg} - --out-uicr-hex ${uicr_hex_file} - ) - set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts - ${uicr_hex_file} ${optional_byproducts} - ) -endif() diff --git a/soc/nordic/common/uicr/Kconfig b/soc/nordic/common/uicr/Kconfig index f132510a7a5d0..3c4c6c8219b6b 100644 --- a/soc/nordic/common/uicr/Kconfig +++ b/soc/nordic/common/uicr/Kconfig @@ -1,29 +1,9 @@ # Copyright (c) 2025 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config NRF_HALTIUM_GENERATE_UICR - bool "Generate UICR file" - depends on SOC_NRF54H20_CPUAPP - default y - help - Generate UICR HEX file. - -if NRF_HALTIUM_GENERATE_UICR - -config NRF_HALTIUM_UICR_PERIPHCONF - bool "Initialize global domain peripherals" - default y - help - Generates a blob containing static global domain peripheral initialization - values extracted from the build artifacts, and configures UICR.PERIPHCONF - to point at the blob. The initialization values are then loaded ahead of - ahead of the application boot. - -endif - config NRF_PERIPHCONF_SECTION bool "Populate global peripheral initialization section" - default y if SOC_NRF54H20_CPUAPP + default y if SOC_NRF54H20_CPUAPP || SOC_NRF54H20_CPURAD depends on LINKER_DEVNULL_SUPPORT imply LINKER_DEVNULL_MEMORY help diff --git a/soc/nordic/common/uicr/Kconfig.sysbuild b/soc/nordic/common/uicr/Kconfig.sysbuild new file mode 100644 index 0000000000000..eb885beaaaf7d --- /dev/null +++ b/soc/nordic/common/uicr/Kconfig.sysbuild @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config NRF_HALTIUM_GENERATE_UICR + bool "Generate UICR file" + depends on SOC_SERIES_NRF54HX + default y + help + Generate UICR HEX file. diff --git a/soc/nordic/common/uicr/gen_uicr.py b/soc/nordic/common/uicr/gen_uicr.py index 50f96eab566f7..78422e4312cd4 100644 --- a/soc/nordic/common/uicr/gen_uicr.py +++ b/soc/nordic/common/uicr/gen_uicr.py @@ -7,25 +7,20 @@ import argparse import ctypes as c -import math -import pickle -import re import sys -from collections import defaultdict from itertools import groupby from elftools.elf.elffile import ELFFile from intelhex import IntelHex +# The UICR format version produced by this script +UICR_FORMAT_VERSION_MAJOR = 2 +UICR_FORMAT_VERSION_MINOR = 0 + # Name of the ELF section containing PERIPHCONF entries. # Must match the name used in the linker script. PERIPHCONF_SECTION = "uicr_periphconf_entry" -# Expected nodelabel of the UICR devicetree node, used to extract its location from the devicetree. -UICR_NODELABEL = "uicr" -# Nodelabel of the PERIPHCONF devicetree node, used to extract its location from the devicetree. -PERIPHCONF_NODELABEL = "periphconf_partition" - # Common values for representing enabled/disabled in the UICR format. ENABLED_VALUE = 0xFFFF_FFFF DISABLED_VALUE = 0xBD23_28A8 @@ -45,6 +40,14 @@ class PeriphconfEntry(c.LittleEndianStructure): PERIPHCONF_ENTRY_SIZE = c.sizeof(PeriphconfEntry) +class Version(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("MINOR", c.c_uint16), + ("MAJOR", c.c_uint16), + ] + + class Approtect(c.LittleEndianStructure): _pack_ = 1 _fields_ = [ @@ -63,23 +66,38 @@ class Protectedmem(c.LittleEndianStructure): ] -class Recovery(c.LittleEndianStructure): +class Wdtstart(c.LittleEndianStructure): _pack_ = 1 _fields_ = [ ("ENABLE", c.c_uint32), - ("PROCESSOR", c.c_uint32), - ("INITSVTOR", c.c_uint32), - ("SIZE4KB", c.c_uint32), + ("INSTANCE", c.c_uint32), + ("CRV", c.c_uint32), + ] + + +class SecurestorageCrypto(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("APPLICATIONSIZE1KB", c.c_uint32), + ("RADIOCORESIZE1KB", c.c_uint32), + ] + + +class SecurestorageIts(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("APPLICATIONSIZE1KB", c.c_uint32), + ("RADIOCORESIZE1KB", c.c_uint32), ] -class Its(c.LittleEndianStructure): +class Securestorage(c.LittleEndianStructure): _pack_ = 1 _fields_ = [ ("ENABLE", c.c_uint32), ("ADDRESS", c.c_uint32), - ("APPLICATIONSIZE", c.c_uint32), - ("RADIOCORESIZE", c.c_uint32), + ("CRYPTO", SecurestorageCrypto), + ("ITS", SecurestorageIts), ] @@ -101,21 +119,82 @@ class Mpcconf(c.LittleEndianStructure): ] +class SecondaryTrigger(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("RESETREAS", c.c_uint32), + ("RESERVED", c.c_uint32), + ] + + +class SecondaryProtectedmem(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("SIZE4KB", c.c_uint32), + ] + + +class SecondaryWdtstart(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("INSTANCE", c.c_uint32), + ("CRV", c.c_uint32), + ] + + +class SecondaryPeriphconf(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("ADDRESS", c.c_uint32), + ("MAXCOUNT", c.c_uint32), + ] + + +class SecondaryMpcconf(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("ADDRESS", c.c_uint32), + ("MAXCOUNT", c.c_uint32), + ] + + +class Secondary(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("PROCESSOR", c.c_uint32), + ("TRIGGER", SecondaryTrigger), + ("ADDRESS", c.c_uint32), + ("PROTECTEDMEM", SecondaryProtectedmem), + ("WDTSTART", SecondaryWdtstart), + ("PERIPHCONF", SecondaryPeriphconf), + ("MPCCONF", SecondaryMpcconf), + ] + + class Uicr(c.LittleEndianStructure): _pack_ = 1 _fields_ = [ - ("VERSION", c.c_uint32), + ("VERSION", Version), ("RESERVED", c.c_uint32), ("LOCK", c.c_uint32), ("RESERVED1", c.c_uint32), ("APPROTECT", Approtect), ("ERASEPROTECT", c.c_uint32), ("PROTECTEDMEM", Protectedmem), - ("RECOVERY", Recovery), - ("ITS", Its), - ("RESERVED2", c.c_uint32 * 7), + ("WDTSTART", Wdtstart), + ("RESERVED2", c.c_uint32), + ("SECURESTORAGE", Securestorage), + ("RESERVED3", c.c_uint32 * 5), ("PERIPHCONF", Periphconf), ("MPCCONF", Mpcconf), + ("SECONDARY", Secondary), + ("PADDING", c.c_uint32 * 15), ] @@ -129,18 +208,6 @@ def main() -> None: "peripherals, and to protect the device in various ways." ), ) - parser.add_argument( - "--in-config", - required=True, - type=argparse.FileType("r"), - help="Path to the .config file from the application build", - ) - parser.add_argument( - "--in-edt-pickle", - required=True, - type=argparse.FileType("rb"), - help="Path to the edt.pickle file from the application build", - ) parser.add_argument( "--in-periphconf-elf", dest="in_periphconf_elfs", @@ -153,67 +220,204 @@ def main() -> None: "by ascending address and cleared of duplicate entries." ), ) + parser.add_argument( + "--out-merged-hex", + required=True, + type=argparse.FileType("w", encoding="utf-8"), + help="Path to write the merged UICR+PERIPHCONF HEX file to", + ) parser.add_argument( "--out-uicr-hex", required=True, type=argparse.FileType("w", encoding="utf-8"), - help="Path to write the generated UICR HEX file to", + help="Path to write the UICR-only HEX file to", ) parser.add_argument( "--out-periphconf-hex", + type=argparse.FileType("w", encoding="utf-8"), + help="Path to write the PERIPHCONF-only HEX file to", + ) + parser.add_argument( + "--periphconf-address", + default=None, + type=lambda s: int(s, 0), + help="Absolute flash address of the PERIPHCONF partition (decimal or 0x-prefixed hex)", + ) + parser.add_argument( + "--periphconf-size", + default=None, + type=lambda s: int(s, 0), + help="Size in bytes of the PERIPHCONF partition (decimal or 0x-prefixed hex)", + ) + parser.add_argument( + "--uicr-address", + required=True, + type=lambda s: int(s, 0), + help="Absolute flash address of the UICR region (decimal or 0x-prefixed hex)", + ) + parser.add_argument( + "--secondary", + action="store_true", + help="Enable secondary firmware support in UICR", + ) + parser.add_argument( + "--secondary-address", default=None, + type=lambda s: int(s, 0), + help="Absolute flash address of the secondary firmware (decimal or 0x-prefixed hex)", + ) + parser.add_argument( + "--secondary-periphconf-address", + default=None, + type=lambda s: int(s, 0), + help=( + "Absolute flash address of the secondary PERIPHCONF partition " + "(decimal or 0x-prefixed hex)" + ), + ) + parser.add_argument( + "--secondary-periphconf-size", + default=None, + type=lambda s: int(s, 0), + help="Size in bytes of the secondary PERIPHCONF partition (decimal or 0x-prefixed hex)", + ) + parser.add_argument( + "--in-secondary-periphconf-elf", + dest="in_secondary_periphconf_elfs", + default=[], + action="append", + type=argparse.FileType("rb"), + help=( + "Path to an ELF file to extract secondary PERIPHCONF data from. " + "Can be provided multiple times. The secondary PERIPHCONF data from each ELF file " + "is combined in a single list which is sorted by ascending address and cleared " + "of duplicate entries." + ), + ) + parser.add_argument( + "--out-secondary-periphconf-hex", type=argparse.FileType("w", encoding="utf-8"), - help="Path to write the generated PERIPHCONF HEX file to", + help="Path to write the secondary PERIPHCONF-only HEX file to", ) args = parser.parse_args() try: + # Validate argument dependencies + if args.out_periphconf_hex: + if args.periphconf_address is None: + raise ScriptError( + "--periphconf-address is required when --out-periphconf-hex is used" + ) + if args.periphconf_size is None: + raise ScriptError("--periphconf-size is required when --out-periphconf-hex is used") + + # Validate secondary argument dependencies + if args.secondary and args.secondary_address is None: + raise ScriptError("--secondary-address is required when --secondary is used") + + if args.out_secondary_periphconf_hex: + if args.secondary_periphconf_address is None: + raise ScriptError( + "--secondary-periphconf-address is required when " + "--out-secondary-periphconf-hex is used" + ) + if args.secondary_periphconf_size is None: + raise ScriptError( + "--secondary-periphconf-size is required when " + "--out-secondary-periphconf-hex is used" + ) + init_values = DISABLED_VALUE.to_bytes(4, "little") * (c.sizeof(Uicr) // 4) uicr = Uicr.from_buffer_copy(init_values) - kconfig_str = args.in_config.read() - kconfig = parse_kconfig(kconfig_str) + uicr.VERSION.MAJOR = UICR_FORMAT_VERSION_MAJOR + uicr.VERSION.MINOR = UICR_FORMAT_VERSION_MINOR - edt = pickle.load(args.in_edt_pickle) + # Process periphconf data first and configure UICR completely before creating hex objects + periphconf_hex = IntelHex() + secondary_periphconf_hex = IntelHex() - try: - periphconf_partition = edt.label2node[PERIPHCONF_NODELABEL] - except LookupError as e: - raise ScriptError( - "Failed to find a PERIPHCONF partition in the devicetree. " - f"Expected a DT node with label '{PERIPHCONF_NODELABEL}'." - ) from e + if args.out_periphconf_hex: + periphconf_combined = extract_and_combine_periphconfs(args.in_periphconf_elfs) - flash_base_address = periphconf_partition.flash_controller.regs[0].addr - periphconf_address = flash_base_address + periphconf_partition.regs[0].addr - periphconf_size = periphconf_partition.regs[0].size + padding_len = args.periphconf_size - len(periphconf_combined) + periphconf_final = periphconf_combined + bytes([0xFF for _ in range(padding_len)]) - periphconf_combined = extract_and_combine_periphconfs(args.in_periphconf_elfs) - padding_len = periphconf_size - len(periphconf_combined) - periphconf_final = periphconf_combined + bytes([0xFF for _ in range(padding_len)]) + # Add periphconf data to periphconf hex object + periphconf_hex.frombytes(periphconf_final, offset=args.periphconf_address) - if kconfig.get("CONFIG_NRF_HALTIUM_UICR_PERIPHCONF") == "y": + # Configure UICR with periphconf settings uicr.PERIPHCONF.ENABLE = ENABLED_VALUE - uicr.PERIPHCONF.ADDRESS = periphconf_address - uicr.PERIPHCONF.MAXCOUNT = math.floor(periphconf_size / 8) + uicr.PERIPHCONF.ADDRESS = args.periphconf_address + + # MAXCOUNT is given in number of 8-byte peripheral + # configuration entries and periphconf_size is given in + # bytes. When setting MAXCOUNT based on the + # periphconf_size we must first assert that + # periphconf_size has not been misconfigured. + if args.periphconf_size % 8 != 0: + raise ScriptError( + f"args.periphconf_size was {args.periphconf_size}, but must be divisible by 8" + ) - try: - uicr_node = edt.label2node[UICR_NODELABEL] - except LookupError as e: - raise ScriptError( - "Failed to find UICR node in the devicetree. " - f"Expected a DT node with label '{UICR_NODELABEL}'." - ) from e + uicr.PERIPHCONF.MAXCOUNT = args.periphconf_size // 8 + # Handle secondary firmware configuration + if args.secondary: + uicr.SECONDARY.ENABLE = ENABLED_VALUE + uicr.SECONDARY.ADDRESS = args.secondary_address + + # Handle secondary periphconf if provided + if args.out_secondary_periphconf_hex: + secondary_periphconf_combined = extract_and_combine_periphconfs( + args.in_secondary_periphconf_elfs + ) + + padding_len = args.secondary_periphconf_size - len(secondary_periphconf_combined) + secondary_periphconf_final = secondary_periphconf_combined + bytes( + [0xFF for _ in range(padding_len)] + ) + + # Add secondary periphconf data to secondary periphconf hex object + secondary_periphconf_hex.frombytes( + secondary_periphconf_final, offset=args.secondary_periphconf_address + ) + + # Configure UICR with secondary periphconf settings + uicr.SECONDARY.PERIPHCONF.ENABLE = ENABLED_VALUE + uicr.SECONDARY.PERIPHCONF.ADDRESS = args.secondary_periphconf_address + + # MAXCOUNT is given in number of 8-byte peripheral + # configuration entries and secondary_periphconf_size is given in + # bytes. When setting MAXCOUNT based on the + # secondary_periphconf_size we must first assert that + # secondary_periphconf_size has not been misconfigured. + if args.secondary_periphconf_size % 8 != 0: + raise ScriptError( + f"args.secondary_periphconf_size was {args.secondary_periphconf_size}, " + f"but must be divisible by 8" + ) + + uicr.SECONDARY.PERIPHCONF.MAXCOUNT = args.secondary_periphconf_size // 8 + + # Create UICR hex object with final UICR data uicr_hex = IntelHex() - uicr_hex.frombytes(bytes(uicr), offset=uicr_node.regs[0].addr) + uicr_hex.frombytes(bytes(uicr), offset=args.uicr_address) - uicr_hex.write_hex_file(args.out_uicr_hex) + # Create merged hex by combining UICR and periphconf hex objects + merged_hex = IntelHex() + merged_hex.fromdict(uicr_hex.todict()) - if args.out_periphconf_hex is not None: - periphconf_hex = IntelHex() - periphconf_hex.frombytes(periphconf_final, offset=periphconf_address) + if args.out_periphconf_hex: periphconf_hex.write_hex_file(args.out_periphconf_hex) + merged_hex.fromdict(periphconf_hex.todict()) + + if args.out_secondary_periphconf_hex: + secondary_periphconf_hex.write_hex_file(args.out_secondary_periphconf_hex) + merged_hex.fromdict(secondary_periphconf_hex.todict()) + + merged_hex.write_hex_file(args.out_merged_hex) + uicr_hex.write_hex_file(args.out_uicr_hex) except ScriptError as e: print(f"Error: {e!s}") @@ -255,16 +459,5 @@ def extract_and_combine_periphconfs(elf_files: list[argparse.FileType]) -> bytes return bytes(final_periphconf) -def parse_kconfig(content: str) -> dict[str, str | None]: - result = defaultdict(None) - match_iter = re.finditer( - r"^(?P(SB_)?CONFIG_[^=\s]+)=(?P[^\s#])+$", content, re.MULTILINE - ) - for match in match_iter: - result[match["config"]] = match["value"] - - return result - - if __name__ == "__main__": main() diff --git a/soc/nordic/common/uicr/gen_uicr/CMakeLists.txt b/soc/nordic/common/uicr/gen_uicr/CMakeLists.txt new file mode 100644 index 0000000000000..1163ff8e21f95 --- /dev/null +++ b/soc/nordic/common/uicr/gen_uicr/CMakeLists.txt @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# The code in this CMakeLists.txt constructs the arguments for gen_uicr.py +# and creates a flashable zephyr.hex file containing UICR data (no C code compiled) +# + +cmake_minimum_required(VERSION 3.20.0) + +# Instead of adding all of Zephyr we add just the subset that is +# required to generate uicr.hex. +# +# The generation of uicr.hex is configured by this image, so we +# include modules from zephyr_default up until kconfig. + +find_package(Zephyr + COMPONENTS zephyr_default:kconfig + REQUIRED HINTS $ENV{ZEPHYR_BASE} + ) + +project(uicr) + +# Function to parse a Kconfig value from a .config file +function(parse_kconfig_value config_file config_name output_var) + file(STRINGS ${config_file} config_lines ENCODING "UTF-8") + foreach(line ${config_lines}) + if("${line}" MATCHES "^${config_name}=\"(.*)\"$") + set(${output_var} "${CMAKE_MATCH_1}" PARENT_SCOPE) + return() + endif() + endforeach() +endfunction() + +# Function to compute partition absolute address and size from devicetree +function(compute_partition_address_and_size partition_nodelabel output_address_var output_size_var) + dt_nodelabel(partition_path NODELABEL ${partition_nodelabel} REQUIRED) + dt_reg_addr(partition_offset PATH ${partition_path} REQUIRED) + dt_reg_size(partition_size PATH ${partition_path} REQUIRED) + + # Calculate absolute partition address + math(EXPR partition_address "${CONFIG_FLASH_BASE_ADDRESS} + ${partition_offset}" OUTPUT_FORMAT HEXADECIMAL) + + # Set output variables in parent scope + set(${output_address_var} ${partition_address} PARENT_SCOPE) + set(${output_size_var} ${partition_size} PARENT_SCOPE) +endfunction() + +# Use CMAKE_VERBOSE_MAKEFILE to silence an unused-variable warning. +if(CMAKE_VERBOSE_MAKEFILE) +endif() + +set(periphconf_args) +set(periphconf_elfs) +set(merged_hex_file ${APPLICATION_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.hex) +set(secondary_periphconf_elfs) +set(uicr_hex_file ${APPLICATION_BINARY_DIR}/zephyr/uicr.hex) +set(periphconf_hex_file ${APPLICATION_BINARY_DIR}/zephyr/periphconf.hex) +set(secondary_periphconf_hex_file ${APPLICATION_BINARY_DIR}/zephyr/secondary_periphconf.hex) + +# Get UICR absolute address from this image's devicetree +dt_nodelabel(uicr_path NODELABEL "uicr" REQUIRED) +dt_reg_addr(UICR_ADDRESS PATH ${uicr_path} REQUIRED) + +if(CONFIG_GEN_UICR_GENERATE_PERIPHCONF) + # gen_uicr.py parses all zephyr.elf files. To find these files (which + # have not been built yet) we scan sibling build directories for + # zephyr.dts + get_filename_component(SYSBUILD_DIR ${APPLICATION_BINARY_DIR} DIRECTORY) + file(GLOB _siblings LIST_DIRECTORIES true "${SYSBUILD_DIR}/*") + foreach(_dir ${_siblings}) + get_filename_component(_name ${_dir} NAME) + if(_name STREQUAL "uicr") + # This image is an exception to the rule. It has a zephyr.dts, but + # no zephyr.elf + continue() + endif() + + if(EXISTS ${_dir}/zephyr/zephyr.dts) + # Read CONFIG_KERNEL_BIN_NAME from the sibling's .config file + parse_kconfig_value(${_dir}/zephyr/.config CONFIG_KERNEL_BIN_NAME kernel_bin_name) + set(kernel_elf_path ${_dir}/zephyr/${kernel_bin_name}.elf) + + # Check if this is secondary firmware by looking for the marker file + if(EXISTS ${_dir}/is_secondary_firmware.txt) + list(APPEND secondary_periphconf_elfs ${kernel_elf_path}) + else() + list(APPEND periphconf_elfs ${kernel_elf_path}) + endif() + endif() + endforeach() + + # Compute PERIPHCONF absolute address and size from this image's devicetree + compute_partition_address_and_size("periphconf_partition" PERIPHCONF_ADDRESS PERIPHCONF_SIZE) + + # Set up periphconf arguments for gen_uicr.py + list(APPEND periphconf_args --periphconf-address ${PERIPHCONF_ADDRESS}) + list(APPEND periphconf_args --periphconf-size ${PERIPHCONF_SIZE}) + list(APPEND periphconf_args --out-periphconf-hex ${periphconf_hex_file}) + + foreach(elf ${periphconf_elfs}) + list(APPEND periphconf_args --in-periphconf-elf ${elf}) + endforeach() +endif(CONFIG_GEN_UICR_GENERATE_PERIPHCONF) + +if(CONFIG_GEN_UICR_SECONDARY) + set(secondary_args --secondary) + + # Compute SECONDARY partition absolute address from this image's devicetree + compute_partition_address_and_size("secondary_partition" SECONDARY_ADDRESS SECONDARY_SIZE) + + list(APPEND secondary_args + --secondary-address ${SECONDARY_ADDRESS} + ) + + if(CONFIG_GEN_UICR_SECONDARY_GENERATE_PERIPHCONF) + # Compute SECONDARY_PERIPHCONF absolute address and size from this image's devicetree + compute_partition_address_and_size("secondary_periphconf_partition" SECONDARY_PERIPHCONF_ADDRESS SECONDARY_PERIPHCONF_SIZE) + + list(APPEND secondary_args --secondary-periphconf-address ${SECONDARY_PERIPHCONF_ADDRESS}) + list(APPEND secondary_args --secondary-periphconf-size ${SECONDARY_PERIPHCONF_SIZE}) + list(APPEND secondary_args --out-secondary-periphconf-hex ${secondary_periphconf_hex_file}) + + foreach(elf ${secondary_periphconf_elfs}) + list(APPEND secondary_args --in-secondary-periphconf-elf ${elf}) + endforeach() + endif() +endif() + +# Generate hex files (merged, uicr-only, periphconf-only, and secondary-periphconf-only) +add_custom_command( + OUTPUT ${merged_hex_file} ${uicr_hex_file} ${periphconf_hex_file} ${secondary_periphconf_hex_file} + COMMAND ${CMAKE_COMMAND} -E env PYTHONPATH=${ZEPHYR_BASE}/scripts/dts/python-devicetree/src + ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/nordic/common/uicr/gen_uicr.py + --uicr-address ${UICR_ADDRESS} + --out-merged-hex ${merged_hex_file} + --out-uicr-hex ${uicr_hex_file} + ${periphconf_args} + ${secondary_args} + DEPENDS ${periphconf_elfs} ${secondary_periphconf_elfs} + WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} + COMMENT "Using gen_uicr.py to generate ${merged_hex_file}, ${uicr_hex_file}, ${periphconf_hex_file}, and ${secondary_periphconf_hex_file} from ${periphconf_elfs} ${secondary_periphconf_elfs}" +) + +# Add zephyr subdirectory to handle flash configuration with correct paths +add_subdirectory(zephyr) + +add_custom_target(gen_uicr ALL DEPENDS ${merged_hex_file} ${uicr_hex_file} ${periphconf_hex_file} ${secondary_periphconf_hex_file}) diff --git a/soc/nordic/common/uicr/gen_uicr/Kconfig b/soc/nordic/common/uicr/gen_uicr/Kconfig new file mode 100644 index 0000000000000..41d31db64647c --- /dev/null +++ b/soc/nordic/common/uicr/gen_uicr/Kconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +menu "UICR generator options" + +config GEN_UICR_GENERATE_PERIPHCONF + bool "Generate PERIPHCONF hex alongside UICR" + default y + help + When enabled, the UICR generator will populate the + periphconf_partition partition. + +config GEN_UICR_SECONDARY + bool "Enable UICR.SECONDARY.ENABLE" + +config GEN_UICR_SECONDARY_GENERATE_PERIPHCONF + bool "Generate SECONDARY.PERIPHCONF hex alongside UICR" + default y + depends on GEN_UICR_SECONDARY + help + When enabled, the UICR generator will populate the + secondary_periphconf_partition partition. + +endmenu + +source "Kconfig.zephyr" diff --git a/soc/nordic/common/uicr/gen_uicr/prj.conf b/soc/nordic/common/uicr/gen_uicr/prj.conf new file mode 100644 index 0000000000000..b2a4ba591044e --- /dev/null +++ b/soc/nordic/common/uicr/gen_uicr/prj.conf @@ -0,0 +1 @@ +# nothing here diff --git a/soc/nordic/common/uicr/gen_uicr/zephyr/CMakeLists.txt b/soc/nordic/common/uicr/gen_uicr/zephyr/CMakeLists.txt new file mode 100644 index 0000000000000..1d02066401611 --- /dev/null +++ b/soc/nordic/common/uicr/gen_uicr/zephyr/CMakeLists.txt @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Flash configuration for UICR domain +# This subdirectory ensures runners.yaml is generated in the correct location + +# Manually include board configuration to enable automatic runners.yaml generation +include(${BOARD_DIR}/board.cmake OPTIONAL) + +# Create the runners_yaml_props_target that flash system expects +add_custom_target(runners_yaml_props_target) + +# Set hex_file property to point to zephyr.hex in this directory +set_target_properties(runners_yaml_props_target PROPERTIES + hex_file "zephyr.hex" +) + +# Override the runners.yaml path to use CMAKE_CURRENT_BINARY_DIR instead of PROJECT_BINARY_DIR +# This ensures runners.yaml is generated at build/uicr/zephyr/ where west expects it +set(PROJECT_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}) + +# Include flash support to automatically generate runners.yaml +include(${ZEPHYR_BASE}/cmake/flash/CMakeLists.txt) diff --git a/soc/nordic/common/uicr/sysbuild.cmake b/soc/nordic/common/uicr/sysbuild.cmake new file mode 100644 index 0000000000000..167ac7c64a2d1 --- /dev/null +++ b/soc/nordic/common/uicr/sysbuild.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Add UICR generator as a utility image +ExternalZephyrProject_Add( + APPLICATION uicr + SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/gen_uicr +) + +# Ensure UICR is configured and built after the default image so EDT/ELFs exist. +sysbuild_add_dependencies(CONFIGURE uicr ${DEFAULT_IMAGE}) +add_dependencies(uicr ${DEFAULT_IMAGE}) diff --git a/soc/nordic/ironside/CMakeLists.txt b/soc/nordic/ironside/CMakeLists.txt index 98e721541d7f3..ea7f68207a89a 100644 --- a/soc/nordic/ironside/CMakeLists.txt +++ b/soc/nordic/ironside/CMakeLists.txt @@ -6,6 +6,7 @@ zephyr_library() zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_CALL call.c) zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_BOOT_REPORT boot_report.c) zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_CPUCONF_SERVICE cpuconf.c) +zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_BOOTMODE_SERVICE bootmode.c) zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_TDD_SERVICE tdd.c) zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_UPDATE_SERVICE update.c) zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_DVFS_SERVICE dvfs.c) diff --git a/soc/nordic/ironside/Kconfig b/soc/nordic/ironside/Kconfig index 3136e3bd5f47f..ce4878b7b182f 100644 --- a/soc/nordic/ironside/Kconfig +++ b/soc/nordic/ironside/Kconfig @@ -56,6 +56,12 @@ config NRF_IRONSIDE_BOOT_REPORT help Support for parsing the Boot Report populated by Nordic IronSide firmware. +config NRF_IRONSIDE_BOOTMODE_SERVICE + bool "IronSide boot mode service" + select NRF_IRONSIDE_CALL + help + Service used to reboot into secondary firmware boot mode. + config NRF_IRONSIDE_DVFS_SERVICE bool "IronSide DVFS service" depends on SOC_NRF54H20_CPUAPP diff --git a/soc/nordic/ironside/bootmode.c b/soc/nordic/ironside/bootmode.c new file mode 100644 index 0000000000000..92ca5e312653c --- /dev/null +++ b/soc/nordic/ironside/bootmode.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +#define BOOT_MODE_SECONDARY (0x1) + +BUILD_ASSERT(IRONSIDE_BOOTMODE_SERVICE_NUM_ARGS <= NRF_IRONSIDE_CALL_NUM_ARGS); + +int ironside_bootmode_secondary_reboot(const uint8_t *msg, size_t msg_size) +{ + int err; + struct ironside_call_buf *buf; + uint8_t *buf_msg; + + if (msg_size > IRONSIDE_BOOTMODE_SERVICE_MSG_MAX_SIZE) { + return -IRONSIDE_BOOTMODE_ERROR_MESSAGE_TOO_LARGE; + } + + buf = ironside_call_alloc(); + + buf->id = IRONSIDE_CALL_ID_BOOTMODE_SERVICE_V1; + + buf->args[IRONSIDE_BOOTMODE_SERVICE_MODE_IDX] = BOOT_MODE_SECONDARY; + + buf_msg = (uint8_t *)&buf->args[IRONSIDE_BOOTMODE_SERVICE_MSG_0_IDX]; + + memset(buf_msg, 0, IRONSIDE_BOOTMODE_SERVICE_MSG_MAX_SIZE); + + if (msg_size > 0) { + memcpy(buf_msg, msg, msg_size); + } + + ironside_call_dispatch(buf); + + if (buf->status == IRONSIDE_CALL_STATUS_RSP_SUCCESS) { + err = buf->args[IRONSIDE_BOOTMODE_SERVICE_RETCODE_IDX]; + } else { + err = buf->status; + } + + ironside_call_release(buf); + + return err; +} diff --git a/soc/nordic/ironside/include/nrf_ironside/boot_report.h b/soc/nordic/ironside/include/nrf_ironside/boot_report.h index 7cd5126753342..c4d31c9dbc59b 100644 --- a/soc/nordic/ironside/include/nrf_ironside/boot_report.h +++ b/soc/nordic/ironside/include/nrf_ironside/boot_report.h @@ -10,57 +10,205 @@ #include /** Constant used to check if an Nordic IronSide SE boot report has been written. */ -#define IRONSIDE_BOOT_REPORT_MAGIC (0x4d69546fUL) +#define IRONSIDE_BOOT_REPORT_MAGIC (0x4d69546fUL) + +/** UICR had no errors. */ +#define IRONSIDE_UICR_SUCCESS 0 +/** There was an unexpected error processing the UICR. */ +#define IRONSIDE_UICR_ERROR_UNEXPECTED 1 +/** The UICR integrity check failed. */ +#define IRONSIDE_UICR_ERROR_INTEGRITY 2 +/** The UICR content check failed. */ +#define IRONSIDE_UICR_ERROR_CONTENT 3 +/** Failed to configure system based on UICR. */ +#define IRONSIDE_UICR_ERROR_CONFIG 4 +/** Unsupported UICR format version. */ +#define IRONSIDE_UICR_ERROR_FORMAT 5 + +/** Error found in UICR.PROTECTEDMEM. */ +#define IRONSIDE_UICR_REGID_PROTECTEDMEM 36 +/** Error found in UICR.SECURESTORAGE. */ +#define IRONSIDE_UICR_REGID_SECURESTORAGE 64 +/** Error found in UICR.PERIPHCONF. */ +#define IRONSIDE_UICR_REGID_PERIPHCONF 104 +/** Error found in UICR.MPCCONF. */ +#define IRONSIDE_UICR_REGID_MPCCONF 116 +/** Error found in UICR.SECONDARY.ADDRESS/SIZE4KB */ +#define IRONSIDE_UICR_REGID_SECONDARY 128 +/** Error found in UICR.SECONDARY.PROTECTEDMEM. */ +#define IRONSIDE_UICR_REGID_SECONDARY_PROTECTEDMEM 152 +/** Error found in UICR.SECONDARY.PERIPHCONF. */ +#define IRONSIDE_UICR_REGID_SECONDARY_PERIPHCONF 172 +/** Error found in UICR.SECONDARY.MPCCONF. */ +#define IRONSIDE_UICR_REGID_SECONDARY_MPCCONF 184 + +/** Failed to mount a CRYPTO secure storage partition in MRAM. */ +#define IRONSIDE_UICR_SECURESTORAGE_ERROR_MOUNT_CRYPTO_FAILED 1 +/** Failed to mount an ITS secure storage partition in MRAM. */ +#define IRONSIDE_UICR_SECURESTORAGE_ERROR_MOUNT_ITS_FAILED 2 +/** The start address and total size of all ITS partitions are not aligned to 4 KB. */ +#define IRONSIDE_UICR_SECURESTORAGE_ERROR_MISALIGNED 3 + +/** There was an unexpected error processing UICR.PERIPHCONF. */ +#define IRONSIDE_UICR_PERIPHCONF_ERROR_UNEXPECTED 1 +/** The address contained in a UICR.PERIPHCONF array entry is not permitted. */ +#define IRONSIDE_UICR_PERIPHCONF_ERROR_NOT_PERMITTED 2 +/** The readback of the value for a UICR.PERIPHCONF array entry did not match. */ +#define IRONSIDE_UICR_PERIPHCONF_ERROR_READBACK_MISMATCH 3 + +/** Booted in secondary mode. */ +#define IRONSIDE_BOOT_MODE_FLAGS_SECONDARY_MASK 0x1 + +/** Booted normally by IronSide SE.*/ +#define IRONSIDE_BOOT_REASON_DEFAULT 0 +/** Booted because of a cpuconf service call by a different core. */ +#define IRONSIDE_BOOT_REASON_CPUCONF_CALL 1 +/** Booted in secondary mode because of a bootmode service call. */ +#define IRONSIDE_BOOT_REASON_BOOTMODE_SECONDARY_CALL 2 +/** Booted in secondary mode because of a boot error in the primary mode. */ +#define IRONSIDE_BOOT_REASON_BOOTERROR 3 +/** Booted in secondary mode because of local domain reset reason trigger. */ +#define IRONSIDE_BOOT_REASON_TRIGGER_RESETREAS 4 +/** Booted in secondary mode via the CTRL-AP. */ +#define IRONSIDE_BOOT_REASON_CTRLAP_SECONDARYMODE 5 + +/** The boot had no errors. */ +#define IRONSIDE_BOOT_ERROR_SUCCESS 0x0 +/** The reset vector for the application firmware was not programmed. */ +#define IRONSIDE_BOOT_ERROR_NO_APPLICATION_FIRMWARE 0x1 +/** The IronSide SE was unable to parse the SysCtrl ROM report. */ +#define IRONSIDE_BOOT_ERROR_ROM_REPORT_INVALID 0x2 +/** The SysCtrl ROM booted the system in current limited mode due to an issue in the BICR. */ +#define IRONSIDE_BOOT_ERROR_ROM_REPORT_CURRENT_LIMITED 0x3 +/** The IronSide SE detected an issue with the HFXO configuration in the BICR. */ +#define IRONSIDE_BOOT_ERROR_BICR_HFXO_INVALID 0x4 +/** The IronSide SE detected an issue with the LFXO configuration in the BICR. */ +#define IRONSIDE_BOOT_ERROR_BICR_LFXO_INVALID 0x5 +/** The IronSide SE failed to boot the SysCtrl Firmware. */ +#define IRONSIDE_BOOT_ERROR_SYSCTRL_START_FAILED 0x6 +/** The UICR integrity check failed. */ +#define IRONSIDE_BOOT_ERROR_UICR_INTEGRITY_FAILED 0x7 +/** The UICR content is not valid */ +#define IRONSIDE_BOOT_ERROR_UICR_CONTENT_INVALID 0x8 +/** Integrity check of PROTECTEDMEM failed. */ +#define IRONSIDE_BOOT_ERROR_UICR_PROTECTEDMEM_INTEGRITY_FAILED 0x9 +/** Failed to configure system based on UICR. */ +#define IRONSIDE_BOOT_ERROR_UICR_CONFIG_FAILED 0xA +/** The IronSide SE failed to mount its own storage. */ +#define IRONSIDE_BOOT_ERROR_SECDOM_STORAGE_MOUNT_FAILED 0xB +/** Failed to initialize DVFS service */ +#define IRONSIDE_BOOT_ERROR_DVFS_INIT_FAILED 0xC +/** Failed to boot secondary application firmware; configuration missing from UICR. */ +#define IRONSIDE_BOOT_ERROR_NO_SECONDARY_APPLICATION_FIRMWARE 0xD +/** Integrity check of secondary PROTECTEDMEM failed. */ +#define IRONSIDE_BOOT_ERROR_UICR_SECONDARY_PROTECTEDMEM_INTEGRITY_FAILED 0xE +/** Unsupported UICR format version. */ +#define IRONSIDE_BOOT_ERROR_UICR_FORMAT_UNSUPPORTED 0xF +/** Value reserved for conditions that should never happen. */ +#define IRONSIDE_BOOT_ERROR_UNEXPECTED 0xff + +/** Index for RESETREAS.DOMAIN[NRF_DOMAIN_APPLICATION]. */ +#define IRONSIDE_SECONDARY_RESETREAS_APPLICATION 0 +/** Index for RESETREAS.DOMAIN[NRF_DOMAIN_RADIOCORE]. */ +#define IRONSIDE_SECONDARY_RESETREAS_RADIOCORE 1 + /** Length of the local domain context buffer in bytes. */ #define IRONSIDE_BOOT_REPORT_LOCAL_DOMAIN_CONTEXT_SIZE (16UL) /** Length of the random data buffer in bytes. */ -#define IRONSIDE_BOOT_REPORT_RANDOM_DATA_SIZE (32UL) - -/** @brief IronSide version structure. */ -struct ironside_version { - /** Wrapping sequence number ranging from 1-126, incremented for each release. */ - uint8_t seqnum; - /** Path version. */ - uint8_t patch; - /** Minor version. */ - uint8_t minor; - /** Major version. */ - uint8_t major; - /** Human readable extraversion string. */ - char extraversion[12]; -}; +#define IRONSIDE_BOOT_REPORT_RANDOM_DATA_SIZE (32UL) -/** @brief UICR error description contained in the boot report. */ -struct ironside_boot_report_uicr_error { - /** The type of error. A value of 0 indicates no error */ - uint32_t error_type; - /** Error descriptions specific to each type of UICR error */ +/** @brief Initialization/boot status description contained in the boot report. */ +struct ironside_boot_report_init_status { + /** Reserved for Future Use. */ + uint8_t rfu1[3]; + /** Boot error for the current boot (same as reported in BOOTSTATUS)*/ + uint8_t boot_error; + /** Overall UICR status. */ + uint8_t uicr_status; + /** Reserved for Future Use. */ + uint8_t rfu2; + /** ID of the register that caused the error. + * Only relevant for IRONSIDE_UICR_ERROR_CONTENT and IRONSIDE_UICR_ERROR_CONFIG. + */ + uint16_t uicr_regid; + /** Additional description for IRONSIDE_UICR_ERROR_CONFIG. */ union { - /** RFU */ + /** UICR.SECURESTORAGE error description. */ struct { - uint32_t rfu[4]; - } rfu; - } description; + /** Reason that UICR.SECURESTORAGE configuration failed. */ + uint16_t status; + /** Owner ID of the failing secure storage partition. + * Only relevant for IRONSIDE_UICR_SECURESTORAGE_ERROR_MOUNT_CRYPTO_FAILED + * and IRONSIDE_UICR_SECURESTORAGE_ERROR_MOUNT_ITS_FAILED. + */ + uint16_t owner_id; + } securestorage; + /** UICR.PERIPHCONF error description. */ + struct { + /** Reason that UICR.PERIPHCONF configuration failed. */ + uint16_t status; + /** Index of the failing entry in the UICR.PERIPHCONF array. */ + uint16_t index; + } periphconf; + } uicr_detail; +}; + +/** @brief Initialization/boot context description contained in the boot report. */ +struct ironside_boot_report_init_context { + /** Reserved for Future Use */ + uint8_t rfu[3]; + /** Reason the processor was started. */ + uint8_t boot_reason; + + union { + /** Data passed from booting local domain to local domain being booted. + * + * Valid if the boot reason is one of the following: + * - IRONSIDE_BOOT_REASON_CPUCONF_CALL + * - IRONSIDE_BOOT_REASON_BOOTMODE_SECONDARY_CALL + */ + uint8_t local_domain_context[IRONSIDE_BOOT_REPORT_LOCAL_DOMAIN_CONTEXT_SIZE]; + + /** Initialiation error that triggered the boot. + * + * Valid if the boot reason is IRONSIDE_BOOT_REASON_BOOTERROR. + */ + struct ironside_boot_report_init_status trigger_init_status; + + /** RESETREAS.DOMAIN that triggered the boot. + * + * Valid if the boot reason is IRONSIDE_BOOT_REASON_TRIGGER_RESETREAS. + */ + uint32_t trigger_resetreas[4]; + }; }; /** @brief IronSide boot report. */ struct ironside_boot_report { /** Magic value used to identify valid boot report */ uint32_t magic; - /** Firmware version of IronSide SE. */ - struct ironside_version ironside_se_version; - /** Firmware version of IronSide SE recovery firmware. */ - struct ironside_version ironside_se_recovery_version; + /** Firmware version of IronSide SE. 8bit MAJOR.MINOR.PATCH.SEQNUM */ + uint32_t ironside_se_version_int; + /** Human readable extraversion of IronSide SE */ + char ironside_se_extraversion[12]; + /** Firmware version of IronSide SE recovery firmware. 8bit MAJOR.MINOR.PATCH.SEQNUM */ + uint32_t ironside_se_recovery_version_int; + /** Human readable extraversion of IronSide SE recovery firmware */ + char ironside_se_recovery_extraversion[12]; /** Copy of SICR.UROT.UPDATE.STATUS.*/ uint32_t ironside_update_status; - /** See @ref ironside_boot_report_uicr_error */ - struct ironside_boot_report_uicr_error uicr_error_description; - /** Data passed from booting local domain to local domain being booted */ - uint8_t local_domain_context[IRONSIDE_BOOT_REPORT_LOCAL_DOMAIN_CONTEXT_SIZE]; + /** Initialization/boot status. */ + struct ironside_boot_report_init_status init_status; + /** Reserved for Future Use */ + uint16_t rfu1; + /** Flags describing the current boot mode. */ + uint16_t boot_mode_flags; + /** Data describing the context under which the CPU was booted. */ + struct ironside_boot_report_init_context init_context; /** CSPRNG data */ uint8_t random_data[IRONSIDE_BOOT_REPORT_RANDOM_DATA_SIZE]; /** Reserved for Future Use */ - uint32_t rfu[64]; + uint32_t rfu2[64]; }; /** diff --git a/soc/nordic/ironside/include/nrf_ironside/bootmode.h b/soc/nordic/ironside/include/nrf_ironside/bootmode.h new file mode 100644 index 0000000000000..4da46f33dd6da --- /dev/null +++ b/soc/nordic/ironside/include/nrf_ironside/bootmode.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_NORDIC_IRONSIDE_INCLUDE_NRF_IRONSIDE_BOOTMODE_H_ +#define ZEPHYR_SOC_NORDIC_IRONSIDE_INCLUDE_NRF_IRONSIDE_BOOTMODE_H_ + +#include +#include +#include + +/** + * @name Boot mode service error codes. + * @{ + */ + +/** Invalid/unsupported boot mode transition. */ +#define IRONSIDE_BOOTMODE_ERROR_UNSUPPORTED_MODE (1) +/** Failed to reboot into the boot mode due to other activity preventing a reset. */ +#define IRONSIDE_BOOTMODE_ERROR_BUSY (2) +/** The boot message is too large to fit in the buffer. */ +#define IRONSIDE_BOOTMODE_ERROR_MESSAGE_TOO_LARGE (3) + +/** + * @} + */ + +/* IronSide call identifiers with implicit versions. */ +#define IRONSIDE_CALL_ID_BOOTMODE_SERVICE_V1 5 + +enum { + IRONSIDE_BOOTMODE_SERVICE_MODE_IDX, + IRONSIDE_BOOTMODE_SERVICE_MSG_0_IDX, + IRONSIDE_BOOTMODE_SERVICE_MSG_1_IDX, + IRONSIDE_BOOTMODE_SERVICE_MSG_2_IDX, + IRONSIDE_BOOTMODE_SERVICE_MSG_3_IDX, + /* The last enum value is reserved for the number of arguments */ + IRONSIDE_BOOTMODE_SERVICE_NUM_ARGS, +}; + +/* Maximum size of the message parameter. */ +#define IRONSIDE_BOOTMODE_SERVICE_MSG_MAX_SIZE (4 * sizeof(uint32_t)) + +/* Index of the return code within the service buffer. */ +#define IRONSIDE_BOOTMODE_SERVICE_RETCODE_IDX (0) + +/** + * @brief Request a reboot into the secondary firmware boot mode. + * + * This invokes the IronSide SE boot mode service to restart the system into the secondary boot + * mode. In this mode, the secondary configuration defined in UICR is applied instead of the + * primary one. The system immediately reboots without a reply if the request succeeds. + * + * The given message data is passed to the boot report of the CPU booted in the secondary boot mode. + * + * @note This function does not return if the request is successful. + * @note The device will boot into the secondary firmware instead of primary firmware. + * @note The request does not fail if the secondary firmware is not defined. + * + * @param msg A message that can be placed in the cpu's boot report. + * @param msg_size Size of the message in bytes. + * + * @retval 0 on success. + * @retval -IRONSIDE_BOOTMODE_ERROR_UNSUPPORTED_MODE if the secondary boot mode is unsupported. + * @retval -IRONSIDE_BOOTMODE_ERROR_BUSY if the reboot was blocked. + * @retval -IRONSIDE_BOOTMODE_ERROR_MESSAGE_TOO_LARGE if msg_size is greater than + * IRONSIDE_BOOTMODE_SERVICE_MSG_MAX_SIZE. + * @retval Positive error status if reported by IronSide call (see error codes in @ref call.h). + */ +int ironside_bootmode_secondary_reboot(const uint8_t *msg, size_t msg_size); + +#endif /* ZEPHYR_SOC_NORDIC_IRONSIDE_INCLUDE_NRF_IRONSIDE_BOOTMODE_H_ */ diff --git a/soc/nordic/ironside/include/nrf_ironside/cpuconf.h b/soc/nordic/ironside/include/nrf_ironside/cpuconf.h index 49e562b136987..b112396704a58 100644 --- a/soc/nordic/ironside/include/nrf_ironside/cpuconf.h +++ b/soc/nordic/ironside/include/nrf_ironside/cpuconf.h @@ -63,10 +63,10 @@ BUILD_ASSERT(IRONSIDE_CPUCONF_NUM_ARGS <= NRF_IRONSIDE_CALL_NUM_ARGS); * If the given msg_size is less than that, the remaining bytes are set to zero. * * @retval 0 on success or if the CPU has already booted. - * @retval Positive non-0 error status if reported by IronSide call. - * @retval -IRONSIDE_CPUCONF_ERROR_WRONG_CPU if cpu is unrecognized + * @retval -IRONSIDE_CPUCONF_ERROR_WRONG_CPU if cpu is unrecognized. * @retval -IRONSIDE_CPUCONF_ERROR_MESSAGE_TOO_LARGE if msg_size is greater than * IRONSIDE_CPUCONF_SERVICE_MSG_MAX_SIZE. + * @retval Positive error status if reported by IronSide call (see error codes in @ref call.h). */ int ironside_cpuconf(NRF_PROCESSORID_Type cpu, const void *vector_table, bool cpu_wait, const uint8_t *msg, size_t msg_size); diff --git a/soc/nordic/ironside/include/nrf_ironside/dvfs.h b/soc/nordic/ironside/include/nrf_ironside/dvfs.h index e2cb03c249e0a..c47cc43a85984 100644 --- a/soc/nordic/ironside/include/nrf_ironside/dvfs.h +++ b/soc/nordic/ironside/include/nrf_ironside/dvfs.h @@ -31,19 +31,19 @@ enum ironside_dvfs_oppoint { */ /** The requested DVFS oppoint is not allowed. */ -#define IRONSIDE_DVFS_ERROR_WRONG_OPPOINT (1) +#define IRONSIDE_DVFS_ERROR_WRONG_OPPOINT (1) /** Waiting for mutex lock timed out, or hardware is busy. */ -#define IRONSIDE_DVFS_ERROR_BUSY (2) +#define IRONSIDE_DVFS_ERROR_BUSY (2) /** There is configuration error in the DVFS service. */ -#define IRONSIDE_DVFS_ERROR_OPPOINT_DATA (3) +#define IRONSIDE_DVFS_ERROR_OPPOINT_DATA (3) /** The caller does not have permission to change the DVFS oppoint. */ -#define IRONSIDE_DVFS_ERROR_PERMISSION (4) +#define IRONSIDE_DVFS_ERROR_PERMISSION (4) /** The requested DVFS oppoint is already set, no change needed. */ #define IRONSIDE_DVFS_ERROR_NO_CHANGE_NEEDED (5) /** The operation timed out, possibly due to a hardware issue. */ -#define IRONSIDE_DVFS_ERROR_TIMEOUT (6) +#define IRONSIDE_DVFS_ERROR_TIMEOUT (6) /** The DVFS oppoint change operation is not allowed in the ISR context. */ -#define IRONSIDE_DVFS_ERROR_ISR_NOT_ALLOWED (7) +#define IRONSIDE_DVFS_ERROR_ISR_NOT_ALLOWED (7) /** * @} @@ -68,7 +68,19 @@ enum ironside_dvfs_oppoint { * specified value. It will block until the change is applied. * * @param dvfs_oppoint The new DVFS oppoint to set. - * @return int 0 on success, negative error code on failure. + * + * @retval 0 on success. + * @retval -IRONSIDE_DVFS_ERROR_WRONG_OPPOINT if the requested DVFS oppoint is not allowed. + * @retval -IRONSIDE_DVFS_ERROR_BUSY if waiting for mutex lock timed out, or hardware is busy. + * @retval -IRONSIDE_DVFS_ERROR_OPPOINT_DATA if there is configuration error in the DVFS service. + * @retval -IRONSIDE_DVFS_ERROR_PERMISSION if the caller does not have permission to change the DVFS + * oppoint. + * @retval -IRONSIDE_DVFS_ERROR_NO_CHANGE_NEEDED if the requested DVFS oppoint is already set. + * @retval -IRONSIDE_DVFS_ERROR_TIMEOUT if the operation timed out, possibly due to a hardware + * issue. + * @retval -IRONSIDE_DVFS_ERROR_ISR_NOT_ALLOWED if the DVFS oppoint change operation is not allowed + * in the ISR context. + * @retval Positive error status if reported by IronSide call (see error codes in @ref call.h). */ int ironside_dvfs_change_oppoint(enum ironside_dvfs_oppoint dvfs_oppoint); @@ -80,8 +92,7 @@ int ironside_dvfs_change_oppoint(enum ironside_dvfs_oppoint dvfs_oppoint); */ static inline bool ironside_dvfs_is_oppoint_valid(enum ironside_dvfs_oppoint dvfs_oppoint) { - if (dvfs_oppoint != IRONSIDE_DVFS_OPP_HIGH && - dvfs_oppoint != IRONSIDE_DVFS_OPP_MEDLOW && + if (dvfs_oppoint != IRONSIDE_DVFS_OPP_HIGH && dvfs_oppoint != IRONSIDE_DVFS_OPP_MEDLOW && dvfs_oppoint != IRONSIDE_DVFS_OPP_LOW) { return false; } diff --git a/soc/nordic/ironside/include/nrf_ironside/tdd.h b/soc/nordic/ironside/include/nrf_ironside/tdd.h index d065b1619a685..adfb1c53a648c 100644 --- a/soc/nordic/ironside/include/nrf_ironside/tdd.h +++ b/soc/nordic/ironside/include/nrf_ironside/tdd.h @@ -31,7 +31,8 @@ enum ironside_se_tdd_config { * @param config The configuration to be applied. * * @retval 0 on success. - * @retval -IRONSIDE_SE_TDD_ERROR_EINVAL on invalid argument. + * @retval -IRONSIDE_SE_TDD_SERVICE_ERROR_INVALID_CONFIG if the configuration is invalid. + * @retval Positive error status if reported by IronSide call (see error codes in @ref call.h). */ int ironside_se_tdd_configure(const enum ironside_se_tdd_config config); diff --git a/soc/nordic/ironside/include/nrf_ironside/update.h b/soc/nordic/ironside/include/nrf_ironside/update.h index 8152a77f5f7c9..b01b5df6dadb1 100644 --- a/soc/nordic/ironside/include/nrf_ironside/update.h +++ b/soc/nordic/ironside/include/nrf_ironside/update.h @@ -40,7 +40,7 @@ /* Index of the update blob pointer within the service buffer. */ #define IRONSIDE_UPDATE_SERVICE_UPDATE_PTR_IDX (0) /* Index of the return code within the service buffer. */ -#define IRONSIDE_UPDATE_SERVICE_RETCODE_IDX (0) +#define IRONSIDE_UPDATE_SERVICE_RETCODE_IDX (0) /** * @brief IronSide update blob. @@ -61,10 +61,10 @@ struct ironside_update_blob { * * @param update Pointer to update blob * + * @retval 0 on a successful request (although the update itself may still fail). * @retval -IRONSIDE_UPDATE_ERROR_NOT_PERMITTED if missing access to the update candidate. * @retval -IRONSIDE_UPDATE_ERROR_SICR_WRITE_FAILED if writing update parameters to SICR failed. - * @returns Positive non-0 error status if reported by IronSide call. - * @returns 0 on a successful request (although the update itself may still fail). + * @retval Positive error status if reported by IronSide call (see error codes in @ref call.h). * */ int ironside_update(const struct ironside_update_blob *update); diff --git a/soc/nordic/nrf53/Kconfig b/soc/nordic/nrf53/Kconfig index 8aade63f54a15..7260d5c7d66d3 100644 --- a/soc/nordic/nrf53/Kconfig +++ b/soc/nordic/nrf53/Kconfig @@ -210,69 +210,6 @@ config BOARD_ENABLE_CPUNET if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM -config SOC_ENABLE_LFXO - bool "LFXO" - select DEPRECATED - help - This option is deprecated, use DT instead. For this option to apply, - make sure to select either "internal" or "external" in the - load-capacitors property. - - Enable the low-frequency oscillator (LFXO) functionality on XL1 and - XL2 pins. - This option must be enabled if either application or network core is - to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular - GPIOs. - -choice SOC_LFXO_LOAD_CAPACITANCE - prompt "LFXO load capacitance" - depends on SOC_ENABLE_LFXO - -config SOC_LFXO_CAP_EXTERNAL - bool "Use external load capacitors" - select DEPRECATED - help - This option is deprecated, use DT instead. Example configuration: - - &lfxo { - load-capacitors = "external"; - }; - -config SOC_LFXO_CAP_INT_6PF - bool "6 pF internal load capacitance" - select DEPRECATED - help - This option is deprecated, use DT instead. Example configuration: - - &lfxo { - load-capacitors = "internal"; - load-capacitance-picofarad = <6>; - }; - -config SOC_LFXO_CAP_INT_7PF - bool "7 pF internal load capacitance" - select DEPRECATED - help - This option is deprecated, use DT instead. Example configuration: - - &lfxo { - load-capacitors = "internal"; - load-capacitance-picofarad = <7>; - }; - -config SOC_LFXO_CAP_INT_9PF - bool "9 pF internal load capacitance" - select DEPRECATED - help - This option is deprecated, use DT instead. Example configuration: - - &lfxo { - load-capacitors = "internal"; - load-capacitance-picofarad = <9>; - }; - -endchoice - choice SOC_HFXO_LOAD_CAPACITANCE prompt "HFXO load capacitance" default SOC_HFXO_CAP_DEFAULT diff --git a/soc/nordic/nrf53/soc.c b/soc/nordic/nrf53/soc.c index e53a3e75231b8..eb01872a71dfc 100644 --- a/soc/nordic/nrf53/soc.c +++ b/soc/nordic/nrf53/soc.c @@ -53,23 +53,23 @@ #define LFXO_NODE DT_NODELABEL(lfxo) #define HFXO_NODE DT_NODELABEL(hfxo) -/* LFXO config from DT */ +/* LFXO config from DT - if the LFXO node has a status of okay, we can assign + * P0.00 and P0.01 to the peripheral and use the load_capacitors property set + * (or default to external if not present). If the LFXO node does not have a + * status of okay, assign the pins for use by the app core. + */ +#if DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) +#define LFXO_PIN_SEL NRF_GPIO_PIN_SEL_PERIPHERAL +#if DT_NODE_HAS_PROP(LFXO_NODE, load_capacitors) #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external) #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL #elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal) #define LFXO_CAP (DT_ENUM_IDX(LFXO_NODE, load_capacitance_picofarad) + 1U) -#else -/* LFXO config from legacy Kconfig */ -#if defined(CONFIG_SOC_LFXO_CAP_INT_6PF) -#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_6PF -#elif defined(CONFIG_SOC_LFXO_CAP_INT_7PF) -#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_7PF -#elif defined(CONFIG_SOC_LFXO_CAP_INT_9PF) -#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_9PF +#endif /*DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external) */ #else #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL -#endif -#endif +#endif /* DT_NODE_HAS_PROP(LFXO_NODE, load_capacitors) */ +#endif /* DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) */ /* HFXO config from DT */ #if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal) @@ -496,17 +496,17 @@ void soc_early_init_hook(void) #endif #ifdef CONFIG_SOC_NRF5340_CPUAPP -#if defined(LFXO_CAP) +#if DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, LFXO_CAP); #if !defined(CONFIG_BUILD_WITH_TFM) /* This can only be done from secure code. * This is handled by the TF-M platform so we skip it when TF-M is * enabled. */ - nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); - nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); + nrf_gpio_pin_control_select(PIN_XL1, LFXO_PIN_SEL); + nrf_gpio_pin_control_select(PIN_XL2, LFXO_PIN_SEL); #endif /* !defined(CONFIG_BUILD_WITH_TFM) */ -#endif /* defined(LFXO_CAP) */ +#endif /* DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) */ #if defined(HFXO_CAP_VAL_X2) /* This register is only accessible from secure code. */ uint32_t xosc32mtrim = soc_secure_read_xosc32mtrim(); diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index 6663fcbb865bb..de88045d32fbf 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -28,7 +28,6 @@ config SOC_NRF54H20_CPUAPP_COMMON select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE select NRFS_HAS_AUDIOPLL_SERVICE select NRFS_HAS_CLOCK_SERVICE - select NRFS_HAS_DVFS_SERVICE select NRFS_HAS_GDFS_SERVICE select NRFS_HAS_GDPWR_SERVICE select NRFS_HAS_MRAM_SERVICE @@ -89,13 +88,23 @@ config SOC_NRF54H20_CPURAD_ENABLE Radiocore, and also power will be requested to the Radiocore subsystem. The Radiocore will then start executing instructions. +if SOC_NRF54H20_CPURAD_ENABLE + config SOC_NRF54H20_CPURAD_ENABLE_CHECK_VTOR bool "Check VTOR before booting Radio core" default y - depends on SOC_NRF54H20_CPURAD_ENABLE help Verify that VTOR is not 0xFFFFFFFF before booting the Radiocore. +config SOC_NRF54H20_CPURAD_ENABLE_DEBUG_WAIT + bool "Boot the Radio core in DEBUGWAIT mode" + help + Halt the Radio core immediately after reset. This ensures that a + debugger can attach and take control from the very first + instruction. + +endif # SOC_NRF54H20_CPURAD_ENABLE + config SOC_NRF54H20_CPURAD select SOC_NRF54H20_CPURAD_COMMON diff --git a/soc/nordic/nrf54h/Kconfig.defconfig b/soc/nordic/nrf54h/Kconfig.defconfig index b11dcd9916c90..a1b7961f3007a 100644 --- a/soc/nordic/nrf54h/Kconfig.defconfig +++ b/soc/nordic/nrf54h/Kconfig.defconfig @@ -35,6 +35,13 @@ config SPI_DW_HSSI config SPI_DW_ACCESS_WORD_ONLY default y if SPI_DW +if PM + +config PM_DEVICE + default y + +endif # PM + if PM_DEVICE config PM_DEVICE_RUNTIME diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c index a20815b2227ed..01cacf48f62f0 100644 --- a/soc/nordic/nrf54h/soc.c +++ b/soc/nordic/nrf54h/soc.c @@ -230,13 +230,12 @@ void soc_late_init_hook(void) return; } - /* Don't wait as this is not yet supported. */ - bool cpu_wait = false; + bool cpu_wait = IS_ENABLED(CONFIG_SOC_NRF54H20_CPURAD_ENABLE_DEBUG_WAIT); err_cpuconf = ironside_cpuconf(NRF_PROCESSOR_RADIOCORE, radiocore_address, cpu_wait, msg, msg_size); __ASSERT(err_cpuconf == 0, "err_cpuconf was %d", err_cpuconf); -#endif +#endif /* CONFIG_SOC_NRF54H20_CPURAD_ENABLE */ } #endif diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c index 85043985e51f6..76225d70ab74f 100644 --- a/soc/nordic/nrf54l/soc.c +++ b/soc/nordic/nrf54l/soc.c @@ -29,7 +29,6 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); !defined(__ZEPHYR__) #include -#include #include #include #include diff --git a/soc/nordic/sysbuild.cmake b/soc/nordic/sysbuild.cmake index 03db1a5ad18e4..631c79d57fc6f 100644 --- a/soc/nordic/sysbuild.cmake +++ b/soc/nordic/sysbuild.cmake @@ -29,3 +29,7 @@ if(SB_CONFIG_VPR_LAUNCHER) sysbuild_cache_set(VAR ${image}_SNIPPET APPEND REMOVE_DUPLICATES ${launcher_snippet}) endif() + +if(SB_CONFIG_NRF_HALTIUM_GENERATE_UICR) + include(${CMAKE_CURRENT_LIST_DIR}/common/uicr/sysbuild.cmake) +endif() diff --git a/soc/nuvoton/numaker/m55m1x/Kconfig b/soc/nuvoton/numaker/m55m1x/Kconfig index c3f973ec8f431..7659b720a53af 100644 --- a/soc/nuvoton/numaker/m55m1x/Kconfig +++ b/soc/nuvoton/numaker/m55m1x/Kconfig @@ -17,6 +17,7 @@ config SOC_SERIES_M55M1X select SOC_EARLY_INIT_HOOK select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS select HAS_POWEROFF + select ARM_MPU config ARMV8_1_M_PMU_EVENTCNT int diff --git a/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig b/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig index 71e688e8cdd23..e601bb7e4845b 100644 --- a/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig +++ b/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig @@ -6,4 +6,10 @@ if SOC_SERIES_M55M1X rsource "Kconfig.defconfig.m55m1*" +DT_NUMAKER_CPU_CLOCK_PATH := $(dt_nodelabel_path,sysclk) +DT_NUMAKER_CPU_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_NUMAKER_CPU_CLOCK_PATH),clock-frequency) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(DT_NUMAKER_CPU_CLOCK_FREQ) + endif # SOC_SERIES_M55M1X diff --git a/soc/nxp/imx/imx9/imx943/Kconfig.defconfig.mimx94398.a55 b/soc/nxp/imx/imx9/imx943/Kconfig.defconfig.mimx94398.a55 index 8e5d11c9593de..b5d7367975021 100644 --- a/soc/nxp/imx/imx9/imx943/Kconfig.defconfig.mimx94398.a55 +++ b/soc/nxp/imx/imx9/imx943/Kconfig.defconfig.mimx94398.a55 @@ -16,6 +16,12 @@ config FLASH_BASE_ADDRESS config GIC_SAFE_CONFIG default y +config GIC_V3_RDIST_DMA_NONCOHERENT + default y + +config GIC_V3_ITS_DMA_NONCOHERENT + default y + # Disable data cache until MMU is enabled when booting from EL2 config ARM64_DCACHE_ALL_OPS default y @@ -26,8 +32,10 @@ config ARM64_BOOT_DISABLE_DCACHE config MCUX_CORE_SUFFIX default "_ca55" if SOC_MIMX94398_A55 +# Reserve 8192 LPI interrupt ID starts from 8192 when ITS is enabled config NUM_IRQS - default 320 + default 16384 if GIC_V3_ITS + default 437 if !GIC_V3_ITS config SYS_CLOCK_HW_CYCLES_PER_SEC default 24000000 diff --git a/soc/nxp/imx/imx9/imx943/a55/soc.c b/soc/nxp/imx/imx9/imx943/a55/soc.c new file mode 100644 index 0000000000000..d1ca788fab0d8 --- /dev/null +++ b/soc/nxp/imx/imx9/imx943/a55/soc.c @@ -0,0 +1,116 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SCMI power domain states */ +#define POWER_DOMAIN_STATE_ON 0x00000000 +#define POWER_DOMAIN_STATE_OFF 0x40000000 + +#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) +/* The function is to reuse code for 250MHz NETC system clock and MACs clocks initialization */ +static int soc_netc_clock_init(int clk_id) +{ + const struct device *clk_dev = DEVICE_DT_GET(DT_NODELABEL(scmi_clk)); + struct scmi_protocol *proto = clk_dev->data; + struct scmi_clock_rate_config clk_cfg = {0}; + uint64_t clk_250m = 250000000; + int ret = 0; + + ret = scmi_clock_parent_set(proto, clk_id, IMX943_CLK_SYSPLL1_PFD0); + if (ret) { + return ret; + } + + clk_cfg.flags = SCMI_CLK_RATE_SET_FLAGS_ROUNDS_AUTO; + clk_cfg.clk_id = clk_id; + clk_cfg.rate[0] = clk_250m & 0xffffffff; + clk_cfg.rate[1] = (clk_250m >> 32) & 0xffffffff; + + return scmi_clock_rate_set(proto, &clk_cfg); +} +#endif + +static int soc_init(void) +{ +#if defined(CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS) + struct scmi_cpu_sleep_mode_config cpu_cfg = {0}; +#endif /* CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS */ + int ret = 0; + +#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) + struct scmi_power_state_config pwr_cfg = {0}; + uint32_t power_state = POWER_DOMAIN_STATE_OFF; + + /* Power up NETCMIX */ + pwr_cfg.domain_id = IMX943_PD_NETC; + pwr_cfg.power_state = POWER_DOMAIN_STATE_ON; + + ret = scmi_power_state_set(&pwr_cfg); + if (ret) { + return ret; + } + + while (power_state != POWER_DOMAIN_STATE_ON) { + ret = scmi_power_state_get(IMX943_PD_NETC, &power_state); + if (ret) { + return ret; + } + } + + ret = soc_netc_clock_init(IMX943_CLK_ENETREF); + if (ret) { + return ret; + } + + ret = soc_netc_clock_init(IMX943_CLK_MAC0); + if (ret) { + return ret; + } + + ret = soc_netc_clock_init(IMX943_CLK_MAC1); + if (ret) { + return ret; + } + + ret = soc_netc_clock_init(IMX943_CLK_MAC2); + if (ret) { + return ret; + } + + ret = soc_netc_clock_init(IMX943_CLK_MAC3); + if (ret) { + return ret; + } + + ret = soc_netc_clock_init(IMX943_CLK_MAC4); + if (ret) { + return ret; + } + + ret = soc_netc_clock_init(IMX943_CLK_MAC5); + if (ret) { + return ret; + } +#endif + + return ret; +} + +/* + * Because platform is using ARM SCMI, drivers like scmi, mbox etc. are + * initialized during PRE_KERNEL_1. Common init hooks is not able to use. + * SoC early init and board early init could be run during PRE_KERNEL_2 instead. + */ +SYS_INIT(soc_init, PRE_KERNEL_2, 0); diff --git a/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7 b/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7 index 64ba81caf7d43..7addf0e799193 100644 --- a/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7 +++ b/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7 @@ -57,4 +57,7 @@ config IDLE_STACK_SIZE default 640 endif +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + endif # SOC_MIMX9596_M7 diff --git a/soc/nxp/imx/imx9/imx95/m7/soc.c b/soc/nxp/imx/imx9/imx95/m7/soc.c index d3de555623c56..0554b43d5f19e 100644 --- a/soc/nxp/imx/imx9/imx95/m7/soc.c +++ b/soc/nxp/imx/imx9/imx95/m7/soc.c @@ -91,6 +91,7 @@ static int soc_init(void) void pm_state_before(void) { struct scmi_cpu_pd_lpm_config cpu_pd_lpm_cfg; + struct scmi_cpu_irq_mask_config cpu_irq_mask_cfg; /* * 1. Set M7 mix as power on state in suspend mode @@ -114,8 +115,27 @@ void pm_state_before(void) cpu_pd_lpm_cfg.cfgs[1].ret_mask = 0; scmi_cpu_pd_lpm_set(&cpu_pd_lpm_cfg); -} + /* Set wakeup mask */ + uint32_t wake_mask[GPC_CMC_IRQ_WAKEUP_MASK_COUNT] = { + [0 ... GPC_CMC_IRQ_WAKEUP_MASK_COUNT - 1] = 0xFFFFFFFFU + }; + + /* IRQs enabled at NVIC level become GPC wake sources */ + for (uint32_t idx = 0; idx < 8; idx++) { + wake_mask[idx] = ~(NVIC->ISER[idx]); + } + + cpu_irq_mask_cfg.cpu_id = CPU_IDX_M7P; + cpu_irq_mask_cfg.mask_idx = 0; + cpu_irq_mask_cfg.num_mask = GPC_CMC_IRQ_WAKEUP_MASK_COUNT; + + for (uint8_t val = 0; val < GPC_CMC_IRQ_WAKEUP_MASK_COUNT; val++) { + cpu_irq_mask_cfg.mask[val] = wake_mask[val]; + } + + scmi_cpu_set_irq_mask(&cpu_irq_mask_cfg); +} void pm_state_set(enum pm_state state, uint8_t substate_id) { @@ -167,6 +187,23 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) { ARG_UNUSED(state); + struct scmi_cpu_irq_mask_config cpu_irq_mask_cfg; + + /* Restore scmi cpu wake mask */ + uint32_t wake_mask[GPC_CMC_IRQ_WAKEUP_MASK_COUNT] = { + [0 ... GPC_CMC_IRQ_WAKEUP_MASK_COUNT - 1] = 0x0U + }; + + cpu_irq_mask_cfg.cpu_id = CPU_IDX_M7P; + cpu_irq_mask_cfg.mask_idx = 0; + cpu_irq_mask_cfg.num_mask = GPC_CMC_IRQ_WAKEUP_MASK_COUNT; + + for (uint8_t val = 0; val < GPC_CMC_IRQ_WAKEUP_MASK_COUNT; val++) { + cpu_irq_mask_cfg.mask[val] = wake_mask[val]; + } + + scmi_cpu_set_irq_mask(&cpu_irq_mask_cfg); + struct scmi_cpu_sleep_mode_config cpu_cfg = {0}; /* restore M7 core state into ACTIVE. */ cpu_cfg.cpu_id = CPU_IDX_M7P; diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig index 87c370170af16..4019d75c2a2c0 100644 --- a/soc/nxp/imxrt/imxrt10xx/Kconfig +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig @@ -84,4 +84,25 @@ config INIT_VIDEO_PLL depends on !SOC_MIMXRT1011 && !SOC_MIMXRT1015 && \ !SOC_MIMXRT1021 && !SOC_MIMXRT1024 +if PM + +config DCDC_TARGET_LOW_POWER_VOLTAGE + int "Target DCDC voltage in mV for low power mode" + default 1075 + range 800 1575 + help + When entering suspend-to-idle drops to this target SOC voltage. + If you are experiencing issues with low power mode stability, + try raising this voltage value. Increment or decrement in steps of 25 mV. + +config DCDC_TARGET_NORMAL_VOLTAGE + int "Target DCDC voltage in mV for normal mode" + default 1275 + range 800 1575 + help + When exiting suspend-to-idle raises to this SOC voltage. + Increment or decrement in steps of 25 mV. + +endif # PM + endif # SOC_SERIES_IMXRT10XX diff --git a/soc/nxp/imxrt/imxrt10xx/power.c b/soc/nxp/imxrt/imxrt10xx/power.c index 5936b70e02a91..237145d99cd3a 100644 --- a/soc/nxp/imxrt/imxrt10xx/power.c +++ b/soc/nxp/imxrt/imxrt10xx/power.c @@ -148,10 +148,10 @@ static void lpm_drop_voltage(void) CLOCK_SwitchOsc(kCLOCK_RcOsc); CLOCK_DeinitExternalClk(); /* - * Change to 1.075V SOC voltage. If you are experiencing issues with + * Change to low power SOC voltage. If you are experiencing issues with * low power mode stability, try raising this voltage value. */ - DCDC_AdjustRunTargetVoltage(DCDC, 0xB); + DCDC_AdjustRunTargetVoltage(DCDC, (CONFIG_DCDC_TARGET_LOW_POWER_VOLTAGE - 800) / 25); /* Enable 2.5 and 1.1V weak regulators */ PMU_2P5EnableWeakRegulator(PMU, true); PMU_1P1EnableWeakRegulator(PMU, true); @@ -173,8 +173,8 @@ static void lpm_raise_voltage(void) /* Disable weak LDOs */ PMU_2P5EnableWeakRegulator(PMU, false); PMU_1P1EnableWeakRegulator(PMU, false); - /* Change to 1.275V SOC voltage */ - DCDC_AdjustRunTargetVoltage(DCDC, 0x13); + /* Change to normal SOC voltage */ + DCDC_AdjustRunTargetVoltage(DCDC, (CONFIG_DCDC_TARGET_NORMAL_VOLTAGE - 800) / 25); /* Move to the external RC oscillator */ CLOCK_InitExternalClk(0); /* Switch clock source to external OSC. */ diff --git a/soc/nxp/mcx/mcxa/Kconfig b/soc/nxp/mcx/mcxa/Kconfig index e3ae4b7d1f559..ca158760e7463 100644 --- a/soc/nxp/mcx/mcxa/Kconfig +++ b/soc/nxp/mcx/mcxa/Kconfig @@ -13,14 +13,12 @@ config SOC_FAMILY_MCXA config SOC_MCXA153 select CPU_CORTEX_M33 select HAS_MCUX_CACHE - select HAS_MCUX_MCX_CMC config SOC_MCXA156 select CPU_CORTEX_M33 select CPU_HAS_FPU select ARMV8_M_DSP select HAS_MCUX_CACHE - select HAS_MCUX_MCX_CMC config SOC_MCXA346 select CPU_CORTEX_M33 @@ -28,7 +26,6 @@ config SOC_MCXA346 select CPU_HAS_FPU select ARMV8_M_DSP select HAS_MCUX_CACHE - select HAS_MCUX_MCX_CMC config SOC_MCXA266 select CPU_CORTEX_M33 @@ -36,4 +33,3 @@ config SOC_MCXA266 select CPU_HAS_FPU select ARMV8_M_DSP select HAS_MCUX_CACHE - select HAS_MCUX_MCX_CMC diff --git a/soc/nxp/mcx/mcxn/Kconfig b/soc/nxp/mcx/mcxn/Kconfig index ff90e29ab932b..bad3352ddb82d 100644 --- a/soc/nxp/mcx/mcxn/Kconfig +++ b/soc/nxp/mcx/mcxn/Kconfig @@ -8,7 +8,6 @@ config SOC_FAMILY_MCXN select HAS_MCUX select CPU_CORTEX_M_HAS_SYSTICK select CPU_CORTEX_M_HAS_DWT - select HAS_MCUX_MCX_CMC config SOC_MCXN947_CPU0 select CPU_CORTEX_M33 diff --git a/soc/nxp/rw/power.c b/soc/nxp/rw/power.c index f7e9bfe869832..09000c3a8359d 100644 --- a/soc/nxp/rw/power.c +++ b/soc/nxp/rw/power.c @@ -6,7 +6,9 @@ #include #include #include +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(standby)) #include +#endif #include #include #if CONFIG_GPIO && (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0)) || \ @@ -220,7 +222,9 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id) CLOCK_AttachClk(kLPOSC_to_OSTIMER_CLK); /* Clear the RTC wakeup bits */ POWER_ClearWakeupStatus(DT_IRQN(DT_NODELABEL(rtc))); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(standby)) RTC_ClearStatusFlags(RTC, kRTC_WakeupFlag); +#endif NVIC_ClearPendingIRQ(DT_IRQN(DT_NODELABEL(rtc))); sys_clock_idle_exit(); sys_clock_set_timeout(0, true); diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index 86bc4c904d9f9..166c6008310e2 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -277,7 +277,8 @@ __weak __ramfunc void clock_init(void) #endif /* CONFIG_COUNTER_MCUX_CTIMER || CONFIG_PWM_MCUX_CTIMER */ #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb_otg)) && \ - (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI) + (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI) || \ + (CONFIG_UHC_NXP_EHCI) /* Enable system xtal from Analog */ SYSCTL2->ANA_GRP_CTRL |= SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK; /* reset USB */ diff --git a/soc/realtek/ec/rts5912/rts5912_ulpm.c b/soc/realtek/ec/rts5912/rts5912_ulpm.c index 1cd8f49325985..643330c397f84 100644 --- a/soc/realtek/ec/rts5912/rts5912_ulpm.c +++ b/soc/realtek/ec/rts5912/rts5912_ulpm.c @@ -24,6 +24,8 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1, "Unsupported number of #define ULPM_RTS5912_MAX_NB_WKUP_PINS DT_INST_PROP(0, wkup_pins_max) +#define RTS5912_ULPM_WAIT_READY (10 * USEC_PER_MSEC) + /** @cond INTERNAL_HIDDEN */ /** @@ -89,13 +91,13 @@ void ulpm_start(void) SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE; /* enable VOUT */ sys_reg->VIVOCTRL &= ~(SYSTEM_VIVOCTRL_VOUTMD_Msk); - k_msleep(10); + k_busy_wait(RTS5912_ULPM_WAIT_READY); /* Set the VOUT to low */ sys_reg->VIVOCTRL &= ~(SYSTEM_VIVOCTRL_VODEF_Msk); - k_msleep(10); + k_busy_wait(RTS5912_ULPM_WAIT_READY); /* update to ULPM */ sys_reg->VIVOCTRL |= SYSTEM_VIVOCTRL_REGWREN_Msk; - k_msleep(10); + k_busy_wait(RTS5912_ULPM_WAIT_READY); } /** * @brief Update register value to ULPM IP @@ -104,11 +106,11 @@ void update_vivo_register(void) { SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE; /* Update Register & reset bit */ - k_msleep(10); + k_busy_wait(RTS5912_ULPM_WAIT_READY); sys_reg->VIVOCTRL |= SYSTEM_VIVOCTRL_REGWREN_Msk; - k_msleep(10); + k_busy_wait(RTS5912_ULPM_WAIT_READY); sys_reg->VIVOCTRL &= ~(SYSTEM_VIVOCTRL_REGWREN_Msk); - k_msleep(10); + k_busy_wait(RTS5912_ULPM_WAIT_READY); } /** @@ -125,7 +127,7 @@ void rts5912_ulpm_enable(void) LOG_INF("rts5912 ULPM enabled\n"); /* VoutEnable, Keep VOUT output default value as bit 16 */ sys_reg->VIVOCTRL |= SYSTEM_VIVOCTRL_VODEF_Msk; - k_msleep(10); + k_busy_wait(RTS5912_ULPM_WAIT_READY); /* set to GPIO mode to clear status and aviod mis-trigger */ sys_reg->VIVOCTRL |= (SYSTEM_VIVOCTRL_VIN0MD_Msk | SYSTEM_VIVOCTRL_VIN1MD_Msk | diff --git a/soc/renesas/ra/Kconfig b/soc/renesas/ra/Kconfig index c3651008a4198..f7fb24c03f4c3 100644 --- a/soc/renesas/ra/Kconfig +++ b/soc/renesas/ra/Kconfig @@ -9,6 +9,19 @@ if SOC_FAMILY_RENESAS_RA config SERIES_SPECIFIC_SOC_INIT bool "Use series specific initialize" +config OUTPUT_RPD + bool "Build a Renesas Partition Data in rpd format" + depends on CPU_HAS_RENESAS_RA_IDAU + help + Build a partition data zephyr/zephyr.rpd in the build directory. + The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. + +config CPU_HAS_RENESAS_RA_IDAU + bool + select CPU_HAS_TEE + help + MCU implements the ARM Implementation-Defined Attribution Unit (IDAU). + rsource "*/Kconfig" endif # SOC_FAMILY_RENESAS_RA diff --git a/soc/renesas/ra/ra6m4/CMakeLists.txt b/soc/renesas/ra/ra6m4/CMakeLists.txt index f8147e8059102..6b526e37972f0 100644 --- a/soc/renesas/ra/ra6m4/CMakeLists.txt +++ b/soc/renesas/ra/ra6m4/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) @@ -10,4 +10,21 @@ zephyr_sources( zephyr_linker_sources(SECTIONS sections.ld) zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +if(CONFIG_ETH_RENESAS_RA_USE_NS_BUF) + # In ra6m4 ethernet peripheral is always non-secure, even in flat project. + # Use this linker script to place ethernet buffer in non-secure RAM. + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") + + if(CONFIG_OUTPUT_RPD) + # Generate zephyr.rpd file + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${SOC_FULL_DIR}/tools/gen_rpd.py + --kernel ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME} + --output-rpd ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.rpd + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + ) + endif() +else() + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/renesas/ra/ra6m4/Kconfig b/soc/renesas/ra/ra6m4/Kconfig index dec6aba2581e9..89e6dfb300666 100644 --- a/soc/renesas/ra/ra6m4/Kconfig +++ b/soc/renesas/ra/ra6m4/Kconfig @@ -5,6 +5,7 @@ config SOC_SERIES_RA6M4 select ARM select CPU_CORTEX_M33 select CPU_HAS_ARM_MPU + select CPU_HAS_RENESAS_RA_IDAU select HAS_RENESAS_RA_FSP select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT @@ -15,3 +16,4 @@ config SOC_SERIES_RA6M4 select XIP select SOC_EARLY_INIT_HOOK select GPIO_RA_HAS_VBTICTLR + select OUTPUT_RPD if ETH_RENESAS_RA diff --git a/soc/renesas/ra/ra6m4/linker.ld b/soc/renesas/ra/ra6m4/linker.ld new file mode 100644 index 0000000000000..3f8937e4c94e4 --- /dev/null +++ b/soc/renesas/ra/ra6m4/linker.ld @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +FLASH_START = CONFIG_FLASH_BASE_ADDRESS; +FLASH_LENGTH = (CONFIG_FLASH_SIZE * 1K); +FLASH_END = FLASH_START + FLASH_LENGTH; + +DATA_FLASH_START = DT_REG_ADDR(DT_NODELABEL(flash1)); +DATA_FLASH_LENGTH = DT_REG_SIZE(DT_NODELABEL(flash1)); +DATA_FLASH_END = DATA_FLASH_START + DATA_FLASH_LENGTH; + +RAM_START = CONFIG_SRAM_BASE_ADDRESS; +RAM_LENGTH = (CONFIG_SRAM_SIZE * 1K); +RAM_END = RAM_START + RAM_LENGTH; + +ETH_BUFFER_LENGTH = ((CONFIG_ETH_RENESAS_TX_BUF_NUM + CONFIG_ETH_RENESAS_RX_BUF_NUM) * 1552); +ETH_BUFFER_START = RAM_START + RAM_LENGTH - ETH_BUFFER_LENGTH; +NS_RAM_REGION_LENGTH = ALIGN(ETH_BUFFER_LENGTH, 8K); +NS_RAM_REGION_START = RAM_START + RAM_LENGTH - NS_RAM_REGION_LENGTH; + +#if !defined(CONFIG_ARM_SECURE_FIRMWARE) && !defined(CONFIG_ARM_NONSECURE_FIRMWARE) + /* + * Boundaries setting in flat project. + * Set entire code flash as secure. + * Set entire data flash as secure. + * These symbols used by partition tool. + */ + + __FLASH_S = ABSOLUTE(FLASH_START); + __FLASH_NSC = ABSOLUTE(FLASH_END); + __FLASH_NS = ABSOLUTE(FLASH_END); + + __DATA_FLASH_S = ABSOLUTE(DATA_FLASH_START); + __DATA_FLASH_NS = ABSOLUTE(DATA_FLASH_END); + + __RAM_S = ORIGIN(RAM); + __RAM_NSC = ABSOLUTE(NS_RAM_REGION_START); + __RAM_NS = ABSOLUTE(NS_RAM_REGION_START); +#else + /* + * Boundaries setting in TrustZone project is not implemented. + */ +#endif + +SECTIONS +{ + /* Create section in non-secure RAM for ethernet buffer */ + SECTION_PROLOGUE(.ns_buffer,(NOLOAD),) + { + . = ABSOLUTE(ETH_BUFFER_START & 0xFFFFFFE0); + KEEP(*(.ns_buffer*)) + } GROUP_NOLOAD_LINK_IN(RAM, RAM) +} diff --git a/soc/renesas/ra/ra6m5/CMakeLists.txt b/soc/renesas/ra/ra6m5/CMakeLists.txt index f8147e8059102..9fa4169634759 100644 --- a/soc/renesas/ra/ra6m5/CMakeLists.txt +++ b/soc/renesas/ra/ra6m5/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) @@ -10,4 +10,21 @@ zephyr_sources( zephyr_linker_sources(SECTIONS sections.ld) zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +if(CONFIG_ETH_RENESAS_RA_USE_NS_BUF) + # In ra6m5 ethernet peripheral is always non-secure, even in flat project. + # Use this linker script to place ethernet buffer in non-secure RAM. + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") + + if(CONFIG_OUTPUT_RPD) + # Generate zephyr.rpd file + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${SOC_FULL_DIR}/tools/gen_rpd.py + --kernel ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME} + --output-rpd ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.rpd + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + ) + endif() +else() + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/renesas/ra/ra6m5/Kconfig b/soc/renesas/ra/ra6m5/Kconfig index 792239394c72c..ef8a383948909 100644 --- a/soc/renesas/ra/ra6m5/Kconfig +++ b/soc/renesas/ra/ra6m5/Kconfig @@ -5,6 +5,7 @@ config SOC_SERIES_RA6M5 select ARM select CPU_CORTEX_M33 select CPU_HAS_ARM_MPU + select CPU_HAS_RENESAS_RA_IDAU select HAS_RENESAS_RA_FSP select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT @@ -15,3 +16,4 @@ config SOC_SERIES_RA6M5 select XIP select SOC_EARLY_INIT_HOOK select GPIO_RA_HAS_VBTICTLR + select OUTPUT_RPD if ETH_RENESAS_RA diff --git a/soc/renesas/ra/ra6m5/linker.ld b/soc/renesas/ra/ra6m5/linker.ld new file mode 100644 index 0000000000000..3f8937e4c94e4 --- /dev/null +++ b/soc/renesas/ra/ra6m5/linker.ld @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +FLASH_START = CONFIG_FLASH_BASE_ADDRESS; +FLASH_LENGTH = (CONFIG_FLASH_SIZE * 1K); +FLASH_END = FLASH_START + FLASH_LENGTH; + +DATA_FLASH_START = DT_REG_ADDR(DT_NODELABEL(flash1)); +DATA_FLASH_LENGTH = DT_REG_SIZE(DT_NODELABEL(flash1)); +DATA_FLASH_END = DATA_FLASH_START + DATA_FLASH_LENGTH; + +RAM_START = CONFIG_SRAM_BASE_ADDRESS; +RAM_LENGTH = (CONFIG_SRAM_SIZE * 1K); +RAM_END = RAM_START + RAM_LENGTH; + +ETH_BUFFER_LENGTH = ((CONFIG_ETH_RENESAS_TX_BUF_NUM + CONFIG_ETH_RENESAS_RX_BUF_NUM) * 1552); +ETH_BUFFER_START = RAM_START + RAM_LENGTH - ETH_BUFFER_LENGTH; +NS_RAM_REGION_LENGTH = ALIGN(ETH_BUFFER_LENGTH, 8K); +NS_RAM_REGION_START = RAM_START + RAM_LENGTH - NS_RAM_REGION_LENGTH; + +#if !defined(CONFIG_ARM_SECURE_FIRMWARE) && !defined(CONFIG_ARM_NONSECURE_FIRMWARE) + /* + * Boundaries setting in flat project. + * Set entire code flash as secure. + * Set entire data flash as secure. + * These symbols used by partition tool. + */ + + __FLASH_S = ABSOLUTE(FLASH_START); + __FLASH_NSC = ABSOLUTE(FLASH_END); + __FLASH_NS = ABSOLUTE(FLASH_END); + + __DATA_FLASH_S = ABSOLUTE(DATA_FLASH_START); + __DATA_FLASH_NS = ABSOLUTE(DATA_FLASH_END); + + __RAM_S = ORIGIN(RAM); + __RAM_NSC = ABSOLUTE(NS_RAM_REGION_START); + __RAM_NS = ABSOLUTE(NS_RAM_REGION_START); +#else + /* + * Boundaries setting in TrustZone project is not implemented. + */ +#endif + +SECTIONS +{ + /* Create section in non-secure RAM for ethernet buffer */ + SECTION_PROLOGUE(.ns_buffer,(NOLOAD),) + { + . = ABSOLUTE(ETH_BUFFER_START & 0xFFFFFFE0); + KEEP(*(.ns_buffer*)) + } GROUP_NOLOAD_LINK_IN(RAM, RAM) +} diff --git a/soc/renesas/ra/tools/gen_rpd.py b/soc/renesas/ra/tools/gen_rpd.py new file mode 100644 index 0000000000000..d9e1155ca83f0 --- /dev/null +++ b/soc/renesas/ra/tools/gen_rpd.py @@ -0,0 +1,144 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2025 Renesas Electronics Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +"""Generate a Renesas Partition Device File (RPD) for RA family + +RFP is used by Renesas Flash Programmer or Renesas Partition Manager. +""" + +import argparse +import os +import sys + +from elftools.elf.elffile import ELFFile + + +def debug(text): + """Display debug message if --verbose""" + if args.verbose: + sys.stdout.write(os.path.basename(sys.argv[0]) + ": " + text + "\n") + + +def error(text): + """Display error message""" + sys.stderr.write(os.path.basename(sys.argv[0]) + ": " + text + "\n") + + +def exit(text): + """Exit program with an error message""" + sys.exit(os.path.basename(sys.argv[0]) + ": " + text + "\n") + + +class ZephyrElf: + """ + Represents memory symbols in an elf file. + """ + + def __init__(self): + """ + Initialize the IDAU object with given parameters + These values refer to HM under security section + """ + self.ram_s_start = 0 + self.ram_s_size = 0 + self.ram_c_start = 0 + self.ram_c_size = 0 + self.flash_s_start = 0 + self.flash_s_size = 0 + self.flash_c_start = 0 + self.flash_c_size = 0 + self.data_flash_s_start = 0 + self.data_flash_s_size = 0 + + def read_symbol(self, symbols, name): + """Reads a symbols from symbol table and returns its address""" + try: + sym = symbols.get_symbol_by_name(name) + address = sym[0]["st_value"] + except Exception as e: + error(f"Could not find symbol {name} in ELF file {e}") + debug(f"Found symbol {name} at 0x{address:x}") + return address + + def parse(self, path): + """Reads IDAU configuration from elf file""" + if not os.path.exists(path): + exit("Invalid kernel path") + + with open(path, "rb") as f: + elf = ELFFile(f) + try: + symtab = elf.get_section_by_name(".symtab") + # Read memory symbols + code_flash_s = self.read_symbol(symtab, "__FLASH_S") + code_flash_nsc = self.read_symbol(symtab, "__FLASH_NSC") + code_flash_ns = self.read_symbol(symtab, "__FLASH_NS") + data_flash_s = self.read_symbol(symtab, "__DATA_FLASH_S") + data_flash_ns = self.read_symbol(symtab, "__DATA_FLASH_NS") + sram_s = self.read_symbol(symtab, "__RAM_S") + sram_nsc = self.read_symbol(symtab, "__RAM_NSC") + sram_ns = self.read_symbol(symtab, "__RAM_NS") + + self.ram_s_start = sram_s + self.ram_s_size = sram_nsc - sram_s + self.ram_c_start = sram_nsc + self.ram_c_size = sram_ns - sram_nsc + + self.flash_s_start = code_flash_s + self.flash_s_size = code_flash_nsc - code_flash_s + self.flash_c_start = code_flash_nsc + self.flash_c_size = code_flash_ns - code_flash_nsc + + self.data_flash_s_start = data_flash_s + self.data_flash_s_size = data_flash_ns - data_flash_s + + except Exception as e: + exit(f"Could not find symbol table in ELF file {e}") + + +def parse_args(): + """Parse command line arguments""" + global args + + parser = argparse.ArgumentParser( + description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter, + allow_abbrev=False, + ) + + parser.add_argument("-k", "--kernel", required=True, help="Zephyr kernel image") + parser.add_argument( + "-v", "--verbose", action="store_true", help="Print extra debugging information" + ) + parser.add_argument("-o", "--output-rpd", required=True, help="output RPD file") + + args = parser.parse_args() + + +def main(): + parse_args() + + # Read boundary setting from elf file + elf_parser = ZephyrElf() + elf_parser.parse(args.kernel) + + with open(args.output_rpd, "w") as rpd: + rpd.write(f"RAM_S_START=0x{elf_parser.ram_s_start:X}\n") + rpd.write(f"RAM_S_SIZE=0x{elf_parser.ram_s_size:X}\n") + rpd.write(f"RAM_C_START=0x{elf_parser.ram_c_start:X}\n") + rpd.write(f"RAM_C_SIZE=0x{elf_parser.ram_c_size:X}\n") + + rpd.write(f"FLASH_S_START=0x{elf_parser.flash_s_start:X}\n") + rpd.write(f"FLASH_S_SIZE=0x{elf_parser.flash_s_size:X}\n") + rpd.write(f"FLASH_C_START=0x{elf_parser.flash_c_start:X}\n") + rpd.write(f"FLASH_C_SIZE=0x{elf_parser.flash_c_size:X}\n") + + rpd.write(f"DATA_FLASH_S_START=0x{elf_parser.data_flash_s_start:X}\n") + rpd.write(f"DATA_FLASH_S_SIZE=0x{elf_parser.data_flash_s_size:X}\n") + + +if __name__ == "__main__": + main() diff --git a/soc/renode/cortex_r8_virtual/arm_mpu_regions.c b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c index 8287a0651d4d0..6a9ea54ed352c 100644 --- a/soc/renode/cortex_r8_virtual/arm_mpu_regions.c +++ b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c @@ -2,62 +2,67 @@ * * Copyright (c) 2021 Lexmark International, Inc. * Copyright (c) 2024 Antmicro + * Copyright (c) 2024 Immo Birnbaum */ #include -#include +#include -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +extern const uint32_t __rom_region_start; +extern const uint32_t __rom_region_mpu_size_bits; -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } - -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } - -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } - -extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), - - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), - - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), - - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + /* + * The address of the vectors is determined by arch/arm/core/cortex_a_r/prep_c.c + * -> for v8-R, there's no other option than 0x0, HIVECS always gets cleared + */ + MPU_REGION_ENTRY( + "vectors", + 0x00000000, + REGION_64B, + {.rasr = P_RO_U_NA_Msk | + NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + /* Basic SRAM mapping is all data, R/W + XN */ + MPU_REGION_ENTRY( + "sram", + CONFIG_SRAM_BASE_ADDRESS, + REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), +#if defined(CONFIG_XIP) + /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), + /* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ + /* .text and .rodata are in RAM, flash is data only -> RO + XN */ + MPU_REGION_ENTRY( + "flash", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | + NOT_EXEC}), + /* add rom_region mapping for SRAM which is RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), +#endif /* CONFIG_XIP */ + MPU_REGION_ENTRY( + "peripherals", + 0xf8000000, + REGION_128M, + {.rasr = P_RW_U_NA_Msk | + DEVICE_SHAREABLE | + NOT_EXEC}), }; const struct arm_mpu_config mpu_config = { diff --git a/soc/silabs/Kconfig b/soc/silabs/Kconfig index 28676194b495d..1bc6ca673f993 100644 --- a/soc/silabs/Kconfig +++ b/soc/silabs/Kconfig @@ -153,6 +153,13 @@ config SOC_GECKO_PM_BACKEND_EMU help Implement PM using direct calls to EMU driver in emlib +config SOC_SILABS_PM_LOW_INTERRUPT_LATENCY + bool "Low interrupt latency mode" + default y if SOC_GECKO_PM_BACKEND_PMGR + help + Enabling low interrupt latency allows interrupts to be executed + before the high frequency clock is restored after sleep. + endif # PM config SOC_GECKO_EMU_DCDC diff --git a/soc/silabs/common/soc_power_pmgr.c b/soc/silabs/common/soc_power_pmgr.c index 443e289cda780..5f9d1909b4840 100644 --- a/soc/silabs/common/soc_power_pmgr.c +++ b/soc/silabs/common/soc_power_pmgr.c @@ -87,6 +87,7 @@ bool sl_power_manager_is_ok_to_sleep(void) return true; } +#if !defined(CONFIG_SOC_SILABS_PM_LOW_INTERRUPT_LATENCY) /* This function is called by sl_power_manager_sleep() right after it was woken up from WFI. */ void sli_power_manager_on_wakeup(void) { @@ -98,6 +99,7 @@ void sli_power_manager_on_wakeup(void) sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); } +#endif /** * Some SiLabs blobs, such as RAIL, call directly into sl_power_manager, and diff --git a/soc/silabs/silabs_s2/CMakeLists.txt b/soc/silabs/silabs_s2/CMakeLists.txt index f170c44fd1838..d5228429c4fd4 100644 --- a/soc/silabs/silabs_s2/CMakeLists.txt +++ b/soc/silabs/silabs_s2/CMakeLists.txt @@ -2,3 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_sources(soc.c) +zephyr_sources_ifdef(CONFIG_SOC_SILABS_IMAGE_PROPERTIES soc_image_properties.c) +zephyr_linker_sources_ifdef(CONFIG_SOC_SILABS_IMAGE_PROPERTIES RODATA soc_image_properties.ld) diff --git a/soc/silabs/silabs_s2/Kconfig b/soc/silabs/silabs_s2/Kconfig index afaada703c38c..c617183644a14 100644 --- a/soc/silabs/silabs_s2/Kconfig +++ b/soc/silabs/silabs_s2/Kconfig @@ -10,6 +10,19 @@ config SOC_FAMILY_SILABS_S2 select SOC_EARLY_INIT_HOOK select HAS_SILABS_SISDK +config SOC_SILABS_IMAGE_PROPERTIES + bool "Include application properties data structure in image" + default y if MCUBOOT + help + Include the Silicon Labs application properties data structure in the + the firmware image. This allows the SE and Gecko bootloader to access + information about the image, such as its version and capabilities. If + MCUboot is used, only the MCUboot image itself needs the image + properties data structure to enable the SE to perform secure boot + verification of the bootloader. MCUboot uses its own TLV format to + verify the application. If Gecko bootloader is used, the Zephyr + application image also needs the data structure. + rsource "*/Kconfig" config ARM_SECURE_FIRMWARE diff --git a/soc/silabs/silabs_s2/soc_image_properties.c b/soc/silabs/silabs_s2/soc_image_properties.c new file mode 100644 index 0000000000000..799956030e1e8 --- /dev/null +++ b/soc/silabs/silabs_s2/soc_image_properties.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if defined __has_include +#if __has_include("app_version.h") +#include "app_version.h" +#define SOC_IMAGE_VERSION APPVERSION +#endif +#endif + +#if !defined(SOC_IMAGE_VERSION) +#include +#define SOC_IMAGE_VERSION KERNELVERSION +#endif + +#if !defined(SOC_IMAGE_TYPE) +#define SOC_IMAGE_TYPE \ + ((IS_ENABLED(CONFIG_MCUBOOT) ? BIT(6) : 0) | (IS_ENABLED(CONFIG_BT) ? BIT(3) : 0)) +#endif + +#if !defined(SOC_IMAGE_CAPABILITIES) +#define SOC_IMAGE_CAPABILITIES 0 +#endif + +#if !defined(SOC_IMAGE_PRODUCT_ID) +#define SOC_IMAGE_PRODUCT_ID {0} +#endif + +struct image_info { + uint32_t type; + uint32_t version; + uint32_t capabilities; + uint8_t id[16]; +}; + +struct image_properties { + uint8_t magic[16]; + uint32_t header_version; + uint32_t signature_type; + uint32_t signature_location; + struct image_info info; + void *cert; + void *token_location; +}; + +const struct image_properties image_props __attribute__((used, section(".image_properties"))) = { + .magic = {0x13, 0xb7, 0x79, 0xfa, 0xc9, 0x25, 0xdd, 0xb7, 0xad, 0xf3, 0xcf, 0xe0, 0xf1, + 0xb6, 0x14, 0xb8}, + .header_version = 0x0101, + .signature_type = 0, + .signature_location = 0, + .info = {.type = SOC_IMAGE_TYPE, + .version = SOC_IMAGE_VERSION, + .capabilities = SOC_IMAGE_CAPABILITIES, + .id = SOC_IMAGE_PRODUCT_ID}, + .cert = NULL, + .token_location = NULL, +}; diff --git a/soc/silabs/silabs_s2/soc_image_properties.ld b/soc/silabs/silabs_s2/soc_image_properties.ld new file mode 100644 index 0000000000000..377edaa603a93 --- /dev/null +++ b/soc/silabs/silabs_s2/soc_image_properties.ld @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Ensure that image properties section is preserved in the final binary. + */ + +_image_properties_start = .; +KEEP(*(.image_properties)); +_image_properties_end = .; +_image_properties_size = ABSOLUTE(_image_properties_end - _image_properties_start); diff --git a/soc/silabs/silabs_s2/xg24/Kconfig b/soc/silabs/silabs_s2/xg24/Kconfig index 4ad62fb3e61ab..e42474c1d4857 100644 --- a/soc/silabs/silabs_s2/xg24/Kconfig +++ b/soc/silabs/silabs_s2/xg24/Kconfig @@ -1,5 +1,6 @@ # Copyright (c) 2020 TriaGnoSys GmbH # Copyright (c) 2025 Silicon Laboratories Inc. +# Copyright (c) 2025 Ephraim Westenberger # SPDX-License-Identifier: Apache-2.0 config SOC_SILABS_XG24 @@ -25,3 +26,7 @@ config SOC_SERIES_EFR32MG24 config SOC_SERIES_MGM24 select SILABS_DEVICE_IS_MODULE select SOC_GECKO_HAS_RADIO + +config SOC_SERIES_BGM24 + select SILABS_DEVICE_IS_MODULE + select SOC_GECKO_HAS_RADIO diff --git a/soc/silabs/silabs_s2/xg24/Kconfig.soc b/soc/silabs/silabs_s2/xg24/Kconfig.soc index 4c798257e14d8..059589101f91c 100644 --- a/soc/silabs/silabs_s2/xg24/Kconfig.soc +++ b/soc/silabs/silabs_s2/xg24/Kconfig.soc @@ -1,5 +1,6 @@ # Copyright (c) 2020 TriaGnoSys GmbH # Copyright (c) 2025 Silicon Laboratories Inc. +# Copyright (c) 2025 Ephraim Westenberger # SPDX-License-Identifier: Apache-2.0 config SOC_SILABS_XG24 @@ -20,6 +21,12 @@ config SOC_SERIES_MGM24 help Silicon Labs MGM240 (Mighty Gecko) Series MCU modules +config SOC_SERIES_BGM24 + bool + select SOC_SILABS_XG24 + help + Silicon Labs BGM240 Series MCU modules + config SOC_EFR32MG24B020F1536IM40 bool select SOC_SERIES_EFR32MG24 @@ -44,9 +51,14 @@ config SOC_MGM240PB32VNA bool select SOC_SERIES_MGM24 +config SOC_BGM240SA22VNA + bool + select SOC_SERIES_BGM24 + config SOC_SERIES default "efr32mg24" if SOC_SERIES_EFR32MG24 default "mgm24" if SOC_SERIES_MGM24 + default "bgm24" if SOC_SERIES_BGM24 config SOC default "efr32mg24b220f1536im48" if SOC_EFR32MG24B220F1536IM48 @@ -55,3 +67,4 @@ config SOC default "efr32mg24b020f1536im40" if SOC_EFR32MG24B020F1536IM40 default "mgm240sd22vna" if SOC_MGM240SD22VNA default "mgm240pb32vna" if SOC_MGM240PB32VNA + default "bgm240sa22vna" if SOC_BGM240SA22VNA diff --git a/soc/silabs/silabs_s2/xg28/Kconfig b/soc/silabs/silabs_s2/xg28/Kconfig index f1dcdfe2ae34c..397a62e8ccc93 100644 --- a/soc/silabs/silabs_s2/xg28/Kconfig +++ b/soc/silabs/silabs_s2/xg28/Kconfig @@ -18,3 +18,6 @@ config SOC_SILABS_XG28 select SOC_GECKO_EMU select SOC_GECKO_GPIO select SOC_GECKO_SE + +config SOC_SERIES_EFR32ZG28 + select SOC_GECKO_HAS_RADIO diff --git a/soc/silabs/silabs_s2/xg28/Kconfig.defconfig b/soc/silabs/silabs_s2/xg28/Kconfig.defconfig index 0e49055d15c15..4fd489f8457a5 100644 --- a/soc/silabs/silabs_s2/xg28/Kconfig.defconfig +++ b/soc/silabs/silabs_s2/xg28/Kconfig.defconfig @@ -5,6 +5,6 @@ if SOC_SILABS_XG28 config NUM_IRQS # must be >= the highest interrupt number used - default 79 + default 78 endif diff --git a/soc/silabs/silabs_s2/xg28/Kconfig.soc b/soc/silabs/silabs_s2/xg28/Kconfig.soc index e664cb2ac35bd..5b36491e101e3 100644 --- a/soc/silabs/silabs_s2/xg28/Kconfig.soc +++ b/soc/silabs/silabs_s2/xg28/Kconfig.soc @@ -1,4 +1,5 @@ # Copyright (c) 2025 Christoph Jans +# Copyright (c) 2025 Shontal Biton # SPDX-License-Identifier: Apache-2.0 config SOC_SILABS_XG28 @@ -13,12 +14,24 @@ config SOC_SERIES_EFM32PG28 help Silicon Labs EFM32PG28 Series MCU +config SOC_SERIES_EFR32ZG28 + bool + select SOC_SILABS_XG28 + help + Silicon Labs EFR32ZG28 Series MCU + config SOC_EFM32PG28B310F1024IM68 bool select SOC_SERIES_EFM32PG28 +config SOC_EFR32ZG28B322F1024IM68 + bool + select SOC_SERIES_EFR32ZG28 + config SOC_SERIES default "efm32pg28" if SOC_SERIES_EFM32PG28 + default "efr32zg28" if SOC_SERIES_EFR32ZG28 config SOC default "efm32pg28b310f1024im68" if SOC_EFM32PG28B310F1024IM68 + default "efr32zg28b322f1024im68" if SOC_EFR32ZG28B322F1024IM68 diff --git a/soc/silabs/silabs_siwx91x/siwg917/nwp.c b/soc/silabs/silabs_siwx91x/siwg917/nwp.c index 4c760d4d92b0e..01019a4c1ddcf 100644 --- a/soc/silabs/silabs_siwx91x/siwg917/nwp.c +++ b/soc/silabs/silabs_siwx91x/siwg917/nwp.c @@ -32,6 +32,96 @@ BUILD_ASSERT(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(195) || DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(255) || DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(319)); +extern const sli_si91x_set_region_ap_request_t default_US_region_2_4GHZ_configurations; +extern const sli_si91x_set_region_ap_request_t default_EU_region_2_4GHZ_configurations; +extern const sli_si91x_set_region_ap_request_t default_JP_region_2_4GHZ_configurations; +extern const sli_si91x_set_region_ap_request_t default_KR_region_2_4GHZ_configurations; +extern const sli_si91x_set_region_ap_request_t default_SG_region_2_4GHZ_configurations; +extern const sli_si91x_set_region_ap_request_t default_CN_region_2_4GHZ_configurations; + +static char current_country_code[WIFI_COUNTRY_CODE_LEN]; +typedef struct { + const char *const *codes; + size_t num_codes; + sl_wifi_region_code_t region_code; + const sli_si91x_set_region_ap_request_t *sdk_reg; +} region_map_t; + +static const char *const us_codes[] = { + "AE", "AR", "AS", "BB", "BM", "BR", "BS", "CA", "CO", "CR", "CU", "CX", + "DM", "DO", "EC", "FM", "GD", "GY", "GU", "HN", "HT", "JM", "KY", "LB", + "LK", "MH", "MN", "MP", "MO", "MY", "NI", "PA", "PE", "PG", "PH", "PK", + "PR", "PW", "PY", "SG", "MX", "SV", "TC", "TH", "TT", "US", "UY", "VE", + "VI", "VN", "VU", "00" + /* Map "00" (world domain) to US region, + * as using the world domain is not recommended + */ +}; +static const char *const eu_codes[] = { + "AD", "AF", "AI", "AL", "AM", "AN", "AT", "AW", "AU", "AZ", "BA", "BE", + "BG", "BH", "BL", "BT", "BY", "CH", "CY", "CZ", "DE", "DK", "EE", "ES", + "FR", "GB", "GE", "GF", "GL", "GP", "GR", "GT", "HK", "HR", "HU", "ID", + "IE", "IL", "IN", "IR", "IS", "IT", "JO", "KH", "FI", "KN", "KW", "KZ", + "LC", "LI", "LT", "LU", "LV", "MD", "ME", "MK", "MF", "MT", "MV", "MQ", + "NL", "NO", "NZ", "OM", "PF", "PL", "PM", "PT", "QA", "RO", "RS", "RU", + "SA", "SE", "SI", "SK", "SR", "SY", "TR", "TW", "UA", "UZ", "VC", "WF", + "WS", "YE", "RE", "YT" +}; +static const char *const jp_codes[] = {"BD", "BN", "BO", "CL", "BZ", "JP", "NP"}; +static const char *const kr_codes[] = {"KR", "KP"}; +static const char *const cn_codes[] = {"CN"}; + +static const region_map_t region_maps[] = { + {us_codes, ARRAY_SIZE(us_codes), SL_WIFI_REGION_US, + &default_US_region_2_4GHZ_configurations}, + {eu_codes, ARRAY_SIZE(eu_codes), SL_WIFI_REGION_EU, + &default_EU_region_2_4GHZ_configurations}, + {jp_codes, ARRAY_SIZE(jp_codes), SL_WIFI_REGION_JP, + &default_JP_region_2_4GHZ_configurations}, + {kr_codes, ARRAY_SIZE(kr_codes), SL_WIFI_REGION_KR, + &default_KR_region_2_4GHZ_configurations}, + {cn_codes, ARRAY_SIZE(cn_codes), SL_WIFI_REGION_CN, + &default_CN_region_2_4GHZ_configurations}, +}; + +int siwx91x_store_country_code(const char *country_code) +{ + __ASSERT(country_code, "country_code cannot be NULL"); + + memcpy(current_country_code, country_code, WIFI_COUNTRY_CODE_LEN); + return 0; +} + +const char *siwx91x_get_country_code(void) +{ + return current_country_code; +} + +sl_wifi_region_code_t siwx91x_map_country_code_to_region(const char *country_code) +{ + __ASSERT(country_code, "country_code cannot be NULL"); + + ARRAY_FOR_EACH(region_maps, i) { + for (size_t j = 0; j < region_maps[i].num_codes; j++) { + if (memcmp(country_code, region_maps[i].codes[j], + WIFI_COUNTRY_CODE_LEN) == 0) { + return region_maps[i].region_code; + } + } + } + return SL_WIFI_DEFAULT_REGION; +} + +const sli_si91x_set_region_ap_request_t *siwx91x_find_sdk_region_table(uint8_t region_code) +{ + ARRAY_FOR_EACH(region_maps, i) { + if (region_maps[i].region_code == region_code) { + return region_maps[i].sdk_reg; + } + } + return NULL; +} + static void siwx91x_apply_sram_config(sl_si91x_boot_configuration_t *boot_config) { /* The size does not match exactly because 1 KB is reserved at the start of the RAM */ @@ -161,8 +251,8 @@ int siwx91x_get_nwp_config(sl_wifi_device_configuration_t *get_config, uint8_t w bool hidden_ssid, uint8_t max_num_sta) { sl_wifi_device_configuration_t default_config = { + .region_code = siwx91x_map_country_code_to_region(DEFAULT_COUNTRY_CODE), .band = SL_SI91X_WIFI_BAND_2_4GHZ, - .region_code = DEFAULT_REGION, .boot_option = LOAD_NWP_FW, .boot_config = { .feature_bit_map = SL_SI91X_FEAT_SECURITY_OPEN | SL_SI91X_FEAT_WPS_DISABLE | @@ -193,6 +283,7 @@ int siwx91x_get_nwp_config(sl_wifi_device_configuration_t *get_config, uint8_t w return -EINVAL; } + siwx91x_store_country_code(DEFAULT_COUNTRY_CODE); siwx91x_apply_sram_config(boot_config); switch (wifi_oper_mode) { diff --git a/soc/silabs/silabs_siwx91x/siwg917/nwp.h b/soc/silabs/silabs_siwx91x/siwg917/nwp.h index 978d7c44ec2ec..f67b5f83f5889 100644 --- a/soc/silabs/silabs_siwx91x/siwg917/nwp.h +++ b/soc/silabs/silabs_siwx91x/siwg917/nwp.h @@ -8,6 +8,7 @@ #include "sl_wifi.h" #define SIWX91X_INTERFACE_MASK (0x03) +#define DEFAULT_COUNTRY_CODE "00" /** * @brief Switch the Wi-Fi operating mode. @@ -24,4 +25,48 @@ */ int siwx91x_nwp_mode_switch(uint8_t oper_mode, bool hidden_ssid, uint8_t max_num_sta); +/** + * @brief Map an ISO/IEC 3166-1 alpha-2 country code to a Wi-Fi region code. + * + * This function maps a 2-character country code (e.g., "US", "FR", "JP") + * to the corresponding region code defined in the SDK (sl_wifi_region_code_t). + * If the country is not explicitly listed, it defaults to the US region. + * + * @param[in] country_code Pointer to a 2-character ISO country code. + * + * @return Corresponding sl_wifi_region_code_t value. + */ +sl_wifi_region_code_t siwx91x_map_country_code_to_region(const char *country_code); + +/** + * @brief Get the default SDK region configuration for a region code. + * + * Looks up the given sl_wifi_region_code_t and returns the corresponding + * SDK region configuration, or NULL if not found. + * + * @param[in] region_code Wi-Fi region code (SL_WIFI_REGION_*). + * + * @return Pointer to SDK region configuration, or NULL if unsupported. + */ +const sli_si91x_set_region_ap_request_t *siwx91x_find_sdk_region_table(uint8_t region_code); + +/** + * @brief Store the country code internally for GET operation. + * + * This function saves the provided country code to a static internal buffer. + * + * @param[in] country_code Pointer to a 2-character ISO country code. + */ +int siwx91x_store_country_code(const char *country_code); + +/** + * @brief Retrieve the currently stored country code. + * + * This function returns a pointer to the internally stored 2-character + * country code set by store_country_code(). + * + * @return Pointer to the stored country code string. + */ +const char *siwx91x_get_country_code(void); + #endif diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml index a6d139cb19462..cada35194443f 100644 --- a/soc/silabs/soc.yml +++ b/soc/silabs/soc.yml @@ -67,6 +67,9 @@ family: - name: efr32mg24b310f1536im48 - name: efr32mg24b210f1536im48 - name: efr32mg24b020f1536im40 + - name: bgm24 + socs: + - name: bgm240sa22vna - name: mgm24 socs: - name: mgm240sd22vna @@ -77,6 +80,9 @@ family: - name: efr32zg23 socs: - name: efr32zg23b020f512im48 + - name: efr32zg28 + socs: + - name: efr32zg28b322f1024im68 - name: efr32bg29 socs: - name: efr32bg29b140f1024im40 diff --git a/soc/st/stm32/common/ccm.ld b/soc/st/stm32/common/ccm.ld index 656b4567b6f37..bf9cf65d0306c 100644 --- a/soc/st/stm32/common/ccm.ld +++ b/soc/st/stm32/common/ccm.ld @@ -9,7 +9,7 @@ GROUP_START(CCM) *(.ccm_bss) *(".ccm_bss.*") __ccm_bss_end = .; - } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm))) + } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME_TOKEN(DT_CHOSEN(zephyr_ccm))) SECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4)) { @@ -17,7 +17,7 @@ GROUP_START(CCM) *(.ccm_noinit) *(".ccm_noinit.*") __ccm_noinit_end = .; - } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm))) + } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME_TOKEN(DT_CHOSEN(zephyr_ccm))) SECTION_PROLOGUE(_CCM_DATA_SECTION_NAME,,SUBALIGN(4)) { @@ -25,7 +25,7 @@ GROUP_START(CCM) *(.ccm_data) *(".ccm_data.*") __ccm_data_end = .; - } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)) AT> ROMABLE_REGION) + } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME_TOKEN(DT_CHOSEN(zephyr_ccm)) AT> ROMABLE_REGION) __ccm_end = .; diff --git a/soc/st/stm32/common/soc_config.c b/soc/st/stm32/common/soc_config.c index e600c4d553803..159a581ff9185 100644 --- a/soc/st/stm32/common/soc_config.c +++ b/soc/st/stm32/common/soc_config.c @@ -88,7 +88,7 @@ static int st_stm32_common_config(void) #else -/* keeping in mind that debugging draws a lot of power we explcitly disable when not needed */ +/* keeping in mind that debugging draws a lot of power we explicitly disable when not needed */ #if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32L1X) LL_DBGMCU_DisableDBGSleepMode(); LL_DBGMCU_DisableDBGStopMode(); diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml index 76fd943ad3e16..e09cd9b1eba80 100644 --- a/soc/st/stm32/soc.yml +++ b/soc/st/stm32/soc.yml @@ -104,6 +104,7 @@ family: - name: stm32h5x socs: - name: stm32h503xx + - name: stm32h523xx - name: stm32h533xx - name: stm32h562xx - name: stm32h563xx diff --git a/soc/st/stm32/stm32c0x/CMakeLists.txt b/soc/st/stm32/stm32c0x/CMakeLists.txt index 8065e36bf13aa..915db18dfe3d1 100644 --- a/soc/st/stm32/stm32c0x/CMakeLists.txt +++ b/soc/st/stm32/stm32c0x/CMakeLists.txt @@ -6,6 +6,7 @@ zephyr_sources( ) zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) +zephyr_sources_ifdef(CONFIG_PM power.c) zephyr_include_directories(.) diff --git a/soc/st/stm32/stm32c0x/Kconfig b/soc/st/stm32/stm32c0x/Kconfig index 1d9770c4e6079..2985fa5f8b16c 100644 --- a/soc/st/stm32/stm32c0x/Kconfig +++ b/soc/st/stm32/stm32c0x/Kconfig @@ -10,5 +10,6 @@ config SOC_SERIES_STM32C0X select CPU_HAS_ARM_MPU select HAS_STM32CUBE select CPU_CORTEX_M_HAS_SYSTICK + select HAS_PM select HAS_POWEROFF select SOC_EARLY_INIT_HOOK diff --git a/soc/st/stm32/stm32c0x/Kconfig.defconfig b/soc/st/stm32/stm32c0x/Kconfig.defconfig index b960c560bc5cc..1a6f727d8abd0 100644 --- a/soc/st/stm32/stm32c0x/Kconfig.defconfig +++ b/soc/st/stm32/stm32c0x/Kconfig.defconfig @@ -7,4 +7,14 @@ if SOC_SERIES_STM32C0X rsource "Kconfig.defconfig.stm32c0*" +if PM + +config COUNTER + default y + +config COUNTER_RTC_STM32_SUBSECONDS + default y if DT_HAS_ST_STM32_RTC_ENABLED + +endif # PM + endif # SOC_SERIES_STM32C0X diff --git a/soc/st/stm32/stm32c0x/power.c b/soc/st/stm32/stm32c0x/power.c new file mode 100644 index 0000000000000..3eb212e247d6c --- /dev/null +++ b/soc/st/stm32/stm32c0x/power.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2023 Google LLC + * Copyright (c) 2025 Tomas Jurena + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include +#include + +#include +#include + +LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); + +BUILD_ASSERT(DT_SAME_NODE(DT_CHOSEN(zephyr_cortex_m_idle_timer), DT_NODELABEL(rtc)), + "STM32C0x series needs RTC as an additional IDLE timer for power management"); + +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_SUSPEND_TO_IDLE: + LL_LPM_DisableEventOnPend(); + LL_PWR_ClearFlag_WU(); + + LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0); + LL_LPM_EnableDeepSleep(); + + k_cpu_idle(); + + break; + default: + LOG_WRN("Unsupported power state %u", state); + break; + } +} + +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_SUSPEND_TO_IDLE: + LL_LPM_DisableSleepOnExit(); + LL_LPM_EnableSleep(); + + /* Restore the clock setup. */ + stm32_clock_control_init(NULL); + break; + default: + LOG_WRN("Unsupported power substate-id %u", state); + break; + } + + /* + * System is now in active mode. Reenable interrupts which were + * disabled when OS started idling code. + */ + irq_unlock(0); +} diff --git a/soc/st/stm32/stm32c0x/soc.c b/soc/st/stm32/stm32c0x/soc.c index e1337f66923b6..030c380110cd0 100644 --- a/soc/st/stm32/stm32c0x/soc.c +++ b/soc/st/stm32/stm32c0x/soc.c @@ -14,6 +14,7 @@ #include #include +#include #include #include @@ -32,4 +33,7 @@ void soc_early_init_hook(void) /* Update CMSIS SystemCoreClock variable (HCLK) */ /* At reset, system core clock is set to 48 MHz from HSI */ SystemCoreClock = 48000000; + + /* Enable PWR clock */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); } diff --git a/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h523xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h523xx new file mode 100644 index 0000000000000..42503ad05ddda --- /dev/null +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h523xx @@ -0,0 +1,11 @@ +# STMicroelectronics STM32H523XX MCU + +# Copyright (c) Filip Stojanovic +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H523XX + +config NUM_IRQS + default 133 + +endif # SOC_STM32H523XX diff --git a/soc/st/stm32/stm32h5x/Kconfig.soc b/soc/st/stm32/stm32h5x/Kconfig.soc index abc8b16f34c7a..1afb40f8c080c 100644 --- a/soc/st/stm32/stm32h5x/Kconfig.soc +++ b/soc/st/stm32/stm32h5x/Kconfig.soc @@ -14,6 +14,10 @@ config SOC_STM32H503XX bool select SOC_SERIES_STM32H5X +config SOC_STM32H523XX + bool + select SOC_SERIES_STM32H5X + config SOC_STM32H533XX bool select SOC_SERIES_STM32H5X @@ -32,6 +36,7 @@ config SOC_STM32H573XX config SOC default "stm32h503xx" if SOC_STM32H503XX + default "stm32h523xx" if SOC_STM32H523XX default "stm32h533xx" if SOC_STM32H533XX default "stm32h562xx" if SOC_STM32H562XX default "stm32h563xx" if SOC_STM32H563XX diff --git a/soc/st/stm32/stm32n6x/CMakeLists.txt b/soc/st/stm32/stm32n6x/CMakeLists.txt index c2a8c56b3c0d1..966ce4a109f4d 100644 --- a/soc/st/stm32/stm32n6x/CMakeLists.txt +++ b/soc/st/stm32/stm32n6x/CMakeLists.txt @@ -5,6 +5,10 @@ zephyr_sources( soc.c ) +zephyr_sources_ifdef(CONFIG_STM32N6_NPU + npu/npu_stm32n6.c + ) + zephyr_include_directories(.) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32n6x/Kconfig b/soc/st/stm32/stm32n6x/Kconfig index 548dea00772fb..791efe077ecaa 100644 --- a/soc/st/stm32/stm32n6x/Kconfig +++ b/soc/st/stm32/stm32n6x/Kconfig @@ -23,3 +23,10 @@ config SOC_SERIES_STM32N6X config STM32N6_BOOT_SERIAL bool "Serial boot target (USB)" + +config STM32N6_NPU + bool "Neural-ART accelerator (NPU)" + select USE_STM32_HAL_RIF + select RESET + default y + depends on DT_HAS_ST_STM32_NPU_ENABLED diff --git a/soc/st/stm32/stm32n6x/npu/npu_stm32n6.c b/soc/st/stm32/stm32n6x/npu/npu_stm32n6.c new file mode 100644 index 0000000000000..77c307f649687 --- /dev/null +++ b/soc/st/stm32/stm32n6x/npu/npu_stm32n6.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT st_stm32_npu + +#include + +#include +#include +#include +#include + +#include + +/* Read-only driver configuration */ +struct npu_stm32_cfg { + /* Clock configuration. */ + struct stm32_pclken pclken; + /* Reset configuration */ + const struct reset_dt_spec reset; +}; + +static void npu_risaf_config(void) +{ + RIMC_MasterConfig_t RIMC_master = {0}; + + RIMC_master.MasterCID = RIF_CID_1; + RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV; + HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_NPU, &RIMC_master); + HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_NPU, + RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV); +} + +static int npu_stm32_init(const struct device *dev) +{ + const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); + const struct npu_stm32_cfg *cfg = dev->config; + + if (!device_is_ready(clk)) { + return -ENODEV; + } + + if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken) != 0) { + return -EIO; + } + + if (!device_is_ready(cfg->reset.dev)) { + return -ENODEV; + } + + /* Reset timer to default state using RCC */ + (void)reset_line_toggle_dt(&cfg->reset); + + npu_risaf_config(); + + return 0; +} + + +static const struct npu_stm32_cfg npu_stm32_cfg = { + .pclken = { + .enr = DT_CLOCKS_CELL(DT_NODELABEL(npu), bits), + .bus = DT_CLOCKS_CELL(DT_NODELABEL(npu), bus), + }, + .reset = RESET_DT_SPEC_GET(DT_NODELABEL(npu)), +}; + +DEVICE_DT_DEFINE(DT_NODELABEL(npu), npu_stm32_init, NULL, + NULL, &npu_stm32_cfg, POST_KERNEL, + CONFIG_APPLICATION_INIT_PRIORITY, NULL); diff --git a/soc/st/stm32/stm32wbax/Kconfig b/soc/st/stm32/stm32wbax/Kconfig index e01cf2f2be903..d9f65049b139e 100644 --- a/soc/st/stm32/stm32wbax/Kconfig +++ b/soc/st/stm32/stm32wbax/Kconfig @@ -18,3 +18,6 @@ config SOC_SERIES_STM32WBAX select HAS_PM select HAS_POWEROFF select SOC_EARLY_INIT_HOOK + select PM_DEVICE if PM + select PM_DEVICE_RUNTIME if PM + select PM_DEVICE_SYSTEM_MANAGED if PM diff --git a/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c index 19f3697de8b55..48bacb00ca885 100644 --- a/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c +++ b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c @@ -10,7 +10,8 @@ #include -#include "scm.h" +#include +#include #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL LOG_MODULE_REGISTER(linklayer_plat_adapt); @@ -245,8 +246,6 @@ void LINKLAYER_PLAT_StartRadioEvt(void) __HAL_RCC_RADIO_CLK_SLEEP_ENABLE(); NVIC_SetPriority((IRQn_Type)RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH_Z); - - scm_notifyradiostate(SCM_RADIO_ACTIVE); } void LINKLAYER_PLAT_StopRadioEvt(void) @@ -254,8 +253,6 @@ void LINKLAYER_PLAT_StopRadioEvt(void) __HAL_RCC_RADIO_CLK_SLEEP_DISABLE(); NVIC_SetPriority((IRQn_Type)RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW_Z); - - scm_notifyradiostate(SCM_RADIO_NOT_ACTIVE); } /* Link Layer notification for RCO calibration start */ diff --git a/soc/st/stm32/stm32wbax/power.c b/soc/st/stm32/stm32wbax/power.c index 43fcd67b6124b..73e81d291f84e 100644 --- a/soc/st/stm32/stm32wbax/power.c +++ b/soc/st/stm32/stm32wbax/power.c @@ -10,6 +10,12 @@ #include #include #include +#include +#include +#include +#include + +#include #include #include @@ -18,69 +24,75 @@ #include #include -#ifdef CONFIG_BT_STM32WBA -#include "scm.h" -#endif - #include LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); -void stm32_power_init(void); -static void set_mode_stop(uint8_t substate_id) -{ +#define HSE_ON (READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) - LL_PWR_ClearFlag_STOP(); - LL_RCC_ClearResetFlags(); +static uint32_t ram_waitstates_backup; +static uint32_t flash_latency_backup; - /* Erratum 2.2.15: - * Disabling ICACHE is required before entering stop mode - */ - sys_cache_instr_disable(); - -#ifdef CONFIG_BT_STM32WBA - scm_setwaitstates(LP); +#if defined(CONFIG_PM_S2RAM) +static struct fpu_ctx_full fpu_state; +static struct scb_context scb_state; +static struct z_mpu_context_retained mpu_state; #endif - /* Set SLEEPDEEP bit of Cortex System Control Register */ + +static int enter_low_power_mode(void) +{ + uint32_t basepri; + LL_LPM_EnableDeepSleep(); while (LL_PWR_IsActiveFlag_ACTVOS() == 0) { } - switch (substate_id) { - case 1: /* enter STOP0 mode */ - LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0); - break; - case 2: /* enter STOP1 mode */ - LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1); - break; - default: - LOG_DBG("Unsupported power state substate-id %u", substate_id); - break; - } -} + /* + * Prevent spurious entry in low-power state if any + * interrupt is currently pending. The WFI instruction + * will not enter low-power state if an interrupt with + * higher priority than BASEPRI is pending, regardless + * of the value of PRIMASK. + * + * When this function executes, Zephyr's arch_irq_lock() has + * configured BASEPRI to mask interrupts. Set PRIMASK to keep + * interrupts masked then lower BASEPRI to 0, after saving its + * current value, so that any pending interrupt is seen by WFI + * and inhibits low-power state entry. + */ + __disable_irq(); + basepri = __get_BASEPRI(); + __set_BASEPRI(0); + __ISB(); + __DSB(); -#if defined(CONFIG_PM_S2RAM) -static int suspend_to_ram(void) -{ - LL_LPM_EnableDeepSleep(); + /* Attempt entry in low-power state */ + __WFI(); - while (LL_PWR_IsActiveFlag_ACTVOS() == 0) { - } + /* + * If entry in STOP mode was attempted, execution + * resumes here regardless of success or failure. + * If entry in STANDBY mode was attempted, execution + * will reach this point only if entry in low-power + * state did not occur. Restore BASEPRI and clear + * PRIMASK then return an error to indicate that + * entry in STANDBY mode failed (return value of + * this function is ignored for STOP mode entry). + */ + __set_BASEPRI(basepri); + __enable_irq(); - /* Select mode entry : WFE or WFI and enter the CPU selected mode */ - k_cpu_idle(); + /* Disable SLEEPDEEP at Cortex-M level */ + LL_LPM_EnableSleep(); - return 0; + return -EBUSY; } -static void set_mode_suspend_to_ram(void) +#if defined(CONFIG_PM_S2RAM) +static void set_mode_suspend_to_ram_enter(void) { - /* Enable SRAM full retention */ - LL_PWR_SetSRAM1SBRetention(LL_PWR_SRAM1_SB_FULL_RETENTION); - LL_PWR_SetSRAM2SBRetention(LL_PWR_SRAM2_SB_FULL_RETENTION); - /* Enable RTC wakeup * This configures an internal pin that generates an event to wakeup the system */ @@ -97,88 +109,124 @@ static void set_mode_suspend_to_ram(void) /* Select standby mode */ LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY); + /* Save FPU, SCB and MPU states */ + z_arm_save_fp_context(&fpu_state); + z_arm_save_scb_context(&scb_state); +#if defined(CONFIG_ARM_MPU) + z_arm_save_mpu_context(&mpu_state); +#endif /* CONFIG_ARM_MPU */ /* Save context and enter Standby mode */ - arch_pm_s2ram_suspend(suspend_to_ram); + arch_pm_s2ram_suspend(enter_low_power_mode); +} + +static void set_mode_suspend_to_ram_exit(void) +{ + /* Save MPU, SCB and FPU states */ +#if defined(CONFIG_ARM_MPU) + z_arm_restore_mpu_context(&mpu_state); +#endif /* CONFIG_ARM_MPU */ + z_arm_restore_scb_context(&scb_state); + z_arm_restore_fp_context(&fpu_state); + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_RAMCFG_CLK_ENABLE(); - /* Execution is restored at this point after wake up */ /* Restore system clock as soon as we exit standby mode */ stm32_clock_control_standby_exit(); + + if (LL_PWR_IsActiveFlag_SB() || !HSE_ON) { + stm32_clock_control_init(NULL); + } + /* Resume configuration */ + stm32wba_init(); + stm32_power_init(); } #endif -/* Invoke Low Power/System Off specific Tasks */ -void pm_state_set(enum pm_state state, uint8_t substate_id) +static void set_mode_stop_enter(uint8_t substate_id) { - switch (state) { - case PM_STATE_SUSPEND_TO_IDLE: - set_mode_stop(substate_id); - - /* Select mode entry : WFE or WFI and enter the CPU selected mode */ - k_cpu_idle(); + LL_PWR_ClearFlag_STOP(); + LL_RCC_ClearResetFlags(); + /* Erratum 2.2.15: + * Disabling ICACHE is required before entering stop mode + */ + sys_cache_instr_disable(); + /* If stop mode is greater than 1, manage flash latency and RAMCFG */ + if (substate_id > 1) { + flash_latency_backup = __HAL_FLASH_GET_LATENCY(); + if (flash_latency_backup < FLASH_LATENCY_1) { + /* Set flash latency to 1, since system will restart from HSI16 */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1); + while (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_1) { + } + } + ram_waitstates_backup = READ_BIT(RAMCFG_SRAM1->CR, RAMCFG_CR_WSC); + MODIFY_REG(RAMCFG_SRAM1->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); + MODIFY_REG(RAMCFG_SRAM2->CR, RAMCFG_CR_WSC, RAMCFG_WAITSTATE_1); + } + switch (substate_id) { + case 1: + LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0); break; -#if defined(CONFIG_PM_S2RAM) - case PM_STATE_SUSPEND_TO_RAM: - set_mode_suspend_to_ram(); + case 2: + LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1); break; -#endif default: - LOG_DBG("Unsupported power state %u", state); + LOG_DBG("Unsupported power state substate-id %u", substate_id); return; } + + enter_low_power_mode(); } -/* Handle SOC specific activity after Low Power Mode Exit */ -void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +static void set_mode_stop_exit(uint8_t substate_id) { -#ifdef CONFIG_BT_STM32WBA - if (LL_PWR_IsActiveFlag_STOP() == 1U) { - scm_setup(); + if (LL_PWR_IsActiveFlag_STOP() || !HSE_ON) { + /* Reconfigure the clock (incl. RAM/FLASH latency) */ + stm32_clock_control_init(NULL); } else { - scm_setwaitstates(RUN); + /* Stop mode skipped */ + if (substate_id > 1) { + __HAL_FLASH_SET_LATENCY(flash_latency_backup); + while (__HAL_FLASH_GET_LATENCY() != flash_latency_backup) { + } + MODIFY_REG(RAMCFG_SRAM1->CR, RAMCFG_CR_WSC, ram_waitstates_backup); + MODIFY_REG(RAMCFG_SRAM2->CR, RAMCFG_CR_WSC, ram_waitstates_backup); + } } -#endif + /* Erratum 2.2.15: + * Enable ICACHE when exiting stop mode + */ + sys_cache_instr_enable(); +} + +/* Invoke Low Power/System Off specific Tasks */ +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ switch (state) { case PM_STATE_SUSPEND_TO_IDLE: - if (substate_id <= 2) { - /* Erratum 2.2.15: - * Enable ICACHE when exiting stop mode - */ - sys_cache_instr_enable(); - - LL_LPM_DisableSleepOnExit(); - LL_LPM_EnableSleep(); - } else { - LOG_DBG("Unsupported power substate-id %u", - substate_id); - } + set_mode_stop_enter(substate_id); + /* Resume here */ + set_mode_stop_exit(substate_id); break; - case PM_STATE_SUSPEND_TO_RAM: #if defined(CONFIG_PM_S2RAM) - stm32wba_init(); - stm32_power_init(); - - LL_LPM_DisableSleepOnExit(); - LL_LPM_EnableSleep(); -#else - LOG_DBG("Suspend to RAM needs CONFIG_PM_S2RAM to be enabled"); -#endif + case PM_STATE_SUSPEND_TO_RAM: + set_mode_suspend_to_ram_enter(); + /* Resume here */ + set_mode_suspend_to_ram_exit(); break; - case PM_STATE_STANDBY: - __fallthrough; - case PM_STATE_SUSPEND_TO_DISK: - __fallthrough; +#endif default: LOG_DBG("Unsupported power state %u", state); - break; + return; } +} - /* When BLE is enabled, clock restoration is performed by SCM */ -#if !defined(CONFIG_BT_STM32WBA) - stm32_clock_control_init(NULL); -#endif - +/* Handle SOC specific activity after Low Power Mode Exit */ +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ /* * System is now in active mode. * Reenable interrupts which were disabled @@ -191,10 +239,6 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) void stm32_power_init(void) { -#ifdef CONFIG_BT_STM32WBA - scm_init(); -#endif - LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR); #ifdef CONFIG_DEBUG @@ -205,6 +249,13 @@ void stm32_power_init(void) LL_DBGMCU_DisableDBGStandbyMode(); #endif + /* Enable SRAM full retention */ + LL_PWR_SetSRAM1SBRetention(LL_PWR_SRAM1_SB_FULL_RETENTION); + LL_PWR_SetSRAM2SBRetention(LL_PWR_SRAM2_SB_FULL_RETENTION); + + /* Enable Radio RAM full retention */ + LL_PWR_SetRadioSBRetention(LL_PWR_RADIO_SB_FULL_RETENTION); + /* Enabling Ultra Low power mode */ LL_PWR_EnableUltraLowPowerMode(); diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig index 9e9f3cb321a84..dd9f43249adb6 100644 --- a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig @@ -66,6 +66,6 @@ config CC13X2_CC26X2_XOSC_CAPARRAY_DELTA range 0 0xFF default 0xD5 help - Enable a specific cap array tunning delta. + Enable a specific cap array tuning delta. endmenu diff --git a/soc/xlnx/versalnet/CMakeLists.txt b/soc/xlnx/versalnet/CMakeLists.txt index a6ccdf4f20302..489b2d1129d09 100644 --- a/soc/xlnx/versalnet/CMakeLists.txt +++ b/soc/xlnx/versalnet/CMakeLists.txt @@ -4,12 +4,14 @@ # SPDX-License-Identifier: Apache-2.0 # -zephyr_sources( - soc.c -) zephyr_sources_ifdef( CONFIG_ARM_MPU arm_mpu_regions.c + soc.c +) +zephyr_sources_ifdef( + CONFIG_ARM_MMU + arm_mmu_regions.c ) zephyr_include_directories(.) @@ -17,3 +19,7 @@ zephyr_include_directories(.) if(CONFIG_SOC_AMD_VERSALNET_RPU) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") endif() + +if(CONFIG_SOC_AMD_VERSALNET_APU) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/xlnx/versalnet/Kconfig b/soc/xlnx/versalnet/Kconfig index 89e185d62664a..952cd8651abd0 100644 --- a/soc/xlnx/versalnet/Kconfig +++ b/soc/xlnx/versalnet/Kconfig @@ -13,3 +13,9 @@ config SOC_AMD_VERSALNET_RPU select GIC_SINGLE_SECURITY_STATE select CPU_HAS_ARM_MPU select ARM_MPU + +config SOC_AMD_VERSALNET_APU + select ARM64 + select ARM_ARCH_TIMER + select CPU_CORTEX_A78 + select CPU_HAS_MMU diff --git a/soc/xlnx/versalnet/Kconfig.defconfig b/soc/xlnx/versalnet/Kconfig.defconfig index 7997b8feb6962..03ae4c6888bbf 100644 --- a/soc/xlnx/versalnet/Kconfig.defconfig +++ b/soc/xlnx/versalnet/Kconfig.defconfig @@ -22,4 +22,19 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC endif # SOC_AMD_VERSALNET_RPU +if SOC_AMD_VERSALNET_APU + +CONFIG_CACHE_MANAGEMENT=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_CACHE_MANAGEMENT=y + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + default 256 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_AMD_VERSALNET_APU endif # SOC_AMD_VERSALNET diff --git a/soc/xlnx/versalnet/Kconfig.soc b/soc/xlnx/versalnet/Kconfig.soc index 181a2100d9bf3..f2eb665b03378 100644 --- a/soc/xlnx/versalnet/Kconfig.soc +++ b/soc/xlnx/versalnet/Kconfig.soc @@ -11,10 +11,17 @@ config SOC_AMD_VERSALNET_RPU bool select SOC_AMD_VERSALNET help - AMD Versal NET SoC + AMD Versal NET SoC RPU + +config SOC_AMD_VERSALNET_APU + bool + select SOC_AMD_VERSALNET + help + AMD Versal NET SoC APU config SOC_FAMILY default "amd_versalnet" if SOC_AMD_VERSALNET config SOC default "amd_versalnet_rpu" if SOC_AMD_VERSALNET_RPU + default "amd_versalnet_apu" if SOC_AMD_VERSALNET_APU diff --git a/soc/xlnx/versalnet/arm_mmu_regions.c b/soc/xlnx/versalnet/arm_mmu_regions.c new file mode 100644 index 0000000000000..11a5f09f55b53 --- /dev/null +++ b/soc/xlnx/versalnet/arm_mmu_regions.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/xlnx/versalnet/soc.yml b/soc/xlnx/versalnet/soc.yml index 8de1e6c40f4fa..9f206c8424f41 100644 --- a/soc/xlnx/versalnet/soc.yml +++ b/soc/xlnx/versalnet/soc.yml @@ -2,3 +2,4 @@ family: - name: amd_versalnet socs: - name: amd_versalnet_rpu + - name: amd_versalnet_apu diff --git a/soc/xlnx/zynqmp/Kconfig.defconfig b/soc/xlnx/zynqmp/Kconfig.defconfig index 869f4403d3202..10ab718bd60b7 100644 --- a/soc/xlnx/zynqmp/Kconfig.defconfig +++ b/soc/xlnx/zynqmp/Kconfig.defconfig @@ -12,7 +12,7 @@ config NUM_IRQS default 220 config SYS_CLOCK_HW_CYCLES_PER_SEC - default 5000000 + default $(dt_nodelabel_int_prop,ttc0,clock-frequency) endif # SOC_XILINX_ZYNQMP_RPU diff --git a/soc/xlnx/zynqmp/arm_mpu_regions.c b/soc/xlnx/zynqmp/arm_mpu_regions.c index a4f36402d2cc7..73fc8bdb073dc 100644 --- a/soc/xlnx/zynqmp/arm_mpu_regions.c +++ b/soc/xlnx/zynqmp/arm_mpu_regions.c @@ -1,62 +1,76 @@ /* SPDX-License-Identifier: Apache-2.0 * * Copyright (c) 2021 Lexmark International, Inc. + * Copyright (c) 2025 Immo Birnbaum */ #include -#include +#include -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +extern const uint32_t __rom_region_start; +extern const uint32_t __rom_region_mpu_size_bits; -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } - -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } - -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } - -extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), - - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), - - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), - - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + /* + * The address of the vectors is determined by arch/arm/core/cortex_a_r/prep_c.c + * -> for v7-R, there's no other option than 0x0, HIVECS always gets cleared + */ + MPU_REGION_ENTRY( + "vectors", + 0x00000000, + REGION_64B, + {.rasr = P_RO_U_NA_Msk | + NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + /* Basic SRAM mapping is all data, R/W + XN */ + MPU_REGION_ENTRY( + "sram", + CONFIG_SRAM_BASE_ADDRESS, + REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), +#if defined(CONFIG_XIP) + /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), + /* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ + /* .text and .rodata are in RAM, flash is data only -> RO + XN */ + MPU_REGION_ENTRY( + "flash", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | + NOT_EXEC}), + /* add rom_region mapping for SRAM which is RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), +#endif /* CONFIG_XIP */ + MPU_REGION_ENTRY( + "peripherals", + 0xf8000000, + REGION_128M, + {.rasr = P_RW_U_NA_Msk | + DEVICE_SHAREABLE | + NOT_EXEC}), +#if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)) + MPU_REGION_ENTRY( + "ocm", + DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)), + REGION_256K, + {.rasr = FULL_ACCESS_Msk | + STRONGLY_ORDERED_SHAREABLE | + NOT_EXEC}), +#endif }; const struct arm_mpu_config mpu_config = { diff --git a/subsys/CMakeLists.txt b/subsys/CMakeLists.txt index 340c7d09e3d7e..e6d83e9c85ea0 100644 --- a/subsys/CMakeLists.txt +++ b/subsys/CMakeLists.txt @@ -39,6 +39,9 @@ add_subdirectory_ifdef(CONFIG_ARM_SIP_SVC_SUBSYS sip_svc) add_subdirectory_ifdef(CONFIG_BINDESC bindesc) add_subdirectory_ifdef(CONFIG_BT bluetooth) add_subdirectory_ifdef(CONFIG_CONSOLE_SUBSYS console) +add_subdirectory_ifdef(CONFIG_CPU_FREQ cpu_freq) +add_subdirectory_ifdef(CONFIG_CPU_LOAD_METRIC cpu_load) +add_subdirectory_ifdef(CONFIG_CRC crc) add_subdirectory_ifdef(CONFIG_DAP dap) add_subdirectory_ifdef(CONFIG_DEMAND_PAGING demand_paging) add_subdirectory_ifdef(CONFIG_DISK_ACCESS disk) diff --git a/subsys/Kconfig b/subsys/Kconfig index db6990eb1d029..748ae9981db0e 100644 --- a/subsys/Kconfig +++ b/subsys/Kconfig @@ -11,6 +11,9 @@ source "subsys/bindesc/Kconfig" source "subsys/bluetooth/Kconfig" source "subsys/canbus/Kconfig" source "subsys/console/Kconfig" +source "subsys/cpu_freq/Kconfig" +source "subsys/cpu_load/Kconfig" +source "subsys/crc/Kconfig" source "subsys/dap/Kconfig" source "subsys/debug/Kconfig" source "subsys/demand_paging/Kconfig" diff --git a/subsys/bindesc/Kconfig b/subsys/bindesc/Kconfig index 50de5286d6b5d..b8e880e1d2ec2 100644 --- a/subsys/bindesc/Kconfig +++ b/subsys/bindesc/Kconfig @@ -27,7 +27,7 @@ config BINDESC_DEFINE_MAX_DATA_SIZE help Determines the maximum size of a binary descriptor's data. The theoretical limit to this value is the maximum value of a uint16_t (65535), in practice - it's recommened to keep this value much smaller for easier handling of the data. + it's recommended to keep this value much smaller for easier handling of the data. endif # BINDESC_DEFINE diff --git a/subsys/bluetooth/audio/Kconfig.bap b/subsys/bluetooth/audio/Kconfig.bap index 01ab717f379dc..0e23d203a5332 100644 --- a/subsys/bluetooth/audio/Kconfig.bap +++ b/subsys/bluetooth/audio/Kconfig.bap @@ -1,7 +1,7 @@ # Bluetooth Audio - Basic Audio Profile configuration options # # Copyright (c) 2020 Intel Corporation -# Copyright (c) 2022-2023 Nordic Semiconductor ASA +# Copyright (c) 2022-2025 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 # @@ -283,5 +283,51 @@ config BT_BAP_DEBUG_STREAM_SEQ_NUM config BT_BAP_BASE def_bool BT_BAP_BROADCAST_SINK || BT_BAP_BROADCAST_ASSISTANT || BT_BAP_SCAN_DELEGATOR +# We use BT_BAP_STREAM as a common ground for audio, as that is set whenever +# any audio stream functionality is enabled. +if LIBLC3 && USBD_AUDIO2_CLASS && BT_SHELL && BT_BAP_STREAM +config BT_BAP_SHELL_USB_PRODUCT + string "USB device sample product string" + default "Zephyr Audio Shell" + help + USB device sample product string. + +config BT_BAP_SHELL_USB_VID + hex "USB device sample Vendor ID" + default 0x2fe3 + help + USB device sample Vendor ID. Defaults to the Zephyr Project. + +config BT_BAP_SHELL_USB_PID + hex "USB device sample Product ID" + default 0x0001 + help + USB device sample Product ID. + +config BT_BAP_SHELL_USB_SELF_POWERED + bool "USB device sample Self-powered attribute" + default y + help + Set the Self-powered attribute in the sample configuration. + +config BT_BAP_SHELL_USB_REMOTE_WAKEUP + bool "USB device sample Remote Wakeup attribute" + help + Set the Remote Wakeup attribute in the sample configuration. + +config BT_BAP_SHELL_USB_MAX_POWER + int "USB device sample bMaxPower value" + default 125 + range 0 250 + help + bMaxPower value in the sample configuration in 2 mA units. + +config BT_BAP_SHELL_USB_20_EXTENSION_DESC + bool "Use default USB 2.0 Extension Descriptor" + depends on USBD_BOS_SUPPORT + help + Set bcdUSB value to 0201 and use default USB 2.0 Extension Descriptor. +endif # LIBLC3 && USBD_AUDIO2_CLASS && BT_SHELL && BT_BAP_STREAM + rsource "Kconfig.pacs" rsource "Kconfig.ascs" diff --git a/subsys/bluetooth/audio/Kconfig.ccp b/subsys/bluetooth/audio/Kconfig.ccp index c397b831cfc01..95d2aac65e72a 100644 --- a/subsys/bluetooth/audio/Kconfig.ccp +++ b/subsys/bluetooth/audio/Kconfig.ccp @@ -50,6 +50,13 @@ config BT_CCP_CALL_CONTROL_SERVER_BEARER_COUNT help The number of supported telephone bearers on the CCP Call Control Server +config BT_CCP_CALL_CONTROL_SERVER_PROVIDER_NAME_MAX_LENGTH + int "The maximum length of the bearer provider name excluding null terminator" + default BT_TBS_MAX_PROVIDER_NAME_LENGTH + range 1 BT_TBS_MAX_PROVIDER_NAME_LENGTH + help + Sets the maximum length of the bearer provider name. + module = BT_CCP_CALL_CONTROL_SERVER module-str = "Call Control Profile Call Control Server" source "subsys/logging/Kconfig.template.log_config" diff --git a/subsys/bluetooth/audio/Kconfig.tbs b/subsys/bluetooth/audio/Kconfig.tbs index 557786a833cdb..3a06931495b09 100644 --- a/subsys/bluetooth/audio/Kconfig.tbs +++ b/subsys/bluetooth/audio/Kconfig.tbs @@ -263,7 +263,7 @@ config BT_TBS_MAX_URI_LENGTH config BT_TBS_MAX_PROVIDER_NAME_LENGTH int "The maximum length of the bearer provider name" default 30 - range 0 512 + range 1 512 help Sets the maximum length of the bearer provider name. diff --git a/subsys/bluetooth/audio/aics.c b/subsys/bluetooth/audio/aics.c index 732a85e7d6955..7c5fc5a5fcd83 100644 --- a/subsys/bluetooth/audio/aics.c +++ b/subsys/bluetooth/audio/aics.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "aics_internal.h" diff --git a/subsys/bluetooth/audio/ascs.c b/subsys/bluetooth/audio/ascs.c index 80ddeb7ff337d..48ed34cfd5704 100644 --- a/subsys/bluetooth/audio/ascs.c +++ b/subsys/bluetooth/audio/ascs.c @@ -66,7 +66,7 @@ BUILD_ASSERT(CONFIG_BT_ASCS_MAX_ACTIVE_ASES <= MAX(MAX_ASES_SESSIONS, #if defined(CONFIG_BT_BAP_UNICAST_SERVER) -#define ASE_ID(_ase) ase->ep.status.id +#define ASE_ID(_ase) ase->ep.id #define ASE_DIR(_id) \ (_id > CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT ? BT_AUDIO_DIR_SOURCE : BT_AUDIO_DIR_SINK) #define ASE_UUID(_id) \ @@ -178,16 +178,11 @@ static bool is_valid_ase_id(uint8_t ase_id) return IN_RANGE(ase_id, 1, ASE_COUNT); } -static enum bt_bap_ep_state ascs_ep_get_state(struct bt_bap_ep *ep) -{ - return ep->status.state; -} - static void ase_free(struct bt_ascs_ase *ase) { __ASSERT(ase && ase->conn, "Non-existing ASE"); - LOG_DBG("conn %p ase %p id 0x%02x", (void *)ase->conn, ase, ase->ep.status.id); + LOG_DBG("conn %p ase %p id 0x%02x", (void *)ase->conn, ase, ASE_ID(ase)); if (ase->ep.iso != NULL) { bt_bap_iso_unbind_ep(ase->ep.iso, &ase->ep); @@ -270,7 +265,7 @@ static void ascs_disconnect_stream_work_handler(struct k_work *work) __ASSERT(pair_stream->ep != NULL, "Invalid pair_stream %p", pair_stream); - if (pair_stream->ep->status.state == BT_BAP_EP_STATE_STREAMING) { + if (pair_stream->ep->state == BT_BAP_EP_STATE_STREAMING) { /* Should not disconnect ISO if the stream is paired * with another one in the streaming state */ @@ -412,9 +407,9 @@ static void ase_metadata_updated(struct bt_ascs_ase *ase) static void ase_exit_state_streaming(struct bt_ascs_ase *ase) { + const enum bt_bap_ep_state next_state = ase->ep.state; struct bt_bap_stream *stream = ase->ep.stream; struct bt_bap_stream_ops *ops; - const enum bt_bap_ep_state next_state = ascs_ep_get_state(&ase->ep); uint8_t reason = ase->ep.reason; __ASSERT_NO_MSG(stream != NULL); @@ -456,9 +451,9 @@ static void ase_exit_state_streaming(struct bt_ascs_ase *ase) static void ase_exit_state_enabling(struct bt_ascs_ase *ase) { + const enum bt_bap_ep_state next_state = ase->ep.state; struct bt_bap_stream *stream = ase->ep.stream; struct bt_bap_stream_ops *ops; - const enum bt_bap_ep_state next_state = ascs_ep_get_state(&ase->ep); ops = stream->ops; @@ -519,11 +514,11 @@ static void state_transition_work_handler(struct k_work *work) { struct k_work_delayable *d_work = k_work_delayable_from_work(work); struct bt_ascs_ase *ase = CONTAINER_OF(d_work, struct bt_ascs_ase, state_transition_work); - const enum bt_bap_ep_state old_state = ascs_ep_get_state(&ase->ep); const enum bt_bap_ep_state new_state = ase->state_pending; + const enum bt_bap_ep_state old_state = ase->ep.state; int err; - ase->ep.status.state = new_state; + ase->ep.state = new_state; /* Notify ASE state */ if (ase->conn != NULL) { @@ -533,7 +528,7 @@ static void state_transition_work_handler(struct k_work *work) uint32_t retry_delay_ms; /* Revert back to old state */ - ase->ep.status.state = old_state; + ase->ep.state = old_state; err = bt_conn_get_info(ase->conn, &info); __ASSERT_NO_MSG(err == 0); @@ -543,8 +538,9 @@ static void state_transition_work_handler(struct k_work *work) /* Reschedule the state transition */ err = k_work_reschedule(d_work, K_MSEC(retry_delay_ms)); if (err >= 0) { - LOG_WRN("Out of buffers for ase state notification. " - "Will retry in %dms", retry_delay_ms); + LOG_DBG("Out of buffers for ase state notification. " + "Will retry in %dms", + retry_delay_ms); return; } } @@ -554,7 +550,7 @@ static void state_transition_work_handler(struct k_work *work) } } - LOG_DBG("ase %p ep %p id 0x%02x %s -> %s", ase, &ase->ep, ase->ep.status.id, + LOG_DBG("ase %p ep %p id 0x%02x %s -> %s", ase, &ase->ep, ASE_ID(ase), bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(new_state)); if (old_state == new_state) { @@ -608,10 +604,10 @@ static void state_transition_work_handler(struct k_work *work) } } -int ascs_ep_set_state(struct bt_bap_ep *ep, uint8_t state) +int ascs_ep_set_state(struct bt_bap_ep *ep, enum bt_bap_ep_state state) { struct bt_ascs_ase *ase = CONTAINER_OF(ep, struct bt_ascs_ase, ep); - const enum bt_bap_ep_state old_state = ascs_ep_get_state(&ase->ep); + const enum bt_bap_ep_state old_state = ep->state; bool valid_state_transition = false; int err; @@ -637,15 +633,15 @@ int ascs_ep_set_state(struct bt_bap_ep *ep, uint8_t state) valid_state_transition = true; break; case BT_BAP_EP_STATE_DISABLING: - valid_state_transition = ase->ep.dir == BT_AUDIO_DIR_SOURCE; + valid_state_transition = ep->dir == BT_AUDIO_DIR_SOURCE; break; case BT_BAP_EP_STATE_ENABLING: case BT_BAP_EP_STATE_STREAMING: /* Source ASE transition Streaming->QoS configured is valid on case of CIS * link-loss. */ - valid_state_transition = ase->ep.dir == BT_AUDIO_DIR_SINK || - ase->unexpected_iso_link_loss; + valid_state_transition = + ep->dir == BT_AUDIO_DIR_SINK || ase->unexpected_iso_link_loss; break; default: break; @@ -672,7 +668,7 @@ int ascs_ep_set_state(struct bt_bap_ep *ep, uint8_t state) switch (old_state) { case BT_BAP_EP_STATE_ENABLING: case BT_BAP_EP_STATE_STREAMING: - valid_state_transition = ase->ep.dir == BT_AUDIO_DIR_SOURCE; + valid_state_transition = ep->dir == BT_AUDIO_DIR_SOURCE; break; default: break; @@ -686,7 +682,7 @@ int ascs_ep_set_state(struct bt_bap_ep *ep, uint8_t state) valid_state_transition = true; break; case BT_BAP_EP_STATE_DISABLING: - valid_state_transition = ase->ep.dir == BT_AUDIO_DIR_SOURCE; + valid_state_transition = ep->dir == BT_AUDIO_DIR_SOURCE; break; default: break; @@ -799,15 +795,15 @@ static int ascs_ep_get_status(struct bt_bap_ep *ep, struct net_buf_simple *buf) return -EINVAL; } - LOG_DBG("ep %p id 0x%02x state %s", ep, ep->status.id, - bt_bap_ep_state_str(ep->status.state)); + LOG_DBG("ep %p id 0x%02x state %s", ep, ep->id, bt_bap_ep_state_str(ep->state)); /* Reset if buffer before using */ net_buf_simple_reset(buf); - (void)net_buf_simple_add_mem(buf, &ep->status, sizeof(ep->status)); + (void)net_buf_simple_add_u8(buf, ep->id); + (void)net_buf_simple_add_u8(buf, ep->state); - switch (ep->status.state) { + switch (ep->state) { case BT_BAP_EP_STATE_IDLE: /* Fallthrough */ case BT_BAP_EP_STATE_RELEASING: @@ -848,7 +844,7 @@ static int ascs_iso_accept(const struct bt_iso_accept_info *info, struct bt_iso_ continue; } - state = ascs_ep_get_state(&ase->ep); + state = ase->ep.state; if (state != BT_BAP_EP_STATE_ENABLING && state != BT_BAP_EP_STATE_QOS_CONFIGURED) { LOG_WRN("ase %p cannot accept ISO connection", ase); break; @@ -900,10 +896,10 @@ static void ascs_iso_recv(struct bt_iso_chan *chan, return; } - if (ep->status.state != BT_BAP_EP_STATE_STREAMING) { + if (ep->state != BT_BAP_EP_STATE_STREAMING) { if (IS_ENABLED(CONFIG_BT_BAP_DEBUG_STREAM_DATA)) { LOG_DBG("ep %p is not in the streaming state: %s", ep, - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(ep->state)); } return; @@ -984,9 +980,8 @@ static void ascs_ep_iso_connected(struct bt_bap_ep *ep) const struct bt_bap_stream_ops *stream_ops; struct bt_bap_stream *stream; - if (ep->status.state != BT_BAP_EP_STATE_ENABLING) { - LOG_DBG("ep %p not in enabling state: %s", ep, - bt_bap_ep_state_str(ep->status.state)); + if (ep->state != BT_BAP_EP_STATE_ENABLING) { + LOG_DBG("ep %p not in enabling state: %s", ep, bt_bap_ep_state_str(ep->state)); return; } @@ -1058,7 +1053,7 @@ static void ascs_ep_iso_disconnected(struct bt_bap_ep *ep, uint8_t reason) } LOG_DBG("stream %p ep %p state %s reason 0x%02x", stream, stream->ep, - bt_bap_ep_state_str(ep->status.state), reason); + bt_bap_ep_state_str(ep->state), reason); stream_ops = stream->ops; if (stream_ops != NULL && stream_ops->disconnected != NULL) { @@ -1069,10 +1064,10 @@ static void ascs_ep_iso_disconnected(struct bt_bap_ep *ep, uint8_t reason) (void)k_work_cancel_delayable(&ase->disconnect_work); ep->reason = reason; - if (ep->status.state == BT_BAP_EP_STATE_RELEASING) { + if (ep->state == BT_BAP_EP_STATE_RELEASING) { ascs_ep_set_state(ep, BT_BAP_EP_STATE_IDLE); - } else if (ep->status.state == BT_BAP_EP_STATE_STREAMING || - ep->status.state == BT_BAP_EP_STATE_DISABLING) { + } else if (ep->state == BT_BAP_EP_STATE_STREAMING || + ep->state == BT_BAP_EP_STATE_DISABLING) { /* ASCS_v1.0 3.2 ASE state machine transitions * * If the server detects link loss of a CIS for an ASE in the Streaming @@ -1082,6 +1077,8 @@ static void ascs_ep_iso_disconnected(struct bt_bap_ep *ep, uint8_t reason) ase->unexpected_iso_link_loss = true; ascs_ep_set_state(ep, BT_BAP_EP_STATE_QOS_CONFIGURED); + } else { + /* no op */ } } @@ -1179,7 +1176,7 @@ static void ascs_cp_rsp_success(uint8_t id) static int ase_release(struct bt_ascs_ase *ase, uint8_t reason, struct bt_bap_ascs_rsp *rsp) { - enum bt_bap_ep_state state = ascs_ep_get_state(&ase->ep); + enum bt_bap_ep_state state = ase->ep.state; int err; if (state == BT_BAP_EP_STATE_IDLE || state == BT_BAP_EP_STATE_RELEASING) { @@ -1218,7 +1215,7 @@ static int ase_release(struct bt_ascs_ase *ase, uint8_t reason, struct bt_bap_as int bt_ascs_release_ase(struct bt_bap_ep *ep) { struct bt_ascs_ase *ase = CONTAINER_OF(ep, struct bt_ascs_ase, ep); - const enum bt_bap_ep_state state = ascs_ep_get_state(&ase->ep); + const enum bt_bap_ep_state state = ep->state; if (state == BT_BAP_EP_STATE_IDLE) { ase_free(ase); @@ -1238,14 +1235,14 @@ static int ase_disable(struct bt_ascs_ase *ase, uint8_t reason, struct bt_bap_as ep = &ase->ep; - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x03 (Enabling) */ case BT_BAP_EP_STATE_ENABLING: /* or 0x04 (Streaming) */ case BT_BAP_EP_STATE_STREAMING: break; default: - LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->state)); *rsp = BT_BAP_ASCS_RSP(BT_BAP_ASCS_RSP_CODE_INVALID_ASE_STATE, BT_BAP_ASCS_REASON_NONE); return -EBADMSG; @@ -1301,7 +1298,7 @@ static void disconnected(struct bt_conn *conn, uint8_t reason) continue; } - if (ase->ep.status.state != BT_BAP_EP_STATE_IDLE) { + if (ase->ep.state != BT_BAP_EP_STATE_IDLE) { /* We must set the state to idle when the ACL is disconnected immediately, * as when the ACL disconnect callbacks have been called, the application * should expect there to be only a single reference to the bt_conn pointer @@ -1377,7 +1374,7 @@ static uint8_t ase_attr_cb(const struct bt_gatt_attr *attr, uint16_t handle, { struct bt_ascs_ase *ase = user_data; - if (ase->ep.status.id == POINTER_TO_UINT(BT_AUDIO_CHRC_USER_DATA(attr))) { + if (ASE_ID(ase) == POINTER_TO_UINT(BT_AUDIO_CHRC_USER_DATA(attr))) { ase->attr = attr; return BT_GATT_ITER_STOP; @@ -1391,7 +1388,7 @@ void ascs_ep_init(struct bt_bap_ep *ep, uint8_t id) LOG_DBG("ep %p id 0x%02x", ep, id); (void)memset(ep, 0, sizeof(*ep)); - ep->status.id = id; + ep->id = id; ep->dir = ASE_DIR(id); ep->reason = BT_HCI_ERR_SUCCESS; } @@ -1442,7 +1439,7 @@ static struct bt_ascs_ase *ase_find(struct bt_conn *conn, uint8_t id) for (size_t i = 0; i < ARRAY_SIZE(ascs.ase_pool); i++) { struct bt_ascs_ase *ase = &ascs.ase_pool[i]; - if (ase->conn == conn && ase->ep.status.id == id) { + if (ase->conn == conn && ASE_ID(ase) == id) { return ase; } } @@ -1450,6 +1447,11 @@ static struct bt_ascs_ase *ase_find(struct bt_conn *conn, uint8_t id) return NULL; } +bool bt_ascs_is_ase_ep(const struct bt_bap_ep *ep) +{ + return PART_OF_ARRAY(ascs.ase_pool, ep); +} + static ssize_t ascs_ase_read(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) @@ -1573,7 +1575,7 @@ static int ase_config(struct bt_ascs_ase *ase, const struct bt_ascs_config *cfg) return -ENOMEM; } - switch (ase->ep.status.state) { + switch (ase->ep.state) { /* Valid only if ASE_State field = 0x00 (Idle) */ case BT_BAP_EP_STATE_IDLE: /* or 0x01 (Codec Configured) */ @@ -1582,8 +1584,7 @@ static int ase_config(struct bt_ascs_ase *ase, const struct bt_ascs_config *cfg) case BT_BAP_EP_STATE_QOS_CONFIGURED: break; default: - LOG_WRN("Invalid operation in state: %s", - bt_bap_ep_state_str(ase->ep.status.state)); + LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ase->ep.state)); ascs_cp_rsp_add(ASE_ID(ase), BT_BAP_ASCS_RSP_CODE_INVALID_ASE_STATE, BT_BAP_ASCS_REASON_NONE); return -EINVAL; @@ -1923,14 +1924,14 @@ static void ase_qos(struct bt_ascs_ase *ase, uint8_t cig_id, uint8_t cis_id, "latency %u pd %u", ase, cig_id, cis_id, qos->interval, qos->framing, qos->phy, qos->sdu, qos->rtn, qos->latency, qos->pd); - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x01 (Codec Configured) */ case BT_BAP_EP_STATE_CODEC_CONFIGURED: /* or 0x02 (QoS Configured) */ case BT_BAP_EP_STATE_QOS_CONFIGURED: break; default: - LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->state)); *rsp = BT_BAP_ASCS_RSP(BT_BAP_ASCS_RSP_CODE_INVALID_ASE_STATE, BT_BAP_ASCS_REASON_NONE); return; @@ -2266,13 +2267,13 @@ static void ase_metadata(struct bt_ascs_ase *ase, struct bt_ascs_metadata *meta) struct bt_bap_ep *ep; struct bt_bap_ascs_rsp rsp = BT_BAP_ASCS_RSP(BT_BAP_ASCS_RSP_CODE_SUCCESS, BT_BAP_ASCS_REASON_NONE); - uint8_t state; + enum bt_bap_ep_state state; int err; LOG_DBG("ase %p meta->len %u", ase, meta->len); ep = &ase->ep; - state = ep->status.state; + state = ep->state; switch (state) { /* Valid for an ASE only if ASE_State field = 0x03 (Enabling) */ @@ -2319,7 +2320,7 @@ static void ase_metadata(struct bt_ascs_ase *ase, struct bt_ascs_metadata *meta) (void)memcpy(ep->codec_cfg.meta, meta->data, meta->len); /* Set the state to the same state to trigger the notifications */ - ascs_ep_set_state(ep, ep->status.state); + ascs_ep_set_state(ep, ep->state); ascs_cp_rsp_success(ASE_ID(ase)); } @@ -2336,9 +2337,9 @@ static int ase_enable(struct bt_ascs_ase *ase, struct bt_ascs_metadata *meta) ep = &ase->ep; /* Valid for an ASE only if ASE_State field = 0x02 (QoS Configured) */ - if (ep->status.state != BT_BAP_EP_STATE_QOS_CONFIGURED) { + if (ep->state != BT_BAP_EP_STATE_QOS_CONFIGURED) { err = -EBADMSG; - LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->state)); ascs_cp_rsp_add(ASE_ID(ase), BT_BAP_ASCS_RSP_CODE_INVALID_ASE_STATE, BT_BAP_ASCS_REASON_NONE); return err; @@ -2479,8 +2480,8 @@ static void ase_start(struct bt_ascs_ase *ase) ep = &ase->ep; /* Valid for an ASE only if ASE_State field = 0x02 (QoS Configured) */ - if (ep->status.state != BT_BAP_EP_STATE_ENABLING) { - LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->status.state)); + if (ep->state != BT_BAP_EP_STATE_ENABLING) { + LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->state)); ascs_cp_rsp_add(ASE_ID(ase), BT_BAP_ASCS_RSP_CODE_INVALID_ASE_STATE, BT_BAP_ASCS_REASON_NONE); return; @@ -2690,8 +2691,8 @@ static void ase_stop(struct bt_ascs_ase *ase) ep = &ase->ep; - if (ep->status.state != BT_BAP_EP_STATE_DISABLING) { - LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->status.state)); + if (ep->state != BT_BAP_EP_STATE_DISABLING) { + LOG_WRN("Invalid operation in state: %s", bt_bap_ep_state_str(ep->state)); ascs_cp_rsp_add(ASE_ID(ase), BT_BAP_ASCS_RSP_CODE_INVALID_ASE_STATE, BT_BAP_ASCS_REASON_NONE); return; @@ -3236,9 +3237,9 @@ int bt_ascs_unregister(void) } for (size_t i = 0; i < ARRAY_SIZE(ascs.ase_pool); i++) { - if (ascs.ase_pool[i].ep.status.state != BT_BAP_EP_STATE_IDLE) { + if (ascs.ase_pool[i].ep.state != BT_BAP_EP_STATE_IDLE) { LOG_DBG("[%zu] ase %p not in idle state: %s", i, &ascs.ase_pool[i].ep, - bt_bap_ep_state_str(ascs.ase_pool[i].ep.status.state)); + bt_bap_ep_state_str(ascs.ase_pool[i].ep.state)); return -EBUSY; } } diff --git a/subsys/bluetooth/audio/ascs_internal.h b/subsys/bluetooth/audio/ascs_internal.h index 7ab415a5ca527..431b2cc915b32 100644 --- a/subsys/bluetooth/audio/ascs_internal.h +++ b/subsys/bluetooth/audio/ascs_internal.h @@ -11,6 +11,7 @@ #ifndef BT_ASCS_INTERNAL_H #define BT_ASCS_INTERNAL_H +#include #include #include @@ -350,7 +351,8 @@ static inline const char *bt_ascs_reason_str(uint8_t reason) int bt_ascs_init(const struct bt_bap_unicast_server_cb *cb); void bt_ascs_cleanup(void); -int ascs_ep_set_state(struct bt_bap_ep *ep, uint8_t state); +int ascs_ep_set_state(struct bt_bap_ep *ep, enum bt_bap_ep_state state); +bool bt_ascs_is_ase_ep(const struct bt_bap_ep *ep); int bt_ascs_config_ase(struct bt_conn *conn, struct bt_bap_stream *stream, struct bt_audio_codec_cfg *codec_cfg, diff --git a/subsys/bluetooth/audio/audio.c b/subsys/bluetooth/audio/audio.c index 75109d4fd9657..e1546c965b8a5 100644 --- a/subsys/bluetooth/audio/audio.c +++ b/subsys/bluetooth/audio/audio.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2022 Codecoup + * Copyright (c) 2025 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,6 +24,7 @@ #include #include #include +#include #include #include "audio_internal.h" @@ -146,18 +148,7 @@ uint8_t bt_audio_get_chan_count(enum bt_audio_location chan_allocation) return 1; } -#ifdef POPCOUNT - return POPCOUNT(chan_allocation); -#else - uint8_t cnt = 0U; - - while (chan_allocation != 0U) { - cnt += chan_allocation & 1U; - chan_allocation >>= 1U; - } - - return cnt; -#endif + return sys_count_bits(&chan_allocation, sizeof(chan_allocation)); } static bool valid_ltv_cb(struct bt_data *data, void *user_data) diff --git a/subsys/bluetooth/audio/bap_broadcast_sink.c b/subsys/bluetooth/audio/bap_broadcast_sink.c index 89f6e4653c7a8..82106a9dfae57 100644 --- a/subsys/bluetooth/audio/bap_broadcast_sink.c +++ b/subsys/bluetooth/audio/bap_broadcast_sink.c @@ -228,13 +228,13 @@ static struct bt_bap_broadcast_sink *broadcast_sink_lookup_iso_chan( return NULL; } -static void broadcast_sink_set_ep_state(struct bt_bap_ep *ep, uint8_t state) +static void broadcast_sink_set_ep_state(struct bt_bap_ep *ep, enum bt_bap_ep_state state) { uint8_t old_state; - old_state = ep->status.state; + old_state = ep->state; - LOG_DBG("ep %p id 0x%02x %s -> %s", ep, ep->status.id, bt_bap_ep_state_str(old_state), + LOG_DBG("ep %p id 0x%02x %s -> %s", ep, ep->id, bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(state)); switch (old_state) { @@ -262,7 +262,7 @@ static void broadcast_sink_set_ep_state(struct bt_bap_ep *ep, uint8_t state) return; } - ep->status.state = state; + ep->state = state; if (state == BT_BAP_EP_STATE_IDLE) { struct bt_bap_stream *stream = ep->stream; @@ -337,7 +337,7 @@ static bool broadcast_sink_is_in_state(struct bt_bap_broadcast_sink *sink, } SYS_SLIST_FOR_EACH_CONTAINER(&sink->streams, stream, _node) { - if (stream->ep != NULL && stream->ep->status.state != state) { + if (stream->ep != NULL && stream->ep->state != state) { return false; } } @@ -1096,22 +1096,6 @@ int bt_bap_broadcast_sink_create(struct bt_le_per_adv_sync *pa_sync, uint32_t br return 0; } -static uint8_t bit_count(uint32_t bitfield) -{ -#ifdef POPCOUNT - return POPCOUNT(bitfield); -#else - uint8_t cnt = 0U; - - while (bitfield != 0U) { - cnt += bitfield & 1U; - bitfield >>= 1U; - } - - return cnt; -#endif -} - struct sync_base_info_data { struct bt_audio_codec_cfg codec_cfgs[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]; struct bt_audio_codec_cfg *subgroup_codec_cfg; @@ -1296,7 +1280,7 @@ int bt_bap_broadcast_sink_sync(struct bt_bap_broadcast_sink *sink, uint32_t inde } /* Validate that number of bits set is within supported range */ - bis_count = bit_count(indexes_bitfield); + bis_count = sys_count_bits(&indexes_bitfield, sizeof(indexes_bitfield)); if (bis_count > CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT) { LOG_DBG("Cannot sync to more than %d streams (%u was requested)", CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT, bis_count); diff --git a/subsys/bluetooth/audio/bap_broadcast_source.c b/subsys/bluetooth/audio/bap_broadcast_source.c index dec695ddc24a4..51b239728613d 100644 --- a/subsys/bluetooth/audio/bap_broadcast_source.c +++ b/subsys/bluetooth/audio/bap_broadcast_source.c @@ -85,9 +85,9 @@ static void broadcast_source_set_ep_state(struct bt_bap_ep *ep, uint8_t state) { uint8_t old_state; - old_state = ep->status.state; + old_state = ep->state; - LOG_DBG("ep %p id 0x%02x %s -> %s", ep, ep->status.id, bt_bap_ep_state_str(old_state), + LOG_DBG("ep %p id 0x%02x %s -> %s", ep, ep->id, bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(state)); switch (old_state) { @@ -121,7 +121,7 @@ static void broadcast_source_set_ep_state(struct bt_bap_ep *ep, uint8_t state) return; } - ep->status.state = state; + ep->state = state; } static void broadcast_source_set_state(struct bt_bap_broadcast_source *source, uint8_t state) @@ -617,7 +617,7 @@ static enum bt_bap_ep_state broadcast_source_get_state(struct bt_bap_broadcast_s SYS_SLIST_FOR_EACH_CONTAINER(&subgroup->streams, stream, _node) { if (stream->ep != NULL) { - state = MAX(state, stream->ep->status.state); + state = MAX(state, stream->ep->state); } } } diff --git a/subsys/bluetooth/audio/bap_endpoint.h b/subsys/bluetooth/audio/bap_endpoint.h index 4f1a5fe7a0b09..2cb54bf9f5a39 100644 --- a/subsys/bluetooth/audio/bap_endpoint.h +++ b/subsys/bluetooth/audio/bap_endpoint.h @@ -43,10 +43,11 @@ struct bt_bap_broadcast_source; struct bt_bap_broadcast_sink; struct bt_bap_ep { - uint8_t dir; - uint8_t cig_id; - uint8_t cis_id; - struct bt_ascs_ase_status status; + uint8_t dir; + uint8_t cig_id; + uint8_t cis_id; + uint8_t id; + enum bt_bap_ep_state state; struct bt_bap_stream *stream; struct bt_audio_codec_cfg codec_cfg; struct bt_bap_qos_cfg qos; @@ -94,6 +95,11 @@ struct bt_bap_unicast_group { /* The ISO API for CIG creation requires an array of pointers to ISO channels */ struct bt_iso_chan *cis[UNICAST_GROUP_STREAM_CNT]; sys_slist_t streams; + + /* Configured sink presentation delay */ + uint32_t sink_pd; + /* Configured source presentation delay */ + uint32_t source_pd; }; #if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 @@ -194,7 +200,7 @@ struct bt_bap_broadcast_sink { }; #endif /* CONFIG_BT_BAP_BROADCAST_SINK */ -static inline const char *bt_bap_ep_state_str(uint8_t state) +static inline const char *bt_bap_ep_state_str(enum bt_bap_ep_state state) { switch (state) { case BT_BAP_EP_STATE_IDLE: diff --git a/subsys/bluetooth/audio/bap_stream.c b/subsys/bluetooth/audio/bap_stream.c index f06baebecac15..99439a1582306 100644 --- a/subsys/bluetooth/audio/bap_stream.c +++ b/subsys/bluetooth/audio/bap_stream.c @@ -126,8 +126,8 @@ int bt_bap_ep_get_info(const struct bt_bap_ep *ep, struct bt_bap_ep_info *info) dir = ep->dir; - info->id = ep->status.id; - info->state = ep->status.state; + info->id = ep->id; + info->state = ep->state; info->dir = dir; info->qos_pref = &ep->qos_pref; @@ -298,14 +298,13 @@ bool bt_bap_valid_qos_pref(const struct bt_bap_qos_cfg_pref *qos_pref) return false; } - if (qos_pref->pref_pd_min != BT_AUDIO_PD_PREF_NONE) { /* If pref_pd_min != BT_AUDIO_PD_PREF_NONE then pd_min <= pref_pd_min <= pd_max */ - if (!IN_RANGE(qos_pref->pref_pd_min, qos_pref->pd_min, qos_pref->pd_max)) { - LOG_DBG("Invalid combination of pref_pd_min %u, pd_min %u and pd_max: %u", - qos_pref->pref_pd_min, qos_pref->pd_min, qos_pref->pd_max); + if (qos_pref->pref_pd_min != BT_AUDIO_PD_PREF_NONE && + !IN_RANGE(qos_pref->pref_pd_min, qos_pref->pd_min, qos_pref->pd_max)) { + LOG_DBG("Invalid combination of pref_pd_min %u, pd_min %u and pd_max: %u", + qos_pref->pref_pd_min, qos_pref->pd_min, qos_pref->pd_max); - return false; - } + return false; } if (qos_pref->pref_pd_max != BT_AUDIO_PD_PREF_NONE) { @@ -380,9 +379,9 @@ static int bap_stream_send(struct bt_bap_stream *stream, struct net_buf *buf, ui ep = stream->ep; - if (ep->status.state != BT_BAP_EP_STATE_STREAMING) { + if (ep->state != BT_BAP_EP_STATE_STREAMING) { LOG_DBG("Channel %p not ready for streaming (state: %s)", stream, - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(ep->state)); return -EBADMSG; } @@ -486,8 +485,8 @@ bool bt_bap_stream_can_disconnect(const struct bt_bap_stream *stream) /* If there are no paired endpoint, or the paired endpoint is in the QoS Configured * or Codec Configured state, we can disconnect the CIS */ - if (pair_ep == NULL || pair_ep->status.state == BT_BAP_EP_STATE_QOS_CONFIGURED || - pair_ep->status.state == BT_BAP_EP_STATE_CODEC_CONFIGURED) { + if (pair_ep == NULL || pair_ep->state == BT_BAP_EP_STATE_QOS_CONFIGURED || + pair_ep->state == BT_BAP_EP_STATE_CODEC_CONFIGURED) { return true; } } @@ -619,7 +618,7 @@ int bt_bap_stream_config(struct bt_conn *conn, struct bt_bap_stream *stream, str return -EINVAL; } - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x00 (Idle) */ case BT_BAP_EP_STATE_IDLE: /* or 0x01 (Codec Configured) */ @@ -628,7 +627,7 @@ int bt_bap_stream_config(struct bt_conn *conn, struct bt_bap_stream *stream, str case BT_BAP_EP_STATE_QOS_CONFIGURED: break; default: - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EBADMSG; } @@ -699,8 +698,8 @@ int bt_bap_stream_enable(struct bt_bap_stream *stream, const uint8_t meta[], siz } /* Valid for an ASE only if ASE_State field = 0x02 (QoS Configured) */ - if (stream->ep->status.state != BT_BAP_EP_STATE_QOS_CONFIGURED) { - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(stream->ep->status.state)); + if (stream->ep->state != BT_BAP_EP_STATE_QOS_CONFIGURED) { + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(stream->ep->state)); return -EBADMSG; } @@ -732,12 +731,12 @@ int bt_bap_stream_stop(struct bt_bap_stream *stream) ep = stream->ep; - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x03 (Disabling) */ case BT_BAP_EP_STATE_DISABLING: break; default: - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EBADMSG; } @@ -754,7 +753,7 @@ int bt_bap_stream_stop(struct bt_bap_stream *stream) int bt_bap_stream_reconfig(struct bt_bap_stream *stream, struct bt_audio_codec_cfg *codec_cfg) { - uint8_t state; + enum bt_bap_ep_state state; uint8_t role; int err; @@ -770,7 +769,7 @@ int bt_bap_stream_reconfig(struct bt_bap_stream *stream, return -EINVAL; } - state = stream->ep->status.state; + state = stream->ep->state; switch (state) { /* Valid only if ASE_State field = 0x00 (Idle) */ case BT_BAP_EP_STATE_IDLE: @@ -805,7 +804,7 @@ int bt_bap_stream_reconfig(struct bt_bap_stream *stream, #if defined(CONFIG_BT_BAP_UNICAST_CLIENT) int bt_bap_stream_connect(struct bt_bap_stream *stream) { - uint8_t state; + enum bt_bap_ep_state state; LOG_DBG("stream %p ep %p", stream, stream == NULL ? NULL : stream->ep); @@ -817,7 +816,7 @@ int bt_bap_stream_connect(struct bt_bap_stream *stream) /* Valid only after the CIS ID has been assigned in QoS configured state and while we are * not streaming */ - state = stream->ep->status.state; + state = stream->ep->state; switch (state) { case BT_BAP_EP_STATE_QOS_CONFIGURED: case BT_BAP_EP_STATE_ENABLING: @@ -838,7 +837,7 @@ int bt_bap_stream_connect(struct bt_bap_stream *stream) int bt_bap_stream_start(struct bt_bap_stream *stream) { - uint8_t state; + enum bt_bap_ep_state state; uint8_t role; int err; @@ -849,7 +848,7 @@ int bt_bap_stream_start(struct bt_bap_stream *stream) return -EINVAL; } - state = stream->ep->status.state; + state = stream->ep->state; switch (state) { /* Valid only if ASE_State field = 0x03 (Enabling) */ case BT_BAP_EP_STATE_ENABLING: @@ -878,7 +877,7 @@ int bt_bap_stream_start(struct bt_bap_stream *stream) int bt_bap_stream_metadata(struct bt_bap_stream *stream, const uint8_t meta[], size_t meta_len) { - uint8_t state; + enum bt_bap_ep_state state; uint8_t role; int err; @@ -894,7 +893,7 @@ int bt_bap_stream_metadata(struct bt_bap_stream *stream, const uint8_t meta[], s return -EINVAL; } - state = stream->ep->status.state; + state = stream->ep->state; switch (state) { /* Valid for an ASE only if ASE_State field = 0x03 (Enabling) */ case BT_BAP_EP_STATE_ENABLING: @@ -925,7 +924,7 @@ int bt_bap_stream_metadata(struct bt_bap_stream *stream, const uint8_t meta[], s int bt_bap_stream_disable(struct bt_bap_stream *stream) { - uint8_t state; + enum bt_bap_ep_state state; uint8_t role; int err; @@ -936,7 +935,7 @@ int bt_bap_stream_disable(struct bt_bap_stream *stream) return -EINVAL; } - state = stream->ep->status.state; + state = stream->ep->state; switch (state) { /* Valid only if ASE_State field = 0x03 (Enabling) */ case BT_BAP_EP_STATE_ENABLING: @@ -967,7 +966,7 @@ int bt_bap_stream_disable(struct bt_bap_stream *stream) int bt_bap_stream_release(struct bt_bap_stream *stream) { - uint8_t state; + enum bt_bap_ep_state state; uint8_t role; int err; @@ -978,7 +977,7 @@ int bt_bap_stream_release(struct bt_bap_stream *stream) return -EINVAL; } - state = stream->ep->status.state; + state = stream->ep->state; switch (state) { /* Valid only if ASE_State field = 0x01 (Codec Configured) */ case BT_BAP_EP_STATE_CODEC_CONFIGURED: diff --git a/subsys/bluetooth/audio/bap_unicast_client.c b/subsys/bluetooth/audio/bap_unicast_client.c index 75666a289efae..48c43f9faa8b8 100644 --- a/subsys/bluetooth/audio/bap_unicast_client.c +++ b/subsys/bluetooth/audio/bap_unicast_client.c @@ -147,8 +147,7 @@ static int unicast_client_ep_set_metadata(struct bt_bap_ep *ep, void *data, uint static int unicast_client_ep_set_codec_cfg(struct bt_bap_ep *ep, uint8_t id, uint16_t cid, uint16_t vid, void *data, uint8_t len, struct bt_audio_codec_cfg *codec_cfg); -static int unicast_client_ep_start(struct bt_bap_ep *ep, - struct net_buf_simple *buf); +static int unicast_client_ep_start(struct bt_bap_ep *ep, struct net_buf_simple *buf); static int unicast_client_ase_discover(struct bt_conn *conn, uint16_t start_handle); @@ -160,8 +159,7 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si static int unicast_client_send_start(struct bt_bap_ep *ep) { if (ep->receiver_ready != true || ep->dir != BT_AUDIO_DIR_SOURCE) { - LOG_DBG("Invalid ep %p %u %s", - ep, ep->receiver_ready, bt_audio_dir_str(ep->dir)); + LOG_DBG("Invalid ep %p %u %s", ep, ep->receiver_ready, bt_audio_dir_str(ep->dir)); return -EINVAL; } @@ -181,8 +179,7 @@ static int unicast_client_send_start(struct bt_bap_ep *ep) err = unicast_client_ep_start(ep, buf); if (err != 0) { - LOG_DBG("unicast_client_ep_start failed: %d", - err); + LOG_DBG("unicast_client_ep_start failed: %d", err); return err; } @@ -199,8 +196,7 @@ static int unicast_client_send_start(struct bt_bap_ep *ep) static void unicast_client_ep_idle_state(struct bt_bap_ep *ep); -static struct bt_bap_stream *audio_stream_by_ep_id(const struct bt_conn *conn, - uint8_t id) +static struct bt_bap_stream *audio_stream_by_ep_id(const struct bt_conn *conn, uint8_t id) { #if CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT > 0 || CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT > 0 const uint8_t conn_index = bt_conn_index(conn); @@ -213,7 +209,7 @@ static struct bt_bap_stream *audio_stream_by_ep_id(const struct bt_conn *conn, const struct bt_bap_unicast_client_ep *client_ep = &uni_cli_insts[conn_index].snks[i]; - if (client_ep->ep.status.id == id) { + if (client_ep->ep.id == id) { return client_ep->ep.stream; } } @@ -224,7 +220,7 @@ static struct bt_bap_stream *audio_stream_by_ep_id(const struct bt_conn *conn, const struct bt_bap_unicast_client_ep *client_ep = &uni_cli_insts[conn_index].srcs[i]; - if (client_ep->ep.status.id == id) { + if (client_ep->ep.id == id) { return client_ep->ep.stream; } } @@ -265,10 +261,10 @@ static void unicast_client_ep_iso_recv(struct bt_iso_chan *chan, return; } - if (ep->status.state != BT_BAP_EP_STATE_STREAMING) { + if (ep->state != BT_BAP_EP_STATE_STREAMING) { if (IS_ENABLED(CONFIG_BT_BAP_DEBUG_STREAM_DATA)) { LOG_DBG("ep %p is not in the streaming state: %s", ep, - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(ep->state)); } return; @@ -331,9 +327,8 @@ static void unicast_client_ep_iso_connected(struct bt_bap_ep *ep) ep->unicast_group->has_been_connected = true; } - if (ep->status.state != BT_BAP_EP_STATE_ENABLING) { - LOG_DBG("endpoint not in enabling state: %s", - bt_bap_ep_state_str(ep->status.state)); + if (ep->state != BT_BAP_EP_STATE_ENABLING) { + LOG_DBG("endpoint not in enabling state: %s", bt_bap_ep_state_str(ep->state)); return; } @@ -343,8 +338,8 @@ static void unicast_client_ep_iso_connected(struct bt_bap_ep *ep) return; } - LOG_DBG("stream %p ep %p dir %s receiver_ready %u", - stream, ep, bt_audio_dir_str(ep->dir), ep->receiver_ready); + LOG_DBG("stream %p ep %p dir %s receiver_ready %u", stream, ep, bt_audio_dir_str(ep->dir), + ep->receiver_ready); #if defined(CONFIG_BT_BAP_DEBUG_STREAM_SEQ_NUM) /* reset sequence number */ @@ -398,7 +393,7 @@ static void unicast_client_ep_iso_disconnected(struct bt_bap_ep *ep, uint8_t rea * then we need to call unicast_client_ep_idle_state again when * the ISO has finalized the disconnection */ - if (ep->status.state == BT_BAP_EP_STATE_IDLE) { + if (ep->state == BT_BAP_EP_STATE_IDLE) { unicast_client_ep_idle_state(ep); @@ -475,7 +470,7 @@ static void unicast_client_ep_init(struct bt_bap_ep *ep, uint16_t handle, uint8_ (void)memset(ep, 0, sizeof(*ep)); client_ep->handle = handle; - ep->status.id = 0U; + ep->id = 0U; ep->dir = dir; ep->reason = BT_HCI_ERR_SUCCESS; k_work_init_delayable(&client_ep->ase_read_work, delayed_ase_read_handler); @@ -580,7 +575,7 @@ static struct bt_bap_ep *unicast_client_ep_get(struct bt_conn *conn, enum bt_aud static void unicast_client_ep_set_local_idle_state(struct bt_bap_ep *ep) { struct bt_ascs_ase_status status = { - .id = ep->status.id, + .id = ep->id, .state = BT_BAP_EP_STATE_IDLE, }; struct net_buf_simple buf; @@ -852,6 +847,36 @@ static void unicast_client_ep_qos_update(struct bt_bap_ep *ep, iso_io_qos->rtn = qos->rtn; } +static void check_and_reset_group_pd(struct bt_bap_unicast_group *group, enum bt_audio_dir dir) +{ + bool dir_in_idle_or_config_state = true; + struct bt_bap_stream *stream; + + SYS_SLIST_FOR_EACH_CONTAINER(&group->streams, stream, _node) { + if (stream->ep == NULL || stream->ep->dir != dir) { + continue; + } + + if (stream->ep->state == BT_BAP_EP_STATE_IDLE || + stream->ep->state == BT_BAP_EP_STATE_CODEC_CONFIGURED) { + continue; + } else { + dir_in_idle_or_config_state = false; + break; + } + } + + if (dir_in_idle_or_config_state) { + if (dir == BT_AUDIO_DIR_SINK) { + group->sink_pd = BT_BAP_PD_UNSET; + } else if (dir == BT_AUDIO_DIR_SOURCE) { + group->source_pd = BT_BAP_PD_UNSET; + } else { + __ASSERT(false, "Invalid dir %d", dir); + } + } +} + static void unicast_client_ep_config_state(struct bt_bap_ep *ep, struct net_buf_simple *buf) { struct bt_bap_unicast_client_ep *client_ep = @@ -932,6 +957,14 @@ static void unicast_client_ep_config_state(struct bt_bap_ep *ep, struct net_buf_ unicast_client_ep_set_codec_cfg(ep, cfg->codec.id, sys_le16_to_cpu(cfg->codec.cid), sys_le16_to_cpu(cfg->codec.vid), cc, cfg->cc_len, NULL); + /* Every time a stream enters the codec configured state, there is a chance that all streams + * in that direction has exited the QoS configured state, and we need to update the stored + * presentation delay + */ + if (stream->group != NULL) { + check_and_reset_group_pd((struct bt_bap_unicast_group *)stream->group, ep->dir); + } + /* Notify upper layer */ if (stream->ops != NULL && stream->ops->configured != NULL) { stream->ops->configured(stream, pref); @@ -943,8 +976,10 @@ static void unicast_client_ep_config_state(struct bt_bap_ep *ep, struct net_buf_ static void unicast_client_ep_qos_state(struct bt_bap_ep *ep, struct net_buf_simple *buf, uint8_t old_state) { + const enum bt_audio_dir dir = ep->dir; const struct bt_bap_stream_ops *ops; struct bt_ascs_ase_status_qos *qos; + struct bt_bap_unicast_group *group; struct bt_bap_stream *stream; ep->receiver_ready = false; @@ -1009,10 +1044,36 @@ static void unicast_client_ep_qos_state(struct bt_bap_ep *ep, struct net_buf_sim LOG_DBG("dir %s cig 0x%02x cis 0x%02x codec 0x%02x interval %u " "framing 0x%02x phy 0x%02x rtn %u latency %u pd %u", - bt_audio_dir_str(ep->dir), ep->cig_id, ep->cis_id, stream->codec_cfg->id, + bt_audio_dir_str(dir), ep->cig_id, ep->cis_id, stream->codec_cfg->id, stream->qos->interval, stream->qos->framing, stream->qos->phy, stream->qos->rtn, stream->qos->latency, stream->qos->pd); + __ASSERT_NO_MSG(stream->group != NULL); + group = (struct bt_bap_unicast_group *)stream->group; + if (dir == BT_AUDIO_DIR_SINK) { + if (group->sink_pd == BT_BAP_PD_UNSET) { + group->sink_pd = stream->qos->pd; + } else { + if (group->sink_pd != stream->qos->pd) { + LOG_WRN("Sink stream %p PD %u does not match the sink PD %u of the " + "group %p", + stream, stream->qos->pd, group->sink_pd, group); + } + } + } else if (dir == BT_AUDIO_DIR_SOURCE) { + if (group->source_pd == BT_BAP_PD_UNSET) { + group->source_pd = stream->qos->pd; + } else { + if (group->source_pd != stream->qos->pd) { + LOG_WRN("Source stream %p PD %u does not match the source PD %u of " + "the group %p", + stream, stream->qos->pd, group->source_pd, group); + } + } + } else { + __ASSERT(false, "Invalid dir %d", dir); + } + /* Disconnect ISO if connected */ if (bt_bap_stream_can_disconnect(stream)) { const int err = bt_bap_stream_disconnect(stream); @@ -1200,9 +1261,10 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si status = net_buf_simple_pull_mem(buf, sizeof(*status)); - old_state = ep->status.state; - ep->status = *status; - state_changed = old_state != ep->status.state; + old_state = ep->state; + ep->id = status->id; + ep->state = status->state; + state_changed = old_state != ep->state; if (state_changed && old_state == BT_BAP_EP_STATE_STREAMING) { /* We left the streaming state, let the upper layers know that the stream is stopped @@ -1257,8 +1319,7 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si break; default: LOG_WRN("Invalid state transition: %s -> %s", - bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(ep->state)); return; } @@ -1280,7 +1341,7 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si default: LOG_WRN("Invalid state transition: %s -> %s", bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(ep->state)); return; } } else { @@ -1297,7 +1358,7 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si default: LOG_WRN("Invalid state transition: %s -> %s", bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(ep->state)); return; } } @@ -1313,8 +1374,7 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si break; default: LOG_WRN("Invalid state transition: %s -> %s", - bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(ep->state)); return; } @@ -1329,8 +1389,7 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si break; default: LOG_WRN("Invalid state transition: %s -> %s", - bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(ep->state)); return; } @@ -1347,14 +1406,13 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si default: LOG_WRN("Invalid state transition: %s -> %s", bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(ep->state)); return; } } else { /* Sinks cannot go into the disabling state */ LOG_WRN("Invalid state transition: %s -> %s", - bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(ep->state)); return; } @@ -1380,8 +1438,7 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si /* fall through */ default: LOG_WRN("Invalid state transition: %s -> %s", - bt_bap_ep_state_str(old_state), - bt_bap_ep_state_str(ep->status.state)); + bt_bap_ep_state_str(old_state), bt_bap_ep_state_str(ep->state)); return; } @@ -1561,10 +1618,10 @@ static uint8_t unicast_client_cp_notify(struct bt_conn *conn, ase_rsp = net_buf_simple_pull_mem(&buf, sizeof(*ase_rsp)); LOG_DBG("op %s (0x%02x) id 0x%02x code %s (0x%02x) " - "reason %s (0x%02x)", bt_ascs_op_str(rsp->op), rsp->op, - ase_rsp->id, bt_ascs_rsp_str(ase_rsp->code), - ase_rsp->code, bt_ascs_reason_str(ase_rsp->reason), - ase_rsp->reason); + "reason %s (0x%02x)", + bt_ascs_op_str(rsp->op), rsp->op, ase_rsp->id, + bt_ascs_rsp_str(ase_rsp->code), ase_rsp->code, + bt_ascs_reason_str(ase_rsp->reason), ase_rsp->reason); stream = audio_stream_by_ep_id(conn, ase_rsp->id); if (stream == NULL) { @@ -1919,7 +1976,7 @@ static int unicast_client_ep_config(struct bt_bap_ep *ep, struct net_buf_simple return -EINVAL; } - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x00 (Idle) */ case BT_BAP_EP_STATE_IDLE: /* or 0x01 (Codec Configured) */ @@ -1928,15 +1985,14 @@ static int unicast_client_ep_config(struct bt_bap_ep *ep, struct net_buf_simple case BT_BAP_EP_STATE_QOS_CONFIGURED: break; default: - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } - LOG_DBG("id 0x%02x dir %s codec 0x%02x", ep->status.id, bt_audio_dir_str(ep->dir), - codec_cfg->id); + LOG_DBG("id 0x%02x dir %s codec 0x%02x", ep->id, bt_audio_dir_str(ep->dir), codec_cfg->id); req = net_buf_simple_add(buf, sizeof(*req)); - req->ase = ep->status.id; + req->ase = ep->id; req->latency = codec_cfg->target_latency; req->phy = codec_cfg->target_phy; req->codec.id = codec_cfg->id; @@ -1963,14 +2019,14 @@ int bt_bap_unicast_client_ep_qos(struct bt_bap_ep *ep, struct net_buf_simple *bu return -EINVAL; } - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x01 (Codec Configured) */ case BT_BAP_EP_STATE_CODEC_CONFIGURED: /* or 0x02 (QoS Configured) */ case BT_BAP_EP_STATE_QOS_CONFIGURED: break; default: - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } @@ -1978,11 +2034,11 @@ int bt_bap_unicast_client_ep_qos(struct bt_bap_ep *ep, struct net_buf_simple *bu LOG_DBG("id 0x%02x cig 0x%02x cis 0x%02x interval %u framing 0x%02x " "phy 0x%02x sdu %u rtn %u latency %u pd %u", - ep->status.id, conn_iso->info.unicast.cig_id, conn_iso->info.unicast.cis_id, - qos->interval, qos->framing, qos->phy, qos->sdu, qos->rtn, qos->latency, qos->pd); + ep->id, conn_iso->info.unicast.cig_id, conn_iso->info.unicast.cis_id, qos->interval, + qos->framing, qos->phy, qos->sdu, qos->rtn, qos->latency, qos->pd); req = net_buf_simple_add(buf, sizeof(*req)); - req->ase = ep->status.id; + req->ase = ep->id; /* TODO: don't hardcode CIG and CIS, they should come from ISO */ req->cig = conn_iso->info.unicast.cig_id; req->cis = conn_iso->info.unicast.cis_id; @@ -2008,15 +2064,15 @@ static int unicast_client_ep_enable(struct bt_bap_ep *ep, struct net_buf_simple return -EINVAL; } - if (ep->status.state != BT_BAP_EP_STATE_QOS_CONFIGURED) { - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + if (ep->state != BT_BAP_EP_STATE_QOS_CONFIGURED) { + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } - LOG_DBG("id 0x%02x", ep->status.id); + LOG_DBG("id 0x%02x", ep->id); req = net_buf_simple_add(buf, sizeof(*req)); - req->ase = ep->status.id; + req->ase = ep->id; req->len = meta_len; net_buf_simple_add_mem(buf, meta, meta_len); @@ -2035,21 +2091,21 @@ static int unicast_client_ep_metadata(struct bt_bap_ep *ep, struct net_buf_simpl return -EINVAL; } - switch (ep->status.state) { + switch (ep->state) { /* Valid for an ASE only if ASE_State field = 0x03 (Enabling) */ case BT_BAP_EP_STATE_ENABLING: /* or 0x04 (Streaming) */ case BT_BAP_EP_STATE_STREAMING: break; default: - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } - LOG_DBG("id 0x%02x", ep->status.id); + LOG_DBG("id 0x%02x", ep->id); req = net_buf_simple_add(buf, sizeof(*req)); - req->ase = ep->status.id; + req->ase = ep->id; req->len = meta_len; net_buf_simple_add_mem(buf, meta, meta_len); @@ -2065,15 +2121,14 @@ static int unicast_client_ep_start(struct bt_bap_ep *ep, struct net_buf_simple * return -EINVAL; } - if (ep->status.state != BT_BAP_EP_STATE_ENABLING && - ep->status.state != BT_BAP_EP_STATE_DISABLING) { - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + if (ep->state != BT_BAP_EP_STATE_ENABLING && ep->state != BT_BAP_EP_STATE_DISABLING) { + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } - LOG_DBG("id 0x%02x", ep->status.id); + LOG_DBG("id 0x%02x", ep->id); - net_buf_simple_add_u8(buf, ep->status.id); + net_buf_simple_add_u8(buf, ep->id); return 0; } @@ -2086,20 +2141,20 @@ static int unicast_client_ep_disable(struct bt_bap_ep *ep, struct net_buf_simple return -EINVAL; } - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x03 (Enabling) */ case BT_BAP_EP_STATE_ENABLING: /* or 0x04 (Streaming) */ case BT_BAP_EP_STATE_STREAMING: break; default: - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } - LOG_DBG("id 0x%02x", ep->status.id); + LOG_DBG("id 0x%02x", ep->id); - net_buf_simple_add_u8(buf, ep->status.id); + net_buf_simple_add_u8(buf, ep->id); return 0; } @@ -2113,14 +2168,14 @@ static int unicast_client_ep_stop(struct bt_bap_ep *ep, struct net_buf_simple *b } /* Valid only if ASE_State field value = 0x05 (Disabling). */ - if (ep->status.state != BT_BAP_EP_STATE_DISABLING) { - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + if (ep->state != BT_BAP_EP_STATE_DISABLING) { + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } - LOG_DBG("id 0x%02x", ep->status.id); + LOG_DBG("id 0x%02x", ep->id); - net_buf_simple_add_u8(buf, ep->status.id); + net_buf_simple_add_u8(buf, ep->id); return 0; } @@ -2133,7 +2188,7 @@ static int unicast_client_ep_release(struct bt_bap_ep *ep, struct net_buf_simple return -EINVAL; } - switch (ep->status.state) { + switch (ep->state) { /* Valid only if ASE_State field = 0x01 (Codec Configured) */ case BT_BAP_EP_STATE_CODEC_CONFIGURED: /* or 0x02 (QoS Configured) */ @@ -2146,13 +2201,13 @@ static int unicast_client_ep_release(struct bt_bap_ep *ep, struct net_buf_simple case BT_BAP_EP_STATE_DISABLING: break; default: - LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->status.state)); + LOG_ERR("Invalid state: %s", bt_bap_ep_state_str(ep->state)); return -EINVAL; } - LOG_DBG("id 0x%02x", ep->status.id); + LOG_DBG("id 0x%02x", ep->id); - net_buf_simple_add_u8(buf, ep->status.id); + net_buf_simple_add_u8(buf, ep->id); return 0; } @@ -2278,7 +2333,7 @@ static void unicast_client_ep_reset(struct bt_conn *conn, uint8_t reason) } static void bt_bap_qos_cfg_to_cig_param(struct bt_iso_cig_param *cig_param, - const struct bt_bap_unicast_group *group) + const struct bt_bap_unicast_group *group) { cig_param->framing = group->cig_param.framing; cig_param->c_to_p_interval = group->cig_param.c_to_p_interval; @@ -2380,8 +2435,7 @@ static int bt_audio_cig_reconfigure(struct bt_bap_unicast_group *group) return 0; } -static void audio_stream_qos_cleanup(const struct bt_conn *conn, - struct bt_bap_unicast_group *group) +static void audio_stream_qos_cleanup(const struct bt_conn *conn, struct bt_bap_unicast_group *group) { struct bt_bap_stream *stream; @@ -2500,8 +2554,7 @@ static void unicast_client_qos_cfg_to_iso_qos(struct bt_bap_iso *iso, } static void unicast_group_set_iso_stream_param(struct bt_bap_unicast_group *group, - struct bt_bap_iso *iso, - struct bt_bap_qos_cfg *qos, + struct bt_bap_iso *iso, struct bt_bap_qos_cfg *qos, enum bt_audio_dir dir) { /* Store the stream Codec QoS in the bap_iso */ @@ -2632,6 +2685,8 @@ static struct bt_bap_unicast_group *unicast_group_alloc(void) group->allocated = true; group->index = i; + group->sink_pd = BT_BAP_PD_UNSET; + group->source_pd = BT_BAP_PD_UNSET; break; } @@ -2673,14 +2728,12 @@ static void unicast_group_free(struct bt_bap_unicast_group *group) static int stream_param_check(const struct bt_bap_unicast_group_stream_param *param) { - CHECKIF(param->stream == NULL) - { + CHECKIF(param->stream == NULL) { LOG_DBG("param->stream is NULL"); return -EINVAL; } - CHECKIF(param->qos == NULL) - { + CHECKIF(param->qos == NULL) { LOG_DBG("param->qos is NULL"); return -EINVAL; } @@ -2690,8 +2743,7 @@ static int stream_param_check(const struct bt_bap_unicast_group_stream_param *pa return -EALREADY; } - CHECKIF(bt_audio_verify_qos(param->qos) != BT_BAP_ASCS_REASON_NONE) - { + CHECKIF(bt_audio_verify_qos(param->qos) != BT_BAP_ASCS_REASON_NONE) { LOG_DBG("Invalid QoS"); return -EINVAL; } @@ -2703,8 +2755,7 @@ static int stream_pair_param_check(const struct bt_bap_unicast_group_stream_pair { int err; - CHECKIF(param->rx_param == NULL && param->tx_param == NULL) - { + CHECKIF(param->rx_param == NULL && param->tx_param == NULL) { LOG_DBG("Invalid stream parameters"); return -EINVAL; } @@ -2875,13 +2926,12 @@ static bool valid_unicast_group_param(struct bt_bap_unicast_group *unicast_group } int bt_bap_unicast_group_create(struct bt_bap_unicast_group_param *param, - struct bt_bap_unicast_group **out_unicast_group) + struct bt_bap_unicast_group **out_unicast_group) { struct bt_bap_unicast_group *unicast_group; int err; - CHECKIF(out_unicast_group == NULL) - { + CHECKIF(out_unicast_group == NULL) { LOG_DBG("out_unicast_group is NULL"); return -EINVAL; } @@ -3030,8 +3080,8 @@ int bt_bap_unicast_group_reconfig(struct bt_bap_unicast_group *unicast_group, } int bt_bap_unicast_group_add_streams(struct bt_bap_unicast_group *unicast_group, - struct bt_bap_unicast_group_stream_pair_param params[], - size_t num_param) + struct bt_bap_unicast_group_stream_pair_param params[], + size_t num_param) { struct bt_bap_stream *tmp_stream; size_t total_stream_cnt; @@ -3039,8 +3089,7 @@ int bt_bap_unicast_group_add_streams(struct bt_bap_unicast_group *unicast_group, size_t num_added; int err; - CHECKIF(unicast_group == NULL) - { + CHECKIF(unicast_group == NULL) { LOG_DBG("unicast_group is NULL"); return -EINVAL; } @@ -3050,14 +3099,12 @@ int bt_bap_unicast_group_add_streams(struct bt_bap_unicast_group *unicast_group, return -EINVAL; } - CHECKIF(params == NULL) - { + CHECKIF(params == NULL) { LOG_DBG("params is NULL"); return -EINVAL; } - CHECKIF(num_param == 0) - { + CHECKIF(num_param == 0) { LOG_DBG("num_param is 0"); return -EINVAL; } @@ -3126,8 +3173,7 @@ int bt_bap_unicast_group_delete(struct bt_bap_unicast_group *unicast_group) { struct bt_bap_stream *stream; - CHECKIF(unicast_group == NULL) - { + CHECKIF(unicast_group == NULL) { LOG_DBG("unicast_group is NULL"); return -EINVAL; } @@ -3184,6 +3230,25 @@ int bt_bap_unicast_group_foreach_stream(struct bt_bap_unicast_group *unicast_gro return 0; } +int bt_bap_unicast_group_get_info(const struct bt_bap_unicast_group *unicast_group, + struct bt_bap_unicast_group_info *info) +{ + if (unicast_group == NULL) { + LOG_DBG("unicast_group is NULL"); + return -EINVAL; + } + + if (info == NULL) { + LOG_DBG("info is NULL"); + return -EINVAL; + } + + info->sink_pd = unicast_group->sink_pd; + info->source_pd = unicast_group->source_pd; + + return 0; +} + int bt_bap_unicast_client_config(struct bt_bap_stream *stream, const struct bt_audio_codec_cfg *codec_cfg) { @@ -3224,11 +3289,15 @@ int bt_bap_unicast_client_config(struct bt_bap_stream *stream, int bt_bap_unicast_client_qos(struct bt_conn *conn, struct bt_bap_unicast_group *group) { + bool source_qos_configured_on_other_conn; + bool sink_qos_configured_on_other_conn; struct bt_bap_stream *stream; struct bt_ascs_config_op *op; struct net_buf_simple *buf; struct bt_bap_ep *ep; bool conn_stream_found; + uint32_t source_pd; + uint32_t sink_pd; int err; if (conn == NULL) { @@ -3237,18 +3306,60 @@ int bt_bap_unicast_client_qos(struct bt_conn *conn, struct bt_bap_unicast_group return -ENOTCONN; } + if (group == NULL) { + LOG_DBG("group is NULL"); + + return -EINVAL; + } + + /* Validate streams before starting the QoS execution */ + source_qos_configured_on_other_conn = false; + sink_qos_configured_on_other_conn = false; + /* Used to determine if a stream for the supplied connection pointer * was actually found */ conn_stream_found = false; + SYS_SLIST_FOR_EACH_CONTAINER(&group->streams, stream, _node) { + enum bt_audio_dir dir; + + if (stream->conn == conn) { + conn_stream_found = true; + continue; + } + + if (stream->ep == NULL) { + /* Only consider configured streams */ + continue; + } + + ep = stream->ep; + dir = ep->dir; + + if (ep->state >= BT_BAP_EP_STATE_QOS_CONFIGURED) { + if (dir == BT_AUDIO_DIR_SINK) { + sink_qos_configured_on_other_conn = true; + } else if (dir == BT_AUDIO_DIR_SOURCE) { + source_qos_configured_on_other_conn = true; + } else { + __ASSERT(false, "Invalid dir %d", dir); + } + } + } + + if (!conn_stream_found) { + LOG_DBG("No streams in the group %p for conn %p", group, conn); + return -EINVAL; + } + + source_pd = group->source_pd; + sink_pd = group->sink_pd; - /* Validate streams before starting the QoS execution */ SYS_SLIST_FOR_EACH_CONTAINER(&group->streams, stream, _node) { if (stream->conn != conn) { /* Channel not part of this ACL, skip */ continue; } - conn_stream_found = true; ep = stream->ep; if (ep == NULL) { @@ -3259,12 +3370,12 @@ int bt_bap_unicast_client_qos(struct bt_conn *conn, struct bt_bap_unicast_group /* Can only be done if all the streams are in the codec * configured state or the QoS configured state */ - switch (ep->status.state) { + switch (ep->state) { case BT_BAP_EP_STATE_CODEC_CONFIGURED: case BT_BAP_EP_STATE_QOS_CONFIGURED: break; default: - LOG_DBG("Invalid state: %s", bt_bap_ep_state_str(stream->ep->status.state)); + LOG_DBG("Invalid state: %s", bt_bap_ep_state_str(stream->ep->state)); return -EINVAL; } @@ -3272,10 +3383,43 @@ int bt_bap_unicast_client_qos(struct bt_conn *conn, struct bt_bap_unicast_group return -EINVAL; } - /* Verify ep->dir */ + /* Verify ep->dir and presentation delay. If the group already has a configured + * presentation delay in a direction, we compare the stream's presentation delay + * with the group's presentation delay, and if they differ we reject the request. + * As per the BAP spec section 7.1, all streams in a direction shall have the same + * presentation delay. The group presentation delay is set once any endpoint in a + * direction has changed state to "QoS configured" or "above", and cleared again if + * all endpoints for that direction enters the codec configured or idle state. + * The check for presentation delay is also conditional on whether other devices are + * involved - If there is only a single connection that has ASEs in a QoS Configured + * state or "above", then we can freely modify the presentation delay. + */ switch (ep->dir) { case BT_AUDIO_DIR_SINK: + if (sink_pd == BT_BAP_PD_UNSET) { + sink_pd = stream->qos->pd; + } else { + if (sink_qos_configured_on_other_conn && + sink_pd != stream->qos->pd) { + LOG_DBG("Sink stream %p did not have the same PD %u as " + "other sink streams %u", + stream, stream->qos->pd, sink_pd); + return -EINVAL; + } + } + break; case BT_AUDIO_DIR_SOURCE: + if (source_pd == BT_BAP_PD_UNSET) { + source_pd = stream->qos->pd; + } else { + if (source_qos_configured_on_other_conn && + source_pd != stream->qos->pd) { + LOG_DBG("Source stream %p did not have the same PD %u as " + "other source streams %u", + stream, stream->qos->pd, source_pd); + return -EINVAL; + } + } break; default: __ASSERT(false, "invalid endpoint dir: %u", ep->dir); @@ -3291,11 +3435,6 @@ int bt_bap_unicast_client_qos(struct bt_conn *conn, struct bt_bap_unicast_group } } - if (!conn_stream_found) { - LOG_DBG("No streams in the group %p for conn %p", group, conn); - return -EINVAL; - } - /* Generate the control point write */ buf = bt_bap_unicast_client_ep_create_pdu(conn, BT_ASCS_QOS_OP); if (buf == NULL) { @@ -3606,7 +3745,7 @@ int bt_bap_unicast_client_release(struct bt_bap_stream *stream) len = buf->len; /* Only attempt to release if not IDLE already */ - if (stream->ep->status.state == BT_BAP_EP_STATE_IDLE) { + if (stream->ep->state == BT_BAP_EP_STATE_IDLE) { bt_bap_stream_reset(stream); } else { err = unicast_client_ep_release(ep, buf); @@ -3776,8 +3915,7 @@ static bool any_ases_found(const struct unicast_client *client) return true; } -static uint8_t unicast_client_ase_discover_cb(struct bt_conn *conn, - const struct bt_gatt_attr *attr, +static uint8_t unicast_client_ase_discover_cb(struct bt_conn *conn, const struct bt_gatt_attr *attr, struct bt_gatt_discover_params *discover) { struct unicast_client *client; @@ -4357,38 +4495,36 @@ static uint8_t unicast_client_read_func(struct bt_conn *conn, uint8_t err, LOG_DBG("pac #%u/%u", i + 1, rsp->num_pac); if (buf->len < sizeof(*pac_codec)) { - LOG_ERR("Malformed PAC: remaining len %u expected %zu", - buf->len, sizeof(*pac_codec)); + LOG_ERR("Malformed PAC: remaining len %u expected %zu", buf->len, + sizeof(*pac_codec)); break; } pac_codec = net_buf_simple_pull_mem(buf, sizeof(*pac_codec)); if (buf->len < sizeof(*cc)) { - LOG_ERR("Malformed PAC: remaining len %u expected %zu", - buf->len, sizeof(*cc)); + LOG_ERR("Malformed PAC: remaining len %u expected %zu", buf->len, + sizeof(*cc)); break; } cc = net_buf_simple_pull_mem(buf, sizeof(*cc)); if (buf->len < cc->len) { - LOG_ERR("Malformed PAC: remaining len %u expected %zu", - buf->len, cc->len); + LOG_ERR("Malformed PAC: remaining len %u expected %zu", buf->len, cc->len); break; } cc_ltv = net_buf_simple_pull_mem(buf, cc->len); if (buf->len < sizeof(*meta)) { - LOG_ERR("Malformed PAC: remaining len %u expected %zu", - buf->len, sizeof(*meta)); + LOG_ERR("Malformed PAC: remaining len %u expected %zu", buf->len, + sizeof(*meta)); break; } meta = net_buf_simple_pull_mem(buf, sizeof(*meta)); if (buf->len < meta->len) { - LOG_ERR("Malformed PAC: remaining len %u expected %u", - buf->len, meta->len); + LOG_ERR("Malformed PAC: remaining len %u expected %u", buf->len, meta->len); break; } @@ -4429,8 +4565,7 @@ static uint8_t unicast_client_read_func(struct bt_conn *conn, uint8_t err, return BT_GATT_ITER_STOP; } -static uint8_t unicast_client_pac_discover_cb(struct bt_conn *conn, - const struct bt_gatt_attr *attr, +static uint8_t unicast_client_pac_discover_cb(struct bt_conn *conn, const struct bt_gatt_attr *attr, struct bt_gatt_discover_params *discover) { struct unicast_client *client = &uni_cli_insts[bt_conn_index(conn)]; diff --git a/subsys/bluetooth/audio/bap_unicast_server.c b/subsys/bluetooth/audio/bap_unicast_server.c index bc83137b0a3fd..9195a60238002 100644 --- a/subsys/bluetooth/audio/bap_unicast_server.c +++ b/subsys/bluetooth/audio/bap_unicast_server.c @@ -106,6 +106,11 @@ int bt_bap_unicast_server_reconfig(struct bt_bap_stream *stream, ep = stream->ep; + if (!bt_ascs_is_ase_ep(ep)) { + LOG_DBG("ep %p not in ASCS", ep); + return -EINVAL; + } + if (unicast_server_cb != NULL && unicast_server_cb->reconfig != NULL) { err = unicast_server_cb->reconfig(stream, ep->dir, codec_cfg, &ep->qos_pref, &rsp); @@ -126,6 +131,11 @@ int bt_bap_unicast_server_start(struct bt_bap_stream *stream) { struct bt_bap_ep *ep = stream->ep; + if (!bt_ascs_is_ase_ep(ep)) { + LOG_DBG("ep %p not in ASCS", ep); + return -EINVAL; + } + if (ep->dir != BT_AUDIO_DIR_SINK) { LOG_DBG("Invalid operation for stream %p with dir %u", stream, ep->dir); @@ -153,6 +163,12 @@ int bt_bap_unicast_server_metadata(struct bt_bap_stream *stream, const uint8_t m BT_BAP_ASCS_REASON_NONE); int err; + ep = stream->ep; + if (!bt_ascs_is_ase_ep(ep)) { + LOG_DBG("ep %p not in ASCS", ep); + return -EINVAL; + } + if (meta_len > sizeof(ep->codec_cfg.meta)) { return -ENOMEM; } @@ -169,20 +185,29 @@ int bt_bap_unicast_server_metadata(struct bt_bap_stream *stream, const uint8_t m return err; } - ep = stream->ep; (void)memcpy(ep->codec_cfg.meta, meta, meta_len); /* Set the state to the same state to trigger the notifications */ - return ascs_ep_set_state(ep, ep->status.state); + return ascs_ep_set_state(ep, ep->state); } int bt_bap_unicast_server_disable(struct bt_bap_stream *stream) { + if (!bt_ascs_is_ase_ep(stream->ep)) { + LOG_DBG("ep %p not in ASCS", stream->ep); + return -EINVAL; + } + return bt_ascs_disable_ase(stream->ep); } int bt_bap_unicast_server_release(struct bt_bap_stream *stream) { + if (!bt_ascs_is_ase_ep(stream->ep)) { + LOG_DBG("ep %p not in ASCS", stream->ep); + return -EINVAL; + } + return bt_ascs_release_ase(stream->ep); } diff --git a/subsys/bluetooth/audio/cap_handover.c b/subsys/bluetooth/audio/cap_handover.c index 61a395b61a6bb..8e985c83096bd 100644 --- a/subsys/bluetooth/audio/cap_handover.c +++ b/subsys/bluetooth/audio/cap_handover.c @@ -191,7 +191,7 @@ void bt_cap_handover_unicast_to_broadcast_reception_start(void) } member_param->addr = bt_addr_le_any; - member_param->adv_sid = proc_param->unicast_to_broadcast.sid; + member_param->adv_sid = adv_info.sid; member_param->pa_interval = proc_param->unicast_to_broadcast.pa_interval; member_param->broadcast_id = proc_param->unicast_to_broadcast.broadcast_id; bt_addr_le_copy(&member_param->addr, adv_info.addr); @@ -632,7 +632,6 @@ int bt_cap_handover_unicast_to_broadcast( proc_param->unicast_to_broadcast.unicast_group = param->unicast_group; proc_param->unicast_to_broadcast.ext_adv = param->ext_adv; proc_param->unicast_to_broadcast.type = param->type; - proc_param->unicast_to_broadcast.sid = param->sid; proc_param->unicast_to_broadcast.pa_interval = param->pa_interval; proc_param->unicast_to_broadcast.broadcast_id = param->broadcast_id; diff --git a/subsys/bluetooth/audio/cap_initiator.c b/subsys/bluetooth/audio/cap_initiator.c index f56f8b29687c1..8720c1bf87d82 100644 --- a/subsys/bluetooth/audio/cap_initiator.c +++ b/subsys/bluetooth/audio/cap_initiator.c @@ -443,6 +443,46 @@ int bt_cap_initiator_broadcast_get_base(struct bt_cap_broadcast_source *broadcas return bt_bap_broadcast_source_get_base(broadcast_source->bap_broadcast, base_buf); } +struct cap_broadcast_source_foreach_stream_data { + bt_cap_initiator_broadcast_foreach_stream_func_t func; + void *user_data; +}; + +static bool cap_broadcast_source_foreach_stream_cb(struct bt_bap_stream *bap_stream, + void *user_data) +{ + struct cap_broadcast_source_foreach_stream_data *data = user_data; + + /* Since we are iterating on a CAP broadcast source, we can assume that all streams are CAP + * streams + */ + return data->func(CONTAINER_OF(bap_stream, struct bt_cap_stream, bap_stream), + data->user_data); +} + +int bt_cap_initiator_broadcast_foreach_stream(struct bt_cap_broadcast_source *broadcast_source, + bt_cap_initiator_broadcast_foreach_stream_func_t func, + void *user_data) +{ + struct cap_broadcast_source_foreach_stream_data data = { + .func = func, + .user_data = user_data, + }; + + if (broadcast_source == NULL) { + LOG_DBG("source is NULL"); + return -EINVAL; + } + + if (func == NULL) { + LOG_DBG("func is NULL"); + return -EINVAL; + } + + return bt_bap_broadcast_source_foreach_stream( + broadcast_source->bap_broadcast, cap_broadcast_source_foreach_stream_cb, &data); +} + #endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ #if defined(CONFIG_BT_BAP_UNICAST_CLIENT) @@ -1071,6 +1111,24 @@ int bt_cap_unicast_group_foreach_stream(struct bt_cap_unicast_group *unicast_gro bap_unicast_group_foreach_stream_cb, &data); } +int bt_cap_unicast_group_get_info(const struct bt_cap_unicast_group *unicast_group, + struct bt_cap_unicast_group_info *info) +{ + if (unicast_group == NULL) { + LOG_DBG("unicast_group is NULL"); + return -EINVAL; + } + + if (info == NULL) { + LOG_DBG("info is NULL"); + return -EINVAL; + } + + info->unicast_group = unicast_group->bap_unicast_group; + + return 0; +} + static bool valid_unicast_audio_start_param(const struct bt_cap_unicast_audio_start_param *param) { struct bt_bap_unicast_group *unicast_group = NULL; diff --git a/subsys/bluetooth/audio/cap_internal.h b/subsys/bluetooth/audio/cap_internal.h index 4ce4d34ff037c..19dbe3eab40f4 100644 --- a/subsys/bluetooth/audio/cap_internal.h +++ b/subsys/bluetooth/audio/cap_internal.h @@ -190,8 +190,6 @@ struct bt_cap_handover_proc_param { /* Set type */ enum bt_cap_set_type type; - /* The SID of the ext_adv */ - uint8_t sid; /* The PA interval of the ext_adv */ uint16_t pa_interval; /* The broadcast ID the broadcast source will use */ diff --git a/subsys/bluetooth/audio/ccp_call_control_server.c b/subsys/bluetooth/audio/ccp_call_control_server.c index c1f955743ba87..053a83ed6bfff 100644 --- a/subsys/bluetooth/audio/ccp_call_control_server.c +++ b/subsys/bluetooth/audio/ccp_call_control_server.c @@ -9,17 +9,20 @@ #include #include #include +#include #include #include #include #include #include +#include LOG_MODULE_REGISTER(bt_ccp_call_control_server, CONFIG_BT_CCP_CALL_CONTROL_SERVER_LOG_LEVEL); /* A service instance can either be a GTBS or a TBS instance */ struct bt_ccp_call_control_server_bearer { + char provider_name[CONFIG_BT_CCP_CALL_CONTROL_SERVER_PROVIDER_NAME_MAX_LENGTH + 1]; uint8_t tbs_index; bool registered; }; @@ -70,6 +73,8 @@ int bt_ccp_call_control_server_register_bearer(const struct bt_tbs_register_para free_bearer->registered = true; free_bearer->tbs_index = (uint8_t)ret; + (void)utf8_lcpy(free_bearer->provider_name, param->provider_name, + sizeof(free_bearer->provider_name)); *bearer = free_bearer; return 0; @@ -105,3 +110,68 @@ int bt_ccp_call_control_server_unregister_bearer(struct bt_ccp_call_control_serv return 0; } + +int bt_ccp_call_control_server_set_bearer_provider_name( + struct bt_ccp_call_control_server_bearer *bearer, const char *name) +{ + size_t len; + + CHECKIF(bearer == NULL) { + LOG_DBG("bearer is NULL"); + + return -EINVAL; + } + + CHECKIF(name == NULL) { + LOG_DBG("name is NULL"); + + return -EINVAL; + } + + if (!bearer->registered) { + LOG_DBG("Bearer %p not registered", bearer); + + return -EFAULT; + } + + len = strlen(name); + if (len > CONFIG_BT_CCP_CALL_CONTROL_SERVER_PROVIDER_NAME_MAX_LENGTH || len == 0) { + LOG_DBG("Invalid name length: %zu", len); + + return -EINVAL; + } + + if (strcmp(bearer->provider_name, name) == 0) { + return 0; + } + + (void)utf8_lcpy(bearer->provider_name, name, sizeof(bearer->provider_name)); + + return bt_tbs_set_bearer_provider_name(bearer->tbs_index, name); +} + +int bt_ccp_call_control_server_get_bearer_provider_name( + struct bt_ccp_call_control_server_bearer *bearer, const char **name) +{ + CHECKIF(bearer == NULL) { + LOG_DBG("bearer is NULL"); + + return -EINVAL; + } + + CHECKIF(name == NULL) { + LOG_DBG("name is NULL"); + + return -EINVAL; + } + + if (!bearer->registered) { + LOG_DBG("Bearer %p not registered", bearer); + + return -EFAULT; + } + + *name = bearer->provider_name; + + return 0; +} diff --git a/subsys/bluetooth/audio/csip_set_member.c b/subsys/bluetooth/audio/csip_set_member.c index 7bbd2bc2f107f..cfeb6ac6e45fb 100644 --- a/subsys/bluetooth/audio/csip_set_member.c +++ b/subsys/bluetooth/audio/csip_set_member.c @@ -1009,6 +1009,7 @@ int bt_csip_set_member_register(const struct bt_csip_set_member_register_param * int bt_csip_set_member_unregister(struct bt_csip_set_member_svc_inst *svc_inst) { + const struct bt_gatt_attr csis_definition[] = BT_CSIP_SERVICE_DEFINITION(svc_inst); int err; CHECKIF(svc_inst == NULL) { @@ -1034,14 +1035,8 @@ int bt_csip_set_member_unregister(struct bt_csip_set_member_svc_inst *svc_inst) } /* Restore original declaration */ - - /* attrs_0 is an array of the original attributes, and while the actual number of attributes - * may change, the size of the array stays the same, so we can use that to restore the - * original attribute count - */ - (void)memcpy(svc_inst->service_p->attrs, - (struct bt_gatt_attr[])BT_CSIP_SERVICE_DEFINITION(svc_inst), sizeof(attrs_0)); - svc_inst->service_p->attr_count = ARRAY_SIZE(attrs_0); + (void)memcpy(svc_inst->service_p->attrs, csis_definition, sizeof(csis_definition)); + svc_inst->service_p->attr_count = ARRAY_SIZE(csis_definition); (void)k_work_cancel_delayable(&svc_inst->set_lock_timer); diff --git a/subsys/bluetooth/audio/has.c b/subsys/bluetooth/audio/has.c index 2cdc8bbe54494..27dc53a4dac89 100644 --- a/subsys/bluetooth/audio/has.c +++ b/subsys/bluetooth/audio/has.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include diff --git a/subsys/bluetooth/audio/has_client.c b/subsys/bluetooth/audio/has_client.c index 78564c851f347..3d48a0ea7e3d2 100644 --- a/subsys/bluetooth/audio/has_client.c +++ b/subsys/bluetooth/audio/has_client.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "has_internal.h" diff --git a/subsys/bluetooth/audio/has_internal.h b/subsys/bluetooth/audio/has_internal.h index 97b4d2017aefa..8560a93ff7603 100644 --- a/subsys/bluetooth/audio/has_internal.h +++ b/subsys/bluetooth/audio/has_internal.h @@ -68,7 +68,7 @@ struct bt_has { struct bt_has_cp_hdr { uint8_t opcode; - uint8_t data[0]; + uint8_t data[]; } __packed; struct bt_has_cp_read_presets_req { @@ -80,25 +80,25 @@ struct bt_has_cp_read_preset_rsp { uint8_t is_last; uint8_t index; uint8_t properties; - uint8_t name[0]; + uint8_t name[]; } __packed; struct bt_has_cp_preset_changed { uint8_t change_id; uint8_t is_last; - uint8_t additional_params[0]; + uint8_t additional_params[]; } __packed; struct bt_has_cp_generic_update { uint8_t prev_index; uint8_t index; uint8_t properties; - uint8_t name[0]; + uint8_t name[]; } __packed; struct bt_has_cp_write_preset_name { uint8_t index; - uint8_t name[0]; + uint8_t name[]; } __packed; struct bt_has_cp_set_active_preset { diff --git a/subsys/bluetooth/audio/pacs_internal.h b/subsys/bluetooth/audio/pacs_internal.h index 897f8800504da..0d6ded670dea7 100644 --- a/subsys/bluetooth/audio/pacs_internal.h +++ b/subsys/bluetooth/audio/pacs_internal.h @@ -23,12 +23,12 @@ struct bt_pac_codec { struct bt_pac_ltv { uint8_t len; uint8_t type; - uint8_t value[0]; + uint8_t value[]; } __packed; struct bt_pac_ltv_data { uint8_t len; - struct bt_pac_ltv data[0]; + struct bt_pac_ltv data[]; } __packed; struct bt_pacs_read_rsp { diff --git a/subsys/bluetooth/audio/shell/CMakeLists.txt b/subsys/bluetooth/audio/shell/CMakeLists.txt index bb71e1e65c0ae..db1641a86f893 100644 --- a/subsys/bluetooth/audio/shell/CMakeLists.txt +++ b/subsys/bluetooth/audio/shell/CMakeLists.txt @@ -89,7 +89,7 @@ zephyr_library_sources_ifdef( CONFIG_BT_BAP_STREAM bap.c ) -if (CONFIG_LIBLC3 AND CONFIG_USB_DEVICE_AUDIO) +if (CONFIG_LIBLC3 AND CONFIG_USBD_AUDIO2_CLASS) zephyr_library_sources(bap_usb.c) endif() zephyr_library_sources_ifdef( diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h index e73e10e0e8332..5cf55bc6ed707 100644 --- a/subsys/bluetooth/audio/shell/audio.h +++ b/subsys/bluetooth/audio/shell/audio.h @@ -48,8 +48,6 @@ size_t cap_acceptor_ad_data_add(struct bt_data data[], size_t data_size, bool di size_t bap_scan_delegator_ad_data_add(struct bt_data data[], size_t data_size); size_t gmap_ad_data_add(struct bt_data data[], size_t data_size); size_t pbp_ad_data_add(struct bt_data data[], size_t data_size); -size_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size, - const bool discoverable, const bool connectable); size_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size); #if defined(CONFIG_BT_AUDIO) @@ -117,13 +115,13 @@ struct shell_stream { size_t lc3_sdu_cnt; lc3_encoder_mem_48k_t lc3_encoder_mem; lc3_encoder_t lc3_encoder; -#if defined(CONFIG_USB_DEVICE_AUDIO) +#if defined(CONFIG_USBD_AUDIO2_CLASS) /* Indicates where to read left USB data in the ring buffer */ size_t left_read_idx; /* Indicates where to read right USB data in the ring buffer */ size_t right_read_idx; size_t right_ring_buf_fail_cnt; -#endif /* CONFIG_USB_DEVICE_AUDIO */ +#endif /* CONFIG_USBD_AUDIO2_CLASS */ #endif /* CONFIG_LIBLC3 */ } tx; #endif /* CONFIG_BT_AUDIO_TX */ @@ -176,6 +174,7 @@ struct broadcast_source { }; struct bt_audio_codec_cfg codec_cfg; struct bt_bap_qos_cfg qos; + uint32_t broadcast_id; }; struct broadcast_sink { diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index dcad633fcfe9a..936dcb7145617 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -57,7 +57,7 @@ #define IS_BAP_INITIATOR \ (IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SOURCE) || IS_ENABLED(CONFIG_BT_BAP_UNICAST_CLIENT)) -#define GENERATE_SINE_SUPPORTED (IS_ENABLED(CONFIG_LIBLC3) && !IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) +#define GENERATE_SINE_SUPPORTED (IS_ENABLED(CONFIG_LIBLC3) && !IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) #if defined(CONFIG_BT_BAP_UNICAST) @@ -318,7 +318,7 @@ static int init_lc3_encoder(struct shell_stream *sh_stream) return -EINVAL; } - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) { const size_t frame_size = bap_usb_get_frame_size(sh_stream); if (frame_size > sizeof(lc3_tx_buf)) { @@ -337,7 +337,7 @@ static int init_lc3_encoder(struct shell_stream *sh_stream) sh_stream->tx.lc3_encoder = lc3_setup_encoder(sh_stream->lc3_frame_duration_us, sh_stream->lc3_freq_hz, - IS_ENABLED(CONFIG_USB_DEVICE_AUDIO) ? USB_SAMPLE_RATE : 0, + IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS) ? USB_SAMPLE_RATE : 0, &sh_stream->tx.lc3_encoder_mem); if (sh_stream->tx.lc3_encoder == NULL) { bt_shell_error("Failed to setup LC3 encoder - wrong parameters?\n"); @@ -375,7 +375,7 @@ static bool encode_frame(struct shell_stream *sh_stream, uint8_t index, size_t f const uint16_t octets_per_frame = sh_stream->lc3_octets_per_frame; int lc3_ret; - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) { enum bt_audio_location chan_alloc; int err; @@ -432,7 +432,7 @@ static size_t encode_frame_block(struct shell_stream *sh_stream, size_t frame_cn static void do_lc3_encode(struct shell_stream *sh_stream, struct net_buf *out_buf) { - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO) && !bap_usb_can_get_full_sdu(sh_stream)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS) && !bap_usb_can_get_full_sdu(sh_stream)) { /* No op - Will just send empty SDU */ } else { size_t frame_cnt = 0U; @@ -2384,7 +2384,7 @@ static uint16_t interval_to_sync_timeout(uint16_t interval) return (uint16_t)timeout; } -static bool scan_check_and_sync_broadcast(struct bt_data *data, void *user_data) +static bool scan_check_and_get_broadcast_values(struct bt_data *data, void *user_data) { struct bt_broadcast_info *sr_info = (struct bt_broadcast_info *)user_data; struct bt_uuid_16 adv_uuid; @@ -2427,17 +2427,11 @@ static void broadcast_scan_recv(const struct bt_le_scan_recv_info *info, struct sr_info.broadcast_id = BT_BAP_INVALID_BROADCAST_ID; - if ((auto_scan.broadcast_info.broadcast_id == BT_BAP_INVALID_BROADCAST_ID) && - (strlen(auto_scan.broadcast_info.broadcast_name) == 0U)) { - /* no op */ - return; - } - if (!passes_scan_filter(info, ad)) { return; } - bt_data_parse(ad, scan_check_and_sync_broadcast, (void *)&sr_info); + bt_data_parse(ad, scan_check_and_get_broadcast_values, (void *)&sr_info); /* Verify that it is a BAP broadcaster*/ if (sr_info.broadcast_id == BT_BAP_INVALID_BROADCAST_ID) { @@ -2446,6 +2440,15 @@ static void broadcast_scan_recv(const struct bt_le_scan_recv_info *info, struct bt_addr_le_to_str(info->addr, addr_str, sizeof(addr_str)); + bt_shell_print("Found broadcaster with ID 0x%06X (%s) and addr %s and sid 0x%02X ", + sr_info.broadcast_id, sr_info.broadcast_name, addr_str, info->sid); + + if ((auto_scan.broadcast_info.broadcast_id == BT_BAP_INVALID_BROADCAST_ID) && + (strlen(auto_scan.broadcast_info.broadcast_name) == 0U)) { + /* no op */ + return; + } + if (sr_info.broadcast_id == auto_scan.broadcast_info.broadcast_id) { identified_broadcast = true; } else if ((strlen(auto_scan.broadcast_info.broadcast_name) != 0U) && @@ -2462,10 +2465,6 @@ static void broadcast_scan_recv(const struct bt_le_scan_recv_info *info, struct struct bt_le_per_adv_sync_param create_params = {0}; int err; - bt_shell_print( - "Found broadcaster with ID 0x%06X and addr %s and sid 0x%02X ", - sr_info.broadcast_id, addr_str, info->sid); - err = bt_le_scan_stop(); if (err != 0) { bt_shell_error("Could not stop scan: %d", err); @@ -2634,7 +2633,7 @@ static int init_lc3_decoder(struct shell_stream *sh_stream) /* Create the decoder instance. This shall complete before stream_started() is called. */ sh_stream->rx.lc3_decoder = lc3_setup_decoder(sh_stream->lc3_frame_duration_us, sh_stream->lc3_freq_hz, - IS_ENABLED(CONFIG_USB_DEVICE_AUDIO) ? USB_SAMPLE_RATE : 0, + IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS) ? USB_SAMPLE_RATE : 0, &sh_stream->rx.lc3_decoder_mem); if (sh_stream->rx.lc3_decoder == NULL) { bt_shell_error("Failed to setup LC3 decoder - wrong parameters?\n"); @@ -2695,7 +2694,7 @@ static size_t decode_frame_block(struct lc3_data *data, size_t frame_cnt) if (decode_frame(data, frame_cnt + decoded_frames)) { decoded_frames++; - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) { enum bt_audio_location chan_alloc; int err; @@ -2723,7 +2722,7 @@ static size_t decode_frame_block(struct lc3_data *data, size_t frame_cnt) /* If decoding failed, we clear the data to USB as it would contain * invalid data */ - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) { bap_usb_clear_frames_to_usb(); } @@ -3009,7 +3008,7 @@ static void stream_started_cb(struct bt_bap_stream *bap_stream) return; } - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) { /* Always mark as active when using USB */ sh_stream->tx.active = true; } @@ -3030,7 +3029,7 @@ static void stream_started_cb(struct bt_bap_stream *bap_stream) sh_stream->rx.decoded_cnt = 0U; - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) { if ((sh_stream->lc3_chan_allocation & BT_AUDIO_LOCATION_FRONT_LEFT) != 0) { if (usb_left_stream == NULL) { @@ -3149,7 +3148,7 @@ static void clear_stream_data(struct shell_stream *sh_stream) sh_stream->is_rx = sh_stream->is_tx = false; #if defined(CONFIG_LIBLC3) - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) { + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) { update_usb_streams(sh_stream); } #endif /* CONFIG_LIBLC3 */ @@ -3267,6 +3266,7 @@ static int cmd_create_broadcast(const struct shell *sh, size_t argc, struct bt_bap_broadcast_source_subgroup_param subgroup_param; struct bt_bap_broadcast_source_param create_param = {0}; const struct named_lc3_preset *named_preset; + uint32_t broadcast_id = 0U; int err; if (default_source.bap_source != NULL) { @@ -3325,6 +3325,15 @@ static int cmd_create_broadcast(const struct shell *sh, size_t argc, } } + err = bt_rand(&broadcast_id, BT_AUDIO_BROADCAST_ID_SIZE); + if (err != 0) { + bt_shell_error("Unable to generate broadcast ID: %d\n", err); + + return -ENOEXEC; + } + + shell_print(sh, "Generated broadcast_id 0x%06X", broadcast_id); + copy_broadcast_source_preset(&default_source, named_preset); (void)memset(stream_params, 0, sizeof(stream_params)); @@ -3342,11 +3351,14 @@ static int cmd_create_broadcast(const struct shell *sh, size_t argc, err = bt_bap_broadcast_source_create(&create_param, &default_source.bap_source); if (err != 0) { shell_error(sh, "Unable to create broadcast source: %d", err); + + default_source.broadcast_id = BT_BAP_INVALID_BROADCAST_ID; return err; } shell_print(sh, "Broadcast source created: preset %s", named_preset->name); + default_source.broadcast_id = broadcast_id; if (default_stream == NULL) { default_stream = bap_stream_from_shell_stream(&broadcast_source_streams[0]); @@ -3891,6 +3903,8 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[]) bt_bap_stream_cb_register( bap_stream_from_shell_stream(&broadcast_source_streams[i]), &stream_ops); } + + default_source.broadcast_id = BT_BAP_INVALID_BROADCAST_ID; #endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ #if defined(CONFIG_LIBLC3) @@ -3917,7 +3931,7 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[]) #endif /* CONFIG_BT_AUDIO_TX */ - if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO) && + if (IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS) && (IS_ENABLED(CONFIG_BT_AUDIO_RX) || IS_ENABLED(CONFIG_BT_AUDIO_TX))) { err = bap_usb_init(); __ASSERT(err == 0, "Failed to enable USB: %d", err); @@ -4315,35 +4329,18 @@ static size_t nonconnectable_ad_data_add(struct bt_data *data_array, const size_ }; size_t ad_len = 0; - if (IS_ENABLED(CONFIG_BT_CAP_ACCEPTOR)) { - static const uint8_t ad_cap_announcement[3] = { - BT_UUID_16_ENCODE(BT_UUID_CAS_VAL), - BT_AUDIO_UNICAST_ANNOUNCEMENT_TARGETED, - }; - - __ASSERT(data_array_size > ad_len, "No space for AD_CAP_ANNOUNCEMENT"); - data_array[ad_len].type = BT_DATA_SVC_DATA16; - data_array[ad_len].data_len = ARRAY_SIZE(ad_cap_announcement); - data_array[ad_len].data = &ad_cap_announcement[0]; - ad_len++; - } - #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) - if (default_source.bap_source != NULL && !default_source.is_cap) { + if (default_source.bap_source != NULL) { static uint8_t ad_bap_broadcast_announcement[5] = { BT_UUID_16_ENCODE(BT_UUID_BROADCAST_AUDIO_VAL), }; - uint32_t broadcast_id; - int err; - - err = bt_rand(&broadcast_id, BT_AUDIO_BROADCAST_ID_SIZE); - if (err != 0) { - bt_shell_error("Unable to generate broadcast ID: %d\n", err); - return 0; + if (data_array_size <= ad_len) { + bt_shell_warn("No space for BT_UUID_BROADCAST_AUDIO_VAL"); + return ad_len; } - sys_put_le24(broadcast_id, &ad_bap_broadcast_announcement[2]); + sys_put_le24(default_source.broadcast_id, &ad_bap_broadcast_announcement[2]); data_array[ad_len].type = BT_DATA_SVC_DATA16; data_array[ad_len].data_len = ARRAY_SIZE(ad_bap_broadcast_announcement); data_array[ad_len].data = ad_bap_broadcast_announcement; @@ -4381,11 +4378,6 @@ size_t audio_ad_data_add(struct bt_data *data_array, const size_t data_array_siz ad_len += nonconnectable_ad_data_add(data_array, data_array_size); } - if (IS_ENABLED(CONFIG_BT_CAP_INITIATOR)) { - ad_len += cap_initiator_ad_data_add(data_array, data_array_size, discoverable, - connectable); - } - return ad_len; } diff --git a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c index 716d2d9bc8dbc..8734805f0bcf0 100644 --- a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c +++ b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include "common/bt_shell_private.h" diff --git a/subsys/bluetooth/audio/shell/bap_usb.c b/subsys/bluetooth/audio/shell/bap_usb.c index 5199c62c77f8d..0a8bf6146a0af 100644 --- a/subsys/bluetooth/audio/shell/bap_usb.c +++ b/subsys/bluetooth/audio/shell/bap_usb.c @@ -19,17 +19,20 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include #include #include #include -#include +#include +#include #if defined(CONFIG_SOC_NRF5340_CPUAPP) #include @@ -51,6 +54,36 @@ LOG_MODULE_REGISTER(bap_usb, CONFIG_BT_BAP_STREAM_LOG_LEVEL); #define USB_OUT_RING_BUF_SIZE (CONFIG_BT_ISO_RX_BUF_COUNT * LC3_MAX_NUM_SAMPLES_STEREO) #define USB_IN_RING_BUF_SIZE (USB_MONO_FRAME_SIZE * USB_ENQUEUE_COUNT) +#define IN_TERMINAL_ID UAC2_ENTITY_ID(DT_NODELABEL(in_terminal)) +#define OUT_TERMINAL_ID UAC2_ENTITY_ID(DT_NODELABEL(out_terminal)) + +#if defined CONFIG_BT_AUDIO_RX +static void usb_data_request(const struct device *dev); +#endif /* CONFIG_BT_AUDIO_RX */ + +static bool in_terminal_enabled; +static bool out_terminal_enabled; +static void usb_terminal_update_cb(const struct device *dev, uint8_t terminal, bool enabled, + bool microframes, void *user_data) +{ + if (terminal == IN_TERMINAL_ID) { + in_terminal_enabled = enabled; + } else if (terminal == OUT_TERMINAL_ID) { + out_terminal_enabled = enabled; + } else { + /* no-op */ + } +} + +static void usb_sof_cb(const struct device *dev, void *user_data) +{ +#if defined CONFIG_BT_AUDIO_RX + if (in_terminal_enabled) { + usb_data_request(dev); + } /* else no-op, but is mandatory to register */ +#endif /* CONFIG_BT_AUDIO_RX */ +} + #if defined CONFIG_BT_AUDIO_RX struct decoded_sdu { int16_t right_frames[MAX_CODEC_FRAMES_PER_SDU][LC3_MAX_NUM_SAMPLES_MONO]; @@ -62,13 +95,13 @@ struct decoded_sdu { } decoded_sdu; RING_BUF_DECLARE(usb_out_ring_buf, USB_OUT_RING_BUF_SIZE); -NET_BUF_POOL_DEFINE(usb_out_buf_pool, USB_ENQUEUE_COUNT, USB_STEREO_FRAME_SIZE, 0, net_buf_destroy); +K_MEM_SLAB_DEFINE_STATIC(usb_out_buf_pool, ROUND_UP(USB_STEREO_FRAME_SIZE, UDC_BUF_GRANULARITY), + USB_ENQUEUE_COUNT, UDC_BUF_ALIGN); /* USB consumer callback, called every 1ms, consumes data from ring-buffer */ -static void usb_data_request_cb(const struct device *dev) +static void usb_data_request(const struct device *dev) { - uint8_t usb_audio_data[USB_STEREO_FRAME_SIZE] = {0}; - struct net_buf *pcm_buf; + void *pcm_buf; uint32_t size; int err; @@ -77,16 +110,18 @@ static void usb_data_request_cb(const struct device *dev) return; } - pcm_buf = net_buf_alloc(&usb_out_buf_pool, K_NO_WAIT); - if (pcm_buf == NULL) { - LOG_WRN("Could not allocate pcm_buf"); + err = k_mem_slab_alloc(&usb_out_buf_pool, &pcm_buf, K_NO_WAIT); + if (err != 0) { + LOG_WRN("Could not allocate pcm_buf: %d", err); return; } /* This may fail without causing issues since usb_audio_data is 0-initialized */ - size = ring_buf_get(&usb_out_ring_buf, usb_audio_data, sizeof(usb_audio_data)); - - net_buf_add_mem(pcm_buf, usb_audio_data, sizeof(usb_audio_data)); + size = ring_buf_get(&usb_out_ring_buf, pcm_buf, USB_STEREO_FRAME_SIZE); + if (size != USB_STEREO_FRAME_SIZE) { + /* If we could not fill the buffer, zero-fill the rest (possibly all) */ + memset(((uint8_t *)pcm_buf) + size, 0, USB_STEREO_FRAME_SIZE - size); + } if (size != 0) { static size_t cnt; @@ -102,7 +137,7 @@ static void usb_data_request_cb(const struct device *dev) } } - err = usb_audio_send(dev, pcm_buf, sizeof(usb_audio_data)); + err = usbd_uac2_send(dev, IN_TERMINAL_ID, pcm_buf, USB_STEREO_FRAME_SIZE); if (err != 0) { static size_t cnt; @@ -111,14 +146,14 @@ static void usb_data_request_cb(const struct device *dev) LOG_ERR("Failed to send USB audio: %d (%zu)", err, cnt); } - net_buf_unref(pcm_buf); + k_mem_slab_free(&usb_out_buf_pool, pcm_buf); } } -static void usb_data_written_cb(const struct device *dev, struct net_buf *buf, size_t size) +static void usb_buf_release_cb(const struct device *dev, uint8_t terminal, void *buf, + void *user_data) { - /* Unreference the buffer now that the USB is done with it */ - net_buf_unref(buf); + k_mem_slab_free(&usb_out_buf_pool, buf); } static void bap_usb_send_frames_to_usb(void) @@ -321,6 +356,11 @@ void bap_usb_clear_frames_to_usb(void) #endif /* CONFIG_BT_AUDIO_RX */ #if defined(CONFIG_BT_AUDIO_TX) +/* Allocate 3: 1 for USB to receive data to and 2 additional buffers to prevent out of memory + * errors when USB host decides to perform rapid terminal enable/disable cycles. + */ +K_MEM_SLAB_DEFINE_STATIC(usb_in_buf_pool, USB_STEREO_FRAME_SIZE, 3, UDC_BUF_ALIGN); + BUILD_ASSERT((USB_IN_RING_BUF_SIZE % USB_MONO_FRAME_SIZE) == 0); static int16_t usb_in_left_ring_buffer[USB_IN_RING_BUF_SIZE]; static int16_t usb_in_right_ring_buffer[USB_IN_RING_BUF_SIZE]; @@ -373,23 +413,39 @@ static void stream_cb(struct shell_stream *sh_stream, void *user_data) } } -static void usb_data_received_cb(const struct device *dev, struct net_buf *buf, size_t size) +static void *usb_get_recv_buf_cb(const struct device *dev, uint8_t terminal, uint16_t size, + void *user_data) { - const size_t old_write_index = write_index; - static size_t cnt; - int16_t *pcm; + void *buf = NULL; + int ret; - if (buf == NULL) { - return; + if (!out_terminal_enabled) { + return NULL; } - if (size != USB_STEREO_FRAME_SIZE) { - net_buf_unref(buf); + __ASSERT(size <= USB_STEREO_FRAME_SIZE, "%u was not <= %d", size, USB_STEREO_FRAME_SIZE); + + ret = k_mem_slab_alloc(&usb_in_buf_pool, &buf, K_NO_WAIT); + if (ret != 0) { + LOG_WRN("Failed to allocate buffer: %d", ret); + } + return buf; +} + +static void usb_data_recv_cb(const struct device *dev, uint8_t terminal, void *buf, uint16_t size, + void *user_data) +{ + const size_t old_write_index = write_index; + static size_t cnt; + int16_t *pcm; + + if (!out_terminal_enabled || buf == NULL || size == 0U) { + k_mem_slab_free(&usb_in_buf_pool, buf); return; } - pcm = (int16_t *)buf->data; + pcm = (int16_t *)buf; /* Split the data into left and right as LC3 uses LLLLRRRR instead of LRLRLRLR as USB * @@ -418,7 +474,7 @@ static void usb_data_received_cb(const struct device *dev, struct net_buf *buf, LOG_DBG("USB Data received (count = %d)", cnt); } - net_buf_unref(buf); + k_mem_slab_free(&usb_in_buf_pool, buf); } bool bap_usb_can_get_full_sdu(struct shell_stream *sh_stream) @@ -522,29 +578,154 @@ void bap_usb_get_frame(struct shell_stream *sh_stream, enum bt_audio_location ch } #endif /* CONFIG_BT_AUDIO_TX */ +static int bap_usbd_setup_device(struct usbd_context *const bap_usbd) +{ + static const uint8_t attributes = + (IS_ENABLED(CONFIG_BT_BAP_SHELL_USB_SELF_POWERED) ? USB_SCD_SELF_POWERED : 0U) | + (IS_ENABLED(CONFIG_BT_BAP_SHELL_USB_REMOTE_WAKEUP) ? USB_SCD_REMOTE_WAKEUP : 0U); + USBD_DESC_CONFIG_DEFINE(fs_cfg_desc, "FS Configuration"); + USBD_CONFIGURATION_DEFINE(bap_usb_fs_config, attributes, CONFIG_BT_BAP_SHELL_USB_MAX_POWER, + &fs_cfg_desc); + USBD_DESC_PRODUCT_DEFINE(bap_usb_product, CONFIG_BT_BAP_SHELL_USB_PRODUCT); + USBD_DESC_MANUFACTURER_DEFINE(bap_usb_mfr, "Zephyr Project"); + USBD_DESC_LANG_DEFINE(bap_usb_lang); + const uint8_t class_cfg = 0x01U; + const uint8_t subclass = 0x02U; + const uint8_t protocol = 0x01U; + + int err; + + err = usbd_add_descriptor(bap_usbd, &bap_usb_lang); + if (err != 0) { + LOG_ERR("Failed to initialize language descriptor: %d", err); + + return err; + } + + err = usbd_add_descriptor(bap_usbd, &bap_usb_mfr); + if (err != 0) { + LOG_ERR("Failed to initialize manufacturer descriptor: %d", err); + + return err; + } + + err = usbd_add_descriptor(bap_usbd, &bap_usb_product); + if (err != 0) { + LOG_ERR("Failed to initialize product descriptor: %d", err); + + return err; + } + + if (IS_ENABLED(CONFIG_HWINFO)) { + USBD_DESC_SERIAL_NUMBER_DEFINE(bap_usb_sn); + + err = usbd_add_descriptor(bap_usbd, &bap_usb_sn); + if (err != 0) { + LOG_ERR("Failed to initialize serial number descriptor: %d", err); + + return err; + } + } + + if (USBD_SUPPORTS_HIGH_SPEED && usbd_caps_speed(bap_usbd) == USBD_SPEED_HS) { + USBD_DESC_CONFIG_DEFINE(hs_cfg_desc, "HS Configuration"); + USBD_CONFIGURATION_DEFINE(bap_usb_hs_config, attributes, + CONFIG_BT_BAP_SHELL_USB_MAX_POWER, &hs_cfg_desc); + + LOG_DBG("Setting up High-Speed USB"); + + err = usbd_add_configuration(bap_usbd, USBD_SPEED_HS, &bap_usb_hs_config); + if (err != 0) { + LOG_ERR("Failed to add High-Speed configuration: %d", err); + + return err; + } + + err = usbd_register_all_classes(bap_usbd, USBD_SPEED_HS, class_cfg, NULL); + if (err != 0) { + LOG_ERR("Failed to add register High-Speed classes: %d", err); + + return err; + } + + err = usbd_device_set_code_triple(bap_usbd, USBD_SPEED_HS, USB_BCC_MISCELLANEOUS, + subclass, protocol); + if (err != 0) { + LOG_ERR("Failed to set High-Speed code triple: %d", err); + + return err; + } + } + + LOG_DBG("Setting up Full-Speed USB"); + + err = usbd_add_configuration(bap_usbd, USBD_SPEED_FS, &bap_usb_fs_config); + if (err != 0) { + LOG_ERR("Failed to add Full-Speed configuration: %d", err); + + return err; + } + + err = usbd_register_all_classes(bap_usbd, USBD_SPEED_FS, class_cfg, NULL); + if (err != 0) { + LOG_ERR("Failed to register Full-Speed classes: %d", err); + + return err; + } + + err = usbd_device_set_code_triple(bap_usbd, USBD_SPEED_FS, USB_BCC_MISCELLANEOUS, subclass, + protocol); + if (err != 0) { + LOG_ERR("Failed to set Full-Speed code triple: %d", err); + + return err; + } + + usbd_self_powered(bap_usbd, attributes & USB_SCD_SELF_POWERED); + + return 0; +} + int bap_usb_init(void) { - const struct device *hs_dev = DEVICE_DT_GET(DT_NODELABEL(hs_0)); - static const struct usb_audio_ops usb_ops = { -#if defined(CONFIG_BT_AUDIO_RX) - .data_request_cb = usb_data_request_cb, - .data_written_cb = usb_data_written_cb, -#endif /* CONFIG_BT_AUDIO_RX */ + USBD_DEVICE_DEFINE(bap_usbd, DEVICE_DT_GET(DT_NODELABEL(zephyr_udc0)), + CONFIG_BT_BAP_SHELL_USB_VID, CONFIG_BT_BAP_SHELL_USB_PID); + const struct device *uac2_headset = DEVICE_DT_GET(DT_NODELABEL(uac2_headset)); + static struct uac2_ops usb_audio_ops = { + .terminal_update_cb = usb_terminal_update_cb, + .sof_cb = usb_sof_cb, #if defined(CONFIG_BT_AUDIO_TX) - .data_received_cb = usb_data_received_cb, + .get_recv_buf = usb_get_recv_buf_cb, + .data_recv_cb = usb_data_recv_cb, #endif /* CONFIG_BT_AUDIO_TX */ +#if defined(CONFIG_BT_AUDIO_RX) + .buf_release_cb = usb_buf_release_cb, +#endif /* CONFIG_BT_AUDIO_RX */ }; int err; - if (!device_is_ready(hs_dev)) { + if (!device_is_ready(uac2_headset)) { LOG_ERR("Cannot get USB Headset Device"); return -EIO; } - usb_audio_register(hs_dev, &usb_ops); - err = usb_enable(NULL); + usbd_uac2_set_ops(uac2_headset, &usb_audio_ops, NULL); + + err = bap_usbd_setup_device(&bap_usbd); if (err != 0) { - LOG_ERR("Failed to enable USB"); + LOG_ERR("Failed to setup USB device: %d", err); + return err; + } + + err = usbd_init(&bap_usbd); + if (err != 0) { + LOG_ERR("Failed to initialize device support: %d", err); + return err; + } + + err = usbd_enable(&bap_usbd); + if (err != 0) { + LOG_ERR("Failed to enable USBD: %d", err); return err; } @@ -561,5 +742,7 @@ int bap_usb_init(void) } } + LOG_INF("USB audio enabled"); + return 0; } diff --git a/subsys/bluetooth/audio/shell/cap_initiator.c b/subsys/bluetooth/audio/shell/cap_initiator.c index d9a076984966e..92044b9328450 100644 --- a/subsys/bluetooth/audio/shell/cap_initiator.c +++ b/subsys/bluetooth/audio/shell/cap_initiator.c @@ -1236,6 +1236,7 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, BT_AUDIO_LOCATION_FRONT_LEFT)}; struct bt_cap_initiator_broadcast_subgroup_param subgroup_param = {0}; struct bt_cap_initiator_broadcast_create_param create_param = {0}; + uint32_t broadcast_id = 0U; struct bt_le_ext_adv *adv; int err; @@ -1250,6 +1251,15 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, return -ENOEXEC; } + err = bt_rand(&broadcast_id, BT_AUDIO_BROADCAST_ID_SIZE); + if (err != 0) { + bt_shell_error("Unable to generate broadcast ID: %d\n", err); + + return -ENOEXEC; + } + + shell_print(sh, "Generated broadcast_id 0x%06X", broadcast_id); + copy_broadcast_source_preset(&default_source, &default_broadcast_source_preset); default_source.qos.sdu *= param->chan_cnt; @@ -1278,6 +1288,7 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, err = bt_cap_initiator_broadcast_audio_create(&create_param, &default_source.cap_source); if (err != 0) { shell_error(sh, "Failed to create broadcast source: %d", err); + return -ENOEXEC; } @@ -1290,6 +1301,7 @@ int cap_ac_broadcast(const struct shell *sh, size_t argc, char **argv, "and update / set the base via `bt per-adv data`", param->name); default_source.is_cap = true; + default_source.broadcast_id = broadcast_id; return 0; } @@ -1430,49 +1442,6 @@ SHELL_CMD_ARG_REGISTER(cap_initiator, &cap_initiator_cmds, "Bluetooth CAP initiator shell commands", cmd_cap_initiator, 1, 1); -static size_t nonconnectable_ad_data_add(struct bt_data *data_array, const size_t data_array_size) -{ -#if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) - if (default_source.cap_source != NULL && default_source.is_cap) { - static uint8_t ad_cap_broadcast_announcement[5] = { - BT_UUID_16_ENCODE(BT_UUID_BROADCAST_AUDIO_VAL), - }; - uint32_t broadcast_id; - int err; - - err = bt_rand(&broadcast_id, BT_AUDIO_BROADCAST_ID_SIZE); - if (err) { - bt_shell_error("Unable to generate broadcast ID: %d\n", err); - - return 0; - } - - sys_put_le24(broadcast_id, &ad_cap_broadcast_announcement[2]); - data_array[0].type = BT_DATA_SVC_DATA16; - data_array[0].data_len = ARRAY_SIZE(ad_cap_broadcast_announcement); - data_array[0].data = ad_cap_broadcast_announcement; - - return 1; - } -#endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ - - return 0; -} - -size_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size, - const bool discoverable, const bool connectable) -{ - if (!discoverable) { - return 0; - } - - if (!connectable) { - return nonconnectable_ad_data_add(data_array, data_array_size); - } - - return 0; -} - size_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size) { #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) diff --git a/subsys/bluetooth/audio/shell/ccp_call_control_server.c b/subsys/bluetooth/audio/shell/ccp_call_control_server.c index dc0bcc8bf8c07..4934fe8b52c3d 100644 --- a/subsys/bluetooth/audio/shell/ccp_call_control_server.c +++ b/subsys/bluetooth/audio/shell/ccp_call_control_server.c @@ -15,6 +15,7 @@ #include #include #include +#include static struct bt_ccp_call_control_server_bearer *bearers[CONFIG_BT_CCP_CALL_CONTROL_SERVER_BEARER_COUNT]; @@ -79,6 +80,81 @@ static int cmd_ccp_call_control_server_init(const struct shell *sh, size_t argc, return 0; } +static int validate_and_get_index(const struct shell *sh, const char *index_arg) +{ + unsigned long index; + int err = 0; + + index = shell_strtoul(index_arg, 0, &err); + if (err != 0) { + shell_error(sh, "Could not parse index: %d", err); + + return -ENOEXEC; + } + + if (index >= CONFIG_BT_TBS_BEARER_COUNT) { + shell_error(sh, "Invalid index: %lu", index); + + return -ENOEXEC; + } + + return (int)index; +} + +static int cmd_ccp_call_control_server_set_bearer_name(const struct shell *sh, size_t argc, + char *argv[]) +{ + const char *name; + int index = 0; + int err = 0; + + if (argc > 2) { + index = validate_and_get_index(sh, argv[1]); + if (index < 0) { + return index; + } + } + + name = argv[argc - 1]; + + err = bt_ccp_call_control_server_set_bearer_provider_name(bearers[index], name); + if (err != 0) { + shell_error(sh, "Failed to set bearer[%d] name: %d", index, err); + + return -ENOEXEC; + } + + shell_print(sh, "Bearer[%d] name: %s", index, name); + + return 0; +} + +static int cmd_ccp_call_control_server_get_bearer_name(const struct shell *sh, size_t argc, + char *argv[]) +{ + const char *name; + int index = 0; + int err = 0; + + if (argc > 1) { + index = validate_and_get_index(sh, argv[1]); + if (index < 0) { + return index; + } + } + + err = bt_ccp_call_control_server_get_bearer_provider_name(bearers[index], &name); + if (err != 0) { + shell_error(sh, "Failed to get bearer[%d] name: %d", index, err); + + return -ENOEXEC; + } + + shell_print(sh, "Bearer[%d] name: %s", index, name); + + return 0; +} + static int cmd_ccp_call_control_server(const struct shell *sh, size_t argc, char **argv) { if (argc > 1) { @@ -93,6 +169,11 @@ static int cmd_ccp_call_control_server(const struct shell *sh, size_t argc, char SHELL_STATIC_SUBCMD_SET_CREATE(ccp_call_control_server_cmds, SHELL_CMD_ARG(init, NULL, "Initialize CCP Call Control Server", cmd_ccp_call_control_server_init, 1, 0), + SHELL_CMD_ARG(set_bearer_name, NULL, + "Set bearer name [index] ", + cmd_ccp_call_control_server_set_bearer_name, 2, 1), + SHELL_CMD_ARG(get_bearer_name, NULL, "Get bearer name [index]", + cmd_ccp_call_control_server_get_bearer_name, 1, 1), SHELL_SUBCMD_SET_END); SHELL_CMD_ARG_REGISTER(ccp_call_control_server, &ccp_call_control_server_cmds, diff --git a/subsys/bluetooth/audio/tbs.c b/subsys/bluetooth/audio/tbs.c index 33fddbdd20a33..7526c5327e0f2 100644 --- a/subsys/bluetooth/audio/tbs.c +++ b/subsys/bluetooth/audio/tbs.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "audio_internal.h" @@ -68,6 +69,10 @@ struct tbs_flags { /* A service instance can either be a GTBS or a TBS instance */ struct tbs_inst { /* Attribute values */ + /* TODO: The provider name should be removed from the tbs_inst and instead by stored by the + * user of TBS. This will be done once the CCP API is complete as the CCP Server will own + * all the data instead of the TBS + */ char provider_name[CONFIG_BT_TBS_MAX_PROVIDER_NAME_LENGTH]; char uci[BT_TBS_MAX_UCI_SIZE]; uint8_t technology; diff --git a/subsys/bluetooth/audio/tbs_client.c b/subsys/bluetooth/audio/tbs_client.c index f22af7c2e3ee1..7895115c911e0 100644 --- a/subsys/bluetooth/audio/tbs_client.c +++ b/subsys/bluetooth/audio/tbs_client.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/subsys/bluetooth/audio/tbs_internal.h b/subsys/bluetooth/audio/tbs_internal.h index 68b4dbb0e7004..e8ae47d44d2da 100644 --- a/subsys/bluetooth/audio/tbs_internal.h +++ b/subsys/bluetooth/audio/tbs_internal.h @@ -246,12 +246,12 @@ struct bt_tbs_call_cp_retrieve { struct bt_tbs_call_cp_originate { uint8_t opcode; - uint8_t uri[0]; + uint8_t uri[]; } __packed; struct bt_tbs_call_cp_join { uint8_t opcode; - uint8_t call_indexes[0]; + uint8_t call_indexes[]; } __packed; union bt_tbs_call_cp_t { diff --git a/subsys/bluetooth/audio/vocs.c b/subsys/bluetooth/audio/vocs.c index d4d0c29002576..a8a5db18bd1ba 100644 --- a/subsys/bluetooth/audio/vocs.c +++ b/subsys/bluetooth/audio/vocs.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include "audio_internal.h" diff --git a/subsys/bluetooth/controller/ll_sw/lll.h b/subsys/bluetooth/controller/ll_sw/lll.h index b5d8fffeac37f..f5d33c90d70cd 100644 --- a/subsys/bluetooth/controller/ll_sw/lll.h +++ b/subsys/bluetooth/controller/ll_sw/lll.h @@ -14,8 +14,6 @@ #define TICKER_USER_ID_ULL_LOW MAYFLY_CALL_ID_2 #define TICKER_USER_ID_THREAD MAYFLY_CALL_ID_PROGRAM -#define EVENT_PIPELINE_MAX 7 - #define ADV_INT_UNIT_US 625U #define SCAN_INT_UNIT_US 625U #define CONN_INT_UNIT_US 1250U @@ -194,6 +192,19 @@ enum { #define TICKER_ID_ULL_BASE ((TICKER_ID_LLL_PREEMPT) + 1) +/* Number of (connection interval) events that can occur per (connection) event length. + * These number of event's prepare will be deferred if overlapping a single Tx-Rx chain. + */ +#if defined(CONFIG_BT_CTLR_PHY_CODED) +/* Connection events per 251 byte PDU Coded PHY S8 event length */ +#define EVENT_DEFER_MAX 4U +#elif defined(CONFIG_BT_CTLR_PHY_2M) +/* Low latency connection interval events per 27 byte PDU 2M PHY event length */ +#define EVENT_DEFER_MAX 1U +#else /* !CONFIG_BT_CTLR_PHY_CODED && !CONFIG_BT_CTLR_PHY_2M */ +#define EVENT_DEFER_MAX 0U +#endif /* !CONFIG_BT_CTLR_PHY_CODED && !CONFIG_BT_CTLR_PHY_2M */ + enum done_result { DONE_COMPLETED, DONE_ABORTED, @@ -236,7 +247,8 @@ struct lll_prepare_param { #if defined(CONFIG_BT_CTLR_JIT_SCHEDULING) int8_t prio; #endif /* CONFIG_BT_CTLR_JIT_SCHEDULING */ - uint8_t force; + uint8_t force:1; + uint8_t defer:1; void *param; }; diff --git a/subsys/bluetooth/controller/ll_sw/lll_common.c b/subsys/bluetooth/controller/ll_sw/lll_common.c index ed35b4ddd0837..c6c561dbb76dc 100644 --- a/subsys/bluetooth/controller/ll_sw/lll_common.c +++ b/subsys/bluetooth/controller/ll_sw/lll_common.c @@ -62,6 +62,8 @@ int lll_prepare(lll_is_abort_cb_t is_abort_cb, lll_abort_cb_t abort_cb, prepare_param->prio = prio; #endif /* CONFIG_BT_CTLR_JIT_SCHEDULING */ + prepare_param->defer = 0U; + err = lll_prepare_resolve(is_abort_cb, abort_cb, prepare_cb, prepare_param, 0U, 0U); return err; diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c index 81df96981dd2a..90a0945f5a19b 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c @@ -150,20 +150,15 @@ void isr_radio(void) { if (radio_has_disabled()) { isr_cb(isr_cb_param); + } else { + /* Nothing to do here, we shall not get spurious Radio IRQ */ } } void radio_isr_set(radio_isr_cb_t cb, void *param) { - irq_disable(HAL_RADIO_IRQn); - isr_cb_param = param; isr_cb = cb; - - nrf_radio_int_enable(NRF_RADIO, HAL_RADIO_INTENSET_DISABLED_Msk); - - NVIC_ClearPendingIRQ(HAL_RADIO_IRQn); - irq_enable(HAL_RADIO_IRQn); } void radio_setup(void) @@ -197,7 +192,6 @@ void radio_setup(void) void radio_reset(void) { - irq_disable(HAL_RADIO_IRQn); /* nRF SoC generic radio reset/initializations * Note: Only registers whose bits are partially modified across @@ -573,6 +567,9 @@ void radio_disable(void) hal_radio_sw_switch_cleanup(); #endif /* !CONFIG_BT_CTLR_TIFS_HW */ + /* Reset/disable PPI/DPPI */ + radio_tmr_status_reset(); + NRF_RADIO->SHORTS = 0; nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_DISABLE); } @@ -2529,6 +2526,7 @@ void radio_ccm_disable(void) nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_STOP); nrf_ccm_disable(NRF_CCM); } +#endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */ #if defined(CONFIG_BT_CTLR_PRIVACY) static uint8_t MALIGN(4) _aar_scratch[3]; @@ -2659,7 +2657,6 @@ uint8_t radio_ar_resolve(const uint8_t *addr) } #endif /* CONFIG_BT_CTLR_PRIVACY */ -#endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */ #if defined(CONFIG_BT_CTLR_DF_SUPPORT) && !defined(CONFIG_ZTEST) /* @brief Function configures CTE inline register to start sampling of CTE diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h index 0afaa7d60bfb1..f01f9859db4bb 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5.h @@ -63,9 +63,12 @@ #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC) #include -#include #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */ +#if defined(CONFIG_BT_CTLR_PRIVACY) +#include +#endif /* CONFIG_BT_CTLR_PRIVACY */ + /* Define to reset PPI registration. * This has to come before the ppi/dppi includes below. */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h index ce0f8ac101475..11bb973994b4f 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h @@ -175,18 +175,6 @@ static inline void hal_trigger_crypt_ppi_disable(void) nrf_ccm_subscribe_clear(NRF_CCM, NRF_CCM_TASK_START); } -#if defined(CONFIG_BT_CTLR_PRIVACY) -/******************************************************************************* - * Trigger automatic address resolution on Bit counter match: - * wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task. - */ -static inline void hal_trigger_aar_ppi_config(void) -{ - nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH, HAL_TRIGGER_AAR_PPI); - nrf_aar_subscribe_set(NRF_AAR, NRF_AAR_TASK_START, HAL_TRIGGER_AAR_PPI); -} -#endif /* CONFIG_BT_CTLR_PRIVACY */ - /* When hardware does not support Coded PHY we still allow the Controller * implementation to accept Coded PHY flags, but the Controller will use 1M * PHY on air. This is implementation specific feature. @@ -229,6 +217,18 @@ static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void) #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */ #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */ +#if defined(CONFIG_BT_CTLR_PRIVACY) +/******************************************************************************* + * Trigger automatic address resolution on Bit counter match: + * wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task. + */ +static inline void hal_trigger_aar_ppi_config(void) +{ + nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH, HAL_TRIGGER_AAR_PPI); + nrf_aar_subscribe_set(NRF_AAR, NRF_AAR_TASK_START, HAL_TRIGGER_AAR_PPI); +} +#endif /* CONFIG_BT_CTLR_PRIVACY */ + /******************************************************************************/ #if !defined(CONFIG_BT_CTLR_TIFS_HW) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h index 21b615892a3bf..4b29bb4fe21d2 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h @@ -259,19 +259,6 @@ static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void) } #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */ -/******************************************************************************* - * Trigger automatic address resolution on Bit counter match: - * wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task. - * - * PPI channel 23 is pre-programmed with the following fixed settings: - * EEP: RADIO->EVENTS_BCMATCH - * TEP: AAR->TASKS_START - */ -static inline void hal_trigger_aar_ppi_config(void) -{ - /* No need to configure anything for the pre-programmed channel. */ -} - /******************************************************************************* * Trigger Radio Rate override upon Rateboost event. */ @@ -286,6 +273,19 @@ static inline void hal_trigger_rateoverride_ppi_config(void) } #endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */ +/******************************************************************************* + * Trigger automatic address resolution on Bit counter match: + * wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task. + * + * PPI channel 23 is pre-programmed with the following fixed settings: + * EEP: RADIO->EVENTS_BCMATCH + * TEP: AAR->TASKS_START + */ +static inline void hal_trigger_aar_ppi_config(void) +{ + /* No need to configure anything for the pre-programmed channel. */ +} + /******************************************************************************/ #if !defined(CONFIG_BT_CTLR_TIFS_HW) /* PPI setup used for SW-based auto-switching during TIFS. */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c index 25f46d3a0ec6a..b44847c05850a 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c @@ -71,7 +71,9 @@ static inline void done_inc(void); #endif /* CONFIG_BT_CTLR_LOW_LAT_ULL_DONE */ static inline bool is_done_sync(void); static inline struct lll_event *prepare_dequeue_iter_ready_get(uint8_t *idx); -static inline struct lll_event *resume_enqueue(lll_prepare_cb_t resume_cb); +static inline struct lll_event *resume_enqueue(lll_is_abort_cb_t is_abort_cb, + lll_abort_cb_t abort_cb, lll_prepare_cb_t resume_cb, + void *param); static void isr_race(void *param); #if !defined(CONFIG_BT_CTLR_LOW_LAT) @@ -307,6 +309,9 @@ int lll_init(void) #endif #endif /* !CONFIG_BT_CTLR_DYNAMIC_INTERRUPTS */ + /* Enable Radio interrupt on radio state disabled; after tx or rx or explicitly disabled */ + nrf_radio_int_enable(NRF_RADIO, HAL_RADIO_INTENSET_DISABLED_Msk); + /* Enable IRQs */ irq_enable(HAL_RADIO_IRQn); irq_enable(HAL_RTC_IRQn); @@ -525,6 +530,9 @@ int lll_done(void *param) param = event.curr.param; event.curr.param = NULL; + /* Resume events will have set event.curr.param to NULL, these + * should not generate done events. + */ if (param) { ull = HDR_LLL2ULL(param); } else { @@ -637,7 +645,8 @@ uint32_t lll_preempt_calc(struct ull_hdr *ull, uint8_t ticker_id, return 0; } - diff += HAL_TICKER_CNTR_CMP_OFFSET_MIN; + diff += HAL_TICKER_CNTR_CMP_OFFSET_MIN + + HAL_TICKER_US_TO_TICKS_CEIL(HAL_RADIO_ISR_LATENCY_MAX_US); if (diff > HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_START_US)) { /* TODO: for Low Latency Feature with Advanced XTAL feature. * 1. Release retained HF clock. @@ -805,6 +814,8 @@ void lll_isr_early_abort(void *param) { int err; + radio_status_reset(); + radio_isr_set(isr_race, param); if (!radio_is_idle()) { radio_disable(); @@ -892,7 +903,7 @@ int lll_prepare_resolve(lll_is_abort_cb_t is_abort_cb, lll_abort_cb_t abort_cb, LL_ASSERT(next); #if !defined(CONFIG_BT_CTLR_LOW_LAT) - if (is_resume) { + if (is_resume || prepare_param->defer) { return -EINPROGRESS; } @@ -933,7 +944,16 @@ int lll_prepare_resolve(lll_is_abort_cb_t is_abort_cb, lll_abort_cb_t abort_cb, LL_ASSERT(err); if (err == -EAGAIN) { - next = resume_enqueue(resume_cb); + void *curr_param; + + /* Remove parameter assignment from currently active radio event so + * that done event is not generated. + */ + curr_param = event.curr.param; + event.curr.param = NULL; + + next = resume_enqueue(event.curr.is_abort_cb, event.curr.abort_cb, + resume_cb, curr_param); LL_ASSERT(next); } else { LL_ASSERT(err == -ECANCELED); @@ -1011,24 +1031,21 @@ static inline struct lll_event *prepare_dequeue_iter_ready_get(uint8_t *idx) do { ready = ull_prepare_dequeue_iter(idx); - } while (ready && (ready->is_aborted || ready->is_resume)); + } while ((ready != NULL) && ((ready->is_aborted != 0U) || (ready->is_resume != 0U) || + (ready->prepare_param.defer != 0U))); return ready; } -static inline struct lll_event *resume_enqueue(lll_prepare_cb_t resume_cb) +static inline struct lll_event *resume_enqueue(lll_is_abort_cb_t is_abort_cb, + lll_abort_cb_t abort_cb, lll_prepare_cb_t resume_cb, + void *param) { struct lll_prepare_param prepare_param = {0}; - /* Enqueue into prepare pipeline as resume radio event, and remove - * parameter assignment from currently active radio event so that - * done event is not generated. - */ - prepare_param.param = event.curr.param; - event.curr.param = NULL; + prepare_param.param = param; - return ull_prepare_enqueue(event.curr.is_abort_cb, event.curr.abort_cb, - &prepare_param, resume_cb, 1); + return ull_prepare_enqueue(is_abort_cb, abort_cb, &prepare_param, resume_cb, 1U); } static void isr_race(void *param) @@ -1311,10 +1328,27 @@ static void preempt(void *param) /* Check if current event want to continue */ err = event.curr.is_abort_cb(ready->prepare_param.param, event.curr.param, &resume_cb); if (!err || (err == -EBUSY)) { - /* Returns -EBUSY when same curr and next state/role, do not - * abort same curr and next event. - */ - if (err != -EBUSY) { + if (err == -EBUSY) { + uint32_t ret; + + /* Returns -EBUSY when same curr and next ready state/role, do not abort + * same curr and next ready event. + */ + ready->prepare_param.defer = 1U; + + /* Find next prepare that is ready and not a resume */ + ready = prepare_dequeue_iter_ready_get(&idx); + if (ready == NULL) { + /* No ready prepare */ + return; + } + + /* Start the preempt timeout for next ready prepare */ + ret = preempt_ticker_start(ready, NULL, ready); + LL_ASSERT((ret == TICKER_STATUS_SUCCESS) || + (ret == TICKER_STATUS_BUSY)); + + } else { /* Let preemptor LLL know about the cancelled prepare */ ready->is_aborted = 1; ready->abort_cb(&ready->prepare_param, ready->prepare_param.param); @@ -1328,9 +1362,27 @@ static void preempt(void *param) /* Check if resume requested */ if (err == -EAGAIN) { - uint8_t is_resume_abort = 0U; + lll_is_abort_cb_t is_abort_cb; + lll_abort_cb_t abort_cb; + uint8_t is_resume_abort; struct lll_event *iter; uint8_t iter_idx; + void *curr_param; + + /* Remove parameter assignment from currently active radio event so that done event + * is not generated. + */ + curr_param = event.curr.param; + event.curr.param = NULL; + + /* backup is_abort_cb and abort_cb */ + is_abort_cb = event.curr.is_abort_cb; + abort_cb = event.curr.abort_cb; + + /* Iterate twice to ensure preempt timeout is setup after all duplicate resume + * events are aborted. + */ + is_resume_abort = 0U; preempt_abort_resume: /* Abort any duplicate non-resume, that they get dequeued */ @@ -1339,7 +1391,7 @@ static void preempt(void *param) while (iter) { if (!iter->is_aborted && (is_resume_abort || !iter->is_resume) && - event.curr.param == iter->prepare_param.param) { + (curr_param == iter->prepare_param.param)) { iter->is_aborted = 1; iter->abort_cb(&iter->prepare_param, iter->prepare_param.param); @@ -1363,7 +1415,7 @@ static void preempt(void *param) } /* Enqueue as resume event */ - iter = resume_enqueue(resume_cb); + iter = resume_enqueue(is_abort_cb, abort_cb, resume_cb, curr_param); LL_ASSERT(iter); } else { LL_ASSERT(err == -ECANCELED); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central.c index 0fd8a368047e1..4f082b4957a40 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central.c @@ -247,12 +247,21 @@ static int prepare_cb(struct lll_prepare_param *p) overhead = lll_preempt_calc(ull, (TICKER_ID_CONN_BASE + lll->handle), ticks_at_event); /* check if preempt to start has changed */ if (overhead) { - LL_ASSERT_OVERHEAD(overhead); + int err; + + if (p->defer == 1U) { + /* We accept the overlap as previous event elected to continue */ + err = 0; + } else { + LL_ASSERT_OVERHEAD(overhead); + + err = -ECANCELED; + } radio_isr_set(lll_isr_abort, lll); radio_disable(); - return -ECANCELED; + return err; } #endif /* !CONFIG_BT_CTLR_XTAL_ADVANCED */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c index e57b0ac513bee..7ae759dd2bec9 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c @@ -466,11 +466,23 @@ static void isr_tx(void *param) struct node_rx_pdu *node_rx; uint32_t hcto; + /* Call to ensure packet/event timer accumulates the elapsed time + * under single timer use. + */ + (void)radio_is_tx_done(); + /* Clear radio tx status and events */ lll_isr_tx_status_reset(); /* Close subevent, one tx-rx chain */ - radio_switch_complete_and_disable(); + if (IS_ENABLED(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)) { + /* Required under single time tIFS switching, to accumulate the packet + * timer value at the time of clear on radio end. + */ + radio_switch_complete_end_capture_and_disable(); + } else { + radio_switch_complete_and_disable(); + } /* Get reference to CIS LLL context */ cis_lll = param; @@ -549,7 +561,9 @@ static void isr_tx(void *param) #if defined(CONFIG_BT_CTLR_PROFILE_ISR) || \ defined(HAL_RADIO_GPIO_HAVE_PA_PIN) radio_tmr_end_capture(); -#endif /* CONFIG_BT_CTLR_PROFILE_ISR */ +#endif /* CONFIG_BT_CTLR_PROFILE_ISR || + * HAL_RADIO_GPIO_HAVE_PA_PIN + */ #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN) radio_gpio_lna_setup(); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c index ea5028a00f104..1527987c02d02 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_conn.c @@ -69,6 +69,7 @@ static uint8_t crc_valid; static uint8_t is_aborted; static uint16_t tx_cnt; static uint16_t trx_cnt; +static uint8_t trx_busy_iteration; #if defined(CONFIG_BT_CTLR_LE_ENC) static uint8_t mic_state; @@ -153,6 +154,7 @@ void lll_conn_prepare_reset(void) crc_valid = 0U; crc_expire = 0U; is_aborted = 0U; + trx_busy_iteration = 0U; #if defined(CONFIG_BT_CTLR_LE_ENC) mic_state = LLL_CONN_MIC_NONE; @@ -160,45 +162,69 @@ void lll_conn_prepare_reset(void) } #if defined(CONFIG_BT_CENTRAL) +/* Number of times central event being aborted by same event instance be skipped */ +/* NOTE: Coded PHY S8 coding of 251 byte PDU at 7.5 ms connection interval need up to 4 events + * to be skipped due to large connection event length. + */ +#define CENTRAL_TRX_BUSY_ITERATION_MAX MIN(4U, (EVENT_DEFER_MAX)) + int lll_conn_central_is_abort_cb(void *next, void *curr, lll_prepare_cb_t *resume_cb) { struct lll_conn *lll = curr; - /* Do not abort if near supervision timeout */ - if (lll->forced) { - return 0; - } + if (next != curr) { + /* Do not be aborted by a different event if near supervision timeout */ + if ((lll->forced == 1U) && (trx_cnt < 1U)) { + return 0; + } - /* Do not be aborted by same event if a single central trx has not been - * exchanged. - */ - if ((next == curr) && (trx_cnt < 1U)) { + } else if ((next == curr) && (trx_cnt < 1U) && + (trx_busy_iteration < CENTRAL_TRX_BUSY_ITERATION_MAX)) { + trx_busy_iteration++; + + /* Do not be aborted by same event if a single central's Rx has not completed. + * Cases where single trx duration can be greater than connection interval. + */ return -EBUSY; } + LL_ASSERT(trx_busy_iteration < CENTRAL_TRX_BUSY_ITERATION_MAX); + return -ECANCELED; } #endif /* CONFIG_BT_CENTRAL */ #if defined(CONFIG_BT_PERIPHERAL) +/* Number of times peripheral event being aborted by same event instance be skipped */ +/* NOTE: Coded PHY S8 coding of 251 byte PDU at 7.5 ms connection interval need up to 4 events + * to be skipped due to large connection event length. + */ +#define PERIPHERAL_TRX_BUSY_ITERATION_MAX MIN(4U, (EVENT_DEFER_MAX)) + int lll_conn_peripheral_is_abort_cb(void *next, void *curr, lll_prepare_cb_t *resume_cb) { struct lll_conn *lll = curr; - /* Do not abort if near supervision timeout */ - if (lll->forced) { - return 0; - } + if (next != curr) { + /* Do not be aborted by a different event if near supervision timeout */ + if ((lll->forced == 1U) && (tx_cnt < 1U)) { + return 0; + } - /* Do not be aborted by same event if a single peripheral trx has not - * been exchanged. - */ - if ((next == curr) && (tx_cnt < 1U)) { + } else if ((next == curr) && (tx_cnt < 1U) && + (trx_busy_iteration < PERIPHERAL_TRX_BUSY_ITERATION_MAX)) { + trx_busy_iteration++; + + /* Do not be aborted by same event if a single peripheral's Tx has not completed. + * Cases where single trx duration can be greater than connection interval. + */ return -EBUSY; } + LL_ASSERT(trx_busy_iteration < PERIPHERAL_TRX_BUSY_ITERATION_MAX); + return -ECANCELED; } #endif /* CONFIG_BT_PERIPHERAL */ @@ -254,13 +280,10 @@ void lll_conn_abort_cb(struct lll_prepare_param *prepare_param, void *param) #if defined(CONFIG_BT_PERIPHERAL) if (lll->role == BT_HCI_ROLE_PERIPHERAL) { /* Accumulate window widening */ - lll->periph.window_widening_prepare_us += - lll->periph.window_widening_periodic_us * - (prepare_param->lazy + 1); - if (lll->periph.window_widening_prepare_us > - lll->periph.window_widening_max_us) { - lll->periph.window_widening_prepare_us = - lll->periph.window_widening_max_us; + lll->periph.window_widening_prepare_us += lll->periph.window_widening_periodic_us * + (prepare_param->lazy + 1); + if (lll->periph.window_widening_prepare_us > lll->periph.window_widening_max_us) { + lll->periph.window_widening_prepare_us = lll->periph.window_widening_max_us; } } #endif /* CONFIG_BT_PERIPHERAL */ @@ -414,11 +437,27 @@ void lll_conn_isr_rx(void *param) cte_len = 0U; } +#if defined(CONFIG_BT_PERIPHERAL) + /* Lets close early so that drift compensation is calculated before this event overlaps + * with next interval. + * TODO: Optimize, to improve throughput, by removing this early close and using the drift + * compensation value in the overlapping next interval, if under high throughput + * scenarios. + */ + is_done = is_done || ((lll->role == BT_HCI_ROLE_PERIPHERAL) && + (lll->periph.window_size_event_us != 0U)); +#endif /* CONFIG_BT_PERIPHERAL */ + /* Decide on event continuation and hence Radio Shorts to use */ is_done = is_done || ((crc_ok) && (pdu_data_rx->md == 0) && (pdu_data_tx->md == 0) && (pdu_data_tx->len == 0)); + /* Do not continue anymore if this event had continued despite an abort requested by same + * connection instance when overlapping due to connection event length being larger than + * the connection interval. + */ + is_done = is_done || (trx_busy_iteration != 0U); if (is_done) { radio_isr_set(isr_done, param); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral.c index 0ed7a63af8d8e..8c3b83efd7215 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral.c @@ -154,24 +154,21 @@ static int prepare_cb(struct lll_prepare_param *p) } /* Accumulate window widening */ - lll->periph.window_widening_prepare_us += - lll->periph.window_widening_periodic_us * (lll->lazy_prepare + 1U); - if (lll->periph.window_widening_prepare_us > - lll->periph.window_widening_max_us) { - lll->periph.window_widening_prepare_us = - lll->periph.window_widening_max_us; + lll->periph.window_widening_prepare_us += lll->periph.window_widening_periodic_us * + lll->lazy_prepare; + if (lll->periph.window_widening_prepare_us > lll->periph.window_widening_max_us) { + lll->periph.window_widening_prepare_us = lll->periph.window_widening_max_us; } - /* current window widening */ - lll->periph.window_widening_event_us += - lll->periph.window_widening_prepare_us; - lll->periph.window_widening_prepare_us = 0; - if (lll->periph.window_widening_event_us > - lll->periph.window_widening_max_us) { - lll->periph.window_widening_event_us = - lll->periph.window_widening_max_us; + /* Current window widening */ + lll->periph.window_widening_event_us += lll->periph.window_widening_prepare_us; + if (lll->periph.window_widening_event_us > lll->periph.window_widening_max_us) { + lll->periph.window_widening_event_us = lll->periph.window_widening_max_us; } + /* Pre-increment window widening */ + lll->periph.window_widening_prepare_us = lll->periph.window_widening_periodic_us; + /* current window size */ lll->periph.window_size_event_us += lll->periph.window_size_prepare_us; @@ -339,12 +336,21 @@ static int prepare_cb(struct lll_prepare_param *p) overhead = lll_preempt_calc(ull, (TICKER_ID_CONN_BASE + lll->handle), ticks_at_event); /* check if preempt to start has changed */ if (overhead) { - LL_ASSERT_OVERHEAD(overhead); + int err; + + if (p->defer == 1U) { + /* We accept the overlap as previous event elected to continue */ + err = 0; + } else { + LL_ASSERT_OVERHEAD(overhead); + + err = -ECANCELED; + } radio_isr_set(lll_isr_abort, lll); radio_disable(); - return -ECANCELED; + return err; } #endif /* CONFIG_BT_CTLR_XTAL_ADVANCED */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c index 6b925b1118e50..5d23a12993bdf 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c @@ -555,8 +555,15 @@ static void isr_rx(void *param) radio_tmr_ready_save(radio_tmr_ready_get() - se_offset_us); } - /* Close subevent, one tx-rx chain */ - radio_switch_complete_and_disable(); + /* Close subevent, one rx-tx chain */ + if (IS_ENABLED(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)) { + /* Required under single time tIFS switching, to accumulate the packet + * timer value at the time of clear on radio end. + */ + radio_switch_complete_end_capture_and_disable(); + } else { + radio_switch_complete_and_disable(); + } /* FIXME: Do not call this for every event/subevent */ ull_conn_iso_lll_cis_established(param); @@ -869,6 +876,11 @@ static void isr_tx(void *param) uint32_t start_us; uint32_t hcto; + /* Call to ensure packet/event timer accumulates the elapsed time + * under single timer use. + */ + (void)radio_is_tx_done(); + lll_isr_tx_sub_status_reset(); /* Get reference to CIS LLL context */ diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c index 8aedcd44a4f88..79f60677be7c5 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c @@ -791,7 +791,12 @@ static void isr_tx(void *param) radio_pkt_rx_set(node_rx->pdu); /* assert if radio packet ptr is not set and radio started rx */ - LL_ASSERT(!radio_is_ready()); + if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) { + LL_ASSERT_MSG(!radio_is_address(), "%s: Radio ISR latency: %u", __func__, + lll_prof_latency_get()); + } else { + LL_ASSERT(!radio_is_address()); + } #if defined(CONFIG_BT_CTLR_PRIVACY) if (ull_filter_lll_rl_enabled()) { @@ -1109,6 +1114,21 @@ static void isr_done_cleanup(void *param) } #endif /* CONFIG_BT_CTLR_ADV_EXT */ + /* Lets tail chain the execution of LLL disable of any scan event in the pipeline if scan + * role is to be stopped. + * This is for the case of connection setup or the duration has expired. + */ + if (lll->is_stop != 0U) { + static memq_link_t link; + static struct mayfly mfy = {0, 0, &link, NULL, lll_disable}; + uint32_t ret; + + mfy.param = param; + + ret = mayfly_enqueue(TICKER_USER_ID_LLL, TICKER_USER_ID_LLL, 1U, &mfy); + LL_ASSERT(!ret); + } + lll_isr_cleanup(param); } @@ -1196,7 +1216,12 @@ static inline int isr_rx_pdu(struct lll_scan *lll, struct pdu_adv *pdu_adv_rx, radio_pkt_tx_set(pdu_tx); /* assert if radio packet ptr is not set and radio started tx */ - LL_ASSERT(!radio_is_ready()); + if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) { + LL_ASSERT_MSG(!radio_is_address(), "%s: Radio ISR latency: %u", __func__, + lll_prof_latency_get()); + } else { + LL_ASSERT(!radio_is_address()); + } if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) { lll_prof_cputime_capture(); @@ -1328,7 +1353,12 @@ static inline int isr_rx_pdu(struct lll_scan *lll, struct pdu_adv *pdu_adv_rx, radio_pkt_tx_set(pdu_tx); /* assert if radio packet ptr is not set and radio started tx */ - LL_ASSERT(!radio_is_ready()); + if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) { + LL_ASSERT_MSG(!radio_is_address(), "%s: Radio ISR latency: %u", __func__, + lll_prof_latency_get()); + } else { + LL_ASSERT(!radio_is_address()); + } if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) { lll_prof_cputime_capture(); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c index 89e5fffc331e9..1a8aeb536f0cf 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c @@ -170,7 +170,8 @@ uint8_t lll_scan_aux_setup(struct pdu_adv *pdu, uint8_t pdu_phy, /* No need to scan further if no aux_ptr filled */ aux_ptr = (void *)pri_dptr; if (unlikely(!pri_hdr->aux_ptr || !PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) || - (PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) > EXT_ADV_AUX_PHY_LE_CODED))) { + (PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) > EXT_ADV_AUX_PHY_LE_CODED) || + (aux_ptr->chan_idx >= CHM_USED_COUNT_MAX))) { return 0; } @@ -355,7 +356,8 @@ void lll_scan_aux_isr_aux_setup(void *param) aux_start_us -= EVENT_JITTER_US; start_us = radio_tmr_start_us(0, aux_start_us); - LL_ASSERT(start_us == (aux_start_us + 1U)); + LL_ASSERT_MSG(start_us == (aux_start_us + 1U), "aux_offset %u us, start_us %u != %u", + aux_offset_us, start_us, (aux_start_us + 1U)); /* Setup header complete timeout */ hcto = start_us; @@ -686,6 +688,7 @@ static void abort_cb(struct lll_prepare_param *prepare_param, void *param) static void isr_done(void *param) { + struct lll_scan *scan_lll = NULL; struct lll_sync *lll; uint8_t is_lll_scan; @@ -693,6 +696,9 @@ static void isr_done(void *param) if (param) { lll = ull_scan_aux_lll_parent_get(param, &is_lll_scan); + if (is_lll_scan) { + scan_lll = (void *)lll; + } } else { lll = NULL; } @@ -726,6 +732,21 @@ static void isr_done(void *param) #endif /* CONFIG_BT_CTLR_SCAN_AUX_USE_CHAINS */ } + /* Lets tail chain the execution of LLL disable of any scan event in the pipeline if scan + * role is to be stopped. + * This is for the case of connection setup or the duration has expired. + */ + if ((scan_lll != NULL) && (scan_lll->is_stop != 0U)) { + static memq_link_t link; + static struct mayfly mfy = {0, 0, &link, NULL, lll_disable}; + uint32_t ret; + + mfy.param = scan_lll; + + ret = mayfly_enqueue(TICKER_USER_ID_LLL, TICKER_USER_ID_LLL, 1U, &mfy); + LL_ASSERT(!ret); + } + lll_isr_cleanup(param); } @@ -916,6 +937,7 @@ static void isr_rx(struct lll_scan *lll, struct lll_scan_aux *lll_aux, radio_isr_set(isr_done, lll->lll_aux); } } + radio_disable(); } diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c index 071e72c73200b..4f4dad90754f5 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c @@ -1301,6 +1301,13 @@ static void isr_rx(void *param) radio_switch_complete_and_disable(); + /* Setup Access Address capture for subsequent subevent if there has been no anchor point + * sync previously. + */ + if (radio_tmr_aa_restore() == 0U) { + radio_tmr_aa_capture(); + } + /* PDU Header Complete TimeOut, calculate the absolute timeout in * microseconds by when a PDU header is to be received for each * subevent. @@ -1344,16 +1351,30 @@ static void isr_rx(void *param) hcto -= radio_rx_chain_delay_get(lll->phy, PHY_FLAGS_S8); hcto -= addr_us_get(lll->phy); hcto -= radio_rx_ready_delay_get(lll->phy, PHY_FLAGS_S8); + overhead_us = radio_rx_chain_delay_get(lll->phy, PHY_FLAGS_S8); overhead_us += addr_us_get(lll->phy); overhead_us += radio_rx_ready_delay_get(lll->phy, PHY_FLAGS_S8); overhead_us += (EVENT_CLOCK_JITTER_US << 1); + + LL_ASSERT(EVENT_IFS_US > overhead_us); + jitter_max_us = (EVENT_IFS_US - overhead_us) >> 1; - jitter_max_us -= RANGE_DELAY_US + HAL_RADIO_TMR_START_DELAY_US; + jitter_max_us = (jitter_max_us * nse) / (lll->num_bis * lll->nse); + overhead_us = HAL_RADIO_TMR_START_DELAY_US; + if (jitter_max_us > overhead_us) { + jitter_max_us -= overhead_us; + } else { + jitter_max_us = 0U; + } + jitter_us = (EVENT_CLOCK_JITTER_US << 1) * nse; if (jitter_us > jitter_max_us) { jitter_us = jitter_max_us; } + + LL_ASSERT(hcto > jitter_us); + hcto -= jitter_us; start_us = hcto; @@ -1365,7 +1386,6 @@ static void isr_rx(void *param) * the current subevent we are listening. */ hcto += (jitter_us << 1); - hcto += RANGE_DELAY_US + HAL_RADIO_TMR_START_DELAY_US; } else { /* First subevent PDU was not received, hence setup radio packet * timer header complete timeout from where the first subevent diff --git a/subsys/bluetooth/controller/ll_sw/openisa/lll/pdu_vendor.h b/subsys/bluetooth/controller/ll_sw/openisa/lll/pdu_vendor.h index 7dd10aa7a247a..e67c22e8b03b7 100644 --- a/subsys/bluetooth/controller/ll_sw/openisa/lll/pdu_vendor.h +++ b/subsys/bluetooth/controller/ll_sw/openisa/lll/pdu_vendor.h @@ -4,33 +4,27 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + /* Minimum vendor specific Rx payload buffer allocation */ #define LL_VND_OCTETS_RX_MIN 0 /* No vendor Data PDU struct octet3 */ struct pdu_data_vnd_octet3 { - union { - uint8_t resv[0]; - } __packed; + FLEXIBLE_ARRAY_DECLARE(uint8_t, resv); } __packed; /* No vendor BIS PDU struct octet3 */ struct pdu_bis_vnd_octet3 { - union { - uint8_t resv[0]; - } __packed; + FLEXIBLE_ARRAY_DECLARE(uint8_t, resv); } __packed; /* No vendor CIS PDU struct octet3 */ struct pdu_cis_vnd_octet3 { - union { - uint8_t resv[0]; - } __packed; + FLEXIBLE_ARRAY_DECLARE(uint8_t, resv); } __packed; /* No ISOAL helper vendor ISO PDU struct octet3 */ struct pdu_iso_vnd_octet3 { - union { - uint8_t resv[0]; - } __packed; + FLEXIBLE_ARRAY_DECLARE(uint8_t, resv); } __packed; diff --git a/subsys/bluetooth/controller/ll_sw/pdu.h b/subsys/bluetooth/controller/ll_sw/pdu.h index e1edced699787..430704c84514f 100644 --- a/subsys/bluetooth/controller/ll_sw/pdu.h +++ b/subsys/bluetooth/controller/ll_sw/pdu.h @@ -210,6 +210,7 @@ /* Channel Map Unused channels count minimum */ #define CHM_USED_COUNT_MIN 2U +#define CHM_USED_COUNT_MAX 37U /* Channel Map hop count minimum and maximum */ #define CHM_HOP_COUNT_MIN 5U diff --git a/subsys/bluetooth/controller/ll_sw/ull.c b/subsys/bluetooth/controller/ll_sw/ull.c index 83af68020ef36..bf15820ecd6db 100644 --- a/subsys/bluetooth/controller/ll_sw/ull.c +++ b/subsys/bluetooth/controller/ll_sw/ull.c @@ -335,8 +335,9 @@ static struct k_sem sem_ticker_api_cb; static struct k_sem *sem_recv; /* Declare prepare-event FIFO: mfifo_prep. - * Queue of struct node_rx_event_done */ +#define EVENT_PIPELINE_MAX (7U + (EVENT_DEFER_MAX)) + static MFIFO_DEFINE(prep, sizeof(struct lll_event), EVENT_PIPELINE_MAX); /* Declare done-event RXFIFO. This is a composite pool-backed MFIFO for rx_nodes. @@ -371,12 +372,12 @@ static MFIFO_DEFINE(prep, sizeof(struct lll_event), EVENT_PIPELINE_MAX); #if !defined(VENDOR_EVENT_DONE_MAX) #if defined(CONFIG_BT_CTLR_ADV_EXT) && defined(CONFIG_BT_OBSERVER) #if defined(CONFIG_BT_CTLR_PHY_CODED) -#define EVENT_DONE_MAX 6 +#define EVENT_DONE_MAX (6U + EVENT_DEFER_MAX) #else /* !CONFIG_BT_CTLR_PHY_CODED */ -#define EVENT_DONE_MAX 5 +#define EVENT_DONE_MAX (5U + EVENT_DEFER_MAX) #endif /* !CONFIG_BT_CTLR_PHY_CODED */ #else /* !CONFIG_BT_CTLR_ADV_EXT || !CONFIG_BT_OBSERVER */ -#define EVENT_DONE_MAX 4 +#define EVENT_DONE_MAX (4U + EVENT_DEFER_MAX) #endif /* !CONFIG_BT_CTLR_ADV_EXT || !CONFIG_BT_OBSERVER */ #else #define EVENT_DONE_MAX VENDOR_EVENT_DONE_MAX @@ -2021,6 +2022,7 @@ int ull_disable(void *lll) struct ull_hdr *hdr; struct k_sem sem; uint32_t ret; + int err; hdr = HDR_LLL2ULL(lll); if (!ull_ref_get(hdr)) { @@ -2053,7 +2055,12 @@ int ull_disable(void *lll) &mfy); LL_ASSERT(!ret); - return k_sem_take(&sem, ULL_DISABLE_TIMEOUT); + err = k_sem_take(&sem, ULL_DISABLE_TIMEOUT); + if (err != 0) { + return err; + } + + return 0; } void *ull_pdu_rx_alloc_peek(uint8_t count) @@ -2143,6 +2150,8 @@ void *ull_prepare_dequeue_iter(uint8_t *idx) void ull_prepare_dequeue(uint8_t caller_id) { + uint32_t param_normal_head_ticks = 0U; + uint32_t param_normal_next_ticks = 0U; void *param_normal_head = NULL; void *param_normal_next = NULL; void *param_resume_head = NULL; @@ -2179,6 +2188,7 @@ void ull_prepare_dequeue(uint8_t caller_id) next = ull_prepare_dequeue_get(); while (next) { + uint32_t ticks = next->prepare_param.ticks_at_expire; void *param = next->prepare_param.param; uint8_t is_aborted = next->is_aborted; uint8_t is_resume = next->is_resume; @@ -2226,8 +2236,10 @@ void ull_prepare_dequeue(uint8_t caller_id) if (!is_resume) { if (!param_normal_head) { param_normal_head = param; + param_normal_head_ticks = ticks; } else if (!param_normal_next) { param_normal_next = param; + param_normal_next_ticks = ticks; } } else { if (!param_resume_head) { @@ -2243,16 +2255,15 @@ void ull_prepare_dequeue(uint8_t caller_id) */ if (!next->is_aborted && ((!next->is_resume && - ((next->prepare_param.param == - param_normal_head) || - (next->prepare_param.param == - param_normal_next))) || - (next->is_resume && - !param_normal_next && - ((next->prepare_param.param == - param_resume_head) || - (next->prepare_param.param == - param_resume_next))))) { + (((next->prepare_param.param == param_normal_head) && + (next->prepare_param.ticks_at_expire == + param_normal_head_ticks)) || + ((next->prepare_param.param == param_normal_next) && + (next->prepare_param.ticks_at_expire == + param_normal_next_ticks)))) || + (next->is_resume && !param_normal_next && + ((next->prepare_param.param == param_resume_head) || + (next->prepare_param.param == param_resume_next))))) { break; } } @@ -3028,6 +3039,9 @@ static inline void rx_demux_event_done(memq_link_t *link, if (ull_hdr) { LL_ASSERT(ull_ref_get(ull_hdr)); ull_ref_dec(ull_hdr); + } else { + /* No reference count decrement, event placed back as resume event in the pipeline. + */ } /* Process role dependent event done */ diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv.c b/subsys/bluetooth/controller/ll_sw/ull_adv.c index 911a433f81de8..18f3f24b11db2 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_adv.c +++ b/subsys/bluetooth/controller/ll_sw/ull_adv.c @@ -1095,7 +1095,8 @@ uint8_t ll_adv_enable(uint8_t enable) conn_lll->df_tx_cfg.is_initialized = 0U; conn_lll->df_tx_cfg.cte_rsp_en = 0U; #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_TX */ - conn->connect_expire = 6; + conn->event_counter = 0U; + conn->connect_expire = CONN_ESTAB_COUNTDOWN; conn->supervision_expire = 0; #if defined(CONFIG_BT_CTLR_LE_PING) diff --git a/subsys/bluetooth/controller/ll_sw/ull_central.c b/subsys/bluetooth/controller/ll_sw/ull_central.c index 000f1640223f7..1771cda124bda 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_central.c +++ b/subsys/bluetooth/controller/ll_sw/ull_central.c @@ -268,6 +268,7 @@ uint8_t ll_create_connection(uint16_t scan_interval, uint16_t scan_window, conn_lll->df_tx_cfg.cte_rsp_en = 0U; #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_TX */ + conn->event_counter = 0U; conn->connect_expire = CONN_ESTAB_COUNTDOWN; conn->supervision_expire = 0U; conn_interval_us = (uint32_t)interval * CONN_INT_UNIT_US; @@ -945,6 +946,15 @@ void ull_central_ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift, ref = ull_ref_inc(&conn->ull); LL_ASSERT(ref); + /* Increment event counter. + * + * Refer to BT Spec v6.0, Vol 6, Part B, Section 4.5.1 Connection events + * + * `the connEventCounter shall wrap from 0xFFFF to 0x0000. This counter is used to + * synchronize Link Layer control procedures.` + */ + conn->event_counter += (lazy + 1U); + /* De-mux 2 tx node from FIFO, sufficient to be able to set MD bit */ ull_conn_tx_demux(2); @@ -1007,8 +1017,6 @@ static void ticker_op_stop_scan_cb(uint32_t status, void *param) #if defined(CONFIG_BT_CTLR_ADV_EXT) && defined(CONFIG_BT_CTLR_PHY_CODED) static void ticker_op_stop_scan_other_cb(uint32_t status, void *param) { - static memq_link_t link; - static struct mayfly mfy = {0, 0, &link, NULL, NULL}; struct ll_scan_set *scan; struct ull_hdr *hdr; @@ -1027,11 +1035,13 @@ static void ticker_op_stop_scan_other_cb(uint32_t status, void *param) */ scan = param; hdr = &scan->ull; - mfy.param = &scan->lll; if (ull_ref_get(hdr)) { + static memq_link_t link; + static struct mayfly mfy = {0, 0, &link, NULL, lll_disable}; uint32_t ret; - mfy.fp = lll_disable; + mfy.param = &scan->lll; + ret = mayfly_enqueue(TICKER_USER_ID_ULL_LOW, TICKER_USER_ID_LLL, 0, &mfy); LL_ASSERT(!ret); diff --git a/subsys/bluetooth/controller/ll_sw/ull_conn.c b/subsys/bluetooth/controller/ll_sw/ull_conn.c index 39043a5a17bac..b68eaea195897 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_conn.c +++ b/subsys/bluetooth/controller/ll_sw/ull_conn.c @@ -130,23 +130,18 @@ static uint8_t force_md_cnt_calc(struct lll_conn *lll_conn, uint32_t tx_rate); (LL_LENGTH_OCTETS_TX_MAX + \ BT_CTLR_USER_TX_BUFFER_OVERHEAD)) -#define CONN_DATA_BUFFERS CONFIG_BT_BUF_ACL_TX_COUNT - -static MFIFO_DEFINE(conn_tx, sizeof(struct lll_tx), CONN_DATA_BUFFERS); +static MFIFO_DEFINE(conn_tx, sizeof(struct lll_tx), CONFIG_BT_BUF_ACL_TX_COUNT); static MFIFO_DEFINE(conn_ack, sizeof(struct lll_tx), - (CONN_DATA_BUFFERS + - LLCP_TX_CTRL_BUF_COUNT)); + (CONFIG_BT_BUF_ACL_TX_COUNT + LLCP_TX_CTRL_BUF_COUNT)); static struct { void *free; - uint8_t pool[CONN_TX_BUF_SIZE * CONN_DATA_BUFFERS]; + uint8_t pool[CONN_TX_BUF_SIZE * CONFIG_BT_BUF_ACL_TX_COUNT]; } mem_conn_tx; static struct { void *free; - uint8_t pool[sizeof(memq_link_t) * - (CONN_DATA_BUFFERS + - LLCP_TX_CTRL_BUF_COUNT)]; + uint8_t pool[sizeof(memq_link_t) * (CONFIG_BT_BUF_ACL_TX_COUNT + LLCP_TX_CTRL_BUF_COUNT)]; } mem_link_tx; #if defined(CONFIG_BT_CTLR_DATA_LENGTH) @@ -909,6 +904,12 @@ void ull_conn_setup(memq_link_t *rx_link, struct node_rx_pdu *rx) LL_ASSERT(!hdr->disabled_cb); hdr->disabled_param = rx; hdr->disabled_cb = conn_setup_adv_scan_disabled_cb; + + /* NOTE: we are not forcing a lll_disable, in case of initiator + * we need let the CONNECT_IND PDU be transmitted. There + * is a possibility that a new scan window is in the LLL + * pipeline, it has to be disabled. + */ } else { conn_setup_adv_scan_disabled_cb(rx); } @@ -1696,14 +1697,11 @@ static int init_reset(void) } /* Initialize tx pool. */ - mem_init(mem_conn_tx.pool, CONN_TX_BUF_SIZE, CONN_DATA_BUFFERS, - &mem_conn_tx.free); + mem_init(mem_conn_tx.pool, CONN_TX_BUF_SIZE, CONFIG_BT_BUF_ACL_TX_COUNT, &mem_conn_tx.free); /* Initialize tx link pool. */ mem_init(mem_link_tx.pool, sizeof(memq_link_t), - (CONN_DATA_BUFFERS + - LLCP_TX_CTRL_BUF_COUNT), - &mem_link_tx.free); + (CONFIG_BT_BUF_ACL_TX_COUNT + LLCP_TX_CTRL_BUF_COUNT), &mem_link_tx.free); /* Initialize control procedure system. */ ull_cp_init(); @@ -2190,7 +2188,7 @@ void ull_conn_resume_rx_data(struct ll_conn *conn) uint16_t ull_conn_event_counter_at_prepare(const struct ll_conn *conn) { - return conn->lll.event_counter + conn->lll.latency_prepare + conn->llcp.prep.lazy; + return conn->event_counter + conn->llcp.prep.lazy; } uint16_t ull_conn_event_counter(struct ll_conn *conn) @@ -2390,6 +2388,11 @@ void ull_conn_update_parameters(struct ll_conn *conn, uint8_t is_cu_proc, uint8_ conn_interval_old_us - conn_interval_new_us); } + /* Adjust ULL event counter */ + conn->event_counter += conn->llcp.prep.lazy; + conn->event_counter -= (instant_latency - latency_upd); + + /* Adjust LLL prepare latency */ lll->latency_prepare += conn->llcp.prep.lazy; lll->latency_prepare -= (instant_latency - latency_upd); @@ -2402,43 +2405,52 @@ void ull_conn_update_parameters(struct ll_conn *conn, uint8_t is_cu_proc, uint8_ /* calculate the window widening and interval */ switch (lll->role) { + #if defined(CONFIG_BT_PERIPHERAL) case BT_HCI_ROLE_PERIPHERAL: /* Since LLL prepare doesn't get to run, accumulate window widening here */ lll->periph.window_widening_prepare_us += lll->periph.window_widening_periodic_us * - (conn->llcp.prep.lazy + 1); - if (lll->periph.window_widening_prepare_us > lll->periph.window_widening_max_us) { - lll->periph.window_widening_prepare_us = - lll->periph.window_widening_max_us; - } + conn->llcp.prep.lazy; + + /* Remove old window widening for the latency events */ + lll->periph.window_widening_prepare_us -= lll->periph.window_widening_periodic_us * + instant_latency; - lll->periph.window_widening_prepare_us -= - lll->periph.window_widening_periodic_us * instant_latency; +#if defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) + conn->periph.ticks_to_offset = 0U; +#endif /* CONFIG_BT_CTLR_CONN_PARAM_REQ */ + /* Calculate new window widening per connection event and permitted maximum value */ lll->periph.window_widening_periodic_us = DIV_ROUND_UP(((lll_clock_ppm_local_get() + lll_clock_ppm_get(conn->periph.sca)) * conn_interval_us), 1000000U); lll->periph.window_widening_max_us = (conn_interval_us >> 1U) - EVENT_IFS_US; - lll->periph.window_size_prepare_us = win_size * CONN_INT_UNIT_US; -#if defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) - conn->periph.ticks_to_offset = 0U; -#endif /* CONFIG_BT_CTLR_CONN_PARAM_REQ */ + /* Use requested window size for anchor point at instant, until successful sync */ + lll->periph.window_size_prepare_us = win_size * CONN_INT_UNIT_US; - lll->periph.window_widening_prepare_us += - lll->periph.window_widening_periodic_us * latency_upd; + /* Accumulated new window widening for latency events */ + lll->periph.window_widening_prepare_us += lll->periph.window_widening_periodic_us * + latency_upd; if (lll->periph.window_widening_prepare_us > lll->periph.window_widening_max_us) { lll->periph.window_widening_prepare_us = lll->periph.window_widening_max_us; } - ticks_at_expire -= HAL_TICKER_US_TO_TICKS(lll->periph.window_widening_periodic_us * - latency_upd); + /* Adjust for future window widening */ + ticks_at_expire -= HAL_TICKER_US_TO_TICKS_CEIL( + lll->periph.window_widening_periodic_us * latency_upd); + + /* Window Offset */ ticks_win_offset = HAL_TICKER_US_TO_TICKS((win_offset_us / CONN_INT_UNIT_US) * CONN_INT_UNIT_US); + + /* Periodic interval considering window widening */ periodic_us -= lll->periph.window_widening_periodic_us; + break; #endif /* CONFIG_BT_PERIPHERAL */ + #if defined(CONFIG_BT_CENTRAL) case BT_HCI_ROLE_CENTRAL: ticks_win_offset = HAL_TICKER_US_TO_TICKS(win_offset_us); @@ -2450,6 +2462,7 @@ void ull_conn_update_parameters(struct ll_conn *conn, uint8_t is_cu_proc, uint8_ ticks_win_offset += 1U; break; #endif /*CONFIG_BT_CENTRAL */ + default: LL_ASSERT(0); break; @@ -2977,7 +2990,7 @@ uint8_t ll_conn_set_path_loss_reporting(uint16_t handle, uint8_t enable) } #endif /* CONFIG_BT_CTLR_LE_PATH_LOSS_MONITORING */ -uint8_t ull_is_lll_tx_queue_empty(struct ll_conn *conn) +bool ull_conn_lll_tx_queue_is_empty(struct ll_conn *conn) { - return (memq_peek(conn->lll.memq_tx.head, conn->lll.memq_tx.tail, NULL) == NULL); + return memq_peek(conn->lll.memq_tx.head, conn->lll.memq_tx.tail, NULL) == NULL; } diff --git a/subsys/bluetooth/controller/ll_sw/ull_conn_internal.h b/subsys/bluetooth/controller/ll_sw/ull_conn_internal.h index 1c888fcf9e1e3..59b45579f0b01 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_conn_internal.h +++ b/subsys/bluetooth/controller/ll_sw/ull_conn_internal.h @@ -138,7 +138,7 @@ void ull_conn_resume_rx_data(struct ll_conn *conn); /** * @brief Check if the lower link layer transmit queue is empty */ -uint8_t ull_is_lll_tx_queue_empty(struct ll_conn *conn); +bool ull_conn_lll_tx_queue_is_empty(struct ll_conn *conn); /** * @brief Set path loss parameters diff --git a/subsys/bluetooth/controller/ll_sw/ull_conn_types.h b/subsys/bluetooth/controller/ll_sw/ull_conn_types.h index f901f2ad3cad0..3dce4b52b2a89 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_conn_types.h +++ b/subsys/bluetooth/controller/ll_sw/ull_conn_types.h @@ -167,31 +167,6 @@ struct ll_conn { struct ull_hdr ull; struct lll_conn lll; -#if defined(CONFIG_BT_CTLR_SYNC_TRANSFER_RECEIVER) - struct past_params past; -#endif /* CONFIG_BT_CTLR_SYNC_TRANSFER_RECEIVER */ - - struct ull_tx_q tx_q; - struct llcp_struct llcp; - - struct { - uint8_t reason_final; - /* node rx type with dummy uint8_t to ensure room for terminate - * reason. - * HCI will reference the value using the pdu member of - * struct node_rx_pdu. - * - */ - struct { - struct node_rx_pdu rx; - uint8_t dummy_reason; - } node_rx; - } llcp_terminate; - -/* - * TODO: all the following comes from the legacy LL llcp structure - * and/or needs to be properly integrated in the control procedures - */ union { struct { #if defined(CONFIG_BT_CTLR_CONN_META) @@ -220,14 +195,42 @@ struct ll_conn { #endif /* CONFIG_BT_CENTRAL */ }; + struct ull_tx_q tx_q; + struct llcp_struct llcp; + + /* ULL tracked connection event counter. Under LLL Prepare deferred cases this member + * accumulates the connection event count, necessary for LLCP instant use in ULL. + */ + uint16_t event_counter; + /* Cancel the prepare in the instant a Connection Update takes place */ uint8_t cancel_prepare:1; + /* + * TODO: all the following comes from the legacy LL llcp structure + * and/or needs to be properly integrated in the control procedures + */ + #if defined(CONFIG_BT_CTLR_LE_ENC) /* Pause Rx data PDU's */ uint8_t pause_rx_data:1; #endif /* CONFIG_BT_CTLR_LE_ENC */ + /* Terminate Procedure reason and event memory per connection */ + struct { + uint8_t reason_final; + /* node rx type with dummy uint8_t to ensure room for terminate + * reason. + * HCI will reference the value using the pdu member of + * struct node_rx_pdu. + * + */ + struct { + struct node_rx_pdu rx; + uint8_t dummy_reason; + } node_rx; + } llcp_terminate; + #if defined(CONFIG_BT_CTLR_LE_PING) uint16_t appto_reload; uint16_t appto_expire; @@ -244,6 +247,7 @@ struct ll_conn { uint8_t phy_pref_tx:3; uint8_t phy_pref_rx:3; #endif /* CONFIG_BT_CTLR_PHY */ + #if defined(CONFIG_BT_CTLR_DATA_LENGTH) uint16_t default_tx_octets; @@ -252,6 +256,10 @@ struct ll_conn { #endif /* CONFIG_BT_CTLR_PHY */ #endif /* CONFIG_BT_CTLR_DATA_LENGTH */ +#if defined(CONFIG_BT_CTLR_SYNC_TRANSFER_RECEIVER) + struct past_params past; +#endif /* CONFIG_BT_CTLR_SYNC_TRANSFER_RECEIVER */ + #if defined(CONFIG_BT_CTLR_CHECK_SAME_PEER_CONN) uint8_t own_id_addr_type:1; uint8_t peer_id_addr_type:1; diff --git a/subsys/bluetooth/controller/ll_sw/ull_llcp_conn_upd.c b/subsys/bluetooth/controller/ll_sw/ull_llcp_conn_upd.c index 1f860ff49c545..5fc5a261640f6 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_llcp_conn_upd.c +++ b/subsys/bluetooth/controller/ll_sw/ull_llcp_conn_upd.c @@ -438,7 +438,9 @@ static void lp_cu_send_conn_update_ind_finalize(struct ll_conn *conn, struct pro static void lp_cu_send_conn_update_ind(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt, void *param) { - if (llcp_lr_ispaused(conn) || !llcp_tx_alloc_peek(conn, ctx)) { + if (llcp_lr_ispaused(conn) || !llcp_tx_alloc_peek(conn, ctx) || + (ull_tx_q_peek(&conn->tx_q) != NULL) || !ull_conn_lll_tx_queue_is_empty(conn)) { + llcp_tx_pause_data(conn, LLCP_TX_QUEUE_PAUSE_DATA_CONN_UPD); ctx->state = LP_CU_STATE_WAIT_TX_CONN_UPDATE_IND; } else { /* ensure alloc of TX node, before possibly waiting for NTF node */ @@ -448,6 +450,7 @@ static void lp_cu_send_conn_update_ind(struct ll_conn *conn, struct proc_ctx *ct ctx->state = LP_CU_STATE_WAIT_NTF_AVAIL; } else { lp_cu_send_conn_update_ind_finalize(conn, ctx, evt, param); + llcp_tx_resume_data(conn, LLCP_TX_QUEUE_PAUSE_DATA_CONN_UPD); } } } @@ -459,6 +462,7 @@ static void lp_cu_st_wait_ntf_avail(struct ll_conn *conn, struct proc_ctx *ctx, case LP_CU_EVT_RUN: if (llcp_ntf_alloc_is_available()) { lp_cu_send_conn_update_ind_finalize(conn, ctx, evt, param); + llcp_tx_resume_data(conn, LLCP_TX_QUEUE_PAUSE_DATA_CONN_UPD); } break; default: @@ -915,7 +919,9 @@ static void rp_cu_send_conn_update_ind_finalize(struct ll_conn *conn, struct pro static void rp_cu_send_conn_update_ind(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt, void *param) { - if (llcp_rr_ispaused(conn) || !llcp_tx_alloc_peek(conn, ctx)) { + if (llcp_rr_ispaused(conn) || !llcp_tx_alloc_peek(conn, ctx) || + (ull_tx_q_peek(&conn->tx_q) != NULL) || !ull_conn_lll_tx_queue_is_empty(conn)) { + llcp_tx_pause_data(conn, LLCP_TX_QUEUE_PAUSE_DATA_CONN_UPD); ctx->state = RP_CU_STATE_WAIT_TX_CONN_UPDATE_IND; } else { /* ensure alloc of TX node, before possibly waiting for NTF node */ @@ -925,6 +931,7 @@ static void rp_cu_send_conn_update_ind(struct ll_conn *conn, struct proc_ctx *ct ctx->state = RP_CU_STATE_WAIT_NTF_AVAIL; } else { rp_cu_send_conn_update_ind_finalize(conn, ctx, evt, param); + llcp_tx_resume_data(conn, LLCP_TX_QUEUE_PAUSE_DATA_CONN_UPD); } } } @@ -937,6 +944,7 @@ static void rp_cu_st_wait_ntf_avail(struct ll_conn *conn, struct proc_ctx *ctx, if (llcp_ntf_alloc_is_available()) { /* If NTF node is now avail, so pick it up and continue */ rp_cu_send_conn_update_ind_finalize(conn, ctx, evt, param); + llcp_tx_resume_data(conn, LLCP_TX_QUEUE_PAUSE_DATA_CONN_UPD); } break; default: @@ -1219,11 +1227,9 @@ static void rp_cu_st_wait_tx_conn_update_ind(struct ll_conn *conn, struct proc_c } } -static void rp_cu_check_instant(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt, - void *param) +static void rp_cu_check_instant_by_counter(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt, + uint16_t event_counter, void *param) { - uint16_t event_counter = ull_conn_event_counter_at_prepare(conn); - if (is_instant_reached_or_passed(ctx->data.cu.instant, event_counter)) { bool notify; @@ -1252,6 +1258,22 @@ static void rp_cu_check_instant(struct ll_conn *conn, struct proc_ctx *ctx, uint } } +static void rp_cu_check_instant(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt, + void *param) +{ + uint16_t event_counter = ull_conn_event_counter_at_prepare(conn); + + rp_cu_check_instant_by_counter(conn, ctx, evt, event_counter, param); +} + +static void rp_cu_check_instant_rx_conn_update_ind(struct ll_conn *conn, struct proc_ctx *ctx, + uint8_t evt, void *param) +{ + uint16_t event_counter = ull_conn_event_counter(conn); + + rp_cu_check_instant_by_counter(conn, ctx, evt, event_counter, param); +} + static void rp_cu_st_wait_rx_conn_update_ind(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt, void *param) { @@ -1267,15 +1289,17 @@ static void rp_cu_st_wait_rx_conn_update_ind(struct ll_conn *conn, struct proc_c /* Valid PDU */ if (cu_check_conn_ind_parameters(conn, ctx)) { - if (is_instant_not_passed(ctx->data.cu.instant, - ull_conn_event_counter(conn))) { + uint16_t event_counter = ull_conn_event_counter(conn); + + if (is_instant_not_passed(ctx->data.cu.instant, event_counter)) { /* Keep RX node to use for NTF */ llcp_rx_node_retain(ctx); ctx->state = RP_CU_STATE_WAIT_INSTANT; /* In case we only just received it in time */ - rp_cu_check_instant(conn, ctx, evt, param); + rp_cu_check_instant_rx_conn_update_ind(conn, ctx, evt, + param); break; } diff --git a/subsys/bluetooth/controller/ll_sw/ull_llcp_internal.h b/subsys/bluetooth/controller/ll_sw/ull_llcp_internal.h index 446d78aeadb73..8c50558a08e1f 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_llcp_internal.h +++ b/subsys/bluetooth/controller/ll_sw/ull_llcp_internal.h @@ -47,6 +47,7 @@ enum llcp_tx_q_pause_data_mask { LLCP_TX_QUEUE_PAUSE_DATA_PHY_UPDATE = 0x02, LLCP_TX_QUEUE_PAUSE_DATA_DATA_LENGTH = 0x04, LLCP_TX_QUEUE_PAUSE_DATA_TERMINATE = 0x08, + LLCP_TX_QUEUE_PAUSE_DATA_CONN_UPD = 0x10, }; #if ((CONFIG_BT_CTLR_LLCP_COMMON_TX_CTRL_BUF_NUM <\ diff --git a/subsys/bluetooth/controller/ll_sw/ull_llcp_phy.c b/subsys/bluetooth/controller/ll_sw/ull_llcp_phy.c index 38d3f85685e70..a9b48be2702f7 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_llcp_phy.c +++ b/subsys/bluetooth/controller/ll_sw/ull_llcp_phy.c @@ -542,12 +542,11 @@ static void lp_pu_send_phy_req(struct ll_conn *conn, struct proc_ctx *ctx, uint8 static void lp_pu_send_phy_update_ind(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt, void *param) { - if (llcp_lr_ispaused(conn) || !llcp_tx_alloc_peek(conn, ctx)) { + if (llcp_lr_ispaused(conn) || !llcp_tx_alloc_peek(conn, ctx) || + (ull_tx_q_peek(&conn->tx_q) != NULL) || !ull_conn_lll_tx_queue_is_empty(conn)) { ctx->state = LP_PU_STATE_WAIT_TX_PHY_UPDATE_IND; } else { ctx->tx_opcode = PDU_DATA_LLCTRL_TYPE_PHY_UPD_IND; - - /* Allocate TX node */ ctx->node_ref.tx = llcp_tx_alloc(conn, ctx); lp_pu_tx(conn, ctx, evt, param); } @@ -1011,14 +1010,13 @@ static void rp_pu_send_phy_update_ind(struct ll_conn *conn, struct proc_ctx *ctx { if (llcp_rr_ispaused(conn) || !llcp_tx_alloc_peek(conn, ctx) || (llcp_rr_get_paused_cmd(conn) == PROC_PHY_UPDATE) || - !ull_is_lll_tx_queue_empty(conn)) { + (ull_tx_q_peek(&conn->tx_q) != NULL) || !ull_conn_lll_tx_queue_is_empty(conn)) { ctx->state = RP_PU_STATE_WAIT_TX_PHY_UPDATE_IND; } else { llcp_rr_set_paused_cmd(conn, PROC_CTE_REQ); ctx->tx_opcode = PDU_DATA_LLCTRL_TYPE_PHY_UPD_IND; ctx->node_ref.tx = llcp_tx_alloc(conn, ctx); rp_pu_tx(conn, ctx, evt, param); - } } #endif /* CONFIG_BT_CENTRAL */ diff --git a/subsys/bluetooth/controller/ll_sw/ull_peripheral.c b/subsys/bluetooth/controller/ll_sw/ull_peripheral.c index ccc711d00aaa8..8032b18e99502 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_peripheral.c +++ b/subsys/bluetooth/controller/ll_sw/ull_peripheral.c @@ -580,6 +580,9 @@ void ull_periph_ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift, ref = ull_ref_inc(&conn->ull); LL_ASSERT(ref); + /* Increment event counter */ + conn->event_counter += (lazy + 1U); + /* Append timing parameters */ p.ticks_at_expire = ticks_at_expire; p.remainder = remainder; diff --git a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c index 84f0ff6e2b7e7..953575885bc5a 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c @@ -584,8 +584,9 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) */ if (!aux_ptr || !PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) || is_scan_req || (PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) > EXT_ADV_AUX_PHY_LE_CODED) || - (!IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) && - PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) == EXT_ADV_AUX_PHY_LE_CODED)) { + (!IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) && + PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) == EXT_ADV_AUX_PHY_LE_CODED) || + (aux_ptr->chan_idx >= CHM_USED_COUNT_MAX)) { if (IS_ENABLED(CONFIG_BT_CTLR_SYNC_PERIODIC) && sync_lll) { struct ll_sync_set *sync_set; @@ -846,6 +847,13 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) if (unlikely(scan->is_stop)) { goto ull_scan_aux_rx_flush; } + + /* Remove auxiliary context association with scan context so + * that LLL can differentiate it to being ULL scheduling. + */ + if ((lll != NULL) && (lll->lll_aux == lll_aux)) { + lll->lll_aux = NULL; + } } else { struct ll_sync_set *sync_set; @@ -1379,6 +1387,10 @@ static void flush_safe(void *param) LL_ASSERT(!hdr->disabled_cb); hdr->disabled_param = aux; hdr->disabled_cb = done_disabled_cb; + + /* NOTE: we are not forcing a lll_disable, we will let window + * close at its duration or when preempted. + */ } } @@ -1422,6 +1434,11 @@ static void flush(void *param) scan = HDR_LLL2ULL(lll); scan = ull_scan_is_valid_get(scan); if (!IS_ENABLED(CONFIG_BT_CTLR_SYNC_PERIODIC) || scan) { + /* Remove auxiliary context association with scan context */ + if (lll->lll_aux == &aux->lll) { + lll->lll_aux = NULL; + } + #if defined(CONFIG_BT_CTLR_JIT_SCHEDULING) lll->scan_aux_score = aux->lll.hdr.score; #endif /* CONFIG_BT_CTLR_JIT_SCHEDULING */ @@ -1988,9 +2005,9 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) */ if (!aux_ptr || !PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) || is_scan_req || (PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) > EXT_ADV_AUX_PHY_LE_CODED) || - (!IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) && - PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) == EXT_ADV_AUX_PHY_LE_CODED)) { - + (!IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) && + PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) == EXT_ADV_AUX_PHY_LE_CODED) || + (aux_ptr->chan_idx >= CHM_USED_COUNT_MAX)) { if (is_scan_req) { LL_ASSERT(chain && chain->rx_last); @@ -2607,10 +2624,13 @@ static void flush_safe(void *param) /* If chain is active we need to flush from disabled callback */ if (chain_is_in_list(scan_aux_set.active_chains, chain) && ull_ref_get(&scan_aux_set.ull)) { - chain->next = scan_aux_set.flushing_chains; scan_aux_set.flushing_chains = chain; scan_aux_set.ull.disabled_cb = done_disabled_cb; + + /* NOTE: we are not forcing a lll_disable, we will let window + * close at its duration or when preempted. + */ } else { flush(chain); } diff --git a/subsys/bluetooth/controller/util/dbuf.h b/subsys/bluetooth/controller/util/dbuf.h index 8593b368d3799..3bd10a431af48 100644 --- a/subsys/bluetooth/controller/util/dbuf.h +++ b/subsys/bluetooth/controller/util/dbuf.h @@ -18,7 +18,7 @@ struct dbuf_hdr { /* Size in a bytes of a single element stored in double buffer. */ uint8_t elem_size; /* Pointer for actual buffer memory. Its size should be 2 times @p elem_size. */ - uint8_t data[0]; + uint8_t data[]; }; /** diff --git a/subsys/bluetooth/host/addr_internal.h b/subsys/bluetooth/host/addr_internal.h index e61f62a5714d2..b079c704dac31 100644 --- a/subsys/bluetooth/host/addr_internal.h +++ b/subsys/bluetooth/host/addr_internal.h @@ -11,4 +11,40 @@ void bt_addr_le_copy_resolved(bt_addr_le_t *dst, const bt_addr_le_t *src); -bool bt_addr_le_is_resolved(const bt_addr_le_t *addr); +/** + * @brief Determine whether an HCI LE event address was resolved by the Controller + * + * This helper inspects an HCI LE event address field and reports whether the + * Controller resolved a Resolvable Private Address (RPA) to an identity address + * when producing the event. + * + * @warning The parameter is not a regular application-layer @ref bt_addr_le_t. + * It must be the address field taken directly from an HCI LE event structure. + * In those events, the address "type" uses the Identity Address values to + * indicate that resolution has occurred; this function only checks that bit. + * Do not use this with any @ref bt_addr_le_t obtained from Zephyr host APIs. + * + * The complete (at time of writing) list of events that contain at least one field like this: + * - LE Advertising Report event (@ref bt_hci_evt_le_advertising_report) + * - LE Enhanced Connection Complete event (@ref bt_hci_evt_le_enh_conn_complete) + * - LE Directed Advertising Report event (@ref bt_hci_evt_le_direct_adv_report) + * - LE Extended Advertising Report event (@ref bt_hci_evt_le_ext_advertising_report) + * - LE Scan Request Received event (@ref bt_hci_evt_le_scan_req_received) + * - LE Periodic Advertising Sync Transfer Received event (@ref bt_hci_evt_le_past_received_v2) + * - LE Monitored Advertisers Report event + * + * @note The exact "potentially resolved address field" type is not a distinct + * type in the Core Specification; it is inferred from the common layout of the + * events above. This function only inspects the address type; it does not perform + * address resolution nor consult the resolve list. + * + * @param hci_addr_field_value Address field taken directly from an HCI LE event + * @retval true The Controller resolved the address (the on-air RPA matched an + * IRK in the Controller's resolve list) + * @retval false The address was not resolved by the Controller (resolution + * disabled or no match) + * + * @see bt_addr_le_copy_resolved() to convert a HCI event address type to a + * regular @ref bt_addr_le_t. + */ +bool bt_addr_le_is_resolved(const bt_addr_le_t *hci_addr_field_value); diff --git a/subsys/bluetooth/host/adv.c b/subsys/bluetooth/host/adv.c index 0f18149b134ef..749495bcb5633 100644 --- a/subsys/bluetooth/host/adv.c +++ b/subsys/bluetooth/host/adv.c @@ -1416,7 +1416,7 @@ void bt_le_adv_resume(void) int err; if (!adv) { - LOG_ERR("No valid legacy adv to resume"); + LOG_DBG("No valid legacy adv to resume"); return; } @@ -1495,6 +1495,7 @@ int bt_le_ext_adv_get_info(const struct bt_le_ext_adv *adv, } info->id = adv->id; + info->sid = adv->sid; info->tx_power = adv->tx_power; info->addr = &adv->random_addr; @@ -1546,6 +1547,7 @@ int bt_le_ext_adv_create(const struct bt_le_adv_param *param, } adv->id = param->id; + adv->sid = param->sid; adv->cb = cb; err = le_ext_adv_param_set(adv, param, false); diff --git a/subsys/bluetooth/host/att.c b/subsys/bluetooth/host/att.c index 04bf353fd5eab..82d82526b5b0c 100644 --- a/subsys/bluetooth/host/att.c +++ b/subsys/bluetooth/host/att.c @@ -748,7 +748,7 @@ static struct net_buf *bt_att_chan_create_pdu(struct bt_att_chan *chan, uint8_t /* This will reserve headspace for lower layers */ buf = bt_l2cap_create_pdu_timeout(&att_pool, 0, timeout); if (!buf) { - LOG_ERR("Unable to allocate buffer for op 0x%02x", op); + LOG_DBG("Unable to allocate buffer for op 0x%02x", op); return NULL; } @@ -831,6 +831,7 @@ static void send_err_rsp(struct bt_att_chan *chan, uint8_t req, uint16_t handle, buf = bt_att_chan_create_pdu(chan, BT_ATT_OP_ERROR_RSP, sizeof(*rsp)); if (!buf) { + LOG_ERR("Unable to create err rsp PDU"); return; } @@ -2129,6 +2130,7 @@ static uint8_t att_write_rsp(struct bt_att_chan *chan, uint8_t req, uint8_t rsp, if (rsp) { data.buf = bt_att_chan_create_pdu(chan, rsp, 0); if (!data.buf) { + LOG_ERR("Unable to create rsp PDU"); return BT_ATT_ERR_INSUFFICIENT_RESOURCES; } } @@ -2291,13 +2293,9 @@ static uint8_t att_prep_write_rsp(struct bt_att_chan *chan, uint16_t handle, return 0; } -#endif /* CONFIG_BT_ATT_PREPARE_COUNT */ static uint8_t att_prepare_write_req(struct bt_att_chan *chan, struct net_buf *buf) { -#if CONFIG_BT_ATT_PREPARE_COUNT == 0 - return BT_ATT_ERR_NOT_SUPPORTED; -#else struct bt_att_prepare_write_req *req; uint16_t handle, offset; @@ -2309,10 +2307,8 @@ static uint8_t att_prepare_write_req(struct bt_att_chan *chan, struct net_buf *b LOG_DBG("handle 0x%04x offset %u", handle, offset); return att_prep_write_rsp(chan, handle, offset, buf->data, buf->len); -#endif /* CONFIG_BT_ATT_PREPARE_COUNT */ } -#if CONFIG_BT_ATT_PREPARE_COUNT > 0 static uint8_t exec_write_reassemble(uint16_t handle, uint16_t offset, sys_slist_t *list, struct net_buf_simple *buf) @@ -2432,14 +2428,9 @@ static uint8_t att_exec_write_rsp(struct bt_att_chan *chan, uint8_t flags) return 0; } -#endif /* CONFIG_BT_ATT_PREPARE_COUNT */ - static uint8_t att_exec_write_req(struct bt_att_chan *chan, struct net_buf *buf) { -#if CONFIG_BT_ATT_PREPARE_COUNT == 0 - return BT_ATT_ERR_NOT_SUPPORTED; -#else struct bt_att_exec_write_req *req; req = (void *)buf->data; @@ -2447,8 +2438,8 @@ static uint8_t att_exec_write_req(struct bt_att_chan *chan, struct net_buf *buf) LOG_DBG("flags 0x%02x", req->flags); return att_exec_write_rsp(chan, req->flags); -#endif /* CONFIG_BT_ATT_PREPARE_COUNT */ } +#endif /* CONFIG_BT_ATT_PREPARE_COUNT > 0 */ static uint8_t att_write_cmd(struct bt_att_chan *chan, struct net_buf *buf) { @@ -2731,6 +2722,7 @@ static uint8_t att_indicate(struct bt_att_chan *chan, struct net_buf *buf) buf = bt_att_chan_create_pdu(chan, BT_ATT_OP_CONFIRM, 0); if (!buf) { + LOG_ERR("Unable to create confirm PDU"); return 0; } @@ -2806,6 +2798,7 @@ static const struct att_handler { sizeof(struct bt_att_write_req), ATT_REQUEST, att_write_req }, +#if CONFIG_BT_ATT_PREPARE_COUNT > 0 { BT_ATT_OP_PREPARE_WRITE_REQ, sizeof(struct bt_att_prepare_write_req), ATT_REQUEST, @@ -2814,6 +2807,7 @@ static const struct att_handler { sizeof(struct bt_att_exec_write_req), ATT_REQUEST, att_exec_write_req }, +#endif /* CONFIG_BT_ATT_PREPARE_COUNT > 0 */ { BT_ATT_OP_CONFIRM, 0, ATT_CONFIRMATION, @@ -3266,6 +3260,7 @@ static uint8_t att_req_retry(struct bt_att_chan *att_chan) buf = bt_att_chan_create_pdu(att_chan, req->att_op, req->len); if (!buf) { + LOG_ERR("Unable to create retry PDU (%u)", req->att_op); return BT_ATT_ERR_UNLIKELY; } diff --git a/subsys/bluetooth/host/classic/Kconfig b/subsys/bluetooth/host/classic/Kconfig index 21a46b313fa01..e8f56dd5f780c 100644 --- a/subsys/bluetooth/host/classic/Kconfig +++ b/subsys/bluetooth/host/classic/Kconfig @@ -485,6 +485,14 @@ config BT_AVRCP_CONTROLLER help This option enables the AVRCP profile controller function +config BT_AVRCP_BROWSING + bool "Bluetooth AVRCP Browsing channel support [EXPERIMENTAL]" + select EXPERIMENTAL + select BT_L2CAP_ENH_RET + help + This option enables support for the AVRCP Browsing channel + over Bluetooth BR/EDR. + endif # BT_AVRCP config BT_PAGE_TIMEOUT diff --git a/subsys/bluetooth/host/classic/a2dp.c b/subsys/bluetooth/host/classic/a2dp.c index ec6e624205228..7b6c1bb2e6275 100644 --- a/subsys/bluetooth/host/classic/a2dp.c +++ b/subsys/bluetooth/host/classic/a2dp.c @@ -125,8 +125,13 @@ static int a2dp_discovery_ind(struct bt_avdtp *session, uint8_t *errcode) } static int a2dp_get_capabilities_ind(struct bt_avdtp *session, struct bt_avdtp_sep *sep, - struct net_buf *rsp_buf, uint8_t *errcode) + struct net_buf *rsp_buf, bool get_all_caps, uint8_t *errcode) { + /* The Reporting, Recovery, Content Protection, Header Compression, Multiplexing and + * Delay Reporting services are not supported, so the same response is replied as + * get_capabilities. + */ + ARG_UNUSED(get_all_caps); struct bt_a2dp_ep *ep; __ASSERT(sep, "Invalid sep"); @@ -363,11 +368,11 @@ static int a2dp_set_config_ind(struct bt_avdtp *session, struct bt_avdtp_sep *se return a2dp_process_config_ind(session, sep, int_seid, buf, errcode, false); } -static int a2dp_re_config_ind(struct bt_avdtp *session, struct bt_avdtp_sep *sep, uint8_t int_seid, +static int a2dp_re_config_ind(struct bt_avdtp *session, struct bt_avdtp_sep *sep, struct net_buf *buf, uint8_t *errcode) { __ASSERT(sep, "Invalid sep"); - return a2dp_process_config_ind(session, sep, int_seid, buf, errcode, true); + return a2dp_process_config_ind(session, sep, 0, buf, errcode, true); } #if defined(CONFIG_BT_A2DP_SINK) @@ -537,12 +542,12 @@ static int bt_a2dp_get_capabilities_cb(struct bt_avdtp_req *req, struct net_buf uint8_t codec_type; uint8_t user_ret; - if (GET_CAP_REQ(req) != &a2dp->get_capabilities_param || buf == NULL) { + if (GET_CAP_REQ(req) != &a2dp->get_capabilities_param) { return -EINVAL; } LOG_DBG("GET CAPABILITIES result:%d", req->status); - if (req->status) { + if ((req->status != 0) || (buf == NULL)) { if ((a2dp->discover_cb_param != NULL) && (a2dp->discover_cb_param->cb != NULL)) { a2dp->discover_cb_param->cb(a2dp, NULL, NULL); a2dp->discover_cb_param = NULL; @@ -613,6 +618,17 @@ static int bt_a2dp_get_sep_caps(struct bt_a2dp *a2dp) a2dp->get_capabilities_param.req.func = bt_a2dp_get_capabilities_cb; a2dp->get_capabilities_param.stream_endpoint_id = a2dp->discover_cb_param->seps_info[a2dp->get_cap_index].id; + + /* The legacy Get Capabilities procedure is deprecated in cases + * where backwards compatibility with AVDTP 1.2 and earlier is irrelevant. + */ + if (AVDTP_VERSION >= AVDTP_VERSION_1_3 && + a2dp->discover_cb_param->avdtp_version >= AVDTP_VERSION_1_3) { + a2dp->get_capabilities_param.get_all_caps = true; + } else { + a2dp->get_capabilities_param.get_all_caps = false; + } + err = bt_avdtp_get_capabilities(&a2dp->session, &a2dp->get_capabilities_param); @@ -635,13 +651,13 @@ static int bt_a2dp_discover_cb(struct bt_avdtp_req *req, struct net_buf *buf) int err; LOG_DBG("DISCOVER result:%d", req->status); - if (a2dp->discover_cb_param == NULL || buf == NULL) { + if (a2dp->discover_cb_param == NULL) { return -EINVAL; } a2dp->peer_seps_count = 0U; - if (!(req->status)) { + if ((req->status == 0) && (buf != NULL)) { if (a2dp->discover_cb_param->sep_count == 0) { if (a2dp->discover_cb_param->cb != NULL) { a2dp->discover_cb_param->cb(a2dp, NULL, NULL); @@ -699,7 +715,6 @@ int bt_a2dp_discover(struct bt_a2dp *a2dp, struct bt_a2dp_discover_param *param) return -EBUSY; } - memset(&a2dp->discover_cb_param, 0U, sizeof(a2dp->discover_cb_param)); a2dp->discover_cb_param = param; a2dp->discover_param.req.func = bt_a2dp_discover_cb; diff --git a/subsys/bluetooth/host/classic/avctp.c b/subsys/bluetooth/host/classic/avctp.c index 939361552b577..eb5d9ce48b6cf 100644 --- a/subsys/bluetooth/host/classic/avctp.c +++ b/subsys/bluetooth/host/classic/avctp.c @@ -31,8 +31,9 @@ LOG_MODULE_REGISTER(bt_avctp); #define AVCTP_CHAN(_ch) CONTAINER_OF(_ch, struct bt_avctp, br_chan.chan) - -static const struct bt_avctp_event_cb *event_cb; +/* L2CAP Server list */ +static sys_slist_t avctp_l2cap_server = SYS_SLIST_STATIC_INIT(&avctp_l2cap_server); +static struct k_sem avctp_server_lock; static void avctp_l2cap_connected(struct bt_l2cap_chan *chan) { @@ -80,7 +81,6 @@ static int avctp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) struct bt_avctp *session = AVCTP_CHAN(chan); struct bt_avctp_header *hdr = (void *)buf->data; uint8_t tid; - bt_avctp_pkt_type_t pkt_type; bt_avctp_cr_t cr; int err; @@ -90,46 +90,34 @@ static int avctp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) } tid = BT_AVCTP_HDR_GET_TRANSACTION_LABLE(hdr); - pkt_type = BT_AVCTP_HDR_GET_PACKET_TYPE(hdr); cr = BT_AVCTP_HDR_GET_CR(hdr); - switch (pkt_type) { - case BT_AVCTP_PKT_TYPE_SINGLE: - break; - case BT_AVCTP_PKT_TYPE_START: - case BT_AVCTP_PKT_TYPE_CONTINUE: - case BT_AVCTP_PKT_TYPE_END: - default: - LOG_ERR("fragmented AVCTP message is not supported, pkt_type = %d", pkt_type); - return -EINVAL; + LOG_DBG("AVCTP msg received, cr:0x%X, tid:0x%X, pid: 0x%04X", + cr, tid, sys_be16_to_cpu(hdr->pid)); + + if (sys_be16_to_cpu(hdr->pid) == session->pid) { + return session->ops->recv(session, buf); } - switch (hdr->pid) { -#if defined(CONFIG_BT_AVRCP) - case sys_cpu_to_be16(BT_SDP_AV_REMOTE_SVCLASS): - break; -#endif - default: - LOG_ERR("unsupported AVCTP PID received: 0x%04x", sys_be16_to_cpu(hdr->pid)); - if (cr == BT_AVCTP_CMD) { - rsp = bt_avctp_create_pdu(session, BT_AVCTP_RESPONSE, - BT_AVCTP_PKT_TYPE_SINGLE, BT_AVCTP_IPID_INVALID, - tid, hdr->pid); - if (!rsp) { - return -ENOMEM; - } - - err = bt_avctp_send(session, rsp); - if (err < 0) { - net_buf_unref(rsp); - LOG_ERR("AVCTP send fail, err = %d", err); - return err; - } + LOG_ERR("unsupported AVCTP PID received: 0x%04x", sys_be16_to_cpu(hdr->pid)); + if (cr == BT_AVCTP_CMD) { + rsp = bt_avctp_create_pdu(session, BT_AVCTP_RESPONSE, + BT_AVCTP_PKT_TYPE_SINGLE, BT_AVCTP_IPID_INVALID, + tid, hdr->pid); + if (rsp == NULL) { + __ASSERT(0, "Failed to create AVCTP response PDU"); + return -ENOMEM; } - return 0; /* No need to report to the upper layer */ - } - return session->ops->recv(session, buf); + err = bt_avctp_send(session, rsp); + if (err < 0) { + net_buf_unref(rsp); + LOG_ERR("AVCTP send fail, err = %d", err); + bt_avctp_disconnect(session); + return err; + } + } + return 0; /* No need to report to the upper layer */ } static const struct bt_l2cap_chan_ops ops = { @@ -139,17 +127,14 @@ static const struct bt_l2cap_chan_ops ops = { .recv = avctp_l2cap_recv, }; -int bt_avctp_connect(struct bt_conn *conn, struct bt_avctp *session) +int bt_avctp_connect(struct bt_conn *conn, uint16_t psm, struct bt_avctp *session) { if (!session) { return -EINVAL; } - session->br_chan.rx.mtu = BT_L2CAP_RX_MTU; session->br_chan.chan.ops = &ops; - session->br_chan.required_sec_level = BT_SECURITY_L2; - - return bt_l2cap_chan_connect(conn, &session->br_chan.chan, BT_L2CAP_PSM_AVCTP); + return bt_l2cap_chan_connect(conn, &session->br_chan.chan, psm); } int bt_avctp_disconnect(struct bt_avctp *session) @@ -163,6 +148,19 @@ int bt_avctp_disconnect(struct bt_avctp *session) return bt_l2cap_chan_disconnect(&session->br_chan.chan); } +void bt_avctp_set_header(struct bt_avctp_header *avctp_hdr, bt_avctp_cr_t cr, + bt_avctp_pkt_type_t pkt_type, bt_avctp_ipid_t ipid, + uint8_t tid, uint16_t pid) +{ + LOG_DBG(""); + + BT_AVCTP_HDR_SET_TRANSACTION_LABLE(avctp_hdr, tid); + BT_AVCTP_HDR_SET_PACKET_TYPE(avctp_hdr, pkt_type); + BT_AVCTP_HDR_SET_CR(avctp_hdr, cr); + BT_AVCTP_HDR_SET_IPID(avctp_hdr, ipid); + avctp_hdr->pid = pid; +} + struct net_buf *bt_avctp_create_pdu(struct bt_avctp *session, bt_avctp_cr_t cr, bt_avctp_pkt_type_t pkt_type, bt_avctp_ipid_t ipid, uint8_t tid, uint16_t pid) @@ -179,11 +177,7 @@ struct net_buf *bt_avctp_create_pdu(struct bt_avctp *session, bt_avctp_cr_t cr, } hdr = net_buf_add(buf, sizeof(*hdr)); - BT_AVCTP_HDR_SET_TRANSACTION_LABLE(hdr, tid); - BT_AVCTP_HDR_SET_PACKET_TYPE(hdr, pkt_type); - BT_AVCTP_HDR_SET_CR(hdr, cr); - BT_AVCTP_HDR_SET_IPID(hdr, ipid); - hdr->pid = pid; + bt_avctp_set_header(hdr, cr, pkt_type, ipid, tid, pid); LOG_DBG("cr:0x%lX, tid:0x%02lX", BT_AVCTP_HDR_GET_CR(hdr), BT_AVCTP_HDR_GET_TRANSACTION_LABLE(hdr)); @@ -195,63 +189,78 @@ int bt_avctp_send(struct bt_avctp *session, struct net_buf *buf) return bt_l2cap_chan_send(&session->br_chan.chan, buf); } -int bt_avctp_register(const struct bt_avctp_event_cb *cb) -{ - LOG_DBG(""); - - if (event_cb) { - return -EALREADY; - } - - event_cb = cb; - - return 0; -} - static int avctp_l2cap_accept(struct bt_conn *conn, struct bt_l2cap_server *server, struct bt_l2cap_chan **chan) { struct bt_avctp *session = NULL; + struct bt_avctp_server *avctp_server; int err; LOG_DBG("conn %p", conn); - if (!event_cb) { - LOG_WRN("AVCTP server is unsupported"); - return -ENOTSUP; + avctp_server = CONTAINER_OF(server, struct bt_avctp_server, l2cap); + + k_sem_take(&avctp_server_lock, K_FOREVER); + + if (!sys_slist_find(&avctp_l2cap_server, &avctp_server->node, NULL)) { + LOG_WRN("Invalid l2cap server"); + k_sem_give(&avctp_server_lock); + return -EINVAL; } + k_sem_give(&avctp_server_lock); + /* Get the AVCTP session from upper layer */ - err = event_cb->accept(conn, &session); + err = avctp_server->accept(conn, &session); if (err < 0) { - LOG_ERR("Get the AVCTP session failed %d", err); + LOG_ERR("Incoming connection rejected"); return err; } - session->br_chan.rx.mtu = BT_L2CAP_RX_MTU; - session->br_chan.psm = BT_L2CAP_PSM_AVCTP; session->br_chan.chan.ops = &ops; *chan = &session->br_chan.chan; return 0; } -int bt_avctp_init(void) +int bt_avctp_server_register(struct bt_avctp_server *server) { int err; - static struct bt_l2cap_server avctp_l2cap = { - .psm = BT_L2CAP_PSM_AVCTP, - .sec_level = BT_SECURITY_L2, - .accept = avctp_l2cap_accept, - }; - LOG_DBG(""); - /* Register AVCTP PSM with L2CAP */ - err = bt_l2cap_br_server_register(&avctp_l2cap); + if ((server == NULL) || (server->accept == NULL)) { + LOG_DBG("Invalid parameter"); + return -EINVAL; + } + + k_sem_take(&avctp_server_lock, K_FOREVER); + + if (sys_slist_find(&avctp_l2cap_server, &server->node, NULL)) { + LOG_WRN("L2CAP server has been registered"); + k_sem_give(&avctp_server_lock); + return -EEXIST; + } + + server->l2cap.accept = avctp_l2cap_accept; + err = bt_l2cap_br_server_register(&server->l2cap); if (err < 0) { LOG_ERR("AVCTP L2CAP registration failed %d", err); + k_sem_give(&avctp_server_lock); + return err; } + LOG_DBG("Register L2CAP server %p", server); + sys_slist_append(&avctp_l2cap_server, &server->node); + + k_sem_give(&avctp_server_lock); + return err; } + +int bt_avctp_init(void) +{ + LOG_DBG("Initializing AVCTP"); + /* Locking semaphore initialized to 1 (unlocked) */ + k_sem_init(&avctp_server_lock, 1, 1); + return 0; +} diff --git a/subsys/bluetooth/host/classic/avctp_internal.h b/subsys/bluetooth/host/classic/avctp_internal.h index 280622be438a1..a9d3fc5c89e32 100644 --- a/subsys/bluetooth/host/classic/avctp_internal.h +++ b/subsys/bluetooth/host/classic/avctp_internal.h @@ -9,8 +9,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define BT_L2CAP_PSM_AVCTP 0x0017 - typedef enum __packed { BT_AVCTP_IPID_NONE = 0b0, BT_AVCTP_IPID_INVALID = 0b1, @@ -82,6 +80,52 @@ struct bt_avctp_ops_cb { struct bt_avctp { struct bt_l2cap_br_chan br_chan; const struct bt_avctp_ops_cb *ops; + uint16_t pid; /** Profile Identifier */ +}; + +/** + * @brief AVCTP L2CAP Server structure + * + * This structure defines the L2CAP server used for AVCTP over L2CAP transport. + */ +struct bt_avctp_server { + /** + * @brief L2CAP server parameters + * + * This field is used to register the L2CAP server. The `psm` field can be set + * to a specific value (not recommended), or set to 0 to allow automatic PSM + * allocation during registration via @ref bt_avctp_server_register. + * + * The `sec_level` field specifies the minimum required security level. + * + * @note The `struct bt_l2cap_server::accept` callback of `l2cap` can not be used + * by AVCTP applications. Instead, use the `struct bt_avctp_server::accept` + * callback defined in this structure. + */ + struct bt_l2cap_server l2cap; + + /** + * @brief Accept callback for incoming AVCTP connections + * + * This callback is invoked when a new incoming AVCTP connection is received. + * The application is responsible for authorizing the connection and allocating + * a new AVCTP session object. + * + * @warning The caller must ensure that the parent object of the AVCTP session + * is properly zero-initialized before use. + * + * @param conn The Bluetooth connection requesting authorization. + * @param session Pointer to receive the allocated AVCTP session object. + * + * @retval 0 Success. + * @retval -ENOMEM No available space for a new session. + * @retval -EACCES Connection not authorized by the application. + * @retval -EPERM Encryption key size is insufficient. + */ + int (*accept)(struct bt_conn *conn, struct bt_avctp **session); + + /** @brief Internal node for list management */ + sys_snode_t node; }; struct bt_avctp_event_cb { @@ -92,10 +136,10 @@ struct bt_avctp_event_cb { int bt_avctp_init(void); /* Application register with AVCTP layer */ -int bt_avctp_register(const struct bt_avctp_event_cb *cb); +int bt_avctp_server_register(struct bt_avctp_server *server); /* AVCTP connect */ -int bt_avctp_connect(struct bt_conn *conn, struct bt_avctp *session); +int bt_avctp_connect(struct bt_conn *conn, uint16_t psm, struct bt_avctp *session); /* AVCTP disconnect */ int bt_avctp_disconnect(struct bt_avctp *session); @@ -105,5 +149,10 @@ struct net_buf *bt_avctp_create_pdu(struct bt_avctp *session, bt_avctp_cr_t cr, bt_avctp_pkt_type_t pkt_type, bt_avctp_ipid_t ipid, uint8_t tid, uint16_t pid); +/* Set AVCTP header */ +void bt_avctp_set_header(struct bt_avctp_header *avctp_hdr, bt_avctp_cr_t cr, + bt_avctp_pkt_type_t pkt_type, bt_avctp_ipid_t ipid, + uint8_t tid, uint16_t pid); + /* Send AVCTP PDU */ int bt_avctp_send(struct bt_avctp *session, struct net_buf *buf); diff --git a/subsys/bluetooth/host/classic/avdtp.c b/subsys/bluetooth/host/classic/avdtp.c index 082d5ed5ffcf7..65d96aca75aa9 100644 --- a/subsys/bluetooth/host/classic/avdtp.c +++ b/subsys/bluetooth/host/classic/avdtp.c @@ -342,39 +342,55 @@ static struct bt_avdtp_sep *avdtp_get_sep(uint8_t stream_endpoint_id) return sep; } -static struct bt_avdtp_sep *avdtp_get_cmd_sep(struct net_buf *buf, uint8_t *error_code) +static struct bt_avdtp_sep *avdtp_get_cmd_sep(struct net_buf *buf, uint8_t *error_code, + uint8_t *seid) { struct bt_avdtp_sep *sep; + uint8_t id; if (buf->len < 1U) { *error_code = BT_AVDTP_BAD_LENGTH; + LOG_WRN("Malformed packet"); + return NULL; + } + + id = net_buf_pull_u8(buf) >> 2; + if ((id < BT_AVDTP_MIN_SEID) || (id > BT_AVDTP_MAX_SEID)) { + *error_code = BT_AVDTP_BAD_ACP_SEID; LOG_WRN("Invalid ACP SEID"); return NULL; } - sep = avdtp_get_sep(net_buf_pull_u8(buf) >> 2); + if (seid != NULL) { + *seid = id; + } + + sep = avdtp_get_sep(id); return sep; } -static void avdtp_get_capabilities_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid) +static void avdtp_get_caps_cmd_internal(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid, + bool get_all_caps) { int err = 0; struct net_buf *rsp_buf; struct bt_avdtp_sep *sep; uint8_t error_code = 0; - sep = avdtp_get_cmd_sep(buf, &error_code); + sep = avdtp_get_cmd_sep(buf, &error_code, NULL); if ((sep == NULL) || (session->ops->get_capabilities_ind == NULL)) { err = -ENOTSUP; } else { rsp_buf = avdtp_create_reply_pdu(BT_AVDTP_ACCEPT, BT_AVDTP_PACKET_TYPE_SINGLE, + get_all_caps ? BT_AVDTP_GET_ALL_CAPABILITIES : BT_AVDTP_GET_CAPABILITIES, tid); if (!rsp_buf) { return; } - err = session->ops->get_capabilities_ind(session, sep, rsp_buf, &error_code); + err = session->ops->get_capabilities_ind(session, sep, rsp_buf, get_all_caps, + &error_code); if (err) { net_buf_unref(rsp_buf); } @@ -382,6 +398,7 @@ static void avdtp_get_capabilities_cmd(struct bt_avdtp *session, struct net_buf if (err) { rsp_buf = avdtp_create_reply_pdu(BT_AVDTP_REJECT, BT_AVDTP_PACKET_TYPE_SINGLE, + get_all_caps ? BT_AVDTP_GET_ALL_CAPABILITIES : BT_AVDTP_GET_CAPABILITIES, tid); if (!rsp_buf) { return; @@ -403,6 +420,17 @@ static void avdtp_get_capabilities_cmd(struct bt_avdtp *session, struct net_buf } } +static void avdtp_get_capabilities_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid) +{ + avdtp_get_caps_cmd_internal(session, buf, tid, false); +} + +static void avdtp_get_all_capabilities_cmd(struct bt_avdtp *session, + struct net_buf *buf, uint8_t tid) +{ + avdtp_get_caps_cmd_internal(session, buf, tid, true); +} + static void avdtp_get_capabilities_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type) { @@ -421,6 +449,99 @@ static void avdtp_get_capabilities_rsp(struct bt_avdtp *session, struct net_buf } } +struct bt_avdtp_service_category_handler { + uint8_t min_len; + uint8_t max_len; + bool reconfig_support; + uint8_t err_code; + uint8_t (*handler)(struct net_buf *buf); +}; + +uint8_t bt_avdtp_check_media_recovery_type(struct net_buf *buf) +{ + struct bt_avdtp_recovery_capabilities *cap + = (struct bt_avdtp_recovery_capabilities *)buf->data; + + if (cap->recovery_type != BT_AVDTP_RECOVERY_TYPE_FORBIDDEN && + cap->recovery_type != BT_ADVTP_RECOVERY_TYPE_RFC2733) { + return BT_AVDTP_BAD_RECOVERY_TYPE; + } + return BT_AVDTP_SUCCESS; +} + +static struct bt_avdtp_service_category_handler category_handler[] = { + {0, 0, false, 0, NULL}, /*None*/ + {0, 0, false, BT_AVDTP_BAD_MEDIA_TRANSPORT_FORMAT, + NULL}, /*BT_AVDTP_SERVICE_MEDIA_TRANSPORT*/ + {0, 0, false, BT_AVDTP_BAD_LENGTH, NULL}, /*BT_AVDTP_SERVICE_REPORTING*/ + {sizeof(struct bt_avdtp_recovery_capabilities), + sizeof(struct bt_avdtp_recovery_capabilities), false, BT_AVDTP_BAD_RECOVERY_FORMAT, + bt_avdtp_check_media_recovery_type}, /*BT_AVDTP_SERVICE_MEDIA_RECOVERY*/ + {sizeof(struct bt_avdtp_content_protection_capabilities), UINT8_MAX, + true, BT_AVDTP_BAD_CP_FORMAT, NULL}, /*BT_AVDTP_SERVICE_CONTENT_PROTECTION*/ + {sizeof(struct bt_avdtp_header_compression_capabilities), + sizeof(struct bt_avdtp_header_compression_capabilities), + false, BT_AVDTP_BAD_LENGTH, NULL}, /*BT_AVDTP_SERVICE_HEADER_COMPRESSION*/ + {sizeof(struct bt_avdtp_multiplexing_capabilities), + sizeof(struct bt_avdtp_multiplexing_capabilities), + false, BT_AVDTP_BAD_MULTIPLEXING_FORMAT, NULL}, /*BT_AVDTP_SERVICE_MULTIPLEXING*/ + {sizeof(struct bt_avdtp_media_codec_capabilities), UINT8_MAX, + true, BT_AVDTP_BAD_LENGTH, NULL}, /*BT_AVDTP_SERVICE_MEDIA_CODEC*/ + {0, 0, 0, BT_AVDTP_BAD_LENGTH, NULL}, /*BT_AVDTP_SERVICE_DELAY_REPORTING*/ +}; + +uint8_t bt_avdtp_check_service_category(struct net_buf *buf, uint8_t *service_category, + bool reconfig) +{ + struct bt_avdtp_generic_service_cap *hdr; + uint8_t err; + struct bt_avdtp_service_category_handler *handler; + struct net_buf_simple_state state; + + if (buf->len == 0U) { + LOG_DBG("Error: buf not valid"); + return BT_AVDTP_BAD_LENGTH; + } + + while (buf->len > 0U) { + if (buf->len < sizeof(*hdr)) { + LOG_DBG("Error: buf not valid"); + return BT_AVDTP_BAD_LENGTH; + } + + hdr = net_buf_pull_mem(buf, sizeof(*hdr)); + *service_category = hdr->service_category; + + if (hdr->service_category != 0 && + hdr->service_category < ARRAY_SIZE(category_handler)) { + handler = &category_handler[hdr->service_category]; + + if (hdr->losc > buf->len || hdr->losc > handler->max_len || + hdr->losc < handler->min_len) { + return handler->err_code; + } + + if (!handler->reconfig_support && reconfig) { + return BT_AVDTP_INVALID_CAPABILITIES; + } + + if (handler->handler != NULL) { + net_buf_simple_save(&buf->b, &state); + err = handler->handler(buf); + net_buf_simple_restore(&buf->b, &state); + if (err != BT_AVDTP_SUCCESS) { + return err; + } + } + net_buf_pull_mem(buf, hdr->losc); + } else { + return BT_AVDTP_BAD_SERV_CATEGORY; + } + } + + return BT_AVDTP_SUCCESS; +} + static void avdtp_process_configuration_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid, bool reconfig) { @@ -428,8 +549,10 @@ static void avdtp_process_configuration_cmd(struct bt_avdtp *session, struct net struct bt_avdtp_sep *sep; struct net_buf *rsp_buf; uint8_t avdtp_err_code = 0; + struct net_buf_simple_state state; + uint8_t service_category = 0; - sep = avdtp_get_cmd_sep(buf, &avdtp_err_code); + sep = avdtp_get_cmd_sep(buf, &avdtp_err_code, NULL); avdtp_sep_lock(sep); if (sep == NULL) { @@ -438,6 +561,9 @@ static void avdtp_process_configuration_cmd(struct bt_avdtp *session, struct net err = -ENOTSUP; } else if (reconfig && session->ops->re_configuration_ind == NULL) { err = -ENOTSUP; + } else if (!reconfig && sep->sep_info.inuse == 1) { + avdtp_err_code = BT_AVDTP_SEP_IN_USE; + err = -EBUSY; } else { uint8_t expected_state; @@ -451,17 +577,29 @@ static void avdtp_process_configuration_cmd(struct bt_avdtp *session, struct net err = -ENOTSUP; avdtp_err_code = BT_AVDTP_BAD_STATE; } else if (buf->len >= 1U) { - uint8_t int_seid; + uint8_t int_seid = 0; + uint8_t err_code = 0; /* INT Stream Endpoint ID */ - int_seid = net_buf_pull_u8(buf) >> 2; - if (!reconfig) { - err = session->ops->set_configuration_ind(session, sep, int_seid, - buf, &avdtp_err_code); + /* int seid not in reconfig cmd*/ + int_seid = net_buf_pull_u8(buf) >> 2; + } + net_buf_simple_save(&buf->b, &state); + err_code = bt_avdtp_check_service_category(buf, &service_category, + reconfig); + net_buf_simple_restore(&buf->b, &state); + if (err_code) { + avdtp_err_code = err_code; + err = -ENOTSUP; } else { - err = session->ops->re_configuration_ind(session, sep, int_seid, - buf, &avdtp_err_code); + if (!reconfig) { + err = session->ops->set_configuration_ind( + session, sep, int_seid, buf, &avdtp_err_code); + } else { + err = session->ops->re_configuration_ind(session, sep, buf, + &avdtp_err_code); + } } } else { LOG_WRN("Invalid INT SEID"); @@ -484,8 +622,8 @@ static void avdtp_process_configuration_cmd(struct bt_avdtp *session, struct net } LOG_DBG("set configuration err code:%d", avdtp_err_code); - /* Service Category: Media Codec */ - net_buf_add_u8(rsp_buf, BT_AVDTP_SERVICE_MEDIA_CODEC); + /* error Service Category*/ + net_buf_add_u8(rsp_buf, service_category); /* ERROR CODE */ net_buf_add_u8(rsp_buf, avdtp_err_code); } @@ -567,7 +705,7 @@ static void avdtp_open_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_ struct net_buf *rsp_buf; uint8_t avdtp_err_code = 0; - sep = avdtp_get_cmd_sep(buf, &avdtp_err_code); + sep = avdtp_get_cmd_sep(buf, &avdtp_err_code, NULL); avdtp_sep_lock(sep); if ((sep == NULL) || (session->ops->open_ind == NULL)) { @@ -662,8 +800,10 @@ static void avdtp_start_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8 struct bt_avdtp_sep *sep; struct net_buf *rsp_buf; uint8_t avdtp_err_code = 0; + uint8_t acp_seid = 0; + + sep = avdtp_get_cmd_sep(buf, &avdtp_err_code, &acp_seid); - sep = avdtp_get_cmd_sep(buf, &avdtp_err_code); avdtp_sep_lock(sep); if ((sep == NULL) || (session->ops->start_ind == NULL)) { @@ -690,6 +830,7 @@ static void avdtp_start_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8 } LOG_DBG("start err code:%d", avdtp_err_code); + net_buf_add_u8(rsp_buf, acp_seid); net_buf_add_u8(rsp_buf, avdtp_err_code); } @@ -740,7 +881,7 @@ static void avdtp_close_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8 struct net_buf *rsp_buf; uint8_t avdtp_err_code = 0; - sep = avdtp_get_cmd_sep(buf, &avdtp_err_code); + sep = avdtp_get_cmd_sep(buf, &avdtp_err_code, NULL); avdtp_sep_lock(sep); if ((sep == NULL) || (session->ops->close_ind == NULL)) { @@ -817,8 +958,9 @@ static void avdtp_suspend_cmd(struct bt_avdtp *session, struct net_buf *buf, uin struct bt_avdtp_sep *sep; struct net_buf *rsp_buf; uint8_t avdtp_err_code = 0; + uint8_t acp_seid = 0; - sep = avdtp_get_cmd_sep(buf, &avdtp_err_code); + sep = avdtp_get_cmd_sep(buf, &avdtp_err_code, &acp_seid); avdtp_sep_lock(sep); if ((sep == NULL) || (session->ops->suspend_ind == NULL)) { @@ -845,6 +987,7 @@ static void avdtp_suspend_cmd(struct bt_avdtp *session, struct net_buf *buf, uin } LOG_DBG("suspend err code:%d", avdtp_err_code); + net_buf_add_u8(rsp_buf, acp_seid); net_buf_add_u8(rsp_buf, avdtp_err_code); } @@ -895,7 +1038,7 @@ static void avdtp_abort_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8 struct net_buf *rsp_buf; uint8_t avdtp_err_code = 0; - sep = avdtp_get_cmd_sep(buf, &avdtp_err_code); + sep = avdtp_get_cmd_sep(buf, &avdtp_err_code, NULL); avdtp_sep_lock(sep); if ((sep == NULL) || (session->ops->abort_ind == NULL)) { @@ -1103,19 +1246,19 @@ void bt_avdtp_l2cap_disconnected(struct bt_l2cap_chan *chan) } void (*cmd_handler[])(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid) = { - avdtp_discover_cmd, /* BT_AVDTP_DISCOVER */ - avdtp_get_capabilities_cmd, /* BT_AVDTP_GET_CAPABILITIES */ - avdtp_set_configuration_cmd, /* BT_AVDTP_SET_CONFIGURATION */ - NULL, /* BT_AVDTP_GET_CONFIGURATION */ - avdtp_re_configure_cmd, /* BT_AVDTP_RECONFIGURE */ - avdtp_open_cmd, /* BT_AVDTP_OPEN */ - avdtp_start_cmd, /* BT_AVDTP_START */ - avdtp_close_cmd, /* BT_AVDTP_CLOSE */ - avdtp_suspend_cmd, /* BT_AVDTP_SUSPEND */ - avdtp_abort_cmd, /* BT_AVDTP_ABORT */ - NULL, /* BT_AVDTP_SECURITY_CONTROL */ - NULL, /* BT_AVDTP_GET_ALL_CAPABILITIES */ - NULL, /* BT_AVDTP_DELAYREPORT */ + avdtp_discover_cmd, /* BT_AVDTP_DISCOVER */ + avdtp_get_capabilities_cmd, /* BT_AVDTP_GET_CAPABILITIES */ + avdtp_set_configuration_cmd, /* BT_AVDTP_SET_CONFIGURATION */ + NULL, /* BT_AVDTP_GET_CONFIGURATION */ + avdtp_re_configure_cmd, /* BT_AVDTP_RECONFIGURE */ + avdtp_open_cmd, /* BT_AVDTP_OPEN */ + avdtp_start_cmd, /* BT_AVDTP_START */ + avdtp_close_cmd, /* BT_AVDTP_CLOSE */ + avdtp_suspend_cmd, /* BT_AVDTP_SUSPEND */ + avdtp_abort_cmd, /* BT_AVDTP_ABORT */ + NULL, /* BT_AVDTP_SECURITY_CONTROL */ + avdtp_get_all_capabilities_cmd, /* BT_AVDTP_GET_ALL_CAPABILITIES */ + NULL, /* BT_AVDTP_DELAYREPORT */ }; void (*rsp_handler[])(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type) = { @@ -1130,7 +1273,7 @@ void (*rsp_handler[])(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg avdtp_suspend_rsp, /* BT_AVDTP_SUSPEND */ avdtp_abort_rsp, /* BT_AVDTP_ABORT */ NULL, /* BT_AVDTP_SECURITY_CONTROL */ - NULL, /* BT_AVDTP_GET_ALL_CAPABILITIES */ + avdtp_get_capabilities_rsp, /* BT_AVDTP_GET_ALL_CAPABILITIES */ NULL, /* BT_AVDTP_DELAYREPORT */ }; @@ -1193,7 +1336,7 @@ int bt_avdtp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) } if (sigid != 0U && sigid <= BT_AVDTP_DELAYREPORT && - cmd_handler[sigid - 1U] != NULL) { + rsp_handler[sigid - 1U] != NULL) { rsp_handler[sigid - 1U](session, buf, msgtype); return 0; } @@ -1342,6 +1485,12 @@ int bt_avdtp_register_sep(uint8_t media_type, uint8_t sep_type, struct bt_avdtp_ } k_sem_take(&avdtp_sem_lock, K_FOREVER); + if (sys_slist_find(&seps, &sep->_node, NULL)) { + k_sem_give(&avdtp_sem_lock); + LOG_ERR("Endpoint is already registered"); + return -EEXIST; + } + /* the id allocation need be locked to protect it */ sep->sep_info.id = bt_avdtp_sep++; sep->sep_info.inuse = 0U; @@ -1436,6 +1585,7 @@ int bt_avdtp_get_capabilities(struct bt_avdtp *session, } buf = avdtp_create_pdu(BT_AVDTP_CMD, BT_AVDTP_PACKET_TYPE_SINGLE, + param->get_all_caps ? BT_AVDTP_GET_ALL_CAPABILITIES : BT_AVDTP_GET_CAPABILITIES); if (!buf) { LOG_ERR("Error: No Buff available"); @@ -1539,12 +1689,14 @@ static int avdtp_process_configure_command(struct bt_avdtp *session, uint8_t cmd /* Body of the message */ /* ACP Stream Endpoint ID */ net_buf_add_u8(buf, (param->acp_stream_ep_id << 2U)); - /* INT Stream Endpoint ID */ - net_buf_add_u8(buf, (param->int_stream_endpoint_id << 2U)); - /* Service Category: Media Transport */ - net_buf_add_u8(buf, BT_AVDTP_SERVICE_MEDIA_TRANSPORT); - /* LOSC */ - net_buf_add_u8(buf, 0); + if (cmd == BT_AVDTP_SET_CONFIGURATION) { + /* INT Stream Endpoint ID */ + net_buf_add_u8(buf, (param->int_stream_endpoint_id << 2U)); + /* Service Category: Media Transport */ + net_buf_add_u8(buf, BT_AVDTP_SERVICE_MEDIA_TRANSPORT); + /* LOSC */ + net_buf_add_u8(buf, 0); + } /* Service Category: Media Codec */ net_buf_add_u8(buf, BT_AVDTP_SERVICE_MEDIA_CODEC); /* LOSC */ diff --git a/subsys/bluetooth/host/classic/avdtp_internal.h b/subsys/bluetooth/host/classic/avdtp_internal.h index 368dba6c278f0..6af196dcfb089 100644 --- a/subsys/bluetooth/host/classic/avdtp_internal.h +++ b/subsys/bluetooth/host/classic/avdtp_internal.h @@ -153,6 +153,7 @@ struct bt_avdtp_discover_params { struct bt_avdtp_get_capabilities_params { struct bt_avdtp_req req; uint8_t stream_endpoint_id; + bool get_all_caps; }; struct bt_avdtp_set_configuration_params { @@ -173,6 +174,54 @@ struct bt_avdtp_ctrl_params { uint8_t acp_stream_ep_id; }; +struct bt_avdtp_generic_service_cap { + uint8_t service_category; + uint8_t losc; +} __packed; + +/* avdtp service capabilities*/ +struct bt_avdtp_recovery_capabilities { + uint8_t recovery_type; + uint8_t MRWS; + uint8_t MNMP; +} __packed; + +struct bt_avdtp_media_codec_capabilities { + uint8_t media_type; + uint8_t media_code_type; + uint8_t media_codec_spec_info[]; +} __packed; + +struct bt_avdtp_content_protection_capabilities { + uint8_t cp_type_lsb; + uint8_t cp_type_msb; + uint8_t cp_type_spec_value[]; +} __packed; + +struct bt_avdtp_header_compression_capabilities { +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t reserved : 5; + uint8_t recovery : 1; + uint8_t media : 1; + uint8_t backch : 1; +#else + uint8_t backch : 1; + uint8_t media : 1; + uint8_t recovery : 1; + uint8_t reserved : 5; +#endif /* CONFIG_LITTLE_ENDIAN */ +} __packed; + +struct bt_avdtp_multiplexing_capabilities { + uint8_t frag; + uint8_t tsid_media; + uint8_t tcid_media; + uint8_t tsid_reporting; + uint8_t tcid_reporting; + uint8_t tsid_recovery; + uint8_t tcid_recovery; +} __packed; + struct bt_avdtp_ops_cb { void (*connected)(struct bt_avdtp *session); @@ -183,13 +232,13 @@ struct bt_avdtp_ops_cb { int (*discovery_ind)(struct bt_avdtp *session, uint8_t *errcode); int (*get_capabilities_ind)(struct bt_avdtp *session, struct bt_avdtp_sep *sep, - struct net_buf *rsp_buf, uint8_t *errcode); + struct net_buf *rsp_buf, bool get_all_caps, uint8_t *errcode); int (*set_configuration_ind)(struct bt_avdtp *session, struct bt_avdtp_sep *sep, uint8_t int_seid, struct net_buf *buf, uint8_t *errcode); int (*re_configuration_ind)(struct bt_avdtp *session, struct bt_avdtp_sep *sep, - uint8_t int_seid, struct net_buf *buf, uint8_t *errcode); + struct net_buf *buf, uint8_t *errcode); int (*open_ind)(struct bt_avdtp *session, struct bt_avdtp_sep *sep, uint8_t *errcode); diff --git a/subsys/bluetooth/host/classic/avrcp.c b/subsys/bluetooth/host/classic/avrcp.c index 16ba1bdc3ee69..be67a3566530d 100644 --- a/subsys/bluetooth/host/classic/avrcp.c +++ b/subsys/bluetooth/host/classic/avrcp.c @@ -35,6 +35,8 @@ struct bt_avrcp { struct bt_avctp session; /* ACL connection handle */ struct bt_conn *acl_conn; + + struct bt_avctp browsing_session; }; struct bt_avrcp_ct { @@ -50,7 +52,14 @@ struct avrcp_handler { void (*func)(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf); }; +struct avrcp_pdu_handler { + bt_avrcp_pdu_id_t pdu_id; + uint8_t min_len; + int (*func)(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf); +}; + #define AVRCP_AVCTP(_avctp) CONTAINER_OF(_avctp, struct bt_avrcp, session) +#define AVRCP_BROW_AVCTP(_avctp) CONTAINER_OF(_avctp, struct bt_avrcp, browsing_session) /* * This macros returns true if the CT/TG has been initialized, which @@ -66,6 +75,10 @@ static struct bt_avrcp avrcp_connection[CONFIG_BT_MAX_CONN]; static struct bt_avrcp_ct bt_avrcp_ct_pool[CONFIG_BT_MAX_CONN]; static struct bt_avrcp_tg bt_avrcp_tg_pool[CONFIG_BT_MAX_CONN]; +static struct bt_avctp_server avctp_server; +#if defined(CONFIG_BT_AVRCP_BROWSING) +static struct bt_avctp_server avctp_browsing_server; +#endif /* CONFIG_BT_AVRCP_BROWSING */ #if defined(CONFIG_BT_AVRCP_TARGET) static struct bt_sdp_attribute avrcp_tg_attrs[] = { BT_SDP_NEW_SERVICE, @@ -108,7 +121,42 @@ static struct bt_sdp_attribute avrcp_tg_attrs[] = { }, ) ), - /* C1: Browsing not supported */ + /* Browsing channel */ +#if defined(CONFIG_BT_AVRCP_BROWSING) + BT_SDP_LIST( + BT_SDP_ATTR_ADD_PROTO_DESC_LIST, + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 18), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 16), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE(BT_SDP_UUID16), + BT_SDP_ARRAY_16(BT_SDP_PROTO_L2CAP) + }, + { + BT_SDP_TYPE_SIZE(BT_SDP_UINT16), + BT_SDP_ARRAY_16(BT_L2CAP_PSM_AVRCP_BROWSING) + }) + }, + { + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE(BT_SDP_UUID16), + BT_SDP_ARRAY_16(BT_UUID_AVCTP_VAL) + }, + { + BT_SDP_TYPE_SIZE(BT_SDP_UINT16), + BT_SDP_ARRAY_16(AVCTP_VER_1_4) + }) + }) + }) + ), +#endif /* CONFIG_BT_AVRCP_BROWSING */ /* C2: Cover Art not supported */ BT_SDP_LIST( BT_SDP_ATTR_PROFILE_DESC_LIST, @@ -129,7 +177,7 @@ static struct bt_sdp_attribute avrcp_tg_attrs[] = { }, ) ), - BT_SDP_SUPPORTED_FEATURES(AVRCP_CAT_1 | AVRCP_CAT_2), + BT_SDP_SUPPORTED_FEATURES(AVRCP_CAT_1 | AVRCP_CAT_2 | AVRCP_BROWSING_ENABLE), /* O: Provider Name not presented */ BT_SDP_SERVICE_NAME("AVRCP Target"), }; @@ -186,7 +234,43 @@ static struct bt_sdp_attribute avrcp_ct_attrs[] = { }, ) ), - /* C1: Browsing not supported */ + /* Browsing channel */ +#if defined(CONFIG_BT_AVRCP_BROWSING) + BT_SDP_LIST( + BT_SDP_ATTR_ADD_PROTO_DESC_LIST, + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 18), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 16), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE(BT_SDP_UUID16), + BT_SDP_ARRAY_16(BT_SDP_PROTO_L2CAP) + }, + { + BT_SDP_TYPE_SIZE(BT_SDP_UINT16), + BT_SDP_ARRAY_16(BT_L2CAP_PSM_AVRCP_BROWSING) + }) + }, + { + BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6), + BT_SDP_DATA_ELEM_LIST( + { + BT_SDP_TYPE_SIZE(BT_SDP_UUID16), + BT_SDP_ARRAY_16(BT_UUID_AVCTP_VAL) + }, + { + BT_SDP_TYPE_SIZE(BT_SDP_UINT16), + BT_SDP_ARRAY_16(AVCTP_VER_1_4) + }) + }) + }) + ), +#endif /* CONFIG_BT_AVRCP_BROWSING */ + /* C2: Cover Art not supported */ BT_SDP_LIST( BT_SDP_ATTR_PROFILE_DESC_LIST, BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 8), @@ -206,8 +290,7 @@ static struct bt_sdp_attribute avrcp_ct_attrs[] = { }, ) ), - BT_SDP_SUPPORTED_FEATURES(AVRCP_CAT_1 | AVRCP_CAT_2), - /* O: Provider Name not presented */ + BT_SDP_SUPPORTED_FEATURES(AVRCP_CAT_1 | AVRCP_CAT_2 | AVRCP_BROWSING_ENABLE), BT_SDP_SERVICE_NAME("AVRCP Controller"), }; @@ -410,6 +493,34 @@ static int avrcp_send(struct bt_avrcp *avrcp, struct net_buf *buf) return 0; } +static struct net_buf *avrcp_create_browsing_pdu(struct bt_avrcp *avrcp, uint8_t tid, + bt_avctp_cr_t cr) +{ + return bt_avctp_create_pdu(&(avrcp->browsing_session), cr, BT_AVCTP_PKT_TYPE_SINGLE, + BT_AVCTP_IPID_NONE, tid, + sys_cpu_to_be16(BT_SDP_AV_REMOTE_SVCLASS)); +} + +static int avrcp_browsing_send(struct bt_avrcp *avrcp, struct net_buf *buf) +{ + int err; + struct bt_avctp_header *avctp_hdr = (struct bt_avctp_header *)(buf->data); + struct bt_avrcp_avc_brow_pdu *hdr = + (struct bt_avrcp_avc_brow_pdu *)(buf->data + sizeof(*avctp_hdr)); + uint8_t tid = BT_AVCTP_HDR_GET_TRANSACTION_LABLE(avctp_hdr); + bt_avctp_cr_t cr = BT_AVCTP_HDR_GET_CR(avctp_hdr); + + LOG_DBG("AVRCP browsing send cr:0x%X, tid:0x%X, pdu_id:0x%02X\n", cr, tid, + hdr->pdu_id); + err = bt_avctp_send(&(avrcp->browsing_session), buf); + if (err < 0) { + LOG_ERR("AVCTP browsing send fail, err = %d", err); + return err; + } + + return 0; +} + static int bt_avrcp_send_unit_info_err_rsp(struct bt_avrcp *avrcp, uint8_t tid) { struct net_buf *buf; @@ -701,6 +812,15 @@ static int avrcp_recv(struct bt_avctp *session, struct net_buf *buf) return 0; } +static void init_avctp_control_channel(struct bt_avctp *session) +{ + LOG_DBG("session %p", session); + + session->br_chan.rx.mtu = BT_L2CAP_RX_MTU; + session->br_chan.required_sec_level = BT_SECURITY_L2; + session->pid = BT_SDP_AV_REMOTE_SVCLASS; +} + static const struct bt_avctp_ops_cb avctp_ops = { .connected = avrcp_connected, .disconnected = avrcp_disconnected, @@ -720,6 +840,7 @@ static int avrcp_accept(struct bt_conn *conn, struct bt_avctp **session) return -EALREADY; } + init_avctp_control_channel(&(avrcp->session)); *session = &(avrcp->session); avrcp->session.ops = &avctp_ops; avrcp->acl_conn = bt_conn_ref(conn); @@ -729,21 +850,235 @@ static int avrcp_accept(struct bt_conn *conn, struct bt_avctp **session) return 0; } -static struct bt_avctp_event_cb avctp_cb = { - .accept = avrcp_accept, +#if defined(CONFIG_BT_AVRCP_BROWSING) +static void init_avctp_browsing_channel(struct bt_avctp *session) +{ + LOG_DBG("session %p", session); + + session->br_chan.rx.mtu = BT_L2CAP_RX_MTU; + session->br_chan.required_sec_level = BT_SECURITY_L2; + session->br_chan.rx.optional = false; + session->br_chan.rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE; + session->br_chan.rx.max_transmit = 3; + session->br_chan.rx.mode = BT_L2CAP_BR_LINK_MODE_ERET; + session->br_chan.tx.monitor_timeout = CONFIG_BT_L2CAP_BR_MONITOR_TIMEOUT; + session->pid = BT_SDP_AV_REMOTE_SVCLASS; +} + +/* The AVCTP L2CAP channel established */ +static void browsing_avrcp_connected(struct bt_avctp *session) +{ + struct bt_avrcp *avrcp = AVRCP_BROW_AVCTP(session); + + if ((avrcp_ct_cb != NULL) && (avrcp_ct_cb->browsing_connected != NULL)) { + avrcp_ct_cb->browsing_connected(session->br_chan.chan.conn, get_avrcp_ct(avrcp)); + } + + if ((avrcp_tg_cb != NULL) && (avrcp_tg_cb->browsing_connected != NULL)) { + avrcp_tg_cb->browsing_connected(session->br_chan.chan.conn, get_avrcp_tg(avrcp)); + } +} + +/* The AVCTP L2CAP channel released */ +static void browsing_avrcp_disconnected(struct bt_avctp *session) +{ + struct bt_avrcp *avrcp = AVRCP_BROW_AVCTP(session); + + if ((avrcp_ct_cb != NULL) && (avrcp_ct_cb->disconnected != NULL)) { + avrcp_ct_cb->browsing_disconnected(get_avrcp_ct(avrcp)); + } + if ((avrcp_tg_cb != NULL) && (avrcp_tg_cb->disconnected != NULL)) { + avrcp_tg_cb->browsing_disconnected(get_avrcp_tg(avrcp)); + } +} + +static int avrcp_ct_handle_set_browsed_player(struct bt_avrcp *avrcp, + uint8_t tid, struct net_buf *buf) +{ + if ((avrcp_ct_cb == NULL) || (avrcp_ct_cb->browsed_player_rsp == NULL)) { + return -EINVAL; + } + + avrcp_ct_cb->browsed_player_rsp(get_avrcp_ct(avrcp), tid, buf); + + return 0; +} + +static const struct avrcp_pdu_handler rsp_brow_handlers[] = { + {BT_AVRCP_PDU_ID_SET_BROWSED_PLAYER, sizeof(struct bt_avrcp_set_browsed_player_rsp), + avrcp_ct_handle_set_browsed_player}, +}; + +static int avrcp_tg_handle_set_browsed_player_req(struct bt_avrcp *avrcp, + uint8_t tid, struct net_buf *buf) +{ + uint16_t player_id; + struct net_buf *rsp_buf; + int err; + + if ((avrcp_tg_cb == NULL) || (avrcp_tg_cb->set_browsed_player_req == NULL)) { + goto error_rsp; + } + + player_id = net_buf_pull_be16(buf); + + LOG_DBG("Set browsed player request: player_id=0x%04x", player_id); + + avrcp_tg_cb->set_browsed_player_req(get_avrcp_tg(avrcp), tid, player_id); + return 0; + +error_rsp: + rsp_buf = bt_avrcp_create_pdu(NULL); + __ASSERT(rsp_buf != NULL, "Failed to allocate response buffer"); + + if (net_buf_tailroom(rsp_buf) < sizeof(uint8_t)) { + LOG_ERR("Insufficient space in response buffer"); + net_buf_unref(rsp_buf); + return -ENOMEM; + } + net_buf_add_u8(rsp_buf, BT_AVRCP_STATUS_INTERNAL_ERROR); + + err = bt_avrcp_tg_send_set_browsed_player_rsp(get_avrcp_tg(avrcp), tid, rsp_buf); + if (err < 0) { + LOG_ERR("Failed to send browsed player error response (err: %d)", err); + net_buf_unref(rsp_buf); + } + return err; +} + +static const struct avrcp_pdu_handler cmd_brow_handlers[] = { + {BT_AVRCP_PDU_ID_SET_BROWSED_PLAYER, sizeof(uint16_t), + avrcp_tg_handle_set_browsed_player_req}, +}; + +static int handle_pdu(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf, + uint8_t pdu_id, const struct avrcp_pdu_handler *handlers, size_t num_handlers) +{ + for (size_t i = 0; i < num_handlers; i++) { + const struct avrcp_pdu_handler *handler = &handlers[i]; + + if (handler->pdu_id != pdu_id) { + continue; + } + + if (buf->len < handler->min_len) { + LOG_ERR("Too small (%u bytes) pdu_id 0x%02x", buf->len, pdu_id); + return -EINVAL; + } + + return handler->func(avrcp, tid, buf); + } + + return -EOPNOTSUPP; +} + +static int browsing_avrcp_recv(struct bt_avctp *session, struct net_buf *buf) +{ + struct bt_avrcp *avrcp = AVRCP_BROW_AVCTP(session); + struct bt_avctp_header *avctp_hdr; + bt_avctp_pkt_type_t pkt_type; + struct bt_avrcp_avc_brow_pdu *brow; + uint8_t tid; + bt_avctp_cr_t cr; + + if (buf->len < sizeof(*avctp_hdr) + sizeof(struct bt_avrcp_avc_brow_pdu)) { + LOG_ERR("Invalid AVRCP browsing header received: buffer too short (%u)", buf->len); + return -EMSGSIZE; + } + + avctp_hdr = net_buf_pull_mem(buf, sizeof(*avctp_hdr)); + pkt_type = BT_AVCTP_HDR_GET_PACKET_TYPE(avctp_hdr); + tid = BT_AVCTP_HDR_GET_TRANSACTION_LABLE(avctp_hdr); + cr = BT_AVCTP_HDR_GET_CR(avctp_hdr); + + brow = net_buf_pull_mem(buf, sizeof(struct bt_avrcp_avc_brow_pdu)); + + if (pkt_type != BT_AVCTP_PKT_TYPE_SINGLE) { + LOG_ERR("Invalid packet type: 0x%02X", pkt_type); + return -EINVAL; + } + + if (avctp_hdr->pid != sys_cpu_to_be16(BT_SDP_AV_REMOTE_SVCLASS)) { + return -EINVAL; /* Ignore other profile */ + } + + if (buf->len != sys_be16_to_cpu(brow->param_len)) { + LOG_ERR("Invalid AVRCP browsing PDU length: expected %u, got %u", + sys_be16_to_cpu(brow->param_len), buf->len); + return -EMSGSIZE; + } + + LOG_DBG("AVRCP browsing msg received, cr:0x%X, tid:0x%X, pdu_id:0x%02X", cr, + tid, brow->pdu_id); + + if (cr == BT_AVCTP_RESPONSE) { + return handle_pdu(avrcp, tid, buf, brow->pdu_id, rsp_brow_handlers, + ARRAY_SIZE(rsp_brow_handlers)); + } + + return handle_pdu(avrcp, tid, buf, brow->pdu_id, cmd_brow_handlers, + ARRAY_SIZE(cmd_brow_handlers)); +} + +static const struct bt_avctp_ops_cb browsing_avctp_ops = { + .connected = browsing_avrcp_connected, + .disconnected = browsing_avrcp_disconnected, + .recv = browsing_avrcp_recv, }; +static int avrcp_browsing_accept(struct bt_conn *conn, struct bt_avctp **session) +{ + struct bt_avrcp *avrcp; + + avrcp = avrcp_get_connection(conn); + if (avrcp == NULL) { + LOG_ERR("Cannot allocate memory"); + return -ENOTCONN; + } + + if (avrcp->acl_conn == NULL) { + LOG_ERR("The control channel not established"); + return -ENOTCONN; + } + + if (avrcp->browsing_session.br_chan.chan.conn != NULL) { + LOG_ERR("Browsing session already connected"); + return -EALREADY; + } + + init_avctp_browsing_channel(&(avrcp->browsing_session)); + avrcp->browsing_session.ops = &browsing_avctp_ops; + *session = &(avrcp->browsing_session); + + LOG_DBG("browsing_session: %p", &(avrcp->browsing_session)); + + return 0; +} +#endif /* CONFIG_BT_AVRCP_BROWSING */ + int bt_avrcp_init(void) { int err; /* Register event handlers with AVCTP */ - err = bt_avctp_register(&avctp_cb); + avctp_server.l2cap.psm = BT_L2CAP_PSM_AVRCP; + avctp_server.accept = avrcp_accept; + err = bt_avctp_server_register(&avctp_server); if (err < 0) { LOG_ERR("AVRCP registration failed"); return err; } +#if defined(CONFIG_BT_AVRCP_BROWSING) + avctp_browsing_server.l2cap.psm = BT_L2CAP_PSM_AVRCP_BROWSING; + avctp_browsing_server.accept = avrcp_browsing_accept; + err = bt_avctp_server_register(&avctp_browsing_server); + if (err < 0) { + LOG_ERR("AVRCP browsing registration failed"); + return err; + } +#endif /* CONFIG_BT_AVRCP_BROWSING */ + #if defined(CONFIG_BT_AVRCP_TARGET) bt_sdp_register_service(&avrcp_tg_rec); #endif /* CONFIG_BT_AVRCP_CONTROLLER */ @@ -781,7 +1116,8 @@ int bt_avrcp_connect(struct bt_conn *conn) } avrcp->session.ops = &avctp_ops; - err = bt_avctp_connect(conn, &(avrcp->session)); + init_avctp_control_channel(&(avrcp->session)); + err = bt_avctp_connect(conn, BT_L2CAP_PSM_AVRCP, &(avrcp->session)); if (err < 0) { /* If error occurs, undo the saving and return the error */ memset(avrcp, 0, sizeof(struct bt_avrcp)); @@ -805,6 +1141,15 @@ int bt_avrcp_disconnect(struct bt_conn *conn) return -ENOTCONN; } + if (avrcp->browsing_session.br_chan.chan.conn != NULL) { + /* If browsing session is still active, disconnect it first */ + err = bt_avrcp_browsing_disconnect(conn); + if (err < 0) { + LOG_ERR("Browsing session disconnect failed: %d", err); + return err; + } + } + err = bt_avctp_disconnect(&(avrcp->session)); if (err < 0) { LOG_DBG("AVCTP Disconnect failed"); @@ -814,6 +1159,69 @@ int bt_avrcp_disconnect(struct bt_conn *conn) return err; } +struct net_buf *bt_avrcp_create_pdu(struct net_buf_pool *pool) +{ + return bt_conn_create_pdu(pool, + sizeof(struct bt_l2cap_hdr) + + sizeof(struct bt_avctp_header) + + sizeof(struct bt_avrcp_header)); +} + +#if defined(CONFIG_BT_AVRCP_BROWSING) +int bt_avrcp_browsing_connect(struct bt_conn *conn) +{ + struct bt_avrcp *avrcp; + int err; + + avrcp = avrcp_get_connection(conn); + if (avrcp == NULL) { + LOG_ERR("Cannot allocate memory"); + return -ENOTCONN; + } + + if (avrcp->acl_conn == NULL) { + LOG_ERR("The control channel not established"); + return -ENOTCONN; + } + + if (avrcp->browsing_session.br_chan.chan.conn != NULL) { + return -EALREADY; + } + + avrcp->browsing_session.ops = &browsing_avctp_ops; + init_avctp_browsing_channel(&(avrcp->browsing_session)); + err = bt_avctp_connect(conn, BT_L2CAP_PSM_AVRCP_BROWSING, &(avrcp->browsing_session)); + if (err < 0) { + LOG_ERR("AVCTP browsing connect failed"); + return err; + } + + LOG_DBG("Browsing connection request sent"); + + return 0; +} + +int bt_avrcp_browsing_disconnect(struct bt_conn *conn) +{ + int err; + struct bt_avrcp *avrcp; + + avrcp = avrcp_get_connection(conn); + if (avrcp == NULL) { + LOG_ERR("Get avrcp connection failure"); + return -ENOTCONN; + } + + err = bt_avctp_disconnect(&(avrcp->browsing_session)); + if (err < 0) { + LOG_ERR("AVCTP browsing disconnect failed"); + return err; + } + + return err; +} +#endif /* CONFIG_BT_AVRCP_BROWSING */ + int bt_avrcp_ct_get_cap(struct bt_avrcp_ct *ct, uint8_t tid, uint8_t cap_id) { struct net_buf *buf; @@ -919,6 +1327,51 @@ int bt_avrcp_ct_passthrough(struct bt_avrcp_ct *ct, uint8_t tid, uint8_t opid, u return avrcp_send(ct->avrcp, buf); } +#if defined(CONFIG_BT_AVRCP_BROWSING) +int bt_avrcp_ct_set_browsed_player(struct bt_avrcp_ct *ct, uint8_t tid, uint16_t player_id) +{ + struct net_buf *buf; + struct bt_avrcp_avc_brow_pdu *pdu; + int err; + + if ((ct == NULL) || (ct->avrcp == NULL)) { + return -EINVAL; + } + + if (!IS_CT_ROLE_SUPPORTED()) { + return -ENOTSUP; + } + + if (ct->avrcp->browsing_session.br_chan.chan.conn == NULL) { + LOG_ERR("Browsing session not connected"); + return -ENOTCONN; + } + + buf = avrcp_create_browsing_pdu(ct->avrcp, tid, BT_AVCTP_CMD); + if (buf == NULL) { + return -ENOMEM; + } + + if (net_buf_tailroom(buf) < sizeof(*pdu) + sizeof(player_id)) { + LOG_ERR("Not enough tailroom in buffer for browsing PDU"); + net_buf_unref(buf); + return -ENOMEM; + } + + pdu = net_buf_add(buf, sizeof(*pdu)); + pdu->pdu_id = BT_AVRCP_PDU_ID_SET_BROWSED_PLAYER; + pdu->param_len = sys_cpu_to_be16(sizeof(player_id)); + net_buf_add_be16(buf, player_id); + + err = avrcp_browsing_send(ct->avrcp, buf); + if (err < 0) { + LOG_ERR("Failed to send AVRCP browsing PDU (err: %d)", err); + net_buf_unref(buf); + } + return err; +} +#endif /* CONFIG_BT_AVRCP_BROWSING */ + int bt_avrcp_ct_register_cb(const struct bt_avrcp_ct_cb *cb) { if (!cb) { @@ -977,3 +1430,57 @@ int bt_avrcp_tg_send_unit_info_rsp(struct bt_avrcp_tg *tg, uint8_t tid, return avrcp_send(tg->avrcp, buf); } + +#if defined(CONFIG_BT_AVRCP_BROWSING) +int bt_avrcp_tg_send_set_browsed_player_rsp(struct bt_avrcp_tg *tg, uint8_t tid, + struct net_buf *buf) +{ + struct bt_avrcp_avc_brow_pdu *hdr; + struct bt_avctp_header *avctp_hdr; + uint16_t param_len; + int err; + + if ((tg == NULL) || (tg->avrcp == NULL) || (buf == NULL)) { + LOG_ERR("Invalid AVRCP target"); + return -EINVAL; + } + + if (!IS_TG_ROLE_SUPPORTED()) { + LOG_ERR("Target role not supported"); + return -ENOTSUP; + } + + if (tg->avrcp->browsing_session.br_chan.chan.conn == NULL) { + LOG_ERR("Browsing session not connected"); + return -ENOTCONN; + } + + param_len = buf->len; + + if (net_buf_headroom(buf) < sizeof(struct bt_avrcp_avc_brow_pdu)) { + LOG_ERR("Not enough headroom in buffer for bt_avrcp_avc_brow_pdu"); + return -ENOMEM; + } + hdr = net_buf_push(buf, sizeof(struct bt_avrcp_avc_brow_pdu)); + memset(hdr, 0, sizeof(struct bt_avrcp_avc_brow_pdu)); + hdr->pdu_id = BT_AVRCP_PDU_ID_SET_BROWSED_PLAYER; + hdr->param_len = sys_cpu_to_be16(param_len); + + if (net_buf_headroom(buf) < sizeof(struct bt_avctp_header)) { + LOG_ERR("Not enough headroom in buffer for bt_avctp_header"); + return -ENOMEM; + } + avctp_hdr = net_buf_push(buf, sizeof(struct bt_avctp_header)); + memset(avctp_hdr, 0, sizeof(struct bt_avctp_header)); + + bt_avctp_set_header(avctp_hdr, BT_AVCTP_RESPONSE, BT_AVCTP_PKT_TYPE_SINGLE, + BT_AVCTP_IPID_NONE, tid, + sys_cpu_to_be16(BT_SDP_AV_REMOTE_SVCLASS)); + + err = avrcp_browsing_send(tg->avrcp, buf); + if (err < 0) { + LOG_ERR("Failed to send AVRCP browsing PDU (err: %d)", err); + } + return err; +} +#endif /* CONFIG_BT_AVRCP_BROWSING */ diff --git a/subsys/bluetooth/host/classic/avrcp_internal.h b/subsys/bluetooth/host/classic/avrcp_internal.h index d1c84986c4b40..2a14317c30c72 100644 --- a/subsys/bluetooth/host/classic/avrcp_internal.h +++ b/subsys/bluetooth/host/classic/avrcp_internal.h @@ -12,10 +12,15 @@ #define AVCTP_VER_1_4 (0x0104u) #define AVRCP_VER_1_6 (0x0106u) -#define AVRCP_CAT_1 BIT(0) /* Player/Recorder */ -#define AVRCP_CAT_2 BIT(1) /* Monitor/Amplifier */ -#define AVRCP_CAT_3 BIT(2) /* Tuner */ -#define AVRCP_CAT_4 BIT(3) /* Menu */ +#define AVRCP_CAT_1 BIT(0) /* Player/Recorder */ +#define AVRCP_CAT_2 BIT(1) /* Monitor/Amplifier */ +#define AVRCP_CAT_3 BIT(2) /* Tuner */ +#define AVRCP_CAT_4 BIT(3) /* Menu */ +#define AVRCP_PLAYER_APPLICATION_SETTINGS BIT(4) /* Bit 0 must also be set */ +#define AVRCP_GROUP_NAVIGATION BIT(5) /* Bit 0 must also be set */ +#define AVRCP_BROWSING_SUPPORT BIT(6) +#define AVRCP_MULTIPLE_MEDIA_PLAYERS BIT(7) +#define AVRCP_COVER_ART_SUPPORT BIT(8) #define AVRCP_SUBUNIT_PAGE (0) /* Fixed value according to AVRCP */ #define AVRCP_SUBUNIT_EXTENSION_CODE (7) /* Fixed value according to TA Document 2001012 */ @@ -23,6 +28,15 @@ #define BT_AVRCP_UNIT_INFO_RSP_SIZE (5) #define BT_AVRCP_SUBUNIT_INFO_RSP_SIZE (5) +#define BT_L2CAP_PSM_AVRCP 0x0017 +#define BT_L2CAP_PSM_AVRCP_BROWSING 0x001b + +#if defined(CONFIG_BT_AVRCP_BROWSING) +#define AVRCP_BROWSING_ENABLE AVRCP_BROWSING_SUPPORT +#else +#define AVRCP_BROWSING_ENABLE 0 +#endif /* CONFIG_BT_AVRCP_BROWSING */ + typedef enum __packed { BT_AVRCP_SUBUNIT_ID_ZERO = 0x0, BT_AVRCP_SUBUNIT_ID_IGNORE = 0x7, @@ -122,6 +136,12 @@ struct bt_avrcp_avc_pdu { uint8_t param[]; } __packed; +struct bt_avrcp_avc_brow_pdu { + uint8_t pdu_id; + uint16_t param_len; + uint8_t param[]; +} __packed; + /** The 4-bit command type or the 4-bit response code. */ #define BT_AVRCP_HDR_GET_CTYPE_OR_RSP(hdr) FIELD_GET(GENMASK(3, 0), ((hdr)->byte0)) /** Taken together, the subunit_type and subunit_ID fields define the command recipient’s address diff --git a/subsys/bluetooth/host/classic/br.c b/subsys/bluetooth/host/classic/br.c index f9265dc948bad..23a43a01959b3 100644 --- a/subsys/bluetooth/host/classic/br.c +++ b/subsys/bluetooth/host/classic/br.c @@ -211,6 +211,12 @@ void bt_hci_synchronous_conn_complete(struct net_buf *buf) } sco_conn->handle = handle; + sco_conn->sco.air_mode = evt->air_mode; + + if (sco_conn->sco.link_type != evt->link_type) { + LOG_WRN("link type mismatch %u != %u", sco_conn->sco.link_type, evt->link_type); + sco_conn->sco.link_type = evt->link_type; + } bt_conn_set_state(sco_conn, BT_CONN_CONNECTED); bt_conn_unref(sco_conn); } diff --git a/subsys/bluetooth/host/classic/l2cap_br.c b/subsys/bluetooth/host/classic/l2cap_br.c index 5323378d376f6..6bf75c24f6df0 100644 --- a/subsys/bluetooth/host/classic/l2cap_br.c +++ b/subsys/bluetooth/host/classic/l2cap_br.c @@ -899,6 +899,11 @@ int bt_l2cap_br_send_cb(struct bt_conn *conn, uint16_t cid, struct net_buf *buf, return -ESHUTDOWN; } + if (ch->conn == NULL) { + LOG_WRN("ACL conn of chan %p is invalid", ch); + return -ENOTCONN; + } + br_chan = CONTAINER_OF(ch, struct bt_l2cap_br_chan, chan); LOG_DBG("chan %p buf %p len %u", br_chan, buf, buf->len); diff --git a/subsys/bluetooth/host/classic/l2cap_br_internal.h b/subsys/bluetooth/host/classic/l2cap_br_internal.h index ad34bb487fbb2..c4989d2c1fc36 100644 --- a/subsys/bluetooth/host/classic/l2cap_br_internal.h +++ b/subsys/bluetooth/host/classic/l2cap_br_internal.h @@ -10,6 +10,7 @@ #include #include +#include #include "l2cap_br_interface.h" #define BT_L2CAP_CID_BR_SIG 0x0001 @@ -177,12 +178,12 @@ struct bt_l2cap_disconn_rsp { #define BT_L2CAP_ECHO_REQ 0x08 struct bt_l2cap_echo_req { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BT_L2CAP_ECHO_RSP 0x09 struct bt_l2cap_echo_rsp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BT_L2CAP_INFO_CONNLESS_MTU 0x0001 diff --git a/subsys/bluetooth/host/classic/sdp.c b/subsys/bluetooth/host/classic/sdp.c index 6ad7130188f00..5a02540791b2c 100644 --- a/subsys/bluetooth/host/classic/sdp.c +++ b/subsys/bluetooth/host/classic/sdp.c @@ -38,6 +38,8 @@ LOG_MODULE_REGISTER(bt_sdp); #define MAX_NUM_ATT_ID_FILTER 10 +#define MAX_NUM_SSP_UUID 12 + #define SDP_SERVICE_HANDLE_BASE 0x10000 #define SDP_DATA_ELEM_NEST_LEVEL_MAX 5 @@ -68,7 +70,7 @@ struct bt_sdp { /* TODO: Allow more than one pending request */ }; -static struct bt_sdp_record *db; +static sys_slist_t sdp_db = SYS_SLIST_STATIC_INIT(&sdp_db); static uint8_t num_services; static struct bt_sdp bt_sdp_pool[CONFIG_BT_MAX_CONN]; @@ -274,7 +276,7 @@ static void send_err_rsp(struct bt_l2cap_chan *chan, uint16_t err, bt_sdp_send(chan, buf, BT_SDP_ERROR_RSP, tid); } -/* @brief Parses data elements from a net_buf +/* @brief Parses data elements * * Parses the first data element from a buffer and splits it into type, size, * data. Used for parsing incoming requests. Net buf is advanced to the data @@ -285,7 +287,7 @@ static void send_err_rsp(struct bt_l2cap_chan *chan, uint16_t err, * * @return 0 for success, or relevant error code */ -static uint16_t parse_data_elem(struct net_buf *buf, +static uint16_t parse_data_elem(struct net_buf_simple *buf, struct bt_sdp_data_elem *data_elem) { uint8_t size_field_len = 0U; /* Space used to accommodate the size */ @@ -295,7 +297,7 @@ static uint16_t parse_data_elem(struct net_buf *buf, return BT_SDP_INVALID_SYNTAX; } - data_elem->type = net_buf_pull_u8(buf); + data_elem->type = net_buf_simple_pull_u8(buf); switch (data_elem->type & BT_SDP_TYPE_DESC_MASK) { case BT_SDP_UINT8: @@ -317,13 +319,13 @@ static uint16_t parse_data_elem(struct net_buf *buf, } switch (size_field_len) { case 1: - data_elem->data_size = net_buf_pull_u8(buf); + data_elem->data_size = net_buf_simple_pull_u8(buf); break; case 2: - data_elem->data_size = net_buf_pull_be16(buf); + data_elem->data_size = net_buf_simple_pull_be16(buf); break; case 4: - data_elem->data_size = net_buf_pull_be32(buf); + data_elem->data_size = net_buf_simple_pull_be32(buf); break; default: LOG_WRN("Invalid size in remote request"); @@ -437,153 +439,165 @@ static uint32_t search_uuid(struct bt_sdp_data_elem *elem, struct bt_uuid *uuid, * @return Pointer to the record where the iterator stopped, or NULL if all * records are covered */ -static struct bt_sdp_record *bt_sdp_foreach_svc(bt_sdp_svc_func_t func, - void *user_data) +static struct bt_sdp_record *bt_sdp_foreach_svc(bt_sdp_svc_func_t func, void *user_data) { - struct bt_sdp_record *rec = db; + struct bt_sdp_record *rec, *next; - while (rec) { + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&sdp_db, rec, next, node) { if (func(rec, user_data) == BT_SDP_ITER_STOP) { break; } - - rec = rec->next; } return rec; } -/* @brief Inserts a service record into a record pointer list +/* @brief Parse service search pattern * - * Inserts a service record into a record pointer list + * Parse service search pattern * - * @param rec The current service record. - * @param user_data Pointer to the destination record list. + * @param buf Request net buf + * @param ssp Service search pattern buffer * - * @return BT_SDP_ITER_CONTINUE to move on to the next record. + * @return 0 for success, or relevant error code */ -static uint8_t insert_record(struct bt_sdp_record *rec, void *user_data) +static uint16_t parse_service_search_pattern(struct net_buf *buf, struct net_buf_simple *ssp) { - struct bt_sdp_record **rec_list = user_data; + struct net_buf_simple_state state; + struct bt_sdp_data_elem data_elem; + uint16_t res; + uint8_t uuid_count = 0U; - rec_list[rec->index] = rec; + res = parse_data_elem(&buf->b, &data_elem); + if (res != 0) { + return res; + } - return BT_SDP_ITER_CONTINUE; + if (((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_SEQ_UNSPEC) && + ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_ALT_UNSPEC)) { + LOG_WRN("Invalid type %x in service search pattern", data_elem.type); + return BT_SDP_INVALID_SYNTAX; + } + + if (buf->len < data_elem.data_size) { + LOG_WRN("Malformed packet"); + return BT_SDP_INVALID_SYNTAX; + } + + net_buf_simple_init_with_data(ssp, net_buf_pull_mem(buf, data_elem.data_size), + data_elem.data_size); + + net_buf_simple_save(ssp, &state); + /* Check the service search pattern is valid or not */ + while (ssp->len > 0) { + res = parse_data_elem(ssp, &data_elem); + if (res != 0) { + return res; + } + + if ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_UUID_UNSPEC) { + LOG_WRN("Invalid type %u in service search pattern", data_elem.type); + return BT_SDP_INVALID_SYNTAX; + } + + if (ssp->len < data_elem.data_size) { + LOG_WRN("Malformed packet"); + return BT_SDP_INVALID_SYNTAX; + } + + if (!((data_elem.data_size == BT_UUID_SIZE_16) || + (data_elem.data_size == BT_UUID_SIZE_32) || + (data_elem.data_size == BT_UUID_SIZE_128))) { + LOG_WRN("INvalid UUID size"); + return BT_SDP_INVALID_SYNTAX; + } + + net_buf_simple_pull(ssp, data_elem.data_size); + uuid_count++; + + if (uuid_count > MAX_NUM_SSP_UUID) { + LOG_WRN("Too many UUIDs in ssp %u> %u", uuid_count, MAX_NUM_SSP_UUID); + return BT_SDP_INVALID_SYNTAX; + } + } + net_buf_simple_restore(ssp, &state); + + return 0; } -/* @brief Looks for matching UUIDs in a list of service records +/* @brief Match service search pattern in the specific SDP record * - * Parses out a sequence of UUIDs from an input buffer, and checks if a record - * in the list contains all the UUIDs. If it doesn't, the record is removed - * from the list, so the list contains only the records which has all the - * input UUIDs in them. + * Match service search pattern in the specific SDP record * - * @param buf Incoming buffer containing all the UUIDs to be matched - * @param matching_recs List of service records to use for storing matching - * records + * @param buf Service search pattern + * @param record SDP record to match against * - * @return 0 for success, or relevant error code + * @return true if matched, false for no match */ -static uint16_t find_services(struct net_buf *buf, - struct bt_sdp_record **matching_recs) +static bool service_search_pattern_matched(struct net_buf_simple *buf, struct bt_sdp_record *record) { + struct net_buf_simple_state state; struct bt_sdp_data_elem data_elem; - struct bt_sdp_record *record; - uint32_t uuid_list_size; uint16_t res; - uint8_t att_idx, rec_idx = 0U; - bool found; union { struct bt_uuid uuid; struct bt_uuid_16 u16; struct bt_uuid_32 u32; struct bt_uuid_128 u128; } u; + bool found = false; - res = parse_data_elem(buf, &data_elem); - if (res) { - return res; - } + net_buf_simple_save(buf, &state); - if (((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_SEQ_UNSPEC) && - ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_ALT_UNSPEC)) { - LOG_WRN("Invalid type %x in service search pattern", data_elem.type); - return BT_SDP_INVALID_SYNTAX; - } - - uuid_list_size = data_elem.data_size; - - bt_sdp_foreach_svc(insert_record, matching_recs); - - /* Go over the sequence of UUIDs, and match one UUID at a time */ - while (uuid_list_size) { + while (buf->len > 0) { res = parse_data_elem(buf, &data_elem); - if (res) { - return res; + if (res != 0) { + break; } - if ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != - BT_SDP_UUID_UNSPEC) { + if ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_UUID_UNSPEC) { LOG_WRN("Invalid type %u in service search pattern", data_elem.type); - return BT_SDP_INVALID_SYNTAX; + break; } if (buf->len < data_elem.data_size) { LOG_WRN("Malformed packet"); - return BT_SDP_INVALID_SYNTAX; + break; } - uuid_list_size -= data_elem.total_size; - - if (data_elem.data_size == 2U) { + if (data_elem.data_size == BT_UUID_SIZE_16) { u.uuid.type = BT_UUID_TYPE_16; - u.u16.val = net_buf_pull_be16(buf); - } else if (data_elem.data_size == 4U) { + u.u16.val = net_buf_simple_pull_be16(buf); + } else if (data_elem.data_size == BT_UUID_SIZE_32) { u.uuid.type = BT_UUID_TYPE_32; - u.u32.val = net_buf_pull_be32(buf); - } else if (data_elem.data_size == 16U) { + u.u32.val = net_buf_simple_pull_be32(buf); + } else if (data_elem.data_size == BT_UUID_SIZE_128) { u.uuid.type = BT_UUID_TYPE_128; - sys_memcpy_swap(u.u128.val, buf->data, - data_elem.data_size); - net_buf_pull(buf, data_elem.data_size); + /* Change big endian to little endian */ + sys_memcpy_swap(u.u128.val, buf->data, data_elem.data_size); + net_buf_simple_pull(buf, data_elem.data_size); } else { LOG_WRN("Invalid UUID len %u in service search pattern", data_elem.data_size); - net_buf_pull(buf, data_elem.data_size); + net_buf_simple_pull(buf, data_elem.data_size); continue; } - /* Go over the list of services, and look for a service which - * doesn't have this UUID - */ - for (rec_idx = 0U; rec_idx < num_services; rec_idx++) { - record = matching_recs[rec_idx]; - - if (!record) { - continue; - } - - found = false; + for (size_t index = 0; index < record->attr_count; index++) { + struct bt_sdp_attribute *attr; - /* Search for the UUID in all the attrs of the svc */ - for (att_idx = 0U; att_idx < record->attr_count; - att_idx++) { - search_uuid(&record->attrs[att_idx].val, - &u.uuid, &found, 1); - if (found) { - break; - } - } + attr = &record->attrs[index]; - /* Remove the record from the list if it doesn't have - * the UUID - */ - if (!found) { - matching_recs[rec_idx] = NULL; + (void)search_uuid(&attr->val, &u.uuid, &found, 1); + if (found) { + goto matched; } } } - return 0; +matched: + net_buf_simple_restore(buf, &state); + + return found; } /* @brief Handler for Service Search Request @@ -596,24 +610,26 @@ static uint16_t find_services(struct net_buf *buf, * * @return 0 for success, or relevant error code */ -static uint16_t sdp_svc_search_req(struct bt_sdp *sdp, struct net_buf *buf, - uint16_t tid) +static uint16_t sdp_svc_search_req(struct bt_sdp *sdp, struct net_buf *buf, uint16_t tid) { struct bt_sdp_svc_rsp *rsp; struct net_buf *resp_buf; - struct bt_sdp_record *record; - struct bt_sdp_record *matching_recs[BT_SDP_MAX_SERVICES]; - uint16_t max_rec_count, total_recs = 0U, current_recs = 0U, res; - uint8_t cont_state_size, cont_state = 0U, idx = 0U, count = 0U; + struct bt_sdp_record *record, *next; + uint16_t max_rec_count, total_recs = 0U, res; + uint8_t cont_state_size; + uint8_t cont_recs = 0U; + uint8_t matched_recs = 0U; + uint8_t current_recs = 0U; bool pkt_full = false; + struct net_buf_simple ssp; - res = find_services(buf, matching_recs); + res = parse_service_search_pattern(buf, &ssp); if (res) { /* Error in parsing */ return res; } - if (buf->len < 3) { + if (buf->len < (sizeof(max_rec_count) + sizeof(cont_state_size))) { LOG_WRN("Malformed packet"); return BT_SDP_INVALID_SYNTAX; } @@ -621,18 +637,6 @@ static uint16_t sdp_svc_search_req(struct bt_sdp *sdp, struct net_buf *buf, max_rec_count = net_buf_pull_be16(buf); cont_state_size = net_buf_pull_u8(buf); - /* Zero out the matching services beyond max_rec_count */ - for (idx = 0U; idx < num_services; idx++) { - if (count == max_rec_count) { - matching_recs[idx] = NULL; - continue; - } - - if (matching_recs[idx]) { - count++; - } - } - /* We send out only SDP_SS_CONT_STATE_SIZE bytes continuation state in * responses, so expect only SDP_SS_CONT_STATE_SIZE bytes in requests */ @@ -647,46 +651,59 @@ static uint16_t sdp_svc_search_req(struct bt_sdp *sdp, struct net_buf *buf, return BT_SDP_INVALID_SYNTAX; } - cont_state = net_buf_pull_u8(buf); + cont_recs = net_buf_pull_u8(buf); /* We include total_recs in the continuation state. We calculate * it once and preserve it across all the partial responses */ total_recs = net_buf_pull_be16(buf); } - LOG_DBG("max_rec_count %u, cont_state %u", max_rec_count, cont_state); + LOG_DBG("max_rec_count %u, cont_recs %u", max_rec_count, cont_recs); resp_buf = bt_sdp_create_pdu(); rsp = net_buf_add(resp_buf, sizeof(*rsp)); - for (; cont_state < num_services; cont_state++) { - record = matching_recs[cont_state]; + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&sdp_db, record, next, node) { + uint16_t require_len; - if (!record) { + if (!service_search_pattern_matched(&ssp, record)) { continue; } + matched_recs++; + /* Calculate total recs only if it is first packet */ if (!cont_state_size) { total_recs++; + } else if (matched_recs > total_recs) { + LOG_WRN("Reached total records %u > %u", matched_recs, total_recs); + break; + } + + if (matched_recs > max_rec_count) { + LOG_WRN("Reached MAX record count %u > %u", matched_recs, max_rec_count); + break; + } + + if (matched_recs < cont_recs) { + continue; } if (pkt_full) { continue; } - /* 4 bytes per Service Record Handle */ - /* 4 bytes for ContinuationState */ - if ((MIN(SDP_MTU, sdp->chan.tx.mtu) - resp_buf->len) < - (4 + 4 + sizeof(struct bt_sdp_hdr))) { + require_len = sizeof(record->handle) + sizeof(cont_state_size) + + SDP_SS_CONT_STATE_SIZE + sizeof(struct bt_sdp_hdr); + if ((MIN(SDP_MTU, sdp->chan.tx.mtu) - resp_buf->len) < require_len) { pkt_full = true; } if (pkt_full) { /* Packet exhausted: Add continuation state and break */ - LOG_DBG("Packet full, num_services_covered %u", cont_state); + LOG_DBG("Packet full, num_services_covered %u", current_recs); net_buf_add_u8(resp_buf, SDP_SS_CONT_STATE_SIZE); - net_buf_add_u8(resp_buf, cont_state); + net_buf_add_u8(resp_buf, matched_recs); /* If it is the first packet of a partial response, * continue dry-running to calculate total_recs. @@ -699,12 +716,14 @@ static uint16_t sdp_svc_search_req(struct bt_sdp *sdp, struct net_buf *buf, continue; } - /* Add the service record handle to the packet */ + /* Add Service Record Handle */ net_buf_add_be32(resp_buf, record->handle); current_recs++; } - /* Add 0 continuation state if packet is exhausted */ + /* If packet is not exhausted, add 0 continuation state. + * Else, add total records count for continuation state. + */ if (!pkt_full) { net_buf_add_u8(resp_buf, 0); } else { @@ -1146,15 +1165,15 @@ static uint16_t create_attr_list(struct bt_sdp *sdp, struct bt_sdp_record *recor * * @return 0 for success, or relevant error code */ -static uint16_t get_att_search_list(struct net_buf *buf, uint32_t *filter, - size_t max_filters, size_t *num_filters) +static uint16_t get_att_search_list(struct net_buf *buf, uint32_t *filter, size_t max_filters, + size_t *num_filters) { struct bt_sdp_data_elem data_elem; uint16_t res; uint32_t size; *num_filters = 0U; - res = parse_data_elem(buf, &data_elem); + res = parse_data_elem(&buf->b, &data_elem); if (res) { return res; } @@ -1167,7 +1186,7 @@ static uint16_t get_att_search_list(struct net_buf *buf, uint32_t *filter, return 0; } - res = parse_data_elem(buf, &data_elem); + res = parse_data_elem(&buf->b, &data_elem); if (res) { return res; } @@ -1352,11 +1371,9 @@ static uint16_t sdp_svc_att_req(struct bt_sdp *sdp, struct net_buf *buf, uint16_ * * @return 0 for success, or relevant error code */ -static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, - uint16_t tid) +static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, uint16_t tid) { uint32_t filter[MAX_NUM_ATT_ID_FILTER]; - struct bt_sdp_record *matching_recs[BT_SDP_MAX_SERVICES]; struct search_state state = { .att_list_size = 0, .current_svc = SDP_INVALID, @@ -1365,7 +1382,7 @@ static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, .pkt_full = false }; struct net_buf *rsp_buf, *rsp_buf_cpy; - struct bt_sdp_record *record; + struct bt_sdp_record *record, *next; struct bt_sdp_att_rsp *rsp; struct bt_sdp_data_elem_seq *seq = NULL; uint16_t max_att_len, res, att_list_len = 0U; @@ -1373,14 +1390,16 @@ static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, size_t num_filters; uint8_t cont_state_size, next_svc = 0U; bool dry_run = false; + struct net_buf_simple ssp; - res = find_services(buf, matching_recs); + res = parse_service_search_pattern(buf, &ssp); if (res) { + /* Error in parsing */ return res; } if (buf->len < sizeof(max_att_len)) { - LOG_WRN("Malformed packet"); + LOG_WRN("Malformed packet - Maximum Attribute Byte Count"); return BT_SDP_INVALID_SYNTAX; } @@ -1392,14 +1411,13 @@ static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, /* Set up the filters */ res = get_att_search_list(buf, filter, ARRAY_SIZE(filter), &num_filters); - if (res) { /* Error in parsing */ return res; } if (buf->len < sizeof(cont_state_size)) { - LOG_WRN("Malformed packet"); + LOG_WRN("Malformed packet - Continuation State"); return BT_SDP_INVALID_SYNTAX; } @@ -1415,7 +1433,7 @@ static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, } if (buf->len < cont_state_size) { - LOG_WRN("Malformed packet"); + LOG_WRN("Malformed packet - Continuation State Size"); return BT_SDP_INVALID_SYNTAX; } @@ -1445,10 +1463,12 @@ static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, rsp_buf_cpy = rsp_buf; - for (; next_svc < num_services; next_svc++) { - record = matching_recs[next_svc]; + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&sdp_db, record, next, node) { + if (!service_search_pattern_matched(&ssp, record)) { + continue; + } - if (!record) { + if (record->index < next_svc) { continue; } @@ -1522,8 +1542,7 @@ static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, } LOG_DBG("Sending response, len %u", rsp_buf->len); - bt_sdp_send(&sdp->chan.chan, rsp_buf, BT_SDP_SVC_SEARCH_ATTR_RSP, - tid); + bt_sdp_send(&sdp->chan.chan, rsp_buf, BT_SDP_SVC_SEARCH_ATTR_RSP, tid); return 0; } @@ -1653,29 +1672,39 @@ void bt_sdp_init(void) int bt_sdp_register_service(struct bt_sdp_record *service) { - uint32_t handle = SDP_SERVICE_HANDLE_BASE; + uint8_t index = 0; if (!service) { LOG_ERR("No service record specified"); return 0; } - if (num_services == BT_SDP_MAX_SERVICES) { - LOG_ERR("Reached max allowed registrations"); - return -ENOMEM; + if (sys_slist_find(&sdp_db, &service->node, NULL)) { + LOG_ERR("Service already registered"); + return -EEXIST; } - if (db) { - handle = db->handle + 1; + if (!sys_slist_is_empty(&sdp_db)) { + struct bt_sdp_record *last; + + last = CONTAINER_OF(sys_slist_peek_tail(&sdp_db), struct bt_sdp_record, node); + index = last->index + 1; + + if (last->index > index) { + LOG_ERR("Registered record is full"); + return -EOVERFLOW; + } } - service->next = db; - service->index = num_services++; - service->handle = handle; - *((uint32_t *)(service->attrs[0].val.data)) = handle; - db = service; + service->index = index; + service->handle = SDP_SERVICE_HANDLE_BASE + index; + *((uint32_t *)(service->attrs[0].val.data)) = service->handle; + + sys_slist_append(&sdp_db, &service->node); - LOG_DBG("Service registered at %u", handle); + num_services++; + + LOG_DBG("Service registered at %u", service->handle); return 0; } @@ -1744,11 +1773,89 @@ static int sdp_client_ss_search(struct bt_sdp_client *session, return bt_sdp_send(&session->chan.chan, buf, BT_SDP_SVC_SEARCH_REQ, session->tid); } +static uint16_t sdp_client_get_attribute_id_list_len(struct bt_sdp_attribute_id_list *ids) +{ + uint16_t len = 0; + + if (ids == NULL || ids->count == 0) { + return sizeof(uint8_t) + sizeof(uint32_t); + } + + for (size_t i = 0; i < ids->count; i++) { + if (ids->ranges[i].beginning == ids->ranges[i].ending) { + len += sizeof(uint8_t) + sizeof(uint16_t); + } else { + len += sizeof(uint8_t) + sizeof(uint32_t); + } + } + + return len; +} + +static void sdp_client_add_attribute_id(struct net_buf *buf, struct bt_sdp_attribute_id_list *ids) +{ + uint16_t len; + + len = sdp_client_get_attribute_id_list_len(ids); + /* + * Sequence definition where data is sequence of elements and where + * additional next byte points the size of elements within + */ + if (len > UINT8_MAX) { + net_buf_add_u8(buf, BT_SDP_SEQ16); + net_buf_add_be16(buf, len); + } else { + net_buf_add_u8(buf, BT_SDP_SEQ8); + net_buf_add_u8(buf, len); + } + + if (ids == NULL || ids->count == 0) { + /* Data element definition for two following 16bits range elements */ + net_buf_add_u8(buf, BT_SDP_UINT32); + /* Get all attributes. It enables filter out wanted only attributes */ + net_buf_add_be16(buf, 0x0000); + net_buf_add_be16(buf, 0xffff); + return; + } + + for (size_t i = 0; i < ids->count; i++) { + if (ids->ranges[i].beginning == ids->ranges[i].ending) { + /* Data element definition for one following 16bits range elements */ + net_buf_add_u8(buf, BT_SDP_UINT16); + /* Get all attributes. It enables filter out wanted only attributes */ + net_buf_add_be16(buf, ids->ranges[i].beginning); + } else { + /* Data element definition for two following 16bits range elements */ + net_buf_add_u8(buf, BT_SDP_UINT32); + /* Get all attributes. It enables filter out wanted only attributes */ + net_buf_add_be16(buf, ids->ranges[i].beginning); + net_buf_add_be16(buf, ids->ranges[i].ending); + } + } +} + +static uint16_t sdp_client_get_total_len(struct bt_sdp_client *session, + const struct bt_sdp_discover_params *param) +{ + uint16_t len; + + len = sdp_client_get_attribute_id_list_len(param->ids); + if (len > UINT8_MAX) { + len += sizeof(uint8_t) + sizeof(uint16_t); + } else { + len += sizeof(uint8_t) + sizeof(uint8_t); + } + len += sizeof(session->cstate.length) + session->cstate.length; + + return len; +} + /* ServiceAttribute PDU, ref to BT Core 5.4, Vol 3, part B, 4.6.1 */ static int sdp_client_sa_search(struct bt_sdp_client *session, const struct bt_sdp_discover_params *param) { struct net_buf *buf; + uint16_t len; /* Update context param directly. */ session->param = param; @@ -1760,17 +1867,17 @@ static int sdp_client_sa_search(struct bt_sdp_client *session, /* Set attribute max bytes count to be returned from server */ net_buf_add_be16(buf, net_buf_tailroom(session->rec_buf)); - /* - * Sequence definition where data is sequence of elements and where - * additional next byte points the size of elements within - */ - net_buf_add_u8(buf, BT_SDP_SEQ8); - net_buf_add_u8(buf, 0x05); - /* Data element definition for two following 16bits range elements */ - net_buf_add_u8(buf, BT_SDP_UINT32); - /* Get all attributes. It enables filter out wanted only attributes */ - net_buf_add_be16(buf, 0x0000); - net_buf_add_be16(buf, 0xffff); + + /* Check the tailroom of the buffer */ + len = sdp_client_get_total_len(session, param); + if (len > net_buf_tailroom(buf)) { + LOG_ERR("No space to add attribute ID"); + net_buf_unref(buf); + return -ENOMEM; + } + + /* Add attribute ID List */ + sdp_client_add_attribute_id(buf, param->ids); /* * Update and validate PDU ContinuationState. Initial SSA Request has @@ -1796,6 +1903,7 @@ static int sdp_client_ssa_search(struct bt_sdp_client *session, { struct net_buf *buf; uint8_t uuid128[BT_UUID_SIZE_128]; + uint16_t len; /* Update context param directly. */ session->param = param; @@ -1833,17 +1941,17 @@ static int sdp_client_ssa_search(struct bt_sdp_client *session, /* Set attribute max bytes count to be returned from server */ net_buf_add_be16(buf, net_buf_tailroom(session->rec_buf)); - /* - * Sequence definition where data is sequence of elements and where - * additional next byte points the size of elements within - */ - net_buf_add_u8(buf, BT_SDP_SEQ8); - net_buf_add_u8(buf, 0x05); - /* Data element definition for two following 16bits range elements */ - net_buf_add_u8(buf, BT_SDP_UINT32); - /* Get all attributes. It enables filter out wanted only attributes */ - net_buf_add_be16(buf, 0x0000); - net_buf_add_be16(buf, 0xffff); + + /* Check the tailroom of the buffer */ + len = sdp_client_get_total_len(session, param); + if (len > net_buf_tailroom(buf)) { + LOG_ERR("No space to add attribute ID"); + net_buf_unref(buf); + return -ENOMEM; + } + + /* Add attribute ID List */ + sdp_client_add_attribute_id(buf, param->ids); /* * Update and validate PDU ContinuationState. Initial SSA Request has @@ -2022,10 +2130,11 @@ static uint16_t get_record_len(struct bt_sdp_client *session) enum uuid_state { UUID_NOT_RESOLVED, UUID_RESOLVED, + UUID_PARTIAL_RESOLVED, }; -static void sdp_client_notify_result(struct bt_sdp_client *session, - enum uuid_state state) +static int sdp_client_notify_result(struct bt_sdp_client *session, + enum uuid_state state) { struct bt_conn *conn = session->chan.chan.conn; struct bt_sdp_client_result result; @@ -2036,17 +2145,61 @@ static void sdp_client_notify_result(struct bt_sdp_client *session, result.resp_buf = NULL; result.next_record_hint = false; session->param->func(conn, &result, session->param); - return; + return 0; } while (session->rec_buf->len) { struct net_buf_simple_state buf_state; + net_buf_simple_save(&session->rec_buf->b, &buf_state); rec_len = get_record_len(session); /* tell the user about multi record resolution */ if (session->rec_buf->len > rec_len) { result.next_record_hint = true; } else { + if (state == UUID_PARTIAL_RESOLVED) { + struct net_buf *buf; + uint8_t *src, *dst; + uint16_t len; + + net_buf_simple_restore(&session->rec_buf->b, &buf_state); + /* Partial resolution, continue processing */ + src = session->rec_buf->data; + len = session->rec_buf->len; + + /* The allocated buffer is full. Try to allocate a new buffer from + * the same pool. Use allocated buffer to continue the SDP + * discovery if the new buffer allocated. Otherwise, use the + * current allocated to continue the SDP discovery. + */ + buf = net_buf_alloc(session->param->pool, K_NO_WAIT); + if (buf != NULL) { + if (net_buf_tailroom(buf) < len) { + LOG_ERR("No more buffer space for SDP discover. " + "Need to increase buffer size of the " + "receiving pool."); + net_buf_unref(buf); + return -ENOMEM; + } + net_buf_add_mem(buf, src, len); + net_buf_unref(session->rec_buf); + session->rec_buf = buf; + LOG_DBG("Continue discovery with new buf %p", buf); + return 0; + } + + net_buf_reset(session->rec_buf); + dst = net_buf_add(session->rec_buf, len); + if (dst == src) { + LOG_ERR("No more buffer space for SDP discover. Need to " + "increase buffer size of the receiving pool."); + return -ENOMEM; + } + + memmove(dst, src, len); + LOG_DBG("Continue discovery with current buf"); + return 0; + } result.next_record_hint = false; } @@ -2071,9 +2224,11 @@ static void sdp_client_notify_result(struct bt_sdp_client *session, */ net_buf_pull(session->rec_buf, rec_len); if (user_ret == BT_SDP_DISCOVER_UUID_STOP) { - break; + return -ECANCELED; } } + + return 0; } static int sdp_client_discover(struct bt_sdp_client *session) @@ -2235,6 +2390,11 @@ static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf * return 0; } +static int sdp_client_ssa_sa_notify(struct bt_sdp_client *session) +{ + return sdp_client_notify_result(session, UUID_PARTIAL_RESOLVED); +} + static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_buf *buf) { struct bt_sdp_pdu_cstate *cstate; @@ -2255,7 +2415,7 @@ static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_b return -EINVAL; } /* Check valid range of attributes length */ - if (((session->cstate.length == 0) && (frame_len < 2)) || (frame_len == 0)) { + if ((session->cstate.length == 0) && (frame_len < 2)) { LOG_ERR("Invalid attributes data length"); return -EINVAL; } @@ -2273,6 +2433,22 @@ static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_b return -EINVAL; } + /* No more data found for given UUID and Continuation State length is not zero. + * It means the remaining tailroom of the RX buffer is not enough to store the data. + * Try to notify the received data, and request the next portion of data by sending a + * continuation request. + */ + if (frame_len == 0 && cstate->length != 0) { + /* Notify current received data */ + int err; + + err = sdp_client_ssa_sa_notify(session); + if (err != 0) { + LOG_ERR("Failed to notify received data: %d", err); + return err; + } + } + /* * No record found for given UUID. The check catches case when * current response frame has Continuation State shortest and @@ -2617,11 +2793,27 @@ static int sdp_client_discovery_start(struct bt_conn *conn, int bt_sdp_discover(struct bt_conn *conn, struct bt_sdp_discover_params *params) { - if (!params || !params->uuid || !params->func || !params->pool) { + if (params == NULL || params->uuid == NULL || params->func == NULL || + params->pool == NULL || + (params->ids != NULL && params->ids->count != 0 && params->ids->ranges == NULL)) { LOG_WRN("Invalid user params"); return -EINVAL; } + if (params->ids != NULL) { + for (size_t i = 0; i < params->ids->count; i++) { + struct bt_sdp_attribute_id_range *range; + + range = ¶ms->ids->ranges[i]; + if (range->beginning <= range->ending) { + continue; + } + + LOG_WRN("Invalid range %u > %u", range->beginning, range->ending); + return -EINVAL; + } + } + return sdp_client_discovery_start(conn, params); } @@ -3200,7 +3392,8 @@ int bt_sdp_get_proto_param(const struct net_buf *buf, enum bt_sdp_proto proto, struct bt_sdp_uuid_desc pd; int res; - if (proto != BT_SDP_PROTO_RFCOMM && proto != BT_SDP_PROTO_L2CAP) { + if (proto != BT_SDP_PROTO_RFCOMM && proto != BT_SDP_PROTO_L2CAP && + proto != BT_SDP_PROTO_AVDTP) { LOG_ERR("Invalid protocol specifier"); return -EINVAL; } @@ -3227,7 +3420,8 @@ int bt_sdp_get_addl_proto_param(const struct net_buf *buf, enum bt_sdp_proto pro struct bt_sdp_uuid_desc pd; int res; - if (proto != BT_SDP_PROTO_RFCOMM && proto != BT_SDP_PROTO_L2CAP) { + if (proto != BT_SDP_PROTO_RFCOMM && proto != BT_SDP_PROTO_L2CAP && + proto != BT_SDP_PROTO_AVDTP) { LOG_ERR("Invalid protocol specifier"); return -EINVAL; } diff --git a/subsys/bluetooth/host/classic/sdp_internal.h b/subsys/bluetooth/host/classic/sdp_internal.h index 1524318c4a19a..43704f87a6695 100644 --- a/subsys/bluetooth/host/classic/sdp_internal.h +++ b/subsys/bluetooth/host/classic/sdp_internal.h @@ -37,8 +37,6 @@ #define BT_SDP_INVALID_PDU_SIZE 0x0004 #define BT_SDP_INVALID_CSTATE 0x0005 -#define BT_SDP_MAX_SERVICES 10 - struct bt_sdp_data_elem_seq { uint8_t type; /* Type: Will be data element sequence */ uint16_t size; /* We only support 2 byte sizes for now */ diff --git a/subsys/bluetooth/host/classic/shell/a2dp.c b/subsys/bluetooth/host/classic/shell/a2dp.c index 19e38e35094dc..14a40bb1e1ccf 100644 --- a/subsys/bluetooth/host/classic/shell/a2dp.c +++ b/subsys/bluetooth/host/classic/shell/a2dp.c @@ -99,7 +99,7 @@ static struct bt_sdp_attribute a2dp_sink_attrs[] = { }, { BT_SDP_TYPE_SIZE(BT_SDP_UINT16), /* 09 */ - BT_SDP_ARRAY_16(0x0100U) /* AVDTP version: 01 00 */ + BT_SDP_ARRAY_16(AVDTP_VERSION) /* AVDTP version: 01 03 */ }, ) }, @@ -168,7 +168,7 @@ static struct bt_sdp_attribute a2dp_source_attrs[] = { }, { BT_SDP_TYPE_SIZE(BT_SDP_UINT16), - BT_SDP_ARRAY_16(0x0100U) + BT_SDP_ARRAY_16(AVDTP_VERSION) }, ) }, @@ -193,7 +193,7 @@ static struct bt_sdp_attribute a2dp_source_attrs[] = { }, ) ), - BT_SDP_SERVICE_NAME("A2DPSink"), + BT_SDP_SERVICE_NAME("A2DPSource"), BT_SDP_SUPPORTED_FEATURES(0x0001U), }; @@ -677,13 +677,22 @@ struct bt_a2dp_discover_param discover_param = { static int cmd_get_peer_eps(const struct shell *sh, int32_t argc, char *argv[]) { + int err = 0; + if (a2dp_initied == 0) { shell_print(sh, "need to register a2dp connection callbacks"); return -ENOEXEC; } if (default_a2dp != NULL) { - int err = bt_a2dp_discover(default_a2dp, &discover_param); + discover_param.avdtp_version = (uint16_t)shell_strtoul(argv[1], 0, &err); + if (err != 0) { + shell_error(sh, "failed to parse avdtp version: %d", err); + + return -ENOEXEC; + } + + err = bt_a2dp_discover(default_a2dp, &discover_param); if (err) { shell_error(sh, "discover fail"); @@ -798,7 +807,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(a2dp_cmds, cmd_register_ep, 3, 0), SHELL_CMD_ARG(connect, NULL, HELP_NONE, cmd_connect, 1, 0), SHELL_CMD_ARG(disconnect, NULL, HELP_NONE, cmd_disconnect, 1, 0), - SHELL_CMD_ARG(discover_peer_eps, NULL, HELP_NONE, cmd_get_peer_eps, 1, 0), + SHELL_CMD_ARG(discover_peer_eps, NULL, "", cmd_get_peer_eps, 2, 0), SHELL_CMD_ARG(configure, NULL, "\"configure/enable the stream\"", cmd_configure, 1, 0), SHELL_CMD_ARG(establish, NULL, "\"establish the stream\"", cmd_establish, 1, 0), SHELL_CMD_ARG(reconfigure, NULL, "\"reconfigure the stream\"", cmd_reconfigure, 1, 0), diff --git a/subsys/bluetooth/host/classic/shell/avrcp.c b/subsys/bluetooth/host/classic/shell/avrcp.c index 91eebe7ab1e1d..9bdc245980019 100644 --- a/subsys/bluetooth/host/classic/shell/avrcp.c +++ b/subsys/bluetooth/host/classic/shell/avrcp.c @@ -29,6 +29,12 @@ #include "host/shell/bt.h" #include "common/bt_shell_private.h" +NET_BUF_POOL_DEFINE(avrcp_tx_pool, CONFIG_BT_MAX_CONN, + BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_TX_MTU), + CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL); + +#define FOLDER_NAME_HEX_BUF_LEN 80 + struct bt_avrcp_ct *default_ct; struct bt_avrcp_tg *default_tg; static bool avrcp_ct_registered; @@ -60,6 +66,16 @@ static void avrcp_ct_disconnected(struct bt_avrcp_ct *ct) default_ct = NULL; } +static void avrcp_ct_browsing_connected(struct bt_conn *conn, struct bt_avrcp_ct *ct) +{ + bt_shell_print("AVRCP CT browsing connected"); +} + +static void avrcp_ct_browsing_disconnected(struct bt_avrcp_ct *ct) +{ + bt_shell_print("AVRCP CT browsing disconnected"); +} + static void avrcp_get_cap_rsp(struct bt_avrcp_ct *ct, uint8_t tid, const struct bt_avrcp_get_cap_rsp *rsp) { @@ -115,13 +131,70 @@ static void avrcp_passthrough_rsp(struct bt_avrcp_ct *ct, uint8_t tid, bt_avrcp_ } } +static void avrcp_browsed_player_rsp(struct bt_avrcp_ct *ct, uint8_t tid, + struct net_buf *buf) +{ + struct bt_avrcp_set_browsed_player_rsp *rsp; + struct bt_avrcp_folder_name *folder_name; + + rsp = net_buf_pull_mem(buf, sizeof(*rsp)); + if (rsp->status != BT_AVRCP_STATUS_OPERATION_COMPLETED) { + bt_shell_print("AVRCP set browsed player failed, tid = %d, status = 0x%02x", + tid, rsp->status); + return; + } + + bt_shell_print("AVRCP set browsed player success, tid = %d", tid); + bt_shell_print(" UID Counter: %u", sys_be16_to_cpu(rsp->uid_counter)); + bt_shell_print(" Number of Items: %u", sys_be32_to_cpu(rsp->num_items)); + bt_shell_print(" Charset ID: 0x%04X", sys_be16_to_cpu(rsp->charset_id)); + bt_shell_print(" Folder Depth: %u", rsp->folder_depth); + + while (buf->len > 0) { + if (buf->len < sizeof(struct bt_avrcp_folder_name)) { + bt_shell_print("incompleted message"); + break; + } + folder_name = net_buf_pull_mem(buf, sizeof(struct bt_avrcp_folder_name)); + folder_name->folder_name_len = sys_be16_to_cpu(folder_name->folder_name_len); + if (buf->len < folder_name->folder_name_len) { + bt_shell_print("incompleted message for folder_name"); + break; + } + net_buf_pull_mem(buf, folder_name->folder_name_len); + + if (sys_be16_to_cpu(rsp->charset_id) == BT_AVRCP_CHARSET_UTF8) { + bt_shell_print("Raw folder name:"); + for (int i = 0; i < folder_name->folder_name_len; i++) { + bt_shell_print("%c", folder_name->folder_name[i]); + } + } else { + bt_shell_print(" Get folder Name : "); + bt_shell_hexdump(folder_name->folder_name, folder_name->folder_name_len); + } + if (rsp->folder_depth > 0) { + rsp->folder_depth--; + } else { + bt_shell_warn("Folder depth is mismatched with received data"); + break; + } + } + + if (rsp->folder_depth > 0) { + bt_shell_print("folder depth mismatch: expected 0, got %u", rsp->folder_depth); + } +} + static struct bt_avrcp_ct_cb app_avrcp_ct_cb = { .connected = avrcp_ct_connected, .disconnected = avrcp_ct_disconnected, + .browsing_connected = avrcp_ct_browsing_connected, + .browsing_disconnected = avrcp_ct_browsing_disconnected, .get_cap_rsp = avrcp_get_cap_rsp, .unit_info_rsp = avrcp_unit_info_rsp, .subunit_info_rsp = avrcp_subunit_info_rsp, .passthrough_rsp = avrcp_passthrough_rsp, + .browsed_player_rsp = avrcp_browsed_player_rsp, }; static void avrcp_tg_connected(struct bt_conn *conn, struct bt_avrcp_tg *tg) @@ -136,16 +209,36 @@ static void avrcp_tg_disconnected(struct bt_avrcp_tg *tg) default_tg = NULL; } +static void avrcp_tg_browsing_connected(struct bt_conn *conn, struct bt_avrcp_tg *tg) +{ + bt_shell_print("AVRCP TG browsing connected"); +} + static void avrcp_unit_info_req(struct bt_avrcp_tg *tg, uint8_t tid) { bt_shell_print("AVRCP unit info request received"); tg_tid = tid; } +static void avrcp_tg_browsing_disconnected(struct bt_avrcp_tg *tg) +{ + bt_shell_print("AVRCP TG browsing disconnected"); +} + +static void avrcp_set_browsed_player_req(struct bt_avrcp_tg *tg, uint8_t tid, + uint16_t player_id) +{ + bt_shell_print("AVRCP set browsed player request received, player_id = %u", player_id); + tg_tid = tid; +} + static struct bt_avrcp_tg_cb app_avrcp_tg_cb = { .connected = avrcp_tg_connected, .disconnected = avrcp_tg_disconnected, + .browsing_connected = avrcp_tg_browsing_connected, + .browsing_disconnected = avrcp_tg_browsing_disconnected, .unit_info_req = avrcp_unit_info_req, + .set_browsed_player_req = avrcp_set_browsed_player_req, }; static int register_ct_cb(const struct shell *sh) @@ -256,6 +349,53 @@ static int cmd_disconnect(const struct shell *sh, int32_t argc, char *argv[]) return 0; } +static int cmd_browsing_connect(const struct shell *sh, int32_t argc, char *argv[]) +{ + int err; + + if (!avrcp_ct_registered && register_ct_cb(sh) != 0) { + return -ENOEXEC; + } + + if (default_conn == NULL) { + shell_error(sh, "BR/EDR not connected"); + return -ENOEXEC; + } + + err = bt_avrcp_browsing_connect(default_conn); + if (err < 0) { + shell_error(sh, "fail to connect AVRCP browsing"); + } else { + shell_print(sh, "AVRCP browsing connect request sent"); + } + + return err; +} + +static int cmd_browsing_disconnect(const struct shell *sh, int32_t argc, char *argv[]) +{ + int err; + + if (default_conn == NULL) { + shell_print(sh, "Not connected"); + return -ENOEXEC; + } + + if ((default_ct != NULL) || (default_tg != NULL)) { + err = bt_avrcp_browsing_disconnect(default_conn); + if (err < 0) { + shell_error(sh, "fail to disconnect AVRCP browsing"); + } else { + shell_print(sh, "AVRCP browsing disconnect request sent"); + } + } else { + shell_error(sh, "AVRCP is not connected"); + err = -ENOEXEC; + } + + return err; +} + static int cmd_get_unit_info(const struct shell *sh, int32_t argc, char *argv[]) { if (!avrcp_ct_registered && register_ct_cb(sh) != 0) { @@ -364,6 +504,139 @@ static int cmd_get_cap(const struct shell *sh, int32_t argc, char *argv[]) return 0; } +static int cmd_set_browsed_player(const struct shell *sh, int32_t argc, char *argv[]) +{ + uint16_t player_id; + int err; + + if (!avrcp_ct_registered && register_ct_cb(sh) != 0) { + return -ENOEXEC; + } + + if (default_ct == NULL) { + shell_error(sh, "AVRCP is not connected"); + return -ENOEXEC; + } + + player_id = (uint16_t)strtoul(argv[1], NULL, 0); + + err = bt_avrcp_ct_set_browsed_player(default_ct, get_next_tid(), player_id); + if (err < 0) { + shell_error(sh, "fail to set browsed player"); + } else { + shell_print(sh, "AVRCP send set browsed player req"); + } + + return 0; +} + +static int cmd_send_set_browsed_player_rsp(const struct shell *sh, int32_t argc, char *argv[]) +{ + struct bt_avrcp_set_browsed_player_rsp *rsp; + struct bt_avrcp_folder_name *folder_name; + char *folder_name_str = "Music"; + uint8_t folder_name_hex[FOLDER_NAME_HEX_BUF_LEN]; + uint16_t folder_name_len = 0; + struct net_buf *buf; + uint16_t param_len; + int err; + + if (!avrcp_tg_registered && register_tg_cb(sh) != 0) { + return -ENOEXEC; + } + + if (default_tg == NULL) { + shell_error(sh, "AVRCP TG is not connected"); + return -ENOEXEC; + } + + buf = bt_avrcp_create_pdu(&avrcp_tx_pool); + if (buf == NULL) { + shell_error(sh, "Failed to allocate buffer for AVRCP browsing response"); + return -ENOMEM; + } + + if (net_buf_tailroom(buf) < sizeof(struct bt_avrcp_set_browsed_player_rsp)) { + shell_error(sh, "Not enough tailroom in buffer for browsed player rsp"); + goto failed; + } + + rsp = net_buf_add(buf, sizeof(*rsp)); + /* Set default rsp */ + rsp->status = BT_AVRCP_STATUS_OPERATION_COMPLETED; + rsp->uid_counter = sys_cpu_to_be16(0x0001U); + rsp->num_items = sys_cpu_to_be32(100U); + rsp->charset_id = sys_cpu_to_be16(BT_AVRCP_CHARSET_UTF8); + rsp->folder_depth = 1; + + /* Parse command line arguments or use default values */ + if (argc >= 2) { + rsp->status = (uint8_t)strtoul(argv[1], NULL, 0); + } + + if (argc >= 3) { + rsp->uid_counter = sys_cpu_to_be16((uint16_t)strtoul(argv[2], NULL, 0)); + } + + if (argc >= 4) { + rsp->num_items = sys_cpu_to_be32((uint32_t)strtoul(argv[3], NULL, 0)); + } + + if (argc >= 5) { + rsp->charset_id = sys_cpu_to_be16((uint16_t)strtoul(argv[4], NULL, 0)); + } + + if (rsp->charset_id == sys_cpu_to_be16(BT_AVRCP_CHARSET_UTF8)) { + if (argc >= 6) { + folder_name_str = argv[5]; + } + folder_name_len = strlen(folder_name_str); + } else { + if (argc >= 6) { + folder_name_len = hex2bin(argv[5], strlen(argv[5]), folder_name_hex, + sizeof(folder_name_hex)); + if (folder_name_len == 0) { + shell_error(sh, "Failed to get folder_name from %s", argv[5]); + } + } else { + shell_error(sh, "Please input hex string for folder_name"); + goto failed; + } + } + + param_len = folder_name_len + sizeof(struct bt_avrcp_folder_name); + if (net_buf_tailroom(buf) < param_len) { + shell_error(sh, "Not enough tailroom in buffer for param"); + goto failed; + } + + folder_name = net_buf_add(buf, sizeof(*folder_name)); + folder_name->folder_name_len = sys_cpu_to_be16(folder_name_len); + if (rsp->charset_id == sys_cpu_to_be16(BT_AVRCP_CHARSET_UTF8)) { + net_buf_add_mem(buf, folder_name_str, folder_name_len); + } else { + net_buf_add_mem(buf, folder_name_hex, folder_name_len); + } + + err = bt_avrcp_tg_send_set_browsed_player_rsp(default_tg, tg_tid, buf); + if (err == 0) { + shell_print(sh, "Send set browsed player response, status = 0x%02x", rsp->status); + } else { + shell_error(sh, "Failed to send set browsed player response, err = %d", err); + goto failed; + } + + return 0; +failed: + net_buf_unref(buf); + return -ENOEXEC; +} + +#define HELP_BROWSED_PLAYER_RSP \ + "Send SetBrowsedPlayer response\n" \ + "Usage: send_browsed_player_rsp [status] [uid_counter] [num_items] " \ + "[charset_id] [folder_name]" + SHELL_STATIC_SUBCMD_SET_CREATE( ct_cmds, SHELL_CMD_ARG(register_cb, NULL, "register avrcp ct callbacks", cmd_register_ct_cb, 1, 0), @@ -373,12 +646,16 @@ SHELL_STATIC_SUBCMD_SET_CREATE( 0), SHELL_CMD_ARG(play, NULL, "request a play at the remote player", cmd_play, 1, 0), SHELL_CMD_ARG(pause, NULL, "request a pause at the remote player", cmd_pause, 1, 0), + SHELL_CMD_ARG(set_browsed_player, NULL, "set browsed player ", + cmd_set_browsed_player, 2, 0), SHELL_SUBCMD_SET_END); SHELL_STATIC_SUBCMD_SET_CREATE( tg_cmds, SHELL_CMD_ARG(register_cb, NULL, "register avrcp tg callbacks", cmd_register_tg_cb, 1, 0), SHELL_CMD_ARG(send_unit_rsp, NULL, "send unit info response", cmd_send_unit_info_rsp, 1, 0), + SHELL_CMD_ARG(send_browsed_player_rsp, NULL, HELP_BROWSED_PLAYER_RSP, + cmd_send_set_browsed_player_rsp, 1, 5), SHELL_SUBCMD_SET_END); static int cmd_avrcp(const struct shell *sh, size_t argc, char **argv) @@ -398,6 +675,9 @@ SHELL_STATIC_SUBCMD_SET_CREATE( avrcp_cmds, SHELL_CMD_ARG(connect, NULL, "connect AVRCP", cmd_connect, 1, 0), SHELL_CMD_ARG(disconnect, NULL, "disconnect AVRCP", cmd_disconnect, 1, 0), + SHELL_CMD_ARG(browsing_connect, NULL, "connect browsing AVRCP", cmd_browsing_connect, 1, 0), + SHELL_CMD_ARG(browsing_disconnect, NULL, "disconnect browsing AVRCP", + cmd_browsing_disconnect, 1, 0), SHELL_CMD(ct, &ct_cmds, "AVRCP CT shell commands", cmd_avrcp), SHELL_CMD(tg, &tg_cmds, "AVRCP TG shell commands", cmd_avrcp), SHELL_SUBCMD_SET_END); diff --git a/subsys/bluetooth/host/classic/shell/bredr.c b/subsys/bluetooth/host/classic/shell/bredr.c index 9b5544b5adad1..a3f57f25fe3b9 100644 --- a/subsys/bluetooth/host/classic/shell/bredr.c +++ b/subsys/bluetooth/host/classic/shell/bredr.c @@ -950,48 +950,122 @@ static uint8_t sdp_a2src_user(struct bt_conn *conn, struct bt_sdp_client_result conn_addr_str(conn, addr, sizeof(addr)); - if (result && result->resp_buf) { - bt_shell_print("SDP A2SRC data@%p (len %u) hint %u from remote %s", - result->resp_buf, result->resp_buf->len, result->next_record_hint, - addr); + if (result == NULL || result->resp_buf == NULL) { + bt_shell_print("No SDP A2SRC data from remote %s", addr); + goto done; + } - /* - * Focus to get BT_SDP_ATTR_PROTO_DESC_LIST attribute item to - * get A2SRC Server PSM Number. - */ - err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_L2CAP, ¶m); - if (err < 0) { - bt_shell_error("A2SRC PSM Number not found, err %d", err); - goto done; - } + bt_shell_print("SDP A2SRC data@%p (len %u) hint %u from remote %s", + result->resp_buf, result->resp_buf->len, result->next_record_hint, + addr); - bt_shell_print("A2SRC Server PSM Number param 0x%04x", param); + /* + * Focus to get BT_SDP_ATTR_PROTO_DESC_LIST attribute item to + * get A2SRC Server PSM Number. + */ + err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_L2CAP, ¶m); + if (err < 0) { + bt_shell_error("A2SRC PSM Number not found, err %d", err); + goto done; + } - /* - * Focus to get BT_SDP_ATTR_PROFILE_DESC_LIST attribute item to - * get profile version number. - */ - err = bt_sdp_get_profile_version(result->resp_buf, BT_SDP_ADVANCED_AUDIO_SVCLASS, - &version); - if (err < 0) { - bt_shell_error("A2SRC version not found, err %d", err); - goto done; - } - bt_shell_print("A2SRC version param 0x%04x", version); + bt_shell_print("A2SRC Server PSM Number param 0x%04x", param); - /* - * Focus to get BT_SDP_ATTR_SUPPORTED_FEATURES attribute item to - * get profile supported features mask. - */ - err = bt_sdp_get_features(result->resp_buf, &features); - if (err < 0) { - bt_shell_error("A2SRC Features not found, err %d", err); - goto done; - } - bt_shell_print("A2SRC Supported Features param 0x%04x", features); - } else { - bt_shell_print("No SDP A2SRC data from remote %s", addr); + err = bt_sdp_get_proto_param(result->resp_buf, BT_UUID_AVDTP_VAL, &version); + if (err < 0) { + bt_shell_error("A2SRC AVDTP version not found, err %d", err); + goto done; + } + + bt_shell_print("A2SRC Server AVDTP version 0x%04x", version); + + /* + * Focus to get BT_SDP_ATTR_PROFILE_DESC_LIST attribute item to + * get profile version number. + */ + err = bt_sdp_get_profile_version(result->resp_buf, BT_SDP_ADVANCED_AUDIO_SVCLASS, &version); + if (err < 0) { + bt_shell_error("A2SRC version not found, err %d", err); + goto done; + } + bt_shell_print("A2SRC version param 0x%04x", version); + + /* + * Focus to get BT_SDP_ATTR_SUPPORTED_FEATURES attribute item to + * get profile supported features mask. + */ + err = bt_sdp_get_features(result->resp_buf, &features); + if (err < 0) { + bt_shell_error("A2SRC Features not found, err %d", err); + goto done; } + bt_shell_print("A2SRC Supported Features param 0x%04x", features); + +done: + return BT_SDP_DISCOVER_UUID_CONTINUE; +} + +static uint8_t sdp_a2snk_user(struct bt_conn *conn, struct bt_sdp_client_result *result, + const struct bt_sdp_discover_params *params) +{ + char addr[BT_ADDR_STR_LEN]; + uint16_t param, version; + uint16_t features; + int err; + + conn_addr_str(conn, addr, sizeof(addr)); + + if (result == NULL || result->resp_buf == NULL) { + bt_shell_print("No SDP A2SNK data from remote %s", addr); + goto done; + } + + bt_shell_print("SDP A2SNK data@%p (len %u) hint %u from remote %s", + result->resp_buf, result->resp_buf->len, result->next_record_hint, + addr); + + /* + * Focus to get BT_SDP_ATTR_PROTO_DESC_LIST attribute item to + * get A2SNK Server PSM Number. + */ + err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_L2CAP, ¶m); + if (err < 0) { + bt_shell_error("A2SNK PSM Number not found, err %d", err); + goto done; + } + + bt_shell_print("A2SNK Server PSM Number param 0x%04x", param); + + err = bt_sdp_get_proto_param(result->resp_buf, BT_UUID_AVDTP_VAL, &version); + if (err < 0) { + bt_shell_error("A2SNK AVDTP version not found, err %d", err); + goto done; + } + + bt_shell_print("A2SNK Server AVDTP version 0x%04x", version); + + /* + * Focus to get BT_SDP_ATTR_PROFILE_DESC_LIST attribute item to + * get profile version number. + */ + err = bt_sdp_get_profile_version(result->resp_buf, BT_SDP_ADVANCED_AUDIO_SVCLASS, &version); + if (err < 0) { + bt_shell_error("A2SNK version not found, err %d", err); + goto done; + } + bt_shell_print("A2SNK version param 0x%04x", version); + + /* + * Focus to get BT_SDP_ATTR_SUPPORTED_FEATURES attribute item to + * get profile supported features mask. + */ + err = bt_sdp_get_features(result->resp_buf, &features); + if (err < 0) { + bt_shell_error("A2SNK Features not found, err %d", err); + goto done; + } + bt_shell_print("A2SNK Supported Features param 0x%04x", features); + done: return BT_SDP_DISCOVER_UUID_CONTINUE; } @@ -1052,6 +1126,13 @@ static struct bt_sdp_discover_params discov_a2src = { .pool = &sdp_client_pool, }; +static struct bt_sdp_discover_params discov_a2snk = { + .type = BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR, + .uuid = BT_UUID_DECLARE_16(BT_SDP_AUDIO_SINK_SVCLASS), + .func = sdp_a2snk_user, + .pool = &sdp_client_pool, +}; + static struct bt_sdp_discover_params discov_pnp = { .type = BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR, .uuid = BT_UUID_DECLARE_16(BT_SDP_PNP_INFO_SVCLASS), @@ -1079,6 +1160,8 @@ static int cmd_sdp_find_record(const struct shell *sh, size_t argc, char *argv[] discov = discov_hfphf; } else if (!strcmp(action, "A2SRC")) { discov = discov_a2src; + } else if (!strcmp(action, "A2SNK")) { + discov = discov_a2snk; } else if (!strcmp(action, "PNP")) { discov = discov_pnp; } else { @@ -1490,7 +1573,8 @@ SHELL_STATIC_SUBCMD_SET_CREATE(br_cmds, SHELL_CMD(l2cap, &l2cap_cmds, HELP_NONE, cmd_default_handler), SHELL_CMD_ARG(oob, NULL, NULL, cmd_oob, 1, 0), SHELL_CMD_ARG(pscan, NULL, "", cmd_connectable, 2, 0), - SHELL_CMD_ARG(sdp-find, NULL, "", cmd_sdp_find_record, 2, 0), + SHELL_CMD_ARG(sdp-find, NULL, "", + cmd_sdp_find_record, 2, 0), SHELL_CMD_ARG(switch-role, NULL, "", cmd_switch_role, 2, 0), SHELL_CMD_ARG(set-role-switchable, NULL, "", cmd_set_role_switchable, 2, 0), diff --git a/subsys/bluetooth/host/classic/shell/hfp.c b/subsys/bluetooth/host/classic/shell/hfp.c index 7911394e60910..7b19ad0ea46b2 100644 --- a/subsys/bluetooth/host/classic/shell/hfp.c +++ b/subsys/bluetooth/host/classic/shell/hfp.c @@ -86,6 +86,9 @@ static void hf_disconnected(struct bt_hfp_hf *hf) static void hf_sco_connected(struct bt_hfp_hf *hf, struct bt_conn *sco_conn) { + struct bt_conn_info info; + uint16_t handle; + bt_shell_print("HF SCO connected %p", sco_conn); if (hf_sco_conn != NULL) { @@ -94,6 +97,19 @@ static void hf_sco_connected(struct bt_hfp_hf *hf, struct bt_conn *sco_conn) } hf_sco_conn = bt_conn_ref(sco_conn); + if (bt_hci_get_conn_handle(sco_conn, &handle) < 0) { + bt_shell_warn("Failed to get SCO connection handle"); + return; + } + + if (bt_conn_get_info(sco_conn, &info) < 0) { + bt_shell_warn("Failed to get SCO connection info"); + return; + } + bt_shell_print("HF SCO info:"); + bt_shell_print(" SCO handle 0x%04X", handle); + bt_shell_print(" SCO air mode %u", info.sco.air_mode); + bt_shell_print(" SCO link type %u", info.sco.link_type); } static void hf_sco_disconnected(struct bt_conn *sco_conn, uint8_t reason) @@ -1064,6 +1080,9 @@ static void ag_disconnected(struct bt_hfp_ag *ag) static void ag_sco_connected(struct bt_hfp_ag *ag, struct bt_conn *sco_conn) { + struct bt_conn_info info; + uint16_t handle; + bt_shell_print("AG SCO connected %p", sco_conn); if (hfp_ag_sco_conn != NULL) { @@ -1072,6 +1091,19 @@ static void ag_sco_connected(struct bt_hfp_ag *ag, struct bt_conn *sco_conn) } hfp_ag_sco_conn = bt_conn_ref(sco_conn); + if (bt_hci_get_conn_handle(sco_conn, &handle) < 0) { + bt_shell_warn("Failed to get SCO connection handle"); + return; + } + + if (bt_conn_get_info(sco_conn, &info) < 0) { + bt_shell_warn("Failed to get SCO connection info"); + return; + } + bt_shell_print("AG SCO info:"); + bt_shell_print(" SCO handle 0x%04X", handle); + bt_shell_print(" SCO air mode %u", info.sco.air_mode); + bt_shell_print(" SCO link type %u", info.sco.link_type); } static void ag_sco_disconnected(struct bt_conn *sco_conn, uint8_t reason) diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 00802d402b864..f3abf67d4fb6d 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -1627,7 +1627,7 @@ struct net_buf *bt_conn_create_pdu_timeout(struct net_buf_pool *pool, } if (!buf) { - LOG_WRN("Unable to allocate buffer within timeout"); + LOG_DBG("Unable to allocate buffer within timeout"); return NULL; } @@ -2876,6 +2876,10 @@ int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info) case BT_CONN_TYPE_BR: info->br.dst = &conn->br.dst; return 0; + case BT_CONN_TYPE_SCO: + info->sco.air_mode = conn->sco.air_mode; + info->sco.link_type = conn->sco.link_type; + return 0; #endif #if defined(CONFIG_BT_ISO) case BT_CONN_TYPE_ISO: diff --git a/subsys/bluetooth/host/conn_internal.h b/subsys/bluetooth/host/conn_internal.h index 33323ee732919..c64ad277b4f8f 100644 --- a/subsys/bluetooth/host/conn_internal.h +++ b/subsys/bluetooth/host/conn_internal.h @@ -167,6 +167,8 @@ struct bt_conn_sco { uint16_t pkt_type; uint8_t dev_class[3]; uint8_t link_type; + /* Reference to BT_HCI_CODING_FORMAT_* */ + uint8_t air_mode; }; struct bt_conn_iso { diff --git a/subsys/bluetooth/host/direction.c b/subsys/bluetooth/host/direction.c index 73a196a8e20b4..b17f7fa08ab66 100644 --- a/subsys/bluetooth/host/direction.c +++ b/subsys/bluetooth/host/direction.c @@ -822,7 +822,7 @@ static int hci_df_set_conn_cte_req_enable(struct bt_conn *conn, bool enable, bt_hci_cmd_state_set_init(buf, &state, conn->flags, BT_CONN_CTE_REQ_ENABLED, enable); - err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_CONN_CTE_RX_PARAMS, buf, &rsp); + err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_CONN_CTE_REQ_ENABLE, buf, &rsp); if (err) { return err; } diff --git a/subsys/bluetooth/host/gatt.c b/subsys/bluetooth/host/gatt.c index 6161ed19ff31e..0770d6a407bb0 100644 --- a/subsys/bluetooth/host/gatt.c +++ b/subsys/bluetooth/host/gatt.c @@ -1738,7 +1738,7 @@ int bt_gatt_service_register(struct bt_gatt_service *svc) if (IS_ENABLED(CONFIG_BT_SETTINGS) && atomic_test_bit(gatt_flags, GATT_INITIALIZED) && !atomic_test_bit(gatt_sc.flags, SC_LOAD)) { - LOG_ERR("Can't register service after init and before settings are loaded."); + LOG_DBG("Can't register service after init and before settings are loaded."); return -EINVAL; } @@ -1842,7 +1842,7 @@ ssize_t bt_gatt_attr_read(struct bt_conn *conn, const struct bt_gatt_attr *attr, } if (value_len != 0U && value == NULL) { - LOG_WRN("value_len of %u provided for NULL value", value_len); + LOG_DBG("value_len of %u provided for NULL value", value_len); return BT_GATT_ERR(BT_ATT_ERR_UNLIKELY); } @@ -2540,7 +2540,7 @@ static int gatt_notify(struct bt_conn *conn, uint16_t handle, /* Confirm that the connection has the correct level of security */ if (bt_gatt_check_perm(conn, params->attr, BT_GATT_PERM_READ_ENCRYPT_MASK)) { - LOG_WRN("Link is not encrypted"); + LOG_DBG("Link is not encrypted"); return -EPERM; } @@ -2550,7 +2550,7 @@ static int gatt_notify(struct bt_conn *conn, uint16_t handle, * but follows its spirit. */ if (!bt_gatt_is_subscribed(conn, params->attr, BT_GATT_CCC_NOTIFY)) { - LOG_WRN("Device is not subscribed to characteristic"); + LOG_DBG("Device is not subscribed to characteristic"); return -EINVAL; } } @@ -2569,7 +2569,7 @@ static int gatt_notify(struct bt_conn *conn, uint16_t handle, buf = bt_att_create_pdu(conn, BT_ATT_OP_NOTIFY, sizeof(*nfy) + params->len); if (!buf) { - LOG_WRN("No buffer available to send notification"); + LOG_DBG("No buffer available to send notification"); return -ENOMEM; } @@ -2704,7 +2704,7 @@ static int gatt_indicate(struct bt_conn *conn, uint16_t handle, /* Confirm that the connection has the correct level of security */ if (bt_gatt_check_perm(conn, params->attr, BT_GATT_PERM_READ_ENCRYPT_MASK)) { - LOG_WRN("Link is not encrypted"); + LOG_DBG("Link is not encrypted"); return -EPERM; } @@ -2714,7 +2714,7 @@ static int gatt_indicate(struct bt_conn *conn, uint16_t handle, * but follows its spirit. */ if (!bt_gatt_is_subscribed(conn, params->attr, BT_GATT_CCC_INDICATE)) { - LOG_WRN("Device is not subscribed to characteristic"); + LOG_DBG("Device is not subscribed to characteristic"); return -EINVAL; } } @@ -2734,7 +2734,7 @@ static int gatt_indicate(struct bt_conn *conn, uint16_t handle, buf = bt_att_create_pdu(conn, BT_ATT_OP_INDICATE, len); if (!buf) { - LOG_WRN("No buffer available to send indication"); + LOG_DBG("No buffer available to send indication"); bt_att_req_free(req); return -ENOMEM; } @@ -2827,7 +2827,7 @@ static uint8_t notify_cb(const struct bt_gatt_attr *attr, uint16_t handle, /* Confirm that the connection has the correct level of security */ if (bt_gatt_check_perm(conn, attr, BT_GATT_PERM_READ_ENCRYPT_MASK)) { - LOG_WRN("Link is not encrypted"); + LOG_DBG("Link %p is not encrypted", (void *)conn); bt_conn_unref(conn); continue; } @@ -3028,7 +3028,7 @@ static int gatt_notify_multiple_verify_params(struct bt_conn *conn, if (bt_gatt_check_perm(conn, params[i].attr, BT_GATT_PERM_READ_ENCRYPT | BT_GATT_PERM_READ_AUTHEN)) { - LOG_WRN("Link is not encrypted"); + LOG_DBG("Link %p is not encrypted", (void *)conn); return -EPERM; } @@ -4754,7 +4754,7 @@ int bt_gatt_discover(struct bt_conn *conn, case BT_GATT_DISCOVER_ATTRIBUTE: return gatt_find_info(conn, params); default: - LOG_ERR("Invalid discovery type: %u", params->type); + LOG_DBG("Invalid discovery type: %u", params->type); } return -EINVAL; @@ -4776,6 +4776,15 @@ static void parse_read_by_uuid(struct bt_conn *conn, uint16_t handle; uint16_t len; + len = MIN(rsp->len, length); + if (len < sizeof(struct bt_att_data)) { + LOG_WRN("Bad peer: ATT read-by-uuid rsp: invalid ATTR PDU len %u", len); + params->func(conn, BT_ATT_ERR_INVALID_PDU, params, NULL, 0); + return; + } + + len -= sizeof(struct bt_att_data); + handle = sys_le16_to_cpu(data->handle); /* Handle 0 is invalid */ @@ -4784,8 +4793,6 @@ static void parse_read_by_uuid(struct bt_conn *conn, return; } - len = rsp->len > length ? length - 2 : rsp->len - 2; - LOG_DBG("handle 0x%04x len %u value %u", handle, rsp->len, len); if (!IN_RANGE(handle, req_start_handle, req_end_handle)) { @@ -5108,7 +5115,7 @@ int bt_gatt_write_without_response_cb(struct bt_conn *conn, uint16_t handle, { struct net_buf *buf; struct bt_att_write_cmd *cmd; - size_t write; + __maybe_unused size_t write; __ASSERT(conn, "invalid parameters\n"); __ASSERT(handle, "invalid parameters\n"); @@ -5139,11 +5146,7 @@ int bt_gatt_write_without_response_cb(struct bt_conn *conn, uint16_t handle, cmd->handle = sys_cpu_to_le16(handle); write = net_buf_append_bytes(buf, length, data, K_NO_WAIT, NULL, NULL); - if (write != length) { - LOG_WRN("Unable to allocate length %u: only %zu written", length, write); - net_buf_unref(buf); - return -ENOMEM; - } + __ASSERT(write == length, "Unable to allocate length %u: only %zu written", length, write); LOG_DBG("handle 0x%04x length %u", handle, length); diff --git a/subsys/bluetooth/host/hci_core.h b/subsys/bluetooth/host/hci_core.h index 5a193dfea6968..315db2d388846 100644 --- a/subsys/bluetooth/host/hci_core.h +++ b/subsys/bluetooth/host/hci_core.h @@ -171,6 +171,17 @@ struct bt_le_ext_adv { /* Advertising handle */ uint8_t handle; +#if defined(CONFIG_BT_EXT_ADV) + /* TX Power in use by the controller */ + int8_t tx_power; + + /* Advertising Set ID */ + uint8_t sid; + + /* Callbacks for the advertising set */ + const struct bt_le_ext_adv_cb *cb; +#endif /* defined(CONFIG_BT_EXT_ADV) */ + /* Current local Random Address */ bt_addr_le_t random_addr; @@ -179,13 +190,6 @@ struct bt_le_ext_adv { ATOMIC_DEFINE(flags, BT_ADV_NUM_FLAGS); -#if defined(CONFIG_BT_EXT_ADV) - const struct bt_le_ext_adv_cb *cb; - - /* TX Power in use by the controller */ - int8_t tx_power; -#endif /* defined(CONFIG_BT_EXT_ADV) */ - struct k_work_delayable lim_adv_timeout_work; /** The options used to set the parameters for this advertising set diff --git a/subsys/bluetooth/host/iso.c b/subsys/bluetooth/host/iso.c index 9013e6172d4d8..a4f30a3ba0dbf 100644 --- a/subsys/bluetooth/host/iso.c +++ b/subsys/bluetooth/host/iso.c @@ -2716,12 +2716,19 @@ static void big_disconnect(struct bt_iso_big *big, uint8_t reason) { struct bt_iso_chan *bis; + atomic_set_bit(big->flags, BT_BIG_BUSY); + SYS_SLIST_FOR_EACH_CONTAINER(&big->bis_channels, bis, node) { bis->iso->err = reason; bt_iso_chan_disconnected(bis, reason); } + /* Cleanup the BIG before calling the `stopped` so that the `big` pointer and the ISO + * channels in the `big` can be reused in the callback + */ + cleanup_big(big); + if (!sys_slist_is_empty(&iso_big_cbs)) { struct bt_iso_big_cb *listener; @@ -3158,7 +3165,6 @@ void hci_le_big_complete(struct net_buf *buf) big = big_lookup_flag(BT_BIG_PENDING); if (big) { big_disconnect(big, evt->status ? evt->status : BT_HCI_ERR_UNSPECIFIED); - cleanup_big(big); } return; @@ -3176,10 +3182,10 @@ void hci_le_big_complete(struct net_buf *buf) big->num_bis); } big_disconnect(big, evt->status ? evt->status : BT_HCI_ERR_UNSPECIFIED); - cleanup_big(big); return; } + atomic_set_bit(big->flags, BT_BIG_BUSY); i = 0; SYS_SLIST_FOR_EACH_CONTAINER(&big->bis_channels, bis, node) { const uint16_t handle = evt->handle[i++]; @@ -3190,6 +3196,8 @@ void hci_le_big_complete(struct net_buf *buf) bt_conn_set_state(iso_conn, BT_CONN_CONNECTED); } + atomic_clear_bit(big->flags, BT_BIG_BUSY); + if (!sys_slist_is_empty(&iso_big_cbs)) { struct bt_iso_big_cb *listener; @@ -3216,7 +3224,6 @@ void hci_le_big_terminate(struct net_buf *buf) LOG_DBG("BIG[%u] %p terminated", big->handle, big); big_disconnect(big, evt->reason); - cleanup_big(big); } #endif /* CONFIG_BT_ISO_BROADCASTER */ @@ -3282,6 +3289,11 @@ int bt_iso_big_terminate(struct bt_iso_big *big) return -EINVAL; } + if (atomic_test_bit(big->flags, BT_BIG_BUSY)) { + LOG_DBG("BIG %p is busy", big); + return -EBUSY; + } + bis = SYS_SLIST_PEEK_HEAD_CONTAINER(&big->bis_channels, bis, node); __ASSERT(bis != NULL, "bis was NULL"); @@ -3303,7 +3315,6 @@ int bt_iso_big_terminate(struct bt_iso_big *big) if (!err) { big_disconnect(big, BT_HCI_ERR_LOCALHOST_TERM_CONN); - cleanup_big(big); } } else { err = -EINVAL; @@ -3352,7 +3363,6 @@ void hci_le_big_sync_established(struct net_buf *buf) big = big_lookup_flag(BT_BIG_SYNCING); if (big) { big_disconnect(big, evt->status ? evt->status : BT_HCI_ERR_UNSPECIFIED); - cleanup_big(big); } return; @@ -3370,10 +3380,10 @@ void hci_le_big_sync_established(struct net_buf *buf) big->num_bis); } big_disconnect(big, evt->status ? evt->status : BT_HCI_ERR_UNSPECIFIED); - cleanup_big(big); return; } + atomic_set_bit(big->flags, BT_BIG_BUSY); i = 0; SYS_SLIST_FOR_EACH_CONTAINER(&big->bis_channels, bis, node) { const uint16_t handle = evt->handle[i++]; @@ -3384,6 +3394,8 @@ void hci_le_big_sync_established(struct net_buf *buf) bt_conn_set_state(iso_conn, BT_CONN_CONNECTED); } + atomic_clear_bit(big->flags, BT_BIG_BUSY); + if (!sys_slist_is_empty(&iso_big_cbs)) { struct bt_iso_big_cb *listener; @@ -3410,7 +3422,6 @@ void hci_le_big_sync_lost(struct net_buf *buf) LOG_DBG("BIG[%u] %p sync lost", big->handle, big); big_disconnect(big, evt->reason); - cleanup_big(big); } static int hci_le_big_create_sync(const struct bt_le_per_adv_sync *sync, struct bt_iso_big *big, @@ -3621,7 +3632,6 @@ void bt_iso_reset(void) struct bt_iso_big *big = &bigs[i]; big_disconnect(big, BT_HCI_ERR_UNSPECIFIED); - cleanup_big(big); } #endif /* CONFIG_BT_ISO_BROADCAST */ } diff --git a/subsys/bluetooth/host/iso_internal.h b/subsys/bluetooth/host/iso_internal.h index cc1ed399fef2e..dd29b5fa36006 100644 --- a/subsys/bluetooth/host/iso_internal.h +++ b/subsys/bluetooth/host/iso_internal.h @@ -51,6 +51,11 @@ enum { BT_BIG_PENDING, /* Creating a BIG as a receiver */ BT_BIG_SYNCING, + /* BIG is busy handling an HCI event. + * + * Use this to prevent API calls from modifying the BIG while the event is being processed. + */ + BT_BIG_BUSY, BT_BIG_NUM_FLAGS, }; diff --git a/subsys/bluetooth/host/shell/bt.c b/subsys/bluetooth/host/shell/bt.c index 9ecb9ff148d9d..a09afe4e3e5cb 100644 --- a/subsys/bluetooth/host/shell/bt.c +++ b/subsys/bluetooth/host/shell/bt.c @@ -6,12 +6,13 @@ /* * Copyright (c) 2017 Intel Corporation - * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2018-2025 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include @@ -2241,9 +2242,10 @@ static int cmd_directed_adv(const struct shell *sh, #endif /* CONFIG_BT_PERIPHERAL */ #if defined(CONFIG_BT_EXT_ADV) -static bool adv_param_parse(size_t argc, char *argv[], - struct bt_le_adv_param *param) +static bool parse_and_set_adv_param(size_t argc, char *argv[], struct bt_le_adv_param *param) { + static uint8_t next_adv_sid = BT_GAP_SID_MIN; + memset(param, 0, sizeof(struct bt_le_adv_param)); if (!strcmp(argv[1], "conn-scan")) { @@ -2312,7 +2314,7 @@ static bool adv_param_parse(size_t argc, char *argv[], } param->id = selected_id; - param->sid = 0; + param->sid = next_adv_sid++; if (param->peer && !(param->options & BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY)) { param->interval_min = 0; @@ -2322,6 +2324,10 @@ static bool adv_param_parse(size_t argc, char *argv[], param->interval_max = BT_GAP_ADV_FAST_INT_MAX_2; } + if (next_adv_sid > BT_GAP_SID_MAX) { + next_adv_sid = BT_GAP_SID_MIN; + } + return true; } @@ -2332,7 +2338,7 @@ static int cmd_adv_create(const struct shell *sh, size_t argc, char *argv[]) uint8_t adv_index; int err; - if (!adv_param_parse(argc, argv, ¶m)) { + if (!parse_and_set_adv_param(argc, argv, ¶m)) { shell_help(sh); return -ENOEXEC; } @@ -2363,7 +2369,7 @@ static int cmd_adv_param(const struct shell *sh, size_t argc, char *argv[]) struct bt_le_adv_param param; int err; - if (!adv_param_parse(argc, argv, ¶m)) { + if (!parse_and_set_adv_param(argc, argv, ¶m)) { shell_help(sh); return -ENOEXEC; } @@ -2648,7 +2654,7 @@ static int cmd_adv_info(const struct shell *sh, size_t argc, char *argv[]) } shell_print(sh, "Advertiser[%d] %p", selected_adv, adv); - shell_print(sh, "Id: %d, TX power: %d dBm", info.id, info.tx_power); + shell_print(sh, "Id: %d, SID %u, TX power: %d dBm", info.id, info.sid, info.tx_power); shell_print(sh, "Adv state: %d", info.ext_adv_state); print_le_addr("Address", info.addr); diff --git a/subsys/bluetooth/host/shell/iso.c b/subsys/bluetooth/host/shell/iso.c index cc2adda15cd5b..17f2839b0349a 100644 --- a/subsys/bluetooth/host/shell/iso.c +++ b/subsys/bluetooth/host/shell/iso.c @@ -36,7 +36,9 @@ #if defined(CONFIG_BT_ISO_TX) #define DEFAULT_IO_QOS \ { \ - .sdu = 40u, .phy = BT_GAP_LE_PHY_2M, .rtn = 2u, \ + .sdu = 40u, \ + .phy = BT_GAP_LE_PHY_2M, \ + .rtn = 2u, \ } #define TX_BUF_TIMEOUT K_SECONDS(1) @@ -56,8 +58,7 @@ static int64_t bis_sn_last_updated_ticks; * * @return The next sequence number to use */ -static uint32_t get_next_sn(uint32_t last_sn, int64_t *last_ticks, - uint32_t interval_us) +static uint32_t get_next_sn(uint32_t last_sn, int64_t *last_ticks, uint32_t interval_us) { int64_t uptime_ticks, delta_ticks; uint64_t delta_us; @@ -84,8 +85,8 @@ static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *in struct net_buf *buf) { if (info->flags & BT_ISO_FLAGS_VALID) { - bt_shell_print("Incoming data channel %p len %u, seq: %d, ts: %d", - chan, buf->len, info->seq_num, info->ts); + bt_shell_print("Incoming data channel %p len %u, seq: %d, ts: %d", chan, buf->len, + info->seq_num, info->ts); } } #endif /* CONFIG_BT_ISO_RX */ @@ -204,9 +205,7 @@ static long parse_interval(const struct shell *sh, const char *interval_str) return -ENOEXEC; } - if (!IN_RANGE(interval, - BT_ISO_SDU_INTERVAL_MIN, - BT_ISO_SDU_INTERVAL_MAX)) { + if (!IN_RANGE(interval, BT_ISO_SDU_INTERVAL_MIN, BT_ISO_SDU_INTERVAL_MAX)) { shell_error(sh, "Invalid interval %lu", interval); return -ENOEXEC; @@ -228,9 +227,7 @@ static long parse_latency(const struct shell *sh, const char *latency_str) return -ENOEXEC; } - if (!IN_RANGE(latency, - BT_ISO_LATENCY_MIN, - BT_ISO_LATENCY_MAX)) { + if (!IN_RANGE(latency, BT_ISO_LATENCY_MIN, BT_ISO_LATENCY_MAX)) { shell_error(sh, "Invalid latency %lu", latency); return -ENOEXEC; @@ -406,8 +403,7 @@ static int cmd_cig_create(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } - if (phy != BT_GAP_LE_PHY_1M && - phy != BT_GAP_LE_PHY_2M && + if (phy != BT_GAP_LE_PHY_1M && phy != BT_GAP_LE_PHY_2M && phy != BT_GAP_LE_PHY_CODED) { shell_error(sh, "Invalid phy %lu", phy); @@ -486,10 +482,7 @@ static int cmd_cig_term(const struct shell *sh, size_t argc, char *argv[]) static int cmd_connect(const struct shell *sh, size_t argc, char *argv[]) { - struct bt_iso_connect_param connect_param = { - .acl = default_conn, - .iso_chan = &iso_chan - }; + struct bt_iso_connect_param connect_param = {.acl = default_conn, .iso_chan = &iso_chan}; int err; if (iso_chan.iso == NULL) { @@ -517,11 +510,10 @@ static int cmd_connect(const struct shell *sh, size_t argc, char *argv[]) #if defined(CONFIG_BT_ISO_PERIPHERAL) -static int iso_accept(const struct bt_iso_accept_info *info, - struct bt_iso_chan **chan) +static int iso_accept(const struct bt_iso_accept_info *info, struct bt_iso_chan **chan) { - bt_shell_print("Incoming request from %p with CIG ID 0x%02X and CIS ID 0x%02X", - info->acl, info->cig_id, info->cis_id); + bt_shell_print("Incoming request from %p with CIG ID 0x%02X and CIS ID 0x%02X", info->acl, + info->cig_id, info->cis_id); if (iso_chan.iso) { bt_shell_print("No channels available"); @@ -590,9 +582,7 @@ static int cmd_listen(const struct shell *sh, size_t argc, char *argv[]) static int cmd_send(const struct shell *sh, size_t argc, char *argv[]) { - static uint8_t buf_data[CONFIG_BT_ISO_TX_MTU] = { - [0 ... (CONFIG_BT_ISO_TX_MTU - 1)] = 0xff - }; + static uint8_t buf_data[CONFIG_BT_ISO_TX_MTU] = {[0 ...(CONFIG_BT_ISO_TX_MTU - 1)] = 0xff}; unsigned long count = 1; struct net_buf *buf; int ret = 0; @@ -624,8 +614,7 @@ static int cmd_send(const struct shell *sh, size_t argc, char *argv[]) } len = MIN(iso_chan.qos->tx->sdu, CONFIG_BT_ISO_TX_MTU); - cis_sn_last = get_next_sn(cis_sn_last, &cis_sn_last_updated_ticks, - cis_sdu_interval_us); + cis_sn_last = get_next_sn(cis_sn_last, &cis_sn_last_updated_ticks, cis_sdu_interval_us); while (count--) { buf = net_buf_alloc(&tx_pool, TX_BUF_TIMEOUT); @@ -651,8 +640,7 @@ static int cmd_send(const struct shell *sh, size_t argc, char *argv[]) return 0; } -static int cmd_disconnect(const struct shell *sh, size_t argc, - char *argv[]) +static int cmd_disconnect(const struct shell *sh, size_t argc, char *argv[]) { int err; @@ -701,7 +689,7 @@ static struct bt_iso_chan bis_iso_chan = { .qos = &bis_iso_qos, }; -static struct bt_iso_chan *bis_channels[BIS_ISO_CHAN_COUNT] = { &bis_iso_chan }; +static struct bt_iso_chan *bis_channels[BIS_ISO_CHAN_COUNT] = {&bis_iso_chan}; #if defined(CONFIG_BT_ISO_BROADCASTER) static uint32_t bis_sdu_interval_us; @@ -712,9 +700,7 @@ NET_BUF_POOL_FIXED_DEFINE(bis_tx_pool, BIS_ISO_CHAN_COUNT, static int cmd_broadcast(const struct shell *sh, size_t argc, char *argv[]) { - static uint8_t buf_data[CONFIG_BT_ISO_TX_MTU] = { - [0 ... (CONFIG_BT_ISO_TX_MTU - 1)] = 0xff - }; + static uint8_t buf_data[CONFIG_BT_ISO_TX_MTU] = {[0 ...(CONFIG_BT_ISO_TX_MTU - 1)] = 0xff}; unsigned long count = 1; struct net_buf *buf; int ret = 0; @@ -746,8 +732,7 @@ static int cmd_broadcast(const struct shell *sh, size_t argc, char *argv[]) } len = MIN(bis_iso_chan.qos->tx->sdu, CONFIG_BT_ISO_TX_MTU); - bis_sn_last = get_next_sn(bis_sn_last, &bis_sn_last_updated_ticks, - bis_sdu_interval_us); + bis_sn_last = get_next_sn(bis_sn_last, &bis_sn_last_updated_ticks, bis_sdu_interval_us); while (count--) { buf = net_buf_alloc(&bis_tx_pool, TX_BUF_TIMEOUT); @@ -790,8 +775,8 @@ static int cmd_big_create(const struct shell *sh, size_t argc, char *argv[]) bis_iso_qos.tx->rtn = 2; bis_iso_qos.tx->sdu = CONFIG_BT_ISO_TX_MTU; - bis_sdu_interval_us = param.interval = 10000; /* us */ - param.latency = 20; /* ms */ + bis_sdu_interval_us = param.interval = 10000; /* us */ + param.latency = 20; /* ms */ param.bis_channels = bis_channels; param.num_bis = BIS_ISO_CHAN_COUNT; param.encryption = false; @@ -800,10 +785,11 @@ static int cmd_big_create(const struct shell *sh, size_t argc, char *argv[]) if (argc > 1) { if (!strcmp(argv[1], "enc")) { - uint8_t bcode_len = hex2bin(argv[1], strlen(argv[1]), param.bcode, - sizeof(param.bcode)); + size_t bcode_len = + hex2bin(argv[2], strlen(argv[2]), param.bcode, sizeof(param.bcode)); + if (!bcode_len || bcode_len != sizeof(param.bcode)) { - shell_error(sh, "Invalid Broadcast Code Length"); + shell_error(sh, "Invalid Broadcast Code Length %zu", bcode_len); return -ENOEXEC; } param.encryption = true; @@ -928,8 +914,7 @@ static int cmd_big_sync(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } - if (!IN_RANGE(sync_timeout, - BT_ISO_SYNC_TIMEOUT_MIN, + if (!IN_RANGE(sync_timeout, BT_ISO_SYNC_TIMEOUT_MIN, BT_ISO_SYNC_TIMEOUT_MAX)) { shell_error(sh, "Invalid sync_timeout %lu", sync_timeout); @@ -947,8 +932,8 @@ static int cmd_big_sync(const struct shell *sh, size_t argc, char *argv[]) } memset(param.bcode, 0, sizeof(param.bcode)); - bcode_len = hex2bin(argv[i], strlen(argv[i]), param.bcode, - sizeof(param.bcode)); + bcode_len = + hex2bin(argv[i], strlen(argv[i]), param.bcode, sizeof(param.bcode)); if (bcode_len == 0) { shell_error(sh, "Invalid Broadcast Code"); @@ -991,7 +976,8 @@ static int cmd_big_term(const struct shell *sh, size_t argc, char *argv[]) } #endif /* CONFIG_BT_ISO_BROADCAST*/ -SHELL_STATIC_SUBCMD_SET_CREATE(iso_cmds, +SHELL_STATIC_SUBCMD_SET_CREATE( + iso_cmds, #if defined(CONFIG_BT_ISO_UNICAST) #if defined(CONFIG_BT_ISO_CENTRAL) SHELL_CMD_ARG(cig_create, NULL, @@ -1001,14 +987,14 @@ SHELL_STATIC_SUBCMD_SET_CREATE(iso_cmds, SHELL_CMD_ARG(cig_term, NULL, "Terminate the CIG", cmd_cig_term, 1, 0), #if defined(CONFIG_BT_SMP) SHELL_CMD_ARG(connect, NULL, "Connect ISO Channel [security level]", cmd_connect, 1, 1), -#else /* !CONFIG_BT_SMP */ +#else /* !CONFIG_BT_SMP */ SHELL_CMD_ARG(connect, NULL, "Connect ISO Channel", cmd_connect, 1, 0), #endif /* CONFIG_BT_SMP */ #endif /* CONFIG_BT_ISO_CENTRAL */ #if defined(CONFIG_BT_ISO_PERIPHERAL) #if defined(CONFIG_BT_SMP) SHELL_CMD_ARG(listen, NULL, " [security level]", cmd_listen, 2, 1), -#else /* !CONFIG_BT_SMP */ +#else /* !CONFIG_BT_SMP */ SHELL_CMD_ARG(listen, NULL, "", cmd_listen, 2, 0), #endif /* CONFIG_BT_SMP */ #endif /* CONFIG_BT_ISO_PERIPHERAL */ @@ -1019,22 +1005,21 @@ SHELL_STATIC_SUBCMD_SET_CREATE(iso_cmds, SHELL_CMD_ARG(tx_sync_read_cis, NULL, "Read CIS TX sync info", cmd_tx_sync_read_cis, 1, 0), #endif /* CONFIG_BT_ISO_UNICAST */ #if defined(CONFIG_BT_ISO_BROADCASTER) - SHELL_CMD_ARG(create-big, NULL, "Create a BIG as a broadcaster [enc ]", + SHELL_CMD_ARG(create - big, NULL, "Create a BIG as a broadcaster [enc ]", cmd_big_create, 1, 2), SHELL_CMD_ARG(broadcast, NULL, "Broadcast on ISO channels", cmd_broadcast, 1, 1), SHELL_CMD_ARG(tx_sync_read_bis, NULL, "Read BIS TX sync info", cmd_tx_sync_read_bis, 1, 0), #endif /* CONFIG_BT_ISO_BROADCASTER */ #if defined(CONFIG_BT_ISO_SYNC_RECEIVER) - SHELL_CMD_ARG(sync-big, NULL, + SHELL_CMD_ARG(sync - big, NULL, "Synchronize to a BIG as a receiver [mse] " "[timeout] [enc ]", cmd_big_sync, 2, 4), #endif /* CONFIG_BT_ISO_SYNC_RECEIVER */ #if defined(CONFIG_BT_ISO_BROADCAST) - SHELL_CMD_ARG(term-big, NULL, "Terminate a BIG", cmd_big_term, 1, 0), + SHELL_CMD_ARG(term - big, NULL, "Terminate a BIG", cmd_big_term, 1, 0), #endif /* CONFIG_BT_ISO_BROADCAST */ - SHELL_SUBCMD_SET_END -); + SHELL_SUBCMD_SET_END); static int cmd_iso(const struct shell *sh, size_t argc, char **argv) { @@ -1049,5 +1034,4 @@ static int cmd_iso(const struct shell *sh, size_t argc, char **argv) return -EINVAL; } -SHELL_CMD_ARG_REGISTER(iso, &iso_cmds, "Bluetooth ISO shell commands", - cmd_iso, 1, 1); +SHELL_CMD_ARG_REGISTER(iso, &iso_cmds, "Bluetooth ISO shell commands", cmd_iso, 1, 1); diff --git a/subsys/bluetooth/mesh/pb_adv.c b/subsys/bluetooth/mesh/pb_adv.c index c6b3f77816548..1f77f782c8500 100644 --- a/subsys/bluetooth/mesh/pb_adv.c +++ b/subsys/bluetooth/mesh/pb_adv.c @@ -522,7 +522,7 @@ static void gen_prov_cont(struct prov_rx *rx, struct net_buf_simple *buf) return; } - if (seg > link.rx.last_seg) { + if (seg > link.rx.last_seg || seg == 0) { LOG_ERR("Invalid segment index %u", seg); prov_failed(PROV_ERR_NVAL_FMT); return; @@ -634,6 +634,13 @@ static void gen_prov_start(struct prov_rx *rx, struct net_buf_simple *buf) return; } + if (link.rx.buf->len < buf->len) { + LOG_ERR("Invalid declared provisionig PDU length (%u > %u)", buf->len, + link.rx.buf->len); + prov_failed(PROV_ERR_NVAL_FMT); + return; + } + if (START_LAST_SEG(rx->gpc) > 0 && link.rx.buf->len <= 20U) { LOG_ERR("Too small total length for multi-segment PDU"); prov_failed(PROV_ERR_NVAL_FMT); diff --git a/subsys/bluetooth/services/Kconfig.dis b/subsys/bluetooth/services/Kconfig.dis index 6a15853903dbc..d8b14fe568617 100644 --- a/subsys/bluetooth/services/Kconfig.dis +++ b/subsys/bluetooth/services/Kconfig.dis @@ -233,7 +233,7 @@ config BT_DIS_SYSTEM_ID_OUI help The OUI is a 24-bit number issued by the IEEE Registration Authority. System ID characteristic in Device Information Service. - Shall contain an Organisationally Unique Identifier (OUI) followed by a manufacturer-defined indentifier unique for the device. + Shall contain an Organisationally Unique Identifier (OUI) followed by a manufacturer-defined identifier unique for the device. config BT_DIS_SYSTEM_ID_IDENTIFIER hex "Manufacturer-defined unique identifier." diff --git a/subsys/cpu_freq/CMakeLists.txt b/subsys/cpu_freq/CMakeLists.txt new file mode 100644 index 0000000000000..6d5ceb78e6bb5 --- /dev/null +++ b/subsys/cpu_freq/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}) + +zephyr_library() +zephyr_library_sources(cpu_freq.c) + +# Policy selection +if(CONFIG_CPU_FREQ_POLICY_NONE) + message(FATAL_ERROR "No CPU frequency policy selected. Please choose a valid policy in Kconfig.") +endif() + +zephyr_sources_ifdef(CONFIG_CPU_FREQ_POLICY_ON_DEMAND policies/on_demand/on_demand.c) diff --git a/subsys/cpu_freq/Kconfig b/subsys/cpu_freq/Kconfig new file mode 100644 index 0000000000000..e44bc01ec6926 --- /dev/null +++ b/subsys/cpu_freq/Kconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +config HAS_CPU_FREQ + bool + +menuconfig CPU_FREQ + bool "CPU Frequency Scaling Subsystem" + select EXPERIMENTAL + depends on !SMP + depends on HAS_CPU_FREQ + help + CPU Frequency scaling subsystem + +if CPU_FREQ + +module = CPU_FREQ +module-str = CPU Frequency Scaling +source "subsys/logging/Kconfig.template.log_config" + +config CPU_FREQ_INTERVAL_MS + int "CPU Freq evaluation interval" + default 1000 + help + Controls the interval (in milliseconds) at which the CPU Frequency + subsystem runs and evaluates the current policy. + +choice CPU_FREQ_POLICY + prompt "CPU Frequency Scaling Policy" + default CPU_FREQ_POLICY_NONE + help + The policy algorithm to use when using the CPU freq subsystem. + +config CPU_FREQ_POLICY_NONE + bool "No selected policy" + help + Kconfig placeholder if no policy is chosen. This Kconfig will produce a build error + +config CPU_FREQ_POLICY_ON_DEMAND + bool "On-demand Policy" + select CPU_LOAD_METRIC + +endchoice # CPU_FREQ_POLICY + +endif # CPU_FREQ diff --git a/subsys/cpu_freq/cpu_freq.c b/subsys/cpu_freq/cpu_freq.c new file mode 100644 index 0000000000000..63dfa4f2dae0d --- /dev/null +++ b/subsys/cpu_freq/cpu_freq.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(cpu_freq, CONFIG_CPU_FREQ_LOG_LEVEL); + +static void cpu_freq_timer_handler(struct k_timer *timer); +K_TIMER_DEFINE(cpu_freq_timer, cpu_freq_timer_handler, NULL); + +/* + * Timer that expires periodically to execute the selected policy algorithm + * and pass the next P-state to the P-state driver. + */ +static void cpu_freq_timer_handler(struct k_timer *timer) +{ + int ret; + + /* Get next performance state */ + const struct pstate *pstate_next; + + ret = cpu_freq_policy_select_pstate(&pstate_next); + if (ret) { + LOG_ERR("Failed to get pstate: %d", ret); + return; + } + + /* Set performance state using pstate driver */ + ret = cpu_freq_pstate_set(pstate_next); + if (ret) { + LOG_ERR("Failed to set performance state: %d", ret); + return; + } +} + +static int cpu_freq_init(void) +{ + k_timer_start(&cpu_freq_timer, K_MSEC(CONFIG_CPU_FREQ_INTERVAL_MS), + K_MSEC(CONFIG_CPU_FREQ_INTERVAL_MS)); + LOG_INF("CPU frequency subsystem initialized with interval %d ms", + CONFIG_CPU_FREQ_INTERVAL_MS); + return 0; +} + +SYS_INIT(cpu_freq_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/subsys/cpu_freq/policies/on_demand/on_demand.c b/subsys/cpu_freq/policies/on_demand/on_demand.c new file mode 100644 index 0000000000000..79e07d810119b --- /dev/null +++ b/subsys/cpu_freq/policies/on_demand/on_demand.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(cpu_freq_policy_on_demand, CONFIG_CPU_FREQ_LOG_LEVEL); + +const struct pstate *soc_pstates[] = { + DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(performance_states), PSTATE_DT_GET, (,)) +}; + +/* + * On-demand policy scans the list of P-states from the devicetree and selects the + * first P-state where the cpu_load is greater than or equal to the trigger threshold + * of the P-state. + */ +int cpu_freq_policy_select_pstate(const struct pstate **pstate_out) +{ + int cpu_load; + + if (pstate_out == NULL) { + LOG_ERR("On-Demand Policy: pstate_out is NULL"); + return -EINVAL; + } + + cpu_load = cpu_load_get(0); + if (cpu_load < 0) { + LOG_ERR("Unable to retrieve CPU load"); + return cpu_load; + } + + LOG_DBG("Current CPU Load: %d%%", cpu_load); + + for (int i = 0; i < ARRAY_SIZE(soc_pstates); i++) { + const struct pstate *state = soc_pstates[i]; + + if (cpu_load >= state->load_threshold) { + *pstate_out = state; + LOG_DBG("On-Demand Policy: Selected P-state %d with load_threshold=%d%%", i, + state->load_threshold); + return 0; + } + } + + LOG_ERR("On-Demand Policy: No suitable P-state found for CPU load %d%%", cpu_load); + + return -ENOTSUP; +} diff --git a/subsys/cpu_load/CMakeLists.txt b/subsys/cpu_load/CMakeLists.txt new file mode 100644 index 0000000000000..82fc600a5e393 --- /dev/null +++ b/subsys/cpu_load/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}) + +zephyr_library() +zephyr_library_sources(cpu_load.c) diff --git a/subsys/cpu_load/Kconfig b/subsys/cpu_load/Kconfig new file mode 100644 index 0000000000000..7772a6695e717 --- /dev/null +++ b/subsys/cpu_load/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +menuconfig CPU_LOAD_METRIC + bool "CPU Load Subsystem" + select EXPERIMENTAL + select THREAD_RUNTIME_STATS + select SCHED_THREAD_USAGE + select SCHED_THREAD_USAGE_ALL + select SCHED_THREAD_USAGE_AUTO_ENABLE + help + CPU Load subsystem + +if CPU_LOAD_METRIC + +module = CPU_LOAD +module-str = CPU Load Metric +source "subsys/logging/Kconfig.template.log_config" + +endif # CPU_LOAD_METRIC diff --git a/subsys/cpu_load/cpu_load.c b/subsys/cpu_load/cpu_load.c new file mode 100644 index 0000000000000..ba0c13d40cbf6 --- /dev/null +++ b/subsys/cpu_load/cpu_load.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +LOG_MODULE_REGISTER(cpu_load_metric, CONFIG_CPU_LOAD_LOG_LEVEL); + +static uint64_t execution_cycles_prev; +static uint64_t total_cycles_prev; + +int cpu_load_get(int cpu_id) +{ + int ret; + int load; + uint64_t execution_cycles; + uint64_t total_cycles; + + struct k_thread_runtime_stats cpu_query; + + ret = k_thread_runtime_stats_cpu_get(cpu_id, &cpu_query); + if (ret) { + LOG_ERR("Could not retrieve runtime statistics from scheduler"); + return ret; + } + + execution_cycles = cpu_query.execution_cycles - execution_cycles_prev; + total_cycles = cpu_query.total_cycles - total_cycles_prev; + + LOG_DBG("Execution cycles: %llu, Total cycles: %llu", execution_cycles, total_cycles); + + if (execution_cycles == 0) { + load = 0; + } else { + load = (int)((100 * total_cycles) / execution_cycles); + } + + execution_cycles_prev = cpu_query.execution_cycles; + total_cycles_prev = cpu_query.total_cycles; + + return load; +} diff --git a/subsys/crc/CMakeLists.txt b/subsys/crc/CMakeLists.txt new file mode 100644 index 0000000000000..0413b1b2158c9 --- /dev/null +++ b/subsys/crc/CMakeLists.txt @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(crc4_sw.c) +zephyr_library_sources(crc8_sw.c) +zephyr_library_sources(crc16_sw.c) +zephyr_library_sources(crc7_sw.c) +zephyr_library_sources(crc24_sw.c) +zephyr_library_sources(crc32c_sw.c) +zephyr_library_sources(crc32_sw.c) +zephyr_library_sources(crc32k_4_2_sw.c) + +zephyr_library_sources_ifdef(CONFIG_CRC_HW_HANDLER crc_hardware.c) +zephyr_library_sources_ifdef(CONFIG_CRC_SHELL crc_shell.c) diff --git a/subsys/crc/Kconfig b/subsys/crc/Kconfig new file mode 100644 index 0000000000000..c8403734aba69 --- /dev/null +++ b/subsys/crc/Kconfig @@ -0,0 +1,163 @@ +# Copyright (c) 2016,2023 Intel Corporation +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +DT_CHOSEN_Z_CRC := zephyr,crc + +menuconfig CRC + bool "Cyclic redundancy check (CRC) Support" + help + Enable use of CRC. + +if CRC + +module = CRC +module-str = CRC +source "subsys/logging/Kconfig.template.log_config" + +config CRC_HW_HANDLER + bool "CRC Hardware Accelerator" + default y if $(dt_chosen_enabled,$(DT_CHOSEN_Z_CRC)) + select CRC_DRIVER + help + Enable use of CRC hardware + +config CRC4 + bool "CRC-4 (Generic)" + depends on CRC_DRIVER_HAS_CRC4 + default y + help + Implements a generic CRC-4 algorithm. This is suitable for platforms + without hardware CRC support. Offers flexibility but has lower performance + compared to hardware-based implementations. + +config CRC4_TI + bool "CRC-4 (TI Polynomial)" + depends on CRC_DRIVER_HAS_CRC4_TI + default y + help + Implements the TI-specific CRC-4 algorithm. Commonly used in low-level + embedded communication where minimal CRC overhead is needed. + +config CRC7_BE + bool "CRC-7 (Big Endian)" + depends on CRC_DRIVER_HAS_CRC7_BE + default y + help + Implements a CRC-7 algorithm with Big Endian bit order. Often used + in SD card protocols and other serial communication standards. + +config CRC8 + bool "CRC-8 (Generic)" + depends on CRC_DRIVER_HAS_CRC8 + default y + help + Implements a generic CRC-8 algorithm. Useful for small data integrity + checks such as checksums and simple communication protocols. + +config CRC8_ROHC + bool "CRC-8 (ROHC)" + depends on CRC_DRIVER_HAS_CRC8_ROHC + default y + help + Implements the CRC-8 ROHC (Robust Header Compression) algorithm, + typically used in compressed IP header protocols and networking. + +config CRC8_CCITT + bool "CRC-8 (CCITT)" + depends on CRC_DRIVER_HAS_CRC8_CCITT + default y + help + Implements the CRC-8 CCITT polynomial. Commonly used in + telecommunications and low-power sensor protocols. + +config CRC16 + bool "CRC-16 (Generic)" + depends on CRC_DRIVER_HAS_CRC16 + default y + help + Implements the generic CRC-16 algorithm. Frequently used in + storage, file transmission, and basic serial communication protocols. + +config CRC16_ANSI + bool "CRC-16 (ANSI)" + depends on CRC_DRIVER_HAS_CRC16_ANSI + default y + help + Implements the ANSI variant of CRC-16, also known as CRC-16-IBM. + Commonly applied in legacy serial and file systems. + +config CRC16_CCITT + bool "CRC-16 (CCITT)" + depends on CRC_DRIVER_HAS_CRC16_CCITT + default y + help + Implements the CCITT variant of CRC-16, widely used in + telecommunication systems such as XMODEM and HDLC protocols. + +config CRC16_ITU_T + bool "CRC-16 (ITU-T)" + depends on CRC_DRIVER_HAS_CRC16_ITU_T + default y + help + Implements the ITU-T (formerly CCITT) CRC-16 variant. + Popular in modem protocols and wireless communication standards. + +config CRC16_REFLECT + bool "CRC-16 (Reflected)" + depends on CRC_DRIVER_HAS_CRC16_REFLECT + default y + help + Implements the reflected (bit-reversed) variant of CRC-16-CCITT. + Useful in systems that process data in LSB-first order. + +config CRC24_PGP + bool "CRC-24 (PGP)" + depends on CRC_DRIVER_HAS_CRC24_PGP + default y + help + Implements a CRC24 algorithm, used in applications like Bluetooth + and certain cryptographic protocols. + +config CRC32_C + bool "CRC-32C" + depends on CRC_DRIVER_HAS_CRC32_C + default y + help + Implements the CRC32-C (Castagnoli) algorithm, optimized for + high-performance applications such as storage, networking, + and error detection in modern processors. + +config CRC32_IEEE + bool "CRC-32 (IEEE)" + depends on CRC_DRIVER_HAS_CRC32_IEEE + default y + help + Implements the CRC32-IEEE (CRC-32) algorithm, commonly used + in Ethernet, ZIP file integrity checks, and other standard + networking and storage applications. + + +config CRC32_K_4_2 + bool "CRC-32K/4.2" + depends on CRC_DRIVER_HAS_CRC32_K_4_2 + default y + help + Implement the CRC-32K/4.2 algorithm, a variant of the standard + CRC32-IEEE used in Ethernet, ZIP files, and other data integrity + applications. + +config CRC32_K_4_2_TABLE_256 + bool "CRC-32K/4.2 Table 256" + help + Enables the software implementation of the CRC-32K/4.2 algorithm + using a 256-entry lookup table for faster computation. + +config CRC_SHELL + bool "CRC Shell" + depends on SHELL + select POSIX_C_LIB_EXT + help + Enable CRC checking for memory regions from the shell. + +endif # CRC diff --git a/lib/crc/crc16_sw.c b/subsys/crc/crc16_sw.c similarity index 75% rename from lib/crc/crc16_sw.c rename to subsys/crc/crc16_sw.c index 50684e25722d2..eea8be335472b 100644 --- a/lib/crc/crc16_sw.c +++ b/subsys/crc/crc16_sw.c @@ -6,7 +6,7 @@ #include -uint16_t crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) { uint16_t crc = seed; size_t i, j; @@ -23,11 +23,10 @@ uint16_t crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) } } - return crc; } -uint16_t crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) { uint16_t crc = seed; size_t i, j; @@ -44,12 +43,10 @@ uint16_t crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t } } - return crc; } - -uint16_t crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) { for (; len > 0; len--) { uint8_t e, f; @@ -63,7 +60,7 @@ uint16_t crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) return seed; } -uint16_t crc16_itu_t(uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16_itu_t(uint16_t seed, const uint8_t *src, size_t len) { for (; len > 0; len--) { seed = (seed >> 8U) | (seed << 8U); diff --git a/lib/crc/crc24_sw.c b/subsys/crc/crc24_sw.c similarity index 95% rename from lib/crc/crc24_sw.c rename to subsys/crc/crc24_sw.c index f46c7f2f585d2..119e71bc37ed0 100644 --- a/lib/crc/crc24_sw.c +++ b/subsys/crc/crc24_sw.c @@ -9,15 +9,13 @@ #include -#define CRC24_PGP_POLY 0x01864cfbU - -uint32_t crc24_pgp(const uint8_t *data, size_t len) +uint32_t __weak crc24_pgp(const uint8_t *data, size_t len) { return crc24_pgp_update(CRC24_PGP_INITIAL_VALUE, data, len) & CRC24_FINAL_VALUE_MASK; } /* CRC-24 implementation from the section 6.1 of the RFC 4880 */ -uint32_t crc24_pgp_update(uint32_t crc, const uint8_t *data, size_t len) +uint32_t __weak crc24_pgp_update(uint32_t crc, const uint8_t *data, size_t len) { int i; diff --git a/lib/crc/crc32_sw.c b/subsys/crc/crc32_sw.c similarity index 63% rename from lib/crc/crc32_sw.c rename to subsys/crc/crc32_sw.c index f2f2712ff5bf3..56c2490072b6c 100644 --- a/lib/crc/crc32_sw.c +++ b/subsys/crc/crc32_sw.c @@ -6,18 +6,17 @@ #include -uint32_t crc32_ieee(const uint8_t *data, size_t len) +uint32_t __weak crc32_ieee(const uint8_t *data, size_t len) { return crc32_ieee_update(0x0, data, len); } -uint32_t crc32_ieee_update(uint32_t crc, const uint8_t *data, size_t len) +uint32_t __weak crc32_ieee_update(uint32_t crc, const uint8_t *data, size_t len) { /* crc table generated from polynomial 0xedb88320 */ static const uint32_t table[16] = { - 0x00000000U, 0x1db71064U, 0x3b6e20c8U, 0x26d930acU, - 0x76dc4190U, 0x6b6b51f4U, 0x4db26158U, 0x5005713cU, - 0xedb88320U, 0xf00f9344U, 0xd6d6a3e8U, 0xcb61b38cU, + 0x00000000U, 0x1db71064U, 0x3b6e20c8U, 0x26d930acU, 0x76dc4190U, 0x6b6b51f4U, + 0x4db26158U, 0x5005713cU, 0xedb88320U, 0xf00f9344U, 0xd6d6a3e8U, 0xcb61b38cU, 0x9b64c2b0U, 0x86d3d2d4U, 0xa00ae278U, 0xbdbdf21cU, }; diff --git a/lib/crc/crc32c_sw.c b/subsys/crc/crc32c_sw.c similarity index 65% rename from lib/crc/crc32c_sw.c rename to subsys/crc/crc32c_sw.c index 4d885bcb0df71..c6a38b7c799b4 100644 --- a/lib/crc/crc32c_sw.c +++ b/subsys/crc/crc32c_sw.c @@ -8,24 +8,23 @@ /* crc table generated from polynomial 0x1EDC6F41UL (Castagnoli) */ static const uint32_t crc32c_table[16] = { - 0x00000000UL, 0x105EC76FUL, 0x20BD8EDEUL, 0x30E349B1UL, - 0x417B1DBCUL, 0x5125DAD3UL, 0x61C69362UL, 0x7198540DUL, - 0x82F63B78UL, 0x92A8FC17UL, 0xA24BB5A6UL, 0xB21572C9UL, - 0xC38D26C4UL, 0xD3D3E1ABUL, 0xE330A81AUL, 0xF36E6F75UL + 0x00000000UL, 0x105EC76FUL, 0x20BD8EDEUL, 0x30E349B1UL, 0x417B1DBCUL, 0x5125DAD3UL, + 0x61C69362UL, 0x7198540DUL, 0x82F63B78UL, 0x92A8FC17UL, 0xA24BB5A6UL, 0xB21572C9UL, + 0xC38D26C4UL, 0xD3D3E1ABUL, 0xE330A81AUL, 0xF36E6F75UL, }; /* This value needs to be XORed with the final crc value once crc for * the entire stream is calculated. This is a requirement of crc32c algo. */ -#define CRC32C_XOR_OUT 0xFFFFFFFFUL +#define CRC32C_XOR_OUT 0xFFFFFFFFUL /* The crc32c algorithm requires the below value as Init value at the * beginning of the stream. */ -#define CRC32C_INIT 0xFFFFFFFFUL +#define CRC32C_INIT 0xFFFFFFFFUL -uint32_t crc32_c(uint32_t crc, const uint8_t *data, - size_t len, bool first_pkt, bool last_pkt) +uint32_t __weak crc32_c(uint32_t crc, const uint8_t *data, size_t len, bool first_pkt, + bool last_pkt) { if (first_pkt) { crc = CRC32C_INIT; diff --git a/lib/crc/crc32k_4_2_sw.c b/subsys/crc/crc32k_4_2_sw.c similarity index 97% rename from lib/crc/crc32k_4_2_sw.c rename to subsys/crc/crc32k_4_2_sw.c index 9208d780de92d..419ecb2f48567 100644 --- a/lib/crc/crc32k_4_2_sw.c +++ b/subsys/crc/crc32k_4_2_sw.c @@ -6,7 +6,7 @@ #include -uint32_t crc32_k_4_2_update(uint32_t crc, const uint8_t *const data, const size_t len) +uint32_t __weak crc32_k_4_2_update(uint32_t crc, const uint8_t *const data, const size_t len) { #if defined(CONFIG_CRC32_K_4_2_TABLE_256) diff --git a/lib/crc/crc4_sw.c b/subsys/crc/crc4_sw.c similarity index 69% rename from lib/crc/crc4_sw.c rename to subsys/crc/crc4_sw.c index e636a2c8fae26..b541435f0df92 100644 --- a/lib/crc/crc4_sw.c +++ b/subsys/crc/crc4_sw.c @@ -6,8 +6,8 @@ #include -uint8_t crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, - bool reversed) +uint8_t __weak crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) { uint8_t crc = initial_value; size_t i, j, k; @@ -37,14 +37,14 @@ uint8_t crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial return crc & 0xF; } -uint8_t crc4_ti(uint8_t seed, const uint8_t *src, size_t len) +uint8_t __weak crc4_ti(uint8_t seed, const uint8_t *src, size_t len) { - static const uint8_t lookup[8] = { 0x03, 0x65, 0xcf, 0xa9, 0xb8, 0xde, 0x74, 0x12 }; + static const uint8_t lookup[8] = {0x03, 0x65, 0xcf, 0xa9, 0xb8, 0xde, 0x74, 0x12}; uint8_t index; for (size_t i = 0; i < len; i++) { for (size_t j = 0U; j < 2U; j++) { - index = seed ^ ((src[i] >> (4*(1-j))) & 0xf); + index = seed ^ ((src[i] >> (4 * (1 - j))) & 0xf); seed = (lookup[index >> 1] >> (1 - (index & 1)) * 4) & 0xf; } } diff --git a/lib/crc/crc7_sw.c b/subsys/crc/crc7_sw.c similarity index 78% rename from lib/crc/crc7_sw.c rename to subsys/crc/crc7_sw.c index 970c5734c7ab3..1d004c782cfd4 100644 --- a/lib/crc/crc7_sw.c +++ b/subsys/crc/crc7_sw.c @@ -6,7 +6,7 @@ #include -uint8_t crc7_be(uint8_t seed, const uint8_t *src, size_t len) +uint8_t __weak crc7_be(uint8_t seed, const uint8_t *src, size_t len) { while (len-- != 0UL) { uint8_t e = seed ^ *src++; diff --git a/lib/crc/crc8_sw.c b/subsys/crc/crc8_sw.c similarity index 77% rename from lib/crc/crc8_sw.c rename to subsys/crc/crc8_sw.c index 59900e14a62f1..ac151157abcee 100644 --- a/lib/crc/crc8_sw.c +++ b/subsys/crc/crc8_sw.c @@ -10,15 +10,15 @@ static const uint8_t crc8_ccitt_small_table[16] = { 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d + 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, }; static const uint8_t crc8_rohc_small_table[16] = { 0x00, 0x1c, 0x38, 0x24, 0x70, 0x6c, 0x48, 0x54, - 0xe0, 0xfc, 0xd8, 0xc4, 0x90, 0x8c, 0xa8, 0xb4 + 0xe0, 0xfc, 0xd8, 0xc4, 0x90, 0x8c, 0xa8, 0xb4, }; -uint8_t crc8_ccitt(uint8_t val, const void *buf, size_t cnt) +uint8_t __weak crc8_ccitt(uint8_t val, const void *buf, size_t cnt) { size_t i; const uint8_t *p = buf; @@ -31,7 +31,7 @@ uint8_t crc8_ccitt(uint8_t val, const void *buf, size_t cnt) return val; } -uint8_t crc8_rohc(uint8_t val, const void *buf, size_t cnt) +uint8_t __weak crc8_rohc(uint8_t val, const void *buf, size_t cnt) { size_t i; const uint8_t *p = buf; @@ -44,8 +44,8 @@ uint8_t crc8_rohc(uint8_t val, const void *buf, size_t cnt) return val; } -uint8_t crc8(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, - bool reversed) +uint8_t __weak crc8(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) { uint8_t crc = initial_value; size_t i, j; diff --git a/subsys/crc/crc_hardware.c b/subsys/crc/crc_hardware.c new file mode 100644 index 0000000000000..443b1e782609e --- /dev/null +++ b/subsys/crc/crc_hardware.c @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(crc, CONFIG_CRC_LOG_LEVEL); + +#include +#include + +/* This value needs to be XORed with the final crc value once crc for + * the entire stream is calculated. This is a requirement of crc32c algo. + */ +#define CRC32C_XOR_OUT 0xFFFFFFFFUL + +static const struct device *const crc_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + +static int crc_operation(const struct device *const dev, struct crc_ctx *ctx, const uint8_t *src, + size_t len) +{ + int ret; + + if (!device_is_ready((crc_dev))) { + return -ENODEV; + } + + ret = crc_begin(crc_dev, ctx); + if (ret != 0) { + return ret; + } + + ret = crc_update(crc_dev, ctx, src, len); + if (ret != 0) { + return ret; + } + + ret = crc_finish(crc_dev, ctx); + if (ret != 0) { + return ret; + } + + return 0; +} + +#ifdef CONFIG_CRC4 +uint8_t crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) +{ + uint8_t flag_reversed; + int ret; + + if (reversed) { + flag_reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT; + } + + struct crc_ctx ctx = { + .type = CRC4, + .polynomial = polynomial, + .seed = initial_value, + .reversed = flag_reversed, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result & 0x0F; +} +#endif + +#ifdef CONFIG_CRC4_TI +uint8_t crc4_ti(uint8_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC4, + .polynomial = CRC4_POLY, + .seed = seed, + .reversed = 0, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result & 0x0F; +} +#endif + +#ifdef CONFIG_CRC7_BE +uint8_t crc7_be(uint8_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC7_BE, + .polynomial = CRC7_BE_POLY, + .seed = seed, + .reversed = 0, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result & 0x7F; +} +#endif + +#ifdef CONFIG_CRC8 +uint8_t crc8(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) +{ + uint8_t flag_reversed; + int ret; + + if (reversed) { + flag_reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT; + } + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = polynomial, + .seed = initial_value, + .reversed = flag_reversed, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC8_ROHC +uint8_t crc8_rohc(uint8_t initial_value, const void *buf, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = initial_value, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC8_CCITT +uint8_t crc8_ccitt(uint8_t initial_value, const void *buf, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = initial_value, + .reversed = 0, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16 +uint16_t crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = seed, + .reversed = 0, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16_REFLECT +uint16_t crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = seed, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16_CCITT +uint16_t crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = seed, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16_ITU_T +uint16_t crc16_itu_t(uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = seed, + .reversed = 0, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC24_PGP +uint32_t crc24_pgp_update(uint32_t crc, const uint8_t *data, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC24_PGP, + .polynomial = CRC24_PGP_POLY, + .seed = CRC24_PGP_INITIAL_VALUE, + .reversed = 0, + }; + + ret = crc_operation(crc_dev, &ctx, data, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} + +uint32_t crc24_pgp(const uint8_t *data, size_t len) +{ + return crc24_pgp_update(CRC24_PGP_INITIAL_VALUE, data, len) & CRC24_FINAL_VALUE_MASK; +} +#endif + +#ifdef CONFIG_CRC32_C +uint32_t crc32_c(uint32_t crc, const uint8_t *buf, size_t len, bool first_pkt, bool last_pkt) +{ + int ret; + + if (first_pkt) { + crc = CRC32_C_INIT_VAL; + } + + struct crc_ctx ctx = { + .type = CRC32_C, + .polynomial = CRC32C_POLY, + .seed = crc, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return last_pkt ? (ctx.result ^ CRC32C_XOR_OUT) : ctx.result; +} +#endif + +#ifdef CONFIG_CRC32_IEEE +uint32_t crc32_ieee_update(uint32_t crc, const uint8_t *buf, size_t len) +{ + int ret; + + crc = ~crc; + + struct crc_ctx ctx = { + .type = CRC32_IEEE, + .polynomial = CRC32_IEEE_POLY, + .seed = crc, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} + +uint32_t crc32_ieee(const uint8_t *buf, size_t len) +{ + return crc32_ieee_update(0x0, buf, len); +} +#endif + +#ifdef CONFIG_CRC32_K_4_2 +uint32_t crc32_k_4_2_update(uint32_t crc, const uint8_t *const data, const size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC32_K_4_2, + .polynomial = CRC32K_4_2_POLY, + .seed = crc, + .reversed = 0, + }; + + ret = crc_operation(crc_dev, &ctx, data, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif diff --git a/lib/crc/crc_shell.c b/subsys/crc/crc_shell.c similarity index 100% rename from lib/crc/crc_shell.c rename to subsys/crc/crc_shell.c diff --git a/subsys/dfu/boot/mcuboot.c b/subsys/dfu/boot/mcuboot.c index 623e3a0c97619..ad8ade044d41f 100644 --- a/subsys/dfu/boot/mcuboot.c +++ b/subsys/dfu/boot/mcuboot.c @@ -96,7 +96,7 @@ struct mcuboot_v1_raw_header { uint8_t boot_fetch_active_slot(void) { int rc; - uint8_t slot, fa_id; + uint8_t slot; rc = blinfo_lookup(BLINFO_RUNNING_SLOT, &slot, sizeof(slot)); @@ -110,45 +110,38 @@ uint8_t boot_fetch_active_slot(void) /* Map slot number back to flash area ID */ switch (slot) { case 0: - fa_id = FIXED_PARTITION_ID(SLOT0_PARTITION); - break; + return FIXED_PARTITION_ID(SLOT0_PARTITION); #if FIXED_PARTITION_EXISTS(SLOT1_PARTITION) case 1: - fa_id = FIXED_PARTITION_ID(SLOT1_PARTITION); - break; + return FIXED_PARTITION_ID(SLOT1_PARTITION); #endif #if FIXED_PARTITION_EXISTS(SLOT2_PARTITION) case 2: - fa_id = FIXED_PARTITION_ID(SLOT2_PARTITION); - break; + return FIXED_PARTITION_ID(SLOT2_PARTITION); #endif #if FIXED_PARTITION_EXISTS(SLOT3_PARTITION) case 3: - fa_id = FIXED_PARTITION_ID(SLOT3_PARTITION); - break; + return FIXED_PARTITION_ID(SLOT3_PARTITION); #endif #if FIXED_PARTITION_EXISTS(SLOT4_PARTITION) case 4: - fa_id = FIXED_PARTITION_ID(SLOT4_PARTITION); - break; + return FIXED_PARTITION_ID(SLOT4_PARTITION); #endif #if FIXED_PARTITION_EXISTS(SLOT5_PARTITION) case 5: - fa_id = FIXED_PARTITION_ID(SLOT5_PARTITION); - break; + return FIXED_PARTITION_ID(SLOT5_PARTITION); #endif default: - fa_id = INVALID_SLOT_ID; break; } - return fa_id; + return INVALID_SLOT_ID; } #else /* CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD || * CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD_WITH_REVERT diff --git a/subsys/dfu/img_util/flash_img.c b/subsys/dfu/img_util/flash_img.c index 322174c0c8f9b..83eb013c66123 100644 --- a/subsys/dfu/img_util/flash_img.c +++ b/subsys/dfu/img_util/flash_img.c @@ -27,7 +27,7 @@ LOG_MODULE_REGISTER(flash_img, CONFIG_IMG_MANAGER_LOG_LEVEL); (FIXED_PARTITION_OFFSET(label) == CONFIG_FLASH_LOAD_OFFSET) #include -#ifdef CONFIG_TRUSTED_EXECUTION_NONSECURE +#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && (CONFIG_TFM_MCUBOOT_IMAGE_NUMBER == 2) #define UPLOAD_FLASH_AREA_LABEL slot1_ns_partition #else #if FIXED_PARTITION_EXISTS(slot1_partition) && \ diff --git a/subsys/fb/cfb_shell.c b/subsys/fb/cfb_shell.c index 77286f719d374..d7cafc69f3c76 100644 --- a/subsys/fb/cfb_shell.c +++ b/subsys/fb/cfb_shell.c @@ -531,7 +531,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(sub_cmd_draw, SHELL_CMD_ARG(point, NULL, HELP_DRAW_POINT, cmd_draw_point, 3, 0), SHELL_CMD_ARG(line, NULL, HELP_DRAW_LINE, cmd_draw_line, 5, 0), SHELL_CMD_ARG(rect, NULL, HELP_DRAW_RECT, cmd_draw_rect, 5, 0), - SHELL_CMD_ARG(circle, NULL, HELP_DRAW_RECT, cmd_draw_circle, 4, 0), + SHELL_CMD_ARG(circle, NULL, HELP_DRAW_CIRCLE, cmd_draw_circle, 4, 0), SHELL_SUBCMD_SET_END ); diff --git a/subsys/fs/Kconfig b/subsys/fs/Kconfig index 709bb91bb5e89..b1e570436db01 100644 --- a/subsys/fs/Kconfig +++ b/subsys/fs/Kconfig @@ -85,6 +85,13 @@ config FILE_SYSTEM_SHELL_BUFFER_SIZE maximum size that can be used with a read/write test. Note that this is used on the stack. +config FILE_SYSTEM_SHELL_LS_SIZE + bool "File system shell ls command to also list size" + default y + help + While listing files in the file system shell, also list the size of + each file. + endif # FILE_SYSTEM_SHELL config FILE_SYSTEM_MKFS diff --git a/subsys/fs/nvs/nvs.c b/subsys/fs/nvs/nvs.c index 2e553fdbf554f..8a710d570fb12 100644 --- a/subsys/fs/nvs/nvs.c +++ b/subsys/fs/nvs/nvs.c @@ -1025,6 +1025,13 @@ int nvs_mount(struct nvs_fs *fs) return -EINVAL; } + /* check that sector size is not greater than max */ + if (fs->sector_size > NVS_MAX_SECTOR_SIZE) { + LOG_ERR("Sector size %u too large, maximum is %zu", + fs->sector_size, NVS_MAX_SECTOR_SIZE); + return -EINVAL; + } + /* check that sector size is a multiple of pagesize */ rc = flash_get_page_info_by_offs(fs->flash_device, fs->offset, &info); if (rc) { diff --git a/subsys/fs/nvs/nvs_priv.h b/subsys/fs/nvs/nvs_priv.h index 53f109ee13201..0c302d132f6ca 100644 --- a/subsys/fs/nvs/nvs_priv.h +++ b/subsys/fs/nvs/nvs_priv.h @@ -21,6 +21,8 @@ extern "C" { #define ADDR_SECT_SHIFT 16 #define ADDR_OFFS_MASK 0x0000FFFF +#define NVS_MAX_SECTOR_SIZE KB(64) + /* * Status return values */ diff --git a/subsys/fs/shell.c b/subsys/fs/shell.c index 75a87ba62cf3c..a591a96bb5712 100644 --- a/subsys/fs/shell.c +++ b/subsys/fs/shell.c @@ -188,6 +188,7 @@ static int cmd_ls(const struct shell *sh, size_t argc, char **argv) while (1) { struct fs_dirent entry; + const char *name_end; err = fs_readdir(&dir, &entry); if (err != 0) { @@ -200,7 +201,12 @@ static int cmd_ls(const struct shell *sh, size_t argc, char **argv) break; } - shell_print(sh, "%s%s", entry.name, (entry.type == FS_DIR_ENTRY_DIR) ? "/" : ""); + name_end = (entry.type == FS_DIR_ENTRY_DIR) ? "/" : ""; + if (IS_ENABLED(CONFIG_FILE_SYSTEM_SHELL_LS_SIZE)) { + shell_print(sh, "%8zu %s%s", entry.size, entry.name, name_end); + } else { + shell_print(sh, "%s%s", entry.name, name_end); + } } fs_closedir(&dir); diff --git a/subsys/fs/zms/Kconfig b/subsys/fs/zms/Kconfig index 8aa6392ba62d4..9266fada236af 100644 --- a/subsys/fs/zms/Kconfig +++ b/subsys/fs/zms/Kconfig @@ -64,7 +64,7 @@ config ZMS_NO_DOUBLE_WRITE bool "Avoid writing the same data again in the storage" help For some memory technologies, write cycles for memory cells are limited and any - unncessary writes should be avoided. + unnecessary writes should be avoided. Enable this config to avoid rewriting data in the storage if it already exists. This option will reduce write performance as it will need to do a research of the data in the whole storage before any write. diff --git a/subsys/fs/zms/zms.c b/subsys/fs/zms/zms.c index 80b86a41cdcbd..b4b11aa6923ef 100644 --- a/subsys/fs/zms/zms.c +++ b/subsys/fs/zms/zms.c @@ -1101,6 +1101,11 @@ int zms_clear(struct zms_fs *fs) int rc; uint64_t addr; + if (!fs) { + LOG_ERR("Invalid fs"); + return -EINVAL; + } + if (!fs->ready) { LOG_ERR("zms not initialized"); return -EACCES; @@ -1395,6 +1400,11 @@ int zms_mount(struct zms_fs *fs) struct flash_pages_info info; size_t write_block_size; + if (!fs) { + LOG_ERR("Invalid fs"); + return -EINVAL; + } + k_mutex_init(&fs->zms_lock); fs->flash_parameters = flash_get_parameters(fs->flash_device); @@ -1465,6 +1475,11 @@ ssize_t zms_write(struct zms_fs *fs, uint32_t id, const void *data, size_t len) uint32_t gc_count; uint32_t required_space = 0U; /* no space, appropriate for delete ate */ + if (!fs) { + LOG_ERR("Invalid fs"); + return -EINVAL; + } + if (!fs->ready) { LOG_ERR("zms not initialized"); return -EACCES; @@ -1615,6 +1630,10 @@ ssize_t zms_read_hist(struct zms_fs *fs, uint32_t id, void *data, size_t len, ui #ifdef CONFIG_ZMS_DATA_CRC uint32_t computed_data_crc; #endif + if (!fs) { + LOG_ERR("Invalid fs"); + return -EINVAL; + } if (!fs->ready) { LOG_ERR("zms not initialized"); @@ -1739,6 +1758,12 @@ ssize_t zms_calc_free_space(struct zms_fs *fs) uint64_t data_wra = 0U; uint8_t current_cycle; ssize_t free_space = 0; + + if (!fs) { + LOG_ERR("Invalid fs"); + return -EINVAL; + } + const uint32_t second_to_last_offset = (2 * fs->ate_size); if (!fs->ready) { @@ -1837,8 +1862,13 @@ ssize_t zms_calc_free_space(struct zms_fs *fs) return free_space; } -size_t zms_active_sector_free_space(struct zms_fs *fs) +ssize_t zms_active_sector_free_space(struct zms_fs *fs) { + if (!fs) { + LOG_ERR("Invalid fs"); + return -EINVAL; + } + if (!fs->ready) { LOG_ERR("ZMS not initialized"); return -EACCES; @@ -1851,6 +1881,11 @@ int zms_sector_use_next(struct zms_fs *fs) { int ret; + if (!fs) { + LOG_ERR("Invalid fs"); + return -EINVAL; + } + if (!fs->ready) { LOG_ERR("ZMS not initialized"); return -EACCES; diff --git a/subsys/logging/Kconfig.misc b/subsys/logging/Kconfig.misc index 0dd3afb40adb9..dc785176ff27c 100644 --- a/subsys/logging/Kconfig.misc +++ b/subsys/logging/Kconfig.misc @@ -13,7 +13,7 @@ config LOG_TEST_CLEAR_MESSAGE_SPACE default y depends on ZTEST help - Used in testing to simplify message comparision if message contains + Used in testing to simplify message comparison if message contains paddings. config LOG_USE_VLA diff --git a/subsys/logging/backends/Kconfig.spinel b/subsys/logging/backends/Kconfig.spinel index d2d29370aa35d..94ed1f040a94a 100644 --- a/subsys/logging/backends/Kconfig.spinel +++ b/subsys/logging/backends/Kconfig.spinel @@ -4,7 +4,7 @@ config LOG_BACKEND_SPINEL bool "OpenThread dedicated Spinel protocol backend" depends on !LOG_BACKEND_UART - depends on NET_L2_OPENTHREAD + depends on OPENTHREAD help When enabled, backend will use OpenThread dedicated SPINEL protocol for logging. This protocol is byte oriented and wraps given messages into serial frames. diff --git a/subsys/logging/backends/log_backend_net.c b/subsys/logging/backends/log_backend_net.c index b0e3ca5c42587..4470d9c3392c8 100644 --- a/subsys/logging/backends/log_backend_net.c +++ b/subsys/logging/backends/log_backend_net.c @@ -295,7 +295,7 @@ bool log_backend_net_set_ip(const struct sockaddr *addr) } #if defined(CONFIG_NET_HOSTNAME_ENABLE) -void log_backend_net_hostname_set(char *hostname, size_t len) +void log_backend_net_hostname_set(const char *hostname, size_t len) { (void)strncpy(dev_hostname, hostname, MIN(len, MAX_HOSTNAME_LEN)); log_output_hostname_set(&log_output_net, dev_hostname); diff --git a/subsys/logging/backends/log_backend_swo.c b/subsys/logging/backends/log_backend_swo.c index 666333b95e0ab..27a2f5c2d9593 100644 --- a/subsys/logging/backends/log_backend_swo.c +++ b/subsys/logging/backends/log_backend_swo.c @@ -94,23 +94,25 @@ static void log_backend_swo_init(struct log_backend const *const backend) { /* Enable DWT and ITM units */ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; +#if (__CORTEX_M <= 7U) /* Enable access to ITM registers */ ITM->LAR = 0xC5ACCE55; +#endif /* Disable stimulus ports ITM_STIM0-ITM_STIM31 */ ITM->TER = 0x0; /* Disable ITM */ ITM->TCR = 0x0; /* Select TPIU encoding protocol */ - TPI->SPPR = IS_ENABLED(CONFIG_LOG_BACKEND_SWO_PROTOCOL_NRZ) ? 2 : 1; + TPIU->SPPR = IS_ENABLED(CONFIG_LOG_BACKEND_SWO_PROTOCOL_NRZ) ? 2 : 1; /* Set SWO baud rate prescaler value: SWO_clk = ref_clock/(ACPR + 1) */ - TPI->ACPR = SWO_FREQ_DIV - 1; + TPIU->ACPR = SWO_FREQ_DIV - 1; /* Enable unprivileged access to ITM stimulus ports */ ITM->TPR = 0x0; /* Configure Debug Watchpoint and Trace */ DWT->CTRL &= (DWT_CTRL_POSTPRESET_Msk | DWT_CTRL_POSTINIT_Msk | DWT_CTRL_CYCCNTENA_Msk); DWT->CTRL |= (DWT_CTRL_POSTPRESET_Msk | DWT_CTRL_POSTINIT_Msk); /* Configure Formatter and Flush Control Register */ - TPI->FFCR = 0x00000100; + TPIU->FFCR = 0x00000100; /* Enable ITM, set TraceBusID=1, no local timestamp generation */ ITM->TCR = 0x0001000D; /* Enable stimulus port used by the logger */ diff --git a/subsys/mgmt/ec_host_cmd/Kconfig b/subsys/mgmt/ec_host_cmd/Kconfig index 1cd5c8acba37d..d17f27c36dcf4 100644 --- a/subsys/mgmt/ec_host_cmd/Kconfig +++ b/subsys/mgmt/ec_host_cmd/Kconfig @@ -47,6 +47,14 @@ config EC_HOST_CMD_HANDLER_RX_BUFFER_SIZE avoid duplicating buffers. If multiple backends are used, the size has to be set by user to the largest one. +config EC_HOST_CMD_HANDLER_BUFFER_ALIGN + int "Memory alignment for the tx/rx buffers" + default DCACHE_LINE_SIZE if (DCACHE_LINE_SIZE > 0) && EC_HOST_CMD_BACKEND_USB + default 4 + help + Some interfaces need a special memory alignment to work properly. Use that config + to specify the alignment. + config EC_HOST_CMD_HANDLER_PRIO int "Priority of host command task" default 13 diff --git a/subsys/mgmt/ec_host_cmd/backends/CMakeLists.txt b/subsys/mgmt/ec_host_cmd/backends/CMakeLists.txt index 06d06ae22a4b7..093a77c3f1719 100644 --- a/subsys/mgmt/ec_host_cmd/backends/CMakeLists.txt +++ b/subsys/mgmt/ec_host_cmd/backends/CMakeLists.txt @@ -25,3 +25,7 @@ zephyr_library_sources_ifdef( zephyr_library_sources_ifdef( CONFIG_EC_HOST_CMD_BACKEND_SPI_STM32 ec_host_cmd_backend_spi_stm32.c) + +zephyr_library_sources_ifdef( + CONFIG_EC_HOST_CMD_BACKEND_USB + ec_host_cmd_backend_usb.c) diff --git a/subsys/mgmt/ec_host_cmd/backends/Kconfig b/subsys/mgmt/ec_host_cmd/backends/Kconfig index e97b1d2fd184f..4c6cdae344276 100644 --- a/subsys/mgmt/ec_host_cmd/backends/Kconfig +++ b/subsys/mgmt/ec_host_cmd/backends/Kconfig @@ -132,3 +132,10 @@ config EC_HOST_CMD_BACKEND_UART_TIMEOUT chunk. endif # EC_HOST_CMD_BACKEND_UART + +config EC_HOST_CMD_BACKEND_USB + bool "Host commands support using USB" + default y + depends on USB_DEVICE_STACK_NEXT + help + Enable support for Embedded Controller host commands using the USB. diff --git a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c index 721b770d8d1f2..7a3c4d11a20c8 100644 --- a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c +++ b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c @@ -346,11 +346,11 @@ static void shi_npcx_bad_received_data(const struct device *dev) /* SHI receive bad data */ LOG_WRN("SHIBD"); LOG_HEXDUMP_DBG(data->in_msg, data->rx_ctx->len, "in_msg="); - - /* Reset shi's state machine for error recovery */ - shi_npcx_reset_prepare(dev); - - LOG_DBG("END"); + /* + * When unexpected data is received, continuously send the code EC_SHI_RX_BAD_DATA (0xFB) + * to the host on the output line. The SHI state machine is reset when the CS pin is + * de-asserted. + */ } /* diff --git a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_usb.c b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_usb.c new file mode 100644 index 0000000000000..e037c01fb3219 --- /dev/null +++ b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_usb.c @@ -0,0 +1,681 @@ +/* + * Copyright (c) 2025 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(ec_host_cmd_usb, LOG_LEVEL_DBG); + +BUILD_ASSERT((CONFIG_EC_HOST_CMD_HANDLER_BUFFER_ALIGN % UDC_BUF_ALIGN) == 0, "Buffers not aligned"); + +#define USB_SUBCLASS_GOOGLE_EC_HOST_CMD 0x5a +#define USB_PROTOCOL_GOOGLE_EC_HOST_CMD 0x00 + +/* Supported version of host commands protocol. */ +#define EC_HOST_REQUEST_VERSION 3 + +#define EC_HOST_CMD_SEND_TIMEOUT_MS 100 + +#define EP_BULK_SIZE 64U +#define EP_INT_SIZE_SIZE 4U + +#define INT_POOL_SIZE 4 + +/* Timeout for receiving entire request. */ +#define OUT_TRANSFER_TIMEOUT_MS 100 +/* Timeout for sending response, starting from notifing host that it is ready. */ +#define IN_TRANSFER_TIMEOUT_MS 200 + +enum ec_host_cmd_usb_irq_type { + USB_EC_HOST_CMD_IRQ_TYPE_EVENT = 0, + USB_EC_HOST_CMD_IRQ_TYPE_RESP_READY = 1, +}; + +NET_BUF_POOL_DEFINE(ec_host_cmd_ep_pool, 2, 0, sizeof(struct udc_buf_info), NULL); +UDC_BUF_POOL_DEFINE(int_ep_pool, INT_POOL_SIZE, EP_INT_SIZE_SIZE, sizeof(struct udc_buf_info), + NULL); + +enum ec_host_cmd_usb_state { + /* + * Host commands not enabled. + */ + USB_EC_HOST_CMD_STATE_DISABLED, + + /* + * USB interface is enabled and ready to receive host request. + * Once the response is sent, the current state is reset to this state to accept a next + * request. + */ + USB_EC_HOST_CMD_STATE_READY_TO_RX, + + /* + * Receiving ongoing. The first part of the host command request has been received, + * potentialy waiting for the rest. + */ + USB_EC_HOST_CMD_STATE_RECEIVING, + + /* + * The host command request has been fully received and the command is being proccessed. + * The host command handler always has to send a respond, even if the request is invalid. + */ + USB_EC_HOST_CMD_STATE_PROCESSING, + + /* + * Processing is finished, the response is being sent. + */ + USB_EC_HOST_CMD_STATE_SENDING, +}; + +enum { + EC_HOST_CMD_CLASS_ENABLED, +}; + +static const char *const state_name[] = { + [USB_EC_HOST_CMD_STATE_DISABLED] = "DISABLED", + [USB_EC_HOST_CMD_STATE_READY_TO_RX] = "READY_TO_RX", + [USB_EC_HOST_CMD_STATE_RECEIVING] = "RECEIVING", + [USB_EC_HOST_CMD_STATE_PROCESSING] = "PROCESSING", + [USB_EC_HOST_CMD_STATE_SENDING] = "SENDING", +}; + +struct ec_host_cmd_desc { + struct usb_if_descriptor if0; + struct usb_ep_descriptor out_ep; + struct usb_ep_descriptor in_bulk_ep; + struct usb_ep_descriptor in_int_ep; + struct usb_desc_header nil_desc; +}; + +struct ec_host_cmd_usb_ctx { + struct usbd_class_data *c_data; + struct ec_host_cmd_desc *const desc; + const struct usb_desc_header **const fs_desc; + struct ec_host_cmd_rx_ctx *rx_ctx; + struct ec_host_cmd_tx_buf *tx_buf; + uint8_t *bulk_out_buf; + struct net_buf *usb_rx_buf; + struct net_buf *usb_tx_buf; + enum ec_host_cmd_usb_state state; + atomic_t class_state; + bool pending_event; + struct k_work_delayable reset_work; +}; + +static int expected_request_len(const struct ec_host_cmd_request_header *header) +{ + /* Check host request version */ + if (header->prtcl_ver != EC_HOST_REQUEST_VERSION) { + return 0; + } + + /* Reserved byte should be 0 */ + if (header->reserved) { + return 0; + } + + return sizeof(*header) + header->data_len; +} + +static inline uint8_t ec_host_cmd_get_out_ep(struct usbd_class_data *const c_data) +{ + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + struct ec_host_cmd_desc *desc = ctx->desc; + + return desc->out_ep.bEndpointAddress; +} + +static inline uint8_t ec_host_cmd_get_in_bulk_ep(struct usbd_class_data *const c_data) +{ + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + struct ec_host_cmd_desc *desc = ctx->desc; + + return desc->in_bulk_ep.bEndpointAddress; +} + +static inline uint8_t ec_host_cmd_get_in_int_ep(struct usbd_class_data *const c_data) +{ + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + struct ec_host_cmd_desc *desc = ctx->desc; + + return desc->in_int_ep.bEndpointAddress; +} + +static struct net_buf *ec_host_cmd_buf_alloc(const uint8_t ep, const size_t size, void *const data) +{ + struct net_buf *buf = NULL; + struct udc_buf_info *bi; + + __ASSERT(IS_UDC_ALIGNED(data), "Application provided unaligned buffer"); + + buf = net_buf_alloc_with_data(&ec_host_cmd_ep_pool, data, size, K_NO_WAIT); + if (!buf) { + return NULL; + } + + bi = udc_get_buf_info(buf); + bi->ep = ep; + + if (USB_EP_DIR_IS_OUT(ep)) { + buf->len = 0; + } + + return buf; +} + +static struct net_buf *ec_host_cmd_buf_alloc_int(const uint8_t ep) +{ + struct net_buf *buf = NULL; + struct udc_buf_info *bi; + + buf = net_buf_alloc(&int_ep_pool, K_NO_WAIT); + if (!buf) { + return NULL; + } + + bi = udc_get_buf_info(buf); + bi->ep = ep; + + return buf; +} + +static int ec_host_cmd_signal_event(struct usbd_class_data *const c_data) +{ + struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data); + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + struct net_buf *buf; + int ret; + + buf = ec_host_cmd_buf_alloc_int(ec_host_cmd_get_in_int_ep(c_data)); + if (buf == NULL) { + LOG_WRN("Event has been already signaled but not polled by the host"); + return 0; + } + net_buf_add_u8(buf, USB_EC_HOST_CMD_IRQ_TYPE_EVENT); + buf->len = EP_INT_SIZE_SIZE; + ret = usbd_ep_enqueue(c_data, buf); + if (ret) { + LOG_ERR("Failed to enqueue EP IN INT: %d", ret); + usbd_ep_buf_free(uds_ctx, buf); + return ret; + } + ctx->pending_event = false; + + return 0; +} + +static int handle_out_transfer(struct usbd_class_data *const c_data) +{ + int ret; + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + size_t expected_len = + expected_request_len((struct ec_host_cmd_request_header *)ctx->rx_ctx->buf); + + /* Notify about a new command or response with a proper error code. */ + if ((ctx->rx_ctx->len >= expected_len) || (expected_len == 0) || + (expected_len > ctx->rx_ctx->len_max)) { + k_work_cancel_delayable(&ctx->reset_work); + if (ctx->rx_ctx->len > expected_len) { + LOG_ERR("Received incorrect number of bytes, got: %d, expected: %d", + ctx->rx_ctx->len, expected_len); + } + ctx->state = USB_EC_HOST_CMD_STATE_PROCESSING; + ec_host_cmd_rx_notify(); + } + + /* Enqueue OUT transfer if we are still receiving. */ + if (ctx->state == USB_EC_HOST_CMD_STATE_RECEIVING) { + if (!IS_UDC_ALIGNED(ctx->rx_ctx->len)) { + LOG_ERR("Received unaligned OUT transfer: %d", ctx->rx_ctx->len); + k_work_reschedule(&ctx->reset_work, K_NO_WAIT); + return 0; + } + ctx->usb_rx_buf = ec_host_cmd_buf_alloc(ec_host_cmd_get_out_ep(c_data), + expected_len - ctx->rx_ctx->len, + ctx->rx_ctx->buf + ctx->rx_ctx->len); + if (ctx->usb_rx_buf == NULL) { + LOG_ERR("Failed to allocate buf OUT"); + k_work_reschedule(&ctx->reset_work, K_NO_WAIT); + return 0; + } + ret = usbd_ep_enqueue(c_data, ctx->usb_rx_buf); + if (ret) { + net_buf_unref(ctx->usb_rx_buf); + k_work_reschedule(&ctx->reset_work, K_NO_WAIT); + LOG_ERR("Failed to enqueue EP OUT: %d", ret); + return 0; + } + } + + return 0; +} + +static int ec_host_cmd_request(struct usbd_class_data *const c_data, struct net_buf *const buf, + int err) +{ + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data); + struct udc_buf_info *bi = NULL; + int ret; + + bi = udc_get_buf_info(buf); + + if (err) { + if (err == -ECONNABORTED) { + LOG_WRN("Request EP 0x%02x cancelled", bi->ep); + } else { + LOG_ERR("Request EP 0x%02x failed: %d", bi->ep, err); + } + + if ((bi->ep == ec_host_cmd_get_in_int_ep(c_data)) || + (bi->ep == ec_host_cmd_get_out_ep(c_data))) { + usbd_ep_buf_free(uds_ctx, buf); + usbd_ep_buf_free(uds_ctx, buf); + } + + return 0; + } + + if (bi->ep == ec_host_cmd_get_out_ep(c_data)) { + uint16_t buf_len = buf->len; + + ret = usbd_ep_buf_free(uds_ctx, buf); + if (ret) { + LOG_ERR("Failed to free buf OUT"); + /* Schedule the reset work even if it hasn't been queued */ + k_work_reschedule(&ctx->reset_work, K_NO_WAIT); + return ret; + } + + if (ctx->state == USB_EC_HOST_CMD_STATE_READY_TO_RX) { + if (buf_len < sizeof(struct ec_host_cmd_request_header)) { + LOG_ERR("First transfer less than header: %d", buf_len); + k_work_schedule(&ctx->reset_work, K_NO_WAIT); + return 0; + } + ctx->state = USB_EC_HOST_CMD_STATE_RECEIVING; + ctx->rx_ctx->len = 0; + k_work_schedule(&ctx->reset_work, K_MSEC(OUT_TRANSFER_TIMEOUT_MS)); + } + + if (ctx->state != USB_EC_HOST_CMD_STATE_RECEIVING) { + LOG_ERR("Unexpected transfer in state: %s", state_name[ctx->state]); + return 0; + } + + ctx->rx_ctx->len = ctx->rx_ctx->len + buf_len; + + return handle_out_transfer(c_data); + } + + if (bi->ep == ec_host_cmd_get_in_bulk_ep(c_data)) { + k_work_cancel_delayable(&ctx->reset_work); + ctx->usb_rx_buf = ec_host_cmd_buf_alloc(ec_host_cmd_get_out_ep(c_data), + EP_BULK_SIZE, ctx->rx_ctx->buf); + if (ctx->usb_rx_buf == NULL) { + LOG_ERR("Failed to allocate buf OUT"); + k_work_schedule(&ctx->reset_work, K_NO_WAIT); + return 0; + } + + ret = usbd_ep_enqueue(c_data, ctx->usb_rx_buf); + if (ret) { + LOG_ERR("Failed to enqueue EP OUT: %d", ret); + net_buf_unref(ctx->usb_rx_buf); + k_work_schedule(&ctx->reset_work, K_NO_WAIT); + return 0; + } + + ctx->state = USB_EC_HOST_CMD_STATE_READY_TO_RX; + } + + if (bi->ep == ec_host_cmd_get_in_int_ep(c_data)) { + usbd_ep_buf_free(uds_ctx, buf); + } + + return 0; +} + +static void *ec_host_cmd_get_desc(struct usbd_class_data *const c_data, const enum usbd_speed speed) +{ + const struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + + if (speed == USBD_SPEED_HS) { + return NULL; + } + + return ctx->fs_desc; +} + +static void ec_host_cmd_enable(struct usbd_class_data *const c_data) +{ + int ret; + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + struct udc_buf_info *bi; + struct net_buf *buf; + + atomic_set_bit(&ctx->class_state, EC_HOST_CMD_CLASS_ENABLED); + if (!ctx->usb_tx_buf) { + LOG_ERR("Host Commands not initaliazed"); + return; + } + + /* Update EP IN address. Buf is allocated in the backend init procedure. */ + bi = udc_get_buf_info(ctx->usb_tx_buf); + bi->ep = ec_host_cmd_get_in_bulk_ep(c_data); + + buf = ec_host_cmd_buf_alloc(ec_host_cmd_get_out_ep(c_data), EP_BULK_SIZE, ctx->rx_ctx->buf); + if (buf == NULL) { + ctx->state = USB_EC_HOST_CMD_STATE_DISABLED; + LOG_ERR("Failed to allocate buf OUT"); + return; + } + ctx->usb_rx_buf = buf; + + /* Enqueue OUT transfer to receive a host command request. */ + ret = usbd_ep_enqueue(c_data, ctx->usb_rx_buf); + if (ret) { + ctx->state = USB_EC_HOST_CMD_STATE_DISABLED; + LOG_ERR("Failed to enqueue EP OUT: %d", ret); + net_buf_unref(ctx->usb_rx_buf); + return; + } + ctx->state = USB_EC_HOST_CMD_STATE_READY_TO_RX; + + if (ctx->pending_event) { + ec_host_cmd_signal_event(c_data); + } + + LOG_INF("Configuration enabled"); +} + +static void ec_host_cmd_resumed(struct usbd_class_data *const c_data) +{ + LOG_DBG("Configuration resumed"); + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + + if (ctx->pending_event) { + ec_host_cmd_signal_event(c_data); + } +} + +static void ec_host_cmd_suspended(struct usbd_class_data *const c_data) +{ + LOG_DBG("Configuration suspended"); +} + +static void ec_host_cmd_disable(struct usbd_class_data *const c_data) +{ + struct ec_host_cmd_usb_ctx *ctx = usbd_class_get_private(c_data); + + atomic_clear_bit(&ctx->class_state, EC_HOST_CMD_CLASS_ENABLED); + + k_work_cancel_delayable(&ctx->reset_work); + if (ctx->state != USB_EC_HOST_CMD_STATE_READY_TO_RX) { + LOG_WRN("Disabled usb in state %s", state_name[ctx->state]); + } + ctx->state = USB_EC_HOST_CMD_STATE_DISABLED; +} + +static int ec_host_cmd_usbd_init(struct usbd_class_data *c_data) +{ + LOG_DBG("Class init"); + + return 0; +} + +static void ec_host_cmd_reset(struct k_work *work) +{ + struct k_work_delayable *dwork = k_work_delayable_from_work(work); + struct ec_host_cmd_usb_ctx *ctx = + CONTAINER_OF(dwork, struct ec_host_cmd_usb_ctx, reset_work); + struct usbd_class_data *const c_data = ctx->c_data; + struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data); + int ret; + + LOG_INF("Resetting backend in state %s", state_name[ctx->state]); + + if (!ctx->usb_tx_buf) { + LOG_ERR("Host Commands not initaliazed"); + return; + } + + ctx->state = USB_EC_HOST_CMD_STATE_DISABLED; + ret = usbd_ep_dequeue(uds_ctx, ec_host_cmd_get_out_ep(c_data)); + if (ret) { + LOG_ERR("Failed to dequeue EP OUT: %d", ret); + return; + } + ret = usbd_ep_dequeue(uds_ctx, ec_host_cmd_get_in_bulk_ep(c_data)); + if (ret) { + LOG_ERR("Failed to dequeue EP IN: %d", ret); + return; + } + ret = usbd_ep_dequeue(uds_ctx, ec_host_cmd_get_in_int_ep(c_data)); + if (ret) { + LOG_ERR("Failed to dequeue EP IN INT: %d", ret); + return; + } + + ec_host_cmd_enable(ctx->c_data); +} + +__maybe_unused static struct usbd_class_api ec_host_cmd_api = { + .request = ec_host_cmd_request, + .suspended = ec_host_cmd_suspended, + .resumed = ec_host_cmd_resumed, + .enable = ec_host_cmd_enable, + .disable = ec_host_cmd_disable, + .get_desc = ec_host_cmd_get_desc, + .init = ec_host_cmd_usbd_init, +}; + +static int ec_host_cmd_backend_init(const struct ec_host_cmd_backend *backend, + struct ec_host_cmd_rx_ctx *rx_ctx, + struct ec_host_cmd_tx_buf *tx) +{ + struct ec_host_cmd_usb_ctx *ctx = backend->ctx; + struct usbd_class_data *const c_data = ctx->c_data; + struct net_buf *buf; + + ctx->rx_ctx = rx_ctx; + ctx->tx_buf = tx; + + ctx->state = USB_EC_HOST_CMD_STATE_DISABLED; + + k_work_init_delayable(&ctx->reset_work, ec_host_cmd_reset); + + if ((ctx->rx_ctx->buf == NULL) || (ctx->tx_buf->buf == NULL)) { + LOG_ERR("Buffers not provided"); + return -EINVAL; + } + + /* EPs addresses can be changed, but it is updated in the enable procedure. */ + buf = ec_host_cmd_buf_alloc(ec_host_cmd_get_in_bulk_ep(c_data), ctx->tx_buf->len_max, + ctx->tx_buf->buf); + if (buf == NULL) { + LOG_ERR("Failed to allocate buf IN"); + return -ENOMEM; + } + ctx->usb_tx_buf = buf; + + return 0; +} + +static int ec_host_cmd_backend_send(const struct ec_host_cmd_backend *backend) +{ + struct ec_host_cmd_usb_ctx *ctx = backend->ctx; + struct usbd_class_data *const c_data = ctx->c_data; + struct net_buf *buf = NULL; + int ret; + + if (!atomic_test_bit(&ctx->class_state, EC_HOST_CMD_CLASS_ENABLED)) { + LOG_ERR("Class not enabled"); + return -EACCES; + } + + if (ctx->state != USB_EC_HOST_CMD_STATE_PROCESSING) { + LOG_ERR("Unexpected state when sending: %s", state_name[ctx->state]); + return -EACCES; + } + + ctx->state = USB_EC_HOST_CMD_STATE_SENDING; + + k_work_schedule(&ctx->reset_work, K_MSEC(IN_TRANSFER_TIMEOUT_MS)); + + net_buf_reset(ctx->usb_tx_buf); + ctx->usb_tx_buf->len = ctx->tx_buf->len; + ret = usbd_ep_enqueue(c_data, ctx->usb_tx_buf); + if (ret) { + LOG_ERR("Failed to enqueue EP IN: %d", ret); + k_work_reschedule(&ctx->reset_work, K_NO_WAIT); + return ret; + } + + buf = ec_host_cmd_buf_alloc_int(ec_host_cmd_get_in_int_ep(c_data)); + if (buf == NULL) { + LOG_ERR("Failed to allocate buf INT OUT: %d", ret); + k_work_reschedule(&ctx->reset_work, K_NO_WAIT); + return -ENOMEM; + } + + /* Signal to host that response is ready. */ + net_buf_add_u8(buf, USB_EC_HOST_CMD_IRQ_TYPE_RESP_READY); + buf->len = EP_INT_SIZE_SIZE; + + ret = usbd_ep_enqueue(c_data, buf); + if (ret) { + net_buf_unref(buf); + LOG_ERR("Failed to enqueue EP INT OUT: %d", ret); + k_work_reschedule(&ctx->reset_work, K_NO_WAIT); + return ret; + } + + return ret; +} + +static const struct ec_host_cmd_backend_api ec_host_cmd_backend_api = { + .init = ec_host_cmd_backend_init, + .send = ec_host_cmd_backend_send, +}; + +BUILD_ASSERT(!USBD_SUPPORTS_HIGH_SPEED, "High speed is not supported"); + +static struct ec_host_cmd_desc ec_host_cmd_desc = { + .if0 = { + .bLength = sizeof(struct usb_if_descriptor), + .bDescriptorType = USB_DESC_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 3, + .bInterfaceClass = USB_BCC_VENDOR, + .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_EC_HOST_CMD, + .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_EC_HOST_CMD, + .iInterface = 0, + }, + .out_ep = { + .bLength = sizeof(struct usb_ep_descriptor), + .bDescriptorType = USB_DESC_ENDPOINT, + .bEndpointAddress = 0x01, + .bmAttributes = USB_EP_TYPE_BULK, + .wMaxPacketSize = sys_cpu_to_le16(EP_BULK_SIZE), + .bInterval = 0x00, + }, + .in_bulk_ep = { + .bLength = sizeof(struct usb_ep_descriptor), + .bDescriptorType = USB_DESC_ENDPOINT, + .bEndpointAddress = 0x81, + .bmAttributes = USB_EP_TYPE_BULK, + .wMaxPacketSize = sys_cpu_to_le16(EP_BULK_SIZE), + .bInterval = 0x00, + }, + .in_int_ep = { + .bLength = sizeof(struct usb_ep_descriptor), + .bDescriptorType = USB_DESC_ENDPOINT, + .bEndpointAddress = 0x82, + .bmAttributes = USB_EP_TYPE_INTERRUPT, + .wMaxPacketSize = sys_cpu_to_le16(EP_INT_SIZE_SIZE), + .bInterval = USB_FS_INT_EP_INTERVAL(1000), + }, + .nil_desc = { + .bLength = 0, + .bDescriptorType = 0, + }, +}; + +static const struct usb_desc_header *ec_host_cmd_fs_desc[] = { + (struct usb_desc_header *)&ec_host_cmd_desc.if0, + (struct usb_desc_header *)&ec_host_cmd_desc.out_ep, + (struct usb_desc_header *)&ec_host_cmd_desc.in_bulk_ep, + (struct usb_desc_header *)&ec_host_cmd_desc.in_int_ep, + (struct usb_desc_header *)&ec_host_cmd_desc.nil_desc, +}; + +static struct ec_host_cmd_usb_ctx ec_host_cmd_ctx; + +USBD_DEFINE_CLASS(ec_host_cmd_class, &ec_host_cmd_api, (void *)&ec_host_cmd_ctx, NULL); + +static uint8_t bulk_out_buf[EP_BULK_SIZE] __aligned(UDC_BUF_ALIGN); +static struct ec_host_cmd_usb_ctx ec_host_cmd_ctx = { + .desc = &ec_host_cmd_desc, + .fs_desc = ec_host_cmd_fs_desc, + .c_data = &ec_host_cmd_class, + .bulk_out_buf = bulk_out_buf, +}; + +static struct ec_host_cmd_backend usb_ec_host_cmd_backend = { + .api = &ec_host_cmd_backend_api, + .ctx = &ec_host_cmd_ctx, +}; + +struct ec_host_cmd_backend *ec_host_cmd_backend_get_usb(void) +{ + return &usb_ec_host_cmd_backend; +} + +#ifdef CONFIG_EC_HOST_CMD_INITIALIZE_AT_BOOT +static int host_cmd_init(void) +{ + ec_host_cmd_init(ec_host_cmd_backend_get_usb()); + return 0; +} +SYS_INIT(host_cmd_init, POST_KERNEL, CONFIG_EC_HOST_CMD_INIT_PRIORITY); +#endif + +void ec_host_cmd_backend_usb_trigger_event(void) +{ + int ret; + struct ec_host_cmd_usb_ctx *ctx = ec_host_cmd_backend_get_usb()->ctx; + struct usbd_class_data *const c_data = ctx->c_data; + struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data); + + ctx->pending_event = true; + if (!atomic_test_bit(&ctx->class_state, EC_HOST_CMD_CLASS_ENABLED)) { + return; + } + + if (usbd_is_suspended(uds_ctx)) { + if (uds_ctx->status.rwup) { + ret = usbd_wakeup_request(uds_ctx); + if (ret) { + LOG_ERR("Failed to wake-up host %d", ret); + } + } + } else { + ec_host_cmd_signal_event(c_data); + } +} diff --git a/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c b/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c index 0e8df2316b832..e82a6756b0eed 100644 --- a/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c +++ b/subsys/mgmt/ec_host_cmd/ec_host_cmd_handler.c @@ -40,10 +40,12 @@ BUILD_ASSERT(NUMBER_OF_CHOSEN_BACKENDS < 2, "Number of chosen backends > 1"); #endif COND_CODE_1(CONFIG_EC_HOST_CMD_HANDLER_RX_BUFFER_DEF, - (static uint8_t hc_rx_buffer[CONFIG_EC_HOST_CMD_HANDLER_RX_BUFFER_SIZE] __aligned(4) + (static uint8_t hc_rx_buffer[CONFIG_EC_HOST_CMD_HANDLER_RX_BUFFER_SIZE] + __aligned(CONFIG_EC_HOST_CMD_HANDLER_BUFFER_ALIGN) BUFFERS_CACHE_ATTR;), ()) COND_CODE_1(CONFIG_EC_HOST_CMD_HANDLER_TX_BUFFER_DEF, - (static uint8_t hc_tx_buffer[CONFIG_EC_HOST_CMD_HANDLER_TX_BUFFER_SIZE] __aligned(4) + (static uint8_t hc_tx_buffer[CONFIG_EC_HOST_CMD_HANDLER_TX_BUFFER_SIZE] + __aligned(CONFIG_EC_HOST_CMD_HANDLER_BUFFER_ALIGN) BUFFERS_CACHE_ATTR;), ()) #ifdef CONFIG_EC_HOST_CMD_DEDICATED_THREAD diff --git a/subsys/mgmt/hawkbit/Kconfig b/subsys/mgmt/hawkbit/Kconfig index 0d301c21e34b2..ce0fd7c160f3e 100644 --- a/subsys/mgmt/hawkbit/Kconfig +++ b/subsys/mgmt/hawkbit/Kconfig @@ -220,6 +220,11 @@ config HAWKBIT_REBOOT_COLD help Do a cold reboot after the update. +config HAWKBIT_REBOOT_NONE + bool "Don't reboot after update" + help + Do not reboot after the update. + endchoice config HEAP_MEM_POOL_ADD_SIZE_HAWKBIT diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c index 1f99c3d0dec11..69a75d44efff9 100644 --- a/subsys/mgmt/hawkbit/hawkbit.c +++ b/subsys/mgmt/hawkbit/hawkbit.c @@ -1099,7 +1099,10 @@ static bool send_request(struct hawkbit_context *hb_context, enum hawkbit_http_r static const char *const headers[] = {AUTH_HEADER_FULL, NULL}; #endif /* CONFIG_HAWKBIT_SET_SETTINGS_RUNTIME */ #endif /* CONFIG_HAWKBIT_DDI_NO_SECURITY */ - +#ifdef CONFIG_HAWKBIT_SAVE_PROGRESS + char header_range[RANGE_HEADER_SIZE] = {0}; + char const *headers_range[] = {header_range, NULL}; +#endif http_req.url = url_buffer; http_req.host = HAWKBIT_SERVER_DOMAIN; http_req.port = HAWKBIT_PORT; @@ -1172,13 +1175,10 @@ static bool send_request(struct hawkbit_context *hb_context, enum hawkbit_http_r #ifdef CONFIG_HAWKBIT_SAVE_PROGRESS hb_context->dl.downloaded_size = flash_img_bytes_written(&hb_context->flash_ctx); if (IN_RANGE(hb_context->dl.downloaded_size, 1, hb_context->dl.file_size)) { - char header_range[RANGE_HEADER_SIZE] = {0}; - snprintf(header_range, sizeof(header_range), "Range: bytes=%u-" HTTP_CRLF, hb_context->dl.downloaded_size); - const char *const headers_range[] = {header_range, NULL}; - http_req.optional_headers = (const char **)headers_range; + http_req.optional_headers = headers_range; LOG_DBG("optional header: %s", header_range); LOG_INF("Resuming download from %d bytes", hb_context->dl.downloaded_size); } @@ -1209,6 +1209,11 @@ static bool send_request(struct hawkbit_context *hb_context, enum hawkbit_http_r void hawkbit_reboot(void) { hawkbit_event_raise(HAWKBIT_EVENT_BEFORE_REBOOT); + + if (IS_ENABLED(CONFIG_HAWKBIT_REBOOT_NONE)) { + return; + } + LOG_PANIC(); sys_reboot(IS_ENABLED(CONFIG_HAWKBIT_REBOOT_COLD) ? SYS_REBOOT_COLD : SYS_REBOOT_WARM); } diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/include/mgmt/mcumgr/grp/img_mgmt/img_mgmt_priv.h b/subsys/mgmt/mcumgr/grp/img_mgmt/include/mgmt/mcumgr/grp/img_mgmt/img_mgmt_priv.h index 133a1abf054fa..d584467ee2bfa 100644 --- a/subsys/mgmt/mcumgr/grp/img_mgmt/include/mgmt/mcumgr/grp/img_mgmt/img_mgmt_priv.h +++ b/subsys/mgmt/mcumgr/grp/img_mgmt/include/mgmt/mcumgr/grp/img_mgmt/img_mgmt_priv.h @@ -18,6 +18,14 @@ extern "C" { #endif +#ifdef CONFIG_MCUBOOT_BOOTLOADER_USES_SHA512 +#define IMAGE_TLV_SHA IMAGE_TLV_SHA512 +#define IMAGE_SHA_LEN 64 +#else +#define IMAGE_TLV_SHA IMAGE_TLV_SHA256 +#define IMAGE_SHA_LEN 32 +#endif + /** * @brief Ensures the spare slot (slot 1) is fully erased. * diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c index 035a765798ee8..7abcac8afad56 100644 --- a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c +++ b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c @@ -322,7 +322,7 @@ int img_mgmt_read_info(int image_slot, struct image_version *ver, uint8_t *hash, if (tlv.it_type == 0xff && tlv.it_len == 0xffff) { return IMG_MGMT_ERR_INVALID_TLV; } - if (tlv.it_type != IMAGE_TLV_SHA256 || tlv.it_len != IMAGE_HASH_LEN) { + if (tlv.it_type != IMAGE_TLV_SHA || tlv.it_len != IMAGE_SHA_LEN) { /* Non-hash TLV. Skip it. */ data_off += sizeof(tlv) + tlv.it_len; continue; @@ -336,10 +336,10 @@ int img_mgmt_read_info(int image_slot, struct image_version *ver, uint8_t *hash, data_off += sizeof(tlv); if (hash != NULL) { - if (data_off + IMAGE_HASH_LEN > data_end) { + if (data_off + IMAGE_SHA_LEN > data_end) { return IMG_MGMT_ERR_TLV_INVALID_SIZE; } - rc = img_mgmt_read(image_slot, data_off, hash, IMAGE_HASH_LEN); + rc = img_mgmt_read(image_slot, data_off, hash, IMAGE_SHA_LEN); if (rc != 0) { return rc; } @@ -382,13 +382,13 @@ int img_mgmt_find_by_hash(uint8_t *find, struct image_version *ver) { int i; - uint8_t hash[IMAGE_HASH_LEN]; + uint8_t hash[IMAGE_SHA_LEN]; for (i = 0; i < SLOTS_PER_IMAGE * CONFIG_MCUMGR_GRP_IMG_UPDATABLE_IMAGE_NUMBER; i++) { if (img_mgmt_read_info(i, ver, hash, NULL) != 0) { continue; } - if (!memcmp(hash, find, IMAGE_HASH_LEN)) { + if (!memcmp(hash, find, IMAGE_SHA_LEN)) { return i; } } @@ -698,7 +698,7 @@ img_mgmt_upload_good_rsp(struct smp_streamer *ctxt) static int img_mgmt_upload_log(bool is_first, bool is_last, int status) { - uint8_t hash[IMAGE_HASH_LEN]; + uint8_t hash[IMAGE_SHA_LEN]; const uint8_t *hashp; int rc; diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c index de9fba4a1c19b..fb15c15b6e9e7 100644 --- a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c +++ b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c @@ -435,8 +435,11 @@ static bool img_mgmt_state_encode_slot(struct smp_streamer *ctxt, uint32_t slot, zcbor_state_t *zse = ctxt->writer->zs; uint32_t flags; char vers_str[IMG_MGMT_VER_MAX_STR_LEN]; - uint8_t hash[IMAGE_HASH_LEN]; /* SHA256 hash */ - struct zcbor_string zhash = { .value = hash, .len = IMAGE_HASH_LEN }; + uint8_t hash[IMAGE_SHA_LEN]; + struct zcbor_string zhash = { + .value = hash, + .len = IMAGE_SHA_LEN, + }; struct image_version ver; bool ok; int rc = img_mgmt_read_info(slot, &ver, hash, &flags); @@ -780,14 +783,14 @@ img_mgmt_state_write(struct smp_streamer *ctxt) IMG_MGMT_ERR_INVALID_HASH); goto end; } - } else if (zhash.len != IMAGE_HASH_LEN) { + } else if (zhash.len != IMAGE_SHA_LEN) { /* The img_mgmt_find_by_hash does exact length compare * so just fail here. */ ok = smp_add_cmd_err(zse, MGMT_GROUP_ID_IMAGE, IMG_MGMT_ERR_INVALID_HASH); goto end; } else { - uint8_t hash[IMAGE_HASH_LEN]; + uint8_t hash[IMAGE_SHA_LEN]; memcpy(hash, zhash.value, zhash.len); diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h index 1fc8f165d3d57..118e3c7a6bea5 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h @@ -131,6 +131,8 @@ extern "C" { #define PROCESSOR_NAME "cortex-a76" #elif defined(CONFIG_CPU_CORTEX_A76) #define PROCESSOR_NAME "cortex-a76" +#elif defined(CONFIG_CPU_CORTEX_A78) +#define PROCESSOR_NAME "cortex-a78" #elif defined(CONFIG_CPU_CORTEX_R82) #define PROCESSOR_NAME "armv8.4-a+nolse" #endif diff --git a/subsys/modbus/modbus_serial.c b/subsys/modbus/modbus_serial.c index 416941b5838e7..7953025546ff8 100644 --- a/subsys/modbus/modbus_serial.c +++ b/subsys/modbus/modbus_serial.c @@ -291,7 +291,7 @@ static int modbus_rtu_rx_adu(struct modbus_context *ctx) return 0; } -static void rtu_tx_adu(struct modbus_context *ctx) +static void modbus_rtu_tx_adu(struct modbus_context *ctx) { struct modbus_serial_config *cfg = ctx->cfg; uint16_t tx_bytes = 0; @@ -560,7 +560,7 @@ int modbus_serial_tx_adu(struct modbus_context *ctx) { switch (ctx->mode) { case MODBUS_MODE_RTU: - rtu_tx_adu(ctx); + modbus_rtu_tx_adu(ctx); return 0; case MODBUS_MODE_ASCII: if (IS_ENABLED(CONFIG_MODBUS_ASCII_MODE)) { diff --git a/subsys/modem/Kconfig b/subsys/modem/Kconfig index c4f4c0cd8982c..b7c3f7ba9014c 100644 --- a/subsys/modem/Kconfig +++ b/subsys/modem/Kconfig @@ -3,7 +3,6 @@ menuconfig MODEM_MODULES bool "Modem modules" - select EXPERIMENTAL if MODEM_MODULES diff --git a/subsys/net/ip/connection.c b/subsys/net/ip/connection.c index 2140b84e25b9c..51e22ea16ffc4 100644 --- a/subsys/net/ip/connection.c +++ b/subsys/net/ip/connection.c @@ -637,7 +637,7 @@ static void conn_raw_socket_deliver(struct net_pkt *pkt, struct net_conn *conn, #endif /* defined(CONFIG_NET_SOCKETS_PACKET) || defined(CONFIG_NET_SOCKETS_INET_RAW) */ #if defined(CONFIG_NET_SOCKETS_PACKET) -enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto) +enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto, enum net_sock_type type) { bool raw_sock_found = false; bool raw_pkt_continue = false; @@ -670,7 +670,7 @@ enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto) continue; /* wrong family */ } - if (conn->type == SOCK_DGRAM && !net_pkt_is_l2_processed(pkt)) { + if (conn->type == SOCK_DGRAM && type == SOCK_RAW) { /* If DGRAM packet sockets are present, we shall continue * with this packet regardless the result. */ @@ -678,7 +678,7 @@ enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto) continue; /* L2 not processed yet */ } - if (conn->type == SOCK_RAW && net_pkt_is_l2_processed(pkt)) { + if (conn->type == SOCK_RAW && type != SOCK_RAW) { continue; /* L2 already processed */ } @@ -727,10 +727,11 @@ enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto) return NET_CONTINUE; } #else -enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto) +enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto, enum net_sock_type type) { ARG_UNUSED(pkt); ARG_UNUSED(proto); + ARG_UNUSED(type); return NET_CONTINUE; } diff --git a/subsys/net/ip/connection.h b/subsys/net/ip/connection.h index a6660cad6bbca..bc11703e16b6a 100644 --- a/subsys/net/ip/connection.h +++ b/subsys/net/ip/connection.h @@ -189,11 +189,14 @@ int net_conn_update(struct net_conn_handle *handle, * * @param pkt Network packet holding received data * @param proto LL protocol for the connection + * @param type socket type * * @return NET_OK if the packet was consumed, NET_CONTINUE if the packet should * be processed further in the stack. */ -enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto); +enum net_verdict net_conn_packet_input(struct net_pkt *pkt, + uint16_t proto, + enum net_sock_type type); /** * @brief Called by net_core.c when an IP packet is received diff --git a/subsys/net/ip/ipv4.c b/subsys/net/ip/ipv4.c index 9e7d7a900f6aa..1e902bf471534 100644 --- a/subsys/net/ip/ipv4.c +++ b/subsys/net/ip/ipv4.c @@ -240,7 +240,7 @@ int net_ipv4_parse_hdr_options(struct net_pkt *pkt, } #endif -enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback) +enum net_verdict net_ipv4_input(struct net_pkt *pkt) { NET_PKT_DATA_ACCESS_CONTIGUOUS_DEFINE(ipv4_access, struct net_ipv4_hdr); NET_PKT_DATA_ACCESS_DEFINE(udp_access, struct net_udp_hdr); @@ -301,7 +301,7 @@ enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback) net_pkt_update_length(pkt, pkt_len); } - if (!is_loopback) { + if (!net_pkt_is_loopback(pkt)) { if (net_ipv4_is_addr_loopback_raw(hdr->dst) || net_ipv4_is_addr_loopback_raw(hdr->src)) { NET_DBG("DROP: localhost packet"); diff --git a/subsys/net/ip/ipv4_fragment.c b/subsys/net/ip/ipv4_fragment.c index 3df39c28970b0..bbe41ab534ea3 100644 --- a/subsys/net/ip/ipv4_fragment.c +++ b/subsys/net/ip/ipv4_fragment.c @@ -211,9 +211,9 @@ static void reassemble_packet(struct net_ipv4_reassembly *reass) /* We need to use the queue when feeding the packet back into the * IP stack as we might run out of stack if we call processing_data() * directly. As the packet does not contain link layer header, we - * MUST NOT pass it to L2 so there will be a special check for that - * in process_data() when handling the packet. + * MUST NOT pass it to L2 so mark it as l2_processed. */ + net_pkt_set_l2_processed(pkt, true); if (net_recv_data(net_pkt_iface(pkt), pkt) >= 0) { return; } diff --git a/subsys/net/ip/ipv6.c b/subsys/net/ip/ipv6.c index 7cf8f7d58dcb7..e481f2ed84208 100644 --- a/subsys/net/ip/ipv6.c +++ b/subsys/net/ip/ipv6.c @@ -475,7 +475,7 @@ static inline bool is_src_non_tentative_itself(const uint8_t *src) return false; } -enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback) +enum net_verdict net_ipv6_input(struct net_pkt *pkt) { NET_PKT_DATA_ACCESS_CONTIGUOUS_DEFINE(ipv6_access, struct net_ipv6_hdr); NET_PKT_DATA_ACCESS_DEFINE(udp_access, struct net_udp_hdr); @@ -537,7 +537,7 @@ enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback) goto drop; } - if (!is_loopback) { + if (!net_pkt_is_loopback(pkt)) { if (net_ipv6_is_addr_loopback_raw(hdr->dst) || net_ipv6_is_addr_loopback_raw(hdr->src)) { NET_DBG("DROP: ::1 packet"); @@ -631,7 +631,7 @@ enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback) } if ((IS_ENABLED(CONFIG_NET_ROUTING) || IS_ENABLED(CONFIG_NET_ROUTE_MCAST)) && - !is_loopback && is_src_non_tentative_itself(hdr->src)) { + !net_pkt_is_loopback(pkt) && is_src_non_tentative_itself(hdr->src)) { NET_DBG("DROP: src addr is %s", "mine"); goto drop; } diff --git a/subsys/net/ip/ipv6_fragment.c b/subsys/net/ip/ipv6_fragment.c index 22408a46f9c14..dc913a7a6033c 100644 --- a/subsys/net/ip/ipv6_fragment.c +++ b/subsys/net/ip/ipv6_fragment.c @@ -346,9 +346,9 @@ static void reassemble_packet(struct net_ipv6_reassembly *reass) /* We need to use the queue when feeding the packet back into the * IP stack as we might run out of stack if we call processing_data() * directly. As the packet does not contain link layer header, we - * MUST NOT pass it to L2 so there will be a special check for that - * in process_data() when handling the packet. + * MUST NOT pass it to L2 so mark it as l2_processed. */ + net_pkt_set_l2_processed(pkt, true); if (net_recv_data(net_pkt_iface(pkt), pkt) >= 0) { return; } diff --git a/subsys/net/ip/net_core.c b/subsys/net/ip/net_core.c index e090e38aa4681..888ce9da9fc9e 100644 --- a/subsys/net/ip/net_core.c +++ b/subsys/net/ip/net_core.c @@ -64,27 +64,15 @@ LOG_MODULE_REGISTER(net_core, CONFIG_NET_CORE_LOG_LEVEL); #include "net_stats.h" #if defined(CONFIG_NET_NATIVE) -static inline enum net_verdict process_data(struct net_pkt *pkt, - bool is_loopback) +static inline enum net_verdict process_data(struct net_pkt *pkt) { int ret; - bool locally_routed = false; - net_pkt_set_l2_processed(pkt, false); - - /* Initial call will forward packets to SOCK_RAW packet sockets. */ - ret = net_packet_socket_input(pkt, ETH_P_ALL); + ret = net_packet_socket_input(pkt, ETH_P_ALL, SOCK_RAW); if (ret != NET_CONTINUE) { return ret; } - /* If the packet is routed back to us when we have reassembled an IPv4 or IPv6 packet, - * then do not pass it to L2 as the packet does not have link layer headers in it. - */ - if (net_pkt_is_ip_reassembled(pkt)) { - locally_routed = true; - } - /* If there is no data, then drop the packet. */ if (!pkt->frags) { NET_DBG("Corrupted packet (frags %p)", pkt->frags); @@ -93,8 +81,9 @@ static inline enum net_verdict process_data(struct net_pkt *pkt, return NET_DROP; } - if (!is_loopback && !locally_routed) { + if (!net_pkt_is_l2_processed(pkt)) { ret = net_if_recv_data(net_pkt_iface(pkt), pkt); + net_pkt_set_l2_processed(pkt, true); if (ret != NET_CONTINUE) { if (ret == NET_DROP) { NET_DBG("Packet %p discarded by L2", pkt); @@ -106,18 +95,13 @@ static inline enum net_verdict process_data(struct net_pkt *pkt, } } - net_pkt_set_l2_processed(pkt, true); - /* L2 has modified the buffer starting point, it is easier * to re-initialize the cursor rather than updating it. */ net_pkt_cursor_init(pkt); if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET_DGRAM)) { - /* Consecutive call will forward packets to SOCK_DGRAM packet sockets - * (after L2 removed header). - */ - ret = net_packet_socket_input(pkt, net_pkt_ll_proto_type(pkt)); + ret = net_packet_socket_input(pkt, net_pkt_ll_proto_type(pkt), SOCK_DGRAM); if (ret != NET_CONTINUE) { return ret; } @@ -131,9 +115,9 @@ static inline enum net_verdict process_data(struct net_pkt *pkt, uint8_t vtc_vhl = NET_IPV6_HDR(pkt)->vtc & 0xf0; if (IS_ENABLED(CONFIG_NET_IPV6) && vtc_vhl == 0x60) { - return net_ipv6_input(pkt, is_loopback); + return net_ipv6_input(pkt); } else if (IS_ENABLED(CONFIG_NET_IPV4) && vtc_vhl == 0x40) { - return net_ipv4_input(pkt, is_loopback); + return net_ipv4_input(pkt); } NET_DBG("Unknown IP family packet (0x%x)", NET_IPV6_HDR(pkt)->vtc & 0xf0); @@ -148,10 +132,10 @@ static inline enum net_verdict process_data(struct net_pkt *pkt, return NET_DROP; } -static void processing_data(struct net_pkt *pkt, bool is_loopback) +static void processing_data(struct net_pkt *pkt) { again: - switch (process_data(pkt, is_loopback)) { + switch (process_data(pkt)) { case NET_CONTINUE: if (IS_ENABLED(CONFIG_NET_L2_VIRTUAL)) { /* If we have a tunneling packet, feed it back @@ -421,7 +405,9 @@ int net_try_send_data(struct net_pkt *pkt, k_timeout_t timeout) * to RX processing. */ NET_DBG("Loopback pkt %p back to us", pkt); - processing_data(pkt, true); + net_pkt_set_loopback(pkt, true); + net_pkt_set_l2_processed(pkt, true); + processing_data(pkt); ret = 0; goto err; } @@ -481,7 +467,6 @@ int net_try_send_data(struct net_pkt *pkt, k_timeout_t timeout) static void net_rx(struct net_if *iface, struct net_pkt *pkt) { - bool is_loopback = false; size_t pkt_len; pkt_len = net_pkt_get_len(pkt); @@ -493,12 +478,13 @@ static void net_rx(struct net_if *iface, struct net_pkt *pkt) if (IS_ENABLED(CONFIG_NET_LOOPBACK)) { #ifdef CONFIG_NET_L2_DUMMY if (net_if_l2(iface) == &NET_L2_GET_NAME(DUMMY)) { - is_loopback = true; + net_pkt_set_loopback(pkt, true); + net_pkt_set_l2_processed(pkt, true); } #endif } - processing_data(pkt, is_loopback); + processing_data(pkt); net_print_statistics(); net_pkt_print(); diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index 495dbde59e086..502105fdb2c07 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -6415,6 +6415,11 @@ static void set_default_name(struct net_if *iface) static int count; snprintk(name, sizeof(name), "thread%d", count++); + } else if (IS_ENABLED(CONFIG_NET_VLAN) && + (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL))) { + static int count; + + snprintk(name, sizeof(name), "vlan%d", count++); } else { static int count; diff --git a/subsys/net/ip/net_pkt.c b/subsys/net/ip/net_pkt.c index 96bc95471f71f..34a018a270ff6 100644 --- a/subsys/net/ip/net_pkt.c +++ b/subsys/net/ip/net_pkt.c @@ -2050,6 +2050,7 @@ static void clone_pkt_attributes(struct net_pkt *pkt, struct net_pkt *clone_pkt) net_pkt_set_rx_timestamping(clone_pkt, net_pkt_is_rx_timestamping(pkt)); net_pkt_set_forwarding(clone_pkt, net_pkt_forwarding(pkt)); net_pkt_set_chksum_done(clone_pkt, net_pkt_is_chksum_done(pkt)); + net_pkt_set_loopback(pkt, net_pkt_is_loopback(pkt)); net_pkt_set_ip_reassembled(pkt, net_pkt_is_ip_reassembled(pkt)); net_pkt_set_cooked_mode(clone_pkt, net_pkt_is_cooked_mode(pkt)); net_pkt_set_ipv4_pmtu(clone_pkt, net_pkt_ipv4_pmtu(pkt)); diff --git a/subsys/net/ip/net_private.h b/subsys/net/ip/net_private.h index ff82973a577ed..11ae1be6b9fbd 100644 --- a/subsys/net/ip/net_private.h +++ b/subsys/net/ip/net_private.h @@ -183,25 +183,21 @@ extern void loopback_enable_address_swap(bool swap_addresses); #endif /* CONFIG_NET_TEST */ #if defined(CONFIG_NET_NATIVE) -enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback); -enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback); +enum net_verdict net_ipv4_input(struct net_pkt *pkt); +enum net_verdict net_ipv6_input(struct net_pkt *pkt); extern void net_tc_tx_init(void); extern void net_tc_rx_init(void); #else -static inline enum net_verdict net_ipv4_input(struct net_pkt *pkt, - bool is_loopback) +static inline enum net_verdict net_ipv4_input(struct net_pkt *pkt) { ARG_UNUSED(pkt); - ARG_UNUSED(is_loopback); return NET_CONTINUE; } -static inline enum net_verdict net_ipv6_input(struct net_pkt *pkt, - bool is_loopback) +static inline enum net_verdict net_ipv6_input(struct net_pkt *pkt) { ARG_UNUSED(pkt); - ARG_UNUSED(is_loopback); return NET_CONTINUE; } diff --git a/subsys/net/ip/packet_socket.c b/subsys/net/ip/packet_socket.c index 829e990dafefd..3ce571f5d8750 100644 --- a/subsys/net/ip/packet_socket.c +++ b/subsys/net/ip/packet_socket.c @@ -22,7 +22,9 @@ LOG_MODULE_REGISTER(net_sockets_raw, CONFIG_NET_SOCKETS_LOG_LEVEL); #include "connection.h" #include "packet_socket.h" -enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint16_t proto) +enum net_verdict net_packet_socket_input(struct net_pkt *pkt, + uint16_t proto, + enum net_sock_type type) { sa_family_t orig_family; enum net_verdict net_verdict; @@ -41,7 +43,7 @@ enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint16_t proto) net_pkt_set_family(pkt, AF_PACKET); - net_verdict = net_conn_packet_input(pkt, proto); + net_verdict = net_conn_packet_input(pkt, proto, type); net_pkt_set_family(pkt, orig_family); diff --git a/subsys/net/ip/packet_socket.h b/subsys/net/ip/packet_socket.h index b44717635b410..a2704c4e59140 100644 --- a/subsys/net/ip/packet_socket.h +++ b/subsys/net/ip/packet_socket.h @@ -26,10 +26,13 @@ * disabled, the function will always return NET_DROP. */ #if defined(CONFIG_NET_SOCKETS_PACKET) -enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint16_t proto); +enum net_verdict net_packet_socket_input(struct net_pkt *pkt, + uint16_t proto, + enum net_sock_type type); #else static inline enum net_verdict net_packet_socket_input(struct net_pkt *pkt, - uint16_t proto) + uint16_t proto, + enum net_sock_type type) { return NET_CONTINUE; } diff --git a/subsys/net/l2/ethernet/gptp/Kconfig b/subsys/net/l2/ethernet/gptp/Kconfig index 01c15f02d37ad..68c751727d49e 100644 --- a/subsys/net/l2/ethernet/gptp/Kconfig +++ b/subsys/net/l2/ethernet/gptp/Kconfig @@ -75,7 +75,7 @@ config NET_GPTP_CLOCK_ACCURACY_1MS bool "1ms" config NET_GPTP_CLOCK_ACCURACY_2_5MS - bool "1.5ms" + bool "2.5ms" config NET_GPTP_CLOCK_ACCURACY_10MS bool "10ms" diff --git a/subsys/net/l2/ethernet/vlan.c b/subsys/net/l2/ethernet/vlan.c index 23c73b40deb88..7e51b1d0d9c78 100644 --- a/subsys/net/l2/ethernet/vlan.c +++ b/subsys/net/l2/ethernet/vlan.c @@ -32,8 +32,6 @@ LOG_MODULE_REGISTER(net_ethernet_vlan, CONFIG_NET_L2_ETHERNET_LOG_LEVEL); */ #if CONFIG_NET_VLAN_COUNT > 0 -#define MAX_VLAN_NAME_LEN MIN(sizeof("VLAN-<#####>"), \ - CONFIG_NET_INTERFACE_NAME_LEN) #define MAX_VIRT_NAME_LEN MIN(sizeof(""), \ CONFIG_NET_L2_VIRTUAL_MAX_NAME_LEN) @@ -246,7 +244,7 @@ static bool enable_vlan_iface(struct vlan_context *ctx, struct net_if *iface) { int iface_idx = net_if_get_by_iface(iface); - char name[MAX(MAX_VLAN_NAME_LEN, MAX_VIRT_NAME_LEN)]; + char name[MAX_VIRT_NAME_LEN]; int ret; if (iface_idx < 0) { @@ -263,9 +261,6 @@ static bool enable_vlan_iface(struct vlan_context *ctx, ctx->is_used = true; - snprintk(name, sizeof(name), "VLAN-%d", ctx->tag); - net_if_set_name(ctx->iface, name); - snprintk(name, sizeof(name), "VLAN to %d", net_if_get_by_iface(ctx->attached_to)); net_virtual_set_name(ctx->iface, name); @@ -277,7 +272,7 @@ static bool disable_vlan_iface(struct vlan_context *ctx, struct net_if *iface) { int iface_idx = net_if_get_by_iface(iface); - char name[MAX(MAX_VLAN_NAME_LEN, MAX_VIRT_NAME_LEN)]; + char name[MAX_VIRT_NAME_LEN]; if (iface_idx < 0) { return false; @@ -286,9 +281,6 @@ static bool disable_vlan_iface(struct vlan_context *ctx, (void)net_virtual_interface_attach(iface, NULL); ctx->is_used = false; - snprintk(name, sizeof(name), "VLAN-"); - net_if_set_name(iface, name); - snprintk(name, sizeof(name), ""); net_virtual_set_name(iface, name); @@ -659,7 +651,7 @@ static int vlan_interface_attach(struct net_if *vlan_iface, static void vlan_iface_init(struct net_if *iface) { struct vlan_context *ctx = net_if_get_device(iface)->data; - char name[MAX(MAX_VLAN_NAME_LEN, MAX_VIRT_NAME_LEN)]; + char name[MAX_VIRT_NAME_LEN]; if (ctx->init_done) { return; @@ -668,9 +660,6 @@ static void vlan_iface_init(struct net_if *iface) ctx->iface = iface; net_if_flag_set(iface, NET_IF_NO_AUTO_START); - snprintk(name, sizeof(name), "VLAN-"); - net_if_set_name(iface, name); - snprintk(name, sizeof(name), "not attached"); net_virtual_set_name(iface, name); diff --git a/subsys/net/l2/virtual/ipip/ipip.c b/subsys/net/l2/virtual/ipip/ipip.c index 44b7c51c8c478..bd339ea213260 100644 --- a/subsys/net/l2/virtual/ipip/ipip.c +++ b/subsys/net/l2/virtual/ipip/ipip.c @@ -374,7 +374,10 @@ static enum net_verdict interface_recv(struct net_if *iface, net_pkt_cursor_restore(pkt, &hdr_start); - return net_ipv6_input(pkt, false); + /* Ensure the loopback flag is no longer set */ + net_pkt_set_loopback(pkt, false); + + return net_ipv6_input(pkt); } if (IS_ENABLED(CONFIG_NET_IPV4) && net_pkt_family(pkt) == AF_INET) { @@ -421,7 +424,10 @@ static enum net_verdict interface_recv(struct net_if *iface, net_pkt_cursor_restore(pkt, &hdr_start); - return net_ipv4_input(pkt, false); + /* Ensure the loopback flag is no longer set */ + net_pkt_set_loopback(pkt, false); + + return net_ipv4_input(pkt); } return NET_CONTINUE; diff --git a/subsys/net/l2/wifi/Kconfig b/subsys/net/l2/wifi/Kconfig index 49d061c7439c9..63680dba9b30a 100644 --- a/subsys/net/l2/wifi/Kconfig +++ b/subsys/net/l2/wifi/Kconfig @@ -82,6 +82,7 @@ if WIFI_NM config WIFI_NM_MAX_MANAGED_INTERFACES int "Maximum number of managed interfaces per Wi-Fi network manager" + default 2 if WIFI_USAGE_MODE_STA_AP default 1 help This option defines the maximum number of managed interfaces per Wi-Fi diff --git a/subsys/net/lib/config/Kconfig b/subsys/net/lib/config/Kconfig index fe7577229c97b..3e9685643172f 100644 --- a/subsys/net/lib/config/Kconfig +++ b/subsys/net/lib/config/Kconfig @@ -248,10 +248,12 @@ if NET_CONFIG_SNTP_INIT_RESYNC config NET_CONFIG_SNTP_INIT_RESYNC_INTERVAL int "SNTP resync interval (sec)" default 3600 + range 15 $(UINT32_MAX) config NET_CONFIG_SNTP_INIT_RESYNC_ON_FAILURE_INTERVAL int "SNTP resync interval (sec) on failure" default NET_CONFIG_SNTP_INIT_RESYNC_INTERVAL + range 15 $(UINT32_MAX) help If the SNTP request fails, then this is the interval to wait before trying again. diff --git a/subsys/net/lib/config/init_clock_sntp.c b/subsys/net/lib/config/init_clock_sntp.c index a426f79cfc1e2..5eeae0a8df5a1 100644 --- a/subsys/net/lib/config/init_clock_sntp.c +++ b/subsys/net/lib/config/init_clock_sntp.c @@ -53,13 +53,14 @@ int net_init_clock_via_sntp(void) int res = sntp_init_helper(&ts); if (res < 0) { - LOG_ERR("Cannot set time using SNTP"); + LOG_ERR("Cannot set time using SNTP: %d", res); goto end; } tspec.tv_sec = ts.seconds; tspec.tv_nsec = ((uint64_t)ts.fraction * (1000 * 1000 * 1000)) >> 32; res = sys_clock_settime(SYS_CLOCK_REALTIME, &tspec); + LOG_DBG("Time synced using SNTP"); end: #ifdef CONFIG_NET_CONFIG_SNTP_INIT_RESYNC @@ -74,16 +75,8 @@ int net_init_clock_via_sntp(void) #ifdef CONFIG_NET_CONFIG_SNTP_INIT_RESYNC static void sntp_resync_handler(struct k_work *work) { - int res; - ARG_UNUSED(work); - - res = net_init_clock_via_sntp(); - if (res < 0) { - LOG_ERR("Cannot resync time using SNTP"); - return; - } - LOG_DBG("Time resynced using SNTP"); + (void)net_init_clock_via_sntp(); } #endif /* CONFIG_NET_CONFIG_SNTP_INIT_RESYNC */ diff --git a/subsys/net/lib/dns/Kconfig b/subsys/net/lib/dns/Kconfig index 2804e856d4bd8..0edce7b61becf 100644 --- a/subsys/net/lib/dns/Kconfig +++ b/subsys/net/lib/dns/Kconfig @@ -87,6 +87,15 @@ config DNS_RESOLVER_MAX_NAME_LEN DNS server. For example if we query a DNS-SD service, then this value should be long enough to store the returned string. +config DNS_RESOLVER_MAX_TEXT_LEN + int "Max length of the resolved DNS text string in a record" + range 1 $(UINT8_MAX) + default 255 if DNS_SD + default 64 + help + Max length of a buffer that is used to store text record string + returned from a DNS server. + menuconfig DNS_SERVER_IP_ADDRESSES bool "Set DNS server IP addresses" help diff --git a/subsys/net/lib/dns/dns_pack.c b/subsys/net/lib/dns/dns_pack.c index 78d5d50d949a9..a6f9c91cf4845 100644 --- a/subsys/net/lib/dns/dns_pack.c +++ b/subsys/net/lib/dns/dns_pack.c @@ -170,6 +170,14 @@ int dns_unpack_answer(struct dns_msg_t *dns_msg, int dname_ptr, uint32_t *ttl, set_dns_msg_response(dns_msg, DNS_RESPONSE_DATA, pos, len); return 0; + case DNS_RR_TYPE_TXT: + set_dns_msg_response(dns_msg, DNS_RESPONSE_TXT, pos, len); + return 0; + + case DNS_RR_TYPE_SRV: + set_dns_msg_response(dns_msg, DNS_RESPONSE_SRV, pos, len); + return 0; + case DNS_RR_TYPE_CNAME: set_dns_msg_response(dns_msg, DNS_RESPONSE_CNAME_NO_IP, pos, len); @@ -545,7 +553,10 @@ int dns_unpack_name(const uint8_t *msg, int maxlen, const uint8_t *src, loop_check += label_len + 1; - net_buf_add_u8(buf, '.'); + /* separate labels by periods */ + if (buf->len > 0) { + net_buf_add_u8(buf, '.'); + } net_buf_add_mem(buf, curr_src, label_len); curr_src += label_len; diff --git a/subsys/net/lib/dns/dns_pack.h b/subsys/net/lib/dns/dns_pack.h index a22a6197d2192..fc953a01c6d05 100644 --- a/subsys/net/lib/dns/dns_pack.h +++ b/subsys/net/lib/dns/dns_pack.h @@ -99,8 +99,10 @@ enum dns_rr_type { enum dns_response_type { DNS_RESPONSE_INVALID = -EINVAL, - DNS_RESPONSE_IP, + DNS_RESPONSE_IP = 1, DNS_RESPONSE_DATA, + DNS_RESPONSE_TXT, + DNS_RESPONSE_SRV, DNS_RESPONSE_CNAME_WITH_IP, DNS_RESPONSE_CNAME_NO_IP }; @@ -322,6 +324,21 @@ static inline int dns_answer_rdlength(uint16_t dname_size, return ntohs(UNALIGNED_GET((uint16_t *)(answer + dname_size + 8))); } +static inline int dns_unpack_srv_priority(const uint8_t *srv) +{ + return ntohs(UNALIGNED_GET((uint16_t *)(srv + 0))); +} + +static inline int dns_unpack_srv_weight(const uint8_t *srv) +{ + return ntohs(UNALIGNED_GET((uint16_t *)(srv + 2))); +} + +static inline int dns_unpack_srv_port(const uint8_t *srv) +{ + return ntohs(UNALIGNED_GET((uint16_t *)(srv + 4))); +} + /** * @brief Packs a QNAME * diff --git a/subsys/net/lib/dns/resolve.c b/subsys/net/lib/dns/resolve.c index 1f533f1e2a2b9..33070482f862b 100644 --- a/subsys/net/lib/dns/resolve.c +++ b/subsys/net/lib/dns/resolve.c @@ -1023,6 +1023,65 @@ static inline int get_slot_by_id(struct dns_resolve_context *ctx, return -ENOENT; } +static int update_query_idx(struct dns_resolve_context *ctx, + struct dns_msg_t *dns_msg, + uint16_t *dns_id, + int *query_idx, + uint16_t *query_hash) +{ + int ret; + char *query_name; + int query_name_len; + + query_name = dns_msg->msg + dns_msg->query_offset; + query_name_len = strlen(query_name); + + /* Convert the query name to small case so that our + * hash checker can find it. + */ + for (size_t i = 0, n = query_name_len; i < n; i++) { + query_name[i] = tolower(query_name[i]); + } + + /* Hash the name with \0 and query type */ + *query_hash = crc16_ansi(query_name, + query_name_len + 1 + 2); + + *query_idx = get_slot_by_id(ctx, *dns_id, *query_hash); + if (*query_idx < 0) { + /* Re-check if this was a mDNS probe query */ + if (IS_ENABLED(CONFIG_MDNS_RESPONDER_PROBE) && *dns_id == 0) { + uint16_t orig_qtype; + + orig_qtype = sys_get_be16(&query_name[query_name_len + 1]); + + /* Replace the query type with ANY as that was used + * when creating the hash. + */ + sys_put_be16(DNS_RR_TYPE_ANY, + &query_name[query_name_len + 1]); + + *query_hash = crc16_ansi(query_name, + query_name_len + 1 + 2); + + sys_put_be16(orig_qtype, &query_name[query_name_len + 1]); + + *query_idx = get_slot_by_id(ctx, *dns_id, *query_hash); + if (*query_idx < 0) { + ret = -ENOENT; + goto quit; + } + } else { + ret = -ENOENT; + goto quit; + } + } + + ret = 0; +quit: + return ret; +} + /* Unit test needs to be able to call this function */ #if !defined(CONFIG_NET_TEST) static @@ -1037,7 +1096,6 @@ int dns_validate_msg(struct dns_resolve_context *ctx, struct dns_addrinfo info = { 0 }; uint32_t ttl; /* RR ttl, so far it is not passed to caller */ uint8_t *src, *addr; - char *query_name; int address_size; /* index that points to the current answer being analyzed */ int answer_ptr; @@ -1131,61 +1189,17 @@ int dns_validate_msg(struct dns_resolve_context *ctx, switch (dns_msg->response_type) { case DNS_RESPONSE_DATA: - case DNS_RESPONSE_IP: { - int query_name_len; - - if (*query_idx >= 0) { - goto query_known; - } - - query_name = dns_msg->msg + dns_msg->query_offset; - - query_name_len = strlen(query_name); - - /* Convert the query name to small case so that our - * hash checker can find it. - */ - for (size_t i = 0, n = query_name_len; i < n; i++) { - query_name[i] = tolower(query_name[i]); - } - - /* Add \0 and query type (A or AAAA) to the hash */ - *query_hash = crc16_ansi(query_name, - query_name_len + 1 + 2); - - *query_idx = get_slot_by_id(ctx, *dns_id, *query_hash); + case DNS_RESPONSE_IP: if (*query_idx < 0) { - /* Re-check if this was a mDNS probe query */ - if (IS_ENABLED(CONFIG_MDNS_RESPONDER_PROBE) && *dns_id == 0) { - uint16_t orig_qtype; - - orig_qtype = sys_get_be16(&query_name[query_name_len + 1]); - - /* Replace the query type with ANY as that was used - * when creating the hash. - */ - sys_put_be16(DNS_RR_TYPE_ANY, - &query_name[query_name_len + 1]); - - *query_hash = crc16_ansi(query_name, - query_name_len + 1 + 2); - - sys_put_be16(orig_qtype, &query_name[query_name_len + 1]); - - *query_idx = get_slot_by_id(ctx, *dns_id, *query_hash); - if (*query_idx < 0) { - errno = ENOENT; - ret = DNS_EAI_SYSTEM; - goto quit; - } - } else { - errno = ENOENT; + ret = update_query_idx(ctx, dns_msg, dns_id, + query_idx, query_hash); + if (ret < 0) { + errno = -ret; ret = DNS_EAI_SYSTEM; goto quit; } } -query_known: if (ctx->queries[*query_idx].query_type == DNS_QUERY_TYPE_A) { if (answer_type != DNS_RR_TYPE_A) { @@ -1274,7 +1288,7 @@ int dns_validate_msg(struct dns_resolve_context *ctx, info.ai_family = AF_LOCAL; info.ai_addrlen = MIN(result->len, DNS_MAX_NAME_SIZE); - memcpy(&info.ai_canonname, result->data, info.ai_addrlen); + memcpy(info.ai_canonname, result->data, info.ai_addrlen); info.ai_canonname[info.ai_addrlen] = '\0'; net_buf_unref(result); @@ -1307,6 +1321,103 @@ int dns_validate_msg(struct dns_resolve_context *ctx, memcpy(addr, src, address_size); } + invoke_query_callback(DNS_EAI_INPROGRESS, &info, + &ctx->queries[*query_idx]); +#ifdef CONFIG_DNS_RESOLVER_CACHE + dns_cache_add(&dns_cache, + ctx->queries[*query_idx].query, &info, ttl); +#endif /* CONFIG_DNS_RESOLVER_CACHE */ + items++; + break; + + case DNS_RESPONSE_TXT: { + uint8_t *pos; + + if (*query_idx < 0) { + ret = update_query_idx(ctx, dns_msg, dns_id, + query_idx, query_hash); + if (ret < 0) { + errno = -ret; + ret = DNS_EAI_SYSTEM; + goto quit; + } + } + + pos = dns_msg->msg + dns_msg->response_position; + + info.ai_family = AF_UNSPEC; + info.ai_extension = DNS_RESOLVE_TXT; + info.ai_txt.textlen = MIN(dns_msg->response_length, + DNS_MAX_TEXT_SIZE); + memcpy(info.ai_txt.text, pos, info.ai_txt.textlen); + info.ai_txt.text[info.ai_txt.textlen] = '\0'; + + invoke_query_callback(DNS_EAI_INPROGRESS, &info, + &ctx->queries[*query_idx]); + break; + } + case DNS_RESPONSE_SRV: { + int priority; + int weight; + int port; + struct net_buf *target; + uint8_t *pos; + + if (*query_idx < 0) { + ret = update_query_idx(ctx, dns_msg, dns_id, + query_idx, query_hash); + if (ret < 0) { + errno = -ret; + ret = DNS_EAI_SYSTEM; + goto quit; + } + } + + address_size = MIN(dns_msg->response_length, + 6 + DNS_MAX_NAME_SIZE); + if (address_size < 6) { + /* 3 tuples of be16 - priority, weight, port */ + errno = EMSGSIZE; + ret = DNS_EAI_SYSTEM; + goto quit; + } + + /* Temporary buffer that is needed by dns_unpack_name() + * to unpack the target. + */ + target = net_buf_alloc(&dns_qname_pool, ctx->buf_timeout); + if (target == NULL) { + NET_DBG("Cannot allocate buffer for DNS query target"); + ret = DNS_EAI_MEMORY; + goto quit; + } + + pos = dns_msg->msg + dns_msg->response_position; + + priority = dns_unpack_srv_priority(pos); + weight = dns_unpack_srv_weight(pos); + port = dns_unpack_srv_port(pos); + + ret = dns_unpack_name(dns_msg->msg, dns_msg->msg_size, pos + 6, + target, NULL); + if (ret < 0) { + errno = -ret; + ret = DNS_EAI_SYSTEM; + net_buf_unref(target); + goto quit; + } + + info.ai_family = AF_UNSPEC; + info.ai_extension = DNS_RESOLVE_SRV; + info.ai_srv.priority = priority; + info.ai_srv.weight = weight; + info.ai_srv.port = port; + info.ai_srv.targetlen = MIN(target->len, DNS_MAX_NAME_SIZE); + memcpy(info.ai_srv.target, target->data, info.ai_srv.targetlen); + info.ai_srv.target[info.ai_srv.targetlen] = '\0'; + + net_buf_unref(target); + invoke_query_callback(DNS_EAI_INPROGRESS, &info, &ctx->queries[*query_idx]); #ifdef CONFIG_DNS_RESOLVER_CACHE @@ -1340,13 +1451,10 @@ int dns_validate_msg(struct dns_resolve_context *ctx, /* If the query_idx is still unknown, try to get it here * and hope it is found. */ - query_name = dns_msg->msg + dns_msg->query_offset; - *query_hash = crc16_ansi(query_name, - strlen(query_name) + 1 + 2); - - *query_idx = get_slot_by_id(ctx, *dns_id, *query_hash); - if (*query_idx < 0) { - errno = ENOENT; + ret = update_query_idx(ctx, dns_msg, dns_id, + query_idx, query_hash); + if (ret < 0) { + errno = -ret; ret = DNS_EAI_SYSTEM; goto quit; } diff --git a/subsys/net/lib/http/Kconfig b/subsys/net/lib/http/Kconfig index 824de81d57980..f36fb6d053934 100644 --- a/subsys/net/lib/http/Kconfig +++ b/subsys/net/lib/http/Kconfig @@ -179,7 +179,7 @@ config HTTP_SERVER_RESTART_DELAY range 1 60000 help In case server restarts for any reason, the server re-initialization - will be delayed by this value (miliseconds). The delay is needed to + will be delayed by this value (milliseconds). The delay is needed to allow any existing connections to finalize to avoid binding errors during initialization. diff --git a/subsys/net/lib/ocpp/Kconfig b/subsys/net/lib/ocpp/Kconfig index 5d6507f0e0553..d3b64184118b5 100644 --- a/subsys/net/lib/ocpp/Kconfig +++ b/subsys/net/lib/ocpp/Kconfig @@ -31,10 +31,10 @@ config OCPP_WSREADER_THREAD_STACKSIZE OCPP websocket reader thread stacksize config OCPP_RECV_BUFFER_SIZE - int "OCPP websocket recive buffer size" + int "OCPP websocket receive buffer size" default 2048 help - OCPP websocket recive buffer size + OCPP websocket receive buffer size config OCPP_INTERNAL_MSGQ_CNT int "OCPP internal message queue count" @@ -73,7 +73,7 @@ config OCPP_PROFILE_LOCAL_AUTH_LIST help Enables the OCPP library to support the Local Authorization List functionality. Stores IdTag and its validity information in the - persistent stroage. Charge Point may support this as optional. + persistent storage. Charge Point may support this as optional. config OCPP_PROFILE_FIRMWARE_MGNT bool "OCPP profile firmware management" diff --git a/subsys/net/lib/shell/dns.c b/subsys/net/lib/shell/dns.c index ee45a98a298e0..4bff14452d0c5 100644 --- a/subsys/net/lib/shell/dns.c +++ b/subsys/net/lib/shell/dns.c @@ -5,6 +5,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include +#include + #include LOG_MODULE_DECLARE(net_shell); @@ -31,21 +34,46 @@ static void dns_result_cb(enum dns_resolve_status status, #define MAX_STR_LEN CONFIG_DNS_RESOLVER_MAX_NAME_LEN char str[MAX_STR_LEN + 1]; - if (info->ai_family == AF_INET) { + switch (info->ai_family) { + case AF_INET: net_addr_ntop(AF_INET, &net_sin(&info->ai_addr)->sin_addr, str, NET_IPV4_ADDR_LEN); - } else if (info->ai_family == AF_INET6) { + break; + + case AF_INET6: net_addr_ntop(AF_INET6, &net_sin6(&info->ai_addr)->sin6_addr, str, NET_IPV6_ADDR_LEN); - } else if (info->ai_family == AF_LOCAL) { + break; + + case AF_LOCAL: /* service discovery */ memset(str, 0, MAX_STR_LEN); memcpy(str, info->ai_canonname, MIN(info->ai_addrlen, MAX_STR_LEN)); - } else { + break; + + case AF_UNSPEC: + if (info->ai_extension == DNS_RESOLVE_TXT) { + memset(str, 0, MAX_STR_LEN); + memcpy(str, info->ai_txt.text, + MIN(info->ai_txt.textlen, MAX_STR_LEN)); + break; + } else if (info->ai_extension == DNS_RESOLVE_SRV) { + snprintf(str, sizeof(str), "%d %d %d %.*s", + info->ai_srv.priority, + info->ai_srv.weight, + info->ai_srv.port, + (int)info->ai_srv.targetlen, + info->ai_srv.target); + break; + } + + /* fallthru */ + default: strncpy(str, "Invalid proto family", MAX_STR_LEN + 1); + break; } str[MAX_STR_LEN] = '\0'; @@ -210,6 +238,7 @@ static int cmd_net_dns_query(const struct shell *sh, size_t argc, char *argv[]) #if defined(CONFIG_DNS_RESOLVER) #define DNS_TIMEOUT (MSEC_PER_SEC * 2) /* ms */ + struct dns_resolve_context *ctx; enum dns_query_type qtype = DNS_QUERY_TYPE_A; char *host, *type = NULL; int ret, arg = 1; @@ -225,20 +254,38 @@ static int cmd_net_dns_query(const struct shell *sh, size_t argc, char *argv[]) } if (type) { - if (strcmp(type, "A") == 0) { + if (strcasecmp(type, "A") == 0) { qtype = DNS_QUERY_TYPE_A; - PR("IPv4 address type\n"); - } else if (strcmp(type, "AAAA") == 0) { + PR("IPv4 address query type\n"); + } else if (strcasecmp(type, "CNAME") == 0) { + qtype = DNS_QUERY_TYPE_CNAME; + PR("CNAME query type\n"); + } else if (strcasecmp(type, "PTR") == 0) { + qtype = DNS_QUERY_TYPE_PTR; + PR("Pointer query type\n"); + } else if (strcasecmp(type, "TXT") == 0) { + qtype = DNS_QUERY_TYPE_TXT; + PR("Text query type\n"); + } else if (strcasecmp(type, "AAAA") == 0) { qtype = DNS_QUERY_TYPE_AAAA; - PR("IPv6 address type\n"); + PR("IPv6 address query type\n"); + } else if (strcasecmp(type, "SRV") == 0) { + qtype = DNS_QUERY_TYPE_SRV; + PR("Service query type\n"); } else { PR_WARNING("Unknown query type, specify either " - "A or AAAA\n"); + "A, CNAME, PTR, TXT, AAAA, or SRV\n"); return -ENOEXEC; } } - ret = dns_get_addr_info(host, qtype, NULL, dns_result_cb, + ctx = dns_resolve_get_default(); + if (!ctx) { + PR_WARNING("No default DNS context found.\n"); + return -ENOEXEC; + } + + ret = dns_resolve_name(ctx, host, qtype, NULL, dns_result_cb, (void *)sh, DNS_TIMEOUT); if (ret < 0) { PR_WARNING("Cannot resolve '%s' (%d)\n", host, ret); diff --git a/subsys/net/lib/shell/vlan.c b/subsys/net/lib/shell/vlan.c index 824832f4054d9..b0a52afca0d7e 100644 --- a/subsys/net/lib/shell/vlan.c +++ b/subsys/net/lib/shell/vlan.c @@ -45,18 +45,16 @@ static void iface_vlan_del_cb(struct net_if *iface, void *user_data) static void iface_vlan_cb(struct net_if *iface, void *user_data) { + struct virtual_interface_context *ctx; struct net_shell_user_data *data = user_data; const struct shell *sh = data->sh; int *count = data->user_data; char name[IFNAMSIZ]; - if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) { + if (!net_eth_is_vlan_interface(iface)) { return; } - if (!(net_virtual_get_iface_capabilities(iface) & VIRTUAL_INTERFACE_VLAN)) { - return; - } if (*count == 0) { PR(" Interface Name \tTag\tAttached\n"); @@ -64,9 +62,14 @@ static void iface_vlan_cb(struct net_if *iface, void *user_data) (void)net_if_get_name(iface, name, sizeof(name)); - PR("[%d] %p %-12s\t%d\t%d\n", net_if_get_by_iface(iface), iface, - name, net_eth_get_vlan_tag(iface), - net_if_get_by_iface(net_eth_get_vlan_main(iface))); + ctx = net_if_l2_data(iface); + if (ctx->iface != NULL) { + PR("[%d] %p %-12s\t%d\t%d\n", net_if_get_by_iface(iface), iface, + name, net_eth_get_vlan_tag(iface), + net_if_get_by_iface(net_eth_get_vlan_main(iface))); + } else { + PR("[%d] %p %-12s\n", net_if_get_by_iface(iface), iface, name); + } (*count)++; } diff --git a/subsys/net/lib/wifi_credentials/Kconfig b/subsys/net/lib/wifi_credentials/Kconfig index d0843d689a28c..1a5671ccd739a 100644 --- a/subsys/net/lib/wifi_credentials/Kconfig +++ b/subsys/net/lib/wifi_credentials/Kconfig @@ -44,7 +44,7 @@ config WIFI_CREDENTIALS_MAX_ENTRIES int "Number of supported WiFi credentials" default 2 help - This detemines how many different WiFi networks can be configured at a time. + This determines how many different WiFi networks can be configured at a time. config WIFI_CREDENTIALS_SAE_PASSWORD_LENGTH int "Max. length of SAE password" diff --git a/subsys/pm/device_runtime.c b/subsys/pm/device_runtime.c index 2b04a44854980..490d7de493349 100644 --- a/subsys/pm/device_runtime.c +++ b/subsys/pm/device_runtime.c @@ -321,6 +321,7 @@ static int put_sync_locked(const struct device *dev) if (pm->base.usage == 0U) { ret = pm->base.action_cb(dev, PM_DEVICE_ACTION_SUSPEND); if (ret < 0) { + pm->base.usage++; return ret; } pm->base.state = PM_DEVICE_STATE_SUSPENDED; diff --git a/subsys/pm/policy/Kconfig b/subsys/pm/policy/Kconfig index 1a224c4ecc760..eb54df9798061 100644 --- a/subsys/pm/policy/Kconfig +++ b/subsys/pm/policy/Kconfig @@ -38,7 +38,7 @@ config PM_POLICY_LATENCY_STANDALONE depends on !PM help This option allows using the pm_policy_latency* APIs to gather latency - requirements on systems that do not support PM (e.g. systems whithout + requirements on systems that do not support PM (e.g. systems without CPU idle states). Because the API has a subscription mechanism, it can be useful to perform system-level adjustments based on latency requirements gathered from multiple system components. diff --git a/subsys/pm/policy/policy_default.c b/subsys/pm/policy/policy_default.c index 7c917264e78f5..fd1976c93f7cf 100644 --- a/subsys/pm/policy/policy_default.c +++ b/subsys/pm/policy/policy_default.c @@ -25,10 +25,13 @@ const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks) for (uint32_t i = 0; i < num_cpu_states; i++) { const struct pm_state_info *state = &cpu_states[i]; - uint32_t min_residency_ticks; + uint32_t min_residency_ticks = 0; + uint32_t min_residency_us = state->min_residency_us + state->exit_latency_us; - min_residency_ticks = - k_us_to_ticks_ceil32(state->min_residency_us + state->exit_latency_us); + /* If the input is zero, avoid 64-bit conversion from microseconds to ticks. */ + if (min_residency_us > 0) { + min_residency_ticks = k_us_to_ticks_ceil32(min_residency_us); + } if (ticks < min_residency_ticks) { /* If current state has higher residency then use the previous state; */ diff --git a/subsys/pmci/Kconfig b/subsys/pmci/Kconfig index 917a084a52ffb..7f7a04029c913 100644 --- a/subsys/pmci/Kconfig +++ b/subsys/pmci/Kconfig @@ -3,7 +3,7 @@ # Copyright (c) 2025 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -menu "Platform Management Communication Infrastruction (PMCI)" +menu "Platform Management Communications Infrastructure (PMCI)" # zephyr-keep-sorted-start diff --git a/subsys/portability/cmsis_rtos_v1/cmsis_kernel.c b/subsys/portability/cmsis_rtos_v1/cmsis_kernel.c index cd3b7263c4acd..0e61a1b8ea913 100644 --- a/subsys/portability/cmsis_rtos_v1/cmsis_kernel.c +++ b/subsys/portability/cmsis_rtos_v1/cmsis_kernel.c @@ -5,7 +5,6 @@ */ #include -#include #include #include diff --git a/subsys/portability/cmsis_rtos_v2/thread.c b/subsys/portability/cmsis_rtos_v2/thread.c index 8c5c1186b9991..699331ce27c5f 100644 --- a/subsys/portability/cmsis_rtos_v2/thread.c +++ b/subsys/portability/cmsis_rtos_v2/thread.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include #include diff --git a/subsys/retention/Kconfig.blinfo b/subsys/retention/Kconfig.blinfo index 57c5222511afd..0f7af1ef2e2b3 100644 --- a/subsys/retention/Kconfig.blinfo +++ b/subsys/retention/Kconfig.blinfo @@ -5,7 +5,7 @@ menuconfig RETENTION_BOOTLOADER_INFO bool "Bootloader info" help Adds a bootloader information sharing system which allows for - retreiving data from the bootloader when data sharing is enabled. + retrieving data from the bootloader when data sharing is enabled. if RETENTION_BOOTLOADER_INFO diff --git a/subsys/rtio/CMakeLists.txt b/subsys/rtio/CMakeLists.txt index f75eaa7912af4..8fa968b771a65 100644 --- a/subsys/rtio/CMakeLists.txt +++ b/subsys/rtio/CMakeLists.txt @@ -11,7 +11,7 @@ if(CONFIG_RTIO) zephyr_library_sources(rtio_executor.c) zephyr_library_sources(rtio_init.c) zephyr_library_sources(rtio_sched.c) - zephyr_library_sources_ifdef(CONFIG_USERSPACE rtio_handlers.c) + zephyr_library_sources_ifdef(CONFIG_USERSPACE rtio_syscalls.c) endif() zephyr_library_sources_ifdef(CONFIG_RTIO_WORKQ rtio_workq.c) diff --git a/subsys/rtio/rtio_executor.c b/subsys/rtio/rtio_executor.c index 6a4c800053273..eb42760300cce 100644 --- a/subsys/rtio/rtio_executor.c +++ b/subsys/rtio/rtio_executor.c @@ -12,6 +12,22 @@ #include LOG_MODULE_REGISTER(rtio_executor, CONFIG_RTIO_LOG_LEVEL); +/** + * @brief Callback which completes an RTIO_AWAIT_OP handled by the executor + * + * The callback is triggered when the rtio_sqe tied to the RTIO_AWAIT_OP + * is signaled by the user. + * + * @param iodev_sqe Submission to complete + * @param userdata Additional data passed along + */ +static void rtio_executor_sqe_signaled(struct rtio_iodev_sqe *iodev_sqe, void *userdata) +{ + ARG_UNUSED(userdata); + + rtio_iodev_sqe_ok(iodev_sqe, 0); +} + /** * @brief Executor handled submissions */ @@ -27,6 +43,9 @@ static void rtio_executor_op(struct rtio_iodev_sqe *iodev_sqe) case RTIO_OP_DELAY: rtio_sched_alarm(iodev_sqe, sqe->delay.timeout); break; + case RTIO_OP_AWAIT: + rtio_iodev_sqe_await_signal(iodev_sqe, rtio_executor_sqe_signaled, NULL); + break; default: rtio_iodev_sqe_err(iodev_sqe, -EINVAL); } diff --git a/subsys/rtio/rtio_handlers.c b/subsys/rtio/rtio_syscalls.c similarity index 88% rename from subsys/rtio/rtio_handlers.c rename to subsys/rtio/rtio_syscalls.c index beb2a545c520b..08e91a508615f 100644 --- a/subsys/rtio/rtio_handlers.c +++ b/subsys/rtio/rtio_syscalls.c @@ -135,3 +135,22 @@ static inline int z_vrfy_rtio_submit(struct rtio *r, uint32_t wait_count) return z_impl_rtio_submit(r, wait_count); } #include + + +static inline struct rtio *z_vrfy_rtio_pool_acquire(struct rtio_pool *rpool) +{ + K_OOPS(K_SYSCALL_OBJ(rpool, K_OBJ_RTIO_POOL)); + + return z_impl_rtio_pool_acquire(rpool); +} +#include + + +static inline void z_vrfy_rtio_pool_release(struct rtio_pool *rpool, struct rtio *r) +{ + K_OOPS(K_SYSCALL_OBJ(rpool, K_OBJ_RTIO_POOL)); + K_OOPS(K_SYSCALL_OBJ(r, K_OBJ_RTIO)); + + z_impl_rtio_pool_release(rpool, r); +} +#include diff --git a/subsys/secure_storage/Kconfig b/subsys/secure_storage/Kconfig index 3fe8eb0f76a79..b0ac8c08a14c9 100644 --- a/subsys/secure_storage/Kconfig +++ b/subsys/secure_storage/Kconfig @@ -25,6 +25,17 @@ module = SECURE_STORAGE module-str = secure_storage source "subsys/logging/Kconfig.template.log_config" +config SECURE_STORAGE_64_BIT_UID + bool "Make psa_storage_uid_t 64-bit" + help + Zephyr, by default, uses a 30-bit psa_storage_uid_t, which allows using only 32 bits to + identify entries. + UID ranges are defined for the different users of the API which guarantees that all the + UIDs fit within 30 bits. See for example the zephyr/psa/key_ids.h header file. + Enable this for backward compatibility if you are updating an existing installation with + stored entries that was using Zephyr prior to 4.3 or if for some reason you need the full + 64-bit UID range. + choice SECURE_STORAGE_ITS_IMPLEMENTATION prompt "Internal Trusted Storage (ITS) API implementation" diff --git a/subsys/secure_storage/Kconfig.its_store b/subsys/secure_storage/Kconfig.its_store index ccd15b968a7ca..c924def563fa1 100644 --- a/subsys/secure_storage/Kconfig.its_store +++ b/subsys/secure_storage/Kconfig.its_store @@ -17,7 +17,7 @@ config SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS depends on ZMS help This implementation of the ITS store module makes direct use of ZMS for storage. - It needs a `secure_storage_its_partition` devicetree chosen property that points + It needs a secure_storage_its_partition devicetree chosen property that points to a fixed storage partition that will be dedicated to the ITS. It has lower overhead compared to the settings-based implementation, both in terms of runtime execution and storage space, and also ROM footprint if the settings subsystem is disabled. @@ -78,7 +78,8 @@ config SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX config SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_MAX_LEN int "Maximum setting name length" range 2 64 - default 22 if !SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM - default 0 + default 0 if SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM + default 22 if SECURE_STORAGE_64_BIT_UID + default 14 endif # SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS diff --git a/subsys/secure_storage/include/internal/zephyr/secure_storage/its.h b/subsys/secure_storage/include/internal/zephyr/secure_storage/its.h index 009bb5e061af7..c19dd7be7b63e 100644 --- a/subsys/secure_storage/include/internal/zephyr/secure_storage/its.h +++ b/subsys/secure_storage/include/internal/zephyr/secure_storage/its.h @@ -14,18 +14,21 @@ #include "its/common.h" /** @brief See `psa_its_set()`, to which this function is analogous. */ -psa_status_t secure_storage_its_set(secure_storage_its_uid_t uid, size_t data_length, - const void *p_data, psa_storage_create_flags_t create_flags); +psa_status_t secure_storage_its_set(secure_storage_its_caller_id_t caller_id, psa_storage_uid_t uid, + size_t data_length, const void *p_data, + psa_storage_create_flags_t create_flags); /** @brief See `psa_its_get()`, to which this function is analogous. */ -psa_status_t secure_storage_its_get(secure_storage_its_uid_t uid, size_t data_offset, - size_t data_size, void *p_data, size_t *p_data_length); +psa_status_t secure_storage_its_get(secure_storage_its_caller_id_t caller_id, psa_storage_uid_t uid, + size_t data_offset, size_t data_size, + void *p_data, size_t *p_data_length); /** @brief See `psa_its_get_info()`, to which this function is analogous. */ -psa_status_t secure_storage_its_get_info(secure_storage_its_uid_t uid, - struct psa_storage_info_t *p_info); +psa_status_t secure_storage_its_get_info(secure_storage_its_caller_id_t caller_id, + psa_storage_uid_t uid, struct psa_storage_info_t *p_info); /** @brief See `psa_its_remove()`, to which this function is analogous. */ -psa_status_t secure_storage_its_remove(secure_storage_its_uid_t uid); +psa_status_t secure_storage_its_remove(secure_storage_its_caller_id_t caller_id, + psa_storage_uid_t uid); #endif diff --git a/subsys/secure_storage/include/internal/zephyr/secure_storage/its/common.h b/subsys/secure_storage/include/internal/zephyr/secure_storage/its/common.h index cd953086950a0..6ffc1bc78f57c 100644 --- a/subsys/secure_storage/include/internal/zephyr/secure_storage/its/common.h +++ b/subsys/secure_storage/include/internal/zephyr/secure_storage/its/common.h @@ -12,8 +12,7 @@ #include /** @brief The ID of the caller from which the ITS API call originates. - * This is used to prevent ID collisions between different callers that are not aware - * of each other and so might use the same numerical IDs, e.g. PSA Crypto and PSA ITS. + * This is used to namespace the different callers and possibly treat them differently. */ typedef enum { SECURE_STORAGE_ITS_CALLER_PSA_ITS, @@ -22,12 +21,33 @@ typedef enum { SECURE_STORAGE_ITS_CALLER_COUNT } secure_storage_its_caller_id_t; +#ifdef CONFIG_SECURE_STORAGE_64_BIT_UID + /** The UID (caller + entry IDs) of an ITS entry. */ typedef struct { psa_storage_uid_t uid; secure_storage_its_caller_id_t caller_id; } __packed secure_storage_its_uid_t; +#else + +#define SECURE_STORAGE_ITS_UID_BIT_SIZE 30 +#define SECURE_STORAGE_ITS_CALLER_ID_BIT_SIZE 2 + +/** @brief The UID (caller + entry IDs) of an ITS entry. + * This is a packed, 32-bit version of `psa_storage_uid_t` which allows storing + * smaller IDs compared to the 64-bit ones that PSA Secure Storage specifies. + * Zephyr defines ranges of IDs to be used by different users of the API (subsystems, application) + * which guarantees 1. no collisions and 2. that the IDs used fit within `uid`. + * @see @ref zephyr/psa/key_ids.h and the other header files under `zephyr/psa`. + */ +typedef struct { + psa_storage_uid_t uid : SECURE_STORAGE_ITS_UID_BIT_SIZE; + secure_storage_its_caller_id_t caller_id : SECURE_STORAGE_ITS_CALLER_ID_BIT_SIZE; +} secure_storage_its_uid_t; + +#endif /* CONFIG_SECURE_STORAGE_64_BIT_UID */ + #ifdef CONFIG_SECURE_STORAGE_ITS_TRANSFORM_MODULE /** The maximum size, in bytes, of an entry's data after it has been transformed for storage. */ diff --git a/subsys/secure_storage/include/psa/internal_trusted_storage.h b/subsys/secure_storage/include/psa/internal_trusted_storage.h index a8c3b77c601a0..06a09e34988b9 100644 --- a/subsys/secure_storage/include/psa/internal_trusted_storage.h +++ b/subsys/secure_storage/include/psa/internal_trusted_storage.h @@ -16,7 +16,6 @@ #else #define ITS_CALLER_ID SECURE_STORAGE_ITS_CALLER_PSA_ITS #endif -#define ITS_UID (secure_storage_its_uid_t){.uid = uid, .caller_id = ITS_CALLER_ID} /** @endcond */ #include @@ -50,7 +49,7 @@ static ALWAYS_INLINE psa_status_t psa_its_set(psa_storage_uid_t uid, size_t data_length, const void *p_data, psa_storage_create_flags_t create_flags) { - return secure_storage_its_set(ITS_UID, data_length, p_data, create_flags); + return secure_storage_its_set(ITS_CALLER_ID, uid, data_length, p_data, create_flags); } /** @@ -76,7 +75,8 @@ static ALWAYS_INLINE psa_status_t psa_its_get(psa_storage_uid_t uid, size_t data_offset, size_t data_size, void *p_data, size_t *p_data_length) { - return secure_storage_its_get(ITS_UID, data_offset, data_size, p_data, p_data_length); + return secure_storage_its_get(ITS_CALLER_ID, uid, data_offset, + data_size, p_data, p_data_length); } /** @@ -96,7 +96,7 @@ static ALWAYS_INLINE /** @endcond */ psa_status_t psa_its_get_info(psa_storage_uid_t uid, struct psa_storage_info_t *p_info) { - return secure_storage_its_get_info(ITS_UID, p_info); + return secure_storage_its_get_info(ITS_CALLER_ID, uid, p_info); } /** @@ -117,7 +117,7 @@ static ALWAYS_INLINE /** @endcond */ psa_status_t psa_its_remove(psa_storage_uid_t uid) { - return secure_storage_its_remove(ITS_UID); + return secure_storage_its_remove(ITS_CALLER_ID, uid); } #undef ITS_UID diff --git a/subsys/secure_storage/include/psa/protected_storage.h b/subsys/secure_storage/include/psa/protected_storage.h index 7c20d3097a2ad..40d731b042544 100644 --- a/subsys/secure_storage/include/psa/protected_storage.h +++ b/subsys/secure_storage/include/psa/protected_storage.h @@ -12,8 +12,7 @@ /** @cond INTERNAL_HIDDEN */ #ifdef CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_ITS #include "../internal/zephyr/secure_storage/its.h" -#define ITS_UID (secure_storage_its_uid_t){.uid = uid, \ - .caller_id = SECURE_STORAGE_ITS_CALLER_PSA_PS} +#define ITS_CALLER_ID SECURE_STORAGE_ITS_CALLER_PSA_PS #else #include "../internal/zephyr/secure_storage/ps.h" #endif @@ -50,7 +49,7 @@ psa_status_t psa_ps_set(psa_storage_uid_t uid, size_t data_length, const void *p_data, psa_storage_create_flags_t create_flags) { #ifdef CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_ITS - return secure_storage_its_set(ITS_UID, data_length, p_data, create_flags); + return secure_storage_its_set(ITS_CALLER_ID, uid, data_length, p_data, create_flags); #else return secure_storage_ps_set(uid, data_length, p_data, create_flags); #endif @@ -83,7 +82,8 @@ psa_status_t psa_ps_get(psa_storage_uid_t uid, size_t data_offset, size_t data_size, void *p_data, size_t *p_data_length) { #ifdef CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_ITS - return secure_storage_its_get(ITS_UID, data_offset, data_size, p_data, p_data_length); + return secure_storage_its_get(ITS_CALLER_ID, uid, data_offset, + data_size, p_data, p_data_length); #else return secure_storage_ps_get(uid, data_offset, data_size, p_data, p_data_length); #endif @@ -110,7 +110,7 @@ static ALWAYS_INLINE psa_status_t psa_ps_get_info(psa_storage_uid_t uid, struct psa_storage_info_t *p_info) { #ifdef CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_ITS - return secure_storage_its_get_info(ITS_UID, p_info); + return secure_storage_its_get_info(ITS_CALLER_ID, uid, p_info); #else return secure_storage_ps_get_info(uid, p_info); #endif @@ -138,7 +138,7 @@ static ALWAYS_INLINE psa_status_t psa_ps_remove(psa_storage_uid_t uid) { #ifdef CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_ITS - return secure_storage_its_remove(ITS_UID); + return secure_storage_its_remove(ITS_CALLER_ID, uid); #else return secure_storage_ps_remove(uid); #endif diff --git a/subsys/secure_storage/include/psa/storage_common.h b/subsys/secure_storage/include/psa/storage_common.h index d5bed2a692e70..2bd0f7cce7327 100644 --- a/subsys/secure_storage/include/psa/storage_common.h +++ b/subsys/secure_storage/include/psa/storage_common.h @@ -20,7 +20,11 @@ #include /** UID type for identifying entries. */ +#ifdef CONFIG_SECURE_STORAGE_64_BIT_UID typedef uint64_t psa_storage_uid_t; +#else +typedef uint32_t psa_storage_uid_t; +#endif /** Flags used when creating an entry. */ typedef uint32_t psa_storage_create_flags_t; diff --git a/subsys/secure_storage/src/its/implementation.c b/subsys/secure_storage/src/its/implementation.c index 2ad937d45d27b..6f33195a0628d 100644 --- a/subsys/secure_storage/src/its/implementation.c +++ b/subsys/secure_storage/src/its/implementation.c @@ -11,6 +11,33 @@ LOG_MODULE_DECLARE(secure_storage, CONFIG_SECURE_STORAGE_LOG_LEVEL); +#ifndef CONFIG_SECURE_STORAGE_64_BIT_UID +BUILD_ASSERT(sizeof(secure_storage_its_uid_t) == 4); /* ITS UIDs are 32-bit */ +BUILD_ASSERT(1 << SECURE_STORAGE_ITS_CALLER_ID_BIT_SIZE >= SECURE_STORAGE_ITS_CALLER_COUNT); +BUILD_ASSERT(SECURE_STORAGE_ITS_CALLER_ID_BIT_SIZE + SECURE_STORAGE_ITS_UID_BIT_SIZE == 32); +#endif + +static psa_status_t make_its_uid(secure_storage_its_caller_id_t caller_id, psa_storage_uid_t uid, + secure_storage_its_uid_t *its_uid) +{ + if (uid == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + +#ifndef CONFIG_SECURE_STORAGE_64_BIT_UID + /* Check that the UID is not bigger than the maximum defined size. */ + if (uid & GENMASK64(63, SECURE_STORAGE_ITS_UID_BIT_SIZE)) { + LOG_DBG("UID %u/%#llx cannot be used as it has bits set past " + "the first " STRINGIFY(SECURE_STORAGE_ITS_UID_BIT_SIZE) " ones.", + caller_id, (unsigned long long)uid); + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif /* !CONFIG_SECURE_STORAGE_64_BIT_UID */ + + *its_uid = (secure_storage_its_uid_t){.caller_id = caller_id, .uid = uid}; + return PSA_SUCCESS; +} + static void log_failed_operation(const char *operation, const char *preposition, psa_status_t ret) { LOG_ERR("Failed to %s data %s storage. (%d)", operation, preposition, ret); @@ -88,8 +115,15 @@ static bool keep_stored_entry(secure_storage_its_uid_t uid, size_t data_length, if (existing_data_len == data_length && existing_create_flags == create_flags && !memcmp(existing_data, p_data, data_length)) { - LOG_DBG("Not writing entry %u/%llu to storage because its stored data" - " (of length %zu) is identical.", uid.caller_id, uid.uid, data_length); +#ifdef CONFIG_SECURE_STORAGE_64_BIT_UID + LOG_DBG("Not writing entry %u/%#llx to storage because its stored data" + " (of length %zu) is identical.", uid.caller_id, + (unsigned long long)uid.uid, data_length); +#else + LOG_DBG("Not writing entry %u/%#lx to storage because its stored data" + " (of length %zu) is identical.", uid.caller_id, + (unsigned long)uid.uid, data_length); +#endif *ret = PSA_SUCCESS; return true; } @@ -117,12 +151,17 @@ static psa_status_t store_entry(secure_storage_its_uid_t uid, size_t data_length return ret; } -psa_status_t secure_storage_its_set(secure_storage_its_uid_t uid, size_t data_length, - const void *p_data, psa_storage_create_flags_t create_flags) +psa_status_t secure_storage_its_set(secure_storage_its_caller_id_t caller_id, psa_storage_uid_t uid, + size_t data_length, const void *p_data, + psa_storage_create_flags_t create_flags) { psa_status_t ret; + secure_storage_its_uid_t its_uid; - if (uid.uid == 0 || (p_data == NULL && data_length != 0)) { + if (make_its_uid(caller_id, uid, &its_uid) != PSA_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (p_data == NULL && data_length != 0) { return PSA_ERROR_INVALID_ARGUMENT; } if (create_flags & ~SECURE_STORAGE_ALL_CREATE_FLAGS) { @@ -134,43 +173,49 @@ psa_status_t secure_storage_its_set(secure_storage_its_uid_t uid, size_t data_le return PSA_ERROR_INSUFFICIENT_STORAGE; } - if (keep_stored_entry(uid, data_length, p_data, create_flags, &ret)) { + if (keep_stored_entry(its_uid, data_length, p_data, create_flags, &ret)) { return ret; } - ret = store_entry(uid, data_length, p_data, create_flags); + ret = store_entry(its_uid, data_length, p_data, create_flags); return ret; } - -psa_status_t secure_storage_its_get(secure_storage_its_uid_t uid, size_t data_offset, - size_t data_size, void *p_data, size_t *p_data_length) +psa_status_t secure_storage_its_get(secure_storage_its_caller_id_t caller_id, psa_storage_uid_t uid, + size_t data_offset, size_t data_size, + void *p_data, size_t *p_data_length) { - if (uid.uid == 0 || (p_data == NULL && data_size != 0) || p_data_length == NULL) { + psa_status_t ret; + secure_storage_its_uid_t its_uid; + uint8_t stored_data[SECURE_STORAGE_ITS_TRANSFORM_MAX_STORED_DATA_SIZE]; + size_t stored_data_len; + psa_storage_create_flags_t create_flags; + + if (make_its_uid(caller_id, uid, &its_uid) != PSA_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if ((p_data == NULL && data_size != 0) || p_data_length == NULL) { return PSA_ERROR_INVALID_ARGUMENT; } if (data_size == 0) { *p_data_length = 0; return PSA_SUCCESS; } - psa_status_t ret; - uint8_t stored_data[SECURE_STORAGE_ITS_TRANSFORM_MAX_STORED_DATA_SIZE]; - size_t stored_data_len; - psa_storage_create_flags_t create_flags; - ret = get_stored_data(uid, stored_data, &stored_data_len); + + ret = get_stored_data(its_uid, stored_data, &stored_data_len); if (ret != PSA_SUCCESS) { return ret; } if (data_offset == 0 && data_size >= SECURE_STORAGE_ITS_TRANSFORM_DATA_SIZE(stored_data_len)) { /* All the data fits directly in the provided buffer. */ - return transform_stored_data(uid, stored_data_len, stored_data, data_size, p_data, - p_data_length, &create_flags); + return transform_stored_data(its_uid, stored_data_len, stored_data, data_size, + p_data, p_data_length, &create_flags); } uint8_t data[CONFIG_SECURE_STORAGE_ITS_MAX_DATA_SIZE]; size_t data_len; - ret = transform_stored_data(uid, stored_data_len, stored_data, sizeof(data), data, + ret = transform_stored_data(its_uid, stored_data_len, stored_data, sizeof(data), data, &data_len, &create_flags); if (ret == PSA_SUCCESS) { if (data_offset > data_len) { @@ -184,41 +229,47 @@ psa_status_t secure_storage_its_get(secure_storage_its_uid_t uid, size_t data_of return ret; } -psa_status_t secure_storage_its_get_info(secure_storage_its_uid_t uid, - struct psa_storage_info_t *p_info) +psa_status_t secure_storage_its_get_info(secure_storage_its_caller_id_t caller_id, + psa_storage_uid_t uid, struct psa_storage_info_t *p_info) { psa_status_t ret; + secure_storage_its_uid_t its_uid; uint8_t data[CONFIG_SECURE_STORAGE_ITS_MAX_DATA_SIZE]; - if (uid.uid == 0 || p_info == NULL) { + if (make_its_uid(caller_id, uid, &its_uid) != PSA_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (p_info == NULL) { return PSA_ERROR_INVALID_ARGUMENT; } - ret = get_entry(uid, sizeof(data), data, &p_info->size, &p_info->flags); + ret = get_entry(its_uid, sizeof(data), data, &p_info->size, &p_info->flags); if (ret == PSA_SUCCESS) { p_info->capacity = p_info->size; } return ret; } -psa_status_t secure_storage_its_remove(secure_storage_its_uid_t uid) +psa_status_t secure_storage_its_remove(secure_storage_its_caller_id_t caller_id, + psa_storage_uid_t uid) { psa_status_t ret; + secure_storage_its_uid_t its_uid; psa_storage_create_flags_t create_flags; uint8_t data[CONFIG_SECURE_STORAGE_ITS_MAX_DATA_SIZE]; size_t data_len; - if (uid.uid == 0) { + if (make_its_uid(caller_id, uid, &its_uid) != PSA_SUCCESS) { return PSA_ERROR_INVALID_ARGUMENT; } - ret = get_entry(uid, sizeof(data), data, &data_len, &create_flags); + ret = get_entry(its_uid, sizeof(data), data, &data_len, &create_flags); if (ret == PSA_SUCCESS && (create_flags & PSA_STORAGE_FLAG_WRITE_ONCE)) { return PSA_ERROR_NOT_PERMITTED; } /* Allow overwriting corrupted entries as well to not be stuck with them forever. */ if (ret == PSA_SUCCESS || ret == PSA_ERROR_STORAGE_FAILURE) { - ret = secure_storage_its_store_remove(uid); + ret = secure_storage_its_store_remove(its_uid); if (ret != PSA_SUCCESS) { log_failed_operation("remove", "from", ret); return PSA_ERROR_STORAGE_FAILURE; diff --git a/subsys/secure_storage/src/its/store/settings.c b/subsys/secure_storage/src/its/store/settings.c index 962fa516770a9..37973ffb02447 100644 --- a/subsys/secure_storage/src/its/store/settings.c +++ b/subsys/secure_storage/src/its/store/settings.c @@ -38,9 +38,15 @@ void secure_storage_its_store_settings_get_name( { int ret; +#ifdef CONFIG_SECURE_STORAGE_64_BIT_UID ret = snprintf(name, SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE, CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX "%x/%llx", uid.caller_id, (unsigned long long)uid.uid); +#else + ret = snprintf(name, SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE, + CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX "%x/%lx", + uid.caller_id, (unsigned long)uid.uid); +#endif __ASSERT_NO_MSG(ret > 0 && ret < SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE); } diff --git a/subsys/secure_storage/src/its/store/zms.c b/subsys/secure_storage/src/its/store/zms.c index ede296952ab5d..4778e0365e917 100644 --- a/subsys/secure_storage/src/its/store/zms.c +++ b/subsys/secure_storage/src/its/store/zms.c @@ -33,26 +33,26 @@ static int init_zms(void) } SYS_INIT(init_zms, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY); +#ifdef CONFIG_SECURE_STORAGE_64_BIT_UID + /* Bit position of the ITS caller ID in the ZMS entry ID. */ #define ITS_CALLER_ID_POS 30 /* Make sure that every ITS caller ID fits in ZMS entry IDs at the defined position. */ BUILD_ASSERT(1 << (32 - ITS_CALLER_ID_POS) >= SECURE_STORAGE_ITS_CALLER_COUNT); -static bool has_forbidden_bits_set(secure_storage_its_uid_t uid) +static uint32_t zms_id_from(secure_storage_its_uid_t uid) { - if (uid.uid & GENMASK64(63, ITS_CALLER_ID_POS)) { - LOG_DBG("UID %u/0x%llx cannot be used as it has bits set past " - "the first " STRINGIFY(ITS_CALLER_ID_POS) " ones.", - uid.caller_id, (unsigned long long)uid.uid); - return true; - } - return false; + __ASSERT_NO_MSG(!(uid.uid & GENMASK64(63, ITS_CALLER_ID_POS))); + return (uint32_t)uid.uid | (uid.caller_id << ITS_CALLER_ID_POS); } +#else static uint32_t zms_id_from(secure_storage_its_uid_t uid) { - return (uint32_t)uid.uid | (uid.caller_id << ITS_CALLER_ID_POS); + BUILD_ASSERT(sizeof(uid) == sizeof(uint32_t)); + return *(uint32_t *)&uid; } +#endif /* CONFIG_SECURE_STORAGE_64_BIT_UID */ psa_status_t secure_storage_its_store_set(secure_storage_its_uid_t uid, size_t data_length, const void *data) @@ -61,10 +61,6 @@ psa_status_t secure_storage_its_store_set(secure_storage_its_uid_t uid, ssize_t zms_ret; const uint32_t zms_id = zms_id_from(uid); - if (has_forbidden_bits_set(uid)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - zms_ret = zms_write(&s_zms, zms_id, data, data_length); if (zms_ret == data_length) { psa_ret = PSA_SUCCESS; @@ -73,7 +69,7 @@ psa_status_t secure_storage_its_store_set(secure_storage_its_uid_t uid, } else { psa_ret = PSA_ERROR_STORAGE_FAILURE; } - LOG_DBG("%s 0x%x with %zu bytes. (%zd)", (psa_ret == PSA_SUCCESS) ? + LOG_DBG("%s %#x with %zu bytes. (%zd)", (psa_ret == PSA_SUCCESS) ? "Wrote" : "Failed to write", zms_id, data_length, zms_ret); return psa_ret; } @@ -85,10 +81,6 @@ psa_status_t secure_storage_its_store_get(secure_storage_its_uid_t uid, size_t d ssize_t zms_ret; const uint32_t zms_id = zms_id_from(uid); - if (has_forbidden_bits_set(uid)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - zms_ret = zms_read(&s_zms, zms_id, data, data_size); if (zms_ret > 0) { *data_length = zms_ret; @@ -98,7 +90,7 @@ psa_status_t secure_storage_its_store_get(secure_storage_its_uid_t uid, size_t d } else { psa_ret = PSA_ERROR_STORAGE_FAILURE; } - LOG_DBG("%s 0x%x for up to %zu bytes. (%zd)", (psa_ret != PSA_ERROR_STORAGE_FAILURE) ? + LOG_DBG("%s %#x for up to %zu bytes. (%zd)", (psa_ret != PSA_ERROR_STORAGE_FAILURE) ? "Read" : "Failed to read", zms_id, data_size, zms_ret); return psa_ret; } @@ -108,12 +100,8 @@ psa_status_t secure_storage_its_store_remove(secure_storage_its_uid_t uid) int ret; const uint32_t zms_id = zms_id_from(uid); - if (has_forbidden_bits_set(uid)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - ret = zms_delete(&s_zms, zms_id); - LOG_DBG("%s 0x%x. (%d)", ret ? "Failed to delete" : "Deleted", zms_id, ret); + LOG_DBG("%s %#x. (%d)", ret ? "Failed to delete" : "Deleted", zms_id, ret); return ret ? PSA_ERROR_STORAGE_FAILURE : PSA_SUCCESS; } diff --git a/subsys/settings/Kconfig b/subsys/settings/Kconfig index 2e75286550e98..617d311335ff4 100644 --- a/subsys/settings/Kconfig +++ b/subsys/settings/Kconfig @@ -44,7 +44,6 @@ choice SETTINGS_BACKEND default SETTINGS_NVS if NVS default SETTINGS_FCB if FCB default SETTINGS_FILE if FILE_SYSTEM - default SETTINGS_TFM_ITS if TFM_PARTITION_INTERNAL_TRUSTED_STORAGE default SETTINGS_RETENTION if SETTINGS_SUPPORTED_RETENTION default SETTINGS_NONE help @@ -128,6 +127,7 @@ config SETTINGS_CUSTOM config SETTINGS_TFM_ITS bool "Internal Trusted Storage (ITS) settings backend" depends on TFM_PARTITION_INTERNAL_TRUSTED_STORAGE + select EXPERIMENTAL help Enables Internal Trusted Storage (ITS) Settings backend. Intended for use with boards using TF-M which cannot make use of persistent storage otherwise. diff --git a/subsys/shell/backends/Kconfig.backends b/subsys/shell/backends/Kconfig.backends index c68ec201197c2..13b6997947268 100644 --- a/subsys/shell/backends/Kconfig.backends +++ b/subsys/shell/backends/Kconfig.backends @@ -288,8 +288,7 @@ config SHELL_BACKEND_MQTT select DNS_RESOLVER select HWINFO select MQTT_LIB - select NET_MGMT - select NET_MGMT_EVENT + select NET_CONNECTION_MANAGER help Enable MQTT backend. @@ -334,7 +333,7 @@ config SHELL_MQTT_CONNECT_TIMEOUT_MS int "MQTT connect timeout [ms]" default 2000 help - Time to await MQTT connect acknowlegde in milliseconds. + Time to await MQTT connect acknowledge in milliseconds. config SHELL_MQTT_WORK_DELAY_MS int "MQTT work delay [ms]" @@ -348,6 +347,18 @@ config SHELL_MQTT_LISTEN_TIMEOUT_MS help Time to listen for incoming packets in milliseconds. +config SHELL_MQTT_TOPIC_RX_ID + string "MQTT topic receive identifier" + default "/sh/rx" + help + String used as receive identifier in the MQTT topic. + +config SHELL_MQTT_TOPIC_TX_ID + string "MQTT topic transmit identifier" + default "/sh/tx" + help + String used as transmit identifier in the MQTT topic. + module = SHELL_BACKEND_MQTT default-timeout = 100 source "subsys/shell/Kconfig.template.shell_log_queue_timeout" diff --git a/subsys/shell/backends/shell_mqtt.c b/subsys/shell/backends/shell_mqtt.c index dcc7f83812e2f..5b9b452f720b1 100644 --- a/subsys/shell/backends/shell_mqtt.c +++ b/subsys/shell/backends/shell_mqtt.c @@ -26,18 +26,6 @@ LOG_MODULE_REGISTER(shell_mqtt, CONFIG_SHELL_MQTT_LOG_LEVEL); #define PROCESS_INTERVAL K_MSEC(CONFIG_SHELL_MQTT_WORK_DELAY_MS) #define SHELL_MQTT_WORKQ_STACK_SIZE 2048 -#ifdef CONFIG_SHELL_MQTT_SERVER_USERNAME -#define MQTT_USERNAME CONFIG_SHELL_MQTT_SERVER_USERNAME -#else -#define MQTT_USERNAME NULL -#endif /* CONFIG_SHELL_MQTT_SERVER_USERNAME */ - -#ifdef CONFIG_SHELL_MQTT_SERVER_PASSWORD -#define MQTT_PASSWORD CONFIG_SHELL_MQTT_SERVER_PASSWORD -#else -#define MQTT_PASSWORD NULL -#endif /*SHELL_MQTT_SERVER_PASSWORD */ - struct shell_mqtt *sh_mqtt; K_KERNEL_STACK_DEFINE(sh_mqtt_workq_stack, SHELL_MQTT_WORKQ_STACK_SIZE); @@ -187,10 +175,10 @@ static void client_init(struct shell_mqtt *sh) static struct mqtt_utf8 password; static struct mqtt_utf8 username; - password.utf8 = (uint8_t *)MQTT_PASSWORD; - password.size = strlen(MQTT_PASSWORD); - username.utf8 = (uint8_t *)MQTT_USERNAME; - username.size = strlen(MQTT_USERNAME); + password.utf8 = (uint8_t *)CONFIG_SHELL_MQTT_SERVER_PASSWORD; + password.size = strlen(CONFIG_SHELL_MQTT_SERVER_PASSWORD); + username.utf8 = (uint8_t *)CONFIG_SHELL_MQTT_SERVER_USERNAME; + username.size = strlen(CONFIG_SHELL_MQTT_SERVER_USERNAME); mqtt_client_init(&sh->mqtt_cli); @@ -657,8 +645,10 @@ static int init(const struct shell_transport *transport, const void *config, LOG_DBG("Client ID is %s", sh->device_id); - (void)snprintf(sh->pub_topic, SH_MQTT_TOPIC_MAX_SIZE, "%s_tx", sh->device_id); - (void)snprintf(sh->sub_topic, SH_MQTT_TOPIC_MAX_SIZE, "%s_rx", sh->device_id); + (void)snprintf(sh->pub_topic, SH_MQTT_TOPIC_TX_MAX_SIZE, "%s" CONFIG_SHELL_MQTT_TOPIC_TX_ID, + sh->device_id); + (void)snprintf(sh->sub_topic, SH_MQTT_TOPIC_RX_MAX_SIZE, "%s" CONFIG_SHELL_MQTT_TOPIC_RX_ID, + sh->device_id); ring_buf_init(&sh->rx_rb, RX_RB_SIZE, sh->rx_rb_buf); diff --git a/subsys/shell/modules/devmem_service.c b/subsys/shell/modules/devmem_service.c index 3663e0a2cfa16..559a946d6d677 100644 --- a/subsys/shell/modules/devmem_service.c +++ b/subsys/shell/modules/devmem_service.c @@ -175,14 +175,25 @@ static void bypass_cb(const struct shell *sh, uint8_t *recv, size_t len) static uint8_t tail; uint8_t byte; - if (tail == CHAR_CAN && recv[0] == CHAR_DC1) { - escape = true; - } else { - for (int i = 0; i < (len - 1); i++) { - if (recv[i] == CHAR_CAN && recv[i + 1] == CHAR_DC1) { - escape = true; - break; - } + for (size_t i = 0; i < len; i++) { + if (tail == CHAR_CAN && recv[i] == CHAR_DC1) { + escape = true; + tail = 0; + break; + } + tail = recv[i]; + + if (is_ascii(recv[i])) { + chunk[chunk_element] = recv[i]; + chunk_element++; + } + + if (chunk_element == 2) { + byte = (uint8_t)strtoul(chunk, NULL, 16); + *bytes = byte; + bytes++; + sum++; + chunk_element = 0; } } @@ -206,21 +217,6 @@ static void bypass_cb(const struct shell *sh, uint8_t *recv, size_t len) } return; } - - tail = recv[len - 1]; - - if (is_ascii(*recv)) { - chunk[chunk_element] = *recv; - chunk_element++; - } - - if (chunk_element == 2) { - byte = (uint8_t)strtoul(chunk, NULL, 16); - *bytes = byte; - bytes++; - sum++; - chunk_element = 0; - } } static int cmd_load(const struct shell *sh, size_t argc, char **argv) diff --git a/subsys/storage/stream/stream_flash.c b/subsys/storage/stream/stream_flash.c index 8155ef3dfe354..c611dde9dc411 100644 --- a/subsys/storage/stream/stream_flash.c +++ b/subsys/storage/stream/stream_flash.c @@ -307,6 +307,11 @@ size_t stream_flash_bytes_written(const struct stream_flash_ctx *ctx) return ctx->bytes_written; } +size_t stream_flash_bytes_buffered(const struct stream_flash_ctx *ctx) +{ + return ctx->buf_bytes; +} + #ifdef CONFIG_STREAM_FLASH_INSPECT struct _inspect_flash { size_t buf_len; diff --git a/subsys/testsuite/ztest/src/ztest.c b/subsys/testsuite/ztest/src/ztest.c index a5d6fc264ef32..080e172652845 100644 --- a/subsys/testsuite/ztest/src/ztest.c +++ b/subsys/testsuite/ztest/src/ztest.c @@ -538,7 +538,7 @@ static int run_test(struct ztest_suite_node *suite, struct ztest_unit_test *test ret = get_final_test_result(test, ret); Z_TC_END_RESULT(ret, test->name); if (ret == TC_SKIP && current_test_failed_assumption) { - test_status = 1; + test_status = ZTEST_STATUS_HAS_FAILURE; } return ret; @@ -741,7 +741,7 @@ static int run_test(struct ztest_suite_node *suite, struct ztest_unit_test *test ret = get_final_test_result(test, ret); Z_TC_END_RESULT(ret, test->name); if (ret == TC_SKIP && current_test_failed_assumption) { - test_status = 1; + test_status = ZTEST_STATUS_HAS_FAILURE; } return ret; @@ -1168,7 +1168,7 @@ void ztest_verify_all_test_suites_ran(void) if (test->stats->fail_count + test->stats->pass_count + test->stats->skip_count != test->stats->run_count) { PRINT_DATA("Bad stats for %s.%s\n", test->test_suite_name, test->name); - test_status = 1; + test_status = ZTEST_STATUS_HAS_FAILURE; } } } diff --git a/subsys/tracing/ctf/ctf_top.h b/subsys/tracing/ctf/ctf_top.h index 43d11774ef9ba..d1461086a6fb1 100644 --- a/subsys/tracing/ctf/ctf_top.h +++ b/subsys/tracing/ctf/ctf_top.h @@ -52,9 +52,11 @@ #ifdef CONFIG_TRACING_CTF_TIMESTAMP #define CTF_EVENT(...) \ { \ + int key = irq_lock(); \ const uint32_t tstamp = k_cyc_to_ns_floor64(k_cycle_get_32()); \ \ CTF_GATHER_FIELDS(tstamp, __VA_ARGS__) \ + irq_unlock(key); \ } #else #define CTF_EVENT(...) \ diff --git a/subsys/tracing/sysview/sysview.c b/subsys/tracing/sysview/sysview.c index 42059fb0f5d73..33905e2d4e43f 100644 --- a/subsys/tracing/sysview/sysview.c +++ b/subsys/tracing/sysview/sysview.c @@ -4,10 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include -#include #include diff --git a/subsys/tracing/sysview/sysview_config.c b/subsys/tracing/sysview/sysview_config.c index ed13c87661fcd..ec471afe7cd46 100644 --- a/subsys/tracing/sysview/sysview_config.c +++ b/subsys/tracing/sysview/sysview_config.c @@ -5,8 +5,8 @@ */ #include +#include #include -#include #ifdef CONFIG_SYMTAB #include #include @@ -58,6 +58,10 @@ static void cbSendSystemDesc(void) CONFIG_SOC_FAMILY " " CONFIG_ARCH); SEGGER_SYSVIEW_SendSysDesc("O=Zephyr"); +#ifdef CONFIG_BOARD_QUALIFIERS + SEGGER_SYSVIEW_SendSysDesc("C=" CONFIG_BOARD_QUALIFIERS); +#endif + #ifdef CONFIG_SYMTAB char isr_desc[SEGGER_SYSVIEW_MAX_STRING_LEN]; diff --git a/subsys/usb/device/class/cdc_acm.c b/subsys/usb/device/class/cdc_acm.c index 469215e6aa51f..7b44163c6ab82 100644 --- a/subsys/usb/device/class/cdc_acm.c +++ b/subsys/usb/device/class/cdc_acm.c @@ -823,7 +823,7 @@ static int cdc_acm_line_ctrl_set(const struct device *dev, if (val) { dev_data->serial_state |= SERIAL_STATE_RX_CARRIER; } - cdc_acm_send_notification(dev, SERIAL_STATE_RX_CARRIER); + cdc_acm_send_notification(dev, dev_data->serial_state); return 0; case USB_CDC_LINE_CTRL_DSR: dev_data->serial_state &= ~SERIAL_STATE_TX_CARRIER; diff --git a/subsys/usb/device_next/class/usbd_cdc_ecm.c b/subsys/usb/device_next/class/usbd_cdc_ecm.c index ce8b27c5dc71a..6fe1dbb7b6451 100644 --- a/subsys/usb/device_next/class/usbd_cdc_ecm.c +++ b/subsys/usb/device_next/class/usbd_cdc_ecm.c @@ -455,10 +455,12 @@ static int usbd_cdc_ecm_init(struct usbd_class_data *const c_data) desc->if0_union.bSubordinateInterface0 = if_num + 1; LOG_DBG("CDC ECM class initialized"); - if (usbd_add_descriptor(uds_ctx, data->mac_desc_data)) { - LOG_ERR("Failed to add iMACAddress string descriptor"); - } else { - desc->if0_ecm.iMACAddress = usbd_str_desc_get_idx(data->mac_desc_data); + if (desc->if0_ecm.iMACAddress == 0) { + if (usbd_add_descriptor(uds_ctx, data->mac_desc_data)) { + LOG_ERR("Failed to add iMACAddress string descriptor"); + } else { + desc->if0_ecm.iMACAddress = usbd_str_desc_get_idx(data->mac_desc_data); + } } return 0; diff --git a/subsys/usb/device_next/class/usbd_cdc_ncm.c b/subsys/usb/device_next/class/usbd_cdc_ncm.c index 31970a95dc26b..204d685a48fac 100644 --- a/subsys/usb/device_next/class/usbd_cdc_ncm.c +++ b/subsys/usb/device_next/class/usbd_cdc_ncm.c @@ -989,10 +989,12 @@ static int usbd_cdc_ncm_init(struct usbd_class_data *const c_data) LOG_DBG("CDC NCM class initialized"); - if (usbd_add_descriptor(uds_ctx, data->mac_desc_data)) { - LOG_ERR("Failed to add iMACAddress string descriptor"); - } else { - desc->if0_ecm.iMACAddress = usbd_str_desc_get_idx(data->mac_desc_data); + if (desc->if0_ecm.iMACAddress == 0) { + if (usbd_add_descriptor(uds_ctx, data->mac_desc_data)) { + LOG_ERR("Failed to add iMACAddress string descriptor"); + } else { + desc->if0_ecm.iMACAddress = usbd_str_desc_get_idx(data->mac_desc_data); + } } return 0; @@ -1243,7 +1245,7 @@ static struct usbd_cdc_ncm_desc cdc_ncm_desc_##n = { \ .bFunctionLength = sizeof(struct cdc_ecm_descriptor), \ .bDescriptorType = USB_DESC_CS_INTERFACE, \ .bDescriptorSubtype = ETHERNET_FUNC_DESC, \ - .iMACAddress = 4, \ + .iMACAddress = 0, \ .bmEthernetStatistics = sys_cpu_to_le32(0), \ .wMaxSegmentSize = sys_cpu_to_le16(NET_ETH_MAX_FRAME_SIZE), \ .wNumberMCFilters = sys_cpu_to_le16(0), \ diff --git a/subsys/usb/device_next/class/usbd_uac2.c b/subsys/usb/device_next/class/usbd_uac2.c index 3a53b5c5d217b..ee95e643294e1 100644 --- a/subsys/usb/device_next/class/usbd_uac2.c +++ b/subsys/usb/device_next/class/usbd_uac2.c @@ -378,7 +378,7 @@ static void schedule_iso_out_read(struct usbd_class_data *const c_data, /* Prepare transfer to read audio OUT data from host */ data_buf = ctx->ops->get_recv_buf(dev, terminal, mps, ctx->user_data); if (!data_buf) { - LOG_ERR("No data buffer for terminal %d", terminal); + LOG_ERR_RATELIMIT("No data buffer for terminal %d", terminal); atomic_clear_bit(queued_bits, as_idx); return; } diff --git a/subsys/usb/host/usbh_api.c b/subsys/usb/host/usbh_api.c index e1aa6e99ac3b9..8501ee044b2ad 100644 --- a/subsys/usb/host/usbh_api.c +++ b/subsys/usb/host/usbh_api.c @@ -6,16 +6,17 @@ #include #include +#include "usbh_host.h" #include "usbh_internal.h" #include LOG_MODULE_REGISTER(uhs_api, CONFIG_USBH_LOG_LEVEL); -int usbh_init(struct usbh_contex *uhs_ctx) +int usbh_init(struct usbh_context *uhs_ctx) { int ret; - k_mutex_lock(&uhs_ctx->mutex, K_FOREVER); + usbh_host_lock(uhs_ctx); if (!device_is_ready(uhs_ctx->dev)) { LOG_ERR("USB host controller is not ready"); @@ -32,15 +33,15 @@ int usbh_init(struct usbh_contex *uhs_ctx) ret = usbh_init_device_intl(uhs_ctx); init_exit: - k_mutex_unlock(&uhs_ctx->mutex); + usbh_host_unlock(uhs_ctx); return ret; } -int usbh_enable(struct usbh_contex *uhs_ctx) +int usbh_enable(struct usbh_context *uhs_ctx) { int ret; - k_mutex_lock(&uhs_ctx->mutex, K_FOREVER); + usbh_host_lock(uhs_ctx); if (!uhc_is_initialized(uhs_ctx->dev)) { LOG_WRN("USB host controller is not initialized"); @@ -61,11 +62,11 @@ int usbh_enable(struct usbh_contex *uhs_ctx) } enable_exit: - k_mutex_unlock(&uhs_ctx->mutex); + usbh_host_unlock(uhs_ctx); return ret; } -int usbh_disable(struct usbh_contex *uhs_ctx) +int usbh_disable(struct usbh_context *uhs_ctx) { int ret; @@ -74,30 +75,30 @@ int usbh_disable(struct usbh_contex *uhs_ctx) return 0; } - k_mutex_lock(&uhs_ctx->mutex, K_FOREVER); + usbh_host_lock(uhs_ctx); ret = uhc_disable(uhs_ctx->dev); if (ret) { LOG_ERR("Failed to disable USB controller"); } - k_mutex_unlock(&uhs_ctx->mutex); + usbh_host_unlock(uhs_ctx); return 0; } -int usbh_shutdown(struct usbh_contex *const uhs_ctx) +int usbh_shutdown(struct usbh_context *const uhs_ctx) { int ret; - k_mutex_lock(&uhs_ctx->mutex, K_FOREVER); + usbh_host_lock(uhs_ctx); ret = uhc_shutdown(uhs_ctx->dev); if (ret) { LOG_ERR("Failed to shutdown USB device"); } - k_mutex_unlock(&uhs_ctx->mutex); + usbh_host_unlock(uhs_ctx); return ret; } diff --git a/subsys/usb/host/usbh_core.c b/subsys/usb/host/usbh_core.c index c18ef39cb63cf..1b654b5041133 100644 --- a/subsys/usb/host/usbh_core.c +++ b/subsys/usb/host/usbh_core.c @@ -43,7 +43,7 @@ static int usbh_event_carrier(const struct device *dev, return err; } -static void dev_connected_handler(struct usbh_contex *const ctx, +static void dev_connected_handler(struct usbh_context *const ctx, const struct uhc_event *const event) { @@ -73,7 +73,7 @@ static void dev_connected_handler(struct usbh_contex *const ctx, } } -static void dev_removed_handler(struct usbh_contex *const ctx) +static void dev_removed_handler(struct usbh_context *const ctx) { if (ctx->root != NULL) { usbh_device_free(ctx->root); @@ -84,7 +84,7 @@ static void dev_removed_handler(struct usbh_contex *const ctx) } } -static int discard_ep_request(struct usbh_contex *const ctx, +static int discard_ep_request(struct usbh_context *const ctx, struct uhc_transfer *const xfer) { const struct device *dev = ctx->dev; @@ -97,7 +97,7 @@ static int discard_ep_request(struct usbh_contex *const ctx, return uhc_xfer_free(dev, xfer); } -static ALWAYS_INLINE int usbh_event_handler(struct usbh_contex *const ctx, +static ALWAYS_INLINE int usbh_event_handler(struct usbh_context *const ctx, struct uhc_event *const event) { int ret = 0; @@ -141,7 +141,7 @@ static void usbh_bus_thread(void *p1, void *p2, void *p3) ARG_UNUSED(p2); ARG_UNUSED(p3); - struct usbh_contex *uhs_ctx; + struct usbh_context *uhs_ctx; struct uhc_event event; while (true) { @@ -158,7 +158,7 @@ static void usbh_thread(void *p1, void *p2, void *p3) ARG_UNUSED(p2); ARG_UNUSED(p3); - struct usbh_contex *uhs_ctx; + struct usbh_context *uhs_ctx; struct uhc_event event; usbh_udev_cb_t cb; int ret; @@ -182,7 +182,7 @@ static void usbh_thread(void *p1, void *p2, void *p3) } } -int usbh_init_device_intl(struct usbh_contex *const uhs_ctx) +int usbh_init_device_intl(struct usbh_context *const uhs_ctx) { int ret; diff --git a/subsys/usb/host/usbh_data.ld b/subsys/usb/host/usbh_data.ld index 193c63efc0ed2..4363154f29474 100644 --- a/subsys/usb/host/usbh_data.ld +++ b/subsys/usb/host/usbh_data.ld @@ -1,4 +1,4 @@ #include -ITERABLE_SECTION_RAM(usbh_contex, Z_LINK_ITERABLE_SUBALIGN) +ITERABLE_SECTION_RAM(usbh_context, Z_LINK_ITERABLE_SUBALIGN) ITERABLE_SECTION_RAM(usbh_class_data, Z_LINK_ITERABLE_SUBALIGN) diff --git a/subsys/usb/host/usbh_device.c b/subsys/usb/host/usbh_device.c index 13a2a81ccd2c1..92ecf6ae7aee1 100644 --- a/subsys/usb/host/usbh_device.c +++ b/subsys/usb/host/usbh_device.c @@ -18,7 +18,7 @@ K_MEM_SLAB_DEFINE_STATIC(usb_device_slab, sizeof(struct usb_device), K_HEAP_DEFINE(usb_device_heap, CONFIG_USBH_USB_DEVICE_HEAP); -struct usb_device *usbh_device_alloc(struct usbh_contex *const uhs_ctx) +struct usb_device *usbh_device_alloc(struct usbh_context *const uhs_ctx) { struct usb_device *udev; @@ -37,7 +37,7 @@ struct usb_device *usbh_device_alloc(struct usbh_contex *const uhs_ctx) void usbh_device_free(struct usb_device *const udev) { - struct usbh_contex *const uhs_ctx = udev->ctx; + struct usbh_context *const uhs_ctx = udev->ctx; sys_bitarray_clear_bit(uhs_ctx->addr_ba, udev->addr); sys_dlist_remove(&udev->node); @@ -48,7 +48,7 @@ void usbh_device_free(struct usb_device *const udev) k_mem_slab_free(&usb_device_slab, (void *)udev); } -struct usb_device *usbh_device_get_any(struct usbh_contex *const uhs_ctx) +struct usb_device *usbh_device_get_any(struct usbh_context *const uhs_ctx) { sys_dnode_t *const node = sys_dlist_peek_head(&uhs_ctx->udevs); struct usb_device *udev; @@ -58,7 +58,7 @@ struct usb_device *usbh_device_get_any(struct usbh_contex *const uhs_ctx) return udev; } -struct usb_device *usbh_device_get(struct usbh_contex *const uhs_ctx, const uint8_t addr) +struct usb_device *usbh_device_get(struct usbh_context *const uhs_ctx, const uint8_t addr) { struct usb_device *udev; @@ -99,7 +99,7 @@ static int validate_device_mps0(const struct usb_device *const udev) static int alloc_device_address(struct usb_device *const udev, uint8_t *const addr) { - struct usbh_contex *const uhs_ctx = udev->ctx; + struct usbh_context *const uhs_ctx = udev->ctx; int val; int err; @@ -285,7 +285,7 @@ static int parse_configuration_descriptor(struct usb_device *const udev) dhp = (void *)((uint8_t *)udev->cfg_desc + cfg_desc->bLength); desc_end = (void *)((uint8_t *)udev->cfg_desc + cfg_desc->wTotalLength); - while ((dhp->bDescriptorType != 0 || dhp->bLength != 0) && (void *)dhp < desc_end) { + while ((void *)dhp < desc_end && (dhp->bDescriptorType != 0 || dhp->bLength != 0)) { if (dhp->bDescriptorType == USB_DESC_INTERFACE_ASSOC) { iad = (struct usb_association_descriptor *)dhp; LOG_DBG("bFirstInterface %u", iad->bFirstInterface); @@ -449,7 +449,7 @@ int usbh_device_set_configuration(struct usb_device *const udev, const uint8_t n int usbh_device_init(struct usb_device *const udev) { - struct usbh_contex *const uhs_ctx = udev->ctx; + struct usbh_context *const uhs_ctx = udev->ctx; uint8_t new_addr; int err; diff --git a/subsys/usb/host/usbh_device.h b/subsys/usb/host/usbh_device.h index 19613bda3bfa4..5c5637fb0bee8 100644 --- a/subsys/usb/host/usbh_device.h +++ b/subsys/usb/host/usbh_device.h @@ -20,12 +20,12 @@ typedef int (*usbh_udev_cb_t)(struct usb_device *const udev, * connection without hub support, this is the device connected directly to the * host controller. */ -struct usb_device *usbh_device_get_any(struct usbh_contex *const ctx); +struct usb_device *usbh_device_get_any(struct usbh_context *const ctx); -struct usb_device *usbh_device_get(struct usbh_contex *const uhs_ctx, const uint8_t addr); +struct usb_device *usbh_device_get(struct usbh_context *const uhs_ctx, const uint8_t addr); /* Allocate/free USB device */ -struct usb_device *usbh_device_alloc(struct usbh_contex *const uhs_ctx); +struct usb_device *usbh_device_alloc(struct usbh_context *const uhs_ctx); void usbh_device_free(struct usb_device *const udev); /* Reset and configure new USB device */ @@ -42,7 +42,7 @@ static inline struct uhc_transfer *usbh_xfer_alloc(struct usb_device *udev, usbh_udev_cb_t cb, void *const cb_priv) { - struct usbh_contex *const ctx = udev->ctx; + struct usbh_context *const ctx = udev->ctx; return uhc_xfer_alloc(ctx->dev, ep, udev, cb, cb_priv); } @@ -51,7 +51,7 @@ static inline int usbh_xfer_buf_add(const struct usb_device *udev, struct uhc_transfer *const xfer, struct net_buf *buf) { - struct usbh_contex *const ctx = udev->ctx; + struct usbh_context *const ctx = udev->ctx; return uhc_xfer_buf_add(ctx->dev, xfer, buf); } @@ -59,7 +59,7 @@ static inline int usbh_xfer_buf_add(const struct usb_device *udev, static inline struct net_buf *usbh_xfer_buf_alloc(struct usb_device *udev, const size_t size) { - struct usbh_contex *const ctx = udev->ctx; + struct usbh_context *const ctx = udev->ctx; return uhc_xfer_buf_alloc(ctx->dev, size); } @@ -67,7 +67,7 @@ static inline struct net_buf *usbh_xfer_buf_alloc(struct usb_device *udev, static inline int usbh_xfer_free(const struct usb_device *udev, struct uhc_transfer *const xfer) { - struct usbh_contex *const ctx = udev->ctx; + struct usbh_context *const ctx = udev->ctx; return uhc_xfer_free(ctx->dev, xfer); } @@ -75,7 +75,7 @@ static inline int usbh_xfer_free(const struct usb_device *udev, static inline void usbh_xfer_buf_free(const struct usb_device *udev, struct net_buf *const buf) { - struct usbh_contex *const ctx = udev->ctx; + struct usbh_context *const ctx = udev->ctx; uhc_xfer_buf_free(ctx->dev, buf); } @@ -83,7 +83,7 @@ static inline void usbh_xfer_buf_free(const struct usb_device *udev, static inline int usbh_xfer_enqueue(const struct usb_device *udev, struct uhc_transfer *const xfer) { - struct usbh_contex *const ctx = udev->ctx; + struct usbh_context *const ctx = udev->ctx; return uhc_ep_enqueue(ctx->dev, xfer); } @@ -91,7 +91,7 @@ static inline int usbh_xfer_enqueue(const struct usb_device *udev, static inline int usbh_xfer_dequeue(const struct usb_device *udev, struct uhc_transfer *const xfer) { - struct usbh_contex *const ctx = udev->ctx; + struct usbh_context *const ctx = udev->ctx; return uhc_ep_dequeue(ctx->dev, xfer); } diff --git a/subsys/usb/host/usbh_host.h b/subsys/usb/host/usbh_host.h new file mode 100644 index 0000000000000..1f04a72cdd019 --- /dev/null +++ b/subsys/usb/host/usbh_host.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_USBH_HOST_H +#define ZEPHYR_INCLUDE_USBH_HOST_H + +#include +#include + +/** + * @brief Lock the USB host stack context + * + * @param[in] uhs_ctx Pointer to a host context + */ +static inline void usbh_host_lock(struct usbh_context *const uhs_ctx) +{ + k_mutex_lock(&uhs_ctx->mutex, K_FOREVER); +} + +/** + * @brief Unlock the USB host stack context + * + * @param[in] uhs_ctx Pointer to a host context + */ +static inline void usbh_host_unlock(struct usbh_context *const uhs_ctx) +{ + k_mutex_unlock(&uhs_ctx->mutex); +} + +#endif /* ZEPHYR_INCLUDE_USBH_HOST_H */ diff --git a/subsys/usb/host/usbh_internal.h b/subsys/usb/host/usbh_internal.h index c731520118ed2..8fa8e7d48e19c 100644 --- a/subsys/usb/host/usbh_internal.h +++ b/subsys/usb/host/usbh_internal.h @@ -10,6 +10,6 @@ #include #include -int usbh_init_device_intl(struct usbh_contex *const uhs_ctx); +int usbh_init_device_intl(struct usbh_context *const uhs_ctx); #endif /* ZEPHYR_INCLUDE_USBH_INTERNAL_H */ diff --git a/subsys/usb/host/usbip.c b/subsys/usb/host/usbip.c index 773acbb55d32e..385f763463cdd 100644 --- a/subsys/usb/host/usbip.c +++ b/subsys/usb/host/usbip.c @@ -48,7 +48,7 @@ struct usbip_dev_ctx { /* Context of the exported bus (not really used yet) */ struct usbip_bus_ctx { - struct usbh_contex *uhs_ctx; + struct usbh_context *uhs_ctx; struct usbip_dev_ctx devs[CONFIG_USBIP_DEVICES_COUNT]; uint8_t busnum; }; diff --git a/subsys/zbus/Kconfig b/subsys/zbus/Kconfig index f20e42ff4c8e6..2e418f99ff284 100644 --- a/subsys/zbus/Kconfig +++ b/subsys/zbus/Kconfig @@ -54,7 +54,7 @@ config ZBUS_MSG_SUBSCRIBER_NET_BUF_POOL_ISOLATION config ZBUS_MSG_SUBSCRIBER_NET_BUF_POOL_SIZE default 16 - int "The count of net_buf available to be used simutaneously." + int "The count of net_buf available to be used simultaneously." if ZBUS_MSG_SUBSCRIBER_BUF_ALLOC_STATIC diff --git a/tests/application_development/code_relocation/src/main.c b/tests/application_development/code_relocation/src/main.c index e8554c4354c0e..e9cd592401e82 100644 --- a/tests/application_development/code_relocation/src/main.c +++ b/tests/application_development/code_relocation/src/main.c @@ -42,7 +42,7 @@ void disable_mpu_rasr_xn(void) /* override the default memcpy as zephyr will call this before relocation happens */ __boot_func -void z_early_memcpy(void *dst, const void *src, size_t n) +void arch_early_memcpy(void *dst, const void *src, size_t n) { /* attempt word-sized copying only if buffers have identical alignment */ unsigned char *d_byte = (unsigned char *)dst; @@ -56,7 +56,7 @@ void z_early_memcpy(void *dst, const void *src, size_t n) } __boot_func -void z_early_memset(void *dst, int c, size_t n) +void arch_early_memset(void *dst, int c, size_t n) { /* do byte-sized initialization until word-aligned or finished */ diff --git a/tests/application_development/ram_context_for_isr/Kconfig b/tests/application_development/ram_context_for_isr/Kconfig new file mode 100644 index 0000000000000..30f2e20a3d12a --- /dev/null +++ b/tests/application_development/ram_context_for_isr/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2025 Muhmmad Waleed Badar +# +# SPDX-License-Identifier: Apache-2.0 + +source "Kconfig.zephyr" + +config TEST_IRQ_NUM + int "Test IRQ number" + default 42 if BOARD_QEMU_CORTEX_M3 + default 14 if GIC + default 22 if SOC_SERIES_DA1469X + default 18 if SOC_SERIES_STM32C0X + default 0 + help + IRQ number to use for testing purposes. This should be an + available/unused IRQ on the target platform. + + Platform-specific defaults: + - QEMU Cortex-M3: 42 (available test IRQ) + - GIC platforms: 14 (available test SGI - Software Generated Interrupt) + - DA1469X series: 22 (available test IRQ) + - STM32C0X series: 18 (available test IRQ) + - Other platforms: 0 (magic config value to select the last IRQ: NUM_IRQS - 1) + +config TEST_IRQ_PRIO + int "Test IRQ priority" + default 160 if GIC + default 1 + help + Platform-specific defaults: + - GIC platforms: IRQ_DEFAULT_PRIORITY (system default) + - Other platforms: 1 (high priority for testing) diff --git a/tests/application_development/ram_context_for_isr/include/fake_driver.h b/tests/application_development/ram_context_for_isr/include/fake_driver.h index 27d7ca2f2e286..78477ca093238 100644 --- a/tests/application_development/ram_context_for_isr/include/fake_driver.h +++ b/tests/application_development/ram_context_for_isr/include/fake_driver.h @@ -11,23 +11,11 @@ extern "C" { #endif -#ifdef CONFIG_BOARD_QEMU_CORTEX_M3 - -#define TEST_IRQ_NUM 42 -#define TEST_IRQ_PRIO 1 - -#elif defined(CONFIG_GIC) -/* - * For the platforms that use the ARM GIC, use the SGI (software generated - * interrupt) line 14 for testing. - */ -#define TEST_IRQ_NUM 14 -#define TEST_IRQ_PRIO IRQ_DEFAULT_PRIORITY - -#else +#if CONFIG_TEST_IRQ_NUM == 0 /* For all the other platforms, use the last available IRQ line for testing. */ -#define TEST_IRQ_NUM (CONFIG_NUM_IRQS - 1) -#define TEST_IRQ_PRIO 1 +#define TEST_IRQ_NUM (CONFIG_NUM_IRQS - 1) +#else +#define TEST_IRQ_NUM CONFIG_TEST_IRQ_NUM #endif typedef void (*fake_driver_irq_callback_t)(const struct device *dev, void *user_data); diff --git a/tests/application_development/ram_context_for_isr/src/fake_driver.c b/tests/application_development/ram_context_for_isr/src/fake_driver.c index c750c99ddb135..d2d968f39467a 100644 --- a/tests/application_development/ram_context_for_isr/src/fake_driver.c +++ b/tests/application_development/ram_context_for_isr/src/fake_driver.c @@ -63,14 +63,14 @@ static int fake_driver_init(const struct device *dev) static struct fake_driver_data fake_driver_data_##inst; \ static void fake_driver_irq_config_func_##inst(void) \ { \ - IRQ_CONNECT(TEST_IRQ_NUM, TEST_IRQ_PRIO, fake_driver_isr, \ + IRQ_CONNECT(TEST_IRQ_NUM, CONFIG_TEST_IRQ_PRIO, fake_driver_isr, \ DEVICE_DT_INST_GET(inst), 0); \ irq_enable(TEST_IRQ_NUM); \ } \ static struct fake_driver_config fake_driver_config_##inst = { \ .irq_config_func = fake_driver_irq_config_func_##inst, \ .irq_num = TEST_IRQ_NUM, \ - .irq_priority = TEST_IRQ_PRIO, \ + .irq_priority = CONFIG_TEST_IRQ_PRIO, \ }; \ DEVICE_DT_INST_DEFINE(inst, &fake_driver_init, NULL, &fake_driver_data_##inst, \ &fake_driver_config_##inst, PRE_KERNEL_1, \ diff --git a/tests/application_development/ram_context_for_isr/testcase.yaml b/tests/application_development/ram_context_for_isr/testcase.yaml index ad7cd96115924..6aa5806c28b3e 100644 --- a/tests/application_development/ram_context_for_isr/testcase.yaml +++ b/tests/application_development/ram_context_for_isr/testcase.yaml @@ -6,7 +6,6 @@ tests: application_development.ram_context_for_isr: # Exclude mps3/corstone310 because it uses another mechanism to support relocation # of the vector table (CONFIG_ROMSTART_RELOCATION_ROM). - # (Temporarily) Exclude STM32C0 platforms as last IRQ in vector is always used. platform_exclude: - mps3/corstone310/an555 - mps3/corstone310/fvp @@ -20,7 +19,3 @@ tests: - hexiwear/mkw40z4 - frdm_kw41z/mkw41z4 - frdm_kl25z/mkl25z4 - - stm32c0116_dk/stm32c011xx - - nucleo_c031c6/stm32c031xx - - nucleo_c071rb/stm32c071xx - - nucleo_c092rc/stm32c092xx diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index d1566b5aa6313..57d4a8a5babe0 100644 --- a/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -8,6 +8,6 @@ status = "disabled"; }; -&cpusec_bellboard{ +&cpusec_bellboard { status = "disabled"; }; diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpurad.overlay index 04c22168b6c21..be4b7c565d6dc 100644 --- a/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -8,6 +8,6 @@ status = "disabled"; }; -&cpusec_bellboard{ +&cpusec_bellboard { status = "disabled"; }; diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpuapp.overlay index d1566b5aa6313..57d4a8a5babe0 100644 --- a/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpuapp.overlay +++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpuapp.overlay @@ -8,6 +8,6 @@ status = "disabled"; }; -&cpusec_bellboard{ +&cpusec_bellboard { status = "disabled"; }; diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpurad.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpurad.overlay index 04c22168b6c21..be4b7c565d6dc 100644 --- a/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpurad.overlay +++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpurad.overlay @@ -8,6 +8,6 @@ status = "disabled"; }; -&cpusec_bellboard{ +&cpusec_bellboard { status = "disabled"; }; diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_an547.overlay b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_an547.overlay index 7c5a2c5767778..4cae5456dbcf4 100644 --- a/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_an547.overlay +++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_an547.overlay @@ -7,12 +7,11 @@ #include #include - / { sram: sram@11000000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x11000000 DT_SIZE_M(1)>; zephyr,memory-region = "SRAM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>; + zephyr,memory-attr = ; }; }; diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_fvp.overlay b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_fvp.overlay index 7c5a2c5767778..4cae5456dbcf4 100644 --- a/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_fvp.overlay +++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_fvp.overlay @@ -7,12 +7,11 @@ #include #include - / { sram: sram@11000000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x11000000 DT_SIZE_M(1)>; zephyr,memory-region = "SRAM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>; + zephyr,memory-attr = ; }; }; diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone310_fvp.overlay b/tests/arch/arm/arm_mpu_pxn/mps3_corstone310_fvp.overlay index cb51331990fa4..dbff9651c9771 100644 --- a/tests/arch/arm/arm_mpu_pxn/mps3_corstone310_fvp.overlay +++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone310_fvp.overlay @@ -7,12 +7,11 @@ #include #include - / { dtcm: dtcm@30000000 { compatible = "zephyr,memory-region"; reg = <0x30000000 DT_SIZE_K(32)>; zephyr,memory-region = "DTCM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>; + zephyr,memory-attr = ; }; }; diff --git a/tests/arch/arm/arm_mpu_pxn/mps4_corstone315_fvp.overlay b/tests/arch/arm/arm_mpu_pxn/mps4_corstone315_fvp.overlay index cb51331990fa4..dbff9651c9771 100644 --- a/tests/arch/arm/arm_mpu_pxn/mps4_corstone315_fvp.overlay +++ b/tests/arch/arm/arm_mpu_pxn/mps4_corstone315_fvp.overlay @@ -7,12 +7,11 @@ #include #include - / { dtcm: dtcm@30000000 { compatible = "zephyr,memory-region"; reg = <0x30000000 DT_SIZE_K(32)>; zephyr,memory-region = "DTCM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>; + zephyr,memory-attr = ; }; }; diff --git a/tests/arch/arm/arm_mpu_pxn/mps4_corstone320_fvp.overlay b/tests/arch/arm/arm_mpu_pxn/mps4_corstone320_fvp.overlay index cb51331990fa4..dbff9651c9771 100644 --- a/tests/arch/arm/arm_mpu_pxn/mps4_corstone320_fvp.overlay +++ b/tests/arch/arm/arm_mpu_pxn/mps4_corstone320_fvp.overlay @@ -7,12 +7,11 @@ #include #include - / { dtcm: dtcm@30000000 { compatible = "zephyr,memory-region"; reg = <0x30000000 DT_SIZE_K(32)>; zephyr,memory-region = "DTCM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>; + zephyr,memory-attr = ; }; }; diff --git a/tests/arch/arm/arm_pacbti/CMakeLists.txt b/tests/arch/arm/arm_pacbti/CMakeLists.txt new file mode 100644 index 0000000000000..e51a99b7e8d13 --- /dev/null +++ b/tests/arch/arm/arm_pacbti/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(arm_pacbti) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/arch/arm/arm_pacbti/prj.conf b/tests/arch/arm/arm_pacbti/prj.conf new file mode 100644 index 0000000000000..861387ac2246c --- /dev/null +++ b/tests/arch/arm/arm_pacbti/prj.conf @@ -0,0 +1,9 @@ +CONFIG_ZTEST=y +CONFIG_ZTEST_FATAL_HOOK=y + +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_TIMER_RANDOM_INITIAL_STATE=123456789 +CONFIG_TIMER_RANDOM_GENERATOR=y + +CONFIG_IDLE_STACK_SIZE=1024 +CONFIG_ISR_STACK_SIZE=1024 diff --git a/tests/arch/arm/arm_pacbti/src/main.c b/tests/arch/arm/arm_pacbti/src/main.c new file mode 100644 index 0000000000000..b35a304cb1d16 --- /dev/null +++ b/tests/arch/arm/arm_pacbti/src/main.c @@ -0,0 +1,112 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/* size of stack area used by each thread */ +#define STACKSIZE 1024 + +/* scheduling priority used by each thread */ +#define PRIORITY 7 + +/* number of times to check if PAC keys were retained */ +#define NUM_TRIALS 5 + +K_THREAD_STACK_DEFINE(pac_test_thread_stack_area, STACKSIZE); +static struct k_thread pac_test_thread; + +void test_arm_pacbti(void) +{ + printf("%s This should never have been called if BTI was enforced\n", __func__); + + /* If func call was successful then BTI didn't work as expected */ + ztest_test_fail(); +} + +/* Without PAC this function would have returned to test_arm_pacbti() but with PAC enabled + * the AUT instruction should result in a USAGE FAULT since the `lr` was corrupted on stack. + */ +__asm__(".thumb\n" + ".thumb_func\n" + ".global corrupt_lr_on_stack\n" + "corrupt_lr_on_stack:\n" + " pacbti r12, lr, sp\n" + " stmdb sp!, {ip, lr}\n" + " ldr r0,=test_arm_pacbti\n" + " str r0, [sp, #4]\n" + " ldmia.w sp!, {ip, lr}\n" + " aut r12, lr, sp\n" + " bx lr\n"); +void corrupt_lr_on_stack(void); + +static int set_invalid_pac_key(void) +{ + struct pac_keys test_pac_keys = {0}; + + __get_PAC_KEY_P((uint32_t *)&test_pac_keys); + + /* Change PAC KEY for the current thread */ + test_pac_keys.key_0 += 1; + test_pac_keys.key_1 += 1; + test_pac_keys.key_2 += 1; + test_pac_keys.key_3 += 1; + + __set_PAC_KEY_P((uint32_t *)&test_pac_keys); + + /* The AUT instruction before this test returns should now result in a USAGE FAULT */ + return 1; +} + +static void pac_test_thread_entry_point(void *dummy1, void *dummy2, void *dummy3) +{ + ztest_set_fault_valid(true); + + corrupt_lr_on_stack(); +} + +ZTEST(arm_pacbti, test_arm_pac_corrupt_lr_in_userspace) +{ + k_thread_create(&pac_test_thread, pac_test_thread_stack_area, + K_THREAD_STACK_SIZEOF(pac_test_thread_stack_area), + pac_test_thread_entry_point, NULL, NULL, NULL, PRIORITY, K_USER, K_FOREVER); + + k_thread_start(&pac_test_thread); + k_thread_join(&pac_test_thread, K_FOREVER); +} + +ZTEST(arm_pacbti, test_arm_pac_corrupt_lr) +{ + ztest_set_fault_valid(true); + + corrupt_lr_on_stack(); +} + +ZTEST(arm_pacbti, test_arm_pac_invalid_key) +{ + ztest_set_fault_valid(true); + + if (set_invalid_pac_key()) { + printf("set_invalid_pac_key should never have returned if AUT was enforced\n"); + ztest_test_fail(); + } +} + +ZTEST(arm_pacbti, test_arm_bti) +{ + /* Try jumping to middle of a random function and mark that fault as expected because if + * BTI is enforced and an indirect jump is made on a non-BTI instruction then a usage fault + * is generated. + */ + ztest_set_fault_valid(true); + + __asm__ volatile(" ldr r1, =test_arm_pacbti\n" + " add r1, #4\n" + " bx r1\n"); +} + +ZTEST_SUITE(arm_pacbti, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/arch/arm/arm_pacbti/testcase.yaml b/tests/arch/arm/arm_pacbti/testcase.yaml new file mode 100644 index 0000000000000..b0e43e706c475 --- /dev/null +++ b/tests/arch/arm/arm_pacbti/testcase.yaml @@ -0,0 +1,16 @@ +common: + tags: + - arm + platform_allow: + - mps3/corstone310/fvp + - mps3/corstone310/fvp/ns + - mps4/corstone315/fvp + - mps4/corstone320/fvp +tests: + arch.arm.pacbti.standard: + # TODO: remove skip after Zephyr sdk makes GCC 14.3 as default + skip: true + extra_configs: + - CONFIG_ARM_PACBTI_STANDARD=y + - CONFIG_ARM_PAC_PER_THREAD=y + - CONFIG_USERSPACE=y diff --git a/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay b/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay index 1f5086aa8cc63..3d2dc239fcbf8 100644 --- a/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay +++ b/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay @@ -4,13 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ - - /* This partition table should be used along with TFM configuration: - * - TEST_S=OFF (NO REGRESSION) - * - * In this configuration, TFM binary does not include tests. - * The partition sizes are compatible with TF-M platform flash_layout.h. - */ +/* This partition table should be used along with TFM configuration: + * - TEST_S=OFF (NO REGRESSION) + * + * In this configuration, TFM binary does not include tests. + * The partition sizes are compatible with TF-M platform flash_layout.h. + */ / { chosen { diff --git a/tests/arch/arm64/arm64_gicv3_its/boards/imx943_evk_mimx94398_a55.conf b/tests/arch/arm64/arm64_gicv3_its/boards/imx943_evk_mimx94398_a55.conf new file mode 100644 index 0000000000000..70a699068df66 --- /dev/null +++ b/tests/arch/arm64/arm64_gicv3_its/boards/imx943_evk_mimx94398_a55.conf @@ -0,0 +1,15 @@ +# The GICv3 & ITS drivers allocation needs are: +# - LPI prop table: global 1x64K aligned on 64K +# - LPI pend table: for each redistributor/cpu 1x64K aligned on 64K +# - Devices table: 128x4K aligned on 4K +# - Interrupt Collections table: 1x4K aligned on 4K +# +# This makes 11x64K to permit all allocations to success. +# +# Note, will need 64K HEAP_MEM per CPUs added. +# +# This doesn't necessarily include the Interrupt Translation Table, which are +# 256bytes aligned tables, for reference a 32 ITEs table needs 256bytes. +# +# To permit allocating 256 ITT tables of 32 ITEs, 13x64K HEAP_MEM is needed +CONFIG_HEAP_MEM_POOL_SIZE=851968 diff --git a/tests/arch/arm64/arm64_gicv3_its/src/main.c b/tests/arch/arm64/arm64_gicv3_its/src/main.c index 940e4f504f0d7..af76ebd174b67 100644 --- a/tests/arch/arm64/arm64_gicv3_its/src/main.c +++ b/tests/arch/arm64/arm64_gicv3_its/src/main.c @@ -19,7 +19,7 @@ static void lpi_irq_handle(const void *parameter) last_lpi_irq_num = i; } -#ifdef CONFIG_SOC_MIMX9596_A55 +#if defined(CONFIG_SOC_MIMX9596_A55) || defined(CONFIG_SOC_MIMX94398_A55) /* DeviceID is 8bits */ #define ITS_TEST_DEV(id) (id & 0xff) /* Cover up to 832 LPIs over 26 DevicesIDs and 32 EventIDs per DeviceID */ diff --git a/tests/kernel/gen_isr_table/CMakeLists.txt b/tests/arch/common/gen_isr_table/CMakeLists.txt similarity index 100% rename from tests/kernel/gen_isr_table/CMakeLists.txt rename to tests/arch/common/gen_isr_table/CMakeLists.txt diff --git a/tests/kernel/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf b/tests/arch/common/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf similarity index 100% rename from tests/kernel/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf rename to tests/arch/common/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf diff --git a/tests/kernel/gen_isr_table/prj.conf b/tests/arch/common/gen_isr_table/prj.conf similarity index 100% rename from tests/kernel/gen_isr_table/prj.conf rename to tests/arch/common/gen_isr_table/prj.conf diff --git a/tests/kernel/gen_isr_table/src/main.c b/tests/arch/common/gen_isr_table/src/main.c similarity index 100% rename from tests/kernel/gen_isr_table/src/main.c rename to tests/arch/common/gen_isr_table/src/main.c diff --git a/tests/kernel/gen_isr_table/src/multilevel_irq.c b/tests/arch/common/gen_isr_table/src/multilevel_irq.c similarity index 100% rename from tests/kernel/gen_isr_table/src/multilevel_irq.c rename to tests/arch/common/gen_isr_table/src/multilevel_irq.c diff --git a/tests/kernel/gen_isr_table/testcase.yaml b/tests/arch/common/gen_isr_table/testcase.yaml similarity index 100% rename from tests/kernel/gen_isr_table/testcase.yaml rename to tests/arch/common/gen_isr_table/testcase.yaml diff --git a/tests/kernel/interrupt/CMakeLists.txt b/tests/arch/common/interrupt/CMakeLists.txt similarity index 100% rename from tests/kernel/interrupt/CMakeLists.txt rename to tests/arch/common/interrupt/CMakeLists.txt diff --git a/tests/kernel/interrupt/Kconfig b/tests/arch/common/interrupt/Kconfig similarity index 100% rename from tests/kernel/interrupt/Kconfig rename to tests/arch/common/interrupt/Kconfig diff --git a/tests/kernel/interrupt/multilevel_irq.overlay b/tests/arch/common/interrupt/multilevel_irq.overlay similarity index 80% rename from tests/kernel/interrupt/multilevel_irq.overlay rename to tests/arch/common/interrupt/multilevel_irq.overlay index a33b27fbcfdf6..18e720d49f2bc 100644 --- a/tests/kernel/interrupt/multilevel_irq.overlay +++ b/tests/arch/common/interrupt/multilevel_irq.overlay @@ -5,17 +5,17 @@ / { test { - #address-cells = < 0x1 >; - #size-cells = < 0x1 >; + #address-cells = <0x1>; + #size-cells = <0x1>; - test_cpu_intc: interrupt-controller { + test_cpu_intc: interrupt-controller { compatible = "vnd,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; - test_l1_irq: interrupt-controller@bbbbcccc { + test_l1_irq: interrupt-controller@bbbbcccc { compatible = "vnd,intc"; reg = <0xbbbbcccc 0x1000>; interrupt-controller; @@ -24,7 +24,7 @@ interrupt-parent = <&test_cpu_intc>; }; - test_l2_irq: interrupt-controller@bbbccccc { + test_l2_irq: interrupt-controller@bbbccccc { compatible = "vnd,intc"; reg = <0xbbbccccc 0x1000>; interrupt-controller; @@ -41,7 +41,7 @@ interrupt-names = "test"; }; - test_l1_irq_inc: interrupt-controller@bbbbdccc { + test_l1_irq_inc: interrupt-controller@bbbbdccc { compatible = "vnd,intc"; reg = <0xbbbbdccc 0x10>; interrupt-controller; @@ -50,7 +50,7 @@ interrupt-parent = <&test_cpu_intc>; }; - test_l2_irq_inc: interrupt-controller@bbbbdcdc { + test_l2_irq_inc: interrupt-controller@bbbbdcdc { compatible = "vnd,intc"; reg = <0xbbbbdcdc 0x10>; interrupt-controller; diff --git a/tests/kernel/interrupt/prj.conf b/tests/arch/common/interrupt/prj.conf similarity index 100% rename from tests/kernel/interrupt/prj.conf rename to tests/arch/common/interrupt/prj.conf diff --git a/tests/kernel/interrupt/src/dynamic_isr.c b/tests/arch/common/interrupt/src/dynamic_isr.c similarity index 100% rename from tests/kernel/interrupt/src/dynamic_isr.c rename to tests/arch/common/interrupt/src/dynamic_isr.c diff --git a/tests/kernel/interrupt/src/dynamic_shared_irq.c b/tests/arch/common/interrupt/src/dynamic_shared_irq.c similarity index 100% rename from tests/kernel/interrupt/src/dynamic_shared_irq.c rename to tests/arch/common/interrupt/src/dynamic_shared_irq.c diff --git a/tests/kernel/interrupt/src/interrupt_offload.c b/tests/arch/common/interrupt/src/interrupt_offload.c similarity index 100% rename from tests/kernel/interrupt/src/interrupt_offload.c rename to tests/arch/common/interrupt/src/interrupt_offload.c diff --git a/tests/kernel/interrupt/src/multilevel_irq.c b/tests/arch/common/interrupt/src/multilevel_irq.c similarity index 100% rename from tests/kernel/interrupt/src/multilevel_irq.c rename to tests/arch/common/interrupt/src/multilevel_irq.c diff --git a/tests/kernel/interrupt/src/nested_irq.c b/tests/arch/common/interrupt/src/nested_irq.c similarity index 100% rename from tests/kernel/interrupt/src/nested_irq.c rename to tests/arch/common/interrupt/src/nested_irq.c diff --git a/tests/kernel/interrupt/src/prevent_irq.c b/tests/arch/common/interrupt/src/prevent_irq.c similarity index 100% rename from tests/kernel/interrupt/src/prevent_irq.c rename to tests/arch/common/interrupt/src/prevent_irq.c diff --git a/tests/kernel/interrupt/src/regular_isr.c b/tests/arch/common/interrupt/src/regular_isr.c similarity index 100% rename from tests/kernel/interrupt/src/regular_isr.c rename to tests/arch/common/interrupt/src/regular_isr.c diff --git a/tests/kernel/interrupt/src/static_shared_irq.c b/tests/arch/common/interrupt/src/static_shared_irq.c similarity index 100% rename from tests/kernel/interrupt/src/static_shared_irq.c rename to tests/arch/common/interrupt/src/static_shared_irq.c diff --git a/tests/kernel/interrupt/src/sw_isr_table.c b/tests/arch/common/interrupt/src/sw_isr_table.c similarity index 100% rename from tests/kernel/interrupt/src/sw_isr_table.c rename to tests/arch/common/interrupt/src/sw_isr_table.c diff --git a/tests/kernel/interrupt/src/test_shared_irq.h b/tests/arch/common/interrupt/src/test_shared_irq.h similarity index 100% rename from tests/kernel/interrupt/src/test_shared_irq.h rename to tests/arch/common/interrupt/src/test_shared_irq.h diff --git a/tests/kernel/interrupt/testcase.yaml b/tests/arch/common/interrupt/testcase.yaml similarity index 100% rename from tests/kernel/interrupt/testcase.yaml rename to tests/arch/common/interrupt/testcase.yaml diff --git a/tests/kernel/xip/CMakeLists.txt b/tests/arch/common/xip/CMakeLists.txt similarity index 100% rename from tests/kernel/xip/CMakeLists.txt rename to tests/arch/common/xip/CMakeLists.txt diff --git a/tests/kernel/xip/README.txt b/tests/arch/common/xip/README.txt similarity index 100% rename from tests/kernel/xip/README.txt rename to tests/arch/common/xip/README.txt diff --git a/tests/kernel/xip/prj.conf b/tests/arch/common/xip/prj.conf similarity index 100% rename from tests/kernel/xip/prj.conf rename to tests/arch/common/xip/prj.conf diff --git a/tests/kernel/xip/src/main.c b/tests/arch/common/xip/src/main.c similarity index 100% rename from tests/kernel/xip/src/main.c rename to tests/arch/common/xip/src/main.c diff --git a/tests/kernel/xip/testcase.yaml b/tests/arch/common/xip/testcase.yaml similarity index 100% rename from tests/kernel/xip/testcase.yaml rename to tests/arch/common/xip/testcase.yaml diff --git a/tests/arch/x86/cet/CMakeLists.txt b/tests/arch/x86/cet/CMakeLists.txt new file mode 100644 index 0000000000000..6223e8cf7c137 --- /dev/null +++ b/tests/arch/x86/cet/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(cet) + +enable_language(C ASM) + +target_sources(app PRIVATE src/main.c src/asm.S) diff --git a/tests/arch/x86/cet/prj.conf b/tests/arch/x86/cet/prj.conf new file mode 100644 index 0000000000000..1f3f9c819682d --- /dev/null +++ b/tests/arch/x86/cet/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_X86_CET=y +CONFIG_IRQ_OFFLOAD=y diff --git a/tests/arch/x86/cet/src/asm.S b/tests/arch/x86/cet/src/asm.S new file mode 100644 index 0000000000000..4aaec318fdbb3 --- /dev/null +++ b/tests/arch/x86/cet/src/asm.S @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +GTEXT(should_work) +GTEXT(should_not_work) + +#if defined(CONFIG_X86_64) +should_work: + endbr64 + mov %rdi, %rax + inc %rax + ret + +should_not_work: + mov %rdi, %rax + inc %rax + ret +#else +should_work: + endbr32 + push %ebp + mov %esp, %ebp + mov 0x8(%ebp), %eax + inc %eax + pop %ebp + ret + +should_not_work: + push %ebp + mov %esp, %ebp + mov 0x8(%ebp), %eax + inc %eax + pop %ebp + ret +#endif diff --git a/tests/arch/x86/cet/src/main.c b/tests/arch/x86/cet/src/main.c new file mode 100644 index 0000000000000..76ffb3ffd0d2a --- /dev/null +++ b/tests/arch/x86/cet/src/main.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#define IV_CTRL_PROTECTION_EXCEPTION 21 + +#define CTRL_PROTECTION_ERRORCODE_NEAR_RET 1 +#define CTRL_PROTECTION_ERRORCODE_ENDBRANCH 3 + +#define STACKSIZE 1024 +#define THREAD_PRIORITY 5 + +K_SEM_DEFINE(error_handler_sem, 0, 1); + +volatile bool expect_fault; +volatile int expect_code; +volatile int expect_reason; + +void k_sys_fatal_error_handler(unsigned int reason, const struct arch_esf *pEsf) +{ + if (expect_fault) { +#ifdef CONFIG_X86_64 + zassert_equal(pEsf->vector, expect_reason, "unexpected exception"); + zassert_equal(pEsf->code, expect_code, "unexpected error code"); +#else + zassert_equal(z_x86_exception_vector, expect_reason, "unexpected exception"); + zassert_equal(pEsf->errorCode, expect_code, "unexpected error code"); +#endif + printk("fatal error expected as part of test case\n"); + expect_fault = false; + + k_sem_give(&error_handler_sem); + } else { + printk("fatal error was unexpected, aborting\n"); + TC_END_REPORT(TC_FAIL); + k_fatal_halt(reason); + } +} + +#ifdef CONFIG_HW_SHADOW_STACK +void thread_a_entry(void *p1, void *p2, void *p3); +K_SEM_DEFINE(thread_a_sem, 0, 1); +K_THREAD_DEFINE(thread_a, STACKSIZE, thread_a_entry, NULL, NULL, NULL, + THREAD_PRIORITY, 0, -1); + +void thread_b_entry(void *p1, void *p2, void *p3); +K_SEM_DEFINE(thread_b_sem, 0, 1); +K_SEM_DEFINE(thread_b_irq_sem, 0, 1); +K_THREAD_DEFINE(thread_b, STACKSIZE, thread_b_entry, NULL, NULL, NULL, + THREAD_PRIORITY, 0, -1); + +static bool is_shstk_enabled(void) +{ + long cur; + + cur = z_x86_msr_read(X86_S_CET_MSR); + return (cur & X86_S_CET_MSR_SHSTK_EN) == X86_S_CET_MSR_SHSTK_EN; +} + +void thread_c_entry(void *p1, void *p2, void *p3) +{ + zassert_true(is_shstk_enabled(), "shadow stack not enabled on static thread"); +} + +K_THREAD_DEFINE(thread_c, STACKSIZE, thread_c_entry, NULL, NULL, NULL, + THREAD_PRIORITY, 0, 0); + +void __attribute__((optimize("O0"))) foo(void) +{ + printk("foo called\n"); +} + +void __attribute__((optimize("O0"))) fail(void) +{ + long a[] = {0}; + + printk("should fail after this\n"); + + *(a + 2) = (long)&foo; +} + +struct k_work work; + +void work_handler(struct k_work *wrk) +{ + printk("work handler\n"); + + zassert_true(is_shstk_enabled(), "shadow stack not enabled"); +} + +ZTEST(cet, test_shstk_work_q) +{ + k_work_init(&work, work_handler); + k_work_submit(&work); +} + +void intr_handler(const void *p) +{ + printk("interrupt handler\n"); + + if (p != NULL) { + /* Test one nested level. It should just work. */ + printk("trying interrupt handler\n"); + irq_offload(intr_handler, NULL); + + k_sem_give((struct k_sem *)p); + } else { + printk("interrupt handler nested\n"); + } +} + +void thread_b_entry(void *p1, void *p2, void *p3) +{ + k_sem_take(&thread_b_sem, K_FOREVER); + + irq_offload(intr_handler, &thread_b_irq_sem); + + k_sem_take(&thread_b_irq_sem, K_FOREVER); +} + +ZTEST(cet, test_shstk_irq) +{ + k_thread_start(thread_b); + + k_sem_give(&thread_b_sem); + + k_thread_join(thread_b, K_FOREVER); +} + +void thread_a_entry(void *p1, void *p2, void *p3) +{ + k_sem_take(&thread_a_sem, K_FOREVER); + + fail(); + + zassert_unreachable("should not reach here"); +} + +ZTEST(cet, test_shstk) +{ + k_thread_start(thread_a); + + expect_fault = true; + expect_code = CTRL_PROTECTION_ERRORCODE_NEAR_RET; + expect_reason = IV_CTRL_PROTECTION_EXCEPTION; + k_sem_give(&thread_a_sem); + + k_sem_take(&error_handler_sem, K_FOREVER); + k_thread_abort(thread_a); +} +#endif /* CONFIG_HW_SHADOW_STACK */ + +#ifdef CONFIG_X86_CET_IBT +extern int should_work(int a); +extern int should_not_work(int a); + +/* Round trip to trick optimisations and ensure the calls are indirect */ +int do_call(int (*func)(int), int a) +{ + return func(a); +} + +ZTEST(cet, test_ibt) +{ + zassert_equal(do_call(should_work, 1), 2, "should_work failed"); + + expect_fault = true; + expect_code = CTRL_PROTECTION_ERRORCODE_ENDBRANCH; + expect_reason = IV_CTRL_PROTECTION_EXCEPTION; + do_call(should_not_work, 1); + zassert_unreachable("should_not_work did not fault"); +} +#endif /* CONFIG_X86_CET_IBT */ + +ZTEST_SUITE(cet, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/arch/x86/cet/testcase.yaml b/tests/arch/x86/cet/testcase.yaml new file mode 100644 index 0000000000000..3cb9bc00043a2 --- /dev/null +++ b/tests/arch/x86/cet/testcase.yaml @@ -0,0 +1,30 @@ +common: + ignore_faults: true + tags: + - kernel + - cet + filter: CONFIG_X86_CPU_HAS_CET + +tests: + arch.x86.cet.kernel.ibt32: + arch_allow: x86 + filter: not CONFIG_X86_64 + extra_configs: + - CONFIG_X86_CET_IBT=y + - CONFIG_DEBUG_COREDUMP=y + arch.x86.cet.kernel.ibt64: + arch_allow: x86 + filter: CONFIG_X86_64 + extra_configs: + - CONFIG_X86_CET_IBT=y + arch.x86.cet.kernel.shstk64: + arch_allow: x86 + filter: CONFIG_X86_64 + extra_configs: + - CONFIG_HW_SHADOW_STACK=y + arch.x86.cet.kernel.shstk32: + arch_allow: x86 + filter: not CONFIG_X86_64 + extra_configs: + - CONFIG_DEBUG_COREDUMP=y + - CONFIG_HW_SHADOW_STACK=y diff --git a/tests/arch/x86/static_idt/src/test_stubs.S b/tests/arch/x86/static_idt/src/test_stubs.S index cbab47b7f5767..1656bd733f6a7 100644 --- a/tests/arch/x86/static_idt/src/test_stubs.S +++ b/tests/arch/x86/static_idt/src/test_stubs.S @@ -26,6 +26,7 @@ testing. GTEXT(int_stub) SECTION_FUNC(TEXT, int_stub) + endbr32 pushl $0 pushl $isr_handler jmp _interrupt_enter diff --git a/tests/bluetooth/audio/cap_initiator/src/test_common.c b/tests/bluetooth/audio/cap_initiator/src/test_common.c index d671d93d264de..d8fa9517a2e1a 100644 --- a/tests/bluetooth/audio/cap_initiator/src/test_common.c +++ b/tests/bluetooth/audio/cap_initiator/src/test_common.c @@ -64,5 +64,5 @@ void test_unicast_set_state(struct bt_cap_stream *cap_stream, struct bt_conn *co bap_stream->ep = ep; bap_stream->qos = &preset->qos; bap_stream->codec_cfg = &preset->codec_cfg; - bap_stream->ep->status.state = state; + bap_stream->ep->state = state; } diff --git a/tests/bluetooth/audio/cap_initiator/src/test_unicast_group.c b/tests/bluetooth/audio/cap_initiator/src/test_unicast_group.c index 0e64b9f773f20..bf39491cb7d38 100644 --- a/tests/bluetooth/audio/cap_initiator/src/test_unicast_group.c +++ b/tests/bluetooth/audio/cap_initiator/src/test_unicast_group.c @@ -413,3 +413,39 @@ static ZTEST_F(cap_initiator_test_unicast_group, zassert_equal(cnt, expect_cnt, "Unexpected cnt (%zu != %zu)", cnt, expect_cnt); } + +static ZTEST_F(cap_initiator_test_unicast_group, test_initiator_unicast_group_get_info) +{ + struct bt_cap_unicast_group_info cap_info; + int err; + + err = bt_cap_unicast_group_create(fixture->group_param, &fixture->unicast_group); + zassert_equal(err, 0, "Unexpected return value %d", err); + + err = bt_cap_unicast_group_get_info(fixture->unicast_group, &cap_info); + zassert_equal(err, 0, "Unexpected return value %d", err); + + zassert_not_null(cap_info.unicast_group); +} + +static ZTEST_F(cap_initiator_test_unicast_group, + test_initiator_unicast_group_get_info_inval_null_group) +{ + struct bt_cap_unicast_group_info cap_info; + int err; + + err = bt_cap_unicast_group_get_info(NULL, &cap_info); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} + +static ZTEST_F(cap_initiator_test_unicast_group, + test_initiator_unicast_group_get_info_inval_null_info) +{ + int err; + + err = bt_cap_unicast_group_create(fixture->group_param, &fixture->unicast_group); + zassert_equal(err, 0, "Unexpected return value %d", err); + + err = bt_cap_unicast_group_get_info(fixture->unicast_group, NULL); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} diff --git a/tests/bluetooth/audio/cap_initiator/src/test_unicast_start.c b/tests/bluetooth/audio/cap_initiator/src/test_unicast_start.c index b32f50f6f0fa3..710e745386f74 100644 --- a/tests/bluetooth/audio/cap_initiator/src/test_unicast_start.c +++ b/tests/bluetooth/audio/cap_initiator/src/test_unicast_start.c @@ -139,7 +139,7 @@ static ZTEST_F(cap_initiator_test_unicast_start, test_initiator_unicast_start) for (size_t i = 0U; i < ARRAY_SIZE(stream_params); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_STREAMING, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -430,7 +430,7 @@ static ZTEST_F(cap_initiator_test_unicast_start, for (size_t i = 0U; i < ARRAY_SIZE(stream_params); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_STREAMING, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -471,7 +471,7 @@ static ZTEST_F(cap_initiator_test_unicast_start, test_initiator_unicast_start_st for (size_t i = 0U; i < ARRAY_SIZE(stream_params); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_STREAMING, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -512,7 +512,7 @@ static ZTEST_F(cap_initiator_test_unicast_start, test_initiator_unicast_start_st for (size_t i = 0U; i < ARRAY_SIZE(stream_params); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_STREAMING, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -549,7 +549,7 @@ static ZTEST_F(cap_initiator_test_unicast_start, test_initiator_unicast_start_st for (size_t i = 0U; i < ARRAY_SIZE(stream_params); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_STREAMING, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); diff --git a/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c b/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c index a3342a6bc4e81..dd456d16a6e09 100644 --- a/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c +++ b/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c @@ -135,7 +135,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, for (size_t i = 0U; i < ARRAY_SIZE(streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_CODEC_CONFIGURED, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -170,7 +170,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, for (size_t i = 0U; i < ARRAY_SIZE(streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_QOS_CONFIGURED, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -204,7 +204,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, test_initiator_unicast_stop_disa for (size_t i = 0U; i < ARRAY_SIZE(streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_QOS_CONFIGURED, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -238,7 +238,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, test_initiator_unicast_stop_disa for (size_t i = 0U; i < ARRAY_SIZE(fixture->cap_streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_QOS_CONFIGURED, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -273,7 +273,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, for (size_t i = 0U; i < ARRAY_SIZE(streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = bap_stream->ep->status.state; + const enum bt_bap_ep_state state = bap_stream->ep->state; zassert_equal(state, BT_BAP_EP_STATE_CODEC_CONFIGURED, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -308,7 +308,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, for (size_t i = 0U; i < ARRAY_SIZE(streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = fixture->eps[i].status.state; + const enum bt_bap_ep_state state = fixture->eps[i].state; zassert_equal(state, BT_BAP_EP_STATE_IDLE, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -342,7 +342,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, test_initiator_unicast_stop_rele for (size_t i = 0U; i < ARRAY_SIZE(streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = fixture->eps[i].status.state; + const enum bt_bap_ep_state state = fixture->eps[i].state; zassert_equal(state, BT_BAP_EP_STATE_IDLE, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); @@ -376,7 +376,7 @@ static ZTEST_F(cap_initiator_test_unicast_stop, test_initiator_unicast_stop_rele for (size_t i = 0U; i < ARRAY_SIZE(fixture->cap_streams); i++) { const struct bt_bap_stream *bap_stream = &fixture->cap_streams[i].bap_stream; - const enum bt_bap_ep_state state = fixture->eps[i].status.state; + const enum bt_bap_ep_state state = fixture->eps[i].state; zassert_equal(state, BT_BAP_EP_STATE_IDLE, "[%zu]: Stream %p unexpected state: %d", i, bap_stream, state); diff --git a/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c b/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c index dfc797216d07a..e3d71f931a6a2 100644 --- a/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c +++ b/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c @@ -38,7 +38,7 @@ int bt_bap_unicast_client_config(struct bt_bap_stream *stream, return -EINVAL; } - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_IDLE: case BT_BAP_EP_STATE_CODEC_CONFIGURED: break; @@ -51,7 +51,7 @@ int bt_bap_unicast_client_config(struct bt_bap_stream *stream, BT_BAP_ASCS_REASON_NONE); } - stream->ep->status.state = BT_BAP_EP_STATE_CODEC_CONFIGURED; + stream->ep->state = BT_BAP_EP_STATE_CODEC_CONFIGURED; if (stream->ops != NULL && stream->ops->configured != NULL) { const struct bt_bap_qos_cfg_pref pref = {0}; @@ -72,7 +72,7 @@ int bt_bap_unicast_client_qos(struct bt_conn *conn, struct bt_bap_unicast_group SYS_SLIST_FOR_EACH_CONTAINER(&group->streams, stream, _node) { if (stream->conn == conn) { - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_CODEC_CONFIGURED: case BT_BAP_EP_STATE_QOS_CONFIGURED: break; @@ -89,7 +89,7 @@ int bt_bap_unicast_client_qos(struct bt_conn *conn, struct bt_bap_unicast_group BT_BAP_ASCS_REASON_NONE); } - stream->ep->status.state = BT_BAP_EP_STATE_QOS_CONFIGURED; + stream->ep->state = BT_BAP_EP_STATE_QOS_CONFIGURED; if (stream->ops != NULL && stream->ops->qos_set != NULL) { stream->ops->qos_set(stream); @@ -107,7 +107,7 @@ int bt_bap_unicast_client_enable(struct bt_bap_stream *stream, const uint8_t met return -EINVAL; } - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_QOS_CONFIGURED: break; default: @@ -119,7 +119,7 @@ int bt_bap_unicast_client_enable(struct bt_bap_stream *stream, const uint8_t met BT_BAP_ASCS_REASON_NONE); } - stream->ep->status.state = BT_BAP_EP_STATE_ENABLING; + stream->ep->state = BT_BAP_EP_STATE_ENABLING; if (stream->ops != NULL && stream->ops->enabled != NULL) { stream->ops->enabled(stream); @@ -135,7 +135,7 @@ int bt_bap_unicast_client_metadata(struct bt_bap_stream *stream, const uint8_t m return -EINVAL; } - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_ENABLING: case BT_BAP_EP_STATE_STREAMING: break; @@ -165,7 +165,7 @@ int bt_bap_unicast_client_connect(struct bt_bap_stream *stream) ep = stream->ep; - switch (ep->status.state) { + switch (ep->state) { case BT_BAP_EP_STATE_QOS_CONFIGURED: case BT_BAP_EP_STATE_ENABLING: break; @@ -180,7 +180,7 @@ int bt_bap_unicast_client_connect(struct bt_bap_stream *stream) if (ep->dir == BT_AUDIO_DIR_SINK) { /* Mocking that the unicast server automatically starts the stream */ - ep->status.state = BT_BAP_EP_STATE_STREAMING; + ep->state = BT_BAP_EP_STATE_STREAMING; if (stream->ops != NULL && stream->ops->started != NULL) { stream->ops->started(stream); @@ -197,7 +197,7 @@ int bt_bap_unicast_client_start(struct bt_bap_stream *stream) return -EINVAL; } - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_ENABLING: break; default: @@ -209,7 +209,7 @@ int bt_bap_unicast_client_start(struct bt_bap_stream *stream) BT_BAP_ASCS_REASON_NONE); } - stream->ep->status.state = BT_BAP_EP_STATE_STREAMING; + stream->ep->state = BT_BAP_EP_STATE_STREAMING; if (stream->ops != NULL && stream->ops->started != NULL) { stream->ops->started(stream); @@ -226,7 +226,7 @@ int bt_bap_unicast_client_disable(struct bt_bap_stream *stream) printk("%s %p %d\n", __func__, stream, stream->ep->dir); - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_ENABLING: case BT_BAP_EP_STATE_STREAMING: break; @@ -246,7 +246,7 @@ int bt_bap_unicast_client_disable(struct bt_bap_stream *stream) /* Disabled sink ASEs go directly to the QoS configured state */ if (stream->ep->dir == BT_AUDIO_DIR_SINK) { - stream->ep->status.state = BT_BAP_EP_STATE_QOS_CONFIGURED; + stream->ep->state = BT_BAP_EP_STATE_QOS_CONFIGURED; if (stream->ops != NULL && stream->ops->disabled != NULL) { stream->ops->disabled(stream); @@ -260,7 +260,7 @@ int bt_bap_unicast_client_disable(struct bt_bap_stream *stream) stream->ops->qos_set(stream); } } else if (stream->ep->dir == BT_AUDIO_DIR_SOURCE) { - stream->ep->status.state = BT_BAP_EP_STATE_DISABLING; + stream->ep->state = BT_BAP_EP_STATE_DISABLING; if (stream->ops != NULL && stream->ops->disabled != NULL) { stream->ops->disabled(stream); @@ -279,7 +279,7 @@ int bt_bap_unicast_client_stop(struct bt_bap_stream *stream) return -EINVAL; } - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_DISABLING: break; default: @@ -291,7 +291,7 @@ int bt_bap_unicast_client_stop(struct bt_bap_stream *stream) BT_BAP_ASCS_REASON_NONE); } - stream->ep->status.state = BT_BAP_EP_STATE_QOS_CONFIGURED; + stream->ep->state = BT_BAP_EP_STATE_QOS_CONFIGURED; if (stream->ops != NULL && stream->ops->stopped != NULL) { stream->ops->stopped(stream, BT_HCI_ERR_LOCALHOST_TERM_CONN); @@ -312,7 +312,7 @@ int bt_bap_unicast_client_stop(struct bt_bap_stream *stream) if (pair_ep != NULL && pair_ep->stream != NULL) { struct bt_bap_stream *pair_stream = pair_ep->stream; - pair_stream->ep->status.state = BT_BAP_EP_STATE_QOS_CONFIGURED; + pair_stream->ep->state = BT_BAP_EP_STATE_QOS_CONFIGURED; if (pair_stream->ops != NULL && pair_stream->ops->stopped != NULL) { pair_stream->ops->stopped(pair_stream, @@ -336,7 +336,7 @@ int bt_bap_unicast_client_release(struct bt_bap_stream *stream) return -EINVAL; } - switch (stream->ep->status.state) { + switch (stream->ep->state) { case BT_BAP_EP_STATE_CODEC_CONFIGURED: case BT_BAP_EP_STATE_QOS_CONFIGURED: case BT_BAP_EP_STATE_ENABLING: @@ -352,7 +352,7 @@ int bt_bap_unicast_client_release(struct bt_bap_stream *stream) BT_BAP_ASCS_REASON_NONE); } - stream->ep->status.state = BT_BAP_EP_STATE_IDLE; + stream->ep->state = BT_BAP_EP_STATE_IDLE; bt_bap_stream_reset(stream); if (stream->ops != NULL && stream->ops->released != NULL) { diff --git a/tests/bluetooth/audio/ccp_call_control_server/src/main.c b/tests/bluetooth/audio/ccp_call_control_server/src/main.c index 7ed6c1ef0e192..af09be763bb17 100644 --- a/tests/bluetooth/audio/ccp_call_control_server/src/main.c +++ b/tests/bluetooth/audio/ccp_call_control_server/src/main.c @@ -26,6 +26,8 @@ DEFINE_FFF_GLOBALS; +#define DEFAULT_BEARER_NAME "test" + struct ccp_call_control_server_test_suite_fixture { /** Need 1 additional bearer than the max to trigger some corner cases */ struct bt_ccp_call_control_server_bearer @@ -81,7 +83,7 @@ ZTEST_SUITE(ccp_call_control_server_test_suite, NULL, ccp_call_control_server_te static void register_default_bearer(struct ccp_call_control_server_test_suite_fixture *fixture) { const struct bt_tbs_register_param register_param = { - .provider_name = "test", + .provider_name = DEFAULT_BEARER_NAME, .uci = "un999", .uri_schemes_supported = "tel", .gtbs = true, @@ -262,3 +264,148 @@ static ZTEST_F(ccp_call_control_server_test_suite, err = bt_ccp_call_control_server_unregister_bearer(NULL); zassert_equal(err, -EINVAL, "Unexpected return value %d", err); } + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_set_bearer_provider_name) +{ + const char *new_bearer_name = "New bearer name"; + const char *res_bearer_name; + int err; + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_set_bearer_provider_name(fixture->bearers[0], + new_bearer_name); + zassert_equal(err, 0, "Unexpected return value %d", err); + + err = bt_ccp_call_control_server_get_bearer_provider_name(fixture->bearers[0], + &res_bearer_name); + zassert_equal(err, 0, "Unexpected return value %d", err); + + zassert_str_equal(new_bearer_name, res_bearer_name, "%s != %s", new_bearer_name, + res_bearer_name); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_set_bearer_provider_name_inval_not_registered) +{ + const char *new_bearer_name = "New bearer name"; + int err; + + /* Register and unregister bearer to get a valid pointer but where it is unregistered*/ + register_default_bearer(fixture); + err = bt_ccp_call_control_server_unregister_bearer(fixture->bearers[0]); + zassert_equal(err, 0, "Unexpected return value %d", err); + + err = bt_ccp_call_control_server_set_bearer_provider_name(fixture->bearers[0], + new_bearer_name); + zassert_equal(err, -EFAULT, "Unexpected return value %d", err); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_set_bearer_provider_name_inval_null_bearer) +{ + const char *new_bearer_name = "New bearer name"; + int err; + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_set_bearer_provider_name(NULL, new_bearer_name); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_set_bearer_provider_name_inval_null_name) +{ + int err; + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_set_bearer_provider_name(fixture->bearers[0], NULL); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_set_bearer_provider_name_inval_empty_name) +{ + const char *inval_bearer_name = ""; + int err; + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_set_bearer_provider_name(fixture->bearers[0], + inval_bearer_name); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_set_bearer_provider_name_inval_long_name) +{ + char inval_bearer_name[CONFIG_BT_CCP_CALL_CONTROL_SERVER_PROVIDER_NAME_MAX_LENGTH + 1]; + int err; + + for (size_t i = 0; i < ARRAY_SIZE(inval_bearer_name); i++) { + inval_bearer_name[i] = 'a'; + } + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_set_bearer_provider_name(fixture->bearers[0], + inval_bearer_name); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_get_bearer_provider_name) +{ + const char *res_bearer_name; + int err; + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_get_bearer_provider_name(fixture->bearers[0], + &res_bearer_name); + zassert_equal(err, 0, "Unexpected return value %d", err); + + zassert_str_equal(DEFAULT_BEARER_NAME, res_bearer_name, "%s != %s", DEFAULT_BEARER_NAME, + res_bearer_name); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_get_bearer_provider_name_inval_not_registered) +{ + const char *res_bearer_name; + int err; + + /* Register and unregister bearer to get a valid pointer but where it is unregistered*/ + register_default_bearer(fixture); + err = bt_ccp_call_control_server_unregister_bearer(fixture->bearers[0]); + zassert_equal(err, 0, "Unexpected return value %d", err); + + err = bt_ccp_call_control_server_get_bearer_provider_name(fixture->bearers[0], + &res_bearer_name); + zassert_equal(err, -EFAULT, "Unexpected return value %d", err); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_get_bearer_provider_name_inval_null_bearer) +{ + const char *res_bearer_name; + int err; + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_get_bearer_provider_name(NULL, &res_bearer_name); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} + +static ZTEST_F(ccp_call_control_server_test_suite, + test_bt_ccp_call_control_server_get_bearer_provider_name_inval_null_name) +{ + int err; + + register_default_bearer(fixture); + + err = bt_ccp_call_control_server_get_bearer_provider_name(fixture->bearers[0], NULL); + zassert_equal(err, -EINVAL, "Unexpected return value %d", err); +} diff --git a/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py b/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py index f1f3f627bdb88..9d9184bb5db77 100644 --- a/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py +++ b/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py @@ -542,6 +542,73 @@ async def sdp_ssa_discover_multiple_records(hci_port, shell, dut, address) -> No assert found is True +async def sdp_ssa_discover_multiple_records_with_range(hci_port, shell, dut, address) -> None: + logger.info('<<< SDP Discovery ...') + async with await open_transport_or_link(hci_port) as hci_transport: + device = Device.with_hci( + 'Bumble', + Address('F0:F1:F2:F3:F4:F5'), + hci_transport.source, + hci_transport.sink, + ) + device.classic_enabled = True + device.le_enabled = False + device.sdp_service_records = SDP_SERVICE_MULTIPLE_RECORDS + with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file: + device.host.snooper = BtSnooper(snoop_file) + await device_power_on(device) + await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF)) + + target_address = address.split(" ")[0] + logger.info(f'=== Connecting to {target_address}...') + try: + connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT) + logger.info(f'=== Connected to {connection.peer_address}!') + except Exception as e: + logger.error(f'Fail to connect to {target_address}!') + raise e + + # Discover SDP Record with range SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID ~ + # SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID + shell.exec_command( + f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()} " + f"{SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID} " + f"{SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID}" + ) + found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") + logger.info(f'{lines}') + assert found is True + + # Discover SDP Record with range SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID ~ + # SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID + shell.exec_command( + f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()} " + f"{SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID} " + f"{SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID}" + ) + found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") + logger.info(f'{lines}') + assert found is True + + # Discover SDP Record with range SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID ~ + # 0xffff + shell.exec_command( + f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()} " + f"{SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID} 0xffff" + ) + found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") + logger.info(f'{lines}') + assert found is True + + # Discover SDP Record with range 0xff00 ~ 0xffff + shell.exec_command( + f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()} 0xff00 0xffff" + ) + found, lines = await wait_for_shell_response(dut, "No SDP Record") + logger.info(f'{lines}') + assert found is True + + async def sdp_ss_discover_no_record(hci_port, shell, dut, address) -> None: logger.info('<<< SDP Discovery ...') async with await open_transport_or_link(hci_port) as hci_transport: @@ -889,6 +956,69 @@ async def sdp_sa_discover_multiple_records(hci_port, shell, dut, address) -> Non assert found is True +async def sdp_sa_discover_multiple_records_with_range(hci_port, shell, dut, address) -> None: + logger.info('<<< SDP Discovery ...') + async with await open_transport_or_link(hci_port) as hci_transport: + device = Device.with_hci( + 'Bumble', + Address('F0:F1:F2:F3:F4:F5'), + hci_transport.source, + hci_transport.sink, + ) + device.classic_enabled = True + device.le_enabled = False + device.sdp_service_records = SDP_SERVICE_MULTIPLE_RECORDS + with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file: + device.host.snooper = BtSnooper(snoop_file) + await device_power_on(device) + await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF)) + + target_address = address.split(" ")[0] + logger.info(f'=== Connecting to {target_address}...') + try: + connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT) + logger.info(f'=== Connected to {connection.peer_address}!') + except Exception as e: + logger.error(f'Fail to connect to {target_address}!') + raise e + + # Discover SDP Record with range SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID ~ + # SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID + shell.exec_command( + f"sdp_client sa_discovery 00010003 {SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID} " + f"{SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID}" + ) + found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") + logger.info(f'{lines}') + assert found is True + + # Discover SDP Record with range SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID ~ + # SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID + shell.exec_command( + f"sdp_client sa_discovery 00010003 {SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID} " + f"{SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID}" + ) + found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") + logger.info(f'{lines}') + assert found is True + + # Discover SDP Record with range SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID ~ + # 0xffff + shell.exec_command( + "sdp_client sa_discovery 00010003 " + f"{SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID} 0xffff" + ) + found, lines = await wait_for_shell_response(dut, "SDP Discovery Done") + logger.info(f'{lines}') + assert found is True + + # Discover SDP Record with range 0xff00 ~ 0xffff + shell.exec_command("sdp_client sa_discovery 00010003 0xff00 0xffff") + found, lines = await wait_for_shell_response(dut, "No SDP Record") + logger.info(f'{lines}') + assert found is True + + async def sdp_ssa_discover_fail(hci_port, shell, dut, address) -> None: def on_app_connection_request(self, request) -> None: logger.info('Force L2CAP connection failure') @@ -969,6 +1099,14 @@ def test_sdp_ssa_discover_multiple_records( hci, iut_address = sdp_client_dut asyncio.run(sdp_ssa_discover_multiple_records(hci, shell, dut, iut_address)) + def test_sdp_ssa_discover_multiple_records_with_range( + self, shell: Shell, dut: DeviceAdapter, sdp_client_dut + ): + """Test case to request SDP records with range. Multiple SDP record registered.""" + logger.info(f'test_sdp_ssa_discover_multiple_records_with_range {sdp_client_dut}') + hci, iut_address = sdp_client_dut + asyncio.run(sdp_ssa_discover_multiple_records_with_range(hci, shell, dut, iut_address)) + def test_sdp_ss_discover_no_record(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut): """Test case to request SDP records. No SDP record registered.""" logger.info(f'test_sdp_ss_discover_no_record {sdp_client_dut}') @@ -1021,6 +1159,14 @@ def test_sdp_sa_discover_multiple_records( hci, iut_address = sdp_client_dut asyncio.run(sdp_sa_discover_multiple_records(hci, shell, dut, iut_address)) + def test_sdp_sa_discover_multiple_records_with_range( + self, shell: Shell, dut: DeviceAdapter, sdp_client_dut + ): + """Test case to request SDP records with range. Multiple SDP record registered.""" + logger.info(f'test_sdp_sa_discover_multiple_records_with_range {sdp_client_dut}') + hci, iut_address = sdp_client_dut + asyncio.run(sdp_sa_discover_multiple_records_with_range(hci, shell, dut, iut_address)) + def test_sdp_ssa_discover_fail(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut): """Test case to request SDP records. but the L2CAP connecting fail.""" logger.info(f'test_sdp_ssa_discover_fail {sdp_client_dut}') diff --git a/tests/bluetooth/classic/sdp_c/src/sdp_client.c b/tests/bluetooth/classic/sdp_c/src/sdp_client.c index 71626fc5ca0a9..00df8fcd8332c 100644 --- a/tests/bluetooth/classic/sdp_c/src/sdp_client.c +++ b/tests/bluetooth/classic/sdp_c/src/sdp_client.c @@ -166,9 +166,12 @@ static uint8_t sdp_discover_func(struct bt_conn *conn, struct bt_sdp_client_resu return BT_SDP_DISCOVER_UUID_CONTINUE; } +static struct bt_sdp_attribute_id_list attr_ids; +static struct bt_sdp_attribute_id_range attr_id_ranges[1]; + static int cmd_ssa_discovery(const struct shell *sh, size_t argc, char *argv[]) { - int err; + int err = 0; size_t len; uint8_t uuid128[BT_UUID_SIZE_128]; @@ -198,9 +201,33 @@ static int cmd_ssa_discovery(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } + attr_ids.count = 0; + + if (argc > 2) { + attr_ids.count = ARRAY_SIZE(attr_id_ranges); + attr_ids.ranges = attr_id_ranges; + attr_id_ranges[0].beginning = (uint16_t)shell_strtol(argv[2], 0, &err); + if (err < 0) { + shell_error(sh, "Invalid beginning ATTR ID"); + return -ENOEXEC; + } + attr_id_ranges[0].ending = 0xffff; + } + + if (argc > 3) { + attr_id_ranges[0].ending = (uint16_t)shell_strtol(argv[3], 0, &err); + if (err < 0) { + shell_error(sh, "Invalid ending ATTR ID"); + return -ENOEXEC; + } + } + sdp_discover.func = sdp_discover_func; sdp_discover.pool = &sdp_client_pool; sdp_discover.type = BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR; + if (attr_ids.count != 0) { + sdp_discover.ids = &attr_ids; + } err = bt_sdp_discover(default_conn, &sdp_discover); if (err) { @@ -256,7 +283,7 @@ static int cmd_ss_discovery(const struct shell *sh, size_t argc, char *argv[]) static int cmd_sa_discovery(const struct shell *sh, size_t argc, char *argv[]) { - int err; + int err = 0; size_t len; uint32_t handle; @@ -270,9 +297,33 @@ static int cmd_sa_discovery(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } + attr_ids.count = 0; + + if (argc > 2) { + attr_ids.count = ARRAY_SIZE(attr_id_ranges); + attr_ids.ranges = attr_id_ranges; + attr_id_ranges[0].beginning = (uint16_t)shell_strtol(argv[2], 0, &err); + if (err < 0) { + shell_error(sh, "Invalid beginning ATTR ID"); + return -ENOEXEC; + } + attr_id_ranges[0].ending = 0xffff; + } + + if (argc > 3) { + attr_id_ranges[0].ending = (uint16_t)shell_strtol(argv[3], 0, &err); + if (err < 0) { + shell_error(sh, "Invalid ending ATTR ID"); + return -ENOEXEC; + } + } + sdp_discover.func = sdp_discover_func; sdp_discover.pool = &sdp_client_pool; sdp_discover.type = BT_SDP_DISCOVER_SERVICE_ATTR; + if (attr_ids.count != 0) { + sdp_discover.ids = &attr_ids; + } err = bt_sdp_discover(default_conn, &sdp_discover); if (err) { @@ -311,10 +362,14 @@ static int cmd_ssa_discovery_fail(const struct shell *sh, size_t argc, char *arg return 0; } +#define HELP_ATTR_ID_LIST " [start] [end]" + SHELL_STATIC_SUBCMD_SET_CREATE(sdp_client_cmds, SHELL_CMD_ARG(ss_discovery, NULL, "", cmd_ss_discovery, 2, 0), - SHELL_CMD_ARG(sa_discovery, NULL, "", cmd_sa_discovery, 2, 0), - SHELL_CMD_ARG(ssa_discovery, NULL, "", cmd_ssa_discovery, 2, 0), + SHELL_CMD_ARG(sa_discovery, NULL, "" HELP_ATTR_ID_LIST, + cmd_sa_discovery, 2, 2), + SHELL_CMD_ARG(ssa_discovery, NULL, "" HELP_ATTR_ID_LIST, + cmd_ssa_discovery, 2, 2), SHELL_CMD_ARG(ssa_discovery_fail, NULL, "", cmd_ssa_discovery_fail, 1, 0), SHELL_SUBCMD_SET_END ); diff --git a/tests/bluetooth/controller/common/src/helper_util.c b/tests/bluetooth/controller/common/src/helper_util.c index 5aeca45c90c8f..cac779f9e4e42 100644 --- a/tests/bluetooth/controller/common/src/helper_util.c +++ b/tests/bluetooth/controller/common/src/helper_util.c @@ -314,7 +314,7 @@ void test_set_role(struct ll_conn *conn, uint8_t role) void event_prepare(struct ll_conn *conn) { - struct lll_conn *lll; + struct lll_conn *lll = &conn->lll; uint32_t *evt_active = &(event_active[find_idx(conn)]); /* Can only be called with no active event */ @@ -323,11 +323,13 @@ void event_prepare(struct ll_conn *conn) /*** ULL Prepare ***/ + /* Event counter */ + conn->event_counter = lll->event_counter + lll->latency_prepare; + /* Handle any LL Control Procedures */ ull_cp_run(conn); /*** LLL Prepare ***/ - lll = &conn->lll; /* Save the latency for use in event */ lll->latency_prepare += lll->latency; diff --git a/tests/bluetooth/shell/audio.conf b/tests/bluetooth/shell/audio.conf index 4208bd7a56c99..bae871f97cb2c 100644 --- a/tests/bluetooth/shell/audio.conf +++ b/tests/bluetooth/shell/audio.conf @@ -65,7 +65,7 @@ CONFIG_BT_PER_ADV_SYNC_TRANSFER_SENDER=y # Support an ISO channel per ASE CONFIG_BT_ISO_BROADCASTER=y CONFIG_BT_ISO_PERIPHERAL=y -CONFIG_BT_ISO_MAX_CHAN=4 +CONFIG_BT_ISO_MAX_CHAN=2 CONFIG_BT_ISO_TEST_PARAMS=y CONFIG_BT_ISO_TX_BUF_COUNT=10 CONFIG_BT_ISO_RX_BUF_COUNT=20 @@ -76,7 +76,7 @@ CONFIG_BT_AUDIO=y CONFIG_BT_BAP_UNICAST_SERVER=y CONFIG_BT_BAP_UNICAST_CLIENT=y -CONFIG_BT_BAP_UNICAST_CLIENT_GROUP_STREAM_COUNT=4 +CONFIG_BT_BAP_UNICAST_CLIENT_GROUP_STREAM_COUNT=2 CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT=2 CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT=2 @@ -89,12 +89,12 @@ CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT=2 CONFIG_BT_PAC_SRC=y CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT=2 CONFIG_BT_BAP_BROADCAST_SOURCE=y -CONFIG_BT_BAP_BROADCAST_SRC_SUBGROUP_COUNT=4 -CONFIG_BT_BAP_BROADCAST_SRC_STREAM_COUNT=4 +CONFIG_BT_BAP_BROADCAST_SRC_SUBGROUP_COUNT=1 +CONFIG_BT_BAP_BROADCAST_SRC_STREAM_COUNT=2 CONFIG_BT_BAP_BROADCAST_SINK=y -CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT=2 -CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT=4 +CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT=1 +CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT=2 CONFIG_BT_VOCS_MAX_INSTANCE_COUNT=1 CONFIG_BT_VOCS_CLIENT_MAX_INSTANCE_COUNT=1 @@ -131,11 +131,6 @@ CONFIG_MCTL_REMOTE_PLAYER_CONTROL_OBJECTS=y CONFIG_BT_MPL=y CONFIG_BT_MPL_OBJECTS=y -# TODO Check which value is sensible in the line below -# Must be larger than any of the object sizes - icon, track, group, segments, ... -CONFIG_BT_MPL_MAX_OBJ_SIZE=600 -CONFIG_BT_MPL_ICON_BITMAP_SIZE=321 -CONFIG_BT_MPL_TRACK_MAX_SIZE=50 # Call Control CONFIG_BT_CCP_CALL_CONTROL_SERVER=y @@ -151,20 +146,17 @@ CONFIG_BT_TBS_CLIENT_GTBS=y CONFIG_BT_MCS=y CONFIG_BT_MCC=y CONFIG_BT_MCC_OTS=y -CONFIG_BT_MCC_TOTAL_OBJ_CONTENT_MEM=4096 CONFIG_UTF8=y # Object Transfer CONFIG_BT_OTS=y CONFIG_BT_OTS_SECONDARY_SVC=y -CONFIG_BT_OTS_MAX_OBJ_CNT=0x30 CONFIG_BT_OTS_CLIENT=y CONFIG_BT_BAP_SCAN_DELEGATOR=y -CONFIG_BT_BAP_BASS_MAX_SUBGROUPS=2 -CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE=255 +CONFIG_BT_BAP_BASS_MAX_SUBGROUPS=1 CONFIG_BT_BAP_BROADCAST_ASSISTANT=y -CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT=4 +CONFIG_BT_BAP_BROADCAST_ASSISTANT_RECV_STATE_COUNT=2 # IAS CONFIG_BT_IAS=y @@ -172,7 +164,7 @@ CONFIG_BT_IAS_CLIENT=y CONFIG_BT_HAS=y CONFIG_BT_HAS_PRESET_NAME_DYNAMIC=y -CONFIG_BT_HAS_PRESET_COUNT=4 +CONFIG_BT_HAS_PRESET_COUNT=2 CONFIG_BT_HAS_CLIENT=y CONFIG_BT_HAS_FEATURES_NOTIFIABLE=y @@ -202,44 +194,44 @@ CONFIG_BT_GMAP=y # DEBUGGING CONFIG_LOG=y -CONFIG_BT_AUDIO_LOG_LEVEL_DBG=y -CONFIG_BT_MPL_LOG_LEVEL_DBG=y -CONFIG_BT_MCS_LOG_LEVEL_DBG=y -CONFIG_BT_MCC_LOG_LEVEL_DBG=y -CONFIG_BT_OTS_LOG_LEVEL_DBG=y -CONFIG_BT_OTS_CLIENT_LOG_LEVEL_DBG=y -CONFIG_MCTL_LOG_LEVEL_DBG=y -CONFIG_BT_ASCS_LOG_LEVEL_DBG=y -CONFIG_BT_PACS_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_UNICAST_SERVER_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_UNICAST_CLIENT_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_BROADCAST_SOURCE_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_BROADCAST_SINK_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_BROADCAST_ASSISTANT_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_SCAN_DELEGATOR_LOG_LEVEL_DBG=y -CONFIG_BT_HAS_LOG_LEVEL_DBG=y -CONFIG_BT_HAS_CLIENT_LOG_LEVEL_DBG=y -CONFIG_BT_TBS_LOG_LEVEL_DBG=y -CONFIG_BT_TBS_CLIENT_LOG_LEVEL_DBG=y -CONFIG_BT_VCP_VOL_CTLR_LOG_LEVEL_DBG=y -CONFIG_BT_VCP_VOL_REND_LOG_LEVEL_DBG=y -CONFIG_BT_MICP_MIC_CTLR_LOG_LEVEL_DBG=y -CONFIG_BT_MICP_MIC_DEV_LOG_LEVEL_DBG=y -CONFIG_BT_AICS_CLIENT_LOG_LEVEL_DBG=y -CONFIG_BT_VOCS_CLIENT_LOG_LEVEL_DBG=y -CONFIG_BT_AICS_LOG_LEVEL_DBG=y -CONFIG_BT_VOCS_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_STREAM_LOG_LEVEL_DBG=y -CONFIG_BT_BAP_ISO_LOG_LEVEL_DBG=y -CONFIG_BT_AUDIO_CODEC_LOG_LEVEL_DBG=y -CONFIG_BT_CSIP_SET_COORDINATOR_LOG_LEVEL_DBG=y -CONFIG_BT_CSIP_SET_MEMBER_LOG_LEVEL_DBG=y -CONFIG_BT_CAP_ACCEPTOR_LOG_LEVEL_DBG=y -CONFIG_BT_CAP_INITIATOR_LOG_LEVEL_DBG=y -CONFIG_BT_CAP_COMMANDER_LOG_LEVEL_DBG=y -CONFIG_BT_CAP_COMMON_LOG_LEVEL_DBG=y -CONFIG_BT_TMAP_LOG_LEVEL_DBG=y -CONFIG_BT_GMAP_LOG_LEVEL_DBG=y +# CONFIG_BT_AUDIO_LOG_LEVEL_DBG=y +# CONFIG_BT_AUDIO_CODEC_LOG_LEVEL_DBG=y +# CONFIG_BT_AICS_LOG_LEVEL_DBG=y +# CONFIG_BT_AICS_CLIENT_LOG_LEVEL_DBG=y +# CONFIG_BT_ASCS_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_BROADCAST_SOURCE_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_BROADCAST_SINK_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_BROADCAST_ASSISTANT_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_ISO_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_SCAN_DELEGATOR_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_STREAM_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_UNICAST_SERVER_LOG_LEVEL_DBG=y +# CONFIG_BT_BAP_UNICAST_CLIENT_LOG_LEVEL_DBG=y +# CONFIG_BT_CAP_ACCEPTOR_LOG_LEVEL_DBG=y +# CONFIG_BT_CAP_COMMANDER_LOG_LEVEL_DBG=y +# CONFIG_BT_CAP_COMMON_LOG_LEVEL_DBG=y +# CONFIG_BT_CAP_INITIATOR_LOG_LEVEL_DBG=y +# CONFIG_BT_CSIP_SET_COORDINATOR_LOG_LEVEL_DBG=y +# CONFIG_BT_CSIP_SET_MEMBER_LOG_LEVEL_DBG=y +# CONFIG_BT_GMAP_LOG_LEVEL_DBG=y +# CONFIG_BT_HAS_LOG_LEVEL_DBG=y +# CONFIG_BT_HAS_CLIENT_LOG_LEVEL_DBG=y +# CONFIG_BT_MCS_LOG_LEVEL_DBG=y +# CONFIG_BT_MCC_LOG_LEVEL_DBG=y +# CONFIG_BT_MICP_MIC_CTLR_LOG_LEVEL_DBG=y +# CONFIG_BT_MICP_MIC_DEV_LOG_LEVEL_DBG=y +# CONFIG_BT_MPL_LOG_LEVEL_DBG=y +# CONFIG_BT_OTS_LOG_LEVEL_DBG=y +# CONFIG_BT_OTS_CLIENT_LOG_LEVEL_DBG=y +# CONFIG_BT_PACS_LOG_LEVEL_DBG=y +# CONFIG_BT_TBS_LOG_LEVEL_DBG=y +# CONFIG_BT_TBS_CLIENT_LOG_LEVEL_DBG=y +# CONFIG_BT_TMAP_LOG_LEVEL_DBG=y +# CONFIG_BT_VCP_VOL_CTLR_LOG_LEVEL_DBG=y +# CONFIG_BT_VCP_VOL_REND_LOG_LEVEL_DBG=y +# CONFIG_BT_VOCS_CLIENT_LOG_LEVEL_DBG=y +# CONFIG_BT_VOCS_LOG_LEVEL_DBG=y +# CONFIG_MCTL_LOG_LEVEL_DBG=y # Controller settings CONFIG_BT_CTLR_DATA_LENGTH_MAX=251 diff --git a/tests/bluetooth/shell/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf b/tests/bluetooth/shell/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf index 488baa3f0368d..ba20761468a57 100644 --- a/tests/bluetooth/shell/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf +++ b/tests/bluetooth/shell/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf @@ -4,6 +4,5 @@ CONFIG_LIBLC3=y # For USB audio the following configs are needed CONFIG_RING_BUFFER=y -CONFIG_USB_DEVICE_STACK=y -CONFIG_USB_DEVICE_AUDIO=y -CONFIG_USB_DEVICE_PRODUCT="Zephyr Shell USB" +CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_USBD_AUDIO2_CLASS=y diff --git a/tests/bluetooth/shell/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay b/tests/bluetooth/shell/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay new file mode 100644 index 0000000000000..1d86c97a217d2 --- /dev/null +++ b/tests/bluetooth/shell/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../usb_audio.overlay" diff --git a/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.conf b/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.conf index 488baa3f0368d..ba20761468a57 100644 --- a/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.conf +++ b/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.conf @@ -4,6 +4,5 @@ CONFIG_LIBLC3=y # For USB audio the following configs are needed CONFIG_RING_BUFFER=y -CONFIG_USB_DEVICE_STACK=y -CONFIG_USB_DEVICE_AUDIO=y -CONFIG_USB_DEVICE_PRODUCT="Zephyr Shell USB" +CONFIG_USB_DEVICE_STACK_NEXT=y +CONFIG_USBD_AUDIO2_CLASS=y diff --git a/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.overlay index b8e72f1b61c5b..1d86c97a217d2 100644 --- a/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/tests/bluetooth/shell/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -1,15 +1,7 @@ -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ - hs_0: hs_0 { - compatible = "usb-audio-hs"; - mic-feature-mute; - mic-channel-l; - mic-channel-r; - - hp-feature-mute; - hp-channel-l; - hp-channel-r; - }; -}; +#include "../usb_audio.overlay" diff --git a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay index db86ee4eb9a2e..52011e3c2b559 100644 --- a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay +++ b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay @@ -6,7 +6,8 @@ }; /* Use the PTY driver instead of the UART peripheral emulation that is now the - * default on nrf52_bsim. */ + * default on nrf52_bsim. + */ &uart1 { status = "okay"; diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml index 15f1c8e45409f..399c939b0661e 100644 --- a/tests/bluetooth/shell/testcase.yaml +++ b/tests/bluetooth/shell/testcase.yaml @@ -429,7 +429,7 @@ tests: extra_configs: - CONFIG_RING_BUFFER=n - CONFIG_USB_DEVICE_STACK=n - - CONFIG_USB_DEVICE_AUDIO=n + - CONFIG_USBD_AUDIO2_CLASS=n bluetooth.native_shell: build_only: true extra_args: diff --git a/tests/bluetooth/shell/usb_audio.overlay b/tests/bluetooth/shell/usb_audio.overlay new file mode 100644 index 0000000000000..bf04628dcacf8 --- /dev/null +++ b/tests/bluetooth/shell/usb_audio.overlay @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + uac2_headset: usb_audio2 { + compatible = "zephyr,uac2"; + status = "okay"; + full-speed; + high-speed; + audio-function = ; + + /* Clock supporting 48KHz + * + * Since the incoming audio may be between 8 and 48 KHz, we always upsample to 48KHz + */ + uac_aclk: aclk { + compatible = "zephyr,uac2-clock-source"; + clock-type = "internal-programmable"; + frequency-control = "read-only"; + sampling-frequencies = <48000>; + /* Falsely claim synchronous audio because we + * currently don't calculate feedback value + */ + sof-synchronized; + }; + + /* USB Audio terminal from USB host to USB device */ + out_terminal: out_terminal { + compatible = "zephyr,uac2-input-terminal"; + clock-source = <&uac_aclk>; + terminal-type = ; + front-left; + front-right; + }; + + as_iso_out: out_interface { + compatible = "zephyr,uac2-audio-streaming"; + linked-terminal = <&out_terminal>; + subslot-size = <2>; + bit-resolution = <16>; + }; + + /* USB Audio terminal from USB device to USB host */ + in_terminal: in_terminal { + compatible = "zephyr,uac2-output-terminal"; + data-source = <&bt_input>; + clock-source = <&uac_aclk>; + terminal-type = ; + }; + + as_iso_in: in_interface { + compatible = "zephyr,uac2-audio-streaming"; + linked-terminal = <&in_terminal>; + subslot-size = <2>; + bit-resolution = <16>; + }; + + /* The bt_output terminal defines what we are sending over Bluetooth */ + bt_output: headphones { + compatible = "zephyr,uac2-output-terminal"; + data-source = <&out_terminal>; + clock-source = <&uac_aclk>; + terminal-type = ; + assoc-terminal = <&bt_input>; + }; + + /* The bt_input terminal defines what we are receiving over Bluetooth */ + bt_input: microphone { + compatible = "zephyr,uac2-input-terminal"; + clock-source = <&uac_aclk>; + terminal-type = ; + /* Circular reference, macros will figure it out and + * provide correct associated terminal ID because the + * terminals associations are always 1-to-1. + * + * assoc-terminal = <&bt_output>; + */ + front-left; + front-right; + }; + }; +}; diff --git a/tests/bluetooth/tester/gap_iso.conf b/tests/bluetooth/tester/gap_iso.conf new file mode 100644 index 0000000000000..acc0aad80a4e2 --- /dev/null +++ b/tests/bluetooth/tester/gap_iso.conf @@ -0,0 +1,4 @@ +CONFIG_BT_ISO_BROADCASTER=y +CONFIG_BT_ISO_SYNC_RECEIVER=y +CONFIG_BT_ISO_CENTRAL=y +CONFIG_BT_ISO_PERIPHERAL=y diff --git a/tests/bluetooth/tester/overlay-le-audio.conf b/tests/bluetooth/tester/overlay-le-audio.conf index 4b18c651be275..30f609b9ace5b 100644 --- a/tests/bluetooth/tester/overlay-le-audio.conf +++ b/tests/bluetooth/tester/overlay-le-audio.conf @@ -67,6 +67,7 @@ CONFIG_BT_BAP_SCAN_DELEGATOR=y CONFIG_BT_BAP_BROADCAST_SINK=y CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT=2 CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT=2 +CONFIG_BT_ISO_RX_BUF_COUNT=4 # BASS CONFIG_BT_BAP_BASS_MAX_SUBGROUPS=2 diff --git a/tests/bluetooth/tester/prj.conf b/tests/bluetooth/tester/prj.conf index 863e34d01d758..382ed5eb6cdcd 100644 --- a/tests/bluetooth/tester/prj.conf +++ b/tests/bluetooth/tester/prj.conf @@ -2,6 +2,7 @@ CONFIG_TEST=y CONFIG_UART_PIPE=y CONFIG_UART_CONSOLE=n CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048 +CONFIG_BTTESTER_LOG_LEVEL_DBG=y CONFIG_BT=y CONFIG_BT_CENTRAL=y diff --git a/tests/bluetooth/tester/src/audio/btp/btp_bap.h b/tests/bluetooth/tester/src/audio/btp/btp_bap.h index c0e1470fd415a..90544cdcbd0d0 100644 --- a/tests/bluetooth/tester/src/audio/btp/btp_bap.h +++ b/tests/bluetooth/tester/src/audio/btp/btp_bap.h @@ -11,11 +11,12 @@ #include #include #include +#include /* BAP commands */ #define BTP_BAP_READ_SUPPORTED_COMMANDS 0x01 struct btp_bap_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_BAP_DISCOVER 0x02 @@ -31,7 +32,7 @@ struct btp_bap_send_cmd { bt_addr_le_t address; uint8_t ase_id; uint8_t data_len; - uint8_t data[0]; + uint8_t data[]; } __packed; struct btp_bap_send_rp { @@ -148,7 +149,7 @@ struct btp_bap_add_broadcast_src_cmd { uint8_t padv_sync; uint16_t padv_interval; uint8_t num_subgroups; - uint8_t subgroups[0]; + uint8_t subgroups[]; } __packed; #define BTP_BAP_REMOVE_BROADCAST_SRC 0x15 @@ -164,7 +165,7 @@ struct btp_bap_modify_broadcast_src_cmd { uint8_t padv_sync; uint16_t padv_interval; uint8_t num_subgroups; - uint8_t subgroups[0]; + uint8_t subgroups[]; } __packed; #define BTP_BAP_SET_BROADCAST_CODE 0x17 @@ -287,7 +288,7 @@ struct btp_bap_broadcast_receive_state_ev { uint8_t pa_sync_state; uint8_t big_encryption; uint8_t num_subgroups; - uint8_t subgroups[0]; + uint8_t subgroups[]; } __packed; #define BTP_BAP_EV_PA_SYNC_REQ 0x8a diff --git a/tests/bluetooth/tester/src/audio/btp/btp_cap.h b/tests/bluetooth/tester/src/audio/btp/btp_cap.h index d039bee7dbda0..b59aec900539a 100644 --- a/tests/bluetooth/tester/src/audio/btp/btp_cap.h +++ b/tests/bluetooth/tester/src/audio/btp/btp_cap.h @@ -11,12 +11,13 @@ #include #include #include +#include #include /* CAP commands */ #define BTP_CAP_READ_SUPPORTED_COMMANDS 0x01 struct btp_cap_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_CAP_DISCOVER 0x02 @@ -41,7 +42,7 @@ struct btp_cap_unicast_setup_ase_cmd { uint8_t presentation_delay[3]; uint8_t cc_ltvs_len; uint8_t metadata_ltvs_len; - uint8_t ltvs[0]; + uint8_t ltvs[]; } __packed; #define BTP_CAP_UNICAST_AUDIO_START 0x04 @@ -55,13 +56,13 @@ struct btp_cap_unicast_audio_start_cmd { #define BTP_CAP_UNICAST_AUDIO_UPDATE 0x05 struct btp_cap_unicast_audio_update_cmd { uint8_t stream_count; - uint8_t update_data[0]; + uint8_t update_data[]; } __packed; struct btp_cap_unicast_audio_update_data { bt_addr_le_t address; uint8_t ase_id; uint8_t metadata_ltvs_len; - uint8_t metadata_ltvs[0]; + uint8_t metadata_ltvs[]; } __packed; #define BTP_CAP_UNICAST_AUDIO_STOP 0x06 @@ -80,7 +81,7 @@ struct btp_cap_broadcast_source_setup_stream_cmd { uint16_t cid; uint8_t cc_ltvs_len; uint8_t metadata_ltvs_len; - uint8_t ltvs[0]; + uint8_t ltvs[]; } __packed; #define BTP_CAP_BROADCAST_SOURCE_SETUP_SUBGROUP 0x08 @@ -92,7 +93,7 @@ struct btp_cap_broadcast_source_setup_subgroup_cmd { uint16_t cid; uint8_t cc_ltvs_len; uint8_t metadata_ltvs_len; - uint8_t ltvs[0]; + uint8_t ltvs[]; } __packed; #define BTP_CAP_BROADCAST_SOURCE_SETUP 0x09 @@ -145,7 +146,7 @@ struct btp_cap_broadcast_source_stop_cmd { struct btp_cap_broadcast_source_update_cmd { uint8_t source_id; uint8_t metadata_ltvs_len; - uint8_t metadata_ltvs[0]; + uint8_t metadata_ltvs[]; } __packed; /* CAP events */ diff --git a/tests/bluetooth/tester/src/audio/btp/btp_mcp.h b/tests/bluetooth/tester/src/audio/btp/btp_mcp.h index 77a3b25063be4..0b2cac9fe9e06 100644 --- a/tests/bluetooth/tester/src/audio/btp/btp_mcp.h +++ b/tests/bluetooth/tester/src/audio/btp/btp_mcp.h @@ -11,11 +11,12 @@ #include #include +#include /* MCP commands */ #define BTP_MCP_READ_SUPPORTED_COMMANDS 0x01 struct btp_mcp_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_MCP_DISCOVER 0x02 diff --git a/tests/bluetooth/tester/src/audio/btp/btp_micp.h b/tests/bluetooth/tester/src/audio/btp/btp_micp.h index a480358773471..4992b033768a0 100644 --- a/tests/bluetooth/tester/src/audio/btp/btp_micp.h +++ b/tests/bluetooth/tester/src/audio/btp/btp_micp.h @@ -13,7 +13,7 @@ /* MICP commands */ #define BTP_MICP_READ_SUPPORTED_COMMANDS 0x01 struct btp_micp_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_MICP_CTLR_DISCOVER 0x02 diff --git a/tests/bluetooth/tester/src/audio/btp/btp_pacs.h b/tests/bluetooth/tester/src/audio/btp/btp_pacs.h index e17700581504d..84f0728442ec9 100644 --- a/tests/bluetooth/tester/src/audio/btp/btp_pacs.h +++ b/tests/bluetooth/tester/src/audio/btp/btp_pacs.h @@ -11,7 +11,7 @@ /* PACS commands */ #define BTP_PACS_READ_SUPPORTED_COMMANDS 0x01 struct btp_pacs_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_PACS_CHARACTERISTIC_SINK_PAC 0x01 diff --git a/tests/bluetooth/tester/src/audio/btp_bap_unicast.c b/tests/bluetooth/tester/src/audio/btp_bap_unicast.c index 63eeade5e79fd..e839a0ddb7673 100644 --- a/tests/bluetooth/tester/src/audio/btp_bap_unicast.c +++ b/tests/bluetooth/tester/src/audio/btp_bap_unicast.c @@ -21,7 +21,6 @@ #include #include "ascs_internal.h" -#include "bap_endpoint.h" #include #include #define LOG_MODULE_NAME bttester_bap_unicast @@ -157,13 +156,14 @@ struct bt_bap_ep *btp_bap_unicast_end_point_find(struct btp_bap_unicast_connecti return NULL; } -static void btp_send_ascs_ase_state_changed_ev(struct bt_conn *conn, uint8_t ase_id, uint8_t state) +static void btp_send_ascs_ase_state_changed_ev(struct bt_conn *conn, uint8_t ase_id, + enum bt_bap_ep_state state) { struct btp_ascs_ase_state_changed_ev ev; bt_addr_le_copy(&ev.address, bt_conn_get_dst(conn)); ev.ase_id = ase_id; - ev.state = state; + ev.state = (uint8_t)state; tester_event(BTP_SERVICE_ID_ASCS, BTP_ASCS_EV_ASE_STATE_CHANGED, &ev, sizeof(ev)); } @@ -696,16 +696,20 @@ static void send_stream_received_ev(struct bt_conn *conn, struct bt_bap_ep *ep, uint8_t data_len, uint8_t *data) { struct btp_bap_stream_received_ev *ev; + struct bt_bap_ep_info ep_info; + int err; + + err = bt_bap_ep_get_info(ep, &ep_info); + __ASSERT_NO_MSG(err == 0); tester_rsp_buffer_lock(); tester_rsp_buffer_allocate(sizeof(*ev) + data_len, (uint8_t **)&ev); - LOG_DBG("Stream received, ep %d, dir %d, len %d", ep->status.id, ep->dir, - data_len); + LOG_DBG("Stream received, ep %d, dir %d, len %d", ep_info.id, ep_info.dir, data_len); bt_addr_le_copy(&ev->address, bt_conn_get_dst(conn)); - ev->ase_id = ep->status.id; + ev->ase_id = ep_info.id; ev->data_len = data_len; memcpy(ev->data, data, data_len); @@ -931,7 +935,13 @@ static void unicast_client_endpoint_cb(struct bt_conn *conn, enum bt_audio_dir d LOG_DBG(""); if (ep != NULL) { - LOG_DBG("Discovered ASE %p, id %u, dir 0x%02x", ep, ep->status.id, ep->dir); + struct bt_bap_ep_info ep_info; + int err; + + err = bt_bap_ep_get_info(ep, &ep_info); + __ASSERT_NO_MSG(err == 0); + + LOG_DBG("Discovered ASE %p, id %u, dir 0x%02x", ep, ep_info.id, ep_info.dir); u_conn = &connections[bt_conn_index(conn)]; diff --git a/tests/bluetooth/tester/src/btp.c b/tests/bluetooth/tester/src/btp.c index da8a2826409a7..32165786b4fb8 100644 --- a/tests/bluetooth/tester/src/btp.c +++ b/tests/bluetooth/tester/src/btp.c @@ -111,13 +111,17 @@ static void cmd_handler(void *p1, void *p2, void *p3) if (len > BTP_DATA_MAX_SIZE) { status = BTP_STATUS_FAILED; + LOG_ERR("Data len exceeds BTP MTU %u > %u", len, BTP_DATA_MAX_SIZE); } else if (btp->index != hdr->index) { status = BTP_STATUS_FAILED; + LOG_ERR("Index mismatch %u != %u", btp->index, hdr->index); } else if ((btp->expect_len >= 0) && (btp->expect_len != len)) { status = BTP_STATUS_FAILED; + LOG_ERR("len mismatch %u != %u", btp->expect_len, len); } else { status = btp->func(hdr->data, len, cmd->rsp, &rsp_len); + LOG_DBG("Command returns status %u", status); } /* This means that caller likely overwrote rsp buffer */ diff --git a/tests/bluetooth/tester/src/btp/btp_core.h b/tests/bluetooth/tester/src/btp/btp_core.h index 9b4f1a88d4019..867042084a5d9 100644 --- a/tests/bluetooth/tester/src/btp/btp_core.h +++ b/tests/bluetooth/tester/src/btp/btp_core.h @@ -8,16 +8,17 @@ */ #include +#include /* Core Service */ #define BTP_CORE_READ_SUPPORTED_COMMANDS 0x01 struct btp_core_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_CORE_READ_SUPPORTED_SERVICES 0x02 struct btp_core_read_supported_services_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_CORE_REGISTER_SERVICE 0x03 diff --git a/tests/bluetooth/tester/src/btp/btp_gap.h b/tests/bluetooth/tester/src/btp/btp_gap.h index a4c902553f47c..924859c461c2d 100644 --- a/tests/bluetooth/tester/src/btp/btp_gap.h +++ b/tests/bluetooth/tester/src/btp/btp_gap.h @@ -11,12 +11,14 @@ #include #include +#include +#include /* GAP Service */ /* commands */ #define BTP_GAP_READ_SUPPORTED_COMMANDS 0x01 struct btp_gap_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_GAP_READ_CONTROLLER_INDEX_LIST 0x02 @@ -347,6 +349,45 @@ struct btp_gap_pair_v2_cmd { uint8_t flags; } __packed; +#define BTP_GAP_BIG_CREATE_SYNC_ENC_DISABLE 0x00 +#define BTP_GAP_BIG_CREATE_SYNC_ENC_ENABLE 0x01 + +#define BTP_GAP_BIG_CREATE_SYNC 0x2c +struct btp_gap_big_create_sync_cmd { + bt_addr_le_t address; + uint8_t sid; + uint8_t num_bis; + uint32_t bis_bitfield; + uint32_t mse; + uint16_t sync_timeout; + uint8_t encryption; + uint8_t broadcast_code[]; +} __packed; + +#define BTP_GAP_CREATE_BIG_ENC_DISABLE 0x00 +#define BTP_GAP_CREATE_BIG_ENC_ENABLE 0x01 + +#define BTP_GAP_CREATE_BIG 0x2d +struct btp_gap_create_big_cmd { + uint8_t id; + uint8_t num_bis; + uint32_t interval; + uint16_t latency; + uint8_t rtn; + uint8_t phy; + uint8_t packing; + uint8_t framing; + uint8_t encryption; + uint8_t broadcast_code[]; +} __packed; + +#define BTP_GAP_BIS_BROADCAST 0x2e +struct btp_gap_bis_broadcast_cmd { + uint8_t bis_id; + uint8_t data_len; + uint8_t data[]; +} __packed; + #define BTP_GAP_SET_RPA_TIMEOUT 0x30 struct btp_gap_set_rpa_timeout_cmd { uint16_t rpa_timeout; @@ -480,6 +521,63 @@ struct btp_gap_encryption_change_ev { uint8_t key_size; } __packed; +#define BTP_GAP_EV_BIG_SYNC_ESTABLISHED 0x93 +struct btp_gap_big_sync_established_ev { + bt_addr_le_t address; + uint32_t latency; + uint8_t nse; + uint8_t bn; + uint32_t pto; + uint8_t irc; + uint16_t max_pdu; + uint16_t iso_interval; +} __packed; + +#define BTP_GAP_EV_BIG_SYNC_LOST 0x94 +struct btp_gap_big_sync_lost_ev { + bt_addr_le_t address; + uint8_t reason; +} __packed; + +#define BTP_GAP_EV_BIS_DATA_PATH_SETUP 0x95 +struct btp_gap_bis_data_path_setup_ev { + bt_addr_le_t address; + uint8_t bis_id; +} __packed; + +#define BTP_GAP_EV_BIS_STREAM_RECEIVED 0x96 +struct btp_gap_bis_stream_received_ev { + bt_addr_le_t address; + uint8_t bis_id; + uint8_t flags; + uint32_t ts; + uint16_t seq_num; + uint8_t data_len; + uint8_t data[]; +} __packed; + +#define BTP_GAP_EV_PERIODIC_BIGINFO_ENC_DISABLE 0x00 +#define BTP_GAP_EV_PERIODIC_BIGINFO_ENC_ENABLE 0x01 + +#define BTP_GAP_EV_PERIODIC_BIGINFO 0x97 +struct btp_gap_periodic_biginfo_ev { + bt_addr_le_t address; + uint16_t sync_handle; + uint8_t sid; + uint8_t num_bis; + uint8_t nse; + uint16_t iso_interval; + uint8_t bn; + uint8_t pto; + uint8_t irc; + uint16_t max_pdu; + uint32_t sdu_interval; + uint16_t max_sdu; + uint8_t phy; + uint8_t framing; + uint8_t encryption; +} __packed; + #if defined(CONFIG_BT_EXT_ADV) struct bt_le_per_adv_param; struct bt_le_per_adv_sync_param; diff --git a/tests/bluetooth/tester/src/btp/btp_mesh.h b/tests/bluetooth/tester/src/btp/btp_mesh.h index 7f197e907cdf5..353971261b437 100644 --- a/tests/bluetooth/tester/src/btp/btp_mesh.h +++ b/tests/bluetooth/tester/src/btp/btp_mesh.h @@ -10,13 +10,14 @@ #include #include +#include #include /* MESH Service */ /* commands */ #define BTP_MESH_READ_SUPPORTED_COMMANDS 0x01 struct btp_mesh_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_MESH_OUT_BLINK BIT(0) @@ -156,7 +157,7 @@ struct btp_mesh_comp_data_get_cmd { uint8_t page; } __packed; struct btp_mesh_comp_data_get_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_MESH_CFG_BEACON_GET 0x15 @@ -824,7 +825,7 @@ struct btp_mesh_large_comp_data_get_cmd { uint16_t offset; } __packed; struct btp_mesh_large_comp_data_get_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_MESH_MODELS_METADATA_GET 0x54 @@ -835,7 +836,7 @@ struct btp_mesh_models_metadata_get_cmd { uint16_t offset; } __packed; struct btp_mesh_models_metadata_get_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_MESH_OPCODES_AGGREGATOR_INIT 0x55 diff --git a/tests/bluetooth/tester/src/btp/btp_ots.h b/tests/bluetooth/tester/src/btp/btp_ots.h index be2f2fab48804..54b36cd00bafb 100644 --- a/tests/bluetooth/tester/src/btp/btp_ots.h +++ b/tests/bluetooth/tester/src/btp/btp_ots.h @@ -7,11 +7,12 @@ */ #include +#include /* OTS commands */ #define BTP_OTS_READ_SUPPORTED_COMMANDS 0x01 struct btp_ots_read_supported_commands_rp { - uint8_t data[0]; + FLEXIBLE_ARRAY_DECLARE(uint8_t, data); } __packed; #define BTP_OTS_REGISTER_OBJECT_FLAGS_SKIP_UNSUPPORTED_PROPS 0x01 @@ -23,7 +24,7 @@ struct btp_ots_register_object_cmd { uint32_t alloc_size; uint32_t current_size; uint8_t name_len; - uint8_t name[0]; + uint8_t name[]; } __packed; struct btp_ots_register_object_rp { uint64_t object_id; diff --git a/tests/bluetooth/tester/src/btp_gap.c b/tests/bluetooth/tester/src/btp_gap.c index ad22d1548ce34..1344933eec529 100644 --- a/tests/bluetooth/tester/src/btp_gap.c +++ b/tests/bluetooth/tester/src/btp_gap.c @@ -31,6 +31,7 @@ #include #include +#include #include "btp/btp.h" @@ -830,7 +831,8 @@ int tester_gap_create_adv_instance(struct bt_le_adv_param *param, err = bt_le_ext_adv_create(param, NULL, &ext_adv_sets[index]); if (err != 0) { - return BTP_STATUS_FAILED; + LOG_ERR("Failed to create ext adv(err %d)", err); + return err; } err = bt_le_ext_adv_set_data(ext_adv_sets[index], ad, ad_len, sd_len ? @@ -842,6 +844,8 @@ int tester_gap_create_adv_instance(struct bt_le_adv_param *param, return err; } +static struct bt_le_ext_adv *gap_ext_adv; + static uint8_t start_advertising(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { @@ -895,17 +899,15 @@ static uint8_t start_advertising(const void *cmd, uint16_t cmd_len, i += sd[sd_len].data_len; } - struct bt_le_ext_adv *ext_adv = NULL; - err = tester_gap_create_adv_instance(¶m, own_addr_type, ad, adv_len, sd, - sd_len, NULL, &ext_adv); + sd_len, NULL, &gap_ext_adv); if (err != 0) { return BTP_STATUS_FAILED; } if (IS_ENABLED(CONFIG_BT_EXT_ADV) && atomic_test_bit(¤t_settings, BTP_GAP_SETTINGS_EXTENDED_ADVERTISING)) { - err = bt_le_ext_adv_start(ext_adv, BT_LE_EXT_ADV_START_DEFAULT); + err = bt_le_ext_adv_start(gap_ext_adv, BT_LE_EXT_ADV_START_DEFAULT); } else { err = bt_le_adv_start(¶m, ad, adv_len, sd_len ? sd : NULL, sd_len); } @@ -969,7 +971,13 @@ static uint8_t stop_advertising(const void *cmd, uint16_t cmd_len, struct btp_gap_stop_advertising_rp *rp = rsp; int err; - err = bt_le_adv_stop(); + if (IS_ENABLED(CONFIG_BT_EXT_ADV) && + atomic_test_bit(¤t_settings, BTP_GAP_SETTINGS_EXTENDED_ADVERTISING)) { + err = bt_le_ext_adv_stop(gap_ext_adv); + } else { + err = bt_le_adv_stop(); + } + if (err < 0) { tester_rsp(BTP_SERVICE_ID_GAP, BTP_GAP_STOP_ADVERTISING, BTP_STATUS_FAILED); LOG_ERR("Failed to stop advertising: %d", err); @@ -1859,6 +1867,10 @@ static uint8_t set_extended_advertising(const void *cmd, uint16_t cmd_len, void LOG_DBG("ext adv settings: %u", cp->settings); + if (atomic_test_bit(¤t_settings, BTP_GAP_SETTINGS_ADVERTISING)) { + return BTP_STATUS_FAILED; + } + if (cp->settings != 0) { atomic_set_bit(¤t_settings, BTP_GAP_SETTINGS_EXTENDED_ADVERTISING); } else { @@ -1976,10 +1988,38 @@ static void pa_sync_recv_cb(struct bt_le_per_adv_sync *sync, ev, sizeof(*ev) + ev->data_len); } +static void pa_sync_biginfo_cb(struct bt_le_per_adv_sync *sync, + const struct bt_iso_biginfo *biginfo) +{ + struct btp_gap_periodic_biginfo_ev ev; + + LOG_DBG(""); + + bt_addr_le_copy(&ev.address, biginfo->addr); + ev.sync_handle = sys_cpu_to_le16(sync->handle); + ev.sid = biginfo->sid; + ev.num_bis = biginfo->num_bis; + ev.nse = biginfo->sub_evt_count; + ev.iso_interval = sys_cpu_to_le16(biginfo->iso_interval); + ev.bn = biginfo->burst_number; + ev.pto = biginfo->offset; + ev.irc = biginfo->rep_count; + ev.max_pdu = sys_cpu_to_le16(biginfo->max_pdu); + ev.sdu_interval = sys_cpu_to_le32(biginfo->sdu_interval); + ev.max_sdu = sys_cpu_to_le16(biginfo->max_sdu); + ev.phy = biginfo->phy; + ev.framing = biginfo->framing; + ev.encryption = biginfo->encryption ? BTP_GAP_EV_PERIODIC_BIGINFO_ENC_ENABLE : + BTP_GAP_EV_PERIODIC_BIGINFO_ENC_DISABLE; + + tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PERIODIC_BIGINFO, &ev, sizeof(ev)); +} + static struct bt_le_per_adv_sync_cb pa_sync_cb = { .synced = pa_sync_synced_cb, .term = pa_sync_terminated_cb, .recv = pa_sync_recv_cb, + .biginfo = pa_sync_biginfo_cb, }; #if defined(CONFIG_BT_PER_ADV) @@ -1999,6 +2039,7 @@ int tester_gap_padv_configure(struct bt_le_ext_adv *ext_adv, BTP_GAP_ADDR_TYPE_IDENTITY, ad, 1, NULL, 0, NULL, &ext_adv); if (err != 0) { + LOG_ERR("Failed to create adv instance (err %d)\n", err); return -EINVAL; } } @@ -2008,7 +2049,7 @@ int tester_gap_padv_configure(struct bt_le_ext_adv *ext_adv, */ err = bt_le_per_adv_set_param(ext_adv, param); if (err != 0) { - LOG_DBG("Failed to set periodic advertising parameters (err %d)\n", err); + LOG_ERR("Failed to set periodic advertising parameters (err %d)\n", err); } return err; @@ -2364,6 +2405,432 @@ static uint8_t set_rpa_timeout(const void *cmd, uint16_t cmd_len, void *rsp, uin } #endif /* defined(CONFIG_BT_RPA_TIMEOUT_DYNAMIC) */ +#if defined(CONFIG_BT_ISO_SYNC_RECEIVER) || defined(CONFIG_BT_ISO_BROADCASTER) +static int bt_iso_chan_get_index(struct bt_iso_chan *chan); +#endif /* defined(CONFIG_BT_ISO_SYNC_RECEIVER) || defined(CONFIG_BT_ISO_BROADCASTER) */ + +#if defined(CONFIG_BT_ISO_SYNC_RECEIVER) +static struct bt_iso_big *iso_sync_receiver_big; + +static void iso_sync_receiver_big_started_cb(struct bt_iso_big *big) +{ + __maybe_unused struct btp_gap_big_sync_established_ev ev; + struct bt_iso_info info; + struct bt_iso_chan *bis; + bool found = false; + + if (big != iso_sync_receiver_big) { + return; + } + + SYS_SLIST_FOR_EACH_CONTAINER(&big->bis_channels, bis, node) { + int err = bt_iso_chan_get_info(bis, &info); + + if (err != 0) { + LOG_DBG("Failed to get ISO chan info: %d", err); + continue; + } + + if (info.type != BT_ISO_CHAN_TYPE_SYNC_RECEIVER) { + continue; + } + + found = true; + break; + } + + __ASSERT(found, "Failed to find the valid ISO info"); + + if (!found) { + LOG_ERR("Failed to find the valid ISO info"); + return; + } + + bt_addr_le_copy(&ev.address, &pa_sync->addr); + ev.latency = sys_cpu_to_le32(info.sync_receiver.latency); + ev.nse = info.max_subevent; + ev.bn = info.sync_receiver.bn; + ev.pto = sys_cpu_to_le32(info.sync_receiver.pto); + ev.irc = info.sync_receiver.irc; + ev.max_pdu = sys_cpu_to_le16(info.sync_receiver.max_pdu); + ev.iso_interval = sys_cpu_to_le16(info.iso_interval); + + tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIG_SYNC_ESTABLISHED, &ev, sizeof(ev)); +} + +static void iso_sync_receiver_big_stopped_cb(struct bt_iso_big *big, uint8_t reason) +{ + struct btp_gap_big_sync_lost_ev ev; + + if (big != iso_sync_receiver_big) { + return; + } + + bt_addr_le_copy(&ev.address, &pa_sync->addr); + ev.reason = reason; + + tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIG_SYNC_LOST, &ev, sizeof(ev)); + + iso_sync_receiver_big = NULL; +} + +static struct bt_iso_big_cb iso_sync_receiver_big_cb = { + .started = iso_sync_receiver_big_started_cb, + .stopped = iso_sync_receiver_big_stopped_cb, +}; + +#define BIS_STREAM_DATA_LEN (CONFIG_BT_ISO_RX_MTU + \ + sizeof(struct btp_gap_bis_stream_received_ev)) + +BUILD_ASSERT(BIS_STREAM_DATA_LEN < BTP_DATA_MAX_SIZE, "BIS stream data length exceeds BTP MTU"); + +static struct net_buf_simple *iso_sync_receiver_buf = NET_BUF_SIMPLE(BIS_STREAM_DATA_LEN); + +static void iso_sync_receiver_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *info, + struct net_buf *buf) +{ + struct btp_gap_bis_stream_received_ev *ev; + int err; + + if (pa_sync == NULL) { + return; + } + + err = bt_iso_chan_get_index(chan); + if (err < 0) { + LOG_ERR("Failed to get BIS channel index: %d", err); + return; + } + + /* cleanup */ + net_buf_simple_init(iso_sync_receiver_buf, 0); + + ev = net_buf_simple_add(iso_sync_receiver_buf, sizeof(*ev)); + + __ASSERT(buf->len <= net_buf_simple_tailroom(iso_sync_receiver_buf), "No more tailroom"); + + bt_addr_le_copy(&ev->address, &pa_sync->addr); + ev->bis_id = (uint8_t)err; + ev->data_len = buf->len; + ev->flags = info->flags; + ev->ts = sys_cpu_to_le32(info->ts); + ev->seq_num = sys_cpu_to_le16(info->seq_num); + net_buf_simple_add_mem(iso_sync_receiver_buf, buf->data, ev->data_len); + + tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIS_STREAM_RECEIVED, + iso_sync_receiver_buf->data, iso_sync_receiver_buf->len); +} + +static void iso_sync_receiver_connected(struct bt_iso_chan *chan) +{ + const struct bt_iso_chan_path hci_path = { + .pid = BT_ISO_DATA_PATH_HCI, + .format = BT_HCI_CODING_FORMAT_TRANSPARENT, + }; + int err; + struct btp_gap_bis_data_path_setup_ev ev; + + if (pa_sync == NULL) { + return; + } + + err = bt_iso_chan_get_index(chan); + if (err < 0) { + LOG_ERR("Failed to get BIS channel index: %d", err); + return; + } + ev.bis_id = (uint8_t)err; + + err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path); + if (err != 0) { + LOG_ERR("Failed to setup ISO RX data path: %d", err); + return; + } + + bt_addr_le_copy(&ev.address, &pa_sync->addr); + + tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIS_DATA_PATH_SETUP, &ev, sizeof(ev)); +} + +static void iso_sync_receiver_disconnected(struct bt_iso_chan *chan, uint8_t reason) +{ + int err; + + err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST); + if (err != 0) { + LOG_ERR("Failed to remove ISO RX data path: %d", err); + } +} + +static struct bt_iso_chan_ops iso_sync_receiver_ops = { + .recv = iso_sync_receiver_recv, + .connected = iso_sync_receiver_connected, + .disconnected = iso_sync_receiver_disconnected, +}; +#endif /* defined(CONFIG_BT_ISO_SYNC_RECEIVER) */ + +#if defined(CONFIG_BT_ISO_BROADCASTER) +static uint32_t bis_sn_last; +static int64_t bis_sn_last_updated_ticks; +static uint32_t bis_sdu_interval_us; + +static void iso_broadcaster_connected(struct bt_iso_chan *chan) +{ + int err; + const struct bt_iso_chan_path hci_path = { + .pid = BT_ISO_DATA_PATH_HCI, + .format = BT_HCI_CODING_FORMAT_TRANSPARENT, + }; + struct btp_gap_bis_data_path_setup_ev ev; + struct bt_le_ext_adv *ext_adv = tester_gap_ext_adv_get(0); + + err = bt_iso_chan_get_index(chan); + if (err < 0) { + LOG_ERR("Failed to get BIS channel index: %d", err); + return; + } + ev.bis_id = (uint8_t)err; + + bis_sn_last = 0; + bis_sn_last_updated_ticks = k_uptime_ticks(); + + err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path); + if (err != 0) { + LOG_ERR("Failed to setup ISO TX data path: %d", err); + return; + } + + bt_addr_le_copy(&ev.address, &ext_adv->random_addr); + + tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIS_DATA_PATH_SETUP, &ev, sizeof(ev)); +} + +static void iso_broadcaster_disconnected(struct bt_iso_chan *chan, uint8_t reason) +{ + ARG_UNUSED(chan); + ARG_UNUSED(reason); +} + +static struct bt_iso_chan_ops iso_broadcaster_ops = { + .connected = iso_broadcaster_connected, + .disconnected = iso_broadcaster_disconnected, +}; +#endif /* defined(CONFIG_BT_ISO_BROADCASTER) */ + +#if defined(CONFIG_BT_ISO_SYNC_RECEIVER) || defined(CONFIG_BT_ISO_BROADCASTER) +static struct bt_iso_chan_qos bis_iso_qos; + +static struct bt_iso_chan bis_iso_chan = { + .qos = &bis_iso_qos, +}; + +#define DEFAULT_IO_QOS {.sdu = 40u, .phy = BT_GAP_LE_PHY_2M, .rtn = 2u,} + +#define BIS_ISO_CHAN_COUNT 1 + +static struct bt_iso_chan *bis_channels[BIS_ISO_CHAN_COUNT] = { &bis_iso_chan }; + +static int bt_iso_chan_get_index(struct bt_iso_chan *chan) +{ + ARRAY_FOR_EACH(bis_channels, index) { + if (bis_channels[index] == chan) { + return (int)index; + } + } + return -EINVAL; +} +#endif /* defined(CONFIG_BT_ISO_SYNC_RECEIVER) || defined(CONFIG_BT_ISO_BROADCASTER) */ + +#if defined(CONFIG_BT_ISO_SYNC_RECEIVER) +static struct bt_iso_chan_io_qos iso_sync_receiver_qos = DEFAULT_IO_QOS; + +static uint8_t big_create_sync(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) +{ + int err; + const struct btp_gap_big_create_sync_cmd *cp = cmd; + struct bt_iso_big_sync_param param; + + if ((cmd_len < sizeof(*cp)) || + (cmd_len != (sizeof(*cp) + sizeof(param.bcode) * cp->encryption))) { + LOG_ERR("Invalid cmd len"); + return BTP_STATUS_FAILED; + } + + if (!(cp->encryption == BTP_GAP_BIG_CREATE_SYNC_ENC_DISABLE || + cp->encryption == BTP_GAP_BIG_CREATE_SYNC_ENC_ENABLE)) { + LOG_ERR("Invalid encryption %u", cp->encryption); + return BTP_STATUS_FAILED; + } + + if ((pa_sync == NULL) || !bt_addr_le_eq(&cp->address, &pa_sync->addr) || + (cp->sid != pa_sync->sid)) { + LOG_ERR("Invalid PA sync or SID"); + return BTP_STATUS_FAILED; + } + + if (cp->num_bis > ARRAY_SIZE(bis_channels)) { + LOG_ERR("BIS num exceeds %u > %u", cp->num_bis, ARRAY_SIZE(bis_channels)); + return BTP_STATUS_FAILED; + } + + bis_iso_qos.tx = NULL; + bis_iso_qos.rx = &iso_sync_receiver_qos; + + bis_iso_chan.ops = &iso_sync_receiver_ops; + + param.bis_channels = bis_channels; + param.num_bis = cp->num_bis; + param.bis_bitfield = sys_le32_to_cpu(cp->bis_bitfield); + param.mse = sys_le32_to_cpu(cp->mse); + param.sync_timeout = sys_le16_to_cpu(cp->sync_timeout); + param.encryption = cp->encryption == BTP_GAP_BIG_CREATE_SYNC_ENC_ENABLE; + if (param.encryption) { + memcpy(param.bcode, cp->broadcast_code, sizeof(param.bcode)); + } + + err = bt_iso_big_sync(pa_sync, ¶m, &iso_sync_receiver_big); + if (err != 0) { + LOG_ERR("Unable to sync to BIG (err %d)", err); + return BTP_STATUS_FAILED; + } + + LOG_DBG("BIG syncing"); + + return BTP_STATUS_SUCCESS; +} +#endif /* defined(CONFIG_BT_ISO_SYNC_RECEIVER) */ + +#if defined(CONFIG_BT_ISO_BROADCASTER) +static struct bt_iso_chan_io_qos iso_broadcaster_qos = DEFAULT_IO_QOS; + +static struct bt_iso_big *iso_broadcaster_big; + +static uint8_t create_big(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) +{ + int err; + const struct btp_gap_create_big_cmd *cp = cmd; + struct bt_iso_big_create_param param = {0}; + struct bt_le_ext_adv *ext_adv = tester_gap_ext_adv_get(0); + + if ((cmd_len < sizeof(*cp)) || + (cmd_len != (sizeof(*cp) + sizeof(param.bcode) * cp->encryption))) { + LOG_ERR("Invalid cmd len"); + return BTP_STATUS_FAILED; + } + + if (!(cp->encryption == BTP_GAP_CREATE_BIG_ENC_DISABLE || + cp->encryption == BTP_GAP_CREATE_BIG_ENC_ENABLE)) { + LOG_ERR("Invalid encryption %u", cp->encryption); + return BTP_STATUS_FAILED; + } + + if ((ext_adv == NULL) || (cp->id != ext_adv->id)) { + LOG_ERR("Invalid extended adv"); + return BTP_STATUS_FAILED; + } + + if (cp->num_bis > ARRAY_SIZE(bis_channels)) { + LOG_ERR("BIS num exceeds %u > %u", cp->num_bis, ARRAY_SIZE(bis_channels)); + return BTP_STATUS_FAILED; + } + + bis_iso_qos.rx = NULL; + bis_iso_qos.tx = &iso_broadcaster_qos; + bis_iso_qos.tx->phy = cp->phy; + bis_iso_qos.tx->rtn = cp->rtn; + bis_iso_qos.tx->sdu = CONFIG_BT_ISO_TX_MTU; + + bis_iso_chan.ops = &iso_broadcaster_ops; + + param.bis_channels = bis_channels; + param.num_bis = cp->num_bis; + param.interval = sys_le32_to_cpu(cp->interval); + param.packing = cp->packing; + param.framing = cp->framing; + param.latency = sys_le16_to_cpu(cp->latency); + + param.encryption = cp->encryption == BTP_GAP_CREATE_BIG_ENC_ENABLE; + if (param.encryption) { + memcpy(param.bcode, cp->broadcast_code, sizeof(param.bcode)); + } + + bis_sdu_interval_us = param.interval; + + err = bt_iso_big_create(ext_adv, ¶m, &iso_broadcaster_big); + if (err != 0) { + LOG_ERR("Unable to create BIG (err %d)", err); + return BTP_STATUS_FAILED; + } + + LOG_DBG("BIG created"); + + return BTP_STATUS_SUCCESS; +} + +NET_BUF_POOL_FIXED_DEFINE(bis_tx_pool, BIS_ISO_CHAN_COUNT, + BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_TX_MTU), + CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL); + +static uint32_t get_next_sn(uint32_t last_sn, int64_t *last_ticks, + uint32_t interval_us) +{ + int64_t uptime_ticks, delta_ticks; + uint64_t delta_us; + uint64_t sn_incr; + uint64_t next_sn; + + /* Note: This does not handle wrapping of ticks when they go above + * 2^(62-1) + */ + uptime_ticks = k_uptime_ticks(); + delta_ticks = uptime_ticks - *last_ticks; + *last_ticks = uptime_ticks; + + delta_us = k_ticks_to_us_near64((uint64_t)delta_ticks); + sn_incr = delta_us / interval_us; + next_sn = (sn_incr + last_sn); + + return (uint32_t)next_sn; +} + +static uint8_t bis_broadcast(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) +{ + int err; + const struct btp_gap_bis_broadcast_cmd *cp = cmd; + struct net_buf *buf; + + buf = net_buf_alloc(&bis_tx_pool, K_NO_WAIT); + if (buf == NULL) { + LOG_ERR("Failed to allocate buffer"); + return BTP_STATUS_FAILED; + } + + net_buf_reserve(buf, BT_ISO_CHAN_SEND_RESERVE); + + if (cp->data_len > net_buf_tailroom(buf)) { + net_buf_unref(buf); + LOG_ERR("Data length exceeds buffer tailroom"); + return BTP_STATUS_FAILED; + } + + bis_sn_last = get_next_sn(bis_sn_last, &bis_sn_last_updated_ticks, + bis_sdu_interval_us); + + net_buf_add_mem(buf, cp->data, cp->data_len); + + err = bt_iso_chan_send(&bis_iso_chan, buf, bis_sn_last); + if (err < 0) { + LOG_ERR("Unable to broadcast: %d", -err); + net_buf_unref(buf); + return BTP_STATUS_FAILED; + } + + LOG_DBG("ISO broadcasting..., sn %u len %u", bis_sn_last, cp->data_len); + + return BTP_STATUS_SUCCESS; +} +#endif /* defined(CONFIG_BT_ISO_BROADCASTER) */ + static const struct btp_handler handlers[] = { { .opcode = BTP_GAP_READ_SUPPORTED_COMMANDS, @@ -2559,6 +3026,25 @@ static const struct btp_handler handlers[] = { .func = set_rpa_timeout, }, #endif /* defined(CONFIG_BT_RPA_TIMEOUT_DYNAMIC) */ +#if defined(CONFIG_BT_ISO_SYNC_RECEIVER) + { + .opcode = BTP_GAP_BIG_CREATE_SYNC, + .expect_len = BTP_HANDLER_LENGTH_VARIABLE, + .func = big_create_sync, + }, +#endif /* defined(CONFIG_BT_ISO_SYNC_RECEIVER) */ +#if defined(CONFIG_BT_ISO_BROADCASTER) + { + .opcode = BTP_GAP_CREATE_BIG, + .expect_len = BTP_HANDLER_LENGTH_VARIABLE, + .func = create_big, + }, + { + .opcode = BTP_GAP_BIS_BROADCAST, + .expect_len = BTP_HANDLER_LENGTH_VARIABLE, + .func = bis_broadcast, + }, +#endif /* defined(CONFIG_BT_ISO_BROADCASTER) */ }; uint8_t tester_init_gap(void) @@ -2594,6 +3080,10 @@ uint8_t tester_init_gap(void) bt_le_per_adv_sync_cb_register(&pa_sync_cb); } +#if defined(CONFIG_BT_ISO_SYNC_RECEIVER) + bt_iso_big_register_cb(&iso_sync_receiver_big_cb); +#endif /* CONFIG_BT_ISO_SYNC_RECEIVER */ + tester_register_command_handlers(BTP_SERVICE_ID_GAP, handlers, ARRAY_SIZE(handlers)); diff --git a/tests/bluetooth/tester/testcase.yaml b/tests/bluetooth/tester/testcase.yaml index 9d3f7f758ccf6..8f6cd0b98be70 100644 --- a/tests/bluetooth/tester/testcase.yaml +++ b/tests/bluetooth/tester/testcase.yaml @@ -45,6 +45,8 @@ tests: harness: bsim harness_config: bsim_exe_name: tests_bluetooth_tester_prj_conf + extra_args: + - EXTRA_CONF_FILE="gap_iso.conf" sysbuild: true bluetooth.general.tester_le_audio: build_only: true diff --git a/tests/boards/espressif/rtc_clk/src/rtc_clk_test.c b/tests/boards/espressif/rtc_clk/src/rtc_clk_test.c index 41071af768f7e..6933849e3942f 100644 --- a/tests/boards/espressif/rtc_clk/src/rtc_clk_test.c +++ b/tests/boards/espressif/rtc_clk/src/rtc_clk_test.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,8 +15,7 @@ #define DT_CPU_COMPAT espressif_xtensa_lx6 #elif defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32S3) #define DT_CPU_COMPAT espressif_xtensa_lx7 -#elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || \ - defined(CONFIG_SOC_SERIES_ESP32C6) +#elif defined(CONFIG_RISCV) #define DT_CPU_COMPAT espressif_riscv #endif @@ -74,14 +73,22 @@ ZTEST(rtc_clk, test_cpu_xtal_src) } uint32_t rtc_pll_src_freq_mhz[] = { +#if defined(ESP32_CLK_CPU_PLL_48M) + ESP32_CLK_CPU_PLL_48M, +#endif +#if defined(ESP32_CLK_CPU_PLL_80M) ESP32_CLK_CPU_PLL_80M, -#if defined(CONFIG_SOC_SERIES_ESP32C2) +#endif +#if defined(ESP32_CLK_CPU_PLL_96M) + ESP32_CLK_CPU_PLL_96M, +#endif +#if defined(ESP32_CLK_CPU_PLL_120M) ESP32_CLK_CPU_PLL_120M, -#else +#endif +#if defined(ESP32_CLK_CPU_PLL_160M) ESP32_CLK_CPU_PLL_160M, #endif -#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) && \ - !defined(CONFIG_SOC_SERIES_ESP32C6) +#if defined(ESP32_CLK_CPU_PLL_240M) ESP32_CLK_CPU_PLL_240M, #endif }; @@ -159,10 +166,13 @@ ZTEST(rtc_clk, test_rtc_fast_src) } uint32_t rtc_rtc_slow_clk_src[] = { +#if defined(ESP32_RTC_SLOW_CLK_SRC_RC_SLOW) ESP32_RTC_SLOW_CLK_SRC_RC_SLOW, -#if defined(CONFIG_SOC_SERIES_ESP32C6) +#endif +#if defined(ESP32_RTC_SLOW_CLK_SRC_RC32K) ESP32_RTC_SLOW_CLK_SRC_RC32K, -#else +#endif +#if defined(ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256) ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256, #endif #if CONFIG_FIXTURE_XTAL @@ -171,10 +181,13 @@ uint32_t rtc_rtc_slow_clk_src[] = { }; uint32_t rtc_rtc_slow_clk_src_freq[] = { +#if defined(ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ) ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ, -#if defined(CONFIG_SOC_SERIES_ESP32C6) +#endif +#if defined(ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ) ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ, -#else +#endif +#if defined(ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ) ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ, #endif #if CONFIG_FIXTURE_XTAL diff --git a/tests/boards/espressif/rtc_clk/testcase.yaml b/tests/boards/espressif/rtc_clk/testcase.yaml index 1090148d4661f..3cbc65b01b604 100644 --- a/tests/boards/espressif/rtc_clk/testcase.yaml +++ b/tests/boards/espressif/rtc_clk/testcase.yaml @@ -7,6 +7,7 @@ tests: - esp32_devkitc/esp32/procpu - esp32c3_devkitm - esp32c6_devkitc/esp32c6/hpcore + - esp32h2_devkitm - esp32s2_saola - esp32s3_devkitm/esp32s3/procpu boards.esp32.rtc_clk.xtal: diff --git a/tests/boards/mec15xxevb_assy6853/qspi/boards/mec15xxevb_assy6853.overlay b/tests/boards/mec15xxevb_assy6853/qspi/boards/mec15xxevb_assy6853.overlay index d85b70f4f7a80..44c427e4888bb 100644 --- a/tests/boards/mec15xxevb_assy6853/qspi/boards/mec15xxevb_assy6853.overlay +++ b/tests/boards/mec15xxevb_assy6853/qspi/boards/mec15xxevb_assy6853.overlay @@ -10,10 +10,10 @@ chip-select = <0>; lines = <4>; - pinctrl-0 = < &shd_cs0_n_gpio055 - &shd_clk_gpio056 - &shd_io0_gpio223 - &shd_io1_gpio224 - &shd_io2_gpio227 - &shd_io3_gpio016 >; + pinctrl-0 = <&shd_cs0_n_gpio055 + &shd_clk_gpio056 + &shd_io0_gpio223 + &shd_io1_gpio224 + &shd_io2_gpio227 + &shd_io3_gpio016>; }; diff --git a/tests/boards/mec172xevb_assy6906/qspi/boards/mec172xevb_assy6906.overlay b/tests/boards/mec172xevb_assy6906/qspi/boards/mec172xevb_assy6906.overlay index 09711ac84d254..b5f2fca8c90b9 100644 --- a/tests/boards/mec172xevb_assy6906/qspi/boards/mec172xevb_assy6906.overlay +++ b/tests/boards/mec172xevb_assy6906/qspi/boards/mec172xevb_assy6906.overlay @@ -9,10 +9,10 @@ chip-select = <0>; lines = <4>; - pinctrl-0 = < &shd_cs0_n_gpio055 - &shd_clk_gpio056 - &shd_io0_gpio223 - &shd_io1_gpio224 - &shd_io2_gpio227 - &shd_io3_gpio016 >; + pinctrl-0 = <&shd_cs0_n_gpio055 + &shd_clk_gpio056 + &shd_io0_gpio223 + &shd_io1_gpio224 + &shd_io2_gpio227 + &shd_io3_gpio016>; }; diff --git a/tests/boards/nrf/comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index 76cb1918038ee..aaf1006300a54 100644 --- a/tests/boards/nrf/comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/tests/boards/nrf/comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -32,7 +32,7 @@ status = "okay"; psel = "AIN4"; refsel = "AREF"; - extrefsel= "AIN3"; + extrefsel = "AIN3"; sp-mode = "NORMAL"; th-up = <36>; th-down = <30>; diff --git a/tests/boards/nrf/comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index 76cb1918038ee..aaf1006300a54 100644 --- a/tests/boards/nrf/comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/tests/boards/nrf/comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -32,7 +32,7 @@ status = "okay"; psel = "AIN4"; refsel = "AREF"; - extrefsel= "AIN3"; + extrefsel = "AIN3"; sp-mode = "NORMAL"; th-up = <36>; th-down = <30>; diff --git a/tests/boards/nrf/comp/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/comp/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index cb8e9d408b886..4e9e898ea1840 100644 --- a/tests/boards/nrf/comp/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/boards/nrf/comp/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -27,7 +27,7 @@ status = "okay"; psel = "AIN5"; refsel = "AREF"; - extrefsel= "AIN1"; + extrefsel = "AIN1"; sp-mode = "HIGH"; th-up = <36>; th-down = <30>; diff --git a/tests/boards/nrf/comp/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/comp/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index 4c9944b81c394..d6492e37c343a 100644 --- a/tests/boards/nrf/comp/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/boards/nrf/comp/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -31,7 +31,7 @@ status = "okay"; psel = "AIN4"; refsel = "AREF"; - extrefsel= "AIN3"; + extrefsel = "AIN3"; sp-mode = "NORMAL"; th-up = <36>; th-down = <30>; diff --git a/tests/boards/nrf/comp/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay b/tests/boards/nrf/comp/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay index 55d1937a4fee1..45cefc0815bb9 100644 --- a/tests/boards/nrf/comp/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay +++ b/tests/boards/nrf/comp/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay @@ -24,7 +24,7 @@ status = "okay"; psel = "AIN4"; refsel = "AREF"; - extrefsel= "AIN3"; + extrefsel = "AIN3"; sp-mode = "NORMAL"; th-up = <36>; th-down = <30>; diff --git a/tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay index 9d2eceba6678a..3e0b1b4d5356f 100644 --- a/tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -1,7 +1,7 @@ / { aliases { dut-cache = &spi1; - dut-nocache= &spi3; + dut-nocache = &spi3; }; }; @@ -37,8 +37,7 @@ }; }; -&spi1 -{ +&spi1 { compatible = "nordic,nrf-spim"; status = "okay"; pinctrl-0 = <&spi1_default_alt>; @@ -46,8 +45,7 @@ pinctrl-names = "default", "sleep"; }; -&spi3 -{ +&spi3 { compatible = "nordic,nrf-spim"; status = "okay"; pinctrl-0 = <&spi3_default_alt>; diff --git a/tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 39ec122b32fac..e3924657b86eb 100644 --- a/tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -37,8 +37,7 @@ }; }; -&spi130 -{ +&spi130 { compatible = "nordic,nrf-spim"; status = "okay"; pinctrl-0 = <&spi130_default_alt>; @@ -51,8 +50,7 @@ status = "okay"; }; -&spi120 -{ +&spi120 { compatible = "nordic,nrf-spim"; status = "okay"; pinctrl-0 = <&spi120_default_alt>; diff --git a/tests/boards/nrf/hwinfo/reset_cause/src/main.c b/tests/boards/nrf/hwinfo/reset_cause/src/main.c index 150a77da7d971..7df98bce9bc1e 100644 --- a/tests/boards/nrf/hwinfo/reset_cause/src/main.c +++ b/tests/boards/nrf/hwinfo/reset_cause/src/main.c @@ -297,7 +297,7 @@ void test_reset_watchdog(uint32_t cause) /* Flush cache as reboot may invalidate all lines. */ sys_cache_data_flush_range((void *) &machine_state, sizeof(machine_state)); - LOG_INF("Watchdog shall fire in ~%u miliseconds", watchdog_window); + LOG_INF("Watchdog shall fire in ~%u milliseconds", watchdog_window); print_bar(); k_sleep(K_FOREVER); } else { diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index b799dfe3366ed..89bda0720c298 100644 --- a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -28,9 +28,9 @@ i2c22_default_alt: i2c22_default_alt { group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. - */ + /* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. + */ psels = , ; bias-pull-up; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index b799dfe3366ed..89bda0720c298 100644 --- a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -28,9 +28,9 @@ i2c22_default_alt: i2c22_default_alt { group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. - */ + /* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. + */ psels = , ; bias-pull-up; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay index 121ac01b7a7d2..cb4debaa7e3c1 100644 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf52840dk_nrf52840.overlay @@ -49,7 +49,6 @@ dut_twim: &i2c0 { }; }; - dut_twis: &i2c1 { compatible = "nordic,nrf-twis"; status = "okay"; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 51d06377789e2..444db89627d2d 100644 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -22,8 +22,9 @@ i2c131_default_alt: i2c131_default_alt { group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. */ + /* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. + */ psels = , ; bias-pull-up; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuppr.overlay index 39220e934b391..fbfb1e55772d6 100644 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuppr.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuppr.overlay @@ -22,9 +22,9 @@ i2c131_default_alt: i2c131_default_alt { group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. - */ + /* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. + */ psels = , ; bias-pull-up; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index dd580fac4ec57..feaec96977c7f 100644 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -22,9 +22,9 @@ i2c22_default_alt: i2c22_default_alt { group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. - */ + /* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. + */ psels = , ; bias-pull-up; diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay index 3767afee0e7c9..e1655d2cf649c 100644 --- a/tests/boards/nrf/i2c/i2c_slave/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay @@ -33,9 +33,9 @@ i2c22_default_alt: i2c22_default_alt { group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. - */ + /* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. + */ psels = , ; bias-pull-up; diff --git a/tests/boards/nrf/i2c/i2c_slave/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 1d7700959367a..b02c98c3e4fb7 100644 --- a/tests/boards/nrf/i2c/i2c_slave/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/boards/nrf/i2c/i2c_slave/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -16,9 +16,9 @@ i2c131_default_alt: i2c131_default_alt { group1 { -/* Temporary workaround as it is currently not possible - * to configure pins for TWIS with pinctrl. - */ + /* Temporary workaround as it is currently not possible + * to configure pins for TWIS with pinctrl. + */ psels = , ; bias-pull-up; diff --git a/tests/boards/nrf/qdec/boards/nrf52840dk_nrf52840.overlay b/tests/boards/nrf/qdec/boards/nrf52840dk_nrf52840.overlay index f227fb95c3827..9ee3749b4ff8b 100644 --- a/tests/boards/nrf/qdec/boards/nrf52840dk_nrf52840.overlay +++ b/tests/boards/nrf/qdec/boards/nrf52840dk_nrf52840.overlay @@ -21,7 +21,6 @@ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; - }; &pinctrl { @@ -46,8 +45,8 @@ pinctrl-0 = <&qdec_pinctrl>; pinctrl-1 = <&qdec_sleep_pinctrl>; pinctrl-names = "default", "sleep"; - steps = < 127 >; - led-pre = < 500 >; + steps = <127>; + led-pre = <500>; zephyr,pm-device-runtime-auto; }; diff --git a/tests/boards/nrf/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/boards/nrf/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay index ed6a5587f5b37..22f5307a760a5 100644 --- a/tests/boards/nrf/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/tests/boards/nrf/qdec/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -45,8 +45,8 @@ pinctrl-0 = <&qdec_pinctrl>; pinctrl-1 = <&qdec_sleep_pinctrl>; pinctrl-names = "default", "sleep"; - steps = < 127 >; - led-pre = < 500 >; + steps = <127>; + led-pre = <500>; zephyr,pm-device-runtime-auto; }; diff --git a/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840_mem.overlay b/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840_mem.overlay index 4088ac2afaa6b..4df236d5c0872 100644 --- a/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840_mem.overlay +++ b/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840_mem.overlay @@ -23,7 +23,6 @@ }; }; - chosen { zephyr,boot-mode = &boot_mode0; zephyr,uart-mcumgr = &uart1; diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c index be580e02ea61c..32522d79cba5c 100644 --- a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c +++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c @@ -801,7 +801,7 @@ static void test_broadcast_sync(const uint8_t broadcast_code[BT_ISO_BROADCAST_CO return; } - stream_sync_cnt = POPCOUNT(bis_index_bitfield); + stream_sync_cnt = sys_count_bits(&bis_index_bitfield, sizeof(bis_index_bitfield)); } static void test_broadcast_sync_inval(void) diff --git a/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c b/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c index a00dff69e4b50..69da47a4e2e5b 100644 --- a/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c +++ b/tests/bsim/bluetooth/audio/src/bap_unicast_client_test.c @@ -623,6 +623,7 @@ static void codec_configure_streams(size_t stream_cnt) static void qos_configure_streams(struct bt_bap_unicast_group *unicast_group, size_t stream_cnt) { + struct bt_bap_unicast_group_info info; int err; UNSET_FLAG(flag_stream_qos_configured); @@ -640,6 +641,23 @@ static void qos_configure_streams(struct bt_bap_unicast_group *unicast_group, while (atomic_get(&flag_stream_qos_configured) != stream_cnt) { (void)k_sleep(K_MSEC(1)); } + + err = bt_bap_unicast_group_get_info(unicast_group, &info); + if (err != 0) { + FAIL("Unable to QoS configure streams: %d\n", err); + return; + } + + if (info.sink_pd != preset_16_2_1.qos.pd) { + FAIL("Unexpected sink PD %u (expected %u)\n", info.sink_pd, preset_16_2_1.qos.pd); + return; + } + + if (info.source_pd != preset_16_2_1.qos.pd) { + FAIL("Unexpected source PD %u (expected %u)\n", info.source_pd, + preset_16_2_1.qos.pd); + return; + } } static int enable_stream(struct bt_bap_stream *stream) diff --git a/tests/bsim/bluetooth/audio/src/cap_handover_central_test.c b/tests/bsim/bluetooth/audio/src/cap_handover_central_test.c index e6c3236f43f6b..9c972b223cf8a 100644 --- a/tests/bsim/bluetooth/audio/src/cap_handover_central_test.c +++ b/tests/bsim/bluetooth/audio/src/cap_handover_central_test.c @@ -659,7 +659,6 @@ static void handover_unicast_to_broadcast(struct bt_cap_unicast_group *unicast_g param.unicast_group = unicast_group; param.broadcast_create_param = &create_param; param.ext_adv = ext_adv; - param.sid = 0x00; param.pa_interval = BT_BAP_PA_INTERVAL_UNKNOWN; param.broadcast_id = 0x123456; diff --git a/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c b/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c index 719be10c5dcbd..a1b7868a4a478 100644 --- a/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c +++ b/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c @@ -644,6 +644,50 @@ static void unicast_group_create(struct bt_cap_unicast_group **out_unicast_group } } +static bool unicast_group_foreach_stream_cb(struct bt_cap_stream *cap_stream, void *user_data) +{ + const uint32_t expected_pd = cap_stream->bap_stream.qos->pd; + struct bt_cap_unicast_group *unicast_group = user_data; + struct bt_bap_unicast_group_info bap_info; + struct bt_cap_unicast_group_info cap_info; + struct bt_bap_ep_info ep_info; + int err; + + err = bt_bap_ep_get_info(cap_stream->bap_stream.ep, &ep_info); + if (err != 0) { + FAIL("Failed to get EP info: %d\n", err); + return true; + } + + err = bt_cap_unicast_group_get_info(unicast_group, &cap_info); + if (err != 0) { + FAIL("Failed to get CAP unicast group info: %d\n", err); + return true; + } + + err = bt_bap_unicast_group_get_info(cap_info.unicast_group, &bap_info); + if (err != 0) { + FAIL("Failed to get BAP unicast group info: %d\n", err); + return true; + } + + if (ep_info.dir == BT_AUDIO_DIR_SINK) { + if (bap_info.sink_pd != expected_pd) { + FAIL("Unexpected sink PD %u (expected %u)\n", bap_info.sink_pd, + expected_pd); + return true; + } + } else { + if (bap_info.source_pd != expected_pd) { + FAIL("Unexpected source PD %u (expected %u)\n", bap_info.source_pd, + expected_pd); + return true; + } + } + + return false; +} + static void unicast_audio_start(struct bt_cap_unicast_group *unicast_group, bool wait) { struct bt_cap_unicast_audio_start_stream_param stream_param[2]; @@ -676,6 +720,13 @@ static void unicast_audio_start(struct bt_cap_unicast_group *unicast_group, bool WAIT_FOR_FLAG(flag_started); /* let other devices know we have started what we wanted */ backchannel_sync_send_all(); + + err = bt_cap_unicast_group_foreach_stream( + unicast_group, unicast_group_foreach_stream_cb, unicast_group); + if (err != 0) { + FAIL("Failed iterate on unicast group: %d\n", err); + return; + } } } diff --git a/tests/bsim/bluetooth/audio/test_scripts/audio_config_tests/_ac_common.sh b/tests/bsim/bluetooth/audio/test_scripts/audio_config_tests/_ac_common.sh index 05daa11082ed3..979fb81a66e1e 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/audio_config_tests/_ac_common.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/audio_config_tests/_ac_common.sh @@ -5,7 +5,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source VERBOSITY_LEVEL=2 -EXECUTE_TIMEOUT=60 +EXECUTE_TIMEOUT=120 BSIM_EXE=./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf cd ${BSIM_OUT_PATH}/bin diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh index 8e13d495d282f..6c3d71511d887 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_bass_client_sync.sh @@ -20,7 +20,8 @@ Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 \ - -testid=bap_broadcast_assistant_client_sync -RealEncryption=1 -rs=46 -D=3 + -testid=bap_broadcast_assistant_client_sync -RealEncryption=1 -rs=46 -D=3 \ + -start_offset=2e3 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=bass_broadcaster \ diff --git a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh index d6ba945d80800..09c7d8217c557 100755 --- a/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh +++ b/tests/bsim/bluetooth/audio/test_scripts/bap_unicast_audio_acl_disconnect.sh @@ -16,11 +16,11 @@ printf "\n\n======== Unicast Audio ACL Disconnect test =========\n\n" Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=unicast_client_acl_disconnect \ - -RealEncryption=1 -rs=23 -D=2 + -RealEncryption=1 -D=2 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \ -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=unicast_server_acl_disconnect \ - -RealEncryption=1 -rs=28 -D=2 -start_offset=2e3 + -RealEncryption=1 -D=2 -start_offset=2e3 # Simulation time should be larger than the WAIT_TIME in common.h Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \ diff --git a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh index 8943a9605ad37..86d560ed956c4 100755 --- a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh +++ b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh @@ -17,6 +17,7 @@ ${ZEPHYR_BASE}/tests/bsim/bluetooth/tester/compile.sh app=tests/bsim/bluetooth/ll/conn conf_file=prj_split_privacy.conf sysbuild=1 compile app=tests/bsim/bluetooth/ll/throughput sysbuild=1 compile +app=tests/bsim/bluetooth/ll/throughput conf_overlay=overlay-no_phy_update.conf sysbuild=1 compile app=tests/bsim/bluetooth/ll/multiple_id sysbuild=1 compile app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-sequential.conf sysbuild=1 compile app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-interleaved.conf sysbuild=1 compile diff --git a/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh b/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh index e0524dbbdeaa6..9db8bbcf8d25d 100755 --- a/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh +++ b/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh @@ -14,6 +14,7 @@ export BOARD="${BOARD:-nrf54l15bsim/nrf54l15/cpuapp}" source ${ZEPHYR_BASE}/tests/bsim/compile.source app=tests/bsim/bluetooth/ll/throughput compile +app=tests/bsim/bluetooth/ll/throughput conf_overlay=overlay-no_phy_update.conf compile app=tests/bsim/bluetooth/ll/multiple_id compile app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-sequential.conf compile app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-interleaved.conf compile diff --git a/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh b/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh index 045b1eba64903..3f1d5c20fb87e 100755 --- a/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh +++ b/tests/bsim/bluetooth/host/adv/chain/tests_scripts/adv_chain.sh @@ -18,6 +18,6 @@ Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_adv_chain_prj_conf\ -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=scan Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ - -D=2 -sim_length=10e6 $@ + -D=2 -sim_length=11e6 $@ wait_for_background_jobs diff --git a/tests/bsim/bluetooth/ll/compile.sh b/tests/bsim/bluetooth/ll/compile.sh index 87b1f3006addf..d5058386824d6 100755 --- a/tests/bsim/bluetooth/ll/compile.sh +++ b/tests/bsim/bluetooth/ll/compile.sh @@ -41,5 +41,6 @@ app=tests/bsim/bluetooth/ll/edtt/gatt_test_app \ app=tests/bsim/bluetooth/ll/multiple_id compile app=tests/bsim/bluetooth/ll/throughput compile +app=tests/bsim/bluetooth/ll/throughput conf_overlay=overlay-no_phy_update.conf compile wait_for_background_jobs diff --git a/tests/bsim/bluetooth/ll/throughput/Kconfig b/tests/bsim/bluetooth/ll/throughput/Kconfig new file mode 100644 index 0000000000000..3c4be151e4dc6 --- /dev/null +++ b/tests/bsim/bluetooth/ll/throughput/Kconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +source "$(ZEPHYR_BASE)/samples/bluetooth/central_gatt_write/Kconfig" diff --git a/tests/bsim/bluetooth/ll/throughput/overlay-no_phy_update.conf b/tests/bsim/bluetooth/ll/throughput/overlay-no_phy_update.conf new file mode 100644 index 0000000000000..5bbfc6422b603 --- /dev/null +++ b/tests/bsim/bluetooth/ll/throughput/overlay-no_phy_update.conf @@ -0,0 +1,2 @@ +# Disable user initiated PHY update support +CONFIG_BT_USER_PHY_UPDATE=n diff --git a/tests/bsim/bluetooth/ll/throughput/prj.conf b/tests/bsim/bluetooth/ll/throughput/prj.conf index e8848bbf25dbd..5b699d7e892f0 100644 --- a/tests/bsim/bluetooth/ll/throughput/prj.conf +++ b/tests/bsim/bluetooth/ll/throughput/prj.conf @@ -17,6 +17,10 @@ CONFIG_BT_AUTO_DATA_LEN_UPDATE=y # Enable user initiated Data Length update support CONFIG_BT_USER_DATA_LEN_UPDATE=y +# Perform one iteration of PHY and Connection Updates +CONFIG_USE_CONN_UPDATE_ITERATION_ONCE=y +CONFIG_USE_PHY_UPDATE_ITERATION_ONCE=y + # BT HCI Command Buffers # Greater than BT_BUF_ACL_TX_COUNT, to be able to Send Host Number of Completed Packets commands CONFIG_BT_BUF_CMD_TX_COUNT=4 @@ -24,7 +28,7 @@ CONFIG_BT_BUF_CMD_TX_SIZE=255 # BT HCI Event Buffers # Greater than BT_BUF_ACL_TX_COUNT, to be able to receive Number of Completed Packets events -CONFIG_BT_BUF_EVT_RX_COUNT=4 +CONFIG_BT_BUF_EVT_RX_COUNT=7 CONFIG_BT_BUF_EVT_RX_SIZE=255 # BT HCI Discardable Event Buffers @@ -32,7 +36,7 @@ CONFIG_BT_BUF_EVT_DISCARDABLE_COUNT=3 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255 # BT HCI ACL TX Data Buffers -CONFIG_BT_BUF_ACL_TX_COUNT=3 +CONFIG_BT_BUF_ACL_TX_COUNT=6 CONFIG_BT_BUF_ACL_TX_SIZE=251 # BT HCI ACL RX Data Buffers diff --git a/tests/bsim/bluetooth/ll/throughput/src/main.c b/tests/bsim/bluetooth/ll/throughput/src/main.c index a18801d40669b..64e818d4a4e5b 100644 --- a/tests/bsim/bluetooth/ll/throughput/src/main.c +++ b/tests/bsim/bluetooth/ll/throughput/src/main.c @@ -16,15 +16,26 @@ #include "time_machine.h" #include "bstests.h" -/* There are 13 iterations of PHY update every 3 seconds, and based on actual - * simulation 10000 iterations are sufficient to finish these iterations with +/* There are 13 iterations of PHY update every 5 seconds, and based on actual + * simulation COUNT iterations are sufficient to finish these iterations with * a stable 2M throughput value to be verified. If Central and Peripheral take * different duration to complete these iterations, the test will fail due to * the throughput calculated over one second duration will be low due to the * connection being disconnected before the other device could complete all the * iterations. + * If the PHY and connection update iterations complete before the below number + * of iterations, then a COUNT_THROUGHPUT number of write operations are + * performed and throughput calculated. Note, `count` value in the central and + * peripheral sample is referenced using a pointer and the pointer will be used + * to setup the throughput measurement countdown. */ -#define COUNT 10000 +#if defined(CONFIG_BT_USER_PHY_UPDATE) +#define COUNT_CENTRAL 17000U +#define COUNT_PERIPHERAL 17600U +#else /* !CONFIG_BT_USER_PHY_UPDATE */ +#define COUNT_CENTRAL 180000U +#define COUNT_PERIPHERAL 180000U +#endif /* !CONFIG_BT_USER_PHY_UPDATE */ /* Write Throughput calculation: * Measure interval = 1 s @@ -64,7 +75,7 @@ static void test_central_main(void) { uint32_t write_rate; - write_rate = central_gatt_write(COUNT); + write_rate = central_gatt_write(COUNT_CENTRAL); printk("%s: Write Rate = %u bps\n", __func__, write_rate); if (write_rate == WRITE_RATE) { @@ -83,7 +94,7 @@ static void test_peripheral_main(void) { uint32_t write_rate; - write_rate = peripheral_gatt_write(COUNT); + write_rate = peripheral_gatt_write(COUNT_PERIPHERAL); printk("%s: Write Rate = %u bps\n", __func__, write_rate); if (write_rate == WRITE_RATE) { @@ -95,7 +106,7 @@ static void test_peripheral_main(void) static void test_gatt_write_init(void) { - bst_ticker_set_next_tick_absolute(60e6); + bst_ticker_set_next_tick_absolute(1500e6); bst_result = In_progress; } diff --git a/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh index 61fd4bc8edcc4..32f4fed6a0597 100755 --- a/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh +++ b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh @@ -1,4 +1,5 @@ #!/usr/bin/env bash +# Copyright 2025 Nordic Semiconductor ASA # Copyright 2018 Oticon A/S # SPDX-License-Identifier: Apache-2.0 @@ -6,7 +7,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source simulation_id="ll-throughput" verbosity_level=2 -EXECUTE_TIMEOUT=240 +EXECUTE_TIMEOUT=180 cd ${BSIM_OUT_PATH}/bin @@ -19,6 +20,6 @@ Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_throughput_prj_conf\ -testid=peripheral Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ - -D=2 -sim_length=60e6 $@ -argschannel -at=40 + -D=2 -sim_length=120e6 $@ -argschannel -at=40 wait_for_background_jobs diff --git a/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write_no_phy_update.sh b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write_no_phy_update.sh new file mode 100755 index 0000000000000..abe3cf9df7b01 --- /dev/null +++ b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write_no_phy_update.sh @@ -0,0 +1,24 @@ +#!/usr/bin/env bash +# Copyright 2018 Oticon A/S +# SPDX-License-Identifier: Apache-2.0 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +simulation_id="ll-throughput-no-phy-update" +verbosity_level=2 +EXECUTE_TIMEOUT=2400 + +cd ${BSIM_OUT_PATH}/bin + +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_throughput_prj_conf_overlay-no_phy_update_conf \ + -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=0 \ + -testid=central + +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_throughput_prj_conf_overlay-no_phy_update_conf \ + -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=1 \ + -testid=peripheral + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ + -D=2 -sim_length=1500e6 $@ -argschannel -at=40 + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/mesh/src/test_lcd.c b/tests/bsim/bluetooth/mesh/src/test_lcd.c index c31c5d43f72d2..9fcb60a034ccb 100644 --- a/tests/bsim/bluetooth/mesh/src/test_lcd.c +++ b/tests/bsim/bluetooth/mesh/src/test_lcd.c @@ -434,7 +434,7 @@ static void test_srv_comp_data_status_respond(void) atomic_set_bit(bt_mesh.flags, BT_MESH_COMP_DIRTY); } - /* No server callback available. Wait 10 sec for message to be recived */ + /* No server callback available. Wait 10 sec for message to be received */ k_sleep(K_SECONDS(10)); PASS(); @@ -449,7 +449,7 @@ static void test_srv_metadata_status_respond(void) FAIL("Metadata is dirty. Test is not suited for this purpose."); } - /* No server callback available. Wait 10 sec for message to be recived */ + /* No server callback available. Wait 10 sec for message to be received */ k_sleep(K_SECONDS(10)); PASS(); diff --git a/tests/bsim/bluetooth/tester/CMakeLists.txt b/tests/bsim/bluetooth/tester/CMakeLists.txt index b47f2b2fee1f2..d86c1e0c20595 100644 --- a/tests/bsim/bluetooth/tester/CMakeLists.txt +++ b/tests/bsim/bluetooth/tester/CMakeLists.txt @@ -24,14 +24,22 @@ zephyr_include_directories( target_sources(app PRIVATE src/bsim_btp.c src/test_main.c + src/audio/ccp_central.c + src/audio/ccp_peripheral.c src/audio/csip_central.c src/audio/csip_peripheral.c src/audio/hap_central.c src/audio/hap_peripheral.c + src/audio/mcp_central.c + src/audio/mcp_peripheral.c src/audio/micp_central.c src/audio/micp_peripheral.c + src/audio/tmap_central.c + src/audio/tmap_peripheral.c src/audio/vcp_central.c src/audio/vcp_peripheral.c src/host/gap_central.c src/host/gap_peripheral.c + src/host/iso_broadcaster.c + src/host/iso_sync_receiver.c ) diff --git a/tests/bsim/bluetooth/tester/src/audio/ccp_central.c b/tests/bsim/bluetooth/tester/src/audio/ccp_central.c new file mode 100644 index 0000000000000..dc33201c609c2 --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/audio/ccp_central.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_ccp_central, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +static void test_ccp_central(void) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + const char *uri = "tel:12345"; + bt_addr_le_t remote_addr; + uint8_t inst_index = 0U; + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + bsim_btp_core_register(BTP_SERVICE_ID_CCP); + + bsim_btp_gap_start_discovery(BTP_GAP_DISCOVERY_FLAG_LE); + bsim_btp_wait_for_gap_device_found(&remote_addr); + bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str)); + LOG_INF("Found remote device %s", addr_str); + + bsim_btp_gap_stop_discovery(); + bsim_btp_gap_connect(&remote_addr, BTP_GAP_ADDR_TYPE_IDENTITY); + bsim_btp_wait_for_gap_device_connected(NULL); + LOG_INF("Device %s connected", addr_str); + + bsim_btp_gap_pair(&remote_addr); + bsim_btp_wait_for_gap_sec_level_changed(NULL, NULL); + + bsim_btp_ccp_discover(&remote_addr); + bsim_btp_wait_for_ccp_discovered(); + + bsim_btp_ccp_originate_call(&remote_addr, inst_index, uri); + bsim_btp_wait_for_ccp_call_states(); + + bsim_btp_gap_disconnect(&remote_addr); + bsim_btp_wait_for_gap_device_disconnected(NULL); + LOG_INF("Device %s disconnected", addr_str); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "ccp_central", + .test_descr = "Smoketest for the CCP central BT Tester behavior", + .test_main_f = test_ccp_central, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_ccp_central_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/audio/ccp_peripheral.c b/tests/bsim/bluetooth/tester/src/audio/ccp_peripheral.c new file mode 100644 index 0000000000000..a2a08b859d481 --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/audio/ccp_peripheral.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_ccp_peripheral, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +static void test_ccp_peripheral(void) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + bt_addr_le_t remote_addr; + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + bsim_btp_core_register(BTP_SERVICE_ID_TBS); + + bsim_btp_gap_set_discoverable(BTP_GAP_GENERAL_DISCOVERABLE); + bsim_btp_gap_start_advertising(0U, 0U, NULL, BT_HCI_OWN_ADDR_PUBLIC); + bsim_btp_wait_for_gap_device_connected(&remote_addr); + bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str)); + LOG_INF("Device %s connected", addr_str); + bsim_btp_wait_for_gap_device_disconnected(NULL); + LOG_INF("Device %s disconnected", addr_str); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "ccp_peripheral", + .test_descr = "Smoketest for the CCP peripheral BT Tester behavior", + .test_main_f = test_ccp_peripheral, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_ccp_peripheral_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/audio/mcp_central.c b/tests/bsim/bluetooth/tester/src/audio/mcp_central.c new file mode 100644 index 0000000000000..c92e91caf5f32 --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/audio/mcp_central.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_mcp_central, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +static void test_mcp_central(void) +{ + const uint8_t opcode = BT_MCS_OPC_PAUSE; + char addr_str[BT_ADDR_LE_STR_LEN]; + bt_addr_le_t remote_addr; + uint8_t expect_opcode; + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + bsim_btp_core_register(BTP_SERVICE_ID_MCP); + + bsim_btp_gap_start_discovery(BTP_GAP_DISCOVERY_FLAG_LE); + bsim_btp_wait_for_gap_device_found(&remote_addr); + bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str)); + LOG_INF("Found remote device %s", addr_str); + + bsim_btp_gap_stop_discovery(); + bsim_btp_gap_connect(&remote_addr, BTP_GAP_ADDR_TYPE_IDENTITY); + bsim_btp_wait_for_gap_device_connected(NULL); + LOG_INF("Device %s connected", addr_str); + + bsim_btp_gap_pair(&remote_addr); + bsim_btp_wait_for_gap_sec_level_changed(NULL, NULL); + + bsim_btp_mcp_discover(&remote_addr); + bsim_btp_wait_for_mcp_discovered(NULL); + + bsim_btp_mcp_send_cmd(&remote_addr, opcode, false, 0); + bsim_btp_wait_for_mcp_cmd_ntf(&expect_opcode); + TEST_ASSERT(opcode == expect_opcode, "%u != %u", opcode, expect_opcode); + + bsim_btp_gap_disconnect(&remote_addr); + bsim_btp_wait_for_gap_device_disconnected(NULL); + LOG_INF("Device %s disconnected", addr_str); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "mcp_central", + .test_descr = "Smoketest for the MCP central BT Tester behavior", + .test_main_f = test_mcp_central, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_mcp_central_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/audio/mcp_peripheral.c b/tests/bsim/bluetooth/tester/src/audio/mcp_peripheral.c new file mode 100644 index 0000000000000..30ace84b8fcb7 --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/audio/mcp_peripheral.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_mcp_peripheral, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +static void test_mcp_peripheral(void) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + bt_addr_le_t remote_addr; + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + bsim_btp_core_register(BTP_SERVICE_ID_GMCS); + + bsim_btp_gap_set_discoverable(BTP_GAP_GENERAL_DISCOVERABLE); + bsim_btp_gap_start_advertising(0U, 0U, NULL, BT_HCI_OWN_ADDR_PUBLIC); + bsim_btp_wait_for_gap_device_connected(&remote_addr); + bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str)); + LOG_INF("Device %s connected", addr_str); + bsim_btp_wait_for_gap_device_disconnected(NULL); + LOG_INF("Device %s disconnected", addr_str); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "mcp_peripheral", + .test_descr = "Smoketest for the MCP peripheral BT Tester behavior", + .test_main_f = test_mcp_peripheral, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_mcp_peripheral_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/audio/tmap_central.c b/tests/bsim/bluetooth/tester/src/audio/tmap_central.c new file mode 100644 index 0000000000000..7dc32249522b4 --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/audio/tmap_central.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_tmap_central, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +static void test_tmap_central(void) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + bt_addr_le_t remote_addr; + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + bsim_btp_core_register(BTP_SERVICE_ID_TMAP); + + bsim_btp_gap_start_discovery(BTP_GAP_DISCOVERY_FLAG_LE); + bsim_btp_wait_for_gap_device_found(&remote_addr); + bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str)); + LOG_INF("Found remote device %s", addr_str); + + bsim_btp_gap_stop_discovery(); + bsim_btp_gap_connect(&remote_addr, BTP_GAP_ADDR_TYPE_IDENTITY); + bsim_btp_wait_for_gap_device_connected(NULL); + LOG_INF("Device %s connected", addr_str); + + bsim_btp_gap_pair(&remote_addr); + bsim_btp_wait_for_gap_sec_level_changed(NULL, NULL); + + bsim_btp_tmap_discover(&remote_addr); + bsim_btp_wait_for_tmap_discovery_complete(); + + bsim_btp_gap_disconnect(&remote_addr); + bsim_btp_wait_for_gap_device_disconnected(NULL); + LOG_INF("Device %s disconnected", addr_str); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "tmap_central", + .test_descr = "Smoketest for the TMAP central BT Tester behavior", + .test_main_f = test_tmap_central, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_tmap_central_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/audio/tmap_peripheral.c b/tests/bsim/bluetooth/tester/src/audio/tmap_peripheral.c new file mode 100644 index 0000000000000..0a0ebf33cdb58 --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/audio/tmap_peripheral.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include + +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_tmap_peripheral, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +static void test_tmap_peripheral(void) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + bt_addr_le_t remote_addr; + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + bsim_btp_core_register(BTP_SERVICE_ID_TMAP); + + bsim_btp_gap_set_discoverable(BTP_GAP_GENERAL_DISCOVERABLE); + bsim_btp_gap_start_advertising(0U, 0U, NULL, BT_HCI_OWN_ADDR_PUBLIC); + bsim_btp_wait_for_gap_device_connected(&remote_addr); + bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str)); + LOG_INF("Device %s connected", addr_str); + bsim_btp_wait_for_gap_device_disconnected(NULL); + LOG_INF("Device %s disconnected", addr_str); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "tmap_peripheral", + .test_descr = "Smoketest for the TMAP peripheral BT Tester behavior", + .test_main_f = test_tmap_peripheral, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_tmap_peripheral_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/bsim_btp.c b/tests/bsim/bluetooth/tester/src/bsim_btp.c index 30b8f4d198182..a5b2c7000dc88 100644 --- a/tests/bsim/bluetooth/tester/src/bsim_btp.c +++ b/tests/bsim/bluetooth/tester/src/bsim_btp.c @@ -129,6 +129,8 @@ static bool is_valid_gap_packet_len(const struct btp_hdr *hdr, struct net_buf_si case BTP_GAP_SET_EXTENDED_ADVERTISING: return buf_simple->len == sizeof(struct btp_gap_set_extended_advertising_rp); case BTP_GAP_PADV_CONFIGURE: + return buf_simple->len == sizeof(struct btp_gap_padv_configure_rp); + case BTP_GAP_PADV_START: return buf_simple->len == sizeof(struct btp_gap_padv_start_rp); case BTP_GAP_PADV_STOP: return buf_simple->len == sizeof(struct btp_gap_padv_stop_rp); @@ -142,6 +144,12 @@ static bool is_valid_gap_packet_len(const struct btp_hdr *hdr, struct net_buf_si return buf_simple->len == 0U; case BTP_GAP_PADV_SYNC_TRANSFER_RECV: return buf_simple->len == 0U; + case BTP_GAP_BIG_CREATE_SYNC: + return buf_simple->len == 0U; + case BTP_GAP_CREATE_BIG: + return buf_simple->len == 0U; + case BTP_GAP_BIS_BROADCAST: + return buf_simple->len == 0U; /* events */ case BTP_GAP_EV_NEW_SETTINGS: @@ -194,6 +202,23 @@ static bool is_valid_gap_packet_len(const struct btp_hdr *hdr, struct net_buf_si return buf_simple->len == sizeof(struct btp_gap_ev_periodic_transfer_received_ev); case BTP_GAP_EV_ENCRYPTION_CHANGE: return buf_simple->len == sizeof(struct btp_gap_encryption_change_ev); + case BTP_GAP_EV_BIG_SYNC_ESTABLISHED: + return buf_simple->len == sizeof(struct btp_gap_big_sync_established_ev); + case BTP_GAP_EV_BIG_SYNC_LOST: + return buf_simple->len == sizeof(struct btp_gap_big_sync_lost_ev); + case BTP_GAP_EV_BIS_DATA_PATH_SETUP: + return buf_simple->len == sizeof(struct btp_gap_bis_data_path_setup_ev); + case BTP_GAP_EV_BIS_STREAM_RECEIVED: + if (hdr->len >= sizeof(struct btp_gap_bis_stream_received_ev)) { + const struct btp_gap_bis_stream_received_ev *ev = net_buf_simple_pull_mem( + buf_simple, sizeof(struct btp_gap_bis_stream_received_ev)); + + return ev->data_len == buf_simple->len; + } else { + return false; + } + case BTP_GAP_EV_PERIODIC_BIGINFO: + return buf_simple->len == sizeof(struct btp_gap_periodic_biginfo_ev); default: LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode); return false; diff --git a/tests/bsim/bluetooth/tester/src/bsim_btp.h b/tests/bsim/bluetooth/tester/src/bsim_btp.h index 93b4ea678f856..75198bf498eb0 100644 --- a/tests/bsim/bluetooth/tester/src/bsim_btp.h +++ b/tests/bsim/bluetooth/tester/src/bsim_btp.h @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include @@ -22,6 +24,74 @@ void bsim_btp_uart_init(void); void bsim_btp_send_to_tester(const uint8_t *data, size_t len); void bsim_btp_wait_for_evt(uint8_t service, uint8_t opcode, struct net_buf **out_buf); +static inline void bsim_btp_ccp_discover(const bt_addr_le_t *address) +{ + struct btp_ccp_discover_tbs_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_CCP; + cmd_hdr->opcode = BTP_CCP_DISCOVER_TBS; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + bt_addr_le_copy(&cmd->address, address); + + cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_ccp_originate_call(const bt_addr_le_t *address, uint8_t inst_index, + const char *uri) +{ + struct btp_ccp_originate_call_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_CCP; + cmd_hdr->opcode = BTP_CCP_ORIGINATE_CALL; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + bt_addr_le_copy(&cmd->address, address); + cmd->inst_index = inst_index; + cmd->uri_len = strlen(uri) + 1 /* NULL terminator */; + net_buf_simple_add_mem(&cmd_buffer, uri, cmd->uri_len); + + cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_wait_for_ccp_discovered(void) +{ + struct btp_ccp_discovered_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CCP, BTP_CCP_EV_DISCOVERED, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + + TEST_ASSERT(ev->status == BT_ATT_ERR_SUCCESS); + + net_buf_unref(buf); +} + +static inline void bsim_btp_wait_for_ccp_call_states(void) +{ + struct btp_ccp_call_states_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CCP, BTP_CCP_EV_CALL_STATES, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + + TEST_ASSERT(ev->status == BT_ATT_ERR_SUCCESS); + + net_buf_unref(buf); +} + static inline void bsim_btp_core_register(uint8_t id) { struct btp_core_register_service_cmd *cmd; @@ -36,7 +106,7 @@ static inline void bsim_btp_core_register(uint8_t id) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); cmd->id = id; - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -109,6 +179,25 @@ static inline void bsim_btp_wait_for_lock(void) net_buf_unref(buf); } +static inline void bsim_btp_gap_set_connectable(bool enable) +{ + struct btp_gap_set_connectable_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_SET_CONNECTABLE; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + cmd->connectable = enable ? 1 : 0; + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + static inline void bsim_btp_gap_set_discoverable(uint8_t discoverable) { struct btp_gap_set_discoverable_cmd *cmd; @@ -123,7 +212,7 @@ static inline void bsim_btp_gap_set_discoverable(uint8_t discoverable) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); cmd->discoverable = discoverable; - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -153,7 +242,7 @@ static inline void bsim_btp_gap_start_advertising(uint8_t adv_data_len, uint8_t net_buf_simple_add_le32(&cmd_buffer, 0xFFFF); /* unused in Zephyr */ net_buf_simple_add_u8(&cmd_buffer, own_addr_type); - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -172,7 +261,7 @@ static inline void bsim_btp_gap_start_discovery(uint8_t flags) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); cmd->flags = flags; - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -187,7 +276,7 @@ static inline void bsim_btp_gap_stop_discovery(void) cmd_hdr->service = BTP_SERVICE_ID_GAP; cmd_hdr->opcode = BTP_GAP_STOP_DISCOVERY; cmd_hdr->index = BTP_INDEX; - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -221,7 +310,7 @@ static inline void bsim_btp_gap_connect(const bt_addr_le_t *address, uint8_t own bt_addr_le_copy(&cmd->address, address); cmd->own_addr_type = own_addr_type; - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -254,7 +343,7 @@ static inline void bsim_btp_gap_disconnect(const bt_addr_le_t *address) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); bt_addr_le_copy(&cmd->address, address); - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -287,7 +376,7 @@ static inline void bsim_btp_gap_pair(const bt_addr_le_t *address) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); bt_addr_le_copy(&cmd->address, address); - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -365,6 +454,114 @@ static inline void bsim_btp_wait_for_hauc_discovery_complete(bt_addr_le_t *addre net_buf_unref(buf); } +static inline void bsim_btp_mcp_discover(const bt_addr_le_t *address) +{ + struct btp_mcp_discover_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_MCP; + cmd_hdr->opcode = BTP_MCP_DISCOVER; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + bt_addr_le_copy(&cmd->address, address); + + cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_mcp_send_cmd(const bt_addr_le_t *address, uint8_t opcode, + bool use_param, int32_t param) +{ + struct btp_mcp_send_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_MCP; + cmd_hdr->opcode = BTP_MCP_CMD_SEND; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + bt_addr_le_copy(&cmd->address, address); + cmd->opcode = opcode; + cmd->use_param = use_param ? 1U : 0U; + cmd->param = sys_cpu_to_le32(param); + + cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_wait_for_mcp_discovered(bt_addr_le_t *address) +{ + struct btp_mcp_discovered_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_MCP, BTP_MCP_DISCOVERED_EV, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + + TEST_ASSERT(ev->status == BT_ATT_ERR_SUCCESS); + + if (address != NULL) { + bt_addr_le_copy(address, &ev->address); + } + + net_buf_unref(buf); +} + +static inline void bsim_btp_wait_for_mcp_cmd_ntf(uint8_t *requested_opcode) +{ + struct btp_mcp_cmd_ntf_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_MCP, BTP_MCP_NTF_EV, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + + TEST_ASSERT(ev->status == BT_ATT_ERR_SUCCESS); + TEST_ASSERT(ev->result_code == BT_MCS_OPC_NTF_SUCCESS); + + if (requested_opcode != NULL) { + *requested_opcode = ev->requested_opcode; + } + + net_buf_unref(buf); +} + +static inline void bsim_btp_tmap_discover(const bt_addr_le_t *address) +{ + struct btp_tmap_discover_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_TMAP; + cmd_hdr->opcode = BTP_TMAP_DISCOVER; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + bt_addr_le_copy(&cmd->address, address); + + cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_wait_for_tmap_discovery_complete(void) +{ + struct btp_tmap_discovery_complete_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_TMAP, BT_TMAP_EV_DISCOVERY_COMPLETE, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + + TEST_ASSERT(ev->status == BT_ATT_ERR_SUCCESS); + + net_buf_unref(buf); +} static inline void bsim_btp_vcp_discover(const bt_addr_le_t *address) { @@ -380,7 +577,7 @@ static inline void bsim_btp_vcp_discover(const bt_addr_le_t *address) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); bt_addr_le_copy(&cmd->address, address); - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -417,7 +614,7 @@ static inline void bsim_btp_vcp_ctlr_set_vol(const bt_addr_le_t *address, uint8_ bt_addr_le_copy(&cmd->address, address); cmd->volume = volume; - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -458,7 +655,7 @@ static inline void bsim_btp_vocs_state_set(const bt_addr_le_t *address, int16_t bt_addr_le_copy(&cmd->address, address); cmd->offset = sys_cpu_to_le16(offset); - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -499,7 +696,7 @@ static inline void bsim_btp_aics_set_gain(const bt_addr_le_t *address, int8_t ga bt_addr_le_copy(&cmd->address, address); cmd->gain = gain; - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -539,7 +736,7 @@ static inline void bsim_btp_micp_discover(const bt_addr_le_t *address) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); bt_addr_le_copy(&cmd->address, address); - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -575,7 +772,7 @@ static inline void bsim_btp_micp_ctlr_mute(const bt_addr_le_t *address) cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); bt_addr_le_copy(&cmd->address, address); - cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr); + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); } @@ -600,4 +797,323 @@ static inline void bsim_btp_wait_for_micp_state(bt_addr_le_t *address, uint8_t * net_buf_unref(buf); } + +static inline void bsim_btp_gap_set_extended_advertising(bool enable) +{ + struct btp_gap_set_extended_advertising_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_SET_EXTENDED_ADVERTISING; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + cmd->settings = enable ? BIT(0) : 0; + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_gap_padv_configure(uint8_t flags, uint16_t interval_min, + uint16_t interval_max) +{ + struct btp_gap_padv_configure_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_PADV_CONFIGURE; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + cmd->flags = flags; + cmd->interval_min = sys_cpu_to_le16(interval_min); + cmd->interval_max = sys_cpu_to_le16(interval_max); + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_gap_padv_start(void) +{ + struct btp_gap_padv_start_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_PADV_START; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + cmd->flags = 0; + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_gap_padv_stop(void) +{ + struct btp_gap_padv_stop_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_PADV_STOP; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_gap_padv_create_sync(bt_addr_le_t *addr, uint8_t sid, uint16_t skip, + uint16_t sync_timeout, uint8_t flags) +{ + struct btp_gap_padv_create_sync_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_PADV_CREATE_SYNC; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + bt_addr_le_copy(&cmd->address, addr); + cmd->advertiser_sid = sid; + cmd->skip = sys_cpu_to_le16(skip); + cmd->sync_timeout = sys_cpu_to_le16(sync_timeout); + cmd->flags = flags; + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_wait_for_gap_periodic_sync_established(bt_addr_le_t *address, + uint16_t *sync_handle, + uint8_t *status) +{ + struct btp_gap_ev_periodic_sync_established_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PERIODIC_SYNC_ESTABLISHED, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + if (address != NULL) { + bt_addr_le_copy(address, &ev->address); + } + + if (sync_handle != NULL) { + *sync_handle = ev->sync_handle; + } + + if (status != NULL) { + *status = ev->status; + } + + net_buf_unref(buf); +} + +static inline void bsim_btp_wait_for_gap_periodic_sync_lost(uint16_t *sync_handle, uint8_t *reason) +{ + struct btp_gap_ev_periodic_sync_lost_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PERIODIC_SYNC_LOST, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + if (sync_handle != NULL) { + *sync_handle = ev->sync_handle; + } + + if (reason != NULL) { + *reason = ev->reason; + } + + net_buf_unref(buf); +} + +static inline void bsim_btp_wait_for_gap_periodic_biginfo(bt_addr_le_t *address, uint8_t *sid, + uint8_t *num_bis, uint8_t *encryption) +{ + struct btp_gap_periodic_biginfo_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PERIODIC_BIGINFO, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + if (address != NULL) { + bt_addr_le_copy(address, &ev->address); + } + + if (sid != NULL) { + *sid = ev->sid; + } + + if (num_bis != NULL) { + *num_bis = ev->num_bis; + } + + if (encryption != NULL) { + *encryption = ev->encryption; + } + + net_buf_unref(buf); +} + +static inline void bsim_btp_gap_big_create_sync(bt_addr_le_t *address, uint8_t sid, uint8_t num_bis, + uint32_t bis_bitfield, uint32_t mse, + uint16_t sync_timeout, bool encryption, + uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]) +{ + struct btp_gap_big_create_sync_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_BIG_CREATE_SYNC; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + bt_addr_le_copy(&cmd->address, address); + cmd->sid = sid; + cmd->num_bis = num_bis; + cmd->bis_bitfield = sys_cpu_to_le32(bis_bitfield); + cmd->mse = sys_cpu_to_le32(mse); + cmd->sync_timeout = sys_cpu_to_le16(sync_timeout); + cmd->encryption = encryption; + if (encryption) { + net_buf_simple_add(&cmd_buffer, BT_ISO_BROADCAST_CODE_SIZE); + memcpy(cmd->broadcast_code, broadcast_code, BT_ISO_BROADCAST_CODE_SIZE); + } + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_wait_for_gap_big_sync_established(bt_addr_le_t *address) +{ + struct btp_gap_big_sync_established_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIG_SYNC_ESTABLISHED, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + if (address != NULL) { + bt_addr_le_copy(address, &ev->address); + } + + net_buf_unref(buf); +} + +static inline void bsim_btp_gap_create_big(uint8_t num_bis, uint32_t interval, uint16_t latency, + bool encryption, + uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]) +{ + struct btp_gap_create_big_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_CREATE_BIG; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + cmd->id = 0; + cmd->num_bis = num_bis; + cmd->interval = sys_cpu_to_le32(interval); + cmd->latency = sys_cpu_to_le16(latency); + cmd->rtn = 2; + cmd->phy = BT_GAP_LE_PHY_2M; + cmd->packing = BT_ISO_PACKING_SEQUENTIAL; + cmd->framing = BT_ISO_FRAMING_UNFRAMED; + cmd->encryption = encryption; + if (encryption) { + net_buf_simple_add(&cmd_buffer, BT_ISO_BROADCAST_CODE_SIZE); + memcpy(cmd->broadcast_code, broadcast_code, BT_ISO_BROADCAST_CODE_SIZE); + } + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_wait_for_gap_bis_data_path_setup(bt_addr_le_t *address, uint8_t *bis_id) +{ + struct btp_gap_bis_data_path_setup_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIS_DATA_PATH_SETUP, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + if (address != NULL) { + bt_addr_le_copy(address, &ev->address); + } + + if (bis_id != NULL) { + *bis_id = ev->bis_id; + } + + net_buf_unref(buf); +} + +static inline void bsim_btp_gap_bis_broadcast(uint8_t bis_id, struct net_buf_simple *buf) +{ + struct btp_gap_bis_broadcast_cmd *cmd; + struct btp_hdr *cmd_hdr; + + NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU); + + cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr)); + cmd_hdr->service = BTP_SERVICE_ID_GAP; + cmd_hdr->opcode = BTP_GAP_BIS_BROADCAST; + cmd_hdr->index = BTP_INDEX; + cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd)); + __ASSERT(buf->len <= net_buf_simple_tailroom(&cmd_buffer), "No more tail room"); + cmd->bis_id = bis_id; + cmd->data_len = buf->len; + net_buf_simple_add_mem(&cmd_buffer, buf->data, buf->len); + + cmd_hdr->len = sys_cpu_to_le16(cmd_buffer.len - sizeof(*cmd_hdr)); + + bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len); +} + +static inline void bsim_btp_wait_for_gap_bis_stream_received(struct net_buf_simple *rx) +{ + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIS_STREAM_RECEIVED, &buf); + __ASSERT(buf->len <= net_buf_simple_tailroom(rx), "No more tail room"); + net_buf_simple_add_mem(rx, buf->data, buf->len); + net_buf_unref(buf); +} + +static inline void bsim_btp_wait_for_gap_big_sync_lost(bt_addr_le_t *address, uint8_t *reason) +{ + struct btp_gap_big_sync_lost_ev *ev; + struct net_buf *buf; + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BIG_SYNC_LOST, &buf); + ev = net_buf_pull_mem(buf, sizeof(*ev)); + if (address != NULL) { + bt_addr_le_copy(address, &ev->address); + } + + if (reason != NULL) { + *reason = ev->reason; + } + + net_buf_unref(buf); +} + #endif /* BSIM_BTP_H_ */ diff --git a/tests/bsim/bluetooth/tester/src/host/iso_broadcaster.c b/tests/bsim/bluetooth/tester/src/host/iso_broadcaster.c new file mode 100644 index 0000000000000..4ba103da5a306 --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/host/iso_broadcaster.c @@ -0,0 +1,87 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_iso_broadcaster, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, + 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, + 0x0d, 0x0e, 0x0f, 0x10}; + +#define BIS_DATA_LEN 10 +#define BIG_INTERVAL 10000 /* 10ms */ + +static void test_iso_broadcaster(void) +{ + uint8_t bis_id; + uint32_t count = 100; /* 100 BIS data packets */ + char addr_str[BT_ADDR_LE_STR_LEN]; + bt_addr_le_t ev_addr; + + NET_BUF_SIMPLE_DEFINE(data, BIS_DATA_LEN); + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + + bsim_btp_gap_set_connectable(false); + bsim_btp_gap_set_extended_advertising(true); + bsim_btp_gap_set_discoverable(BTP_GAP_GENERAL_DISCOVERABLE); + bsim_btp_gap_start_advertising(0U, 0U, NULL, BT_HCI_OWN_ADDR_PUBLIC); + bsim_btp_gap_padv_configure(BTP_GAP_PADV_INCLUDE_TX_POWER, 150, 200); + bsim_btp_gap_padv_start(); + bsim_btp_gap_create_big(1, BIG_INTERVAL, 20, true, broadcast_code); + + bsim_btp_wait_for_gap_bis_data_path_setup(&ev_addr, &bis_id); + bt_addr_le_to_str(&ev_addr, addr_str, sizeof(addr_str)); + LOG_INF("Device %s: Data path of BIS %u is setup", addr_str, bis_id); + while (count > 0) { + net_buf_simple_reset(&data); + while (net_buf_simple_tailroom(&data) > 0) { + net_buf_simple_add_u8(&data, (uint8_t)count); + } + bsim_btp_gap_bis_broadcast(bis_id, &data); + + k_sleep(K_USEC(BIG_INTERVAL)); + count--; + } + + k_sleep(K_SECONDS(1)); + bsim_btp_gap_padv_stop(); + k_sleep(K_SECONDS(1)); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "iso_broadcaster", + .test_descr = "Smoketest for the GAP ISO Broadcaster BT Tester behavior", + .test_main_f = test_iso_broadcaster, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_iso_broadcaster_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/host/iso_sync_receiver.c b/tests/bsim/bluetooth/tester/src/host/iso_sync_receiver.c new file mode 100644 index 0000000000000..6b0113effb8cb --- /dev/null +++ b/tests/bsim/bluetooth/tester/src/host/iso_sync_receiver.c @@ -0,0 +1,107 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "babblekit/testcase.h" +#include "bstests.h" + +#include "btp/btp.h" +#include "bsim_btp.h" + +LOG_MODULE_REGISTER(bsim_iso_sync_receiver, CONFIG_BSIM_BTTESTER_LOG_LEVEL); + +extern uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]; +NET_BUF_SIMPLE_DEFINE_STATIC(bis_stream_rx, BTP_MTU); + +static void test_iso_sync_receiver(void) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + char ev_addr_str[BT_ADDR_LE_STR_LEN]; + bt_addr_le_t remote_addr; + bt_addr_le_t ev_addr; + uint16_t sync_handle; + uint16_t lost_sync_handle; + uint8_t status; + uint8_t sid; + uint8_t num_bis; + uint8_t encryption; + uint8_t bis_id; + uint8_t reason; + struct btp_gap_bis_stream_received_ev *ev; + + bsim_btp_uart_init(); + + bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL); + + bsim_btp_core_register(BTP_SERVICE_ID_GAP); + bsim_btp_gap_start_discovery(BTP_GAP_DISCOVERY_FLAG_LE); + bsim_btp_wait_for_gap_device_found(&remote_addr); + bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str)); + LOG_INF("Found remote device %s", addr_str); + + bsim_btp_gap_padv_create_sync(&remote_addr, 0, 0, 0x200, 0); + bsim_btp_wait_for_gap_periodic_sync_established(&ev_addr, &sync_handle, &status); + bt_addr_le_to_str(&ev_addr, ev_addr_str, sizeof(ev_addr_str)); + TEST_ASSERT(bt_addr_le_eq(&remote_addr, &ev_addr), "%s != %s", addr_str, ev_addr_str); + TEST_ASSERT(status == 0, "Sync failed with status %u", status); + LOG_INF("Device %s: periodic synced %u status %u", addr_str, sync_handle, status); + + bsim_btp_wait_for_gap_periodic_biginfo(&ev_addr, &sid, &num_bis, &encryption); + bt_addr_le_to_str(&ev_addr, ev_addr_str, sizeof(ev_addr_str)); + TEST_ASSERT(bt_addr_le_eq(&remote_addr, &ev_addr), "%s != %s", addr_str, ev_addr_str); + LOG_INF("Device %s: BIGinfo sid %u num_bis %u enc %u", addr_str, sid, num_bis, encryption); + + bsim_btp_gap_big_create_sync(&remote_addr, sid, num_bis, BIT(0), 0x00, 0xFF, encryption, + broadcast_code); + + bsim_btp_wait_for_gap_bis_data_path_setup(&ev_addr, &bis_id); + bt_addr_le_to_str(&ev_addr, ev_addr_str, sizeof(ev_addr_str)); + TEST_ASSERT(bt_addr_le_eq(&remote_addr, &ev_addr), "%s != %s", addr_str, ev_addr_str); + LOG_INF("Device %s: Data path of BIS %u is setup", addr_str, bis_id); + + do { + net_buf_simple_reset(&bis_stream_rx); + bsim_btp_wait_for_gap_bis_stream_received(&bis_stream_rx); + TEST_ASSERT(bis_stream_rx.len >= sizeof(*ev)); + + ev = net_buf_simple_pull_mem(&bis_stream_rx, sizeof(*ev)); + bt_addr_le_to_str(&ev->address, ev_addr_str, sizeof(ev_addr_str)); + TEST_ASSERT(bt_addr_le_eq(&ev->address, &ev_addr)); + TEST_ASSERT(ev->bis_id == bis_id, "Invalid BIS %u != %u", ev->bis_id, bis_id); + LOG_INF("Device %s: BIS Stream RX BIS %u len %u flags %u TS %u seq_num %u", + addr_str, ev->bis_id, ev->data_len, ev->flags, ev->ts, ev->seq_num); + LOG_HEXDUMP_INF(bis_stream_rx.data, bis_stream_rx.len, "BIS Stream RX data: "); + } while (ev->data_len < 1); + + bsim_btp_wait_for_gap_periodic_sync_lost(&lost_sync_handle, &reason); + TEST_ASSERT(lost_sync_handle == sync_handle, "Sync lost handle mismatch %u != %u", + lost_sync_handle, sync_handle); + LOG_INF("Device %s: Periodic sync lost (reason %u)", addr_str, reason); + + TEST_PASS("PASSED\n"); +} + +static const struct bst_test_instance test_sample[] = { + { + .test_id = "iso_sync_receiver", + .test_descr = "Smoketest for the GAP ISO Sync receiver BT Tester behavior", + .test_main_f = test_iso_sync_receiver, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_iso_sync_receiver_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_sample); +} diff --git a/tests/bsim/bluetooth/tester/src/test_main.c b/tests/bsim/bluetooth/tester/src/test_main.c index ab6e4565e4c7b..9448750ea001a 100644 --- a/tests/bsim/bluetooth/tester/src/test_main.c +++ b/tests/bsim/bluetooth/tester/src/test_main.c @@ -7,28 +7,44 @@ #include "bstests.h" +extern struct bst_test_list *test_ccp_central_install(struct bst_test_list *tests); +extern struct bst_test_list *test_ccp_peripheral_install(struct bst_test_list *tests); extern struct bst_test_list *test_csip_central_install(struct bst_test_list *tests); extern struct bst_test_list *test_csip_peripheral_install(struct bst_test_list *tests); extern struct bst_test_list *test_gap_central_install(struct bst_test_list *tests); extern struct bst_test_list *test_gap_peripheral_install(struct bst_test_list *tests); extern struct bst_test_list *test_hap_central_install(struct bst_test_list *tests); extern struct bst_test_list *test_hap_peripheral_install(struct bst_test_list *tests); +extern struct bst_test_list *test_mcp_central_install(struct bst_test_list *tests); +extern struct bst_test_list *test_mcp_peripheral_install(struct bst_test_list *tests); extern struct bst_test_list *test_micp_central_install(struct bst_test_list *tests); extern struct bst_test_list *test_micp_peripheral_install(struct bst_test_list *tests); +extern struct bst_test_list *test_tmap_central_install(struct bst_test_list *tests); +extern struct bst_test_list *test_tmap_peripheral_install(struct bst_test_list *tests); extern struct bst_test_list *test_vcp_central_install(struct bst_test_list *tests); extern struct bst_test_list *test_vcp_peripheral_install(struct bst_test_list *tests); +extern struct bst_test_list *test_iso_broadcaster_install(struct bst_test_list *tests); +extern struct bst_test_list *test_iso_sync_receiver_install(struct bst_test_list *tests); bst_test_install_t test_installers[] = { + test_ccp_central_install, + test_ccp_peripheral_install, test_csip_central_install, test_csip_peripheral_install, test_gap_central_install, test_gap_peripheral_install, test_hap_central_install, test_hap_peripheral_install, + test_mcp_central_install, + test_mcp_peripheral_install, test_micp_central_install, test_micp_peripheral_install, + test_tmap_central_install, + test_tmap_peripheral_install, test_vcp_central_install, test_vcp_peripheral_install, + test_iso_broadcaster_install, + test_iso_sync_receiver_install, NULL, }; diff --git a/tests/bsim/bluetooth/tester/tests_scripts/ccp.sh b/tests/bsim/bluetooth/tester/tests_scripts/ccp.sh new file mode 100755 index 0000000000000..9cb3df5c2d1eb --- /dev/null +++ b/tests/bsim/bluetooth/tester/tests_scripts/ccp.sh @@ -0,0 +1,41 @@ +#!/usr/bin/env bash +# Copyright 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Smoketest for CCP BTP commands with the BT tester + +simulation_id="tester_ccp" +verbosity_level=2 +EXECUTE_TIMEOUT=100 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +cd ${BSIM_OUT_PATH}/bin + +UART_DIR=/tmp/bs_${USER}/${simulation_id}/ +UART_PER=${UART_DIR}/peripheral +UART_CEN=${UART_DIR}/central + +# Central BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_le_audio_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=10 -d=0 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_CEN}.tx -uart0_fifob_txfile=${UART_CEN}.rx + +# Central Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=21 -d=10 -RealEncryption=1 -testid=ccp_central \ + -nosim -uart0_fifob_rxfile=${UART_CEN}.rx -uart0_fifob_txfile=${UART_CEN}.tx + +# Peripheral BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_le_audio_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=32 -d=1 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_PER}.tx -uart0_fifob_txfile=${UART_PER}.rx + +# Peripheral Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=43 -d=11 -RealEncryption=1 -testid=ccp_peripheral \ + -nosim -uart0_fifob_rxfile=${UART_PER}.rx -uart0_fifob_txfile=${UART_PER}.tx + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=20e6 $@ + +wait_for_background_jobs # Wait for all programs in background and return != 0 if any fails diff --git a/tests/bsim/bluetooth/tester/tests_scripts/gap_iso.sh b/tests/bsim/bluetooth/tester/tests_scripts/gap_iso.sh new file mode 100755 index 0000000000000..a2df2db1e7072 --- /dev/null +++ b/tests/bsim/bluetooth/tester/tests_scripts/gap_iso.sh @@ -0,0 +1,43 @@ +#!/usr/bin/env bash +# Copyright 2024-2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Smoketest for GAP ISO BTP commands with the BT tester + +simulation_id="tester_gap_iso" +verbosity_level=2 +EXECUTE_TIMEOUT=100 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +cd ${BSIM_OUT_PATH}/bin + +UART_DIR=/tmp/bs_${USER}/${simulation_id}/ +UART_ISO_BROADCASTER=${UART_DIR}/broadcaster +UART_ISO_SYNC_RECEIVER=${UART_DIR}/sync_receiver + +# broadcaster BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=10 -d=0 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_ISO_BROADCASTER}.tx -uart0_fifob_txfile=${UART_ISO_BROADCASTER}.rx + +# broadcaster Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=21 -d=10 -RealEncryption=1 -testid=iso_broadcaster \ + -nosim -uart0_fifob_rxfile=${UART_ISO_BROADCASTER}.rx \ + -uart0_fifob_txfile=${UART_ISO_BROADCASTER}.tx + +# Sync receiver BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=32 -d=1 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_ISO_SYNC_RECEIVER}.tx -uart0_fifob_txfile=${UART_ISO_SYNC_RECEIVER}.rx + +# Sync receiver Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=43 -d=11 -RealEncryption=1 \ + -testid=iso_sync_receiver -nosim -uart0_fifob_rxfile=${UART_ISO_SYNC_RECEIVER}.rx \ + -uart0_fifob_txfile=${UART_ISO_SYNC_RECEIVER}.tx + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=20e6 $@ + +wait_for_background_jobs # Wait for all programs in background and return != 0 if any fails diff --git a/tests/bsim/bluetooth/tester/tests_scripts/mcp.sh b/tests/bsim/bluetooth/tester/tests_scripts/mcp.sh new file mode 100755 index 0000000000000..643a32234b0ea --- /dev/null +++ b/tests/bsim/bluetooth/tester/tests_scripts/mcp.sh @@ -0,0 +1,41 @@ +#!/usr/bin/env bash +# Copyright 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Smoketest for MCP BTP commands with the BT tester + +simulation_id="tester_mcp" +verbosity_level=2 +EXECUTE_TIMEOUT=100 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +cd ${BSIM_OUT_PATH}/bin + +UART_DIR=/tmp/bs_${USER}/${simulation_id}/ +UART_PER=${UART_DIR}/peripheral +UART_CEN=${UART_DIR}/central + +# Central BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_le_audio_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=10 -d=0 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_CEN}.tx -uart0_fifob_txfile=${UART_CEN}.rx + +# Central Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=21 -d=10 -RealEncryption=1 -testid=mcp_central \ + -nosim -uart0_fifob_rxfile=${UART_CEN}.rx -uart0_fifob_txfile=${UART_CEN}.tx + +# Peripheral BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_le_audio_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=32 -d=1 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_PER}.tx -uart0_fifob_txfile=${UART_PER}.rx + +# Peripheral Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=43 -d=11 -RealEncryption=1 -testid=mcp_peripheral \ + -nosim -uart0_fifob_rxfile=${UART_PER}.rx -uart0_fifob_txfile=${UART_PER}.tx + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=20e6 $@ + +wait_for_background_jobs # Wait for all programs in background and return != 0 if any fails diff --git a/tests/bsim/bluetooth/tester/tests_scripts/tmap.sh b/tests/bsim/bluetooth/tester/tests_scripts/tmap.sh new file mode 100755 index 0000000000000..d20719d53dfa8 --- /dev/null +++ b/tests/bsim/bluetooth/tester/tests_scripts/tmap.sh @@ -0,0 +1,41 @@ +#!/usr/bin/env bash +# Copyright 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Smoketest for TMAP BTP commands with the BT tester + +simulation_id="tester_tmap" +verbosity_level=2 +EXECUTE_TIMEOUT=100 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +cd ${BSIM_OUT_PATH}/bin + +UART_DIR=/tmp/bs_${USER}/${simulation_id}/ +UART_PER=${UART_DIR}/peripheral +UART_CEN=${UART_DIR}/central + +# Central BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_le_audio_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=10 -d=0 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_CEN}.tx -uart0_fifob_txfile=${UART_CEN}.rx + +# Central Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=21 -d=10 -RealEncryption=1 -testid=tmap_central \ + -nosim -uart0_fifob_rxfile=${UART_CEN}.rx -uart0_fifob_txfile=${UART_CEN}.tx + +# Peripheral BT Tester +Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_le_audio_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=32 -d=1 -RealEncryption=1 \ + -uart0_fifob_rxfile=${UART_PER}.tx -uart0_fifob_txfile=${UART_PER}.rx + +# Peripheral Upper Tester +Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -rs=43 -d=11 -RealEncryption=1 -testid=tmap_peripheral \ + -nosim -uart0_fifob_rxfile=${UART_PER}.rx -uart0_fifob_txfile=${UART_PER}.tx + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=20e6 $@ + +wait_for_background_jobs # Wait for all programs in background and return != 0 if any fails diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2-pinctrl.dtsi b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2-pinctrl.dtsi index da259040e9754..9579e7cb4a9a2 100644 --- a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2-pinctrl.dtsi +++ b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2-pinctrl.dtsi @@ -18,9 +18,9 @@ }; }; - /omit-if-no-ref/ uart4_default: uart4_default { - group1 { - pinmux = ; + /omit-if-no-ref/ uart4_default: uart4_default { + group1 { + pinmux = ; }; group2 { @@ -32,7 +32,7 @@ /omit-if-no-ref/ spi0_default: spi0_default { group1 { pinmux = , , - ; + ; }; group2 { pinmux = ; diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_64_two.dts b/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_64_two.dts index b3fc17d81fbd4..b84b64efa2029 100644 --- a/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_64_two.dts +++ b/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_64_two.dts @@ -9,6 +9,5 @@ / { /delete-node/ added-by-native-one; - added-by-native-two{ - }; + added-by-native-two {}; }; diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts b/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts index d12737469d2e6..ea1f76d6c7020 100644 --- a/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts +++ b/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts @@ -213,6 +213,5 @@ stack-size = <4096>; }; - added-by-native-one { - }; + added-by-native-one {}; }; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/bg29_rb4420a.overlay b/tests/drivers/adc/adc_accuracy_test/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..114d424308bd9 --- /dev/null +++ b/tests/drivers/adc/adc_accuracy_test/boards/bg29_rb4420a.overlay @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "dt-bindings/adc/silabs-adc.h" + +/ { + zephyr,user { + io-channels = <&adc0 4>; + reference-mv = <(1500 / 4)>; + expected-accuracy = <32>; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = ; + }; +}; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra2l1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra2l1.overlay index fb66167f36bde..9a8e447f493a2 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra2l1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra2l1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4c1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4c1.overlay index 71c6e206e6146..56adcfe5d20ec 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4c1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4c1.overlay @@ -12,7 +12,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.overlay index 33657ece6cb64..8a297ad40c01c 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.overlay index fb66167f36bde..9a8e447f493a2 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay index a202ba4d2c56d..b51174b04ca73 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra4e1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra4e1.overlay index fb66167f36bde..9a8e447f493a2 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra4e1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra4e1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay index ce9acbd1677e8..7211338ac6b3f 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.overlay @@ -17,7 +17,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay index 2a42c4e7d9a5f..7f497b9f94bdf 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay @@ -12,7 +12,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay index 5b93ce1011426..ff241d2836487 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay @@ -4,7 +4,7 @@ * Copyright 2024 NXP */ - /* Please connect voltage reference to J6.AN pin to run the test. */ +/* Please connect voltage reference to J6.AN pin to run the test. */ / { zephyr,user { diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.overlay index 69bc918b53207..8680185223996 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.overlay @@ -4,7 +4,7 @@ * Copyright 2024 NXP */ - /* Please connect voltage reference to J4 pin 1 to run the test. */ +/* Please connect voltage reference to J4 pin 1 to run the test. */ / { zephyr,user { diff --git a/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay index f3269f1c97020..6e74fafb26825 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay @@ -13,7 +13,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay index c42437571fe48..c4d51ffe8d7a8 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay @@ -4,7 +4,6 @@ * Copyright (c) 2024 Nordic Semiconductor ASA */ - / { zephyr,user { io-channels = <&adc 0>; @@ -25,5 +24,4 @@ zephyr,input-positive = ; /* P0.03 */ zephyr,resolution = <14>; }; - }; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/xg24_dk2601b.overlay b/tests/drivers/adc/adc_accuracy_test/boards/xg24_dk2601b.overlay index dd3463aecde28..8147998f1dada 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/xg24_dk2601b.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/xg24_dk2601b.overlay @@ -14,7 +14,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/xg27_dk2602a.overlay b/tests/drivers/adc/adc_accuracy_test/boards/xg27_dk2602a.overlay index dd3463aecde28..8147998f1dada 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/xg27_dk2602a.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/xg27_dk2602a.overlay @@ -14,7 +14,7 @@ }; }; -&adc0{ +&adc0 { #address-cells = <1>; #size-cells = <0>; diff --git a/tests/drivers/adc/adc_accuracy_test/boards/xg29_rb4412a.overlay b/tests/drivers/adc/adc_accuracy_test/boards/xg29_rb4412a.overlay index 0cde575193a3b..6843215a0c895 100644 --- a/tests/drivers/adc/adc_accuracy_test/boards/xg29_rb4412a.overlay +++ b/tests/drivers/adc/adc_accuracy_test/boards/xg29_rb4412a.overlay @@ -14,7 +14,7 @@ }; }; -&adc0{ +&adc0 { status = "okay"; #address-cells = <1>; #size-cells = <0>; diff --git a/tests/drivers/adc/adc_accuracy_test/testcase.yaml b/tests/drivers/adc/adc_accuracy_test/testcase.yaml index b3179bfd5ed15..03f122f9cdaae 100644 --- a/tests/drivers/adc/adc_accuracy_test/testcase.yaml +++ b/tests/drivers/adc/adc_accuracy_test/testcase.yaml @@ -43,6 +43,7 @@ tests: - xg24_rb4187c - xg27_dk2602a - xg29_rb4412a + - bg29_rb4420a integration_platforms: - frdm_kl25z - nrf54l15dk/nrf54l15/cpuapp diff --git a/tests/drivers/adc/adc_api/boards/bg29_rb4420a.overlay b/tests/drivers/adc/adc_api/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..76f95bb2ae849 --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/bg29_rb4420a.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "dt-bindings/adc/silabs-adc.h" + +/ { + zephyr,user { + io-channels = <&adc0 0>, <&adc0 1>; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = ; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = ; + }; +}; diff --git a/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay index f04139378c67d..669d95e1d632e 100644 --- a/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay @@ -7,7 +7,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index f04139378c67d..669d95e1d632e 100644 --- a/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -7,7 +7,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index f04139378c67d..669d95e1d632e 100644 --- a/tests/drivers/adc/adc_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -7,7 +7,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra2l1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra2l1.overlay index cc25530b5843b..e50356e6ce231 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra2l1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra2l1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 1>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4c1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4c1.overlay index 9aab1db0db5d2..5c94854365715 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra4c1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra4c1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4e2.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4e2.overlay index 987197ae02a05..d6ba2776ceb69 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra4e2.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra4e2.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4l1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4l1.overlay index cc25530b5843b..e50356e6ce231 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra4l1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra4l1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 1>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4m1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4m1.overlay index 9aab1db0db5d2..5c94854365715 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra4m1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra4m1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4m2.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4m2.overlay index 987197ae02a05..d6ba2776ceb69 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra4m2.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra4m2.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4m3.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4m3.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra4m3.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra4m3.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4w1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4w1.overlay index 6c6955106803e..b8c6367069a01 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra4w1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra4w1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 4>, <&adc0 6>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra6e2.overlay b/tests/drivers/adc/adc_api/boards/ek_ra6e2.overlay index 987197ae02a05..d6ba2776ceb69 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra6e2.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra6e2.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra6m1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra6m1.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra6m1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra6m1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra6m2.overlay b/tests/drivers/adc/adc_api/boards/ek_ra6m2.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra6m2.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra6m2.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra6m3.overlay b/tests/drivers/adc/adc_api/boards/ek_ra6m3.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra6m3.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra6m3.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra6m4.overlay b/tests/drivers/adc/adc_api/boards/ek_ra6m4.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra6m4.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra6m4.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra6m5.overlay b/tests/drivers/adc/adc_api/boards/ek_ra6m5.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra6m5.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra6m5.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra8d1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra8d1.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra8d1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra8d1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay +++ b/tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/esp32s3_devkitc_procpu.overlay b/tests/drivers/adc/adc_api/boards/esp32s3_devkitc_procpu.overlay index 3623819d7cbcb..22a7ac5bada20 100644 --- a/tests/drivers/adc/adc_api/boards/esp32s3_devkitc_procpu.overlay +++ b/tests/drivers/adc/adc_api/boards/esp32s3_devkitc_procpu.overlay @@ -5,34 +5,34 @@ */ / { - zephyr,user { - io-channels = <&adc0 0>, <&adc0 1>; - }; - }; + zephyr,user { + io-channels = <&adc0 0>, <&adc0 1>; + }; +}; - &adc0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; - channel@1 { - reg = <1>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; dmas = <&dma 2>; - }; +}; &dma { status = "okay"; diff --git a/tests/drivers/adc/adc_api/boards/esp32s3_devkitm_procpu.overlay b/tests/drivers/adc/adc_api/boards/esp32s3_devkitm_procpu.overlay index d57876e93ea1b..631ab93917024 100644 --- a/tests/drivers/adc/adc_api/boards/esp32s3_devkitm_procpu.overlay +++ b/tests/drivers/adc/adc_api/boards/esp32s3_devkitm_procpu.overlay @@ -5,35 +5,35 @@ */ / { - zephyr,user { - io-channels = <&adc0 9>, <&adc1 0>; - }; - }; + zephyr,user { + io-channels = <&adc0 9>, <&adc1 0>; + }; +}; - &adc0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - channel@9 { - reg = <9>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; - }; + channel@9 { + reg = <9>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; - &adc1 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&adc1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; - }; + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu.overlay b/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu.overlay index d57876e93ea1b..631ab93917024 100644 --- a/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu.overlay +++ b/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu.overlay @@ -5,35 +5,35 @@ */ / { - zephyr,user { - io-channels = <&adc0 9>, <&adc1 0>; - }; - }; + zephyr,user { + io-channels = <&adc0 9>, <&adc1 0>; + }; +}; - &adc0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - channel@9 { - reg = <9>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; - }; + channel@9 { + reg = <9>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; - &adc1 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&adc1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; - }; + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu_usb.overlay b/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu_usb.overlay index d57876e93ea1b..631ab93917024 100644 --- a/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu_usb.overlay +++ b/tests/drivers/adc/adc_api/boards/esp32s3_luatos_core_procpu_usb.overlay @@ -5,35 +5,35 @@ */ / { - zephyr,user { - io-channels = <&adc0 9>, <&adc1 0>; - }; - }; + zephyr,user { + io-channels = <&adc0 9>, <&adc1 0>; + }; +}; - &adc0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - channel@9 { - reg = <9>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; - }; + channel@9 { + reg = <9>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; - &adc1 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&adc1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1_4"; - zephyr,reference = "ADC_REF_INTERNAL"; - zephyr,acquisition-time = ; - zephyr,resolution = <12>; - }; - }; + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; diff --git a/tests/drivers/adc/adc_api/boards/fpb_ra4e1.overlay b/tests/drivers/adc/adc_api/boards/fpb_ra4e1.overlay index 9aab1db0db5d2..5c94854365715 100644 --- a/tests/drivers/adc/adc_api/boards/fpb_ra4e1.overlay +++ b/tests/drivers/adc/adc_api/boards/fpb_ra4e1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/fpb_ra6e1.overlay b/tests/drivers/adc/adc_api/boards/fpb_ra6e1.overlay index 987197ae02a05..d6ba2776ceb69 100644 --- a/tests/drivers/adc/adc_api/boards/fpb_ra6e1.overlay +++ b/tests/drivers/adc/adc_api/boards/fpb_ra6e1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/fpb_ra6e2.overlay b/tests/drivers/adc/adc_api/boards/fpb_ra6e2.overlay index 987197ae02a05..d6ba2776ceb69 100644 --- a/tests/drivers/adc/adc_api/boards/fpb_ra6e2.overlay +++ b/tests/drivers/adc/adc_api/boards/fpb_ra6e2.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/mck_ra8t1.overlay b/tests/drivers/adc/adc_api/boards/mck_ra8t1.overlay index 07924ac5c84ca..6eddf76a10556 100644 --- a/tests/drivers/adc/adc_api/boards/mck_ra8t1.overlay +++ b/tests/drivers/adc/adc_api/boards/mck_ra8t1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc1 0>, <&adc1 2>; diff --git a/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l05_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l05_cpuapp.overlay index 87707847eeab2..5248c25ae7a4a 100644 --- a/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l05_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l05_cpuapp.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l10_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l10_cpuapp.overlay index 87707847eeab2..5248c25ae7a4a 100644 --- a/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l10_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l10_cpuapp.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index 87707847eeab2..5248c25ae7a4a 100644 --- a/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay index f11e7ea0317c7..68a009fcb1715 100644 --- a/tests/drivers/adc/adc_api/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay b/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay index 7d7ff39af70d1..af99133e3b259 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_h743zi.overlay @@ -14,7 +14,7 @@ }; &sram2 { - zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >; + zephyr,memory-attr = ; }; &adc1 { diff --git a/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay b/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay index f29fa43278e8f..1a0660e7c7d9a 100644 --- a/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay +++ b/tests/drivers/adc/adc_api/boards/nucleo_l073rz.overlay @@ -12,7 +12,7 @@ }; &adc1 { - dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; dma-names = "dma"; pinctrl-0 = <&adc_in0_pa0 &adc_in1_pa1>; diff --git a/tests/drivers/adc/adc_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay index ab90118d232db..02c3c3158ae02 100644 --- a/tests/drivers/adc/adc_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/quill_nrf52840_mesh.overlay b/tests/drivers/adc/adc_api/boards/quill_nrf52840_mesh.overlay new file mode 100644 index 0000000000000..2af48efc4d1d4 --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/quill_nrf52840_mesh.overlay @@ -0,0 +1,7 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2023 Benjamin Björnsson + */ + +#include "nordic,nrf-saadc-common.dtsi" diff --git a/tests/drivers/adc/adc_api/boards/raytac_an54l15q_db_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/raytac_an54l15q_db_nrf54l15_cpuapp.overlay index 87707847eeab2..5248c25ae7a4a 100644 --- a/tests/drivers/adc/adc_api/boards/raytac_an54l15q_db_nrf54l15_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/raytac_an54l15q_db_nrf54l15_cpuapp.overlay @@ -6,7 +6,7 @@ / { zephyr,user { - io-channels = <&adc 0>, <&adc 1> , <&adc 2>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>; }; }; diff --git a/tests/drivers/adc/adc_api/boards/rza3ul_smarc.overlay b/tests/drivers/adc/adc_api/boards/rza3ul_smarc.overlay index 07a933707232e..0a27122fc5c74 100644 --- a/tests/drivers/adc/adc_api/boards/rza3ul_smarc.overlay +++ b/tests/drivers/adc/adc_api/boards/rza3ul_smarc.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc 0>, <&adc 1>; diff --git a/tests/drivers/adc/adc_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/adc/adc_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index 1d80e7ce4219a..18d10855a22bb 100644 --- a/tests/drivers/adc/adc_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/tests/drivers/adc/adc_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc 0>, <&adc 2>; diff --git a/tests/drivers/adc/adc_api/boards/rzn2l_rsk.overlay b/tests/drivers/adc/adc_api/boards/rzn2l_rsk.overlay index 538e8124da8cd..bbcbce74bb365 100644 --- a/tests/drivers/adc/adc_api/boards/rzn2l_rsk.overlay +++ b/tests/drivers/adc/adc_api/boards/rzn2l_rsk.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/adc/adc_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay index 538e8124da8cd..bbcbce74bb365 100644 --- a/tests/drivers/adc/adc_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay +++ b/tests/drivers/adc/adc_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc0 0>, <&adc0 2>; diff --git a/tests/drivers/adc/adc_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/adc/adc_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay index 517b5820bcc19..df36456d1cc92 100644 --- a/tests/drivers/adc/adc_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay +++ b/tests/drivers/adc/adc_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { zephyr,user { io-channels = <&adc 0>, <&adc 2>; diff --git a/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay b/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay index 6140352992bdf..32a2e6b37775c 100644 --- a/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay +++ b/tests/drivers/adc/adc_api/boards/stm32f3_disco.overlay @@ -12,7 +12,7 @@ }; &adc1 { - dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; + dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; dma-names = "dma"; pinctrl-0 = <&adc1_in1_pa0 &adc1_in2_pa1>; diff --git a/tests/drivers/adc/adc_api/boards/stm32f4_disco.overlay b/tests/drivers/adc/adc_api/boards/stm32f4_disco.overlay index 42eb2e4f68ab1..d3747ed096705 100644 --- a/tests/drivers/adc/adc_api/boards/stm32f4_disco.overlay +++ b/tests/drivers/adc/adc_api/boards/stm32f4_disco.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { zephyr,user { io-channels = <&adc1 1>, <&adc1 6>; }; diff --git a/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay b/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay index 683264ab20c48..8b80f3a7a4b46 100644 --- a/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay +++ b/tests/drivers/adc/adc_api/boards/stm32h573i_dk.overlay @@ -16,7 +16,7 @@ dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>; dma-names = "gpdma"; - pinctrl-0 = < &adc1_inp3_pa6 &adc1_inp6_pf12>; + pinctrl-0 = <&adc1_inp3_pa6 &adc1_inp6_pf12>; #address-cells = <1>; #size-cells = <0>; diff --git a/tests/drivers/adc/adc_api/boards/xiao_nrf54l15_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/xiao_nrf54l15_nrf54l15_cpuapp.overlay index a909ce75673f9..a9d3e6d45f625 100644 --- a/tests/drivers/adc/adc_api/boards/xiao_nrf54l15_nrf54l15_cpuapp.overlay +++ b/tests/drivers/adc/adc_api/boards/xiao_nrf54l15_nrf54l15_cpuapp.overlay @@ -7,6 +7,6 @@ / { zephyr,user { io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; }; }; diff --git a/tests/drivers/adc/adc_api/testcase.yaml b/tests/drivers/adc/adc_api/testcase.yaml index 652c3e12a85cb..cd90f5356a51e 100644 --- a/tests/drivers/adc/adc_api/testcase.yaml +++ b/tests/drivers/adc/adc_api/testcase.yaml @@ -9,14 +9,18 @@ tests: min_flash: 40 platform_exclude: - nucleo_u031r8 - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns + - panb611evb/nrf54l15/cpuapp + - panb611evb/nrf54l15/cpuapp/ns - nrf54l15dk/nrf54l15/cpuapp/ns - nrf54l15dk/nrf54l10/cpuapp/ns - bl54l15_dvk/nrf54l10/cpuapp/ns - bl54l15_dvk/nrf54l15/cpuapp/ns - bl54l15u_dvk/nrf54l15/cpuapp/ns - raytac_an54l15q_db/nrf54l15/cpuapp/ns + - rpi_pico/rp2040/mcuboot + - rpi_pico/rp2040/w/mcuboot + - rpi_pico2/rp2350a/m33/mcuboot + - rpi_pico2/rp2350a/m33/w/mcuboot drivers.adc.b_u585i_iot02a_adc4: extra_args: - DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay" diff --git a/tests/drivers/adc/adc_error_cases/boards/bg29_rb4420a.overlay b/tests/drivers/adc/adc_error_cases/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..707d618084d3d --- /dev/null +++ b/tests/drivers/adc/adc_error_cases/boards/bg29_rb4420a.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + adc = &adc0; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/tests/drivers/adc/adc_error_cases/boards/xg24_rb4187c.overlay b/tests/drivers/adc/adc_error_cases/boards/xg24_rb4187c.overlay new file mode 100644 index 0000000000000..707d618084d3d --- /dev/null +++ b/tests/drivers/adc/adc_error_cases/boards/xg24_rb4187c.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + adc = &adc0; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/tests/drivers/adc/adc_error_cases/boards/xg27_dk2602a.overlay b/tests/drivers/adc/adc_error_cases/boards/xg27_dk2602a.overlay new file mode 100644 index 0000000000000..707d618084d3d --- /dev/null +++ b/tests/drivers/adc/adc_error_cases/boards/xg27_dk2602a.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + adc = &adc0; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/tests/drivers/adc/adc_error_cases/boards/xg29_rb4412a.overlay b/tests/drivers/adc/adc_error_cases/boards/xg29_rb4412a.overlay new file mode 100644 index 0000000000000..707d618084d3d --- /dev/null +++ b/tests/drivers/adc/adc_error_cases/boards/xg29_rb4412a.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + adc = &adc0; + }; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/tests/drivers/adc/adc_error_cases/src/adc_error_cases.c b/tests/drivers/adc/adc_error_cases/src/adc_error_cases.c index 0cfdf890d7b74..754d2ad98d7bf 100644 --- a/tests/drivers/adc/adc_error_cases/src/adc_error_cases.c +++ b/tests/drivers/adc/adc_error_cases/src/adc_error_cases.c @@ -24,11 +24,17 @@ static const struct adc_channel_cfg valid_channel_cfg = { #endif }; +#if defined(CONFIG_SOC_FAMILY_SILABS_S2) +#define VALID_RESOLUTION 12 +#else +#define VALID_RESOLUTION 10 +#endif + static const struct adc_sequence valid_seq = { .buffer = m_sample_buffer, .buffer_size = BUFFER_LEN * sizeof(m_sample_buffer), .options = NULL, - .resolution = 10, + .resolution = VALID_RESOLUTION, .oversampling = 0, .channels = 1, }; diff --git a/tests/drivers/adc/adc_error_cases/testcase.yaml b/tests/drivers/adc/adc_error_cases/testcase.yaml index d9d389ab78adb..57513c78e156b 100644 --- a/tests/drivers/adc/adc_error_cases/testcase.yaml +++ b/tests/drivers/adc/adc_error_cases/testcase.yaml @@ -12,3 +12,7 @@ tests: - nrf54lm20dk/nrf54lm20a/cpuapp - nrf54h20dk/nrf54h20/cpuapp - ophelia4ev/nrf54l15/cpuapp + - xg24_rb4187c + - xg27_dk2602a + - xg29_rb4412a + - bg29_rb4420a diff --git a/tests/drivers/adc/adc_rescale/boards/native_sim.overlay b/tests/drivers/adc/adc_rescale/boards/native_sim.overlay index 5d18400d28992..423819f0382d8 100644 --- a/tests/drivers/adc/adc_rescale/boards/native_sim.overlay +++ b/tests/drivers/adc/adc_rescale/boards/native_sim.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { sensor0: vd { diff --git a/tests/drivers/build_all/adc/boards/native_sim.overlay b/tests/drivers/build_all/adc/boards/native_sim.overlay index a6ab0bdcf0eb3..e45e6b9d4a9b4 100644 --- a/tests/drivers/build_all/adc/boards/native_sim.overlay +++ b/tests/drivers/build_all/adc/boards/native_sim.overlay @@ -92,7 +92,7 @@ #io-channel-cells = <1>; }; - test_i2c_ltc2451: ltc2451@8{ + test_i2c_ltc2451: ltc2451@8 { compatible = "lltc,ltc2451"; reg = <0x8>; conversion-speed = <60>; @@ -274,7 +274,6 @@ #io-channel-cells = <1>; }; - test_spi_ads114s08: ads114s08@c { compatible = "ti,ads114s08"; reg = <0xc>; diff --git a/tests/drivers/build_all/adc/boards/qemu_cortex_m3.overlay b/tests/drivers/build_all/adc/boards/qemu_cortex_m3.overlay index 68632d4529de2..a17bc84368719 100644 --- a/tests/drivers/build_all/adc/boards/qemu_cortex_m3.overlay +++ b/tests/drivers/build_all/adc/boards/qemu_cortex_m3.overlay @@ -5,7 +5,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - /{ +/ { test_adc: adc@11112222 { reg = <0x11112222 0x1000>; compatible = "vnd,adc"; diff --git a/tests/drivers/build_all/bbram/app.overlay b/tests/drivers/build_all/bbram/app.overlay index 9143fb1bdf681..31d84c806b3f4 100644 --- a/tests/drivers/build_all/bbram/app.overlay +++ b/tests/drivers/build_all/bbram/app.overlay @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { test { diff --git a/tests/drivers/build_all/bbram/i2c.dtsi b/tests/drivers/build_all/bbram/i2c.dtsi index dbf06f7e39588..b0f84d63d207a 100644 --- a/tests/drivers/build_all/bbram/i2c.dtsi +++ b/tests/drivers/build_all/bbram/i2c.dtsi @@ -5,7 +5,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ mcp7940n@0 { compatible = "microchip,mcp7940n"; diff --git a/tests/drivers/build_all/charger/app.overlay b/tests/drivers/build_all/charger/app.overlay index 54267a7103b18..b2fda73fc8d1e 100644 --- a/tests/drivers/build_all/charger/app.overlay +++ b/tests/drivers/build_all/charger/app.overlay @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { test { diff --git a/tests/drivers/build_all/charger/i2c.dtsi b/tests/drivers/build_all/charger/i2c.dtsi index c10271a17ed05..cdd65b1764693 100644 --- a/tests/drivers/build_all/charger/i2c.dtsi +++ b/tests/drivers/build_all/charger/i2c.dtsi @@ -5,7 +5,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ bq24190@0 { compatible = "ti,bq24190"; diff --git a/tests/drivers/build_all/crypto/app.overlay b/tests/drivers/build_all/crypto/app.overlay index 9143fb1bdf681..31d84c806b3f4 100644 --- a/tests/drivers/build_all/crypto/app.overlay +++ b/tests/drivers/build_all/crypto/app.overlay @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { test { diff --git a/tests/drivers/build_all/crypto/i2c.dtsi b/tests/drivers/build_all/crypto/i2c.dtsi index 14ae11fb2c723..899da7baf286a 100644 --- a/tests/drivers/build_all/crypto/i2c.dtsi +++ b/tests/drivers/build_all/crypto/i2c.dtsi @@ -5,7 +5,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ ataes132a@0 { compatible = "atmel,ataes132a"; diff --git a/tests/drivers/build_all/dac/app.overlay b/tests/drivers/build_all/dac/app.overlay index 48148055ef2cd..fed8d2aca773b 100644 --- a/tests/drivers/build_all/dac/app.overlay +++ b/tests/drivers/build_all/dac/app.overlay @@ -69,7 +69,7 @@ power-down-mode = <0>; }; - test_i2c_dacx0501:dacx0501@62 { + test_i2c_dacx0501: dacx0501@62 { compatible = "ti,dacx0501"; status = "okay"; reg = <0x62>; @@ -81,21 +81,21 @@ status = "okay"; compatible = "adi,ad5691"; reg = <0x4a>; - #io-channel-cells = < 1 >; + #io-channel-cells = <1>; }; test_ad5692: ad5692@4b { status = "okay"; compatible = "adi,ad5692"; reg = <0x4b>; - #io-channel-cells = < 1 >; + #io-channel-cells = <1>; }; test_ad5693: ad5693@4c { status = "okay"; compatible = "adi,ad5693"; reg = <0x4c>; - #io-channel-cells = < 1 >; + #io-channel-cells = <1>; }; }; diff --git a/tests/drivers/build_all/display/app.overlay b/tests/drivers/build_all/display/app.overlay index bcc2fe2932800..99de4a9a12c30 100644 --- a/tests/drivers/build_all/display/app.overlay +++ b/tests/drivers/build_all/display/app.overlay @@ -203,7 +203,7 @@ compatible = "sinowealth,sh1122"; reg = <12>; mipi-max-frequency = <10000000>; - width = <256>; + width = <256>; height = <64>; oscillator-freq = <0>; multiplex-ratio = <0>; @@ -221,7 +221,7 @@ compatible = "solomon,ssd1331"; reg = <13>; mipi-max-frequency = <10000000>; - width = <96>; + width = <96>; height = <64>; display-offset = <0x0>; start-line = <0x0>; @@ -403,9 +403,9 @@ * include MIPI DBI devices as well. */ cs-gpios = <&test_gpio 0 0 &test_gpio 0 1 &test_gpio 0 2 - &test_gpio 0 3 &test_gpio 0 4 &test_gpio 0 5 - &test_gpio 0 6 &test_gpio 0 7 &test_gpio 0 8 - &test_gpio 0 9>; + &test_gpio 0 3 &test_gpio 0 4 &test_gpio 0 5 + &test_gpio 0 6 &test_gpio 0 7 &test_gpio 0 8 + &test_gpio 0 9>; test_led_strip_0: lpd8806@0 { compatible = "greeled,lpd8806"; @@ -463,28 +463,28 @@ start-from-right; }; - test_i2c:i2c@60013000{ + test_i2c: i2c@60013000 { #address-cells = <1>; #size-cells = <0>; - compatible="vnd,i2c"; + compatible = "vnd,i2c"; reg = <0x60013000 0x1000>; - status="okay"; - clock-frequency=<100000>; + status = "okay"; + clock-frequency = <100000>; - test_ist3931:ist3931@0 { - reg=<0x0>; - width=<64>; - height=<32>; + test_ist3931: ist3931@0 { + reg = <0x0>; + width = <64>; + height = <32>; compatible = "istech,ist3931"; - reset-gpios =<&test_gpio 1 0>; - x-offset=<0>; - y-offset=<32>; + reset-gpios = <&test_gpio 1 0>; + x-offset = <0>; + y-offset = <32>; voltage-converter; voltage-follower; - lcd-bias=<3>; - lcd-ct=<223>; - duty-ratio=<64>; - frame-control=<400>; + lcd-bias = <3>; + lcd-ct = <223>; + duty-ratio = <64>; + frame-control = <400>; reverse-com-output; }; @@ -530,7 +530,7 @@ test_sh1122: sh1122@4 { compatible = "sinowealth,sh1122"; reg = <4>; - width = <256>; + width = <256>; height = <64>; oscillator-freq = <0>; multiplex-ratio = <0>; diff --git a/tests/drivers/build_all/eeprom/app.overlay b/tests/drivers/build_all/eeprom/app.overlay index 999a0e859d8b3..fcc4bbe9e0852 100644 --- a/tests/drivers/build_all/eeprom/app.overlay +++ b/tests/drivers/build_all/eeprom/app.overlay @@ -10,8 +10,8 @@ * (and be extended to test) real hardware. */ - #include - #include +#include +#include / { test { diff --git a/tests/drivers/build_all/eeprom/boards/xg28_rb4401c.conf b/tests/drivers/build_all/eeprom/boards/xg28_rb4401c.conf new file mode 100644 index 0000000000000..49603736d45dc --- /dev/null +++ b/tests/drivers/build_all/eeprom/boards/xg28_rb4401c.conf @@ -0,0 +1 @@ +CONFIG_REGULATOR_FIXED_INIT_PRIORITY=55 diff --git a/tests/drivers/build_all/ethernet/spi_devices.overlay b/tests/drivers/build_all/ethernet/spi_devices.overlay index 568b0bd759e10..2ecb3d4f4422d 100644 --- a/tests/drivers/build_all/ethernet/spi_devices.overlay +++ b/tests/drivers/build_all/ethernet/spi_devices.overlay @@ -73,7 +73,7 @@ reset-gpios = <&test_gpio 0 0>; port1 { - local-mac-address = [ CA 2F B7 10 23 63 ]; + local-mac-address = [CA 2F B7 10 23 63]; }; mdio { @@ -98,10 +98,10 @@ reset-gpios = <&test_gpio 0 0>; port1 { - local-mac-address = [ CA 2F B7 10 23 63 ]; + local-mac-address = [CA 2F B7 10 23 63]; }; port2 { - local-mac-address = [ 3C 82 D4 A2 29 8E ]; + local-mac-address = [3C 82 D4 A2 29 8E]; }; mdio { diff --git a/tests/drivers/build_all/flash/spi.dtsi b/tests/drivers/build_all/flash/spi.dtsi index e2c36f8180cf8..197baa25e460d 100644 --- a/tests/drivers/build_all/flash/spi.dtsi +++ b/tests/drivers/build_all/flash/spi.dtsi @@ -24,3 +24,15 @@ spi-nor@1 { size = <1048576>; jedec-id = [00 11 22]; }; + +at25xv021a@2 { + compatible = "atmel,at25xv021a"; + reg = <0x2>; + status = "okay"; + spi-max-frequency = <5000000>; + jedec-id = [00 11 22]; + size = <262144>; + page-size = <1>; + timeout = <1>; + timeout-erase = <1>; +}; diff --git a/tests/drivers/build_all/fpga/app.overlay b/tests/drivers/build_all/fpga/app.overlay index 6135bfa57456b..8b968e15ba3e6 100644 --- a/tests/drivers/build_all/fpga/app.overlay +++ b/tests/drivers/build_all/fpga/app.overlay @@ -33,7 +33,7 @@ /* one entry for every devices at spi.dtsi */ cs-gpios = <&test_gpio 0 0>, /* 0x00 */ - <&test_gpio 0 0>; + <&test_gpio 0 0>; #include "spi.dtsi" }; diff --git a/tests/drivers/build_all/fuel_gauge/app.overlay b/tests/drivers/build_all/fuel_gauge/app.overlay index aa2c38db3ad88..92a24e0038594 100644 --- a/tests/drivers/build_all/fuel_gauge/app.overlay +++ b/tests/drivers/build_all/fuel_gauge/app.overlay @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { test { diff --git a/tests/drivers/build_all/fuel_gauge/i2c.dtsi b/tests/drivers/build_all/fuel_gauge/i2c.dtsi index bd01a7a4aaad0..597dae4eae72f 100644 --- a/tests/drivers/build_all/fuel_gauge/i2c.dtsi +++ b/tests/drivers/build_all/fuel_gauge/i2c.dtsi @@ -5,7 +5,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ max17048@0 { compatible = "maxim,max17048"; @@ -24,3 +25,30 @@ sbs-gauge-new-api@2 { reg = <0x2>; status = "okay"; }; + +axp2101@3 { + compatible = "x-powers,axp2101-fuel-gauge"; + reg = <0x3>; + status = "okay"; +}; + +lc709203f@4 { + compatible = "onnn,lc709203f"; + reg = <0x4>; + status = "okay"; + apa = "500mAh"; + battery-profile = <0x01>; + thermistor; +}; + +sy24561@5 { + compatible = "silergy,sy24561"; + reg = <0x5>; + status = "okay"; +}; + +bq40z50@6 { + compatible = "ti,bq40z50"; + reg = <0x6>; + status = "okay"; +}; diff --git a/tests/drivers/build_all/gpio/altera.overlay b/tests/drivers/build_all/gpio/altera.overlay index 2d92889aff49c..434d0d5cfba45 100644 --- a/tests/drivers/build_all/gpio/altera.overlay +++ b/tests/drivers/build_all/gpio/altera.overlay @@ -13,25 +13,24 @@ #address-cells = <1>; #size-cells = <1>; test_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - #address-cells = < 0x0 >; - #interrupt-cells = < 0x1 >; - interrupt-controller; - phandle = < 0x1 >; + compatible = "riscv,cpu-intc"; + #address-cells = <0x0>; + #interrupt-cells = <0x1>; + interrupt-controller; + phandle = <0x1>; }; test_gpio0: gpio@30070 { - interrupt-parent = < &test_intc >; + interrupt-parent = <&test_intc>; compatible = "altr,pio-1.0"; - reg = < 0x30070 0x10 >; + reg = <0x30070 0x10>; gpio-controller; - #gpio-cells = < 0x2 >; + #gpio-cells = <0x2>; status = "okay"; - ngpios = < 16 >; + ngpios = <16>; #direction = "input"; interrupts = <28>; }; }; }; - }; diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay index 367455b5f0dbe..84118e63a93a6 100644 --- a/tests/drivers/build_all/gpio/app.overlay +++ b/tests/drivers/build_all/gpio/app.overlay @@ -612,8 +612,8 @@ #gpio-cells = <2>; ngpios = <8>; max22190-mode = <1>; - filter-wbes = <1 0 1 0 1 0 1 0>; - filter-fbps = <0 0 0 0 0 0 0 0>; + filter-wbes = <1 0 1 0 1 0 1 0>; + filter-fbps = <0 0 0 0 0 0 0 0>; filter-delays = <50 100 400 800 1600 3200 12800 20000>; drdy-gpios = <&test_gpio 0 0>; fault-gpios = <&test_gpio 0 0>; @@ -629,7 +629,7 @@ #gpio-cells = <2>; ngpios = <8>; max22190-mode = <1>; - filter-fbps = <0 0 0 0 0 0 0 0>; + filter-fbps = <0 0 0 0 0 0 0 0>; filter-delays = <50 100 400 800 1600 3200 12800 20000>; drdy-gpios = <&test_gpio 0 0>; fault-gpios = <&test_gpio 0 0>; diff --git a/tests/drivers/build_all/gpio/iproc.overlay b/tests/drivers/build_all/gpio/iproc.overlay index 1150a9ffe466c..fe107be321e35 100644 --- a/tests/drivers/build_all/gpio/iproc.overlay +++ b/tests/drivers/build_all/gpio/iproc.overlay @@ -13,7 +13,7 @@ #size-cells = <1>; interrupt-parent = <&test_nvic>; - test_nvic: interrupt-controller@bbbbcccc { + test_nvic: interrupt-controller@bbbbcccc { compatible = "arm,v6m-nvic"; reg = <0xbbbbcccc 0xc00>; interrupt-controller; diff --git a/tests/drivers/build_all/haptics/app.overlay b/tests/drivers/build_all/haptics/app.overlay index a80b0cf280573..7566a78e382f4 100644 --- a/tests/drivers/build_all/haptics/app.overlay +++ b/tests/drivers/build_all/haptics/app.overlay @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { test { diff --git a/tests/drivers/build_all/haptics/i2c.dtsi b/tests/drivers/build_all/haptics/i2c.dtsi index a4fc6bb6c2b69..fbd13f4b4d02d 100644 --- a/tests/drivers/build_all/haptics/i2c.dtsi +++ b/tests/drivers/build_all/haptics/i2c.dtsi @@ -5,7 +5,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ drv2605@0 { compatible = "ti,drv2605"; diff --git a/tests/drivers/build_all/i2c/boards/qemu_cortex_m3.overlay b/tests/drivers/build_all/i2c/boards/qemu_cortex_m3.overlay index 634774441380e..6060194486cee 100644 --- a/tests/drivers/build_all/i2c/boards/qemu_cortex_m3.overlay +++ b/tests/drivers/build_all/i2c/boards/qemu_cortex_m3.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { i2c0: i2c@88888888 { @@ -26,8 +26,8 @@ }; i2c2: i2c@888A8888 { - compatible = "brcm,iproc-i2c"; - clock-frequency = ; + compatible = "brcm,iproc-i2c"; + clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x888A8888 0x100>; diff --git a/tests/drivers/build_all/ieee802154/boards/native_sim.overlay b/tests/drivers/build_all/ieee802154/boards/native_sim.overlay index 55ee3fd1d06b6..678f91489f885 100644 --- a/tests/drivers/build_all/ieee802154/boards/native_sim.overlay +++ b/tests/drivers/build_all/ieee802154/boards/native_sim.overlay @@ -37,7 +37,7 @@ reg = <0x0>; spi-max-frequency = <0>; int-gpios = <&test_gpio 0 0>; - status= "okay"; + status = "okay"; }; test_spi_cc2520: cc2520@1 { @@ -50,11 +50,11 @@ cca-gpios = <&test_gpio 0 0>; sfd-gpios = <&test_gpio 0 0>; fifop-gpios = <&test_gpio 0 0>; - status= "okay"; + status = "okay"; crypto { compatible = "ti,cc2520-crypto"; - status= "okay"; + status = "okay"; }; }; @@ -63,8 +63,8 @@ reg = <0x2>; spi-max-frequency = <0>; int-gpios = <&test_gpio 0 0>; - reset-gpios =<&test_gpio 0 0>; - status= "okay"; + reset-gpios = <&test_gpio 0 0>; + status = "okay"; }; test_spi_rf2xx: rf2xx@3 { diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay index b69cabc9081f8..c7c343b57931f 100644 --- a/tests/drivers/build_all/input/app.overlay +++ b/tests/drivers/build_all/input/app.overlay @@ -275,12 +275,12 @@ nunchuk@a { reg = <0xa>; - compatible= "nintendo,nunchuk"; + compatible = "nintendo,nunchuk"; }; cy8cmbr3xxx@b { compatible = "cypress,cy8cmbr3xxx"; - status= "okay"; + status = "okay"; reg = <0xb>; int-gpios = <&test_gpio 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; rst-gpios = <&test_gpio 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; diff --git a/tests/drivers/build_all/interrupt_controller/common/boards/imx8mp_evk_mimx8ml8_adsp.overlay b/tests/drivers/build_all/interrupt_controller/common/boards/imx8mp_evk_mimx8ml8_adsp.overlay index 9da8bafefc1a7..8e0ba6aad585a 100644 --- a/tests/drivers/build_all/interrupt_controller/common/boards/imx8mp_evk_mimx8ml8_adsp.overlay +++ b/tests/drivers/build_all/interrupt_controller/common/boards/imx8mp_evk_mimx8ml8_adsp.overlay @@ -9,7 +9,7 @@ * https://github.com/zephyrproject-rtos/zephyr/pull/62776#issuecomment-1727846332 */ - /{ +/ { soc { irqsteer: interrupt-controller@30a80000 { compatible = "nxp,irqsteer-intc"; @@ -19,11 +19,11 @@ #address-cells = <1>; master0: interrupt-controller@0 { - compatible = "nxp,irqsteer-master"; - reg = <0>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 19 0 0>; + compatible = "nxp,irqsteer-master"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 19 0 0>; }; master1: interrupt-controller@1 { diff --git a/tests/drivers/build_all/interrupt_controller/common/boards/intel_adsp_ace20_lnl.overlay b/tests/drivers/build_all/interrupt_controller/common/boards/intel_adsp_ace20_lnl.overlay index e0594ff091ac2..18c4ed9ac1d78 100644 --- a/tests/drivers/build_all/interrupt_controller/common/boards/intel_adsp_ace20_lnl.overlay +++ b/tests/drivers/build_all/interrupt_controller/common/boards/intel_adsp_ace20_lnl.overlay @@ -6,9 +6,9 @@ /* Made-up devicetree to build intc_dw.c */ - /{ +/ { soc { - dw_intc: dw_intc@7a000 { + dw_intc: dw_intc@7a000 { compatible = "snps,designware-intc"; reg = <0x7a000 0xc00>; interrupt-controller; diff --git a/tests/drivers/build_all/interrupt_controller/intc_plic/app.multi_instance.overlay b/tests/drivers/build_all/interrupt_controller/intc_plic/app.multi_instance.overlay index b509bf59d1efd..4327efa84b164 100644 --- a/tests/drivers/build_all/interrupt_controller/intc_plic/app.multi_instance.overlay +++ b/tests/drivers/build_all/interrupt_controller/intc_plic/app.multi_instance.overlay @@ -4,22 +4,20 @@ * SPDX-License-Identifier: Apache-2.0 */ - /{ +/ { soc { plic1: interrupt-controller@8000000 { riscv,max-priority = <7>; riscv,ndev = <0x35>; reg = <0x08000000 0x04000000>; - interrupts-extended = < - &hlic0 0x08 - &hlic1 0x08 - &hlic2 0x08 - &hlic3 0x08 - &hlic4 0x08 - &hlic5 0x08 - &hlic6 0x08 - &hlic7 0x08 - >; + interrupts-extended = <&hlic0 0x08 + &hlic1 0x08 + &hlic2 0x08 + &hlic3 0x08 + &hlic4 0x08 + &hlic5 0x08 + &hlic6 0x08 + &hlic7 0x08>; interrupt-controller; compatible = "sifive,plic-1.0.0"; #address-cells = <0x00>; diff --git a/tests/drivers/build_all/led_strip/app.overlay b/tests/drivers/build_all/led_strip/app.overlay index 3e91113543cfc..c5733c4c3ded5 100644 --- a/tests/drivers/build_all/led_strip/app.overlay +++ b/tests/drivers/build_all/led_strip/app.overlay @@ -78,8 +78,8 @@ chain-length = <1>; color-mapping = , - , - ; + , + ; spi-one-frame = <1>; spi-zero-frame = <2>; }; diff --git a/tests/drivers/build_all/lora/sx1262.overlay b/tests/drivers/build_all/lora/sx1262.overlay index 9809e95c33ec0..d9c64b03d3a0c 100644 --- a/tests/drivers/build_all/lora/sx1262.overlay +++ b/tests/drivers/build_all/lora/sx1262.overlay @@ -24,8 +24,8 @@ status = "okay"; cs-gpios = <&test_gpio 0 0>, - <&test_gpio 0 0>, - <&test_gpio 0 0>; + <&test_gpio 0 0>, + <&test_gpio 0 0>; test_semtech_sx1262: sx1262@0 { compatible = "semtech,sx1262"; diff --git a/tests/drivers/build_all/lora/sx1272.overlay b/tests/drivers/build_all/lora/sx1272.overlay index 0222be3c142ca..26aad5510cbba 100644 --- a/tests/drivers/build_all/lora/sx1272.overlay +++ b/tests/drivers/build_all/lora/sx1272.overlay @@ -24,8 +24,8 @@ status = "okay"; cs-gpios = <&test_gpio 0 0>, - <&test_gpio 0 0>, - <&test_gpio 0 0>; + <&test_gpio 0 0>, + <&test_gpio 0 0>; test_semtech_sx1272: sx1272@1 { compatible = "semtech,sx1272"; diff --git a/tests/drivers/build_all/pwm/boards/qemu_cortex_m3.overlay b/tests/drivers/build_all/pwm/boards/qemu_cortex_m3.overlay index a81ca63232169..7ec9857c8ab51 100644 --- a/tests/drivers/build_all/pwm/boards/qemu_cortex_m3.overlay +++ b/tests/drivers/build_all/pwm/boards/qemu_cortex_m3.overlay @@ -5,7 +5,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { test_pwm: pwm@11112222 { compatible = "vnd,pwm"; #pwm-cells = <3>; diff --git a/tests/drivers/build_all/pwm/max31790.overlay b/tests/drivers/build_all/pwm/max31790.overlay index 6163d6aa89028..6e30d9efc9b48 100644 --- a/tests/drivers/build_all/pwm/max31790.overlay +++ b/tests/drivers/build_all/pwm/max31790.overlay @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &arduino_i2c { +&arduino_i2c { status = "okay"; clock-frequency = ; diff --git a/tests/drivers/build_all/regulator/i2c.dtsi b/tests/drivers/build_all/regulator/i2c.dtsi index 4c8cb31958a54..e9c75ac0a1300 100644 --- a/tests/drivers/build_all/regulator/i2c.dtsi +++ b/tests/drivers/build_all/regulator/i2c.dtsi @@ -5,7 +5,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ pca9420@0 { compatible = "nxp,pca9420"; diff --git a/tests/drivers/build_all/rtc/i2c_devices.overlay b/tests/drivers/build_all/rtc/i2c_devices.overlay index 1c2758f9f8f6c..b734603c26325 100644 --- a/tests/drivers/build_all/rtc/i2c_devices.overlay +++ b/tests/drivers/build_all/rtc/i2c_devices.overlay @@ -13,7 +13,6 @@ gpio-controller; reg = <0xdeadbeef 0x1000>; #gpio-cells = <0x2>; - status = "okay"; }; test_i2c: i2c@11112222 { @@ -21,19 +20,16 @@ #size-cells = <0>; compatible = "vnd,i2c"; reg = <0x11112222 0x1000>; - status = "okay"; clock-frequency = <100000>; test_am1805: am1805@0 { compatible = "ambiq,am1805"; - status = "okay"; reg = <0x0>; am1805-gpios = <&test_gpio 0 0>; }; test_pcf8523: pcf8523@1 { compatible = "nxp,pcf8523"; - status = "okay"; reg = <0x1>; alarms-count = <1>; battery-switch-over = "standard"; @@ -42,13 +38,11 @@ test_pcf8563: pcf8563@2 { compatible = "nxp,pcf8563"; - status = "okay"; reg = <0x2>; }; test_rv3028: rv3028@3 { compatible = "microcrystal,rv3028"; - status = "okay"; reg = <0x3>; clkout-frequency = <1>; backup-switch-mode = "disabled"; @@ -58,7 +52,6 @@ test_rv8263: rv8263@4 { compatible = "microcrystal,rv-8263-c8"; - status = "okay"; reg = <0x4>; int-gpios = <&test_gpio 0 0>; clkout = <4096>; @@ -66,13 +59,11 @@ test_ds1307: ds1307@5 { compatible = "maxim,ds1307"; - status = "okay"; reg = <0x5>; }; test_rv8803: rv8803@6 { compatible = "microcrystal,rv8803"; - status = "okay"; reg = <0x6>; int-gpios = <&test_gpio 0 0>; clkout-frequency = <1024>; @@ -80,24 +71,32 @@ test_bq32002: bq32002@7 { compatible = "ti,bq32002"; - status = "okay"; reg = <0x7>; irq-frequency = <512>; }; test_rx8130ce: rx8130ce-rtc@8 { compatible = "epson,rx8130ce-rtc"; - status = "okay"; reg = <0x8>; irq-gpios = <&test_gpio 0 0>; }; test_ds1337: ds1337@9 { compatible = "maxim,ds1337"; - status = "okay"; reg = <0x9>; int-gpios = <&test_gpio 0 0>; sqw-frequency = <4096>; }; + + test_ds3231: ds3231@a { + compatible = "maxim,ds3231-mfd"; + reg = <0xa>; + + test_ds3231_rtc: ds3231_rtc { + compatible = "maxim,ds3231-rtc"; + isw-gpios = <&test_gpio 0 0>; + freq-32khz-gpios = <&test_gpio 0 0>; + }; + }; }; }; }; diff --git a/tests/drivers/build_all/sensor/adc.dtsi b/tests/drivers/build_all/sensor/adc.dtsi index fee588876e3c5..08ee520c6241b 100644 --- a/tests/drivers/build_all/sensor/adc.dtsi +++ b/tests/drivers/build_all/sensor/adc.dtsi @@ -7,7 +7,7 @@ * Application overlay for ADC devices */ - #include +#include test_adc_mcp9700a: mcp9700a { status = "okay"; diff --git a/tests/drivers/build_all/sensor/app.overlay b/tests/drivers/build_all/sensor/app.overlay index 5e5b3ef382b3e..ef18ab6bc4629 100644 --- a/tests/drivers/build_all/sensor/app.overlay +++ b/tests/drivers/build_all/sensor/app.overlay @@ -182,7 +182,6 @@ #include "i3c.dtsi" }; - }; }; diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index 4d21e08869593..fbbdf5402b231 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -29,7 +29,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ test_i2c_adt7420: adt7420@0 { compatible = "adi,adt7420"; @@ -528,14 +529,14 @@ test_i2c_itds_2533020201601: wsen_itds_2533020201601@4e { drdy-interrupt-gpios = <&test_gpio 0 0>; odr = "400"; tap-threshold = <0>, <0>, <6>; - tap-latency = < 5 >; - tap-shock = < 2 >; - tap-quiet = < 1 >; - tap-mode = < 1 >; - freefall-duration = < 6 >; - freefall-threshold = < 10 >; - delta-duration = < 1 >; - delta-threshold = < 4 >; + tap-latency = <5>; + tap-shock = <2>; + tap-quiet = <1>; + tap-mode = <1>; + freefall-duration = <6>; + freefall-threshold = <10>; + delta-duration = <1>; + delta-threshold = <4>; op-mode = "high-perf"; power-mode = "normal"; }; @@ -716,7 +717,7 @@ test_i2c_s11059: s11059@64 { test_i2c_wsen_pdus_25131308XXXXX: wsen_pdus_25131308XXXXX@65 { compatible = "we,wsen-pdus-25131308XXXXX"; reg = <0x65>; - sensor-type = < 4 >; + sensor-type = <4>; }; test_i2c_veml7700: veml7700@66 { @@ -1127,7 +1128,7 @@ test_i2c_mmc56x3: mmc56x3@97 { test_i2c_tmp1075: tmp1075@98 { compatible = "ti,tmp1075"; reg = <0x98>; - alert-gpios = <&test_gpio 0 0>; + alert-gpios = <&test_gpio 0 0>; conversion-rate = <220000>; lower-threshold = <27>; upper-threshold = <28>; @@ -1389,3 +1390,18 @@ test_i2c_mb7040: mb7040@ba { reg = <0xba>; status-gpios = <&test_gpio 0 0>; }; + +test_i2c_wsen_isds_2536030320001: wsen_isds_2536030320001@bb { + compatible = "we,wsen-isds-2536030320001"; + reg = <0xbb>; + accel-odr = "416"; + gyro-odr = "416"; + tap-threshold = <9>; + tap-latency = <5>; + tap-shock = <2>; + tap-quiet = <1>; + tap-mode = <1>; + tap-axis-enable = <0 0 1>; + events-interrupt-gpios = <&test_gpio 0 0>; + drdy-interrupt-gpios = <&test_gpio 0 0>; +}; diff --git a/tests/drivers/build_all/sensor/i3c.dtsi b/tests/drivers/build_all/sensor/i3c.dtsi index 8f1dc12ce45a0..97de324de86e6 100644 --- a/tests/drivers/build_all/sensor/i3c.dtsi +++ b/tests/drivers/build_all/sensor/i3c.dtsi @@ -8,7 +8,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ test_i3c_lps22hh: lps22hh@100000803E0000001 { compatible = "st,lps22hh"; diff --git a/tests/drivers/build_all/sensor/sensors_trigger_global.conf b/tests/drivers/build_all/sensor/sensors_trigger_global.conf index 7e38af6795914..bf4023369a49c 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_global.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_global.conf @@ -70,6 +70,7 @@ CONFIG_TSL2540_TRIGGER_GLOBAL_THREAD=y CONFIG_TSL2591_TRIGGER_GLOBAL_THREAD=y CONFIG_VCNL36825T_TRIGGER_GLOBAL_THREAD=y CONFIG_VCNL4040_TRIGGER_GLOBAL_THREAD=y +CONFIG_WSEN_ISDS_2536030320001_TRIGGER_GLOBAL_THREAD=y CONFIG_WSEN_ITDS_2533020201601_TRIGGER_GLOBAL_THREAD=y CONFIG_WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD=y CONFIG_WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_none.conf b/tests/drivers/build_all/sensor/sensors_trigger_none.conf index 37a82d60c0378..15034a0983715 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_none.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_none.conf @@ -72,6 +72,7 @@ CONFIG_TSL2540_TRIGGER_NONE=y CONFIG_TSL2591_TRIGGER_NONE=y CONFIG_VCNL36825T_TRIGGER_NONE=y CONFIG_VCNL4040_TRIGGER_NONE=y +CONFIG_WSEN_ISDS_2536030320001_TRIGGER_NONE=y CONFIG_WSEN_ITDS_2533020201601_TRIGGER_NONE=y CONFIG_WSEN_PADS_2511020213301_TRIGGER_NONE=y CONFIG_WSEN_TIDS_2521020222501_TRIGGER_NONE=y diff --git a/tests/drivers/build_all/sensor/sensors_trigger_own.conf b/tests/drivers/build_all/sensor/sensors_trigger_own.conf index 50b9bd1e7b6cc..0bfd6668d5906 100644 --- a/tests/drivers/build_all/sensor/sensors_trigger_own.conf +++ b/tests/drivers/build_all/sensor/sensors_trigger_own.conf @@ -68,6 +68,7 @@ CONFIG_TSL2540_TRIGGER_OWN_THREAD=y CONFIG_TSL2591_TRIGGER_OWN_THREAD=y CONFIG_VCNL36825T_TRIGGER_OWN_THREAD=y CONFIG_VCNL4040_TRIGGER_OWN_THREAD=y +CONFIG_WSEN_ISDS_2536030320001_TRIGGER_OWN_THREAD=y CONFIG_WSEN_ITDS_2533020201601_TRIGGER_OWN_THREAD=y CONFIG_WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD=y CONFIG_WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD=y diff --git a/tests/drivers/build_all/sensor/spi.dtsi b/tests/drivers/build_all/sensor/spi.dtsi index efa60f5e50908..2f6d38c08c2f7 100644 --- a/tests/drivers/build_all/sensor/spi.dtsi +++ b/tests/drivers/build_all/sensor/spi.dtsi @@ -10,7 +10,8 @@ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ test_spi_adxl362: adxl362@0 { compatible = "adi,adxl362"; @@ -402,7 +403,7 @@ test_spi_ilps22qs: ilps22qs@30 { status = "okay"; }; -test_spi_icm45686:icm45686@31 { +test_spi_icm45686: icm45686@31 { compatible = "invensense,icm45686"; reg = <0x31>; spi-max-frequency = <0>; @@ -436,9 +437,9 @@ test_spi_ad2s1210: ad2s1210@35 { compatible = "adi,ad2s1210"; reg = <0x35>; spi-max-frequency = <0>; - sample-gpios = <&test_gpio 0 (GPIO_ACTIVE_LOW)>; - mode-gpios = <&test_gpio 1 (GPIO_ACTIVE_HIGH)>, <&test_gpio 2 (GPIO_ACTIVE_HIGH)>; - reset-gpios = <&test_gpio 7 (GPIO_ACTIVE_LOW)>; + sample-gpios = <&test_gpio 0 GPIO_ACTIVE_LOW>; + mode-gpios = <&test_gpio 1 GPIO_ACTIVE_HIGH>, <&test_gpio 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&test_gpio 7 GPIO_ACTIVE_LOW>; clock-frequency = <8192000>; }; diff --git a/tests/drivers/build_all/sensor/uart.dtsi b/tests/drivers/build_all/sensor/uart.dtsi index 909a88b78b9e5..0c44fdcee2c7f 100644 --- a/tests/drivers/build_all/sensor/uart.dtsi +++ b/tests/drivers/build_all/sensor/uart.dtsi @@ -18,8 +18,8 @@ test_uart_pms7003: pms7003 { }; grow_r502a { - #address-cells=<1>; - #size-cells=<0>; + #address-cells = <1>; + #size-cells = <0>; test_uart_grow_r502a: grow_r502a@0 { compatible = "hzgrow,r502a"; reg = <0x0>; diff --git a/tests/drivers/build_all/stepper/gpio.dtsi b/tests/drivers/build_all/stepper/gpio.dtsi index 6fe38b0ca30cd..d0d7e79a9c686 100644 --- a/tests/drivers/build_all/stepper/gpio.dtsi +++ b/tests/drivers/build_all/stepper/gpio.dtsi @@ -5,7 +5,8 @@ /**************************************** * PLEASE KEEP ALPHABETICALLY SORTED * - ***************************************/ + ************************************** + */ adi_tmc2209: adi_tmc2209 { compatible = "adi,tmc2209"; @@ -39,7 +40,7 @@ ti_drv84xx: ti_drv84xx { dir-gpios = <&test_gpio 0 0>; step-gpios = <&test_gpio 0 0>; sleep-gpios = <&test_gpio 0 0>; - en-gpios = <&test_gpio 0 0>; + en-gpios = <&test_gpio 0 0>; m0-gpios = <&test_gpio 0 0>; m1-gpios = <&test_gpio 0 0>; counter = <&counter0>; diff --git a/tests/drivers/build_all/stepper/spi.dtsi b/tests/drivers/build_all/stepper/spi.dtsi index 0f6bfbc13db3e..400be1f84669f 100644 --- a/tests/drivers/build_all/stepper/spi.dtsi +++ b/tests/drivers/build_all/stepper/spi.dtsi @@ -4,7 +4,8 @@ */ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ adi_tmc50xx: adi_tmc50xx@0 { compatible = "adi,tmc50xx"; @@ -16,7 +17,9 @@ adi_tmc50xx: adi_tmc50xx@0 { #address-cells = <1>; #size-cells = <0>; - poscmp-enable; test-mode; lock-gconf; /* ADI TMC Global configuration flags */ + poscmp-enable; + test-mode; + lock-gconf; /* ADI TMC Global configuration flags */ clock-frequency = <16000000>; /* Internal/External Clock frequency */ tmc50xx_0: tmc50xx_0@0 { @@ -29,9 +32,9 @@ adi_tmc50xx: adi_tmc50xx@0 { /* ADI TMC stallguard settings specific to TMC50XX */ activate-stallguard2; - stallguard-velocity-check-interval-ms=<100>; - stallguard2-threshold=<9>; - stallguard-threshold-velocity=<500000>; + stallguard-velocity-check-interval-ms = <100>; + stallguard2-threshold = <9>; + stallguard-threshold-velocity = <500000>; /* ADI TMC ramp generator as well as current settings */ vstart = <10>; @@ -59,9 +62,9 @@ adi_tmc50xx: adi_tmc50xx@0 { /* ADI TMC stallguard settings specific to TMC50XX */ activate-stallguard2; - stallguard-velocity-check-interval-ms=<100>; - stallguard2-threshold=<9>; - stallguard-threshold-velocity=<500000>; + stallguard-velocity-check-interval-ms = <100>; + stallguard2-threshold = <9>; + stallguard-threshold-velocity = <500000>; /* ADI TMC ramp generator as well as current settings */ vstart = <10>; @@ -90,7 +93,8 @@ adi_tmc51xx_1: adi_tmc51xx@1 { #address-cells = <1>; #size-cells = <0>; - en-pwm-mode; test-mode; /* ADI TMC Global configuration flags */ + en-pwm-mode; + test-mode; /* ADI TMC Global configuration flags */ clock-frequency = <16000000>; /* Internal/External Clock frequency */ /* common stepper controller settings */ @@ -132,7 +136,8 @@ adi_tmc51xx_2: adi_tmc51xx@2 { #size-cells = <0>; diag0-gpios = <&test_gpio 0x01 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* DIAG pin @0x01 */ - en-pwm-mode; test-mode; /* ADI TMC Global configuration flags */ + en-pwm-mode; + test-mode; /* ADI TMC Global configuration flags */ clock-frequency = <16000000>; /* Internal/External Clock frequency */ /* common stepper controller settings */ diff --git a/tests/drivers/build_all/stepper/uart.dtsi b/tests/drivers/build_all/stepper/uart.dtsi index e2116bae1f423..35480e08f61f7 100644 --- a/tests/drivers/build_all/stepper/uart.dtsi +++ b/tests/drivers/build_all/stepper/uart.dtsi @@ -4,7 +4,8 @@ */ /**************************************** * PLEASE KEEP REG ADDRESSES SEQUENTIAL * - ***************************************/ + ************************************** + */ adi_tmc51xx_uart: adi_tmc51xx { compatible = "adi,tmc51xx"; @@ -12,7 +13,8 @@ adi_tmc51xx_uart: adi_tmc51xx { label = "tmc5160_uart_1"; - en-pwm-mode; test-mode; /* ADI TMC Global configuration flags */ + en-pwm-mode; + test-mode; /* ADI TMC Global configuration flags */ clock-frequency = <16000000>; /* Internal/External Clock frequency */ /* common stepper controller settings */ diff --git a/tests/drivers/build_all/video/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/build_all/video/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay index 3e628f79ac387..808a74ea608e6 100644 --- a/tests/drivers/build_all/video/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay +++ b/tests/drivers/build_all/video/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -66,8 +66,8 @@ reg = <0x33334444 0x200>; status = "okay"; clocks = <&ccm IMX_CCM_MIPI_CSI2RX_ROOT_CLK 0 0>, - <&ccm IMX_CCM_MIPI_CSI2RX_UI_CLK 0 0>, - <&ccm IMX_CCM_MIPI_CSI2RX_ESC_CLK 0 0>; + <&ccm IMX_CCM_MIPI_CSI2RX_UI_CLK 0 0>, + <&ccm IMX_CCM_MIPI_CSI2RX_ESC_CLK 0 0>; ports { #address-cells = <1>; diff --git a/tests/drivers/can/api/twai-enable.overlay b/tests/drivers/can/api/twai-enable.overlay index 7a4ee3b7daf4e..cf7e193979d18 100644 --- a/tests/drivers/can/api/twai-enable.overlay +++ b/tests/drivers/can/api/twai-enable.overlay @@ -25,5 +25,5 @@ pinmux = ; input-enable; /* enable internal loopback */ }; -}; + }; }; diff --git a/tests/drivers/can/host/README.rst b/tests/drivers/can/host/README.rst index 946dcf7f13321..5cba916954b28 100644 --- a/tests/drivers/can/host/README.rst +++ b/tests/drivers/can/host/README.rst @@ -28,7 +28,7 @@ The Zephyr end of the CAN fixture can be configured as follows: The host end of the CAN fixture can be configured through python-can. Available configuration options depend on the type of host CAN adapter used. The python-can library provides a lot of -flexibility for configuration as decribed in the `python-can configuration`_ page, all centered +flexibility for configuration as described in the `python-can configuration`_ page, all centered around the concept of a configuration "context. The configuration context for this test suite can be configured as follows: @@ -46,7 +46,7 @@ Building and Running Running on native_sim ===================== -Running the test suite on :ref:`native_sim` relies on the `Linux SocketCAN`_ virtual CAN driver +Running the test suite on :zephyr:board:`native_sim` relies on the `Linux SocketCAN`_ virtual CAN driver (vcan) providing a virtual CAN interface named ``zcan0``. On the host PC, a virtual SocketCAN interface needs to be created and brought up before running the diff --git a/tests/drivers/can/shell/app.overlay b/tests/drivers/can/shell/app.overlay index 1de44e0e9c5ed..34185ab6dad76 100644 --- a/tests/drivers/can/shell/app.overlay +++ b/tests/drivers/can/shell/app.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { fake_can: fake_can { compatible = "zephyr,fake-can"; status = "okay"; diff --git a/tests/drivers/clock_control/clock_control_api/Kconfig b/tests/drivers/clock_control/clock_control_api/Kconfig index dc1e976d824c1..9315f3e337bcd 100644 --- a/tests/drivers/clock_control/clock_control_api/Kconfig +++ b/tests/drivers/clock_control/clock_control_api/Kconfig @@ -3,7 +3,7 @@ config TEST_NRF_HF_STARTUP_TIME_US int "Delay required for HF clock startup." - default 3000 if CONFIG_SOC_SERIES_NRF91X + default 3000 if SOC_SERIES_NRF91X default 500 depends on SOC_FAMILY_NORDIC_NRF help diff --git a/tests/drivers/clock_control/clock_control_api/testcase.yaml b/tests/drivers/clock_control/clock_control_api/testcase.yaml index 4578b42828276..d3c2669641fc2 100644 --- a/tests/drivers/clock_control/clock_control_api/testcase.yaml +++ b/tests/drivers/clock_control/clock_control_api/testcase.yaml @@ -13,6 +13,7 @@ tests: - xg24_dk2601b - xg27_dk2602a - xg29_rb4412a + - bg29_rb4420a integration_platforms: - esp32_devkitc/esp32/procpu drivers.clock.clock_control_nrf5: diff --git a/tests/drivers/clock_control/fixed_clock/app.overlay b/tests/drivers/clock_control/fixed_clock/app.overlay index 913b32176f155..ccf373699fe26 100644 --- a/tests/drivers/clock_control/fixed_clock/app.overlay +++ b/tests/drivers/clock_control/fixed_clock/app.overlay @@ -12,6 +12,5 @@ clock-frequency = <100>; #clock-cells = <0>; }; - }; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_2.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_2.overlay index 29b6a2df8db58..8fa3fe3d9fb86 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_2.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_2.overlay @@ -1,4 +1,4 @@ - /* +/* * Copyright (c) 2022 STMicroelectronics * * SPDX-License-Identifier: Apache-2.0 diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_4.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_4.overlay index ff9eac49dcaec..37fab67caf713 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_4.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hsi_g0_16_div_4.overlay @@ -1,4 +1,4 @@ - /* +/* * Copyright (c) 2022 STMicroelectronics * * SPDX-License-Identifier: Apache-2.0 diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/l0_pll_32_hsi_16.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/l0_pll_32_hsi_16.overlay new file mode 100644 index 0000000000000..36896295ca7c5 --- /dev/null +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/l0_pll_32_hsi_16.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Warning: This overlay performs configuration from clean sheet. + * It is assumed that it is applied after clear_clocks.overlay file. + */ + +&clk_hsi { + hsi-div = <1>; + status = "okay"; +}; + +&pll { + div = <2>; + mul = <4>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; +}; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/testcase.yaml index dbc0f6722eaa5..08b84a6577f92 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/testcase.yaml +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/testcase.yaml @@ -133,11 +133,16 @@ tests: - nucleo_l073rz integration_platforms: - nucleo_l152re - drivers.clock.stm32_clock_configuration.common_core.l0_l1.sysclksrc_pll_32_hsi_16: + drivers.clock.stm32_clock_configuration.common_core.l0.sysclksrc_pll_32_hsi_16: + extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/l0_pll_32_hsi_16.overlay" + platform_allow: + - nucleo_l073rz + integration_platforms: + - nucleo_l073rz + drivers.clock.stm32_clock_configuration.common_core.l1.sysclksrc_pll_32_hsi_16: extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_32_hsi_16.overlay" platform_allow: - nucleo_l152re - - nucleo_l073rz integration_platforms: - nucleo_l152re drivers.clock.stm32_clock_configuration.common_core.l0_l1.sysclksrc_msi_range6: diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay index cff0687871a9e..f05e3af777ba7 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay @@ -40,7 +40,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -65,7 +64,7 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>; + <&rcc STM32_SRC_HSI I2C1_SEL(2)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay index cff0687871a9e..f05e3af777ba7 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay @@ -40,7 +40,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -65,7 +64,7 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>; + <&rcc STM32_SRC_HSI I2C1_SEL(2)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay index 1efaf4793264c..529877847332c 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_sdmmc48_pll.overlay @@ -7,7 +7,7 @@ /* Node is disabled by default unless the PLL_I2S is enabled */ &clk48 { /* select one source for the clk48MHz domain clock */ -/* clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;*/ + /* clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;*/ clocks = <&rcc STM32_SRC_PLLI2S_Q CK48M_SEL(1)>; status = "okay"; }; @@ -22,13 +22,13 @@ }; &sdmmc1 { - clocks = <&rcc STM32_CLOCK(APB2, 11U)>, - /* select one source for the sdmmc domain clock */ + clocks = <&rcc STM32_CLOCK(APB2, 11)>, + /* select one source for the sdmmc domain clock */ <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>; -/* <&rcc STM32_SRC_CK48 SDIO_SEL(0)>; */ + /* <&rcc STM32_SRC_CK48 SDIO_SEL(0)>; */ pinctrl-0 = <&sdio_cmd_pa6 &sdio_ck_pc12 - &sdio_d0_pc8 &sdio_d1_pc9 - &sdio_d2_pc10 &sdio_d3_pc11>; + &sdio_d0_pc8 &sdio_d1_pc9 + &sdio_d2_pc10 &sdio_d3_pc11>; pinctrl-names = "default"; status = "okay"; disk-name = "SD"; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay index ee2d70a1e00fa..f2f8fe6d5e4fd 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay @@ -33,7 +33,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -66,18 +65,18 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>; + <&rcc STM32_SRC_HSI I2C1_SEL(2)>; status = "okay"; }; &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; + <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; status = "okay"; }; &adc1 { clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>, - <&rcc STM32_SRC_PLL_P ADC_SEL(1)>; + <&rcc STM32_SRC_PLL_P ADC_SEL(1)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay index 00dedf05c8640..3f2d616179d6d 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay @@ -33,7 +33,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -66,13 +65,13 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; + <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; status = "okay"; }; &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; + <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay index 7f6bd50f3be44..8c3d46634a56a 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi_adc1_pllp.overlay @@ -33,7 +33,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -62,13 +61,13 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>; + <&rcc STM32_SRC_HSI I2C1_SEL(2)>; status = "okay"; }; &adc1 { /* changes clock source for both ADC1 and ADC2 */ clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>, - <&rcc STM32_SRC_PLL_P ADC12_SEL(1)>; + <&rcc STM32_SRC_PLL_P ADC12_SEL(1)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay index 5a9d44aca829c..499914b3f133d 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_hsi_lptim1_lse.overlay @@ -38,7 +38,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -73,14 +72,14 @@ /delete-property/ clocks; /* an extra clock at index 2 to check if switching clocks works */ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>, - <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; + <&rcc STM32_SRC_HSI I2C1_SEL(2)>, + <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; status = "okay"; }; &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; + <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay index d96ebeab433c7..e9abed0f64030 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/l4_i2c1_sysclk_lptim1_lsi.overlay @@ -38,7 +38,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -73,14 +72,14 @@ /delete-property/ clocks; /* an extra clock at index 2 to check if switching clocks works */ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>; + <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>, + <&rcc STM32_SRC_HSI I2C1_SEL(2)>; status = "okay"; }; &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; + <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay index e596c6ea891b8..d1351bef876ec 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_hsi_lptim1_lse.overlay @@ -41,7 +41,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -72,13 +71,13 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>; + <&rcc STM32_SRC_HSI I2C1_SEL(2)>; status = "okay"; }; &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; + <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay index 9ec7434937f52..bd3818dab7e9d 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wb_i2c1_sysclk_lptim1_lsi.overlay @@ -41,7 +41,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -72,7 +71,7 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; + <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay index 1629509215e5f..d05075de3e982 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay @@ -41,7 +41,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -83,7 +82,7 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_HSI I2C1_SEL(2)>; + <&rcc STM32_SRC_HSI I2C1_SEL(2)>; pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; pinctrl-names = "default"; status = "okay"; @@ -91,12 +90,12 @@ &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; + <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; status = "okay"; }; &adc1 { clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>, - <&rcc STM32_SRC_PLL_P ADC_SEL(2)>; + <&rcc STM32_SRC_PLL_P ADC_SEL(2)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay index 4775abeb66102..bba90120ce338 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/wl_i2c1_sysclk_lptim1_lsi.overlay @@ -41,7 +41,6 @@ /delete-property/ clock-frequency; }; - /* Core set up * Aim of this part is to provide a base working clock config */ @@ -69,7 +68,7 @@ &i2c1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>, - <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; + <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; pinctrl-names = "default"; status = "okay"; @@ -77,7 +76,7 @@ &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; + <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay index c8e47ac5c471a..f4970e6899223 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay @@ -17,7 +17,7 @@ &usart1 { clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>, - <&rcc STM32_SRC_CSI USART1_SEL(4)>; + <&rcc STM32_SRC_CSI USART1_SEL(4)>; }; &clk_hse { @@ -45,7 +45,6 @@ status = "disabled"; }; - &pll2 { /delete-property/ div-m; /delete-property/ mul-n; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/core_init.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/core_init.overlay index 4648a23ec7474..342266e67df1f 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/core_init.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/core_init.overlay @@ -9,7 +9,6 @@ * be found in stm32h7.dtsi */ - /* Clocks clean up config * Aim is to avoid conflict with specific default board configuration */ diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/core_init.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/core_init.overlay index f0f50c54d8c70..0a32238e0878b 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/core_init.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/core_init.overlay @@ -9,7 +9,6 @@ * be found in stm32h7.dtsi */ - /* Clocks clean up config * Aim is to avoid conflict with specific default board configuration */ diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_hsi_16.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_hsi_16.overlay index dd2f8fb132e46..f1e318b57a237 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_hsi_16.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_hsi_16.overlay @@ -16,6 +16,6 @@ &spi1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, - <&rcc STM32_SRC_HSI16 SPI1_SEL(2)>; + <&rcc STM32_SRC_HSI16 SPI1_SEL(2)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_msik.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_msik.overlay index 60d7bdaf561c1..e431fd3979644 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_msik.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_msik.overlay @@ -18,6 +18,6 @@ &spi1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, - <&rcc STM32_SRC_MSIK SPI1_SEL(3)>; + <&rcc STM32_SRC_MSIK SPI1_SEL(3)>; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_sysclk.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_sysclk.overlay index 96bb9b308d5ae..c1ad5a2666f78 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_sysclk.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_sysclk.overlay @@ -12,6 +12,6 @@ &spi1 { /delete-property/ clocks; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, - <&rcc STM32_SRC_SYSCLK SPI1_SEL(1)>; + <&rcc STM32_SRC_SYSCLK SPI1_SEL(1)>; status = "okay"; }; diff --git a/tests/drivers/comparator/gpio_loopback/boards/bg29_rb4420a.overlay b/tests/drivers/comparator/gpio_loopback/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..9422e6974833d --- /dev/null +++ b/tests/drivers/comparator/gpio_loopback/boards/bg29_rb4420a.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + aliases { + test-comp = &acmp0; + }; + + zephyr,user { + test-gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + acmp0_default: acmp0_default { + group0 { + silabs,analog-bus = ; + }; + }; +}; + +&acmp0 { + pinctrl-0 = <&acmp0_default>; + pinctrl-names = "default"; + status = "okay"; + + bias = <0>; + hysteresis-mode = "disabled"; + accuracy-mode = "high"; + input-range = "full"; + input-positive = ; + input-negative = ; + vref-divider = <63>; +}; diff --git a/tests/drivers/comparator/gpio_loopback/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/boards/nrf5340dk_nrf5340_cpuapp.overlay index a837527e34281..53844d3bc950d 100644 --- a/tests/drivers/comparator/gpio_loopback/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/tests/drivers/comparator/gpio_loopback/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -20,6 +20,6 @@ }; }; -&gpio0{ +&gpio0 { status = "okay"; }; diff --git a/tests/drivers/comparator/gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index aa39ab60e9e13..46f9e9470f3ac 100644 --- a/tests/drivers/comparator/gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/drivers/comparator/gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -26,10 +26,10 @@ /* Temporary workaround to reserve P1.03 for cpuapp */ &led1 { - gpios = < &gpio1 0x3 0x0 >; + gpios = <&gpio1 0x3 0x0>; }; /* Temporary workaround to reserve P1.02 for cpuapp */ &led2 { - gpios = < &gpio1 0x2 0x0 >; + gpios = <&gpio1 0x2 0x0>; }; diff --git a/tests/drivers/comparator/gpio_loopback/boards/xg24_dk2601b.overlay b/tests/drivers/comparator/gpio_loopback/boards/xg24_dk2601b.overlay index d4759d66a20a5..4e05566f2cf6d 100644 --- a/tests/drivers/comparator/gpio_loopback/boards/xg24_dk2601b.overlay +++ b/tests/drivers/comparator/gpio_loopback/boards/xg24_dk2601b.overlay @@ -16,7 +16,6 @@ zephyr,user { test-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; }; - }; &pinctrl { diff --git a/tests/drivers/comparator/gpio_loopback/boards/xg24_rb4187c.overlay b/tests/drivers/comparator/gpio_loopback/boards/xg24_rb4187c.overlay index d4759d66a20a5..4e05566f2cf6d 100644 --- a/tests/drivers/comparator/gpio_loopback/boards/xg24_rb4187c.overlay +++ b/tests/drivers/comparator/gpio_loopback/boards/xg24_rb4187c.overlay @@ -16,7 +16,6 @@ zephyr,user { test-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; }; - }; &pinctrl { diff --git a/tests/drivers/comparator/gpio_loopback/boards/xg29_rb4412a.overlay b/tests/drivers/comparator/gpio_loopback/boards/xg29_rb4412a.overlay index 2930ea787884d..0777857ef0b62 100644 --- a/tests/drivers/comparator/gpio_loopback/boards/xg29_rb4412a.overlay +++ b/tests/drivers/comparator/gpio_loopback/boards/xg29_rb4412a.overlay @@ -16,7 +16,6 @@ zephyr,user { test-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; }; - }; &pinctrl { diff --git a/tests/drivers/comparator/gpio_loopback/testcase.yaml b/tests/drivers/comparator/gpio_loopback/testcase.yaml index bf0e7d127a0c2..dfebf3644756c 100644 --- a/tests/drivers/comparator/gpio_loopback/testcase.yaml +++ b/tests/drivers/comparator/gpio_loopback/testcase.yaml @@ -13,11 +13,13 @@ tests: - xg24_dk2601b - xg24_rb4187c - xg29_rb4412a + - bg29_rb4420a drivers.comparator.gpio_loopback.mcux_acmp: platform_allow: - frdm_ke15z drivers.comparator.gpio_loopback.nrf_comp: extra_args: + - SNIPPET_ROOT="." - SNIPPET="gpio_loopback_nrf_comp" platform_allow: - nrf5340dk/nrf5340/cpuapp @@ -27,6 +29,7 @@ tests: - ophelia4ev/nrf54l15/cpuapp drivers.comparator.gpio_loopback.nrf_lpcomp: extra_args: + - SNIPPET_ROOT="." - SNIPPET="gpio_loopback_nrf_lpcomp" platform_allow: - nrf5340dk/nrf5340/cpuapp diff --git a/tests/drivers/comparator/shell/app.overlay b/tests/drivers/comparator/shell/app.overlay index 3bb03b5a569e5..c6772c56fb5cf 100644 --- a/tests/drivers/comparator/shell/app.overlay +++ b/tests/drivers/comparator/shell/app.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { fake_comp: fake_comp { compatible = "zephyr,fake-comp"; status = "okay"; diff --git a/tests/drivers/coredump/coredump_api/boards/qemu_riscv32.overlay b/tests/drivers/coredump/coredump_api/boards/qemu_riscv32.overlay index 628554a644644..696e941f55e75 100644 --- a/tests/drivers/coredump/coredump_api/boards/qemu_riscv32.overlay +++ b/tests/drivers/coredump/coredump_api/boards/qemu_riscv32.overlay @@ -11,7 +11,7 @@ status = "okay"; memory-regions = <0x85000000 0x4>, - <0x85000004 0x4>; + <0x85000004 0x4>; }; coredump_device1: coredump-device1 { diff --git a/tests/drivers/counter/counter_basic_api/boards/frdm_ke17z.conf b/tests/drivers/counter/counter_basic_api/boards/frdm_ke17z.conf new file mode 100644 index 0000000000000..dbfb697533ac2 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/frdm_ke17z.conf @@ -0,0 +1,6 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +CONFIG_COUNTER_MCUX_FTM=y diff --git a/tests/drivers/counter/counter_basic_api/boards/frdm_ke17z.overlay b/tests/drivers/counter/counter_basic_api/boards/frdm_ke17z.overlay new file mode 100644 index 0000000000000..4ddc68c9d5bfe --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/frdm_ke17z.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&ftm0 { + status = "okay"; + compatible = "nxp,ftm"; + prescaler = <128>; + clocks = <&scg KINETIS_SCG_FIRC_CLK>; + clock-source = "system"; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/nucleo_f207zg.overlay b/tests/drivers/counter/counter_basic_api/boards/nucleo_f207zg.overlay index 042d133b41bbc..265c55da4b631 100644 --- a/tests/drivers/counter/counter_basic_api/boards/nucleo_f207zg.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/nucleo_f207zg.overlay @@ -61,7 +61,6 @@ }; }; - &timers12 { st,prescaler = <79>; counter { diff --git a/tests/drivers/counter/counter_basic_api/boards/siwx917_rb4342a.overlay b/tests/drivers/counter/counter_basic_api/boards/siwx917_rb4342a.overlay index 8f25ee6c54979..a209a5643246b 100644 --- a/tests/drivers/counter/counter_basic_api/boards/siwx917_rb4342a.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/siwx917_rb4342a.overlay @@ -3,6 +3,6 @@ * * SPDX-License-Identifier: Apache-2.0 */ -&sysrtc0 { +&sysrtc0 { status = "okay"; }; diff --git a/tests/drivers/counter/counter_basic_api/boards/stm32l562e_dk.overlay b/tests/drivers/counter/counter_basic_api/boards/stm32l562e_dk.overlay index b9935272a5047..d81fc02bee1f3 100644 --- a/tests/drivers/counter/counter_basic_api/boards/stm32l562e_dk.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/stm32l562e_dk.overlay @@ -19,7 +19,6 @@ }; }; - &timers5 { st,prescaler = <79>; counter { diff --git a/tests/drivers/counter/counter_basic_api/socs/esp32h2.overlay b/tests/drivers/counter/counter_basic_api/socs/esp32h2.overlay new file mode 100644 index 0000000000000..654ca2b00155f --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/socs/esp32h2.overlay @@ -0,0 +1,13 @@ +&timer0 { + status = "okay"; + counter { + status = "okay"; + }; +}; + +&timer1 { + status = "okay"; + counter { + status = "okay"; + }; +}; diff --git a/tests/drivers/counter/counter_basic_api/src/test_counter.c b/tests/drivers/counter/counter_basic_api/src/test_counter.c index 4b724622f6f03..87f2c95f1e5c1 100644 --- a/tests/drivers/counter/counter_basic_api/src/test_counter.c +++ b/tests/drivers/counter/counter_basic_api/src/test_counter.c @@ -126,6 +126,9 @@ static const struct device *const devices[] = { #ifdef CONFIG_COUNTER_MCUX_LPIT DEVS_FOR_DT_COMPAT(nxp_lpit_channel) #endif +#ifdef CONFIG_COUNTER_MCUX_FTM + DEVS_FOR_DT_COMPAT(nxp_ftm) +#endif #ifdef CONFIG_COUNTER_RENESAS_RZ_GTM DEVS_FOR_DT_COMPAT(renesas_rz_gtm_counter) #endif @@ -453,7 +456,6 @@ static void test_single_shot_alarm_instance(const struct device *dev, bool set_t zassert_equal(-EINVAL, err, "%s: Counter should return error because ticks" " exceeded the limit set alarm", dev->name); - cntr_alarm_cfg.ticks = ticks - 1; } cntr_alarm_cfg.ticks = ticks; diff --git a/tests/drivers/counter/counter_nrf_rtc/fixed_top/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/counter/counter_nrf_rtc/fixed_top/boards/nrf54h20dk_nrf54h20_common.dtsi index 181611f712d29..8dc4bdda5236e 100644 --- a/tests/drivers/counter/counter_nrf_rtc/fixed_top/boards/nrf54h20dk_nrf54h20_common.dtsi +++ b/tests/drivers/counter/counter_nrf_rtc/fixed_top/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -1,4 +1,4 @@ - /* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: Apache-2.0 */ &rtc130 { status = "okay"; diff --git a/tests/drivers/counter/counter_nrf_rtc/fixed_top/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/counter/counter_nrf_rtc/fixed_top/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index eef4236c64271..f96ae8ccf7f45 100644 --- a/tests/drivers/counter/counter_nrf_rtc/fixed_top/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/drivers/counter/counter_nrf_rtc/fixed_top/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -1,4 +1,4 @@ - /* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: Apache-2.0 */ &rtc130 { status = "reserved"; diff --git a/tests/drivers/crc/CMakeLists.txt b/tests/drivers/crc/CMakeLists.txt new file mode 100644 index 0000000000000..eb356a6dc870e --- /dev/null +++ b/tests/drivers/crc/CMakeLists.txt @@ -0,0 +1,6 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) + +project(drivers_crc_test) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/drivers/crc/prj.conf b/tests/drivers/crc/prj.conf new file mode 100644 index 0000000000000..e5d697260b126 --- /dev/null +++ b/tests/drivers/crc/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_CRC=y +CONFIG_CRC_LOG_LEVEL_INF=y diff --git a/tests/drivers/crc/src/main.c b/tests/drivers/crc/src/main.c new file mode 100644 index 0000000000000..9a3d4af857c1b --- /dev/null +++ b/tests/drivers/crc/src/main.c @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +#define WAIT_THREAD_STACK_SIZE 1024 +#define WAIT_THREAD_PRIO -10 + +static void wait_thread_entry(void *a, void *b, void *c); + +K_THREAD_STACK_DEFINE(wait_thread_stack_area, WAIT_THREAD_STACK_SIZE); +struct k_thread wait_thread_data; + +/* Define result of CRC computation */ +#define RESULT_CRC_16_THREADSAFE 0xD543 + +/** + * 1) Take the semaphore + * 2) Sleep for 50 ms (to allow ztest main thread to attempt to acquire semaphore) + * 3) Give the semaphore + */ +static void wait_thread_entry(void *a, void *b, void *c) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = CRC16_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + crc_begin(dev, &ctx); + + k_sleep(K_MSEC(50)); + + crc_update(dev, &ctx, data, sizeof(data)); + crc_finish(dev, &ctx); + zassert_equal(crc_verify(&ctx, RESULT_CRC_16_THREADSAFE), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_8 0xB2 + +/** + * @brief Test that crc8 works + */ +ZTEST(crc, test_crc_8) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + crc_begin(dev, &ctx); + + k_sleep(K_MSEC(50)); + + crc_update(dev, &ctx, data, sizeof(data)); + crc_finish(dev, &ctx); + zassert_equal(crc_verify(&ctx, RESULT_CRC_8), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_16 0xD543 + +/** + * @brief Test that crc16 works + */ +ZTEST(crc, test_crc_16) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = CRC16_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_16), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT 0x445C + +/** + * @brief Test that crc_16_ccitt works + */ +ZTEST(crc, test_crc_16_ccitt) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = CRC16_CCITT_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_CCITT), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_32_C 0xBB19ECB2 + +/** + * @brief Test that crc_32_c works + */ +ZTEST(crc, test_crc_32_c) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC32_C, + .polynomial = CRC32C_POLY, + .seed = CRC32_C_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_32_C), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_32_IEEE 0xCEA4A6C2 + +/** + * @brief Test that crc_32_ieee works + */ +ZTEST(crc, test_crc_32_ieee) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + struct crc_ctx ctx = { + .type = CRC32_IEEE, + .polynomial = CRC32_IEEE_POLY, + .seed = CRC32_IEEE_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + zassert_equal(crc_verify(&ctx, RESULT_CRC_32_IEEE), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_8_REMAIN_3 0xBB + +/** + * @brief Test that crc_8_remain_3 works + */ +ZTEST(crc, test_crc_8_remain_3) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[11] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0x4D, 0x51}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + zassert_equal(crc_verify(&ctx, RESULT_CRC_8_REMAIN_3), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_16_REMAIN_1 0x2055 + +/** + * @brief Test that crc_16_remain_1 works + */ +ZTEST(crc, test_crc_16_remain_1) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[9] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D}; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = CRC16_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_16_REMAIN_1), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT_REMAIN_2 0x24BD + +/** + * @brief Test that crc_16_ccitt works + */ +ZTEST(crc, test_crc_16_ccitt_remain_2) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[10] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0xFF, 0xA0}; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = CRC16_CCITT_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_CCITT_REMAIN_2), 0); +} + +/* Define result of CRC computation */ +#define RESULT_DISCONTINUOUS_BUFFER 0x75 + +/** + * @brief Test CRC calculation with discontinuous buffers. + */ +ZTEST(crc, test_discontinuous_buf) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data1[5] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E}; + uint8_t data2[5] = {0x49, 0x00, 0xC4, 0x3B, 0x78}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_INPUT | CRC_FLAG_REVERSE_OUTPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data1, sizeof(data1)), 0); + zassert_equal(crc_update(dev, &ctx, data2, sizeof(data2)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + zassert_equal(crc_verify(&ctx, RESULT_DISCONTINUOUS_BUFFER), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_8_REMAIN_3_THREADSAFE 0xBB + +/** + * @brief Test CRC function semaphore wait for thread safety + * + * Verifies that CRC operations are blocked until a semaphore is released. A new thread + * acquires the semaphore, and the main thread's CRC operations wait until it is released. + */ +ZTEST(crc, test_crc_threadsafe) +{ + static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + + uint8_t data[11] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0x4D, 0x51}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + /** + * Create new thread that will immediately take the semaphore + */ + k_thread_create(&wait_thread_data, wait_thread_stack_area, + K_THREAD_STACK_SIZEOF(wait_thread_stack_area), wait_thread_entry, NULL, + NULL, NULL, WAIT_THREAD_PRIO, 0, K_NO_WAIT); + + /** + * Sleep for 10 ms to ensure that new thread has taken lock + */ + k_sleep(K_MSEC(10)); + + /** + * Attempt to take semaphore, this should wait for the new thread to give the semaphore + * before executing + */ + crc_begin(dev, &ctx); + crc_update(dev, &ctx, data, sizeof(data)); + crc_finish(dev, &ctx); + zassert_equal(crc_verify(&ctx, RESULT_CRC_8_REMAIN_3_THREADSAFE), 0); +} + +ZTEST_SUITE(crc, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/drivers/crc/testcase.yaml b/tests/drivers/crc/testcase.yaml new file mode 100644 index 0000000000000..f37cdba09cbcf --- /dev/null +++ b/tests/drivers/crc/testcase.yaml @@ -0,0 +1,7 @@ +tests: + drivers.crc: + depends_on: crc + tags: + - drivers + - crc + harness: ztest diff --git a/tests/drivers/disk/disk_access/boards/stm32l496g_disco_stm32l496xx.conf b/tests/drivers/disk/disk_access/boards/stm32l496g_disco_stm32l496xx.conf deleted file mode 100644 index 73aff8957e7a7..0000000000000 --- a/tests/drivers/disk/disk_access/boards/stm32l496g_disco_stm32l496xx.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_DMA=y diff --git a/tests/drivers/disk/disk_performance/boards/qemu_x86_64.conf b/tests/drivers/disk/disk_performance/boards/qemu_x86_64.conf index 0c14f763bf95d..64343c52aad37 100644 --- a/tests/drivers/disk/disk_performance/boards/qemu_x86_64.conf +++ b/tests/drivers/disk/disk_performance/boards/qemu_x86_64.conf @@ -3,3 +3,4 @@ CONFIG_PCIE=y CONFIG_PCIE_MSI=y CONFIG_PCIE_MSI_X=y CONFIG_PCIE_MSI_MULTI_VECTOR=y +CONFIG_NVME=y diff --git a/tests/drivers/dma/chan_blen_transfer/boards/adafruit_itsybitsy_m4_express.overlay b/tests/drivers/dma/chan_blen_transfer/boards/adafruit_itsybitsy_m4_express.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/adafruit_itsybitsy_m4_express.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/adafruit_itsybitsy_m4_express.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/adafruit_trinket_m0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/adafruit_trinket_m0.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/adafruit_trinket_m0.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/adafruit_trinket_m0.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/arduino_mkrzero.overlay b/tests/drivers/dma/chan_blen_transfer/boards/arduino_mkrzero.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/arduino_mkrzero.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/arduino_mkrzero.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/arduino_nano_33_iot.overlay b/tests/drivers/dma/chan_blen_transfer/boards/arduino_nano_33_iot.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/arduino_nano_33_iot.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/arduino_nano_33_iot.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/arduino_zero.overlay b/tests/drivers/dma/chan_blen_transfer/boards/arduino_zero.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/arduino_zero.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/arduino_zero.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/bg29_rb4420a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..9e67ecb73d81d --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/bg29_rb4420a.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Silicon Laboratories, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/cy8cproto_062_4343w.overlay b/tests/drivers/dma/chan_blen_transfer/boards/cy8cproto_062_4343w.overlay index 6402db8fbe0ae..57f19f2e4a4a1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/cy8cproto_062_4343w.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/cy8cproto_062_4343w.overlay @@ -2,7 +2,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - tst_dma0: &dma0 { status = "okay"; }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/da1469x_dk_pro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/da1469x_dk_pro.overlay index 5ac7a35afd31e..940ec3fb58ec3 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/da1469x_dk_pro.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/da1469x_dk_pro.overlay @@ -4,6 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - tst_dma0: &dma { +tst_dma0: &dma { status = "okay"; }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/disco_l475_iot1.overlay b/tests/drivers/dma/chan_blen_transfer/boards/disco_l475_iot1.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/disco_l475_iot1.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/disco_l475_iot1.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_devkitm_procpu.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_devkitm_procpu.overlay index a6570c3a8bd75..41822eda6816e 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_devkitm_procpu.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_devkitm_procpu.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu.overlay index a6570c3a8bd75..41822eda6816e 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay index a6570c3a8bd75..41822eda6816e 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/frdm_k64f.overlay b/tests/drivers/dma/chan_blen_transfer/boards/frdm_k64f.overlay index e4501ae477d25..84c2758f746ed 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/frdm_k64f.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/frdm_k64f.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25.overlay b/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25.overlay index 3110e90b5f514..109d0e3548151 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &lpgpdma0 { }; +tst_dma0: &lpgpdma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25_tgph.overlay b/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25_tgph.overlay index 3110e90b5f514..109d0e3548151 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25_tgph.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/intel_adsp_cavs25_tgph.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &lpgpdma0 { }; +tst_dma0: &lpgpdma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s36.overlay b/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s36.overlay index a870cbfe77935..abff0c7ea81f8 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s36.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s36.overlay @@ -1 +1 @@ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay b/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay index 5e4c6a1c43c02..c86764e07b9b2 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0_ns.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32650evkit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32650evkit.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32650evkit.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32650evkit.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32650fthr.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32650fthr.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32650fthr.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32650fthr.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32655evkit_max32655_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32655evkit_max32655_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32655evkit_max32655_m4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32655evkit_max32655_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32655fthr_max32655_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32655fthr_max32655_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32655fthr_max32655_m4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32655fthr_max32655_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657.overlay index 20cce245740b2..f7d4300266c7c 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657_ns.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657_ns.overlay index 99f09a2979869..87cff039456b9 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657_ns.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32657evkit_max32657_ns.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32670evkit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32670evkit.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32670evkit.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32670evkit.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32672evkit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32672evkit.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32672evkit.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32672evkit.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32672fthr.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32672fthr.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32672fthr.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32672fthr.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32680evkit_max32680_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32680evkit_max32680_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32680evkit_max32680_m4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32680evkit_max32680_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32690evkit_max32690_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32690evkit_max32690_m4.overlay index a38592c091449..d3909019e38c5 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max32690evkit_max32690_m4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max32690evkit_max32690_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max78002evkit_max78002_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max78002evkit_max78002_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/max78002evkit_max78002_m4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/max78002evkit_max78002_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1010_evk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1010_evk.overlay index e653967c9c8e5..826c235373d27 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1010_evk.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1010_evk.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1024_evk.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1064_evk.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 5e8bafa1d9b1b..c3ead730f0212 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -8,7 +8,7 @@ #include &sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma_lpsr0 { }; +tst_dma0: &edma_lpsr0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 5e8bafa1d9b1b..c3ead730f0212 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -8,7 +8,7 @@ #include &sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma_lpsr0 { }; +tst_dma0: &edma_lpsr0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 5e8bafa1d9b1b..c3ead730f0212 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -8,7 +8,7 @@ #include &sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma_lpsr0 { }; +tst_dma0: &edma_lpsr0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evkb_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evkb_cm4.overlay index 5e8bafa1d9b1b..c3ead730f0212 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evkb_cm4.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evkb_cm4.overlay @@ -8,7 +8,7 @@ #include &sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma_lpsr0 { }; +tst_dma0: &edma_lpsr0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay index 5e4c6a1c43c02..c86764e07b9b2 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay index 5e4c6a1c43c02..c86764e07b9b2 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mm_feather.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mm_feather.overlay index e4501ae477d25..84c2758f746ed 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mm_feather.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mm_feather.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mr_canhubk3.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mr_canhubk3.overlay index fb42bb5c39c48..5e1d2dc5e89cd 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/mr_canhubk3.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/mr_canhubk3.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/native_sim.overlay b/tests/drivers/dma/chan_blen_transfer/boards/native_sim.overlay index 28f19ac0f0db4..c20d380564a27 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/native_sim.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/native_sim.overlay @@ -9,4 +9,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f091rc.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f091rc.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f091rc.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f091rc.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f103rb.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f103rb.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f103rb.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f103rb.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f429zi.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f429zi.overlay index 2fee10c7ffd2f..c9af81844fbc4 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f429zi.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f429zi.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma2 { }; +tst_dma0: &dma2 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.overlay index c0fbbe714086a..458736850a617 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.overlay @@ -4,9 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma2 { }; +tst_dma0: &dma2 {}; /* The test driver expects the SRAM0 region to be non-cachable */ &sram0 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.overlay index b234285c6b9ba..bf9bcb99eb3d3 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.overlay @@ -14,5 +14,5 @@ tst_dma0: &dma2 { /* The test driver expects the SRAM0 region to be non-cachable */ &sram0 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay index 3e8bd92d5fb13..91e14bb5c1147 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay @@ -20,7 +20,7 @@ tst_dma0: &dmamux1 { * to be non-cachable. */ &sram4 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; &bdma1 { diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_l152re.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_l152re.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_l152re.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_l152re.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index c921a4af96ac8..3af8adf43f377 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay index 13f1c87a01b18..d6010ade41203 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -12,7 +12,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x31870000 DT_SIZE_K(64)>; zephyr,memory-region = "SRAMNOCACHE"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>; + zephyr,memory-attr = ; }; }; }; @@ -26,4 +26,4 @@ status = "okay"; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay index c828ef591ed10..7fb74e2d52e2a 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -12,7 +12,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x35870000 DT_SIZE_K(64)>; zephyr,memory-region = "SRAMNOCACHE"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>; + zephyr,memory-attr = ; }; }; }; @@ -26,4 +26,4 @@ status = "okay"; }; -tst_dma0: &edma5 { }; +tst_dma0: &edma5 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/seeeduino_xiao.overlay b/tests/drivers/dma/chan_blen_transfer/boards/seeeduino_xiao.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/seeeduino_xiao.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/seeeduino_xiao.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/sltb010a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/sltb010a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/sltb010a.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/sltb010a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/slwrb4180a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/slwrb4180a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/slwrb4180a.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/slwrb4180a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/stm32f3_disco.overlay b/tests/drivers/dma/chan_blen_transfer/boards/stm32f3_disco.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/stm32f3_disco.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/stm32f3_disco.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/stm32f746g_disco.overlay b/tests/drivers/dma/chan_blen_transfer/boards/stm32f746g_disco.overlay index c189d0fed6fc0..17022aef0a38d 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/stm32f746g_disco.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/stm32f746g_disco.overlay @@ -9,5 +9,5 @@ tst_dma0: &dma2 { }; &sram0 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/twr_ke18f.overlay b/tests/drivers/dma/chan_blen_transfer/boards/twr_ke18f.overlay index b2314c944bde9..8ce6bfcd2fc4c 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/twr_ke18f.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/twr_ke18f.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma { }; +tst_dma0: &edma {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xg23_rb4210a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xg23_rb4210a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/xg23_rb4210a.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/xg23_rb4210a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xg24_dk2601b.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xg24_dk2601b.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/xg24_dk2601b.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/xg24_dk2601b.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xg27_dk2602a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xg27_dk2602a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/xg27_dk2602a.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/xg27_dk2602a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xg29_rb4412a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xg29_rb4412a.overlay index 73a4023ee35b1..9e67ecb73d81d 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/xg29_rb4412a.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/xg29_rb4412a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.overlay index 2fed134b32c99..d07cfdba82a43 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.overlay index 2fed134b32c99..d07cfdba82a43 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/chan_blen_transfer/socs/esp32c2.overlay b/tests/drivers/dma/chan_blen_transfer/socs/esp32c2.overlay index 22d42af1dcfa2..81ce4631efa79 100644 --- a/tests/drivers/dma/chan_blen_transfer/socs/esp32c2.overlay +++ b/tests/drivers/dma/chan_blen_transfer/socs/esp32c2.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.overlay b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.overlay index 6ac9ff08336ba..5d9b2e0c8b14e 100644 --- a/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.overlay +++ b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.overlay b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.overlay index 6ac9ff08336ba..5d9b2e0c8b14e 100644 --- a/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.overlay +++ b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/bg29_rb4420a.overlay b/tests/drivers/dma/chan_link_transfer/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..57a16a6916a11 --- /dev/null +++ b/tests/drivers/dma/chan_link_transfer/boards/bg29_rb4420a.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Silicon Laboratories, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/frdm_k64f.overlay b/tests/drivers/dma/chan_link_transfer/boards/frdm_k64f.overlay index 9d2f44e723160..9de65ba7b944a 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/frdm_k64f.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/frdm_k64f.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1024_evk.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1024_evk.overlay index 9c29d0ecad005..f3639475d4d62 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1024_evk.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1024_evk.overlay @@ -1 +1 @@ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay index 9d2f44e723160..9de65ba7b944a 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay index 9d2f44e723160..9de65ba7b944a 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1064_evk.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1064_evk.overlay index 9d2f44e723160..9de65ba7b944a 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1064_evk.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1064_evk.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 9d2f44e723160..9de65ba7b944a 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay index 9d2f44e723160..9de65ba7b944a 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/mr_canhubk3.overlay b/tests/drivers/dma/chan_link_transfer/boards/mr_canhubk3.overlay index f13c97d754ed2..a1753c71df829 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/mr_canhubk3.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/mr_canhubk3.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/native_sim.overlay b/tests/drivers/dma/chan_link_transfer/boards/native_sim.overlay index 082fc972cabcc..31acaa6798be0 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/native_sim.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/native_sim.overlay @@ -9,4 +9,4 @@ status = "okay"; }; -dma0: &dma { }; +dma0: &dma {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay index 14728cdfb6a35..159e466c62b1a 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -dma0: &edma0 { }; +dma0: &edma0 {}; diff --git a/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay index b2efe980ac82d..4bb508ed8486d 100644 --- a/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/dma/chan_link_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -dma0: &edma5 { }; +dma0: &edma5 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/adafruit_itsybitsy_m4_express.overlay b/tests/drivers/dma/loop_transfer/boards/adafruit_itsybitsy_m4_express.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/loop_transfer/boards/adafruit_itsybitsy_m4_express.overlay +++ b/tests/drivers/dma/loop_transfer/boards/adafruit_itsybitsy_m4_express.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/loop_transfer/boards/adafruit_trinket_m0.overlay b/tests/drivers/dma/loop_transfer/boards/adafruit_trinket_m0.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/loop_transfer/boards/adafruit_trinket_m0.overlay +++ b/tests/drivers/dma/loop_transfer/boards/adafruit_trinket_m0.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/loop_transfer/boards/arduino_mkrzero.overlay b/tests/drivers/dma/loop_transfer/boards/arduino_mkrzero.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/loop_transfer/boards/arduino_mkrzero.overlay +++ b/tests/drivers/dma/loop_transfer/boards/arduino_mkrzero.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/loop_transfer/boards/arduino_nano_33_iot.overlay b/tests/drivers/dma/loop_transfer/boards/arduino_nano_33_iot.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/loop_transfer/boards/arduino_nano_33_iot.overlay +++ b/tests/drivers/dma/loop_transfer/boards/arduino_nano_33_iot.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/loop_transfer/boards/arduino_zero.overlay b/tests/drivers/dma/loop_transfer/boards/arduino_zero.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/loop_transfer/boards/arduino_zero.overlay +++ b/tests/drivers/dma/loop_transfer/boards/arduino_zero.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/loop_transfer/boards/bg29_rb4420a.overlay b/tests/drivers/dma/loop_transfer/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..9e67ecb73d81d --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/bg29_rb4420a.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Silicon Laboratories, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/disco_l475_iot1.overlay b/tests/drivers/dma/loop_transfer/boards/disco_l475_iot1.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/loop_transfer/boards/disco_l475_iot1.overlay +++ b/tests/drivers/dma/loop_transfer/boards/disco_l475_iot1.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.overlay b/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.overlay index c93ef734fba60..fd20d44cec801 100644 --- a/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.overlay +++ b/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/boards/esp32s3_devkitm_procpu.overlay b/tests/drivers/dma/loop_transfer/boards/esp32s3_devkitm_procpu.overlay index a6570c3a8bd75..41822eda6816e 100644 --- a/tests/drivers/dma/loop_transfer/boards/esp32s3_devkitm_procpu.overlay +++ b/tests/drivers/dma/loop_transfer/boards/esp32s3_devkitm_procpu.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu.overlay b/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu.overlay index a6570c3a8bd75..41822eda6816e 100644 --- a/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu.overlay +++ b/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay b/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay index a6570c3a8bd75..41822eda6816e 100644 --- a/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay +++ b/tests/drivers/dma/loop_transfer/boards/esp32s3_luatos_core_procpu_usb.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/boards/frdm_k64f.overlay b/tests/drivers/dma/loop_transfer/boards/frdm_k64f.overlay index e4501ae477d25..84c2758f746ed 100644 --- a/tests/drivers/dma/loop_transfer/boards/frdm_k64f.overlay +++ b/tests/drivers/dma/loop_transfer/boards/frdm_k64f.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/frdm_ke17z512.overlay b/tests/drivers/dma/loop_transfer/boards/frdm_ke17z512.overlay index b2314c944bde9..8ce6bfcd2fc4c 100644 --- a/tests/drivers/dma/loop_transfer/boards/frdm_ke17z512.overlay +++ b/tests/drivers/dma/loop_transfer/boards/frdm_ke17z512.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma { }; +tst_dma0: &edma {}; diff --git a/tests/drivers/dma/loop_transfer/boards/frdm_rw612.overlay b/tests/drivers/dma/loop_transfer/boards/frdm_rw612.overlay index eb0aab63133fa..8e1acdb07bb68 100644 --- a/tests/drivers/dma/loop_transfer/boards/frdm_rw612.overlay +++ b/tests/drivers/dma/loop_transfer/boards/frdm_rw612.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/intel_adsp_ace15_mtpm.overlay b/tests/drivers/dma/loop_transfer/boards/intel_adsp_ace15_mtpm.overlay index fa730c093c029..82a8c71c671f5 100644 --- a/tests/drivers/dma/loop_transfer/boards/intel_adsp_ace15_mtpm.overlay +++ b/tests/drivers/dma/loop_transfer/boards/intel_adsp_ace15_mtpm.overlay @@ -5,4 +5,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &lpgpdma0 { }; +tst_dma0: &lpgpdma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25.overlay b/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25.overlay index 3110e90b5f514..109d0e3548151 100644 --- a/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25.overlay +++ b/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &lpgpdma0 { }; +tst_dma0: &lpgpdma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25_tgph.overlay b/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25_tgph.overlay index 3110e90b5f514..109d0e3548151 100644 --- a/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25_tgph.overlay +++ b/tests/drivers/dma/loop_transfer/boards/intel_adsp_cavs25_tgph.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &lpgpdma0 { }; +tst_dma0: &lpgpdma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s36.overlay b/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s36.overlay index 14c0d9f848d38..fc401b9a18867 100644 --- a/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s36.overlay +++ b/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s36.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index 0d66744639931..850b833e02669 100644 --- a/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/tests/drivers/dma/loop_transfer/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32650evkit.overlay b/tests/drivers/dma/loop_transfer/boards/max32650evkit.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32650evkit.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32650evkit.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32650fthr.overlay b/tests/drivers/dma/loop_transfer/boards/max32650fthr.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32650fthr.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32650fthr.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32655evkit_max32655_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max32655evkit_max32655_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32655evkit_max32655_m4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32655evkit_max32655_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32655fthr_max32655_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max32655fthr_max32655_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32655fthr_max32655_m4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32655fthr_max32655_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657.overlay b/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657.overlay index 20cce245740b2..f7d4300266c7c 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657_ns.overlay b/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657_ns.overlay index 99f09a2979869..87cff039456b9 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657_ns.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32657evkit_max32657_ns.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32662evkit.overlay b/tests/drivers/dma/loop_transfer/boards/max32662evkit.overlay index 8c711035a3153..552fe4f9b8616 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32662evkit.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32662evkit.overlay @@ -15,4 +15,4 @@ }; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/dma/loop_transfer/boards/max32666evkit_max32666_cpu0.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32666evkit_max32666_cpu0.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32666evkit_max32666_cpu0.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/dma/loop_transfer/boards/max32666fthr_max32666_cpu0.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32666fthr_max32666_cpu0.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32666fthr_max32666_cpu0.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32670evkit.overlay b/tests/drivers/dma/loop_transfer/boards/max32670evkit.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32670evkit.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32670evkit.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32672evkit.overlay b/tests/drivers/dma/loop_transfer/boards/max32672evkit.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32672evkit.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32672evkit.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32672fthr.overlay b/tests/drivers/dma/loop_transfer/boards/max32672fthr.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32672fthr.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32672fthr.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32680evkit_max32680_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max32680evkit_max32680_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32680evkit_max32680_m4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32680evkit_max32680_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max32690evkit_max32690_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max32690evkit_max32690_m4.overlay index a38592c091449..d3909019e38c5 100644 --- a/tests/drivers/dma/loop_transfer/boards/max32690evkit_max32690_m4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max32690evkit_max32690_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max78000evkit_max78000_m4.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/loop_transfer/boards/max78000evkit_max78000_m4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max78000evkit_max78000_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max78000fthr_max78000_m4.overlay index 0e412606f7a07..b28e2e4fe6c38 100644 --- a/tests/drivers/dma/loop_transfer/boards/max78000fthr_max78000_m4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max78000fthr_max78000_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/max78002evkit_max78002_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max78002evkit_max78002_m4.overlay index 63d2081230924..3c286ad5d0f87 100644 --- a/tests/drivers/dma/loop_transfer/boards/max78002evkit_max78002_m4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/max78002evkit_max78002_m4.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1010_evk.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1010_evk.overlay index e653967c9c8e5..826c235373d27 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1010_evk.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1010_evk.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1024_evk.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1024_evk.overlay index 43b7fc3782656..8452f0ef6b0a2 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1024_evk.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1024_evk.overlay @@ -8,7 +8,7 @@ #include &itcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay index 43b7fc3782656..8452f0ef6b0a2 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay @@ -8,7 +8,7 @@ #include &itcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay index 43b7fc3782656..8452f0ef6b0a2 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay @@ -8,7 +8,7 @@ #include &itcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1064_evk.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1064_evk.overlay index 82f0bbe94e899..066c9485d4bb1 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1064_evk.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1064_evk.overlay @@ -8,7 +8,7 @@ #include &dtcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 5e8bafa1d9b1b..c3ead730f0212 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -8,7 +8,7 @@ #include &sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma_lpsr0 { }; +tst_dma0: &edma_lpsr0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 43b7fc3782656..8452f0ef6b0a2 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -8,7 +8,7 @@ #include &itcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 5e8bafa1d9b1b..c3ead730f0212 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -8,7 +8,7 @@ #include &sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma_lpsr0 { }; +tst_dma0: &edma_lpsr0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay index 43b7fc3782656..8452f0ef6b0a2 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -8,7 +8,7 @@ #include &itcm { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index fb42bb5c39c48..5e1d2dc5e89cd 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm4.overlay index 5e8bafa1d9b1b..c3ead730f0212 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm4.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm4.overlay @@ -8,7 +8,7 @@ #include &sram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; -tst_dma0: &edma_lpsr0 { }; +tst_dma0: &edma_lpsr0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay index 5e4c6a1c43c02..c86764e07b9b2 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay index 5e4c6a1c43c02..c86764e07b9b2 100644 --- a/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_mimxrt685s_cm33.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mm_feather.overlay b/tests/drivers/dma/loop_transfer/boards/mm_feather.overlay index e4501ae477d25..84c2758f746ed 100644 --- a/tests/drivers/dma/loop_transfer/boards/mm_feather.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mm_feather.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/mr_canhubk3.overlay b/tests/drivers/dma/loop_transfer/boards/mr_canhubk3.overlay index fb42bb5c39c48..5e1d2dc5e89cd 100644 --- a/tests/drivers/dma/loop_transfer/boards/mr_canhubk3.overlay +++ b/tests/drivers/dma/loop_transfer/boards/mr_canhubk3.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/native_sim.overlay b/tests/drivers/dma/loop_transfer/boards/native_sim.overlay index 28f19ac0f0db4..c20d380564a27 100644 --- a/tests/drivers/dma/loop_transfer/boards/native_sim.overlay +++ b/tests/drivers/dma/loop_transfer/boards/native_sim.overlay @@ -9,4 +9,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f091rc.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_f091rc.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_f091rc.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_f091rc.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f103rb.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_f103rb.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_f103rb.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_f103rb.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f429zi.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_f429zi.overlay index 2fee10c7ffd2f..c9af81844fbc4 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_f429zi.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_f429zi.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma2 { }; +tst_dma0: &dma2 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.overlay index c0fbbe714086a..458736850a617 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.overlay @@ -4,9 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma2 { }; +tst_dma0: &dma2 {}; /* The test driver expects the SRAM0 region to be non-cachable */ &sram0 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.overlay index b234285c6b9ba..bf9bcb99eb3d3 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.overlay @@ -14,5 +14,5 @@ tst_dma0: &dma2 { /* The test driver expects the SRAM0 region to be non-cachable */ &sram0 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay index acffa9f0e1fd6..b820f3b16297b 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay @@ -18,7 +18,7 @@ tst_dma0: &dmamux1 { * to be non-cachable. */ &sram4 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; &bdma1 { diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_l152re.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_l152re.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_l152re.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_l152re.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay b/tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay index eb0aab63133fa..8e1acdb07bb68 100644 --- a/tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay +++ b/tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index c921a4af96ac8..3af8adf43f377 100644 --- a/tests/drivers/dma/loop_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/tests/drivers/dma/loop_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay index 13f1c87a01b18..d6010ade41203 100644 --- a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -12,7 +12,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x31870000 DT_SIZE_K(64)>; zephyr,memory-region = "SRAMNOCACHE"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>; + zephyr,memory-attr = ; }; }; }; @@ -26,4 +26,4 @@ status = "okay"; }; -tst_dma0: &edma0 { }; +tst_dma0: &edma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay index b9bcb12135107..7fb74e2d52e2a 100644 --- a/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/dma/loop_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -12,7 +12,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x35870000 DT_SIZE_K(64)>; zephyr,memory-region = "SRAMNOCACHE"; - zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>; + zephyr,memory-attr = ; }; }; }; @@ -22,9 +22,8 @@ reg = <0x35780000 DT_SIZE_K(960)>; }; - &edma5 { status = "okay"; }; -tst_dma0: &edma5 { }; +tst_dma0: &edma5 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/seeeduino_xiao.overlay b/tests/drivers/dma/loop_transfer/boards/seeeduino_xiao.overlay index 2731332e26b91..c21f76fc76df0 100644 --- a/tests/drivers/dma/loop_transfer/boards/seeeduino_xiao.overlay +++ b/tests/drivers/dma/loop_transfer/boards/seeeduino_xiao.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dmac { }; +tst_dma0: &dmac {}; diff --git a/tests/drivers/dma/loop_transfer/boards/siwx917_dk2605a.overlay b/tests/drivers/dma/loop_transfer/boards/siwx917_dk2605a.overlay index bc14e8c445897..fd07a7f74d411 100644 --- a/tests/drivers/dma/loop_transfer/boards/siwx917_dk2605a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/siwx917_dk2605a.overlay @@ -7,4 +7,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/siwx917_rb4338a.overlay b/tests/drivers/dma/loop_transfer/boards/siwx917_rb4338a.overlay index bc14e8c445897..fd07a7f74d411 100644 --- a/tests/drivers/dma/loop_transfer/boards/siwx917_rb4338a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/siwx917_rb4338a.overlay @@ -7,4 +7,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/siwx917_rb4342a.overlay b/tests/drivers/dma/loop_transfer/boards/siwx917_rb4342a.overlay index bc14e8c445897..fd07a7f74d411 100644 --- a/tests/drivers/dma/loop_transfer/boards/siwx917_rb4342a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/siwx917_rb4342a.overlay @@ -7,4 +7,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/sltb010a.overlay b/tests/drivers/dma/loop_transfer/boards/sltb010a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/loop_transfer/boards/sltb010a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/sltb010a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/slwrb4180a.overlay b/tests/drivers/dma/loop_transfer/boards/slwrb4180a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/loop_transfer/boards/slwrb4180a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/slwrb4180a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/stm32f3_disco.overlay b/tests/drivers/dma/loop_transfer/boards/stm32f3_disco.overlay index f93b51452430b..c0b0de80ee107 100644 --- a/tests/drivers/dma/loop_transfer/boards/stm32f3_disco.overlay +++ b/tests/drivers/dma/loop_transfer/boards/stm32f3_disco.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &dma1 { }; +tst_dma0: &dma1 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/stm32f746g_disco.overlay b/tests/drivers/dma/loop_transfer/boards/stm32f746g_disco.overlay index c189d0fed6fc0..17022aef0a38d 100644 --- a/tests/drivers/dma/loop_transfer/boards/stm32f746g_disco.overlay +++ b/tests/drivers/dma/loop_transfer/boards/stm32f746g_disco.overlay @@ -9,5 +9,5 @@ tst_dma0: &dma2 { }; &sram0 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; diff --git a/tests/drivers/dma/loop_transfer/boards/twr_ke18f.overlay b/tests/drivers/dma/loop_transfer/boards/twr_ke18f.overlay index b2314c944bde9..8ce6bfcd2fc4c 100644 --- a/tests/drivers/dma/loop_transfer/boards/twr_ke18f.overlay +++ b/tests/drivers/dma/loop_transfer/boards/twr_ke18f.overlay @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &edma { }; +tst_dma0: &edma {}; diff --git a/tests/drivers/dma/loop_transfer/boards/xg23_rb4210a.overlay b/tests/drivers/dma/loop_transfer/boards/xg23_rb4210a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/loop_transfer/boards/xg23_rb4210a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/xg23_rb4210a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/xg24_dk2601b.overlay b/tests/drivers/dma/loop_transfer/boards/xg24_dk2601b.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/loop_transfer/boards/xg24_dk2601b.overlay +++ b/tests/drivers/dma/loop_transfer/boards/xg24_dk2601b.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/xg27_dk2602a.overlay b/tests/drivers/dma/loop_transfer/boards/xg27_dk2602a.overlay index a0e0ed0836670..82ee0a4d3cb99 100644 --- a/tests/drivers/dma/loop_transfer/boards/xg27_dk2602a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/xg27_dk2602a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.overlay b/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.overlay index 73a4023ee35b1..9e67ecb73d81d 100644 --- a/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.overlay +++ b/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma0 { }; +tst_dma0: &dma0 {}; diff --git a/tests/drivers/dma/loop_transfer/socs/esp32c2.overlay b/tests/drivers/dma/loop_transfer/socs/esp32c2.overlay index 22d42af1dcfa2..81ce4631efa79 100644 --- a/tests/drivers/dma/loop_transfer/socs/esp32c2.overlay +++ b/tests/drivers/dma/loop_transfer/socs/esp32c2.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/socs/esp32c3.overlay b/tests/drivers/dma/loop_transfer/socs/esp32c3.overlay index 6ac9ff08336ba..5d9b2e0c8b14e 100644 --- a/tests/drivers/dma/loop_transfer/socs/esp32c3.overlay +++ b/tests/drivers/dma/loop_transfer/socs/esp32c3.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.overlay b/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.overlay index 6ac9ff08336ba..5d9b2e0c8b14e 100644 --- a/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.overlay +++ b/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.overlay @@ -8,4 +8,4 @@ status = "okay"; }; -tst_dma0: &dma { }; +tst_dma0: &dma {}; diff --git a/tests/drivers/dma/loop_transfer/src/test_dma_loop.c b/tests/drivers/dma/loop_transfer/src/test_dma_loop.c index 429c41f1e58a5..dd8a8633dde41 100644 --- a/tests/drivers/dma/loop_transfer/src/test_dma_loop.c +++ b/tests/drivers/dma/loop_transfer/src/test_dma_loop.c @@ -169,6 +169,8 @@ static int test_loop(const struct device *dma) } } + dma_release_channel(dma, chan_id); + TC_PRINT("Finished DMA: %s\n", dma->name); return TC_PASS; } @@ -314,6 +316,8 @@ static int test_loop_suspend_resume(const struct device *dma) } } + dma_release_channel(dma, chan_id); + TC_PRINT("Finished DMA: %s\n", dma->name); return TC_PASS; } @@ -468,6 +472,8 @@ static int test_loop_repeated_start_stop(const struct device *dma) return TC_FAIL; } + dma_release_channel(dma, chan_id); + return TC_PASS; } diff --git a/tests/drivers/dma/scatter_gather/boards/bg29_rb4420a.overlay b/tests/drivers/dma/scatter_gather/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..a6fb1d7e0945b --- /dev/null +++ b/tests/drivers/dma/scatter_gather/boards/bg29_rb4420a.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Silicon Laboratories, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + dma0 = &dma0; + }; +}; + +&dma0 { + status = "okay"; +}; diff --git a/tests/drivers/dma/scatter_gather/boards/native_sim.overlay b/tests/drivers/dma/scatter_gather/boards/native_sim.overlay index 8afb0753c106b..8f2083b22046e 100644 --- a/tests/drivers/dma/scatter_gather/boards/native_sim.overlay +++ b/tests/drivers/dma/scatter_gather/boards/native_sim.overlay @@ -10,4 +10,4 @@ status = "okay"; }; -test_dma0: &dma { }; +test_dma0: &dma {}; diff --git a/tests/drivers/dma/scatter_gather/boards/sltb010a.overlay b/tests/drivers/dma/scatter_gather/boards/sltb010a.overlay index c9b4e95a7cd20..430bbbbd3dd0a 100644 --- a/tests/drivers/dma/scatter_gather/boards/sltb010a.overlay +++ b/tests/drivers/dma/scatter_gather/boards/sltb010a.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { aliases { dma0 = &dma0; diff --git a/tests/drivers/dma/scatter_gather/testcase.yaml b/tests/drivers/dma/scatter_gather/testcase.yaml index 00b6d86450814..0e08abae59da4 100644 --- a/tests/drivers/dma/scatter_gather/testcase.yaml +++ b/tests/drivers/dma/scatter_gather/testcase.yaml @@ -20,6 +20,7 @@ tests: - siwx917_dk2605a - adp_xc7k/ae350 - adp_xc7k/ae350/clic + - bg29_rb4420a filter: dt_alias_exists("dma0") integration_platforms: - intel_adsp/cavs25 diff --git a/tests/drivers/eeprom/api/boards/mec172xevb_assy6906.overlay b/tests/drivers/eeprom/api/boards/mec172xevb_assy6906.overlay index 322a421bbe4d2..db352ee0517f9 100644 --- a/tests/drivers/eeprom/api/boards/mec172xevb_assy6906.overlay +++ b/tests/drivers/eeprom/api/boards/mec172xevb_assy6906.overlay @@ -14,8 +14,8 @@ status = "okay"; pinctrl-0 = <&eeprom_cs_gpio116 - &eeprom_clk_gpio117 - &eeprom_mosi_gpio074 - &eeprom_miso_gpio075>; + &eeprom_clk_gpio117 + &eeprom_mosi_gpio074 + &eeprom_miso_gpio075>; pinctrl-names = "default"; }; diff --git a/tests/drivers/eeprom/shell/app.overlay b/tests/drivers/eeprom/shell/app.overlay index c46d58f7866b8..c2b91d1beb1bc 100644 --- a/tests/drivers/eeprom/shell/app.overlay +++ b/tests/drivers/eeprom/shell/app.overlay @@ -6,7 +6,7 @@ #include -/{ +/ { fake_eeprom: fake_eeprom { compatible = "zephyr,fake-eeprom"; status = "okay"; diff --git a/tests/drivers/flash/common/Kconfig b/tests/drivers/flash/common/Kconfig index 4cf79fc6d8b9a..1327ddf320c42 100644 --- a/tests/drivers/flash/common/Kconfig +++ b/tests/drivers/flash/common/Kconfig @@ -8,11 +8,12 @@ DT_CHOSEN_Z_FLASH := zephyr,flash config TEST_DRIVER_FLASH_SIZE int "Size of flash device under test" - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0) if SOC_FAMILY_STM32 + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0) \ + if (SOC_FAMILY_STM32 && !SOC_SERIES_STM32N6X) default -1 help Expected flash device size the test will validate against. If the flash driver does not support the get_size() API, leave this set as -1 to skip the test. - For the STM32 devices, the flash size is direclty given by the soc DTSI. + For the STM32 devices, the flash size is directly given by the soc DTSI. source "Kconfig.zephyr" diff --git a/tests/drivers/flash/common/boards/b_u585i_iot02a_stm32u585xx_ns.overlay b/tests/drivers/flash/common/boards/b_u585i_iot02a_stm32u585xx_ns.overlay deleted file mode 100644 index 83ad465e23387..0000000000000 --- a/tests/drivers/flash/common/boards/b_u585i_iot02a_stm32u585xx_ns.overlay +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022, STMicroelectronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - /{ - chosen { - zephyr,code-partition = &slot0_ns_partition; - }; -}; - -&flash0 { - partitions { - /delete-node/ slot0_partition; - /* Non-secure image primary slot */ - slot0_ns_partition: partition@98000 { - label = "image-0-nonsecure"; - reg = <0x00098000 DT_SIZE_K(512)>; - }; - }; -}; diff --git a/tests/drivers/flash/common/boards/bg29_rb4420a.overlay b/tests/drivers/flash/common/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..c556be1b72aec --- /dev/null +++ b/tests/drivers/flash/common/boards/bg29_rb4420a.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&dma0 { + status = "okay"; +}; + +&msc { + dmas = <&dma0 DMA_REQSEL_MSCWDATA>; +}; + +/* Disable jedec spi nor flash to test internal flash */ + +/ { + + aliases { + /delete-property/ spi-flash0; + }; +}; + +/delete-node/ &mx25r80; diff --git a/tests/drivers/flash/common/boards/ek_ra6e2.overlay b/tests/drivers/flash/common/boards/ek_ra6e2.overlay index 2b8ad1e1e6c21..6f0c4c7cb8658 100644 --- a/tests/drivers/flash/common/boards/ek_ra6e2.overlay +++ b/tests/drivers/flash/common/boards/ek_ra6e2.overlay @@ -18,3 +18,7 @@ }; }; }; + +&at25sf128a { + status = "disabled"; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra6e2_qspi_nor.conf b/tests/drivers/flash/common/boards/ek_ra6e2_qspi_nor.conf new file mode 100644 index 0000000000000..d8d3631c5d59c --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6e2_qspi_nor.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_TEST_DRIVER_FLASH_SIZE=16777216 diff --git a/tests/drivers/flash/common/boards/ek_ra6e2_qspi_nor.overlay b/tests/drivers/flash/common/boards/ek_ra6e2_qspi_nor.overlay new file mode 100644 index 0000000000000..639996d93e576 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6e2_qspi_nor.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &storage_partition; + +&at25sf128a { + status = "okay"; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra6m3.overlay b/tests/drivers/flash/common/boards/ek_ra6m3.overlay index d1b6a6776373b..5692054a716bb 100644 --- a/tests/drivers/flash/common/boards/ek_ra6m3.overlay +++ b/tests/drivers/flash/common/boards/ek_ra6m3.overlay @@ -18,3 +18,7 @@ }; }; }; + +&mx25l25645g { + status = "disabled"; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra6m3_qspi_nor.conf b/tests/drivers/flash/common/boards/ek_ra6m3_qspi_nor.conf new file mode 100644 index 0000000000000..dc601c6675990 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6m3_qspi_nor.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_TEST_DRIVER_FLASH_SIZE=33554432 diff --git a/tests/drivers/flash/common/boards/ek_ra6m3_qspi_nor.overlay b/tests/drivers/flash/common/boards/ek_ra6m3_qspi_nor.overlay new file mode 100644 index 0000000000000..a0268c82da1a1 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6m3_qspi_nor.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &storage_partition; + +&mx25l25645g { + status = "okay"; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra6m4.overlay b/tests/drivers/flash/common/boards/ek_ra6m4.overlay index a910732a53a22..cc09229e41e25 100644 --- a/tests/drivers/flash/common/boards/ek_ra6m4.overlay +++ b/tests/drivers/flash/common/boards/ek_ra6m4.overlay @@ -18,3 +18,7 @@ }; }; }; + +&mx25l25645g { + status = "disabled"; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra6m4_qspi_nor.conf b/tests/drivers/flash/common/boards/ek_ra6m4_qspi_nor.conf new file mode 100644 index 0000000000000..dc601c6675990 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6m4_qspi_nor.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_TEST_DRIVER_FLASH_SIZE=33554432 diff --git a/tests/drivers/flash/common/boards/ek_ra6m4_qspi_nor.overlay b/tests/drivers/flash/common/boards/ek_ra6m4_qspi_nor.overlay new file mode 100644 index 0000000000000..a0268c82da1a1 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6m4_qspi_nor.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &storage_partition; + +&mx25l25645g { + status = "okay"; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra6m5.overlay b/tests/drivers/flash/common/boards/ek_ra6m5.overlay index d1b6a6776373b..8d36cc7d2caa8 100644 --- a/tests/drivers/flash/common/boards/ek_ra6m5.overlay +++ b/tests/drivers/flash/common/boards/ek_ra6m5.overlay @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * SPDX-License-Identifier: Apache-2.0 */ @@ -18,3 +18,7 @@ }; }; }; + +&mx25l25645g { + status = "disabled"; +}; diff --git a/tests/drivers/flash/common/boards/ek_ra6m5_qspi_nor.conf b/tests/drivers/flash/common/boards/ek_ra6m5_qspi_nor.conf new file mode 100644 index 0000000000000..dc601c6675990 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6m5_qspi_nor.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_TEST_DRIVER_FLASH_SIZE=33554432 diff --git a/tests/drivers/flash/common/boards/ek_ra6m5_qspi_nor.overlay b/tests/drivers/flash/common/boards/ek_ra6m5_qspi_nor.overlay new file mode 100644 index 0000000000000..a0268c82da1a1 --- /dev/null +++ b/tests/drivers/flash/common/boards/ek_ra6m5_qspi_nor.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &storage_partition; + +&mx25l25645g { + status = "okay"; +}; diff --git a/tests/drivers/flash/common/boards/mx25uw63_single_io.overlay b/tests/drivers/flash/common/boards/mx25uw63_single_io.overlay index a24ba4e548962..062020aea3533 100644 --- a/tests/drivers/flash/common/boards/mx25uw63_single_io.overlay +++ b/tests/drivers/flash/common/boards/mx25uw63_single_io.overlay @@ -40,7 +40,6 @@ ; }; }; - }; &gpio6 { diff --git a/tests/drivers/flash/common/boards/nrf52840dk_mx25l51245g.overlay b/tests/drivers/flash/common/boards/nrf52840dk_mx25l51245g.overlay index 737723307913c..71a8e99c34561 100644 --- a/tests/drivers/flash/common/boards/nrf52840dk_mx25l51245g.overlay +++ b/tests/drivers/flash/common/boards/nrf52840dk_mx25l51245g.overlay @@ -48,12 +48,10 @@ readoc = "read4io"; sck-frequency = <2000000>; jedec-id = [c2 20 1A]; - sfdp-bfp = [ - e5 20 fb ff 1f ff ff ff 44 eb 08 6b 08 3b 04 bb - fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 - 10 d8 00 ff d6 49 c5 00 81 df 04 e3 44 03 67 38 - 30 b0 30 b0 f7 bd d5 5c 4a 9e 29 ff f0 50 f9 85 - ]; + sfdp-bfp = [e5 20 fb ff 1f ff ff ff 44 eb 08 6b 08 3b 04 bb + fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 + 10 d8 00 ff d6 49 c5 00 81 df 04 e3 44 03 67 38 + 30 b0 30 b0 f7 bd d5 5c 4a 9e 29 ff f0 50 f9 85]; size = <0x20000000>; has-dpd; t-enter-dpd = <10000>; diff --git a/tests/drivers/flash/common/boards/nrf52840dk_mx25r_high_perf.overlay b/tests/drivers/flash/common/boards/nrf52840dk_mx25r_high_perf.overlay index 7e0d89cd92e71..af115dd4e9656 100644 --- a/tests/drivers/flash/common/boards/nrf52840dk_mx25r_high_perf.overlay +++ b/tests/drivers/flash/common/boards/nrf52840dk_mx25r_high_perf.overlay @@ -14,12 +14,10 @@ reg = <0>; spi-max-frequency = <33000000>; jedec-id = [c2 28 17]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; + sfdp-bfp = [e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; size = <67108864>; has-dpd; t-enter-dpd = <10000>; diff --git a/tests/drivers/flash/common/boards/nrf52840dk_spi_nor.overlay b/tests/drivers/flash/common/boards/nrf52840dk_spi_nor.overlay index 922ab42beb47f..1658c1dab59cc 100644 --- a/tests/drivers/flash/common/boards/nrf52840dk_spi_nor.overlay +++ b/tests/drivers/flash/common/boards/nrf52840dk_spi_nor.overlay @@ -11,18 +11,18 @@ &pinctrl { spi0_default: spi0_default { group1 { - psels = , - , - ; + psels = , + , + ; }; }; spi0_sleep: spi0_sleep { group1 { - psels = , - , - ; - low-power-enable; + psels = , + , + ; + low-power-enable; }; }; }; @@ -44,12 +44,10 @@ has-dpd; t-enter-dpd = <10000>; t-exit-dpd = <45000>; - jedec-id = [ C2 23 15 ]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f1 00 82 ec 04 c2 44 83 48 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; + jedec-id = [C2 23 15]; + sfdp-bfp = [e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f1 00 82 ec 04 c2 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; }; }; diff --git a/tests/drivers/flash/common/boards/nrf52840dk_spi_nor_wp_hold.overlay b/tests/drivers/flash/common/boards/nrf52840dk_spi_nor_wp_hold.overlay index c4bcbf280baa8..bb876888320f8 100644 --- a/tests/drivers/flash/common/boards/nrf52840dk_spi_nor_wp_hold.overlay +++ b/tests/drivers/flash/common/boards/nrf52840dk_spi_nor_wp_hold.overlay @@ -11,18 +11,18 @@ &pinctrl { spi0_default: spi0_default { group1 { - psels = , - , - ; + psels = , + , + ; }; }; spi0_sleep: spi0_sleep { group1 { - psels = , - , - ; - low-power-enable; + psels = , + , + ; + low-power-enable; }; }; }; @@ -46,12 +46,10 @@ has-dpd; t-enter-dpd = <10000>; t-exit-dpd = <45000>; - jedec-id = [ C2 23 15 ]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f1 00 82 ec 04 c2 44 83 48 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; + jedec-id = [C2 23 15]; + sfdp-bfp = [e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f1 00 82 ec 04 c2 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff]; }; }; diff --git a/tests/drivers/flash/common/boards/stm32n6570_dk_stm32n657xx_sb.conf b/tests/drivers/flash/common/boards/stm32n6570_dk_stm32n657xx_sb.conf new file mode 100644 index 0000000000000..be1ee4e81cbb4 --- /dev/null +++ b/tests/drivers/flash/common/boards/stm32n6570_dk_stm32n657xx_sb.conf @@ -0,0 +1 @@ +CONFIG_TEST_DRIVER_FLASH_SIZE=134217728 diff --git a/tests/drivers/flash/common/boards/xg29_rb4412a.overlay b/tests/drivers/flash/common/boards/xg29_rb4412a.overlay index c5d1c35f027a7..c556be1b72aec 100644 --- a/tests/drivers/flash/common/boards/xg29_rb4412a.overlay +++ b/tests/drivers/flash/common/boards/xg29_rb4412a.overlay @@ -12,7 +12,6 @@ dmas = <&dma0 DMA_REQSEL_MSCWDATA>; }; - /* Disable jedec spi nor flash to test internal flash */ / { diff --git a/tests/drivers/flash/common/src/main.c b/tests/drivers/flash/common/src/main.c index ab0e63bb60924..337876a9e8d76 100644 --- a/tests/drivers/flash/common/src/main.c +++ b/tests/drivers/flash/common/src/main.c @@ -12,12 +12,16 @@ #if defined(CONFIG_NORDIC_QSPI_NOR) #define TEST_AREA_DEV_NODE DT_INST(0, nordic_qspi_nor) +#elif defined(SOC_SERIES_STM32N6X) +#define TEST_AREA_DEV_NODE DT_INST(0, st_stm32_xspi_nor) #elif defined(CONFIG_FLASH_RENESAS_RA_OSPI_B) #define TEST_AREA_DEV_NODE DT_INST(0, renesas_ra_ospi_b_nor) #elif defined(CONFIG_SPI_NOR) #define TEST_AREA_DEV_NODE DT_INST(0, jedec_spi_nor) #elif defined(CONFIG_FLASH_MSPI_NOR) #define TEST_AREA_DEV_NODE DT_INST(0, jedec_mspi_nor) +#elif defined(CONFIG_FLASH_RENESAS_RA_QSPI) +#define TEST_AREA_DEV_NODE DT_INST(0, renesas_ra_qspi_nor) #else #define TEST_AREA storage_partition #endif @@ -26,6 +30,7 @@ * fixed-partition nodes. */ #ifdef TEST_AREA + #define TEST_AREA_OFFSET FIXED_PARTITION_OFFSET(TEST_AREA) #define TEST_AREA_SIZE FIXED_PARTITION_SIZE(TEST_AREA) #define TEST_AREA_MAX (TEST_AREA_OFFSET + TEST_AREA_SIZE) diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml index fff3a8cc1647f..34123ffde77f3 100644 --- a/tests/drivers/flash/common/testcase.yaml +++ b/tests/drivers/flash/common/testcase.yaml @@ -117,12 +117,14 @@ tests: platform_allow: - xg24_rb4187c - xg29_rb4412a + - bg29_rb4420a extra_configs: - CONFIG_DMA=y drivers.flash.common.silabs.dma.lpwrite: platform_allow: - xg24_rb4187c - xg29_rb4412a + - bg29_rb4420a extra_configs: - CONFIG_DMA=y extra_args: @@ -131,6 +133,7 @@ tests: platform_allow: - xg24_rb4187c - xg29_rb4412a + - bg29_rb4420a extra_configs: - CONFIG_DMA=y - CONFIG_SOC_FLASH_SILABS_S2_DMA_READ=y @@ -169,3 +172,13 @@ tests: - nrf54h20dk/nrf54h20/cpuapp extra_args: - EXTRA_DTC_OVERLAY_FILE=boards/mx25uw63_single_io.overlay + drivers.flash.common.ra_qspi_nor: + filter: CONFIG_FLASH_RENESAS_RA_QSPI and dt_compat_enabled("renesas,ra-qspi-nor") + platform_allow: + - ek_ra6m5 + - ek_ra6m4 + - ek_ra6m3 + - ek_ra6e2 + extra_args: + - DTC_OVERLAY_FILE="./boards/${BOARD}_qspi_nor.overlay" + - CONF_FILE="./prj.conf ./boards/${BOARD}_qspi_nor.conf" diff --git a/tests/drivers/flash_simulator/flash_sim_impl/boards/native_ev_0x00.overlay b/tests/drivers/flash_simulator/flash_sim_impl/boards/native_ev_0x00.overlay index 5a7030b393719..da0e54cb09686 100644 --- a/tests/drivers/flash_simulator/flash_sim_impl/boards/native_ev_0x00.overlay +++ b/tests/drivers/flash_simulator/flash_sim_impl/boards/native_ev_0x00.overlay @@ -5,7 +5,7 @@ */ &flashcontroller0 { - erase-value = < 0x00 >; + erase-value = <0x00>; }; &flash0 { diff --git a/tests/drivers/flash_simulator/flash_sim_impl/boards/nucleo_f411re.overlay b/tests/drivers/flash_simulator/flash_sim_impl/boards/nucleo_f411re.overlay index 60ce2f36e2187..d8b0071c94c0a 100644 --- a/tests/drivers/flash_simulator/flash_sim_impl/boards/nucleo_f411re.overlay +++ b/tests/drivers/flash_simulator/flash_sim_impl/boards/nucleo_f411re.overlay @@ -5,7 +5,7 @@ */ / { - sram_2001C000:sram@2001C000 { + sram_2001C000: sram@2001C000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x2001C000 0x4000>; zephyr,memory-region = "FlashSim"; diff --git a/tests/drivers/flash_simulator/flash_sim_impl/boards/qemu_x86_ev_0x00.overlay b/tests/drivers/flash_simulator/flash_sim_impl/boards/qemu_x86_ev_0x00.overlay index 0f122e3400752..5dc5f348824c5 100644 --- a/tests/drivers/flash_simulator/flash_sim_impl/boards/qemu_x86_ev_0x00.overlay +++ b/tests/drivers/flash_simulator/flash_sim_impl/boards/qemu_x86_ev_0x00.overlay @@ -5,5 +5,5 @@ */ &sim_flash { - erase-value = < 0x00 >; + erase-value = <0x00>; }; diff --git a/tests/drivers/flash_simulator/flash_sim_reboot/boards/mps2_an385.overlay b/tests/drivers/flash_simulator/flash_sim_reboot/boards/mps2_an385.overlay index 8672ce0e8eb5a..77623e89347f9 100644 --- a/tests/drivers/flash_simulator/flash_sim_reboot/boards/mps2_an385.overlay +++ b/tests/drivers/flash_simulator/flash_sim_reboot/boards/mps2_an385.overlay @@ -1,7 +1,7 @@ #include / { - sram_203F0000:sram@203F0000 { + sram_203F0000: sram@203F0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x203F0000 0x10000>; zephyr,memory-region = "FlashSim"; diff --git a/tests/kernel/pipe/deprecated/pipe/CMakeLists.txt b/tests/drivers/fuel_gauge/bq40z50/CMakeLists.txt similarity index 75% rename from tests/kernel/pipe/deprecated/pipe/CMakeLists.txt rename to tests/drivers/fuel_gauge/bq40z50/CMakeLists.txt index ac8bc4dee4622..70ed89044d394 100644 --- a/tests/kernel/pipe/deprecated/pipe/CMakeLists.txt +++ b/tests/drivers/fuel_gauge/bq40z50/CMakeLists.txt @@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(pipe) +project(device) -FILE(GLOB app_sources src/*.c) +FILE(GLOB app_sources src/test_bq40z50.c) target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/fuel_gauge/bq40z50/boards/native_sim.conf b/tests/drivers/fuel_gauge/bq40z50/boards/native_sim.conf new file mode 100644 index 0000000000000..022a71dd0f0a6 --- /dev/null +++ b/tests/drivers/fuel_gauge/bq40z50/boards/native_sim.conf @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_EMUL=y diff --git a/tests/drivers/fuel_gauge/bq40z50/boards/native_sim.overlay b/tests/drivers/fuel_gauge/bq40z50/boards/native_sim.overlay new file mode 100644 index 0000000000000..a66d30d2cb70c --- /dev/null +++ b/tests/drivers/fuel_gauge/bq40z50/boards/native_sim.overlay @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +&i2c0 { + bq40z50: bq40z50@16{ + compatible = "ti,bq40z50"; + reg = <0x16>; + status = "okay"; + }; +}; diff --git a/tests/drivers/fuel_gauge/bq40z50/boards/rpi_pico.overlay b/tests/drivers/fuel_gauge/bq40z50/boards/rpi_pico.overlay new file mode 100644 index 0000000000000..05e77729a400d --- /dev/null +++ b/tests/drivers/fuel_gauge/bq40z50/boards/rpi_pico.overlay @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +&i2c0 { + bq40z50: bq40z50@16 { + compatible="ti,bq40z50"; + reg = <0x16>; + status = "okay"; + }; +}; diff --git a/tests/drivers/fuel_gauge/bq40z50/prj.conf b/tests/drivers/fuel_gauge/bq40z50/prj.conf new file mode 100644 index 0000000000000..ce11abb435a4a --- /dev/null +++ b/tests/drivers/fuel_gauge/bq40z50/prj.conf @@ -0,0 +1,6 @@ +CONFIG_ZTEST=y +CONFIG_I2C=y +CONFIG_TEST_USERSPACE=y +CONFIG_LOG=y + +CONFIG_FUEL_GAUGE=y diff --git a/tests/drivers/fuel_gauge/bq40z50/src/test_bq40z50.c b/tests/drivers/fuel_gauge/bq40z50/src/test_bq40z50.c new file mode 100644 index 0000000000000..10173a3c2daac --- /dev/null +++ b/tests/drivers/fuel_gauge/bq40z50/src/test_bq40z50.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct bq40z50_fixture { + const struct device *dev; + const struct fuel_gauge_driver_api *api; +}; + +static void *bq40z50_setup(void) +{ + static ZTEST_DMEM struct bq40z50_fixture fixture; + + fixture.dev = DEVICE_DT_GET_ANY(ti_bq40z50); + k_object_access_all_grant(fixture.dev); + + zassert_true(device_is_ready(fixture.dev), "Fuel Gauge not found"); + + return &fixture; +} + +ZTEST_USER_F(bq40z50, test_get_some_props_failed_returns_bad_status) +{ + fuel_gauge_prop_t props[] = { + /* First invalid property */ + FUEL_GAUGE_PROP_MAX, + /* Second invalid property */ + FUEL_GAUGE_PROP_MAX, + /* Valid property */ + FUEL_GAUGE_VOLTAGE, + }; + union fuel_gauge_prop_val vals[ARRAY_SIZE(props)]; + + int ret = fuel_gauge_get_props(fixture->dev, props, vals, ARRAY_SIZE(props)); + + zassert_equal(ret, -ENOTSUP, "Getting bad property has a good status."); +} + +ZTEST_USER_F(bq40z50, test_get_buffer_prop) +{ + int ret; + + { + struct sbs_gauge_manufacturer_name mfg_name; + + ret = fuel_gauge_get_buffer_prop(fixture->dev, FUEL_GAUGE_MANUFACTURER_NAME, + &mfg_name, sizeof(mfg_name)); + zassert_ok(ret); +#if CONFIG_EMUL + /* Only test for fixed values in emulation since the real device might be */ + /* reprogrammed and respond with different values */ + zassert_equal(sizeof("Texas Inst.") - 1, mfg_name.manufacturer_name_length); + zassert_mem_equal(mfg_name.manufacturer_name, "Texas Inst.", + mfg_name.manufacturer_name_length, + "mfg_name.manufacturer_name='%s'", mfg_name.manufacturer_name); +#endif + } + { + struct sbs_gauge_device_name dev_name; + + ret = fuel_gauge_get_buffer_prop(fixture->dev, FUEL_GAUGE_DEVICE_NAME, &dev_name, + sizeof(dev_name)); + zassert_ok(ret); +#if CONFIG_EMUL + /* Only test for fixed values in emulation since the real device might be */ + /* reprogrammed and respond with different values */ + zassert_equal(sizeof("bq40z50") - 1, dev_name.device_name_length); + zassert_mem_equal(dev_name.device_name, "bq40z50", dev_name.device_name_length); +#endif + } + { + struct sbs_gauge_device_chemistry device_chemistry; + + ret = fuel_gauge_get_buffer_prop(fixture->dev, FUEL_GAUGE_DEVICE_CHEMISTRY, + &device_chemistry, sizeof(device_chemistry)); + zassert_ok(ret); +#if CONFIG_EMUL + /* Only test for fixed values in emulation since the real device might be */ + /* reprogrammed and respond with different values */ + zassert_equal(sizeof("LION") - 1, device_chemistry.device_chemistry_length); + zassert_mem_equal(device_chemistry.device_chemistry, "LION", + device_chemistry.device_chemistry_length); +#endif + } +} + +ZTEST_USER_F(bq40z50, test_get_props__returns_ok) +{ + /* Validate what props are supported by the driver */ + + fuel_gauge_prop_t props[] = { + FUEL_GAUGE_AVG_CURRENT, + FUEL_GAUGE_CURRENT, + FUEL_GAUGE_CHARGE_CUTOFF, + FUEL_GAUGE_CYCLE_COUNT, + FUEL_GAUGE_FULL_CHARGE_CAPACITY, + FUEL_GAUGE_REMAINING_CAPACITY, + FUEL_GAUGE_RUNTIME_TO_EMPTY, + FUEL_GAUGE_SBS_MFR_ACCESS, + FUEL_GAUGE_ABSOLUTE_STATE_OF_CHARGE, + FUEL_GAUGE_RELATIVE_STATE_OF_CHARGE, + FUEL_GAUGE_TEMPERATURE, + FUEL_GAUGE_VOLTAGE, + FUEL_GAUGE_SBS_MODE, + FUEL_GAUGE_CHARGE_CURRENT, + FUEL_GAUGE_CHARGE_VOLTAGE, + FUEL_GAUGE_STATUS, + FUEL_GAUGE_DESIGN_CAPACITY, + FUEL_GAUGE_DESIGN_VOLTAGE, + FUEL_GAUGE_SBS_ATRATE, + FUEL_GAUGE_SBS_ATRATE_TIME_TO_FULL, + FUEL_GAUGE_SBS_ATRATE_TIME_TO_EMPTY, + FUEL_GAUGE_SBS_ATRATE_OK, + FUEL_GAUGE_SBS_REMAINING_CAPACITY_ALARM, + FUEL_GAUGE_SBS_REMAINING_TIME_ALARM, + + }; + union fuel_gauge_prop_val vals[ARRAY_SIZE(props)]; + + zassert_ok(fuel_gauge_get_props(fixture->dev, props, vals, ARRAY_SIZE(props))); + /* Check properties for valid ranges */ +#if CONFIG_EMUL + zassert_equal(vals[0].avg_current, 1 * 1000); + zassert_equal(vals[1].current, 1 * 1000); + /* Not testing props[2]. This is the charger cutoff and has a boolean.*/ + zassert_equal(vals[3].cycle_count, 1); + zassert_equal(vals[4].full_charge_capacity, 1 * 1000); + zassert_equal(vals[5].remaining_capacity, 1 * 1000); + zassert_equal(vals[6].runtime_to_empty, 65535); + /* Not testing props[7]. This is the manufacturer access and has only status bits */ + zassert_equal(vals[8].absolute_state_of_charge, 100); + zassert_equal(vals[9].relative_state_of_charge, 100); + zassert_equal(vals[10].temperature, 2980); + zassert_equal(vals[11].voltage, 1 * 1000); + zassert_equal(vals[12].sbs_mode, 0); + zassert_equal(vals[13].chg_current, 1 * 1000); + zassert_equal(vals[14].chg_voltage, 1 * 1000); + /* Not testing props[15]. This property is the status and only has only status bits */ + zassert_equal(vals[16].design_cap, 1); + zassert_equal(vals[17].design_volt, 14400); + zassert_equal(vals[18].sbs_at_rate, 0); + zassert_equal(vals[19].sbs_at_rate_time_to_full, 65535); + zassert_equal(vals[20].sbs_at_rate_time_to_empty, 65535); + zassert_equal(vals[21].sbs_at_rate_ok, 0); + zassert_equal(vals[22].sbs_remaining_capacity_alarm, 300); + zassert_equal(vals[23].sbs_remaining_time_alarm, 10); +#else + /* When having a real device, check for the valid ranges */ + zassert_between_inclusive(vals[0].avg_current, -32767 * 1000, 32768 * 1000); + zassert_between_inclusive(vals[1].current, -32767 * 1000, 32768 * 1000); + /* Not testing props[2]. This is the charger cutoff and has a boolean.*/ + zassert_between_inclusive(vals[3].cycle_count, 0, 65535); + zassert_between_inclusive(vals[4].full_charge_capacity, 0, 65535 * 1000); + zassert_between_inclusive(vals[5].remaining_capacity, 0, 65535 * 1000); + zassert_between_inclusive(vals[6].runtime_to_empty, 0, 65535); + /* Not testing props[7]. This is the manufacturer access and has only status bits */ + zassert_between_inclusive(vals[8].absolute_state_of_charge, 0, 100); + zassert_between_inclusive(vals[9].relative_state_of_charge, 0, 100); + zassert_between_inclusive(vals[10].temperature, 0, 65535); + zassert_between_inclusive(vals[11].voltage, 0, 65535 * 1000); + zassert_between_inclusive(vals[12].sbs_mode, 0, 65535 * 1000); + zassert_between_inclusive(vals[13].chg_current, 0, 65535 * 1000); + zassert_between_inclusive(vals[14].chg_voltage, 0, 65535 * 1000); + /* Not testing props[15]. This property is the status and only has only status bits */ + zassert_between_inclusive(vals[16].design_cap, 0, 65535); + zassert_between_inclusive(vals[17].design_volt, 0, 18000); + zassert_between_inclusive(vals[18].sbs_at_rate, -32768, 32767); + zassert_between_inclusive(vals[19].sbs_at_rate_time_to_full, 0, 65535); + zassert_between_inclusive(vals[20].sbs_at_rate_time_to_empty, 0, 65535); + /* Not testing props[21]. This is the sbs_at_rate_ok property and has a boolean.*/ + zassert_between_inclusive(vals[22].sbs_remaining_capacity_alarm, 0, 1000); + zassert_between_inclusive(vals[23].sbs_remaining_time_alarm, 0, 30); +#endif +} + +ZTEST_SUITE(bq40z50, NULL, bq40z50_setup, NULL, NULL, NULL); diff --git a/tests/drivers/fuel_gauge/bq40z50/testcase.yaml b/tests/drivers/fuel_gauge/bq40z50/testcase.yaml new file mode 100644 index 0000000000000..7f08c7a856bd9 --- /dev/null +++ b/tests/drivers/fuel_gauge/bq40z50/testcase.yaml @@ -0,0 +1,7 @@ +tests: + drivers.fuel_gauge.bq40z50: + tags: + - fuel_gauge + filter: dt_compat_enabled("ti,bq40z50") + platform_allow: + - native_sim diff --git a/tests/drivers/fuel_gauge/sbs_gauge/boards/emulated_board_cutoff.overlay b/tests/drivers/fuel_gauge/sbs_gauge/boards/emulated_board_cutoff.overlay index cf40ff46b20bc..2b493608afa0f 100644 --- a/tests/drivers/fuel_gauge/sbs_gauge/boards/emulated_board_cutoff.overlay +++ b/tests/drivers/fuel_gauge/sbs_gauge/boards/emulated_board_cutoff.overlay @@ -21,7 +21,7 @@ clock-frequency = ; compatible = "zephyr,i2c-emul-controller"; smartbattery0: smartbattery@b { - compatible = "sbs,default-sbs-gauge","sbs,sbs-gauge-new-api"; + compatible = "sbs,default-sbs-gauge", "sbs,sbs-gauge-new-api"; reg = <0x0b>; status = "okay"; battery-cutoff-support; diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/aw9523b_on_arduino_header.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/aw9523b_on_arduino_header.overlay index ab5e9ebc2c469..2e6399642fc10 100644 --- a/tests/drivers/gpio/gpio_api_1pin/boards/aw9523b_on_arduino_header.overlay +++ b/tests/drivers/gpio/gpio_api_1pin/boards/aw9523b_on_arduino_header.overlay @@ -10,8 +10,8 @@ gpio-controller; #gpio-cells = <2>; port0-push-pull; - int-gpios = <&arduino_header 18 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; - reset-gpios = <&arduino_header 19 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; + int-gpios = <&arduino_header 18 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + reset-gpios = <&arduino_header 19 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; }; }; @@ -19,7 +19,7 @@ / { leds { aw9523_led0: aw9523_led0 { - gpios = < &aw9523_gpio 8 0>; + gpios = <&aw9523_gpio 8 0>; }; }; diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/bg29_rb4420a.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..9b33553413fdd --- /dev/null +++ b/tests/drivers/gpio/gpio_api_1pin/boards/bg29_rb4420a.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-external-pulldown"; + gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/particle_xenon.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/particle_xenon.overlay index 9c52ce5a5cde0..3fd37d97a2d4b 100644 --- a/tests/drivers/gpio/gpio_api_1pin/boards/particle_xenon.overlay +++ b/tests/drivers/gpio/gpio_api_1pin/boards/particle_xenon.overlay @@ -14,8 +14,8 @@ gpio_keys { compatible = "gpio-keys"; iox_button: button_2 { - gpios = <&sx1509b 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "IOX Button"; + gpios = <&sx1509b 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "IOX Button"; }; }; }; @@ -27,6 +27,6 @@ gpio-controller; #gpio-cells = <2>; ngpios = <16>; - nint-gpios =<&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + nint-gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; }; }; diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index 7ab7cc7049219..c39601e83e606 100644 --- a/tests/drivers/gpio/gpio_api_1pin/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/tests/drivers/gpio/gpio_api_1pin/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -16,7 +16,7 @@ }; }; -&gpio{ +&gpio { status = "okay"; }; diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/up_squared.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/up_squared.overlay index 1ca8989877f2e..eb2250690b331 100644 --- a/tests/drivers/gpio/gpio_api_1pin/boards/up_squared.overlay +++ b/tests/drivers/gpio/gpio_api_1pin/boards/up_squared.overlay @@ -26,6 +26,5 @@ gpios = <&gpio_w 19 0>; label = "HAT Pin 40 as LED"; }; - }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/aw9523b_on_arduino_header.overlay b/tests/drivers/gpio/gpio_basic_api/boards/aw9523b_on_arduino_header.overlay index 5d086016c1929..9833192752f46 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/aw9523b_on_arduino_header.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/aw9523b_on_arduino_header.overlay @@ -9,8 +9,8 @@ compatible = "awinic,aw9523b-gpio"; gpio-controller; #gpio-cells = <2>; - int-gpios = <&arduino_header 18 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; - reset-gpios = <&arduino_header 19 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; + int-gpios = <&arduino_header 18 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + reset-gpios = <&arduino_header 19 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bg29_rb4420a.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..eb0da033f5ef9 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/bg29_rb4420a.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpioc 5 0>; /* WPK EXP4 (PC5) */ + in-gpios = <&gpioc 3 0>; /* WPK EXP6 (PC3) */ + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_procpu.overlay b/tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_procpu.overlay index a29c21b4265af..eef6470e08dc2 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_procpu.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/esp32_devkitc_procpu.overlay @@ -12,7 +12,6 @@ }; }; - /* * Some notes about esp32 pins: * GPIO pins 34-39 are not suitable for this test because: diff --git a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke15z.overlay b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke15z.overlay index 68c941f0cd5dc..853fe1d554f3e 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke15z.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke15z.overlay @@ -12,6 +12,6 @@ resources { compatible = "test-gpio-basic-api"; out-gpios = <&gpioc 8 0>; /* Arduino D0 */ - in-gpios = <&gpioc 9 0>; /* Arduino D1 */ + in-gpios = <&gpioc 9 0>; /* Arduino D1 */ }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z.overlay b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z.overlay index 3d87165cc5410..27d4709220a4d 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z.overlay @@ -8,6 +8,6 @@ resources { compatible = "test-gpio-basic-api"; out-gpios = <&gpiod 8 0>; /* Arduino D2 */ - in-gpios = <&gpiod 9 0>; /* Arduino D3 */ + in-gpios = <&gpiod 9 0>; /* Arduino D3 */ }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z512.overlay b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z512.overlay index ef954c7e16815..a902b873d8892 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z512.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z512.overlay @@ -8,7 +8,7 @@ resources { compatible = "test-gpio-basic-api"; out-gpios = <&gpioc 6 0>; /* Arduino D0 J1-2 */ - in-gpios = <&gpioc 7 0>; /* Arduino D1 J1-4 */ + in-gpios = <&gpioc 7 0>; /* Arduino D1 J1-4 */ }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z_fgpio.overlay b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z_fgpio.overlay index ec980dbeee604..90ec5f90e7096 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z_fgpio.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/frdm_ke17z_fgpio.overlay @@ -8,10 +8,10 @@ resources { compatible = "test-gpio-basic-api"; out-gpios = <&fgpioa 14 0>; /* J1-16 */ - in-gpios = <&fgpioa 17 0>; /* J1-14 */ + in-gpios = <&fgpioa 17 0>; /* J1-14 */ }; }; -&fgpioa{ +&fgpioa { status = "okay"; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay index 74dc34e872a35..e42ca7fc48b57 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { resources { compatible = "test-gpio-basic-api"; /* diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay index 74dc34e872a35..e42ca7fc48b57 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { resources { compatible = "test-gpio-basic-api"; /* diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay index c43cf4c1b1b81..eaf87c60a6d3a 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { resources { compatible = "test-gpio-basic-api"; /* diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx91_evk_mimx9131.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx91_evk_mimx9131.overlay index 69eaac162593d..cd3dc05f43970 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/imx91_evk_mimx9131.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/imx91_evk_mimx9131.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { resources { compatible = "test-gpio-basic-api"; /* diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx93_evk_mimx9352_a55.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx93_evk_mimx9352_a55.overlay index d28f7d93da7f0..4ef709a982417 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/imx93_evk_mimx9352_a55.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/imx93_evk_mimx9352_a55.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { resources { compatible = "test-gpio-basic-api"; out-gpios = <&gpio2 13 0>; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_a55.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_a55.overlay index fe6d484413ae1..874e45931aca3 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_a55.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_a55.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { resources { compatible = "test-gpio-basic-api"; /* diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_m33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_m33.overlay index fe6d484413ae1..874e45931aca3 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_m33.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/imx943_evk_mimx94398_m33.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { resources { compatible = "test-gpio-basic-api"; /* diff --git a/tests/drivers/gpio/gpio_basic_api/boards/intel_adl_crb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/intel_adl_crb.overlay index 90c1c06fdcd9f..4a223fb48dd32 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/intel_adl_crb.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/intel_adl_crb.overlay @@ -17,6 +17,6 @@ compatible = "test-gpio-basic-api"; out-gpios = <&gpio_b 14 0>; - in-gpios = <&gpio_b 15 0>; + in-gpios = <&gpio_b 15 0>; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/intel_btl_s_crb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/intel_btl_s_crb.overlay index aeca82c44e312..5785515020f82 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/intel_btl_s_crb.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/intel_btl_s_crb.overlay @@ -12,6 +12,6 @@ compatible = "test-gpio-basic-api"; out-gpios = <&gpio_0_i 16 0>; - in-gpios = <&gpio_0_i 17 0>; + in-gpios = <&gpio_0_i 17 0>; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/intel_ehl_crb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/intel_ehl_crb.overlay index 3cdf02964f8d5..5e4bd121a7e1c 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/intel_ehl_crb.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/intel_ehl_crb.overlay @@ -21,6 +21,6 @@ compatible = "test-gpio-basic-api"; out-gpios = <&gpio_0_b 4 0>; - in-gpios = <&gpio_0_b 23 0>; + in-gpios = <&gpio_0_b 23 0>; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_p_crb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_p_crb.overlay index 14a6f676558e3..601172402b274 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_p_crb.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_p_crb.overlay @@ -8,6 +8,6 @@ compatible = "test-gpio-basic-api"; out-gpios = <&gpio_4_e 13 0>; - in-gpios = <&gpio_4_e 12 0>; + in-gpios = <&gpio_4_e 12 0>; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay index b7cacf75cb23e..e8b11353b15b3 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/intel_rpl_s_crb.overlay @@ -8,6 +8,6 @@ compatible = "test-gpio-basic-api"; out-gpios = <&gpio_0_i 16 0>; - in-gpios = <&gpio_0_i 17 0>; + in-gpios = <&gpio_0_i 17 0>; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s36.overlay b/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s36.overlay index 5149e81c73715..9d4868762e2c6 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s36.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s36.overlay @@ -10,6 +10,6 @@ resources { compatible = "test-gpio-basic-api"; out-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL | GPIO_PULL_UP)>; - in-gpios = <&arduino_header 1 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL | GPIO_PULL_UP)>; + in-gpios = <&arduino_header 1 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL | GPIO_PULL_UP)>; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index a2caa360a6d67..2235e33cf1d37 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -8,6 +8,6 @@ resources { compatible = "test-gpio-basic-api"; out-gpios = <&arduino_header 0 (GPIO_PUSH_PULL | GPIO_PULL_UP)>; /* Arduino A0 */ - in-gpios = <&arduino_header 1 (GPIO_PUSH_PULL | GPIO_PULL_UP)>; /* Arduino A1 */ + in-gpios = <&arduino_header 1 (GPIO_PUSH_PULL | GPIO_PULL_UP)>; /* Arduino A1 */ }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mec15xxevb_assy6853.overlay b/tests/drivers/gpio/gpio_basic_api/boards/mec15xxevb_assy6853.overlay index 53a9d372a72c4..0aec8bc1af44d 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/mec15xxevb_assy6853.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/mec15xxevb_assy6853.overlay @@ -14,7 +14,7 @@ * Also remove jumpers on JP41 (1-2, 3-4) as the LEDs * are connected to pull-up resistors also. */ - in-gpios = ; /* GPIO_156, JP31 Pin 13 */ + in-gpios = ; /* GPIO_156, JP31 Pin 13 */ out-gpios = ; /* GPIO_157, JP31 Pin 15 */ }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mec172xevb_assy6906.overlay b/tests/drivers/gpio/gpio_basic_api/boards/mec172xevb_assy6906.overlay index 677957fdd603d..970a737b2fcec 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/mec172xevb_assy6906.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/mec172xevb_assy6906.overlay @@ -12,7 +12,7 @@ /* * Connect the JP71 pin 11 and 13 to test the GPIO loopback */ - in-gpios = ; /* GPIO_156, JP71 Pin 11 */ + in-gpios = ; /* GPIO_156, JP71 Pin 11 */ out-gpios = ; /* GPIO_157, JP71 Pin 13 */ }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/gpio/gpio_basic_api/boards/nrf54h20dk_nrf54h20_common.dtsi index 917e28211b81a..47da26b578996 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/nrf54h20dk_nrf54h20_common.dtsi +++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -15,5 +15,5 @@ &gpiote130 { status = "okay"; - owned-channels = < 0 1 >; + owned-channels = <0 1>; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l_sense_edge.overlay b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l_sense_edge.overlay new file mode 100644 index 0000000000000..59839fa9265b9 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l_sense_edge.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpio1 { + sense-edge-mask = <0xC00>; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/particle_xenon.overlay b/tests/drivers/gpio/gpio_basic_api/boards/particle_xenon.overlay index 9c52ce5a5cde0..3fd37d97a2d4b 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/particle_xenon.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/particle_xenon.overlay @@ -14,8 +14,8 @@ gpio_keys { compatible = "gpio-keys"; iox_button: button_2 { - gpios = <&sx1509b 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "IOX Button"; + gpios = <&sx1509b 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "IOX Button"; }; }; }; @@ -27,6 +27,6 @@ gpio-controller; #gpio-cells = <2>; ngpios = <16>; - nint-gpios =<&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + nint-gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.overlay index fd9fcf76dca80..1dabe785ba886 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.overlay @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { resources { diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index 58b19b4dc1232..1087f9b0b5c32 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -11,11 +11,11 @@ }; }; -&gpio{ +&gpio { status = "okay"; }; -&gpio8{ +&gpio8 { irqs = <3 20>; status = "okay"; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzt2l_rsk.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzt2l_rsk.overlay index baf12cf326390..9c90d26681665 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/rzt2l_rsk.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/rzt2l_rsk.overlay @@ -12,7 +12,7 @@ }; &pinctrl { - input_test: input_test{ + input_test: input_test { group1 { pinmux = ; input-enable; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/up_squared.overlay b/tests/drivers/gpio/gpio_basic_api/boards/up_squared.overlay index 2e578336684c7..a073a4813fe36 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/up_squared.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/up_squared.overlay @@ -21,6 +21,6 @@ compatible = "test-gpio-basic-api"; out-gpios = <&gpio_w 19 0>; /* HAT Pin 40 */ - in-gpios = <&gpio_w 18 0>; /* HAT Pin 38 */ + in-gpios = <&gpio_w 18 0>; /* HAT Pin 38 */ }; }; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/yd_esp32_procpu.overlay b/tests/drivers/gpio/gpio_basic_api/boards/yd_esp32_procpu.overlay index a29c21b4265af..eef6470e08dc2 100644 --- a/tests/drivers/gpio/gpio_basic_api/boards/yd_esp32_procpu.overlay +++ b/tests/drivers/gpio/gpio_basic_api/boards/yd_esp32_procpu.overlay @@ -12,7 +12,6 @@ }; }; - /* * Some notes about esp32 pins: * GPIO pins 34-39 are not suitable for this test because: diff --git a/tests/drivers/gpio/gpio_basic_api/testcase.yaml b/tests/drivers/gpio/gpio_basic_api/testcase.yaml index 8dcb4cecf9669..2acaf8d8f621c 100644 --- a/tests/drivers/gpio/gpio_basic_api/testcase.yaml +++ b/tests/drivers/gpio/gpio_basic_api/testcase.yaml @@ -24,6 +24,11 @@ tests: extra_args: "DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840.overlay;\ boards/nrf52840dk_nrf52840_sense_edge.overlay" + drivers.gpio.nrf_sense_edge.nrf54l: + platform_allow: + - nrf54l15dk/nrf54l15/cpuapp + extra_args: "EXTRA_DTC_OVERLAY_FILE=boards/nrf54l_sense_edge.overlay" + drivers.gpio.mr_canhubk3_wkpu: platform_allow: mr_canhubk3 extra_args: "DTC_OVERLAY_FILE=boards/mr_canhubk3_wkpu.overlay" diff --git a/tests/drivers/gpio/gpio_hogs/boards/bg29_rb4420a.overlay b/tests/drivers/gpio/gpio_hogs/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..6c90872704de7 --- /dev/null +++ b/tests/drivers/gpio/gpio_hogs/boards/bg29_rb4420a.overlay @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + zephyr,user { + output-high-gpios = <&gpioc 0 GPIO_ACTIVE_LOW>; + output-low-gpios = <&gpioc 2 GPIO_ACTIVE_HIGH>; + input-gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpioc { + hog1 { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + }; + + hog2 { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + }; + hog3 { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/tests/drivers/gpio/gpio_hogs/boards/frdm_k64f.overlay b/tests/drivers/gpio/gpio_hogs/boards/frdm_k64f.overlay index 6b6e4c3c01049..38103a011000b 100644 --- a/tests/drivers/gpio/gpio_hogs/boards/frdm_k64f.overlay +++ b/tests/drivers/gpio/gpio_hogs/boards/frdm_k64f.overlay @@ -2,7 +2,7 @@ * Copyright (c) 2023 Vestas Wind Systems A/S * * SPDX-License-Identifier: Apache-2.0 -*/ + */ #include diff --git a/tests/drivers/gpio/gpio_hogs/boards/mec172xevb_assy6906.overlay b/tests/drivers/gpio/gpio_hogs/boards/mec172xevb_assy6906.overlay index 13fd853709f04..e663e669e3c53 100644 --- a/tests/drivers/gpio/gpio_hogs/boards/mec172xevb_assy6906.overlay +++ b/tests/drivers/gpio/gpio_hogs/boards/mec172xevb_assy6906.overlay @@ -2,7 +2,7 @@ * Copyright (c) 2023 Microchip Technology Inc. * * SPDX-License-Identifier: Apache-2.0 -*/ + */ #include diff --git a/tests/drivers/gpio/gpio_hogs/boards/native_sim.overlay b/tests/drivers/gpio/gpio_hogs/boards/native_sim.overlay index 2cf864efb09bc..f3a0e1a76fd94 100644 --- a/tests/drivers/gpio/gpio_hogs/boards/native_sim.overlay +++ b/tests/drivers/gpio/gpio_hogs/boards/native_sim.overlay @@ -2,7 +2,7 @@ * Copyright (c) 2023 Vestas Wind Systems A/S * * SPDX-License-Identifier: Apache-2.0 -*/ + */ #include diff --git a/tests/drivers/gpio/gpio_hogs/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/gpio/gpio_hogs/boards/nrf52840dk_nrf52840.overlay index 81ec18ad07a73..df9a5d6a8ac77 100644 --- a/tests/drivers/gpio/gpio_hogs/boards/nrf52840dk_nrf52840.overlay +++ b/tests/drivers/gpio/gpio_hogs/boards/nrf52840dk_nrf52840.overlay @@ -2,7 +2,7 @@ * Copyright (c) 2023 Vestas Wind Systems A/S * * SPDX-License-Identifier: Apache-2.0 -*/ + */ #include diff --git a/tests/drivers/gpio/gpio_hogs/boards/nrf52_bsim.overlay b/tests/drivers/gpio/gpio_hogs/boards/nrf52_bsim.overlay index 81ec18ad07a73..df9a5d6a8ac77 100644 --- a/tests/drivers/gpio/gpio_hogs/boards/nrf52_bsim.overlay +++ b/tests/drivers/gpio/gpio_hogs/boards/nrf52_bsim.overlay @@ -2,7 +2,7 @@ * Copyright (c) 2023 Vestas Wind Systems A/S * * SPDX-License-Identifier: Apache-2.0 -*/ + */ #include diff --git a/tests/drivers/gpio/gpio_hogs/boards/nucleo_g474re.overlay b/tests/drivers/gpio/gpio_hogs/boards/nucleo_g474re.overlay index 5335de6b07684..f4b2b59a8f8eb 100644 --- a/tests/drivers/gpio/gpio_hogs/boards/nucleo_g474re.overlay +++ b/tests/drivers/gpio/gpio_hogs/boards/nucleo_g474re.overlay @@ -2,7 +2,7 @@ * Copyright (c) 2023 Vestas Wind Systems A/S * * SPDX-License-Identifier: Apache-2.0 -*/ + */ #include diff --git a/tests/drivers/gpio/gpio_hogs/testcase.yaml b/tests/drivers/gpio/gpio_hogs/testcase.yaml index 84835abb442ee..3de068163b852 100644 --- a/tests/drivers/gpio/gpio_hogs/testcase.yaml +++ b/tests/drivers/gpio/gpio_hogs/testcase.yaml @@ -22,6 +22,7 @@ tests: - s32z2xxdc2@D/s32z270/rtu0 - s32z2xxdc2@D/s32z270/rtu1 - xg29_rb4412a + - bg29_rb4420a integration_platforms: - native_sim - native_sim/native/64 diff --git a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/boards/native_sim.overlay b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/boards/native_sim.overlay index 9352eee9d74f8..06cbcdaa1ace2 100644 --- a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/boards/native_sim.overlay +++ b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/boards/native_sim.overlay @@ -36,9 +36,9 @@ 8 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; wuc-base = <0xf01b20 0xf01b20 0xf01b20 0xf01b1c - 0xf01b1c 0xf01b1c 0xf01b1c 0xf01b24>; - wuc-mask = ; + 0xf01b1c 0xf01b1c 0xf01b1c 0xf01b24>; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; diff --git a/tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim.overlay b/tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim.overlay index 3e0fc23501e29..53967ab564b3e 100644 --- a/tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim.overlay +++ b/tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim.overlay @@ -14,20 +14,20 @@ test_gpio_1: gpio@deadbeef { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0xdeadbeef 0x10>; - #gpio-cells = < 0x2 >; + reg = <0xdeadbeef 0x10>; + #gpio-cells = <0x2>; status = "okay"; - gpio-reserved-ranges = <0 4>, <5 3>, <9 5>, <11 2>, - <15 2>, <18 2>, <21 1>, <23 1>, - <25 4>, <30 2>; + gpio-reserved-ranges = <0 4>, <5 3>, <9 5>, <11 2>, + <15 2>, <18 2>, <21 1>, <23 1>, + <25 4>, <30 2>; }; test_gpio_2: gpio@abcd1234 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0xabcd1234 0x10>; - #gpio-cells = < 0x2 >; + reg = <0xabcd1234 0x10>; + #gpio-cells = <0x2>; status = "okay"; gpio-reserved-ranges = <0 8>, <9 5>, <14 0>, <15 16>; @@ -36,8 +36,8 @@ test_gpio_3: gpio@1234 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0x1234 0x10 >; - #gpio-cells = < 0x2 >; + reg = <0x1234 0x10>; + #gpio-cells = <0x2>; status = "okay"; ngpios = <18>; @@ -47,8 +47,8 @@ test_gpio_4: gpio@5678 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0x5678 0x10 >; - #gpio-cells = < 0x2 >; + reg = <0x5678 0x10>; + #gpio-cells = <0x2>; status = "okay"; ngpios = <16>; @@ -58,8 +58,8 @@ test_gpio_5: gpio@8765 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0x8765 0x10 >; - #gpio-cells = < 0x2 >; + reg = <0x8765 0x10>; + #gpio-cells = <0x2>; status = "okay"; ngpios = <0>; @@ -69,8 +69,8 @@ test_gpio_6: gpio@3210 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0x3210 0x10 >; - #gpio-cells = < 0x2 >; + reg = <0x3210 0x10>; + #gpio-cells = <0x2>; status = "okay"; }; }; diff --git a/tests/drivers/i2c/i2c_api/boards/cy8cproto_063_ble.overlay b/tests/drivers/i2c/i2c_api/boards/cy8cproto_063_ble.overlay index 17df16974692e..1339222cb12ad 100644 --- a/tests/drivers/i2c/i2c_api/boards/cy8cproto_063_ble.overlay +++ b/tests/drivers/i2c/i2c_api/boards/cy8cproto_063_ble.overlay @@ -8,7 +8,7 @@ / { aliases { gy271 = &i2c1; - i2c-0 =&i2c1; + i2c-0 = &i2c1; }; }; diff --git a/tests/drivers/i2c/i2c_api/boards/cyw920829m2evk_02.overlay b/tests/drivers/i2c/i2c_api/boards/cyw920829m2evk_02.overlay index 4d24e9f4641ce..60eec0bbedf63 100644 --- a/tests/drivers/i2c/i2c_api/boards/cyw920829m2evk_02.overlay +++ b/tests/drivers/i2c/i2c_api/boards/cyw920829m2evk_02.overlay @@ -6,7 +6,7 @@ / { aliases { gy271 = &i2c0; - i2c-0 =&i2c0; + i2c-0 = &i2c0; }; }; diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra2l1.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra2l1.overlay index 36f3089de1398..165e61f852b3a 100644 --- a/tests/drivers/i2c/i2c_api/boards/ek_ra2l1.overlay +++ b/tests/drivers/i2c/i2c_api/boards/ek_ra2l1.overlay @@ -16,7 +16,7 @@ group1 { /* SCL0 SDA0 */ psels = , - ; + ; drive-strength = "medium"; }; }; diff --git a/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.overlay b/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.overlay index 2ce8ae69e5e86..883c13ead7b1f 100644 --- a/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.overlay +++ b/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.overlay @@ -7,7 +7,6 @@ aliases { i2c-0 = &i2c9; gy271 = &i2c9; - }; }; diff --git a/tests/drivers/i2c/i2c_api/boards/rza3ul_smarc.conf b/tests/drivers/i2c/i2c_api/boards/rza3ul_smarc.conf new file mode 100644 index 0000000000000..6fa18f3e27b49 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rza3ul_smarc.conf @@ -0,0 +1 @@ +CONFIG_SENSOR_GY271_HMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/rza3ul_smarc.overlay b/tests/drivers/i2c/i2c_api/boards/rza3ul_smarc.overlay new file mode 100644 index 0000000000000..a8ba1076f145e --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rza3ul_smarc.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-0 = &i2c1; + }; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/tests/drivers/i2c/i2c_api/boards/rzn2l_rsk.conf b/tests/drivers/i2c/i2c_api/boards/rzn2l_rsk.conf new file mode 100644 index 0000000000000..6fa18f3e27b49 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rzn2l_rsk.conf @@ -0,0 +1 @@ +CONFIG_SENSOR_GY271_HMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/rzn2l_rsk.overlay b/tests/drivers/i2c/i2c_api/boards/rzn2l_rsk.overlay new file mode 100644 index 0000000000000..55c3ed1d2ee2d --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rzn2l_rsk.overlay @@ -0,0 +1,9 @@ +/ { + aliases { + i2c-0 = &i2c1; + }; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/tests/drivers/i2c/i2c_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.conf b/tests/drivers/i2c/i2c_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.conf new file mode 100644 index 0000000000000..6fa18f3e27b49 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.conf @@ -0,0 +1 @@ +CONFIG_SENSOR_GY271_HMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/i2c/i2c_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay new file mode 100644 index 0000000000000..a8ba1076f145e --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + i2c-0 = &i2c1; + }; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/tests/drivers/i2c/i2c_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf b/tests/drivers/i2c/i2c_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf new file mode 100644 index 0000000000000..6fa18f3e27b49 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf @@ -0,0 +1 @@ +CONFIG_SENSOR_GY271_HMC=y diff --git a/tests/drivers/i2c/i2c_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/i2c/i2c_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay new file mode 100644 index 0000000000000..a16a6e537a194 --- /dev/null +++ b/tests/drivers/i2c/i2c_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay @@ -0,0 +1,9 @@ +/ { + aliases { + i2c-0 = &i2c3; + }; +}; + +&i2c3 { + status = "okay"; +}; diff --git a/tests/drivers/i2c/i2c_ram/README.rst b/tests/drivers/i2c/i2c_ram/README.rst index 0475a500bc188..fc8fbcca0a058 100644 --- a/tests/drivers/i2c/i2c_ram/README.rst +++ b/tests/drivers/i2c/i2c_ram/README.rst @@ -3,7 +3,7 @@ i2c ram test Tests an i2c controller driver against a (s/f/nv)ram module doing a simple write and readback. -Excercises most of the i2c controller APIs in the process. +Exercises most of the i2c controller APIs in the process. Hardware Setup ============== diff --git a/tests/drivers/i2c/i2c_target_api/README.txt b/tests/drivers/i2c/i2c_target_api/README.txt index 4624da97c5ec7..1204cf8c935b1 100644 --- a/tests/drivers/i2c/i2c_target_api/README.txt +++ b/tests/drivers/i2c/i2c_target_api/README.txt @@ -39,3 +39,9 @@ Presence of this required hardware configuration is identified by the `i2c_bus_short` fixture. If the buses are not connected as required, or the controller driver has bugs, the test will fail one or more I2C transactions. + +Transfer data size +****************** + +One can tune the number of data bytes echanged during the tests using +configuration option ``CONFIG_I2C_TEST_DATA_MAX_SIZE``. diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.overlay index 3eede136743aa..378947ec701a7 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn236.overlay @@ -7,7 +7,7 @@ pinmux_flexcomm3_lpi2c: pinmux_flexcomm3_lpi2c { group0 { pinmux = , - ; + ; slew-rate = "fast"; drive-strength = "low"; input-enable; diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay index fda9cf69c4a66..8f12969f8147a 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -7,7 +7,7 @@ pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c { group0 { pinmux = , - ; + ; slew-rate = "fast"; drive-strength = "low"; input-enable; diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay index c17df12c20041..b0a8bb2ca11fa 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay @@ -7,7 +7,7 @@ pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c { group0 { pinmux = , - ; + ; slew-rate = "fast"; drive-strength = "low"; input-enable; diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay index fda9cf69c4a66..8f12969f8147a 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay @@ -7,7 +7,7 @@ pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c { group0 { pinmux = , - ; + ; slew-rate = "fast"; drive-strength = "low"; input-enable; diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay index c17df12c20041..b0a8bb2ca11fa 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay @@ -7,7 +7,7 @@ pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c { group0 { pinmux = , - ; + ; slew-rate = "fast"; drive-strength = "low"; input-enable; diff --git a/tests/drivers/i2c/i2c_target_api/boards/mec1501modular_assy6885.overlay b/tests/drivers/i2c/i2c_target_api/boards/mec1501modular_assy6885.overlay index 17ae7f879a65f..21b10b3823641 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/mec1501modular_assy6885.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/mec1501modular_assy6885.overlay @@ -13,7 +13,6 @@ }; }; - &i2c_smb_1 { eeprom1: eeprom@56 { compatible = "zephyr,i2c-target-eeprom"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1040_evk.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1040_evk.overlay index a1c329a6926e6..3ffce61221aa8 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1040_evk.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1040_evk.overlay @@ -4,14 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* * Note: this sample requires the board to be modified! Populate resistors * R362 and R356. * To test this sample, connect J17.9<->J17.3 (SDA), J17.10<->J17.6 (SCL) */ - &lpi2c1 { status = "okay"; eeprom0: eeprom@54 { diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay index d47c67068ba92..6090f3f5bd616 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay @@ -8,7 +8,7 @@ pinmux_lpi2c3: pinmux_lpi2c3 { group0 { pinmux = <&iomuxc_gpio_ad_b1_06_lpi2c3_sda>, - <&iomuxc_gpio_ad_b1_07_lpi2c3_scl>; + <&iomuxc_gpio_ad_b1_07_lpi2c3_scl>; drive-strength = "r0-6"; drive-open-drain; slew-rate = "slow"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay index d47c67068ba92..6090f3f5bd616 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -8,7 +8,7 @@ pinmux_lpi2c3: pinmux_lpi2c3 { group0 { pinmux = <&iomuxc_gpio_ad_b1_06_lpi2c3_sda>, - <&iomuxc_gpio_ad_b1_07_lpi2c3_scl>; + <&iomuxc_gpio_ad_b1_07_lpi2c3_scl>; drive-strength = "r0-6"; drive-open-drain; slew-rate = "slow"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_f091rc.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_f091rc.overlay index 9e6db75d1dfad..997671c5d1904 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/nucleo_f091rc.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_f091rc.overlay @@ -18,7 +18,6 @@ }; }; - &i2c2 { /* i2c2 is disabled by default because of pin conflict with can1 */ status = "okay"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_g071rb.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_g071rb.overlay index fb14393c879fd..821c2be889f11 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/nucleo_g071rb.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_g071rb.overlay @@ -1,7 +1,7 @@ /* * Copyright (c) 2020 Thomas Stranger * SPDX-License-Identifier: Apache-2.0 -*/ + */ /* I2C bus pins are exposed on the ST morpho header. * diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_h503rb.conf b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h503rb.conf new file mode 100644 index 0000000000000..ef46de38d35cb --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h503rb.conf @@ -0,0 +1,3 @@ +CONFIG_I2C_STM32_INTERRUPT=y +CONFIG_I2C_TEST_DATA_MAX_SIZE=300 +CONFIG_I2C_VIRTUAL=n diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_h503rb.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h503rb.overlay new file mode 100644 index 0000000000000..37b87dce643bb --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_h503rb.overlay @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/* I2C bus pins are exposed on the ST morpho header. + * + * Bus SDA SCL + * Pin Hdr Pin Hdr + * i2c1 PB7 CN5:9 PB6 CN5:10/CN10:3 + * i2c2 PB4 CN9:6/CN10:27 PB5 CN9:5/CN10:29 + * + * Short Pin PB7 to PB4, and PB6 to PB5, for the test to pass. + */ + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; + + eeprom1: eeprom@10 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x10>; + address-width = <16>; + size = <1024>; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pb5 &i2c2_sda_pb4>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; + + eeprom0: eeprom@18 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x18>; + address-width = <16>; + size = <1024>; + }; +}; diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_l073rz.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_l073rz.overlay index 9c067ae8b5c7c..a0e79dbb9fcdb 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/nucleo_l073rz.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_l073rz.overlay @@ -18,7 +18,6 @@ }; }; - &i2c2 { eeprom1: eeprom@56 { compatible = "zephyr,i2c-target-eeprom"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_l152re.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_l152re.overlay index aeabefb7e27ea..05bbe98fa745d 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/nucleo_l152re.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_l152re.overlay @@ -18,7 +18,6 @@ }; }; - &i2c2 { pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>; pinctrl-names = "default"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/stm32f072b_disco.overlay b/tests/drivers/i2c/i2c_target_api/boards/stm32f072b_disco.overlay index bf249a3bb7637..e579c870d9d0b 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/stm32f072b_disco.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/stm32f072b_disco.overlay @@ -8,7 +8,6 @@ }; }; - &i2c2 { eeprom1: eeprom@56 { compatible = "zephyr,i2c-target-eeprom"; diff --git a/tests/drivers/i2c/i2c_target_api/boards/stm32f3_disco.overlay b/tests/drivers/i2c/i2c_target_api/boards/stm32f3_disco.overlay index 5c8f04c1022e1..4877d89ff1b11 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/stm32f3_disco.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/stm32f3_disco.overlay @@ -10,8 +10,6 @@ * Short Pin PB7 to PA10, and PB6 to PA9, for the test to pass. */ - - &i2c1 { eeprom0: eeprom@54 { compatible = "zephyr,i2c-target-eeprom"; @@ -26,5 +24,4 @@ reg = <0x56>; size = <256>; }; - }; diff --git a/tests/drivers/i2c/i2c_target_api/boards/stm32u083c_dk.overlay b/tests/drivers/i2c/i2c_target_api/boards/stm32u083c_dk.overlay index cf434be71de88..8e4f0f2939532 100644 --- a/tests/drivers/i2c/i2c_target_api/boards/stm32u083c_dk.overlay +++ b/tests/drivers/i2c/i2c_target_api/boards/stm32u083c_dk.overlay @@ -19,7 +19,6 @@ reg = <0x54>; size = <256>; }; - }; &i2c2 { diff --git a/tests/drivers/i2c/i2c_target_api/common/Kconfig b/tests/drivers/i2c/i2c_target_api/common/Kconfig index b516534a8e145..b42bbdba07cfc 100644 --- a/tests/drivers/i2c/i2c_target_api/common/Kconfig +++ b/tests/drivers/i2c/i2c_target_api/common/Kconfig @@ -17,3 +17,7 @@ config I2C_VIRTUAL_NAME config APP_DUAL_ROLE_I2C bool "Test with combined controller/target behavior" + +config I2C_TEST_DATA_MAX_SIZE + int "Max tested data size for the I2C transfers" + default 20 diff --git a/tests/drivers/i2c/i2c_target_api/src/main.c b/tests/drivers/i2c/i2c_target_api/src/main.c index b249daae90bd4..143248d187e4f 100644 --- a/tests/drivers/i2c/i2c_target_api/src/main.c +++ b/tests/drivers/i2c/i2c_target_api/src/main.c @@ -23,9 +23,11 @@ #define NODE_EP0 DT_NODELABEL(eeprom0) #define NODE_EP1 DT_NODELABEL(eeprom1) -#define TEST_DATA_SIZE 20 -static const uint8_t eeprom_0_data[TEST_DATA_SIZE] = "0123456789abcdefghij"; -static const uint8_t eeprom_1_data[TEST_DATA_SIZE] = "jihgfedcba9876543210"; +#define TEST_DATA_SIZE MIN(CONFIG_I2C_TEST_DATA_MAX_SIZE, \ + MIN(DT_PROP(NODE_EP0, size), DT_PROP(NODE_EP1, size))) + +static uint8_t eeprom_0_data[TEST_DATA_SIZE]; +static uint8_t eeprom_1_data[TEST_DATA_SIZE]; static uint8_t i2c_buffer[TEST_DATA_SIZE]; /* @@ -35,6 +37,23 @@ static uint8_t i2c_buffer[TEST_DATA_SIZE]; uint8_t buffer_print_eeprom[TEST_DATA_SIZE * 5 + 1]; uint8_t buffer_print_i2c[TEST_DATA_SIZE * 5 + 1]; +static void init_eeprom_test_data(void) +{ + size_t n; + + /* + * Initialize EEPROM data with printable ASCII value (range [32 126]). + * Make sure content differs between eeprom_0_data[] and eeprom_1_data[]. + */ + for (n = 0; n < sizeof(eeprom_0_data); n++) { + eeprom_0_data[n] = 32 + (n % (126 - 32)); + } + + for (n = 0; n < sizeof(eeprom_1_data); n++) { + eeprom_1_data[n] = 32 + (((n + 10) * 3) % (126 - 32)); + } +} + static void to_display_format(const uint8_t *src, size_t size, char *dst) { size_t i; @@ -123,7 +142,7 @@ static int run_program_read(const struct device *i2c, uint8_t addr, i2c->name, addr, offset); for (i = 0 ; i < TEST_DATA_SIZE-offset ; ++i) { - i2c_buffer[i] = i; + i2c_buffer[i] = i & 0xFF; } switch (addr_width) { @@ -155,11 +174,11 @@ static int run_program_read(const struct device *i2c, uint8_t addr, zassert_equal(ret, 0, "Failed to read EEPROM"); for (i = 0 ; i < TEST_DATA_SIZE-offset ; ++i) { - if (i2c_buffer[i] != i) { + if (i2c_buffer[i] != (i & 0xFF)) { to_display_format(i2c_buffer, TEST_DATA_SIZE-offset, buffer_print_i2c); - TC_PRINT("Error: Unexpected buffer content: %s\n", - buffer_print_i2c); + TC_PRINT("Error: Unexpected %u (%02x) buffer content: %s\n", + i, i2c_buffer[i], buffer_print_i2c); return -EIO; } } @@ -235,6 +254,8 @@ ZTEST(i2c_eeprom_target, test_eeprom_target) uint8_t addr_1_width = DT_PROP_OR(NODE_EP1, address_width, 8); int ret, offset; + init_eeprom_test_data(); + zassert_not_null(i2c_0, "EEPROM 0 - I2C bus not found"); zassert_not_null(eeprom_0, "EEPROM 0 device not found"); diff --git a/tests/drivers/i2c/i2c_target_api/testcase.yaml b/tests/drivers/i2c/i2c_target_api/testcase.yaml index 0a84b703f8b92..13ef2bb16c4c2 100644 --- a/tests/drivers/i2c/i2c_target_api/testcase.yaml +++ b/tests/drivers/i2c/i2c_target_api/testcase.yaml @@ -24,6 +24,7 @@ tests: - nucleo_f207zg - nucleo_f401re - nucleo_f429zi + - nucleo_h503rb - nucleo_wl55jc - nucleo_l073rz - nucleo_l152re diff --git a/tests/drivers/i2c/i2c_tca954x/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/i2c/i2c_tca954x/boards/nrf52840dk_nrf52840.overlay index 5f2605abc9cff..8ae3a1827fab2 100644 --- a/tests/drivers/i2c/i2c_tca954x/boards/nrf52840dk_nrf52840.overlay +++ b/tests/drivers/i2c/i2c_tca954x/boards/nrf52840dk_nrf52840.overlay @@ -29,7 +29,7 @@ }; }; -/{ +/ { aliases { i2c-channel-0 = &ch0; i2c-channel-1 = &ch1; diff --git a/tests/drivers/i2s/i2s_additional/Kconfig b/tests/drivers/i2s/i2s_additional/Kconfig index 3c80dba48532e..ee903546708b1 100644 --- a/tests/drivers/i2s/i2s_additional/Kconfig +++ b/tests/drivers/i2s/i2s_additional/Kconfig @@ -75,6 +75,14 @@ config I2S_TEST_EIGHT_CHANNELS_UNSUPPORTED When set to 'y', test will check that i2s_configure() returns -EINVAL. When set to 'n', test will do the transmission. +config I2S_TEST_EIGHT_CHANNELS_32B_48K_UNSUPPORTED + bool "Skip test with 8 channels, 32 bit word size and 48k sample rate" + depends on !I2S_TEST_EIGHT_CHANNELS_UNSUPPORTED + help + Skip test that is challenging due to high data throughput. + When set to 'y', test will be skipped. + When set to 'n', test will do the transmission. + config I2S_TEST_DATA_FORMAT_I2S_UNSUPPORTED bool "I2S_FMT_DATA_FORMAT_I2S is not supported by the driver" help diff --git a/tests/drivers/i2s/i2s_additional/boards/nrf54h20dk_nrf54h20_cpuapp_aclk.overlay b/tests/drivers/i2s/i2s_additional/boards/nrf54h20dk_nrf54h20_cpuapp_aclk.overlay new file mode 100644 index 0000000000000..ad9e06d0793e2 --- /dev/null +++ b/tests/drivers/i2s/i2s_additional/boards/nrf54h20dk_nrf54h20_cpuapp_aclk.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&audiopll { + status = "okay"; + frequency = ; +}; + +&tdm130 { + mck-frequency = <12288000>; + mck-clock-source = "ACLK"; + sck-clock-source = "ACLK"; +}; diff --git a/tests/drivers/i2s/i2s_additional/src/main.c b/tests/drivers/i2s/i2s_additional/src/main.c index e8852850cee58..0dcfc052bdf38 100644 --- a/tests/drivers/i2s/i2s_additional/src/main.c +++ b/tests/drivers/i2s/i2s_additional/src/main.c @@ -19,7 +19,7 @@ LOG_MODULE_REGISTER(i2s_add, LOG_LEVEL_INF); #define NUMBER_OF_CHANNELS 2 #define FRAME_CLK_FREQ 44100 -#define NUM_BLOCKS 20 +#define NUM_BLOCKS 4 #define TIMEOUT 1000 #define SAMPLES_COUNT 64 @@ -519,9 +519,9 @@ ZTEST(i2s_additional, test_02b_four_channels) #endif /* CONFIG_I2S_TEST_FOUR_CHANNELS_UNSUPPORTED */ } -/** @brief Test I2S transfer with eight channels. +/** @brief Test I2S transfer with eight channels, 16 bit and 44.1 kHz. */ -ZTEST(i2s_additional, test_02c_eight_channels) +ZTEST(i2s_additional, test_02c_eight_channels_default) { struct i2s_config i2s_cfg = default_i2s_cfg; @@ -549,6 +549,43 @@ ZTEST(i2s_additional, test_02c_eight_channels) #endif /* CONFIG_I2S_TEST_EIGHT_CHANNELS_UNSUPPORTED */ } +/** @brief Test I2S transfer with eight channels, 32 bit and 48 kHz. + */ +ZTEST(i2s_additional, test_02d_eight_channels_high_throughput) +{ + struct i2s_config i2s_cfg = default_i2s_cfg; + + i2s_cfg.channels = 8; + i2s_cfg.word_size = 32; + i2s_cfg.frame_clk_freq = 48000; + +#if defined(CONFIG_I2S_TEST_EIGHT_CHANNELS_UNSUPPORTED) + int ret; + + ret = i2s_configure(dev_i2s, I2S_DIR_TX, &i2s_cfg); + zassert_equal(ret, -EINVAL, "Unexpected result %d", ret); +#else /* CONFIG_I2S_TEST_EIGHT_CHANNELS_UNSUPPORTED */ + +#if defined(CONFIG_I2S_TEST_EIGHT_CHANNELS_32B_48K_UNSUPPORTED) + /* Skip this test if driver supports 8ch but fails in this configuration. */ + ztest_test_skip(); +#endif + + /* Select format that supports eight channels. */ +#if !defined(CONFIG_I2S_TEST_DATA_FORMAT_PCM_LONG_UNSUPPORTED) + i2s_cfg.format = I2S_FMT_DATA_FORMAT_PCM_LONG; + TC_PRINT("Selected format is I2S_FMT_DATA_FORMAT_PCM_LONG\n"); +#elif !defined(CONFIG_I2S_TEST_DATA_FORMAT_PCM_SHORT_UNSUPPORTED) + i2s_cfg.format = I2S_FMT_DATA_FORMAT_PCM_SHORT; + TC_PRINT("Selected format is I2S_FMT_DATA_FORMAT_PCM_SHORT\n"); +#else +#error "Don't know what format supports eight channels." +#endif + + i2s_dir_both_transfer_long(&i2s_cfg); +#endif /* CONFIG_I2S_TEST_EIGHT_CHANNELS_UNSUPPORTED */ +} + /** @brief Test I2S transfer with format I2S_FMT_DATA_FORMAT_I2S */ ZTEST(i2s_additional, test_03a_format_i2s) diff --git a/tests/drivers/i2s/i2s_additional/testcase.yaml b/tests/drivers/i2s/i2s_additional/testcase.yaml index 9dcb82d61f3fe..77a18c3ab9d3d 100644 --- a/tests/drivers/i2s/i2s_additional/testcase.yaml +++ b/tests/drivers/i2s/i2s_additional/testcase.yaml @@ -26,6 +26,17 @@ tests: drivers.i2s.additional.gpio_loopback.54h: harness_config: fixture: i2s_loopback + extra_configs: + - CONFIG_I2S_TEST_EIGHT_CHANNELS_32B_48K_UNSUPPORTED=y + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp + integration_platforms: + - nrf54h20dk/nrf54h20/cpuapp + + drivers.i2s.additional.gpio_loopback.54h.aclk: + harness_config: + fixture: i2s_loopback + extra_args: EXTRA_DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_aclk.overlay" platform_allow: - nrf54h20dk/nrf54h20/cpuapp integration_platforms: diff --git a/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay index 1d5290f0bd899..c2059e761fa85 100644 --- a/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay +++ b/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -13,8 +13,8 @@ /* Enable SAI4, and set clocks to match SAI1 */ &sai4 { status = "okay"; - clocks = < &ccm 0x2003 0x2184 0x6 >; - podf = < 0x4 >; + clocks = <&ccm 0x2003 0x2184 0x6>; + podf = <0x4>; pinctrl-0 = <&pinmux_sai4>; pinctrl-names = "default"; }; diff --git a/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay index 6d89796095ad5..e7cb0725f3e3b 100644 --- a/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay +++ b/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay @@ -11,11 +11,11 @@ &pinmux_sai1 { group0 { pinmux = , - , - , - , - , - ; + , + , + , + , + ; drive-strength = "high"; slew-rate = "fast"; input-enable; diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay index fe402d391f868..0cacc7446cbd9 100644 --- a/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay +++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay @@ -8,11 +8,11 @@ pinmux_sai1: pinmux_sai1 { group0 { pinmux = <&iomuxc_gpio_ad_b1_12_sai1_rx_data0>, - <&iomuxc_gpio_ad_b1_11_sai1_rx_bclk>, - <&iomuxc_gpio_ad_b1_10_sai1_rx_sync>, - <&iomuxc_gpio_ad_b1_15_sai1_tx_sync>, - <&iomuxc_gpio_ad_b1_14_sai1_tx_bclk>, - <&iomuxc_gpio_ad_b1_13_sai1_tx_data0>; + <&iomuxc_gpio_ad_b1_11_sai1_rx_bclk>, + <&iomuxc_gpio_ad_b1_10_sai1_rx_sync>, + <&iomuxc_gpio_ad_b1_15_sai1_tx_sync>, + <&iomuxc_gpio_ad_b1_14_sai1_tx_bclk>, + <&iomuxc_gpio_ad_b1_13_sai1_tx_data0>; drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "100-mhz"; diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay index 3414f18e63c9e..1ab967e126635 100644 --- a/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay +++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay @@ -8,7 +8,6 @@ i2s-node0 = &i2s0; i2s-node1 = &i2s1; }; - }; &i2s0 { diff --git a/tests/drivers/input/tsc_keys/boards/stm32u083c_dk.overlay b/tests/drivers/input/tsc_keys/boards/stm32u083c_dk.overlay index 1ef9dc0534106..d2579f2f91c49 100644 --- a/tests/drivers/input/tsc_keys/boards/stm32u083c_dk.overlay +++ b/tests/drivers/input/tsc_keys/boards/stm32u083c_dk.overlay @@ -16,7 +16,7 @@ status = "okay"; pinctrl-0 = <&tsc_g1_io1_pb12 &tsc_g1_io2_pb13 &tsc_g6_io1_pd10 - &tsc_g6_io2_pd11 &tsc_sync_pd2>; + &tsc_g6_io2_pd11 &tsc_sync_pd2>; pinctrl-names = "default"; st,pulse-generator-prescaler = <128>; diff --git a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/exti_default_resources.overlay b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/exti_default_resources.overlay index ce61a56725475..a59fb131eba11 100644 --- a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/exti_default_resources.overlay +++ b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/exti_default_resources.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - /** * NOTE: For this test, a _configurable_ EXTI line that doesn't conflict * with other users should be specified, along with the associated IRQn. diff --git a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/nucleo_c071rb_stm32c071xx.overlay b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/nucleo_c071rb_stm32c071xx.overlay index 8ae2f9ba80c0a..f4dc77561e000 100644 --- a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/nucleo_c071rb_stm32c071xx.overlay +++ b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/nucleo_c071rb_stm32c071xx.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { resources { exti-line-nr = <34>; diff --git a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32h7s78_dk_stm32h7s7xx.overlay b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32h7s78_dk_stm32h7s7xx.overlay index 54e42b2225ecb..fd911f861896a 100644 --- a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32h7s78_dk_stm32h7s7xx.overlay +++ b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32h7s78_dk_stm32h7s7xx.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { resources { exti-line-nr = <16>; diff --git a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32n6570_dk_stm32n657xx_sb.overlay b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32n6570_dk_stm32n657xx_sb.overlay index 875685ad48ebc..749e88b5f52e2 100644 --- a/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32n6570_dk_stm32n657xx_sb.overlay +++ b/tests/drivers/interrupt_controller/intc_exti_stm32/boards/stm32n6570_dk_stm32n657xx_sb.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { resources { exti-line-nr = <66>; diff --git a/tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay b/tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay index a25223d03d147..322476fce7415 100644 --- a/tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay +++ b/tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay @@ -4,26 +4,24 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { soc { plic: interrupt-controller@c000000 { riscv,max-priority = <7>; - riscv,ndev = < 1024 >; + riscv,ndev = <1024>; reg = <0x0c000000 0x04000000>; - interrupts-extended = < - &hlic0 0x0b - &hlic1 0x0b &hlic1 0x09 - &hlic2 0x0b &hlic2 0x09 - &hlic3 0x0b &hlic3 0x09 - &hlic4 0x0b &hlic4 0x09 - &hlic5 0x0b &hlic5 0x09 - &hlic6 0x0b &hlic6 0x09 - &hlic7 0x0b &hlic7 0x09 - >; + interrupts-extended = <&hlic0 0x0b + &hlic1 0x0b &hlic1 0x09 + &hlic2 0x0b &hlic2 0x09 + &hlic3 0x0b &hlic3 0x09 + &hlic4 0x0b &hlic4 0x09 + &hlic5 0x0b &hlic5 0x09 + &hlic6 0x0b &hlic6 0x09 + &hlic7 0x0b &hlic7 0x09>; interrupt-controller; compatible = "sifive,plic-1.0.0"; - #address-cells = < 0x00 >; - #interrupt-cells = < 0x02 >; + #address-cells = <0x00>; + #interrupt-cells = <0x02>; }; }; }; diff --git a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index 0369a05f253c9..56452fc4936bf 100644 --- a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mailbox0@5008b000 { + mbox: mailbox0@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay index 8c4ac95144fbe..4726dfd3b507e 100644 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay index 8c4ac95144fbe..4726dfd3b507e 100644 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@40c48000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c48000 { + mbox: mbox@40c48000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c48000 0x4000>; interrupts = <118 0>; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay index 81461aa9857de..db73f972af89f 100644 --- a/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay @@ -8,8 +8,8 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&mbox1_a 3>, <&mbox1_a 2>, <&mbox1_a 1>, <&mbox1_a 0>, - <&mbox1_a 2>, <&mbox1_a 3>, <&mbox1_a 0>, <&mbox1_a 1>; + <&mbox1_a 2>, <&mbox1_a 3>, <&mbox1_a 0>, <&mbox1_a 1>; mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", - "rx3"; + "rx3"; }; }; diff --git a/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu0.overlay index aaaf945f03228..cc85182dce40b 100644 --- a/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -8,9 +8,9 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&mru0 0>, <&mru0 0>, <&mru0 1>, <&mru0 1>, - <&mru0 2>, <&mru0 2>, <&mru0 3>, <&mru0 3>; + <&mru0 2>, <&mru0 2>, <&mru0 3>, <&mru0 3>; mbox-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; + "tx2", "rx2", "tx3", "rx3"; }; }; diff --git a/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu1.overlay index b01767bd1682b..fac85880b8847 100644 --- a/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/mbox/mbox_data/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -8,9 +8,9 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&mru4 0>, <&mru4 0>, <&mru4 1>, <&mru4 1>, - <&mru4 2>, <&mru4 2>, <&mru4 3>, <&mru4 3>; + <&mru4 2>, <&mru4 2>, <&mru4 3>, <&mru4 3>; mbox-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; + "tx2", "rx2", "tx3", "rx3"; }; }; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay index c38e2728d17b1..eb20ff9a1dd61 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay @@ -17,7 +17,7 @@ /delete-node/ mailbox@8b000; /* Attach MBOX driver to Mailbox Unit */ - mbox:mbox@5008b000 { + mbox: mbox@5008b000 { compatible = "nxp,mbox-mailbox"; reg = <0x5008b000 0xEC>; interrupts = <31 0>; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay index 49185a9b365fd..fc6ade72a8c0b 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay index 49185a9b365fd..fc6ade72a8c0b 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index 49185a9b365fd..fc6ade72a8c0b 100644 --- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -20,7 +20,7 @@ /delete-node/ gpt@400f0000; /* Replace GPT2 with another GPT kernel timer */ - gpt2_hw_timer:gpt@400f0000 { + gpt2_hw_timer: gpt@400f0000 { compatible = "nxp,gpt-hw-timer"; reg = <0x400f0000 0x4000>; interrupts = <120 0>; @@ -31,7 +31,7 @@ /delete-node/ mailbox@40c4c000; /* Attach MBOX driver to MU Unit */ - mbox:mbox@40c4c000 { + mbox: mbox@40c4c000 { compatible = "nxp,mbox-imx-mu"; reg = <0x40c4c000 0x4000>; interrupts = <118 0>; diff --git a/tests/drivers/mbox/mbox_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index 00e65fae41a4f..9ba0dc8a34d78 100644 --- a/tests/drivers/mbox/mbox_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -8,9 +8,9 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&cpuapp_vevif_tx 21>, <&cpuapp_vevif_tx 32>, - <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; + <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; mbox-names = "remote_valid", "remote_incorrect", - "local_valid", "local_incorrect"; + "local_valid", "local_incorrect"; }; }; diff --git a/tests/drivers/mbox/mbox_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index 00e65fae41a4f..9ba0dc8a34d78 100644 --- a/tests/drivers/mbox/mbox_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -8,9 +8,9 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&cpuapp_vevif_tx 21>, <&cpuapp_vevif_tx 32>, - <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; + <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; mbox-names = "remote_valid", "remote_incorrect", - "local_valid", "local_incorrect"; + "local_valid", "local_incorrect"; }; }; diff --git a/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 84006d1d4352b..41a1210691d91 100644 --- a/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -7,9 +7,9 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&cpuppr_vevif 15>, <&cpuppr_vevif 32>, - <&cpuapp_bellboard 18>, <&cpuapp_bellboard 32>; + <&cpuapp_bellboard 18>, <&cpuapp_bellboard 32>; mbox-names = "remote_valid", "remote_incorrect", - "local_valid", "local_incorrect"; + "local_valid", "local_incorrect"; }; }; diff --git a/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuppr.overlay index b39bd5e496211..856bab25f7cc4 100644 --- a/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuppr.overlay +++ b/tests/drivers/mbox/mbox_error_cases/boards/nrf54h20dk_nrf54h20_cpuppr.overlay @@ -7,9 +7,9 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&cpuapp_bellboard 18>, <&cpuapp_bellboard 32>, - <&cpuppr_vevif 15>, <&cpuppr_vevif 32>; + <&cpuppr_vevif 15>, <&cpuppr_vevif 32>; mbox-names = "remote_valid", "remote_incorrect", - "local_valid", "local_incorrect"; + "local_valid", "local_incorrect"; }; }; diff --git a/tests/drivers/mbox/mbox_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index f7fd310c974c9..6d1f935b2ce00 100644 --- a/tests/drivers/mbox/mbox_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/mbox/mbox_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -7,10 +7,9 @@ mbox-consumer { compatible = "vnd,mbox-consumer"; mboxes = <&cpuapp_vevif_tx 21>, <&cpuapp_vevif_tx 32>, - <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; + <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; mbox-names = "remote_valid", "remote_incorrect", - "local_valid", "local_incorrect"; - + "local_valid", "local_incorrect"; }; }; diff --git a/tests/drivers/mbox/mbox_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay index e9203a635a6a0..a53b69a8eb473 100644 --- a/tests/drivers/mbox/mbox_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay +++ b/tests/drivers/mbox/mbox_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay @@ -8,11 +8,10 @@ compatible = "vnd,mbox-consumer"; mboxes = <&cpuapp_vevif_tx 21>, <&cpuapp_vevif_tx 32>, - <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; + <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>; mbox-names = "remote_valid", "remote_incorrect", - "local_valid", "local_incorrect"; - + "local_valid", "local_incorrect"; }; }; diff --git a/tests/drivers/mbox/mbox_error_cases/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/mbox/mbox_error_cases/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay index d812e3a396717..f1e60dfaa6a6c 100644 --- a/tests/drivers/mbox/mbox_error_cases/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay +++ b/tests/drivers/mbox/mbox_error_cases/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -18,7 +18,7 @@ compatible = "zephyr,memory-region"; reg = <0x62F00000 0x600000>; zephyr,memory-region = "openamp_memory"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-attr = ; }; }; @@ -47,7 +47,6 @@ mboxes = <&mbox1 1>, <&mbox1 4>, <&mbox3 0>, <&mbox3 3>; mbox-names = "remote_valid", "remote_incorrect", "local_valid", "local_incorrect"; }; - }; &mbox1 { diff --git a/tests/drivers/memc/ram/boards/apard32690_max32690_m4.conf b/tests/drivers/memc/ram/boards/apard32690_max32690_m4.conf new file mode 100644 index 0000000000000..43398485d6218 --- /dev/null +++ b/tests/drivers/memc/ram/boards/apard32690_max32690_m4.conf @@ -0,0 +1,4 @@ +CONFIG_ZTEST=y +CONFIG_MEMC=y +CONFIG_CLOCK_CONTROL_INIT_PRIORITY=15 +CONFIG_MEMC_INIT_PRIORITY=20 diff --git a/tests/drivers/memc/ram/boards/stm32h735g_disco.overlay b/tests/drivers/memc/ram/boards/stm32h735g_disco.overlay index 41753d2e14e72..0174e250100bb 100644 --- a/tests/drivers/memc/ram/boards/stm32h735g_disco.overlay +++ b/tests/drivers/memc/ram/boards/stm32h735g_disco.overlay @@ -1,7 +1,7 @@ /delete-node/ &sram2; /* D2 domain, AHB SRAM */ -&sram1{ +&sram1 { reg = <0x30000000 DT_SIZE_K(32)>; zephyr,memory-region = "SRAM1-2"; }; diff --git a/tests/drivers/mspi/api/boards/apollo3p_evb.overlay b/tests/drivers/mspi/api/boards/apollo3p_evb.overlay index 39bba4c45cb64..aea16a6c46c8a 100644 --- a/tests/drivers/mspi/api/boards/apollo3p_evb.overlay +++ b/tests/drivers/mspi/api/boards/apollo3p_evb.overlay @@ -29,12 +29,11 @@ reg = <0x0>; mspi-max-frequency = <48000000>; }; - }; &pinctrl { - mspi1_sleep: mspi1_sleep{ + mspi1_sleep: mspi1_sleep { group1 { pinmux = , , @@ -50,7 +49,7 @@ }; }; - mspi1_emul: mspi1_emul{ + mspi1_emul: mspi1_emul { group1 { pinmux = , @@ -83,7 +82,5 @@ group4 { pinmux = ; }; - }; - }; diff --git a/tests/drivers/mspi/api/boards/native_sim.overlay b/tests/drivers/mspi/api/boards/native_sim.overlay index 3c6780e40042b..906b26866ce98 100644 --- a/tests/drivers/mspi/api/boards/native_sim.overlay +++ b/tests/drivers/mspi/api/boards/native_sim.overlay @@ -17,5 +17,4 @@ reg = <0x0>; mspi-max-frequency = <48000000>; }; - }; diff --git a/tests/drivers/mspi/flash/boards/apollo3p_evb.overlay b/tests/drivers/mspi/flash/boards/apollo3p_evb.overlay index cef3bf322ed62..05dc7f6848d6e 100644 --- a/tests/drivers/mspi/flash/boards/apollo3p_evb.overlay +++ b/tests/drivers/mspi/flash/boards/apollo3p_evb.overlay @@ -19,7 +19,7 @@ pinctrl-0 = <&mspi1_default>; pinctrl-1 = <&mspi1_sleep>; pinctrl-2 = <&mspi1_flash>; - pinctrl-names = "default","sleep","flash"; + pinctrl-names = "default", "sleep", "flash"; status = "okay"; ce-gpios = <&gpio32_63 18 GPIO_ACTIVE_LOW>; @@ -47,12 +47,11 @@ ambiq,timing-config-mask = <3>; ambiq,timing-config = <0 8 0 0 0 0 0 0>; }; - }; &pinctrl { - mspi1_sleep: mspi1_sleep{ + mspi1_sleep: mspi1_sleep { group1 { pinmux = , , @@ -68,7 +67,7 @@ }; }; - mspi1_flash: mspi1_flash{ + mspi1_flash: mspi1_flash { group1 { pinmux = , @@ -101,7 +100,5 @@ group4 { pinmux = ; }; - }; - }; diff --git a/tests/drivers/mspi/flash/boards/native_sim.overlay b/tests/drivers/mspi/flash/boards/native_sim.overlay index 9cc80aede14b2..936fb77bb336b 100644 --- a/tests/drivers/mspi/flash/boards/native_sim.overlay +++ b/tests/drivers/mspi/flash/boards/native_sim.overlay @@ -53,5 +53,4 @@ xip-config = <1 0 0 0>; ce-break-config = <1024 4>; }; - }; diff --git a/tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay b/tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay index 177dc9018c277..99ac847c1fb4e 100644 --- a/tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay +++ b/tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay @@ -16,8 +16,9 @@ &pinctrl { test_device_default: test_device_default { /* Note: the groups are just meant for testing if properties and - pins are parsed correctly, but do not necessarily represent a - feasible combination */ + * pins are parsed correctly, but do not necessarily represent a + * feasible combination + */ group1 { pinmux = , , diff --git a/tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay b/tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay index 501d44c38cf28..78921a70d8cd1 100644 --- a/tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay +++ b/tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay @@ -14,8 +14,9 @@ &pinctrl { test_device_default: test_device_default { /* Note: the groups are just meant for testing if properties and - pins are parsed correctly, but do not necessarily represent a - feasible combination */ + * pins are parsed correctly, but do not necessarily represent a + * feasible combination + */ group1 { pinmux = , ; diff --git a/tests/drivers/pinctrl/nrf/app.overlay b/tests/drivers/pinctrl/nrf/app.overlay index 627ea35ca75c2..b3b8426bdba16 100644 --- a/tests/drivers/pinctrl/nrf/app.overlay +++ b/tests/drivers/pinctrl/nrf/app.overlay @@ -15,8 +15,9 @@ &pinctrl { test_device_default: test_device_default { /* Note: the groups are just meant for testing if properties and - pins are parsed correctly, but do not necessarily represent a - feasible combination */ + * pins are parsed correctly, but do not necessarily represent a + * feasible combination + */ group1 { psels = , , diff --git a/tests/drivers/pwm/pwm_api/boards/cyw920829m2evk_02.overlay b/tests/drivers/pwm/pwm_api/boards/cyw920829m2evk_02.overlay new file mode 100644 index 0000000000000..d8ced221f1bd9 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/cyw920829m2evk_02.overlay @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + aliases { + pwm-0 = &pwm0_0; + }; +}; + +&tcpwm0_0 { + status = "okay"; + divider-type = ; + divider-sel = <1>; + divider-val = <9599>; + + pwm0_0: pwm0_0 { + status = "okay"; + pinctrl-0 = <&p3_4_pwm0_0>; + pinctrl-names = "default"; + }; +}; + +&pinctrl { + p3_4_pwm0_0: p3_4_pwm0_0 { + drive-push-pull; + }; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/frdm_ke1xz_flexio_pwm.overlay b/tests/drivers/pwm/pwm_api/boards/frdm_ke1xz_flexio_pwm.overlay index 69a8d0811b1e7..cf4cfe45895e9 100644 --- a/tests/drivers/pwm/pwm_api/boards/frdm_ke1xz_flexio_pwm.overlay +++ b/tests/drivers/pwm/pwm_api/boards/frdm_ke1xz_flexio_pwm.overlay @@ -10,7 +10,6 @@ }; }; - &flexio { status = "okay"; flexio0_pwm: flexio0_pwm { diff --git a/tests/drivers/pwm/pwm_api/boards/intel_ptl_h_crb.overlay b/tests/drivers/pwm/pwm_api/boards/intel_ptl_h_crb.overlay new file mode 100644 index 0000000000000..2d4f0bd802d67 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/intel_ptl_h_crb.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pwm0 { + status = "okay"; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/max32655evkit_max32655_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max32655evkit_max32655_m4.overlay index 51ee2e3d40e83..5ac4e6bb58a05 100644 --- a/tests/drivers/pwm/pwm_api/boards/max32655evkit_max32655_m4.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max32655evkit_max32655_m4.overlay @@ -11,7 +11,7 @@ }; &tmr0a_ioa_p0_2 { - power-source=; + power-source = ; }; &timer0 { diff --git a/tests/drivers/pwm/pwm_api/boards/max32655fthr_max32655_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max32655fthr_max32655_m4.overlay index 0171ca42200e4..b1452dee96963 100644 --- a/tests/drivers/pwm/pwm_api/boards/max32655fthr_max32655_m4.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max32655fthr_max32655_m4.overlay @@ -11,7 +11,7 @@ }; &tmr1b_ioa_p0_20 { - power-source=; + power-source = ; }; &timer1 { diff --git a/tests/drivers/pwm/pwm_api/boards/max32662evkit.overlay b/tests/drivers/pwm/pwm_api/boards/max32662evkit.overlay index 256c6b86adcf8..6a338aade2665 100644 --- a/tests/drivers/pwm/pwm_api/boards/max32662evkit.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max32662evkit.overlay @@ -11,7 +11,7 @@ }; &tmr0c_oa_p0_3 { - power-source=; + power-source = ; }; &timer0 { diff --git a/tests/drivers/pwm/pwm_api/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/pwm/pwm_api/boards/max32666evkit_max32666_cpu0.overlay index 0a9088bb7a952..5ee40990e5539 100644 --- a/tests/drivers/pwm/pwm_api/boards/max32666evkit_max32666_cpu0.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max32666evkit_max32666_cpu0.overlay @@ -11,7 +11,7 @@ }; &tmr0_p0_6 { - power-source=; + power-source = ; }; &timer0 { diff --git a/tests/drivers/pwm/pwm_api/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/pwm/pwm_api/boards/max32666fthr_max32666_cpu0.overlay index 816a58c29fc38..8260eab03298e 100644 --- a/tests/drivers/pwm/pwm_api/boards/max32666fthr_max32666_cpu0.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max32666fthr_max32666_cpu0.overlay @@ -11,7 +11,7 @@ }; &tmr0_p0_0 { - power-source=; + power-source = ; }; &timer0 { diff --git a/tests/drivers/pwm/pwm_api/boards/max32675evkit.overlay b/tests/drivers/pwm/pwm_api/boards/max32675evkit.overlay index 3682a2ac1ddea..13a6b51d8e53a 100644 --- a/tests/drivers/pwm/pwm_api/boards/max32675evkit.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max32675evkit.overlay @@ -11,7 +11,7 @@ }; &tmr1c_oa_p0_11 { - power-source=; + power-source = ; }; &timer1 { diff --git a/tests/drivers/pwm/pwm_api/boards/max32690evkit_max32690_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max32690evkit_max32690_m4.overlay index f0e48b975e9fe..020053daeb962 100644 --- a/tests/drivers/pwm/pwm_api/boards/max32690evkit_max32690_m4.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max32690evkit_max32690_m4.overlay @@ -11,7 +11,7 @@ }; &tmr1b_ioa_p0_7 { - power-source=; + power-source = ; }; &timer1 { diff --git a/tests/drivers/pwm/pwm_api/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max78000evkit_max78000_m4.overlay index e57958f7566a3..50e9259d06730 100644 --- a/tests/drivers/pwm/pwm_api/boards/max78000evkit_max78000_m4.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max78000evkit_max78000_m4.overlay @@ -11,7 +11,7 @@ }; &tmr0a_ioa_p0_2 { - power-source=; + power-source = ; }; &timer0 { diff --git a/tests/drivers/pwm/pwm_api/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max78000fthr_max78000_m4.overlay index e57958f7566a3..50e9259d06730 100644 --- a/tests/drivers/pwm/pwm_api/boards/max78000fthr_max78000_m4.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max78000fthr_max78000_m4.overlay @@ -11,7 +11,7 @@ }; &tmr0a_ioa_p0_2 { - power-source=; + power-source = ; }; &timer0 { diff --git a/tests/drivers/pwm/pwm_api/boards/max78002evkit_max78002_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max78002evkit_max78002_m4.overlay index ce8d1f3596427..e79863d7e2e64 100644 --- a/tests/drivers/pwm/pwm_api/boards/max78002evkit_max78002_m4.overlay +++ b/tests/drivers/pwm/pwm_api/boards/max78002evkit_max78002_m4.overlay @@ -11,7 +11,7 @@ }; &tmr0a_ioa_p0_2 { - power-source=; + power-source = ; }; &timer0 { diff --git a/tests/drivers/pwm/pwm_api/boards/mimxrt1180_evk_flexio_pwm.overlay b/tests/drivers/pwm/pwm_api/boards/mimxrt1180_evk_flexio_pwm.overlay index 481e3b22692da..34f606b592192 100644 --- a/tests/drivers/pwm/pwm_api/boards/mimxrt1180_evk_flexio_pwm.overlay +++ b/tests/drivers/pwm/pwm_api/boards/mimxrt1180_evk_flexio_pwm.overlay @@ -15,7 +15,7 @@ }; &pinctrl { - pinmux_flexio2_pwm_default: pinmux_flexio2_pwm_default { + pinmux_flexio2_pwm_default: pinmux_flexio2_pwm_default { group0 { pinmux = <&iomuxc_gpio_ad_02_flexio2_d02>; drive-strength = "normal"; diff --git a/tests/drivers/pwm/pwm_api/boards/native_sim.overlay b/tests/drivers/pwm/pwm_api/boards/native_sim.overlay index f5b77cacfdf24..0f1a9a4b9cf9c 100644 --- a/tests/drivers/pwm/pwm_api/boards/native_sim.overlay +++ b/tests/drivers/pwm/pwm_api/boards/native_sim.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { pwm0: pwm0 { compatible = "zephyr,fake-pwm"; status = "okay"; diff --git a/tests/drivers/pwm/pwm_api/boards/voice_ra4e1.overlay b/tests/drivers/pwm/pwm_api/boards/voice_ra4e1.overlay index 4031e592b2099..7634b223c05c4 100644 --- a/tests/drivers/pwm/pwm_api/boards/voice_ra4e1.overlay +++ b/tests/drivers/pwm/pwm_api/boards/voice_ra4e1.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &pinctrl { pwm2_default: pwm2_default { group1 { diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/bg29_rb4420a.conf b/tests/drivers/pwm/pwm_gpio_loopback/boards/bg29_rb4420a.conf new file mode 100644 index 0000000000000..795414a504ab4 --- /dev/null +++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/bg29_rb4420a.conf @@ -0,0 +1 @@ +CONFIG_SKIP_EDGE_NUM=4 diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/bg29_rb4420a.overlay b/tests/drivers/pwm/pwm_gpio_loopback/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..02b96de4cfe9f --- /dev/null +++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/bg29_rb4420a.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Connections: + * EXP4 - EXP6: TIMER (PC5) to GPIO (PC3) + */ + +/ { + zephyr,user { + pwms = <&timer0_pwm 0 PWM_MSEC(5) PWM_POLARITY_NORMAL>; + gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + timer0_default: timer0_default { + group1 { + pins = ; + drive-push-pull; + }; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/cyw920829m2evk_02.overlay b/tests/drivers/pwm/pwm_gpio_loopback/boards/cyw920829m2evk_02.overlay new file mode 100644 index 0000000000000..20ee0187daec3 --- /dev/null +++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/cyw920829m2evk_02.overlay @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2025 Infineon Technologies AG, + * or an affiliate of Infineon Technologies AG. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + zephyr,user { + pwms = <&pwm0_1 0 PWM_MSEC(2) (PWM_POLARITY_NORMAL | PWM_IFX_TCPWM_OUTPUT_HIGHZ)>, + <&pwm1_0 1 PWM_MSEC(2) (PWM_POLARITY_NORMAL | PWM_IFX_TCPWM_OUTPUT_HIGHZ)>; + gpios = <&gpio_prt3 7 GPIO_ACTIVE_HIGH>, + <&gpio_prt0 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&tcpwm0_1 { + status = "okay"; + divider-type = ; + divider-sel = <1>; + divider-val = <9599>; + + pwm0_1: pwm0_1 { + status = "okay"; + pinctrl-0 = <&p3_6_pwm0_1>; + pinctrl-names = "default"; + }; +}; + +&tcpwm1_0 { + status = "okay"; + divider-type = ; + divider-sel = <1>; + divider-val = <9599>; + + pwm1_0: pwm1_0 { + status = "okay"; + pinctrl-0 = <&p0_1_pwm1_0>; + pinctrl-names = "default"; + }; +}; + +&pinctrl { + p3_6_pwm0_1: p3_6_pwm0_1 { + drive-push-pull; + }; + + p0_1_pwm1_0: p0_1_pwm1_0 { + drive-push-pull; + }; +}; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 7eb6ff84af33b..94cb6ddda6ec2 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -13,10 +13,10 @@ / { zephyr,user { pwms = <&pwm130 0 160000 PWM_POLARITY_NORMAL>, - <&pwm130 1 160000 PWM_POLARITY_NORMAL>, - <&pwm130 2 160000 PWM_POLARITY_NORMAL>, - <&pwm130 3 160000 PWM_POLARITY_NORMAL>, - <&pwm120 0 80000 PWM_POLARITY_NORMAL>; + <&pwm130 1 160000 PWM_POLARITY_NORMAL>, + <&pwm130 2 160000 PWM_POLARITY_NORMAL>, + <&pwm130 3 160000 PWM_POLARITY_NORMAL>, + <&pwm120 0 80000 PWM_POLARITY_NORMAL>; gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>, <&gpio0 4 GPIO_ACTIVE_HIGH>, <&gpio0 5 GPIO_ACTIVE_HIGH>, diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index 69b0c8c5bed65..6a109b2bbf5e9 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -11,8 +11,8 @@ / { zephyr,user { pwms = <&pwm20 0 160000 PWM_POLARITY_NORMAL>, - <&pwm20 1 160000 PWM_POLARITY_NORMAL>, - <&pwm20 2 160000 PWM_POLARITY_NORMAL>; + <&pwm20 1 160000 PWM_POLARITY_NORMAL>, + <&pwm20 2 160000 PWM_POLARITY_NORMAL>; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>, <&gpio1 11 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; @@ -30,9 +30,9 @@ pwm20_sleep: pwm20_sleep { group1 { - psels = , - , - ; + psels = , + , + ; }; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay index 0f727fe87e7ca..055efaf52ed99 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay @@ -17,9 +17,9 @@ <&gpio0 5 ESP32_GPIO_PIN_OUT_EN>; pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>, - <&ledc0 5 80000 PWM_POLARITY_INVERTED>, - <&ledc0 9 1000000 PWM_POLARITY_NORMAL>, - <&ledc0 10 1000000 PWM_POLARITY_INVERTED>; + <&ledc0 5 80000 PWM_POLARITY_INVERTED>, + <&ledc0 9 1000000 PWM_POLARITY_NORMAL>, + <&ledc0 10 1000000 PWM_POLARITY_INVERTED>; }; }; @@ -27,9 +27,9 @@ ledc0_default: ledc0_default { group1 { pinmux = , - , - , - ; + , + , + ; input-enable; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c2.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c2.overlay index 7901b44125ccf..388af444c6bcf 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c2.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c2.overlay @@ -15,7 +15,7 @@ <&gpio0 3 ESP32_GPIO_PIN_OUT_EN>; pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>, - <&ledc0 5 80000 PWM_POLARITY_INVERTED>; + <&ledc0 5 80000 PWM_POLARITY_INVERTED>; }; }; @@ -23,7 +23,7 @@ ledc0_default: ledc0_default { group1 { pinmux = , - ; + ; input-enable; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3.overlay index 7901b44125ccf..388af444c6bcf 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3.overlay @@ -15,7 +15,7 @@ <&gpio0 3 ESP32_GPIO_PIN_OUT_EN>; pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>, - <&ledc0 5 80000 PWM_POLARITY_INVERTED>; + <&ledc0 5 80000 PWM_POLARITY_INVERTED>; }; }; @@ -23,7 +23,7 @@ ledc0_default: ledc0_default { group1 { pinmux = , - ; + ; input-enable; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3_usb.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3_usb.overlay index 7901b44125ccf..388af444c6bcf 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3_usb.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3_usb.overlay @@ -15,7 +15,7 @@ <&gpio0 3 ESP32_GPIO_PIN_OUT_EN>; pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>, - <&ledc0 5 80000 PWM_POLARITY_INVERTED>; + <&ledc0 5 80000 PWM_POLARITY_INVERTED>; }; }; @@ -23,7 +23,7 @@ ledc0_default: ledc0_default { group1 { pinmux = , - ; + ; input-enable; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6_hpcore.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6_hpcore.overlay index 7901b44125ccf..388af444c6bcf 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6_hpcore.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6_hpcore.overlay @@ -15,7 +15,7 @@ <&gpio0 3 ESP32_GPIO_PIN_OUT_EN>; pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>, - <&ledc0 5 80000 PWM_POLARITY_INVERTED>; + <&ledc0 5 80000 PWM_POLARITY_INVERTED>; }; }; @@ -23,7 +23,7 @@ ledc0_default: ledc0_default { group1 { pinmux = , - ; + ; input-enable; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s2.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s2.overlay index 7901b44125ccf..388af444c6bcf 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s2.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s2.overlay @@ -15,7 +15,7 @@ <&gpio0 3 ESP32_GPIO_PIN_OUT_EN>; pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>, - <&ledc0 5 80000 PWM_POLARITY_INVERTED>; + <&ledc0 5 80000 PWM_POLARITY_INVERTED>; }; }; @@ -23,7 +23,7 @@ ledc0_default: ledc0_default { group1 { pinmux = , - ; + ; input-enable; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s3_procpu.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s3_procpu.overlay index 7901b44125ccf..388af444c6bcf 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s3_procpu.overlay +++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32s3_procpu.overlay @@ -15,7 +15,7 @@ <&gpio0 3 ESP32_GPIO_PIN_OUT_EN>; pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>, - <&ledc0 5 80000 PWM_POLARITY_INVERTED>; + <&ledc0 5 80000 PWM_POLARITY_INVERTED>; }; }; @@ -23,7 +23,7 @@ ledc0_default: ledc0_default { group1 { pinmux = , - ; + ; input-enable; }; }; diff --git a/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml b/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml index 33d085b9fa9b5..2959739d50be7 100644 --- a/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml +++ b/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml @@ -26,3 +26,8 @@ tests: drivers.pwm.gpio_loopback.silabs: platform_allow: - xg29_rb4412a + - bg29_rb4420a + + drivers.pwm.gpio_loopback.ifx: + platform_allow: + - cyw920829m2evk_02 diff --git a/tests/drivers/pwm/pwm_loopback/boards/arduino_uno_r4.overlay b/tests/drivers/pwm/pwm_loopback/boards/arduino_uno_r4.overlay index 23b8bea7e5c0e..c93181e550a08 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/arduino_uno_r4.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/arduino_uno_r4.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>, - <&pwm7 0 0 PWM_POLARITY_NORMAL>; + <&pwm7 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/b_u585i_iot02a.overlay b/tests/drivers/pwm/pwm_loopback/boards/b_u585i_iot02a.overlay index e3d21b116d111..a2c1ad980702d 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/b_u585i_iot02a.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/b_u585i_iot02a.overlay @@ -9,6 +9,6 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm4 1 0 PWM_POLARITY_NORMAL>, - <&pwm3 2 0 PWM_POLARITY_NORMAL>; + <&pwm3 2 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/bg29_rb4420a.overlay b/tests/drivers/pwm/pwm_loopback/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..3d4e6840fca82 --- /dev/null +++ b/tests/drivers/pwm/pwm_loopback/boards/bg29_rb4420a.overlay @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Connections: + * EXP4 - EXP6: TIMER (PC5) to TIMER (PC3) + */ + +/ { + pwm_loopback_0 { + compatible = "test-pwm-loopback"; + pwms = <&pwm1 0 PWM_MSEC(5) PWM_POLARITY_NORMAL>, + <&pwm0 0 PWM_MSEC(5) PWM_POLARITY_NORMAL>; + }; +}; + +&pinctrl { + timer0_default: timer0_default { + group1 { + pins = ; + input-enable; + }; + }; + + timer1_default: timer1_default { + group1 { + pins = ; + drive-push-pull; + }; + }; +}; + +&timer0 { + status = "okay"; + + pwm0: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&timer1 { + status = "okay"; + + pwm1: pwm { + pinctrl-0 = <&timer1_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; diff --git a/tests/drivers/pwm/pwm_loopback/boards/disco_l475_iot1.overlay b/tests/drivers/pwm/pwm_loopback/boards/disco_l475_iot1.overlay index 9497e8128aac5..10cc6e0891c9d 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/disco_l475_iot1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/disco_l475_iot1.overlay @@ -11,7 +11,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm2 1 0 PWM_POLARITY_NORMAL>, - <&pwm15 1 0 PWM_POLARITY_NORMAL>; + <&pwm15 1 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra2a1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra2a1.overlay index e757fedea3d16..58df8ac0d0bee 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra2a1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra2a1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>, - <&pwm6 0 0 PWM_POLARITY_NORMAL>; + <&pwm6 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra2l1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra2l1.overlay index 208f8202dccda..42dad9bd4ae44 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra2l1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra2l1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm2 0 0 PWM_POLARITY_NORMAL>, - <&pwm3 0 0 PWM_POLARITY_NORMAL>; + <&pwm3 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4c1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4c1.overlay index b2904c6067138..86ad5ab22c5f5 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4c1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4c1.overlay @@ -11,7 +11,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4e2.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4e2.overlay index 9197e9decb051..2d30c10780f5a 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4e2.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4e2.overlay @@ -11,7 +11,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4l1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4l1.overlay index 4c16fb9739065..bd7c29f093e6d 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4l1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4l1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m1.overlay index 556410c2aef6a..b523f9ab69777 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm3 0 0 PWM_POLARITY_NORMAL>; + <&pwm3 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m2.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m2.overlay index 077b7bdd4062f..5b7b0005e0def 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m2.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m2.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m3.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m3.overlay index 077b7bdd4062f..5b7b0005e0def 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m3.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m3.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4w1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4w1.overlay index 255db670b6f80..291d3acb99c00 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4w1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4w1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6e2.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6e2.overlay index 9197e9decb051..2d30c10780f5a 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6e2.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6e2.overlay @@ -11,7 +11,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m1.overlay index 077b7bdd4062f..5b7b0005e0def 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m2.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m2.overlay index 077b7bdd4062f..5b7b0005e0def 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m2.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m2.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay index bb7ed90c9e071..a138cc2d978d8 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m4.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m4.overlay index 077b7bdd4062f..a138cc2d978d8 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m4.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m4.overlay @@ -11,8 +11,8 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ - pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>, + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m5.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m5.overlay index 077b7bdd4062f..a138cc2d978d8 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m5.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m5.overlay @@ -11,8 +11,8 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ - pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>, + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8d1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8d1.overlay index 6f4d6ea9660b3..dadd3b74e1939 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8d1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8d1.overlay @@ -11,7 +11,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm7 0 0 PWM_POLARITY_NORMAL>, - <&pwm9 0 0 PWM_POLARITY_NORMAL>; + <&pwm9 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8m1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8m1.overlay index 5cd72c8476dec..f513b0d0ca2cc 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8m1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8m1.overlay @@ -11,7 +11,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm7 0 0 PWM_POLARITY_NORMAL>, - <&pwm9 0 0 PWM_POLARITY_NORMAL>; + <&pwm9 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay index 180d20388d3ed..6ec8a6e129f02 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay @@ -11,7 +11,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm2 0 0 PWM_POLARITY_NORMAL>; + <&pwm2 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/fpb_ra4e1.overlay b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra4e1.overlay index 007bd811c0da5..410b8949514b1 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/fpb_ra4e1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra4e1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e1.overlay b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e1.overlay index 077b7bdd4062f..5b7b0005e0def 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e2.overlay b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e2.overlay index 9197e9decb051..2d30c10780f5a 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e2.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra6e2.overlay @@ -11,7 +11,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z.overlay b/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z.overlay index 4a2c35022880b..6b6bed94b3a57 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z.overlay @@ -8,7 +8,7 @@ ftm0_default: ftm0_default { group0 { pinmux = , - ; + ; drive-strength = "low"; slew-rate = "slow"; }; @@ -31,7 +31,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&ftm0 2 0 PWM_POLARITY_NORMAL>, /* PTB14 J3 pin 11 */ - <&pwt 1 0 PWM_POLARITY_NORMAL>; /* PTE11 J2 pin 2 */ + <&pwt 1 0 PWM_POLARITY_NORMAL>; /* PTE11 J2 pin 2 */ }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z512.overlay b/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z512.overlay index 35bfad2ef8575..47759d16942aa 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z512.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/frdm_ke17z512.overlay @@ -8,7 +8,7 @@ ftm0_default: ftm0_default { group0 { pinmux = , - ; + ; drive-strength = "low"; slew-rate = "slow"; }; @@ -31,7 +31,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&ftm0 2 0 PWM_POLARITY_NORMAL>, /* PTB14 J3 pin 11 */ - <&pwt 1 0 PWM_POLARITY_NORMAL>; /* PTE11 J2 pin 11 */ + <&pwt 1 0 PWM_POLARITY_NORMAL>; /* PTE11 J2 pin 11 */ }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/mck_ra8t1.overlay b/tests/drivers/pwm/pwm_loopback/boards/mck_ra8t1.overlay index 875e0f7736a8f..49fe498fb6f0e 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/mck_ra8t1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/mck_ra8t1.overlay @@ -11,7 +11,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm2 0 0 PWM_POLARITY_NORMAL>, - <&pwm5 0 0 PWM_POLARITY_NORMAL>; + <&pwm5 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay b/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay index 9cbda8857fbd3..888866b62a200 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay @@ -11,7 +11,7 @@ compatible = "test-pwm-loopback"; /* Connect P8A pin 3 and P8A pin 6 */ pwms = <&emios0_pwm 0 0 PWM_POLARITY_NORMAL>, - <&emios0_pwm 1 0 PWM_POLARITY_NORMAL>; + <&emios0_pwm 1 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/nucleo_f103rb.overlay b/tests/drivers/pwm/pwm_loopback/boards/nucleo_f103rb.overlay index 12f306cb34d22..a7e457835adb1 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/nucleo_f103rb.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/nucleo_f103rb.overlay @@ -11,6 +11,6 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm1 1 0 PWM_POLARITY_NORMAL>, - <&pwm2 2 0 PWM_POLARITY_NORMAL>; + <&pwm2 2 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/nucleo_h743zi.overlay b/tests/drivers/pwm/pwm_loopback/boards/nucleo_h743zi.overlay index 7ebf049ee13ef..9011b8390abc8 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/nucleo_h743zi.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/nucleo_h743zi.overlay @@ -11,7 +11,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm2 4 0 PWM_POLARITY_NORMAL>, - <&pwm5 1 0 PWM_POLARITY_NORMAL>; + <&pwm5 1 0 PWM_POLARITY_NORMAL>; }; }; @@ -35,6 +35,6 @@ /* At least one of the test devices need to verify * the four-channel-capture-support in this test. */ - four-channel-capture-support; + four-channel-capture-support; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/nucleo_wba55cg.overlay b/tests/drivers/pwm/pwm_loopback/boards/nucleo_wba55cg.overlay index 043ecaa76a802..ca33d985d4b32 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/nucleo_wba55cg.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/nucleo_wba55cg.overlay @@ -4,13 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { pwm_loopback_0 { compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm2 1 0 PWM_POLARITY_NORMAL>, - <&pwm3 1 0 PWM_POLARITY_NORMAL>; + <&pwm3 1 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/rsk_rx130_512kb.overlay b/tests/drivers/pwm/pwm_loopback/boards/rsk_rx130_512kb.overlay index b3b590f296b09..9a2f7e14d9935 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/rsk_rx130_512kb.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/rsk_rx130_512kb.overlay @@ -10,8 +10,8 @@ / { pwm_loopback_0 { compatible = "test-pwm-loopback"; - pwms =<&pwm4 RX_MTIOCxA 0 PWM_POLARITY_NORMAL>, - <&pwm1 RX_MTIOCxA 0 PWM_POLARITY_NORMAL>; + pwms = <&pwm4 RX_MTIOCxA 0 PWM_POLARITY_NORMAL>, + <&pwm1 RX_MTIOCxA 0 PWM_POLARITY_NORMAL>; }; }; @@ -33,7 +33,6 @@ }; }; - &pclkb { div = <4>; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay index 2b7fa95384e85..79112e9d36c2c 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -10,7 +10,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&emios0_pwm 24 0 PWM_POLARITY_NORMAL>, - <&emios0_pwm 25 0 PWM_POLARITY_NORMAL>; + <&emios0_pwm 25 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay index 2b7fa95384e85..79112e9d36c2c 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -10,7 +10,7 @@ pwm_loopback_0 { compatible = "test-pwm-loopback"; pwms = <&emios0_pwm 24 0 PWM_POLARITY_NORMAL>, - <&emios0_pwm 25 0 PWM_POLARITY_NORMAL>; + <&emios0_pwm 25 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/stm32h573i_dk.overlay b/tests/drivers/pwm/pwm_loopback/boards/stm32h573i_dk.overlay index 80d29cf224135..38090a08be699 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/stm32h573i_dk.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/stm32h573i_dk.overlay @@ -9,6 +9,6 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm2 4 0 PWM_POLARITY_NORMAL>, - <&pwm3 2 0 PWM_POLARITY_NORMAL>; + <&pwm3 2 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/stm32n6570_dk_sb.overlay b/tests/drivers/pwm/pwm_loopback/boards/stm32n6570_dk_sb.overlay index 7cc0790cbe51e..1602a92de3979 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/stm32n6570_dk_sb.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/stm32n6570_dk_sb.overlay @@ -11,6 +11,6 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm15 1 0 PWM_POLARITY_NORMAL>, - <&pwm1 1 0 PWM_POLARITY_NORMAL>; + <&pwm1 1 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/voice_ra4e1.overlay b/tests/drivers/pwm/pwm_loopback/boards/voice_ra4e1.overlay index c62c8793d2e1d..2da24732122c8 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/voice_ra4e1.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/voice_ra4e1.overlay @@ -12,7 +12,7 @@ compatible = "test-pwm-loopback"; /* first index must be a 32-Bit timer */ pwms = <&pwm2 0 0 PWM_POLARITY_NORMAL>, - <&pwm4 0 0 PWM_POLARITY_NORMAL>; + <&pwm4 0 0 PWM_POLARITY_NORMAL>; }; }; diff --git a/tests/drivers/pwm/pwm_loopback/boards/xg29_rb4412a.overlay b/tests/drivers/pwm/pwm_loopback/boards/xg29_rb4412a.overlay index ad168fbc93bbc..7a70d8e353798 100644 --- a/tests/drivers/pwm/pwm_loopback/boards/xg29_rb4412a.overlay +++ b/tests/drivers/pwm/pwm_loopback/boards/xg29_rb4412a.overlay @@ -30,7 +30,6 @@ drive-push-pull; }; }; - }; &timer0 { diff --git a/tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay b/tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay index 97d39d55393a0..554721e877346 100644 --- a/tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay +++ b/tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay @@ -32,7 +32,7 @@ * switch the reference source to VDD_ANA. The user needs to measure the * voltage of VDD_ANA pin to set the value of 'zephyr,vref-mv'. */ - voltage-ref= <2>; + voltage-ref = <2>; channel@0 { reg = <0>; diff --git a/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0.overlay index bbacd70a3fa62..c0c42e9e24b47 100644 --- a/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0.overlay +++ b/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -32,7 +32,7 @@ * switch the reference source to VDD_ANA. The user needs to measure the * voltage of VDD_ANA pin to set the value of 'zephyr,vref-mv'. */ - voltage-ref= <2>; + voltage-ref = <2>; channel@0 { reg = <0>; diff --git a/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay b/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay index bbacd70a3fa62..c0c42e9e24b47 100644 --- a/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay +++ b/tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay @@ -32,7 +32,7 @@ * switch the reference source to VDD_ANA. The user needs to measure the * voltage of VDD_ANA pin to set the value of 'zephyr,vref-mv'. */ - voltage-ref= <2>; + voltage-ref = <2>; channel@0 { reg = <0>; diff --git a/tests/drivers/regulator/voltage/boards/frdm_mcxw71.overlay b/tests/drivers/regulator/voltage/boards/frdm_mcxw71.overlay index 509fc8e49264b..10766656d746f 100644 --- a/tests/drivers/regulator/voltage/boards/frdm_mcxw71.overlay +++ b/tests/drivers/regulator/voltage/boards/frdm_mcxw71.overlay @@ -32,7 +32,7 @@ * switch the reference source to VDD_ANA. The user needs to measure the * voltage of VDD_ANA pin to set the value of 'zephyr,vref-mv'. */ - voltage-ref= <0>; + voltage-ref = <0>; channel@0 { reg = <0>; diff --git a/tests/drivers/regulator/voltage/boards/lpcxpresso55s36.overlay b/tests/drivers/regulator/voltage/boards/lpcxpresso55s36.overlay index a109a427c6348..b33e1883b5fab 100644 --- a/tests/drivers/regulator/voltage/boards/lpcxpresso55s36.overlay +++ b/tests/drivers/regulator/voltage/boards/lpcxpresso55s36.overlay @@ -31,7 +31,7 @@ * switch the reference source to VDDA. The user needs to measure the * voltage of VDDA pin to set the value of 'zephyr,vref-mv'. */ - voltage-ref= <2>; + voltage-ref = <2>; channel@0 { reg = <0>; diff --git a/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay index be214f149ae29..e46f2f979f6a0 100644 --- a/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay +++ b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay @@ -32,7 +32,7 @@ * switch the reference source to VDD_ANA. The user needs to measure the * voltage of VDD_ANA pin to set the value of 'zephyr,vref-mv'. */ - voltage-ref= <2>; + voltage-ref = <2>; channel@0 { reg = <0>; diff --git a/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay index be214f149ae29..e46f2f979f6a0 100644 --- a/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay +++ b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay @@ -32,7 +32,7 @@ * switch the reference source to VDD_ANA. The user needs to measure the * voltage of VDD_ANA pin to set the value of 'zephyr,vref-mv'. */ - voltage-ref= <2>; + voltage-ref = <2>; channel@0 { reg = <0>; diff --git a/tests/drivers/regulator/voltage/boards/mimxrt685_evk_mimxrt685s_cm33.overlay b/tests/drivers/regulator/voltage/boards/mimxrt685_evk_mimxrt685s_cm33.overlay index 4256e19793925..14b10fa5ca63d 100644 --- a/tests/drivers/regulator/voltage/boards/mimxrt685_evk_mimxrt685s_cm33.overlay +++ b/tests/drivers/regulator/voltage/boards/mimxrt685_evk_mimxrt685s_cm33.overlay @@ -9,19 +9,19 @@ * so limit regulator voltage to this range. * Only test regulators we can safely change voltage to in RUN mode */ - &ldo1 { +&ldo1 { regulator-max-microvolt = <1800000>; - }; +}; - &ldo2 { +&ldo2 { regulator-max-microvolt = <1800000>; - }; +}; /* Override LPADC0 pinctrl settings */ &pinmux_lpadc0 { group0 { pinmux = , - ; + ; slew-rate = "normal"; drive-strength = "normal"; nxp,analog-mode; diff --git a/tests/drivers/rtc/rtc_api/boards/nucleo_h533re.overlay b/tests/drivers/rtc/rtc_api/boards/nucleo_h533re.overlay index 0ed5c08c87f20..bd861fccf4292 100644 --- a/tests/drivers/rtc/rtc_api/boards/nucleo_h533re.overlay +++ b/tests/drivers/rtc/rtc_api/boards/nucleo_h533re.overlay @@ -1,4 +1,4 @@ - /* +/* * Copyright (c) 2024 STMicroelectronics * * SPDX-License-Identifier: Apache-2.0 diff --git a/tests/drivers/rtc/shell/app.overlay b/tests/drivers/rtc/shell/app.overlay index 183c4d1ba5193..f64a261ed3bc9 100644 --- a/tests/drivers/rtc/shell/app.overlay +++ b/tests/drivers/rtc/shell/app.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { fake_rtc: fake_rtc { compatible = "zephyr,fake-rtc"; status = "okay"; diff --git a/tests/drivers/sensor/ina230/boards/native_sim.overlay b/tests/drivers/sensor/ina230/boards/native_sim.overlay index 3b81407dee4bb..f8a789a7f6533 100644 --- a/tests/drivers/sensor/ina230/boards/native_sim.overlay +++ b/tests/drivers/sensor/ina230/boards/native_sim.overlay @@ -2,10 +2,10 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include - &i2c0 { - status = "okay"; +&i2c0 { + status = "okay"; /* Datasheet example and Default DT Configuration Test */ ina230_default_test: ina230@40 { diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index 46ee277dbfbb4..ec14118e6b375 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -70,7 +70,7 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; zephyr,pm-device-runtime-auto; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index 46ee277dbfbb4..ec14118e6b375 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -70,7 +70,7 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; zephyr,pm-device-runtime-auto; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/ek_ra8m1.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/ek_ra8m1.overlay index 019a7754da7e2..c1aebe2101f3f 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/ek_ra8m1.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/ek_ra8m1.overlay @@ -8,8 +8,8 @@ group1 { /* MISO MOSI RSPCK SSL */ psels = , - , - ; + , + ; }; }; @@ -17,9 +17,9 @@ group1 { /* MISO MOSI RSPCK SSL */ psels = , - , - , - ; + , + , + ; }; }; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay index 18531a8faf6b7..72bb74931860d 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &spi3 { diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi index 46680e31bf0b1..bad32ea4d1c9e 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &gpio0 { @@ -75,7 +74,7 @@ dut_spis: &spi131 { pinctrl-0 = <&spis131_default_alt>; pinctrl-1 = <&spis131_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; zephyr,pm-device-runtime-auto; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay index f145a10bb67af..81b1303ede153 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay @@ -75,7 +75,7 @@ dut_spis: &spi131 { pinctrl-1 = <&spis131_sleep_alt>; pinctrl-names = "default", "sleep"; memory-regions = <&cpuapp_dma_region>; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; zephyr,pm-device-runtime-auto; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast_spis.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast_spis.overlay index 8a5728e291eb6..be975607c1b53 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast_spis.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast_spis.overlay @@ -78,7 +78,7 @@ }; }; -&exmif{ +&exmif { status = "disabled"; }; @@ -137,6 +137,6 @@ dut_spis: &spi131 { pinctrl-1 = <&spis131_sleep_alt>; pinctrl-names = "default", "sleep"; memory-regions = <&cpuapp_dma_region>; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index e1b2683293260..7915897066d8a 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &gpio2 { @@ -69,7 +68,7 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; zephyr,pm-device-runtime-auto; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay index f2e1ac5ce4ecc..7fd8d54d8db5a 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay @@ -68,6 +68,6 @@ dut_spis: &spi22 { pinctrl-0 = <&spi22_default_alt>; pinctrl-1 = <&spi22_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay index 25d68cd4dfa6d..b02a2be6218ab 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay @@ -49,7 +49,6 @@ }; }; - &gpio1 { status = "okay"; }; @@ -77,6 +76,6 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/ophelia4ev_nrf54l15_cpuapp.overlay index 5b3a64e7fbc47..5a6b6928e0564 100644 --- a/tests/drivers/spi/spi_controller_peripheral/boards/ophelia4ev_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_controller_peripheral/boards/ophelia4ev_nrf54l15_cpuapp.overlay @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &gpio2 { @@ -70,7 +69,7 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; zephyr,pm-device-runtime-auto; }; diff --git a/tests/drivers/spi/spi_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index 43edc077d97b4..b44b4d868dfc6 100644 --- a/tests/drivers/spi/spi_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -69,6 +69,6 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index 43edc077d97b4..b44b4d868dfc6 100644 --- a/tests/drivers/spi/spi_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -69,6 +69,6 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay index 477917e0ca748..fc8c0002171be 100644 --- a/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay +++ b/tests/drivers/spi/spi_error_cases/boards/nrf52840dk_nrf52840.overlay @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &spi3 { diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_common.dtsi index 7b8a3fa033a90..0aac812a28e18 100644 --- a/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_common.dtsi +++ b/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &gpiote130 { @@ -73,6 +72,6 @@ dut_spis: &spi131 { pinctrl-0 = <&spis131_default_alt>; pinctrl-1 = <&spis131_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay index 9422ff33fd6d7..ad68628e8e0f9 100644 --- a/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay +++ b/tests/drivers/spi/spi_error_cases/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay @@ -74,6 +74,6 @@ dut_spis: &spi131 { pinctrl-1 = <&spis131_sleep_alt>; pinctrl-names = "default", "sleep"; memory-regions = <&cpuapp_dma_region>; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index d431f2783373f..94f0e299f4a06 100644 --- a/tests/drivers/spi/spi_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_error_cases/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &gpio2 { @@ -68,6 +67,6 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay index 25d68cd4dfa6d..b02a2be6218ab 100644 --- a/tests/drivers/spi/spi_error_cases/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay +++ b/tests/drivers/spi/spi_error_cases/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay @@ -49,7 +49,6 @@ }; }; - &gpio1 { status = "okay"; }; @@ -77,6 +76,6 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay index 6e272f3f2db2d..f8d9c165f596a 100644 --- a/tests/drivers/spi/spi_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay +++ b/tests/drivers/spi/spi_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay @@ -40,7 +40,6 @@ low-power-enable; }; }; - }; &gpio2 { @@ -69,6 +68,6 @@ dut_spis: &spi21 { pinctrl-0 = <&spi21_default_alt>; pinctrl-1 = <&spi21_sleep_alt>; pinctrl-names = "default", "sleep"; - /delete-property/rx-delay-supported; - /delete-property/rx-delay; + /delete-property/ rx-delay-supported; + /delete-property/ rx-delay; }; diff --git a/tests/drivers/spi/spi_loopback/boards/bg29_rb4420a.conf b/tests/drivers/spi/spi_loopback/boards/bg29_rb4420a.conf new file mode 100644 index 0000000000000..1e3c5f17bfc3a --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/bg29_rb4420a.conf @@ -0,0 +1,2 @@ +CONFIG_DMA_MAX_DESCRIPTOR=16 +CONFIG_SPI_SILABS_EUSART_DMA_MAX_BLOCKS=10 diff --git a/tests/drivers/spi/spi_loopback/boards/bg29_rb4420a.overlay b/tests/drivers/spi/spi_loopback/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..7dcc73aecb8c0 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/bg29_rb4420a.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* + * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header + */ + +&eusart1 { + dmas = <&dma0 DMA_REQSEL_EUSART1TXFL>, + <&dma0 DMA_REQSEL_EUSART1RXFL>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpioc 6 GPIO_ACTIVE_LOW>; + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + fast@1 { + compatible = "test-spi-loopback-fast"; + reg = <1>; + spi-max-frequency = <10000000>; + }; +}; + +&dma0 { + status = "okay"; +}; diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra2l1.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra2l1.overlay index b87c781820939..94066b0660f8f 100644 --- a/tests/drivers/spi/spi_loopback/boards/ek_ra2l1.overlay +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra2l1.overlay @@ -25,8 +25,8 @@ group1 { /* MISO MOSI RSPCK */ psels = , - , - ; + , + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra8m1.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra8m1.overlay index 781069befc34f..09887ba700283 100644 --- a/tests/drivers/spi/spi_loopback/boards/ek_ra8m1.overlay +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra8m1.overlay @@ -3,16 +3,16 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include &pinctrl { spi0_default: spi0_default { group1 { /* MISO MOSI RSPCK SSL*/ psels = , - , - , - ; + , + , + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_ke1xz_flexio_spi.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_ke1xz_flexio_spi.overlay index e7e41c783ee48..84ac332527743 100644 --- a/tests/drivers/spi/spi_loopback/boards/frdm_ke1xz_flexio_spi.overlay +++ b/tests/drivers/spi/spi_loopback/boards/frdm_ke1xz_flexio_spi.overlay @@ -12,9 +12,9 @@ pinmux_flexio_spi0: pinmux_flexio_spi0 { group0 { pinmux = , /* cs */ - , /* sck */ - , /* sdo */ - ; /* sdi */ + , /* sck */ + , /* sdo */ + ; /* sdi */ drive-strength = "low"; slew-rate = "slow"; }; diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxw72_mcxw727c_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxw72_mcxw727c_cpu0.overlay index eca30219f2e01..0ff75f6e12ad6 100644 --- a/tests/drivers/spi/spi_loopback/boards/frdm_mcxw72_mcxw727c_cpu0.overlay +++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxw72_mcxw727c_cpu0.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* * This is a loopback setup for the frdm_mcxw72 * To test this sample, connect J2.6 <-> J2.7 diff --git a/tests/drivers/spi/spi_loopback/boards/gd32f403z_eval.overlay b/tests/drivers/spi/spi_loopback/boards/gd32f403z_eval.overlay index 35f2dea555ab6..a5e8194031bc4 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32f403z_eval.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32f403z_eval.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma0 1 0>, <&dma0 2 0>; + dmas = <&dma0 1 0>, <&dma0 2 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/gd32f407v_start.overlay b/tests/drivers/spi/spi_loopback/boards/gd32f407v_start.overlay index 5ff4b4b8ed4cb..5295091ab8b16 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32f407v_start.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32f407v_start.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; + dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/gd32f450i_eval.overlay b/tests/drivers/spi/spi_loopback/boards/gd32f450i_eval.overlay index 5ff4b4b8ed4cb..5295091ab8b16 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32f450i_eval.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32f450i_eval.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; + dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/gd32f450v_start.overlay b/tests/drivers/spi/spi_loopback/boards/gd32f450v_start.overlay index 5ff4b4b8ed4cb..5295091ab8b16 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32f450v_start.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32f450v_start.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; + dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/gd32f450z_eval.overlay b/tests/drivers/spi/spi_loopback/boards/gd32f450z_eval.overlay index 5ff4b4b8ed4cb..5295091ab8b16 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32f450z_eval.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32f450z_eval.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; + dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/gd32f470i_eval.overlay b/tests/drivers/spi/spi_loopback/boards/gd32f470i_eval.overlay index 5ff4b4b8ed4cb..5295091ab8b16 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32f470i_eval.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32f470i_eval.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; + dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/gd32vf103c_starter.overlay b/tests/drivers/spi/spi_loopback/boards/gd32vf103c_starter.overlay index 35f2dea555ab6..a5e8194031bc4 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32vf103c_starter.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32vf103c_starter.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma0 1 0>, <&dma0 2 0>; + dmas = <&dma0 1 0>, <&dma0 2 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/gd32vf103v_eval.overlay b/tests/drivers/spi/spi_loopback/boards/gd32vf103v_eval.overlay index 35f2dea555ab6..a5e8194031bc4 100644 --- a/tests/drivers/spi/spi_loopback/boards/gd32vf103v_eval.overlay +++ b/tests/drivers/spi/spi_loopback/boards/gd32vf103v_eval.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma0 1 0>, <&dma0 2 0>; + dmas = <&dma0 1 0>, <&dma0 2 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/longan_nano.overlay b/tests/drivers/spi/spi_loopback/boards/longan_nano.overlay index 35f2dea555ab6..a5e8194031bc4 100644 --- a/tests/drivers/spi/spi_loopback/boards/longan_nano.overlay +++ b/tests/drivers/spi/spi_loopback/boards/longan_nano.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma0 1 0>, <&dma0 2 0>; + dmas = <&dma0 1 0>, <&dma0 2 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay b/tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay index 35f2dea555ab6..a5e8194031bc4 100644 --- a/tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay +++ b/tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay @@ -26,7 +26,7 @@ cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dma0 1 0>, <&dma0 2 0>; + dmas = <&dma0 1 0>, <&dma0 2 0>; dma-names = "rx", "tx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay index f42ec2b316041..c901431348f72 100644 --- a/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay +++ b/tests/drivers/spi/spi_loopback/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &hs_lspi { /delete-property/ cs-gpios; slow@1 { diff --git a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qlj.overlay b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qlj.overlay index 1cfdb4d08b36d..d26562c6fb285 100644 --- a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qlj.overlay +++ b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qlj.overlay @@ -16,8 +16,8 @@ compatible = "microchip,mec5-qspi"; clock-frequency = <12000000>; - pinctrl-0 = < &qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 - &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224 >; + pinctrl-0 = <&qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 + &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224>; pinctrl-names = "default"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qsz.overlay b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qsz.overlay index 1cfdb4d08b36d..d26562c6fb285 100644 --- a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qsz.overlay +++ b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1743_qsz.overlay @@ -16,8 +16,8 @@ compatible = "microchip,mec5-qspi"; clock-frequency = <12000000>; - pinctrl-0 = < &qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 - &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224 >; + pinctrl-0 = <&qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 + &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224>; pinctrl-names = "default"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qlj.overlay b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qlj.overlay index 1cfdb4d08b36d..d26562c6fb285 100644 --- a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qlj.overlay +++ b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qlj.overlay @@ -16,8 +16,8 @@ compatible = "microchip,mec5-qspi"; clock-frequency = <12000000>; - pinctrl-0 = < &qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 - &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224 >; + pinctrl-0 = <&qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 + &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224>; pinctrl-names = "default"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qsz.overlay b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qsz.overlay index 1cfdb4d08b36d..d26562c6fb285 100644 --- a/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qsz.overlay +++ b/tests/drivers/spi/spi_loopback/boards/mec_assy6941_mec1753_qsz.overlay @@ -16,8 +16,8 @@ compatible = "microchip,mec5-qspi"; clock-frequency = <12000000>; - pinctrl-0 = < &qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 - &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224 >; + pinctrl-0 = <&qspi_shd_cs0_n_gpio055 &qspi_shd_clk_gpio056 + &qspi_shd_io0_gpio223 &qspi_shd_io1_gpio224>; pinctrl-names = "default"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk_flexio_spi.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk_flexio_spi.overlay index 154a56c46b87b..0c2ae38cbb26f 100644 --- a/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk_flexio_spi.overlay +++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk_flexio_spi.overlay @@ -10,11 +10,10 @@ &pinctrl { pinmux_flexio3spi0: pinmux_flexio3spi0 { group0 { - pinmux = - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, /* cs */ - <&iomuxc_gpio_ad_b1_04_flexio3_flexio04>, /* sck */ - <&iomuxc_gpio_ad_b1_01_flexio3_flexio01>, /* sdo */ - <&iomuxc_gpio_ad_b1_00_flexio3_flexio00>; /* sdi */ + pinmux = <&iomuxc_gpio_ad_b0_15_gpio1_io15>, /* cs */ + <&iomuxc_gpio_ad_b1_04_flexio3_flexio04>, /* sck */ + <&iomuxc_gpio_ad_b1_01_flexio3_flexio01>, /* sdo */ + <&iomuxc_gpio_ad_b1_00_flexio3_flexio00>; /* sdi */ drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "150-mhz"; @@ -22,11 +21,10 @@ }; pinmux_flexio3spi1: pinmux_flexio3spi1 { group0 { - pinmux = - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, /* cs */ - <&iomuxc_gpio_ad_b1_05_flexio3_flexio05>, /* sck */ - <&iomuxc_gpio_ad_b1_03_flexio3_flexio03>, /* sdo */ - <&iomuxc_gpio_ad_b1_02_flexio3_flexio02>; /* sdi */ + pinmux = <&iomuxc_gpio_ad_b0_14_gpio1_io14>, /* cs */ + <&iomuxc_gpio_ad_b1_05_flexio3_flexio05>, /* sck */ + <&iomuxc_gpio_ad_b1_03_flexio3_flexio03>, /* sdo */ + <&iomuxc_gpio_ad_b1_02_flexio3_flexio02>; /* sdi */ drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "150-mhz"; diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_flexio_spi.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_flexio_spi.overlay index 6682f9cd30bdd..c7f145a28a5d4 100644 --- a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_flexio_spi.overlay +++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_flexio_spi.overlay @@ -10,7 +10,6 @@ status = "disabled"; }; - &pinctrl { pinmux_flexio2spi1: pinmux_flexio2spi1 { group0 { @@ -20,12 +19,10 @@ <&iomuxc_gpio_ad_31_flexio2_flexio31>; /* sdi */ drive-strength = "high"; slew-rate = "slow"; - }; }; }; - &flexio2 { status = "okay"; diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay index 54cc40cdb62af..4ea937f1aaee2 100644 --- a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay +++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay @@ -15,7 +15,7 @@ }; &ocram1 { - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; &lpspi3 { diff --git a/tests/drivers/spi/spi_loopback/boards/nrf54lm20dk_nrf54lm20a_cpuapp_spi00.overlay b/tests/drivers/spi/spi_loopback/boards/nrf54lm20dk_nrf54lm20a_cpuapp_spi00.overlay index 2d1015eaf24bc..b39af2af67467 100644 --- a/tests/drivers/spi/spi_loopback/boards/nrf54lm20dk_nrf54lm20a_cpuapp_spi00.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nrf54lm20dk_nrf54lm20a_cpuapp_spi00.overlay @@ -17,7 +17,7 @@ group2 { psels = , ; - nordic,drive-mode = ; + nordic,drive-mode = ; }; }; diff --git a/tests/drivers/spi/spi_loopback/boards/nrf_at_16mhz.overlay b/tests/drivers/spi/spi_loopback/boards/nrf_at_16mhz.overlay index b2cec530184ee..6afb46019206d 100644 --- a/tests/drivers/spi/spi_loopback/boards/nrf_at_16mhz.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nrf_at_16mhz.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &dut_fast { spi-max-frequency = ; }; diff --git a/tests/drivers/spi/spi_loopback/boards/nrf_at_32mhz.overlay b/tests/drivers/spi/spi_loopback/boards/nrf_at_32mhz.overlay index 37d93f21a2476..830c03c024c9d 100644 --- a/tests/drivers/spi/spi_loopback/boards/nrf_at_32mhz.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nrf_at_32mhz.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &dut_fast { spi-max-frequency = ; }; diff --git a/tests/drivers/spi/spi_loopback/boards/nrf_at_8mhz.overlay b/tests/drivers/spi/spi_loopback/boards/nrf_at_8mhz.overlay index d01d89dc6ec73..0a5ebcbce8af5 100644 --- a/tests/drivers/spi/spi_loopback/boards/nrf_at_8mhz.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nrf_at_8mhz.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &dut_fast { spi-max-frequency = ; }; diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_g474re.overlay b/tests/drivers/spi/spi_loopback/boards/nucleo_g474re.overlay index 7f18b475a9310..e4c7c86c30c58 100644 --- a/tests/drivers/spi/spi_loopback/boards/nucleo_g474re.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nucleo_g474re.overlay @@ -6,10 +6,10 @@ &rcc { /* - * Reduce bus clock speed to be able - * to reach SPI_LOOPBACK_SLOW_FREQ = 500000 - * with max prescaler 256 - */ + * Reduce bus clock speed to be able + * to reach SPI_LOOPBACK_SLOW_FREQ = 500000 + * with max prescaler 256 + */ apb2-prescaler = <2>; }; diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_h743zi.overlay b/tests/drivers/spi/spi_loopback/boards/nucleo_h743zi.overlay index f6098fd3426fe..ed80a6ec7034d 100644 --- a/tests/drivers/spi/spi_loopback/boards/nucleo_h743zi.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nucleo_h743zi.overlay @@ -11,7 +11,7 @@ }; &sram2 { - zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >; + zephyr,memory-attr = ; }; &spi1 { diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m4.overlay b/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m4.overlay index 642cbd53941d5..dbdd83cb802f1 100644 --- a/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m4.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m4.overlay @@ -11,7 +11,7 @@ }; &sram2 { - zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >; + zephyr,memory-attr = ; }; &spi1 { diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay b/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay index 642cbd53941d5..dbdd83cb802f1 100644 --- a/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nucleo_h745zi_q_stm32h745xx_m7.overlay @@ -11,7 +11,7 @@ }; &sram2 { - zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >; + zephyr,memory-attr = ; }; &spi1 { diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_h753zi.overlay b/tests/drivers/spi/spi_loopback/boards/nucleo_h753zi.overlay index 097f6ddecba4e..8939d49f854a6 100644 --- a/tests/drivers/spi/spi_loopback/boards/nucleo_h753zi.overlay +++ b/tests/drivers/spi/spi_loopback/boards/nucleo_h753zi.overlay @@ -11,7 +11,7 @@ }; &sram2 { - zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >; + zephyr,memory-attr = ; }; &spi1 { diff --git a/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay b/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay index a910f60637e7b..dab72248ef161 100644 --- a/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay +++ b/tests/drivers/spi/spi_loopback/boards/numaker_m2l31ki.overlay @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ &pinctrl { -/* EVB's NU5: SS/CLK/MISO/MOSI */ + /* EVB's NU5: SS/CLK/MISO/MOSI */ spi0_default: spi0_default { group0 { pinmux = , diff --git a/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.overlay b/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.overlay index 409396e208169..eaf24b3ddbe41 100644 --- a/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.overlay +++ b/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.overlay @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ &pinctrl { -/* EVB's NU5: SS/CLK/MISO/MOSI */ + /* EVB's NU5: SS/CLK/MISO/MOSI */ spi2_default: spi2_default { group0 { pinmux = , diff --git a/tests/drivers/spi/spi_loopback/boards/numaker_pfm_m467.overlay b/tests/drivers/spi/spi_loopback/boards/numaker_pfm_m467.overlay index 8840f8776f363..07b5e6d6e139e 100644 --- a/tests/drivers/spi/spi_loopback/boards/numaker_pfm_m467.overlay +++ b/tests/drivers/spi/spi_loopback/boards/numaker_pfm_m467.overlay @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: Apache-2.0 */ &pinctrl { -/* EVB's NU5: SS/CLK/MISO/MOSI */ + /* EVB's NU5: SS/CLK/MISO/MOSI */ spi2_default: spi2_default { group0 { pinmux = , - , - , - ; + , + , + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf b/tests/drivers/spi/spi_loopback/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf index 20315ebd72e06..7f23148f3c37c 100644 --- a/tests/drivers/spi/spi_loopback/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf +++ b/tests/drivers/spi/spi_loopback/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf @@ -4,3 +4,4 @@ CONFIG_SPI_RENESAS_RZ_RSPI_DMAC=n CONFIG_SPI_RTIO=n CONFIG_SPI_LOOPBACK_MODE_LOOP=n CONFIG_SPI_LARGE_BUFFER_SIZE=2048 +CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING=16 diff --git a/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay b/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay index 00138441dab43..e7562ff6e45e0 100644 --- a/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay +++ b/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &spi0 { +&spi0 { loopback; dmas = <&xdmac 1 DMA_PERID_SPI0_TX>, <&xdmac 2 DMA_PERID_SPI0_RX>; diff --git a/tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay b/tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay index 00138441dab43..e7562ff6e45e0 100644 --- a/tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay +++ b/tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - &spi0 { +&spi0 { loopback; dmas = <&xdmac 1 DMA_PERID_SPI0_TX>, <&xdmac 2 DMA_PERID_SPI0_RX>; diff --git a/tests/drivers/spi/spi_loopback/boards/siwx917_dk2605a.overlay b/tests/drivers/spi/spi_loopback/boards/siwx917_dk2605a.overlay index 7f7ec60287639..0ff4ed58edd01 100644 --- a/tests/drivers/spi/spi_loopback/boards/siwx917_dk2605a.overlay +++ b/tests/drivers/spi/spi_loopback/boards/siwx917_dk2605a.overlay @@ -21,7 +21,7 @@ pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; - dmas = <&dma0 11>, <&dma0 10>; + dmas = <&dma0 11>, <&dma0 10>; dma-names = "tx", "rx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/siwx917_rb4338a.overlay b/tests/drivers/spi/spi_loopback/boards/siwx917_rb4338a.overlay index 6013a8d9d7bc6..e1502cb3f135d 100644 --- a/tests/drivers/spi/spi_loopback/boards/siwx917_rb4338a.overlay +++ b/tests/drivers/spi/spi_loopback/boards/siwx917_rb4338a.overlay @@ -21,7 +21,7 @@ pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; - dmas = <&dma0 11>, <&dma0 10>; + dmas = <&dma0 11>, <&dma0 10>; dma-names = "tx", "rx"; slow@0 { diff --git a/tests/drivers/spi/spi_loopback/boards/xmc45_relax_kit.overlay b/tests/drivers/spi/spi_loopback/boards/xmc45_relax_kit.overlay index da82e0313ae63..381c30afff08b 100644 --- a/tests/drivers/spi/spi_loopback/boards/xmc45_relax_kit.overlay +++ b/tests/drivers/spi/spi_loopback/boards/xmc45_relax_kit.overlay @@ -28,7 +28,7 @@ miso-src = "DX0B"; interrupts = <84 1 85 1>; interrupt-names = "tx", "rx"; - dmas = <&dma0 1 0 XMC4XXX_SET_CONFIG(0,10)>, <&dma0 2 0 XMC4XXX_SET_CONFIG(2,11)>; + dmas = <&dma0 1 0 XMC4XXX_SET_CONFIG(0, 10)>, <&dma0 2 0 XMC4XXX_SET_CONFIG(2, 11)>; dma-names = "tx", "rx"; #address-cells = <1>; diff --git a/tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay b/tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay index 7500cad3b7b7e..c14714f71e749 100644 --- a/tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay +++ b/tests/drivers/spi/spi_loopback/overlay-mcux-flexio-spi.overlay @@ -5,24 +5,22 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* On RT1060 EVKC, SPI loopback test, short J17-9 and J17-10 - * On RT1064 EVK, SPI loopback test, short J24-9 and J24-10 - */ +/* On RT1060 EVKC, SPI loopback test, short J17-9 and J17-10 + * On RT1064 EVK, SPI loopback test, short J24-9 and J24-10 + */ &pinctrl { pinmux_flexio3spi0: pinmux_flexio3spi0 { group0 { - pinmux = - <&iomuxc_gpio_ad_b0_03_gpio1_io03>, /* cs */ - <&iomuxc_gpio_ad_b1_10_flexio3_flexio10>, /* sck */ - <&iomuxc_gpio_ad_b1_00_flexio3_flexio00>, /* sdo */ - <&iomuxc_gpio_ad_b1_01_flexio3_flexio01>; /* sdi */ + pinmux = <&iomuxc_gpio_ad_b0_03_gpio1_io03>, /* cs */ + <&iomuxc_gpio_ad_b1_10_flexio3_flexio10>, /* sck */ + <&iomuxc_gpio_ad_b1_00_flexio3_flexio00>, /* sdo */ + <&iomuxc_gpio_ad_b1_01_flexio3_flexio01>; /* sdi */ drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "150-mhz"; }; }; - }; &flexio3 { @@ -52,5 +50,4 @@ spi-max-frequency = <16000000>; }; }; - }; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32_procpu.overlay b/tests/drivers/spi/spi_loopback/socs/esp32_procpu.overlay index c70cabccddd0d..f0fd747b9a51c 100644 --- a/tests/drivers/spi/spi_loopback/socs/esp32_procpu.overlay +++ b/tests/drivers/spi/spi_loopback/socs/esp32_procpu.overlay @@ -16,7 +16,7 @@ }; group3 { pinmux = , - ; + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c2.overlay b/tests/drivers/spi/spi_loopback/socs/esp32c2.overlay index c708dfc64f340..8d59729064263 100644 --- a/tests/drivers/spi/spi_loopback/socs/esp32c2.overlay +++ b/tests/drivers/spi/spi_loopback/socs/esp32c2.overlay @@ -16,7 +16,7 @@ }; group3 { pinmux = , - ; + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c3.overlay b/tests/drivers/spi/spi_loopback/socs/esp32c3.overlay index 95e9bf56a078f..43b71798d151f 100644 --- a/tests/drivers/spi/spi_loopback/socs/esp32c3.overlay +++ b/tests/drivers/spi/spi_loopback/socs/esp32c3.overlay @@ -16,7 +16,7 @@ }; group3 { pinmux = , - ; + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c3_usb.overlay b/tests/drivers/spi/spi_loopback/socs/esp32c3_usb.overlay index 95e9bf56a078f..43b71798d151f 100644 --- a/tests/drivers/spi/spi_loopback/socs/esp32c3_usb.overlay +++ b/tests/drivers/spi/spi_loopback/socs/esp32c3_usb.overlay @@ -16,7 +16,7 @@ }; group3 { pinmux = , - ; + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.overlay b/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.overlay index 95e9bf56a078f..43b71798d151f 100644 --- a/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.overlay +++ b/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.overlay @@ -16,7 +16,7 @@ }; group3 { pinmux = , - ; + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32h2.conf b/tests/drivers/spi/spi_loopback/socs/esp32h2.conf new file mode 100644 index 0000000000000..36c826845422e --- /dev/null +++ b/tests/drivers/spi/spi_loopback/socs/esp32h2.conf @@ -0,0 +1,3 @@ +CONFIG_SPI_ESP32_INTERRUPT=y +CONFIG_HEAP_MEM_POOL_SIZE=32768 +CONFIG_DMA=y diff --git a/tests/drivers/spi/spi_loopback/socs/esp32h2.overlay b/tests/drivers/spi/spi_loopback/socs/esp32h2.overlay new file mode 100644 index 0000000000000..af59b7ed1f6c2 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/socs/esp32h2.overlay @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + spim2_loopback: spim2_loopback { + group1 { + pinmux = ; + output-enable; /* Enable internal loopback */ + }; + group2 { + pinmux = ; + input-enable; /* Enable internal loopback */ + }; + group3 { + pinmux = , + ; + }; + }; +}; + +&spi2 { + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <16000000>; + }; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + dma-enabled; + pinctrl-0 = <&spim2_loopback>; + pinctrl-names = "default"; + status = "okay"; + + dmas = <&dma 0>, <&dma 1>; + dma-names = "rx", "tx"; +}; + +&dma { + status = "okay"; +}; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32s2.overlay b/tests/drivers/spi/spi_loopback/socs/esp32s2.overlay index 9e1705f063b76..ab4596e0a9a9f 100644 --- a/tests/drivers/spi/spi_loopback/socs/esp32s2.overlay +++ b/tests/drivers/spi/spi_loopback/socs/esp32s2.overlay @@ -16,7 +16,7 @@ }; group3 { pinmux = , - ; + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/socs/esp32s3_procpu.overlay b/tests/drivers/spi/spi_loopback/socs/esp32s3_procpu.overlay index 8edafb44e79e0..7b038c98a05c1 100644 --- a/tests/drivers/spi/spi_loopback/socs/esp32s3_procpu.overlay +++ b/tests/drivers/spi/spi_loopback/socs/esp32s3_procpu.overlay @@ -16,7 +16,7 @@ }; group3 { pinmux = , - ; + ; }; }; }; diff --git a/tests/drivers/spi/spi_loopback/src/spi.c b/tests/drivers/spi/spi_loopback/src/spi.c index a3c0479800e64..6ca688484a289 100644 --- a/tests/drivers/spi/spi_loopback/src/spi.c +++ b/tests/drivers/spi/spi_loopback/src/spi.c @@ -74,8 +74,6 @@ const struct gpio_dt_spec mosi_pin = GPIO_DT_SPEC_GET_OR(DT_PATH(zephyr_user), m #define __NOCACHE #if CONFIG_DCACHE_LINE_SIZE != 0 #define __BUF_ALIGN __aligned(CONFIG_DCACHE_LINE_SIZE) -#else -#define __BUF_ALIGN __aligned(DT_PROP_OR(DT_PATH(cpus, cpu_0), d_cache_line_size, 32)) #endif #endif /* CONFIG_NOCACHE_MEMORY */ @@ -297,6 +295,9 @@ ZTEST(spi_loopback, test_spi_complete_multiple) /* same as the test_spi_complete_multiple test, but seeing if there is any unreasonable latency */ ZTEST(spi_loopback, test_spi_complete_multiple_timed) { + /* Do not check timing when coverage is enabled */ + Z_TEST_SKIP_IFDEF(CONFIG_COVERAGE); + struct spi_dt_spec *spec = loopback_specs[spec_idx]; const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 2, buffer_tx, BUF_SIZE, @@ -641,7 +642,7 @@ ZTEST(spi_loopback, test_spi_same_buf_cmd) spi_loopback_compare_bufs(tx_data, buffer_rx, 1, buffer_print_tx, buffer_print_rx); - char zeros[BUF_SIZE - 1] = {0}; + static const char zeros[BUF_SIZE - 1] = {0}; zassert_ok(memcmp(buffer_rx+1, zeros, BUF_SIZE - 1)); } @@ -687,7 +688,7 @@ ZTEST(spi_loopback, test_spi_word_size_9) { struct spi_dt_spec *spec = loopback_specs[spec_idx]; - static __BUF_ALIGN uint16_t tx_data_9[BUFWIDE_SIZE]; + static __BUF_ALIGN __NOCACHE uint16_t tx_data_9[BUFWIDE_SIZE]; for (int i = 0; i < BUFWIDE_SIZE; i++) { tx_data_9[i] = tx_data_16[i] & 0x1FF; @@ -711,7 +712,7 @@ ZTEST(spi_loopback, test_spi_word_size_24) { struct spi_dt_spec *spec = loopback_specs[spec_idx]; - static __BUF_ALIGN uint32_t tx_data_24[BUFWIDE_SIZE]; + static __BUF_ALIGN __NOCACHE uint32_t tx_data_24[BUFWIDE_SIZE]; for (int i = 0; i < BUFWIDE_SIZE; i++) { tx_data_24[i] = tx_data_32[i] & 0xFFFFFF; diff --git a/tests/drivers/spi/spi_loopback/testcase.yaml b/tests/drivers/spi/spi_loopback/testcase.yaml index 13a61fed6447a..13a3c3bbe54e3 100644 --- a/tests/drivers/spi/spi_loopback/testcase.yaml +++ b/tests/drivers/spi/spi_loopback/testcase.yaml @@ -34,6 +34,7 @@ tests: platform_allow: - robokit1 - mimxrt1170_evk/mimxrt1176/cm7 + - bg29_rb4420a integration_platforms: - robokit1 drivers.spi.mcux_dspi_dma.loopback: @@ -317,6 +318,7 @@ tests: platform_allow: - xg24_rb4187c - xg29_rb4412a + - bg29_rb4420a extra_configs: - CONFIG_SPI_SILABS_EUSART_DMA=n - CONFIG_SPI_ASYNC=n @@ -325,6 +327,7 @@ tests: platform_allow: - xg24_rb4187c - xg29_rb4412a + - bg29_rb4420a extra_configs: - CONFIG_SPI_SILABS_EUSART_DMA=y - CONFIG_SPI_ASYNC=n diff --git a/tests/drivers/stepper/shell/app.overlay b/tests/drivers/stepper/shell/app.overlay index ee0a78de9b784..f6c262f129eae 100644 --- a/tests/drivers/stepper/shell/app.overlay +++ b/tests/drivers/stepper/shell/app.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -/{ +/ { fake_stepper: fake_stepper { compatible = "zephyr,fake-stepper"; status = "okay"; diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209.overlay index caf4f3c5b3a78..6f6fac956c2a2 100644 --- a/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209.overlay +++ b/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &adi_tmc2209; + stepper = &adi_tmc2209; }; }; diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209_work_q.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209_work_q.overlay index a7756000d955d..a9177871f1147 100644 --- a/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209_work_q.overlay +++ b/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209_work_q.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &adi_tmc2209; + stepper = &adi_tmc2209; }; }; diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979.overlay index 3d1c69339dfa5..897d95933c8fb 100644 --- a/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979.overlay +++ b/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &allegro_a4979; + stepper = &allegro_a4979; }; }; diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979_work_q.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979_work_q.overlay index fe4e02eb1f799..85404efc18ace 100644 --- a/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979_work_q.overlay +++ b/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979_work_q.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &allegro_a4979; + stepper = &allegro_a4979; }; }; diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx.overlay index 0763a19e393b7..22b09bc1edf53 100644 --- a/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx.overlay +++ b/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &ti_drv84xx; + stepper = &ti_drv84xx; }; }; diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx_work_q.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx_work_q.overlay index 2ca7a34d38888..b9545a12739a9 100644 --- a/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx_work_q.overlay +++ b/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx_work_q.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &ti_drv84xx; + stepper = &ti_drv84xx; }; }; diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_zephyr_h_bridge_stepper.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_zephyr_h_bridge_stepper.overlay index 8782f68e9611c..11bfb3d560244 100644 --- a/tests/drivers/stepper/stepper_api/boards/native_sim_zephyr_h_bridge_stepper.overlay +++ b/tests/drivers/stepper/stepper_api/boards/native_sim_zephyr_h_bridge_stepper.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &zephyr_h_bridge_stepper; + stepper = &zephyr_h_bridge_stepper; }; }; diff --git a/tests/drivers/stepper/stepper_api/boards/qemu_x86_64_zephyr_h_bridge_stepper.overlay b/tests/drivers/stepper/stepper_api/boards/qemu_x86_64_zephyr_h_bridge_stepper.overlay index a5ca16772ba7a..e11ea8dddc302 100644 --- a/tests/drivers/stepper/stepper_api/boards/qemu_x86_64_zephyr_h_bridge_stepper.overlay +++ b/tests/drivers/stepper/stepper_api/boards/qemu_x86_64_zephyr_h_bridge_stepper.overlay @@ -7,7 +7,7 @@ / { aliases { - stepper = &zephyr_h_bridge_stepper; + stepper = &zephyr_h_bridge_stepper; }; }; diff --git a/tests/drivers/syscon/boards/qemu_cortex_a53.overlay b/tests/drivers/syscon/boards/qemu_cortex_a53.overlay index 352983eb31b03..2da1d021f278f 100644 --- a/tests/drivers/syscon/boards/qemu_cortex_a53.overlay +++ b/tests/drivers/syscon/boards/qemu_cortex_a53.overlay @@ -6,7 +6,7 @@ soc { sram0: memory@40000000 { compatible = "mmio-sram"; - reg = < 0x0 0x40000000 0x0 0x7000000 >; + reg = <0x0 0x40000000 0x0 0x7000000>; }; res: memory@47000000 { diff --git a/tests/drivers/tee/optee/boards/native_sim_64.overlay b/tests/drivers/tee/optee/boards/native_sim_64.overlay index 19789998a57db..65ceec3f5fb27 100644 --- a/tests/drivers/tee/optee/boards/native_sim_64.overlay +++ b/tests/drivers/tee/optee/boards/native_sim_64.overlay @@ -4,10 +4,10 @@ */ / { firmware { - optee { + optee { compatible = "linaro,optee-tz"; method = "smc"; status = "okay"; - }; + }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/bg29_rb4420a.overlay b/tests/drivers/uart/uart_async_api/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..6f5e4ebe73325 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/bg29_rb4420a.overlay @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2025, Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Connect EXP4 (PC5) and EXP6 (PC3) of the Expansion Pin header + */ + +&pinctrl { + usart0_default: usart0_default { + group0 { + pins = ; /* WPK EXP4 (PC5) */ + drive-push-pull; + output-high; + }; + group1 { + pins = ; /* WPK EXP6 (PC3) */ + input-enable; + silabs,input-filter; + }; + }; +}; + +dut: &usart0 { + dmas = <&dma0 DMA_REQSEL_USART0TXBL>, + <&dma0 DMA_REQSEL_USART0RXDATAV>; + dma-names = "tx", "rx"; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/cy8cproto_062_4343w.overlay b/tests/drivers/uart/uart_async_api/boards/cy8cproto_062_4343w.overlay index 8ebe004565462..8ddba811bca9c 100644 --- a/tests/drivers/uart/uart_async_api/boards/cy8cproto_062_4343w.overlay +++ b/tests/drivers/uart/uart_async_api/boards/cy8cproto_062_4343w.overlay @@ -13,7 +13,6 @@ input-enable; }; - dut: &scb3 { compatible = "infineon,cat1-uart"; status = "okay"; diff --git a/tests/drivers/uart/uart_async_api/boards/disco_l475_iot1.overlay b/tests/drivers/uart/uart_async_api/boards/disco_l475_iot1.overlay index 051b9bb4d4c07..5af8d42397fa2 100644 --- a/tests/drivers/uart/uart_async_api/boards/disco_l475_iot1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/disco_l475_iot1.overlay @@ -2,7 +2,7 @@ dut: &uart4 { dmas = <&dma2 3 2 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>, - <&dma2 5 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; + <&dma2 5 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra2a1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra2a1.overlay index 50cafd978b6ed..305283273c3a4 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra2a1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra2a1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra2l1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra2l1.overlay index c12f59bbeee93..c15825bc10984 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra2l1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra2l1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4c1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4c1.overlay index b919990829d6b..7d5414a034538 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra4c1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4c1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4e2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4e2.overlay index 10121b5ad9ee9..401f5491f0b77 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra4e2.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4e2.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4l1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4l1.overlay index e8343b61c6c74..543e6021c4cc7 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra4l1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4l1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4m1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4m1.overlay index 6bf3f9ce967d9..61ac0455ac6af 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra4m1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4m1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4m2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4m2.overlay index 21e0f0f9141cc..3c462c572a9f9 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra4m2.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4m2.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4m3.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4m3.overlay index dbef642d32d9e..6c78865d1d055 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra4m3.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4m3.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4w1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4w1.overlay index 238c284fa2d9b..6a4e124a7f9eb 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra4w1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4w1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay index 10121b5ad9ee9..401f5491f0b77 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6e2.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay index e73ba999f6604..e6653de4d4b28 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m1.overlay @@ -8,7 +8,7 @@ group1 { /* tx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay index dbef642d32d9e..6c78865d1d055 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m2.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay index dbef642d32d9e..6c78865d1d055 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m3.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay index eafbefdaf62b8..6a93c0bdc4065 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m4.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay index eafbefdaf62b8..6a93c0bdc4065 100644 --- a/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay +++ b/tests/drivers/uart/uart_async_api/boards/ek_ra6m5.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra4e1.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra4e1.overlay index 98d8c87cc7f3b..422fb14e212aa 100644 --- a/tests/drivers/uart/uart_async_api/boards/fpb_ra4e1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra4e1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay index c80fe08563968..f13207ef983bf 100644 --- a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay index 10121b5ad9ee9..401f5491f0b77 100644 --- a/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay +++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra6e2.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_c092rc.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_c092rc.overlay index ac4070fe63372..4933794e441b2 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_c092rc.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_c092rc.overlay @@ -8,7 +8,6 @@ status = "okay"; }; - dut: &usart4 { dmas = <&dmamux1 5 57 STM32_DMA_PERIPH_TX>, <&dmamux1 6 56 STM32_DMA_PERIPH_RX>; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_f207zg.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_f207zg.overlay index f727d709a3876..0269ce8144c6b 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_f207zg.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_f207zg.overlay @@ -2,6 +2,6 @@ dut: &usart6 { dmas = <&dma2 7 5 0x28440 0x03>, - <&dma2 2 5 0x28480 0x03>; + <&dma2 2 5 0x28480 0x03>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_f429zi.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_f429zi.overlay index c5174fda3ff48..57fa44ba8f989 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_f429zi.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_f429zi.overlay @@ -2,7 +2,7 @@ dut: &usart6 { dmas = <&dma2 7 5 0x28440 0x03>, - <&dma2 2 5 0x28480 0x03>; + <&dma2 2 5 0x28480 0x03>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_f746zg.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_f746zg.overlay index e9ee7174e10d3..702b23454d205 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_f746zg.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_f746zg.overlay @@ -2,7 +2,7 @@ dut: &usart6 { dmas = <&dma2 7 5 0x28440 0x03>, - <&dma2 2 5 0x28480 0x03>; + <&dma2 2 5 0x28480 0x03>; dma-names = "tx", "rx"; status = "okay"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_f767zi.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_f767zi.overlay index c5174fda3ff48..57fa44ba8f989 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_f767zi.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_f767zi.overlay @@ -2,7 +2,7 @@ dut: &usart6 { dmas = <&dma2 7 5 0x28440 0x03>, - <&dma2 2 5 0x28480 0x03>; + <&dma2 2 5 0x28480 0x03>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_h723zg.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_h723zg.overlay index 9ecaf11a0817a..ed38e470a31e0 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_h723zg.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_h723zg.overlay @@ -10,7 +10,7 @@ dut: &uart9 { pinctrl-names = "default"; current-speed = <115200>; dmas = <&dmamux1 2 117 STM32_DMA_PERIPH_TX>, - <&dmamux1 3 116 STM32_DMA_PERIPH_RX>; + <&dmamux1 3 116 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; status = "okay"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_h743zi.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_h743zi.overlay index 13c49ed1337f5..d8026dedba9fe 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_h743zi.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_h743zi.overlay @@ -4,7 +4,7 @@ dut: &usart2 { dmas = <&dmamux1 2 44 STM32_DMA_PERIPH_TX>, - <&dmamux1 3 43 STM32_DMA_PERIPH_RX>; + <&dmamux1 3 43 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>; pinctrl-names = "default"; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_l152re.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_l152re.overlay index 76d4220ef5eec..1b4168068fe84 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_l152re.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_l152re.overlay @@ -5,7 +5,7 @@ dut: &usart3 { pinctrl-names = "default"; current-speed = <115200>; dmas = <&dma1 2 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>, - <&dma1 3 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; + <&dma1 3 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; status = "okay"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_l4r5zi.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_l4r5zi.overlay index 547eb79e757de..837f57516319e 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_l4r5zi.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_l4r5zi.overlay @@ -2,7 +2,7 @@ dut: &usart3 { dmas = <&dmamux1 5 29 STM32_DMA_PERIPH_TX>, - <&dmamux1 4 28 STM32_DMA_PERIPH_RX>; + <&dmamux1 4 28 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q.overlay index bc491885737aa..49de14721524f 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q.overlay @@ -6,7 +6,7 @@ dut: &usart3 { dmas = <&dmamux1 5 30 STM32_DMA_PERIPH_TX>, - <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; + <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay index bc491885737aa..49de14721524f 100644 --- a/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay +++ b/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay @@ -6,7 +6,7 @@ dut: &usart3 { dmas = <&dmamux1 5 30 STM32_DMA_PERIPH_TX>, - <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; + <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/slwrb4180a.overlay b/tests/drivers/uart/uart_async_api/boards/slwrb4180a.overlay index 1d0220a86bc77..59fa95aa914a7 100644 --- a/tests/drivers/uart/uart_async_api/boards/slwrb4180a.overlay +++ b/tests/drivers/uart/uart_async_api/boards/slwrb4180a.overlay @@ -15,7 +15,7 @@ }; }; -&pinctrl{ +&pinctrl { usart0_default: usart0_default { group0 { pins = ; diff --git a/tests/drivers/uart/uart_async_api/boards/stm32f3_disco.overlay b/tests/drivers/uart/uart_async_api/boards/stm32f3_disco.overlay index c30d89f0f5ee7..27b85b7124c4d 100644 --- a/tests/drivers/uart/uart_async_api/boards/stm32f3_disco.overlay +++ b/tests/drivers/uart/uart_async_api/boards/stm32f3_disco.overlay @@ -2,6 +2,6 @@ dut: &usart2 { dmas = <&dma1 7 STM32_DMA_PERIPH_TX>, - <&dma1 6 STM32_DMA_PERIPH_RX>; + <&dma1 6 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/stm32h735g_disco.overlay b/tests/drivers/uart/uart_async_api/boards/stm32h735g_disco.overlay index 3074284bfe499..18a7dcbfe8a68 100644 --- a/tests/drivers/uart/uart_async_api/boards/stm32h735g_disco.overlay +++ b/tests/drivers/uart/uart_async_api/boards/stm32h735g_disco.overlay @@ -7,7 +7,7 @@ dut: &uart7 { dmas = <&dmamux1 2 80 STM32_DMA_PERIPH_TX>, - <&dmamux1 3 79 STM32_DMA_PERIPH_RX>; + <&dmamux1 3 79 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; pinctrl-0 = <&uart7_tx_pf7 &uart7_rx_pf6>; pinctrl-names = "default"; diff --git a/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk.overlay b/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk.overlay index bc491885737aa..49de14721524f 100644 --- a/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk.overlay +++ b/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk.overlay @@ -6,7 +6,7 @@ dut: &usart3 { dmas = <&dmamux1 5 30 STM32_DMA_PERIPH_TX>, - <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; + <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay b/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay index bc491885737aa..49de14721524f 100644 --- a/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay +++ b/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay @@ -6,7 +6,7 @@ dut: &usart3 { dmas = <&dmamux1 5 30 STM32_DMA_PERIPH_TX>, - <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; + <&dmamux1 4 29 STM32_DMA_PERIPH_RX>; dma-names = "tx", "rx"; }; diff --git a/tests/drivers/uart/uart_async_api/boards/voice_ra4e1.overlay b/tests/drivers/uart/uart_async_api/boards/voice_ra4e1.overlay index e276242dbbe10..28f8e516b4d8c 100644 --- a/tests/drivers/uart/uart_async_api/boards/voice_ra4e1.overlay +++ b/tests/drivers/uart/uart_async_api/boards/voice_ra4e1.overlay @@ -8,7 +8,7 @@ group1 { /* tx rx */ psels = , - ; + ; }; }; }; diff --git a/tests/drivers/uart/uart_async_api/boards/xg23_rb4210a.overlay b/tests/drivers/uart/uart_async_api/boards/xg23_rb4210a.overlay index e275da0aa61cd..4a493ff6f0eed 100644 --- a/tests/drivers/uart/uart_async_api/boards/xg23_rb4210a.overlay +++ b/tests/drivers/uart/uart_async_api/boards/xg23_rb4210a.overlay @@ -4,9 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ - /* - * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header - */ +/* + * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header + */ / { chosen { zephyr,console = &usart0; @@ -16,7 +16,7 @@ }; }; -&pinctrl{ +&pinctrl { eusart1_default: eusart1_default { group0 { pins = ; /* WPK EXP4 (PC1) */ @@ -47,7 +47,7 @@ dut: &eusart1 { compatible = "silabs,eusart-uart"; dmas = <&dma0 DMA_REQSEL_EUSART1TXFL>, - <&dma0 DMA_REQSEL_EUSART1RXFL>; + <&dma0 DMA_REQSEL_EUSART1RXFL>; dma-names = "tx", "rx"; current-speed = <115200>; pinctrl-0 = <&eusart1_default>; diff --git a/tests/drivers/uart/uart_async_api/boards/xg24_rb4187c.overlay b/tests/drivers/uart/uart_async_api/boards/xg24_rb4187c.overlay index 1e9c88c10330f..7799139c6f097 100644 --- a/tests/drivers/uart/uart_async_api/boards/xg24_rb4187c.overlay +++ b/tests/drivers/uart/uart_async_api/boards/xg24_rb4187c.overlay @@ -15,7 +15,7 @@ }; }; -&pinctrl{ +&pinctrl { usart0_default: usart0_default { group0 { pins = ; diff --git a/tests/drivers/uart/uart_async_api/boards/xg29_rb4412a.overlay b/tests/drivers/uart/uart_async_api/boards/xg29_rb4412a.overlay index 9f599003dbc09..a8b2b56eb5e38 100644 --- a/tests/drivers/uart/uart_async_api/boards/xg29_rb4412a.overlay +++ b/tests/drivers/uart/uart_async_api/boards/xg29_rb4412a.overlay @@ -15,7 +15,7 @@ }; }; -&pinctrl{ +&pinctrl { usart0_default: usart0_default { group0 { pins = ; /* WPK EXP4 (PC0) */ diff --git a/tests/drivers/uart/uart_async_api/boards/xmc45_relax_kit.overlay b/tests/drivers/uart/uart_async_api/boards/xmc45_relax_kit.overlay index c08d008736609..69ed39b02208b 100644 --- a/tests/drivers/uart/uart_async_api/boards/xmc45_relax_kit.overlay +++ b/tests/drivers/uart/uart_async_api/boards/xmc45_relax_kit.overlay @@ -10,7 +10,7 @@ dut: &usic2ch0 { input-src = "DX0G"; interrupts = <96 1 97 1>; interrupt-names = "tx", "rx"; - dmas = <&dma1 1 0 XMC4XXX_SET_CONFIG(10,6)>, <&dma1 2 0 XMC4XXX_SET_CONFIG(11,6)>; + dmas = <&dma1 1 0 XMC4XXX_SET_CONFIG(10, 6)>, <&dma1 2 0 XMC4XXX_SET_CONFIG(11, 6)>; dma-names = "tx", "rx"; fifo-start-offset = <0>; fifo-tx-size = <0>; diff --git a/tests/drivers/uart/uart_async_api/boards/xmc47_relax_kit.overlay b/tests/drivers/uart/uart_async_api/boards/xmc47_relax_kit.overlay index 431232855f4ac..a6db8e6f8d8af 100644 --- a/tests/drivers/uart/uart_async_api/boards/xmc47_relax_kit.overlay +++ b/tests/drivers/uart/uart_async_api/boards/xmc47_relax_kit.overlay @@ -12,7 +12,7 @@ dut: &usic1ch1 { current-speed = <921600>; interrupts = <90 1 91 1>; interrupt-names = "tx", "rx"; - dmas = <&dma0 2 0 XMC4XXX_SET_CONFIG(1,11)>, <&dma0 3 0 XMC4XXX_SET_CONFIG(3,12)>; + dmas = <&dma0 2 0 XMC4XXX_SET_CONFIG(1, 11)>, <&dma0 3 0 XMC4XXX_SET_CONFIG(3, 12)>; dma-names = "tx", "rx"; pinctrl-0 = <&uart_tx_p3_15_u1c1 &uart_rx_p3_14_u1c1>; pinctrl-names = "default"; diff --git a/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm12.overlay b/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm12.overlay index 7bf3f93f6cc57..f22135eb2aac2 100644 --- a/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm12.overlay +++ b/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm12.overlay @@ -8,4 +8,4 @@ * mimxrt595_evk/mimxrt595s/cm33 Short J27-1 to J27-2 */ -dut: &flexcomm12 { }; +dut: &flexcomm12 {}; diff --git a/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm4.overlay b/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm4.overlay index 56b71c7fff87b..1819b72028508 100644 --- a/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm4.overlay +++ b/tests/drivers/uart/uart_async_api/nxp/dut_flexcomm4.overlay @@ -8,4 +8,4 @@ * mimxrt685_evk/mimxrt685s/cm33 Short J27-1 to J27-2 */ -dut: &flexcomm4 { }; +dut: &flexcomm4 {}; diff --git a/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_common.dtsi index 79dac0ca96079..e651cf5399ed2 100644 --- a/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_common.dtsi +++ b/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -4,7 +4,7 @@ uart134_alt_default: uart134_alt_default { group1 { psels = ; - bias-pull-up; + bias-pull-up; }; group2 { psels = ; @@ -25,7 +25,7 @@ }; group2 { psels = ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index ab144c4b1c801..2f3f32035b958 100644 --- a/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/drivers/uart/uart_async_dual/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -10,7 +10,6 @@ memory-regions = <&cpuapp_dma_region>; }; - &dma_fast_region { status = "okay"; }; diff --git a/tests/drivers/uart/uart_async_dual/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_async_dual/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index cd06494115318..93ad73f3b3738 100644 --- a/tests/drivers/uart/uart_async_dual/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/uart/uart_async_dual/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -4,7 +4,7 @@ uart21_default: uart21_default { group1 { psels = ; - bias-pull-up; + bias-pull-up; }; group2 { psels = ; @@ -25,7 +25,7 @@ }; group2 { psels = ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_async_dual/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_async_dual/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay index fe79690cbbadc..be5aec5de8069 100644 --- a/tests/drivers/uart/uart_async_dual/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/uart/uart_async_dual/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay @@ -4,7 +4,7 @@ uart21_default: uart21_default { group1 { psels = ; - bias-pull-up; + bias-pull-up; }; group2 { psels = ; @@ -25,7 +25,7 @@ }; group2 { psels = ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_async_dual/boards/nrf9160dk_nrf9160.overlay b/tests/drivers/uart/uart_async_dual/boards/nrf9160dk_nrf9160.overlay index d47b0db3ad9c4..cc644420477b1 100644 --- a/tests/drivers/uart/uart_async_dual/boards/nrf9160dk_nrf9160.overlay +++ b/tests/drivers/uart/uart_async_dual/boards/nrf9160dk_nrf9160.overlay @@ -4,7 +4,7 @@ uart1_default: uart1_default { group1 { psels = ; - bias-pull-up; + bias-pull-up; }; group2 { psels = ; @@ -25,7 +25,7 @@ }; group2 { psels = ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_elementary/boards/bg29_rb4420a.overlay b/tests/drivers/uart/uart_elementary/boards/bg29_rb4420a.overlay new file mode 100644 index 0000000000000..ab1a67de996db --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/bg29_rb4420a.overlay @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025, Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Connect EXP4 (PC5) and EXP6 (PC3) of the Expansion Pin header + */ + +&pinctrl { + usart0_default: usart0_default { + group0 { + pins = ; /* WPK EXP4 (PC5) */ + drive-push-pull; + output-high; + }; + group1 { + pins = ; /* WPK EXP6 (PC3) */ + input-enable; + silabs,input-filter; + }; + }; +}; + +dut: &usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp_dual_uart.overlay index afe50c3b16af6..ec936b265d236 100644 --- a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp_dual_uart.overlay +++ b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp_dual_uart.overlay @@ -10,7 +10,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; @@ -26,7 +26,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr_dual_uart.overlay index afe50c3b16af6..ec936b265d236 100644 --- a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr_dual_uart.overlay +++ b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr_dual_uart.overlay @@ -10,7 +10,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; @@ -26,7 +26,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp_dual_uart.overlay index afe50c3b16af6..ec936b265d236 100644 --- a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp_dual_uart.overlay +++ b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp_dual_uart.overlay @@ -10,7 +10,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; @@ -26,7 +26,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr_dual_uart.overlay index afe50c3b16af6..ec936b265d236 100644 --- a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr_dual_uart.overlay +++ b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr_dual_uart.overlay @@ -10,7 +10,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; @@ -26,7 +26,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi index 22d8378937c25..93cb223ce68a2 100644 --- a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi +++ b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ &cpuapp_dma_region { - status="okay"; + status = "okay"; }; &pinctrl { @@ -33,5 +33,4 @@ dut: &uart135 { pinctrl-names = "default", "sleep"; current-speed = <115200>; hw-flow-control; - }; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay index fb2f80460fe85..5721c590f4392 100644 --- a/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay +++ b/tests/drivers/uart/uart_elementary/boards/nrf54h20dk_nrf54h20_cpuapp_dual_uart.overlay @@ -2,12 +2,11 @@ #include "nrf54h20dk_nrf54h20_common.dtsi" - &pinctrl { uart135_default_alt: uart135_default_alt { group1 { psels = ; - bias-pull-up; + bias-pull-up; }; group2 { psels = ; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l15dk_nrf54l15_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l15dk_nrf54l15_dual_uart.overlay index 2031f7a244413..70d37955a71f4 100644 --- a/tests/drivers/uart/uart_elementary/boards/nrf54l15dk_nrf54l15_dual_uart.overlay +++ b/tests/drivers/uart/uart_elementary/boards/nrf54l15dk_nrf54l15_dual_uart.overlay @@ -5,7 +5,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; @@ -21,7 +21,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54lm20dk_nrf54lm20a_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54lm20dk_nrf54lm20a_dual_uart.overlay index 72e7e968d0b78..e6762501544ce 100644 --- a/tests/drivers/uart/uart_elementary/boards/nrf54lm20dk_nrf54lm20a_dual_uart.overlay +++ b/tests/drivers/uart/uart_elementary/boards/nrf54lm20dk_nrf54lm20a_dual_uart.overlay @@ -10,7 +10,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; @@ -26,7 +26,7 @@ group1 { psels = , ; - bias-pull-up; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_elementary/boards/xg24_rb4187c.overlay b/tests/drivers/uart/uart_elementary/boards/xg24_rb4187c.overlay new file mode 100644 index 0000000000000..af0bf4be88ad4 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/boards/xg24_rb4187c.overlay @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2025, Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,console = &eusart0; + zephyr,shell-uart = &eusart0; + zephyr,uart-pipe = &eusart0; + }; +}; + +/* + * Connect EXP4 (PC1) and EXP6 (PC2) of the Expansion Pin header + */ + +&pinctrl { + eusart0_default: eusart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = ; /* WPK EXP4 (PC1) */ + drive-push-pull; + output-high; + }; + group1 { + pins = ; /* WPK EXP6 (PC2) */ + input-enable; + silabs,input-filter; + }; + }; +}; + +dut: &usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&eusart0 { + compatible = "silabs,eusart-uart"; + current-speed = <115200>; + pinctrl-0 = <&eusart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32_procpu.overlay b/tests/drivers/uart/uart_elementary/socs/esp32_procpu.overlay index 7db2beb0b009a..a6824a6c9f722 100644 --- a/tests/drivers/uart/uart_elementary/socs/esp32_procpu.overlay +++ b/tests/drivers/uart/uart_elementary/socs/esp32_procpu.overlay @@ -7,13 +7,13 @@ uart1_test: uart1_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; @@ -22,13 +22,13 @@ uart2_test: uart2_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32c2.overlay b/tests/drivers/uart/uart_elementary/socs/esp32c2.overlay index 3bb87cd42530d..79fc4d403ecaa 100644 --- a/tests/drivers/uart/uart_elementary/socs/esp32c2.overlay +++ b/tests/drivers/uart/uart_elementary/socs/esp32c2.overlay @@ -7,13 +7,13 @@ uart1_test: uart1_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32c3.overlay b/tests/drivers/uart/uart_elementary/socs/esp32c3.overlay index d2df77b7ebc50..f825fa90ee3d7 100644 --- a/tests/drivers/uart/uart_elementary/socs/esp32c3.overlay +++ b/tests/drivers/uart/uart_elementary/socs/esp32c3.overlay @@ -7,13 +7,13 @@ uart1_test: uart1_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32c3_usb.overlay b/tests/drivers/uart/uart_elementary/socs/esp32c3_usb.overlay index d2df77b7ebc50..f825fa90ee3d7 100644 --- a/tests/drivers/uart/uart_elementary/socs/esp32c3_usb.overlay +++ b/tests/drivers/uart/uart_elementary/socs/esp32c3_usb.overlay @@ -7,13 +7,13 @@ uart1_test: uart1_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32c6_hpcore.overlay b/tests/drivers/uart/uart_elementary/socs/esp32c6_hpcore.overlay index d2df77b7ebc50..f825fa90ee3d7 100644 --- a/tests/drivers/uart/uart_elementary/socs/esp32c6_hpcore.overlay +++ b/tests/drivers/uart/uart_elementary/socs/esp32c6_hpcore.overlay @@ -7,13 +7,13 @@ uart1_test: uart1_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32h2.overlay b/tests/drivers/uart/uart_elementary/socs/esp32h2.overlay new file mode 100644 index 0000000000000..ef36c4dbbbf45 --- /dev/null +++ b/tests/drivers/uart/uart_elementary/socs/esp32h2.overlay @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart1_test: uart1_test { + group1 { + pinmux = , + ; + input-enable; + output-high; + }; + group2 { + pinmux = , + ; + output-enable; + bias-pull-up; + }; + }; +}; + +dut: &uart1 { + status = "okay"; + pinctrl-0 = <&uart1_test>; + pinctrl-names = "default"; + current-speed = <115200>; +}; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32s2.overlay b/tests/drivers/uart/uart_elementary/socs/esp32s2.overlay index d2df77b7ebc50..f825fa90ee3d7 100644 --- a/tests/drivers/uart/uart_elementary/socs/esp32s2.overlay +++ b/tests/drivers/uart/uart_elementary/socs/esp32s2.overlay @@ -7,13 +7,13 @@ uart1_test: uart1_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; diff --git a/tests/drivers/uart/uart_elementary/socs/esp32s3_procpu.overlay b/tests/drivers/uart/uart_elementary/socs/esp32s3_procpu.overlay index 7db2beb0b009a..a6824a6c9f722 100644 --- a/tests/drivers/uart/uart_elementary/socs/esp32s3_procpu.overlay +++ b/tests/drivers/uart/uart_elementary/socs/esp32s3_procpu.overlay @@ -7,13 +7,13 @@ uart1_test: uart1_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; @@ -22,13 +22,13 @@ uart2_test: uart2_test { group1 { pinmux = , - ; + ; input-enable; output-high; }; group2 { pinmux = , - ; + ; output-enable; bias-pull-up; }; diff --git a/tests/drivers/uart/uart_elementary/testcase.yaml b/tests/drivers/uart/uart_elementary/testcase.yaml index cbf222fa72cf7..8b3ea127695a5 100644 --- a/tests/drivers/uart/uart_elementary/testcase.yaml +++ b/tests/drivers/uart/uart_elementary/testcase.yaml @@ -22,8 +22,11 @@ tests: - esp8684_devkitm - esp32c3_devkitm - esp32c6_devkitc/esp32c6/hpcore + - esp32h2_devkitm - esp32s2_saola - esp32s3_devkitm/esp32s3/procpu + - xg24_rb4187c + - bg29_rb4420a integration_platforms: - nrf54h20dk/nrf54h20/cpuapp drivers.uart.uart_elementary_dual_nrf54h: diff --git a/tests/drivers/uart/uart_emul/uart_emul.overlay b/tests/drivers/uart/uart_emul/uart_emul.overlay index 03ff62cdd2562..1a3c4af97499b 100644 --- a/tests/drivers/uart/uart_emul/uart_emul.overlay +++ b/tests/drivers/uart/uart_emul/uart_emul.overlay @@ -2,7 +2,7 @@ * Copyright (c) 2023 Fabian Blatz * * SPDX-License-Identifier: Apache-2.0 -*/ + */ / { euart0: uart-emul { diff --git a/tests/drivers/uart/uart_errors/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay index e2364f091be73..e19eff8044c4f 100644 --- a/tests/drivers/uart/uart_errors/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/uart/uart_errors/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay @@ -23,9 +23,8 @@ uart22_default: uart22_default { group1 { - psels = - ; - bias-pull-up; + psels = ; + bias-pull-up; }; group2 { diff --git a/tests/drivers/uart/uart_errors/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay index e2364f091be73..e19eff8044c4f 100644 --- a/tests/drivers/uart/uart_errors/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/uart/uart_errors/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay @@ -23,9 +23,8 @@ uart22_default: uart22_default { group1 { - psels = - ; - bias-pull-up; + psels = ; + bias-pull-up; }; group2 { diff --git a/tests/drivers/uart/uart_errors/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/nrf5340dk_nrf5340_cpuapp.overlay index 9be4328f7d19a..f5cbe0b8905c0 100644 --- a/tests/drivers/uart/uart_errors/boards/nrf5340dk_nrf5340_cpuapp.overlay +++ b/tests/drivers/uart/uart_errors/boards/nrf5340dk_nrf5340_cpuapp.overlay @@ -3,8 +3,11 @@ &pinctrl { uart1_default_alt: uart1_default_alt { group1 { - psels = , - ; + psels = ; + bias-pull-up; + }; + group2 { + psels = ; }; }; diff --git a/tests/drivers/uart/uart_errors/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/uart/uart_errors/boards/nrf54h20dk_nrf54h20_common.dtsi index 2294da14eb678..3e790d5953c4d 100644 --- a/tests/drivers/uart/uart_errors/boards/nrf54h20dk_nrf54h20_common.dtsi +++ b/tests/drivers/uart/uart_errors/boards/nrf54h20dk_nrf54h20_common.dtsi @@ -26,9 +26,8 @@ psels = ; }; group2 { - psels = - ; - bias-pull-up; + psels = ; + bias-pull-up; }; }; diff --git a/tests/drivers/uart/uart_errors/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index babbc740133f4..af6b9d31dd9cb 100644 --- a/tests/drivers/uart/uart_errors/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/tests/drivers/uart/uart_errors/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -18,9 +18,8 @@ uart22_default: uart22_default { group1 { - psels = - ; - bias-pull-up; + psels = ; + bias-pull-up; }; group2 { psels = ; diff --git a/tests/drivers/uart/uart_errors/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay index 4cc6508c1d18d..4c95c29c75cdb 100644 --- a/tests/drivers/uart/uart_errors/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay +++ b/tests/drivers/uart/uart_errors/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay @@ -18,9 +18,8 @@ uart22_default: uart22_default { group1 { - psels = - ; - bias-pull-up; + psels = ; + bias-pull-up; }; group2 { psels = ; diff --git a/tests/drivers/uart/uart_errors/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/ophelia4ev_nrf54l15_cpuapp.overlay index a1748b3784b97..12276e58abb75 100644 --- a/tests/drivers/uart/uart_errors/boards/ophelia4ev_nrf54l15_cpuapp.overlay +++ b/tests/drivers/uart/uart_errors/boards/ophelia4ev_nrf54l15_cpuapp.overlay @@ -18,9 +18,8 @@ uart22_default: uart22_default { group1 { - psels = - ; - bias-pull-up; + psels = ; + bias-pull-up; }; group2 { diff --git a/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf52_bsim.overlay b/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf52_bsim.overlay index 7799b63b73d8f..7ac2e37970496 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf52_bsim.overlay +++ b/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf52_bsim.overlay @@ -2,7 +2,6 @@ #include "nrf52840dk_nrf52840.overlay" - dut: &uart0 { current-speed = <1000000>; }; diff --git a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml index 550424dc95017..01b8e6d833a8f 100644 --- a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml +++ b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml @@ -21,10 +21,10 @@ tests: - mps2/an383 - mps2/an386 - mps2/an500 - - panb511evb/nrf54l15/cpuapp - - panb511evb/nrf54l15/cpuapp/ns - - panb511evb/nrf54l15/cpuflpr - - panb511evb/nrf54l15/cpuflpr/xip + - panb611evb/nrf54l15/cpuapp + - panb611evb/nrf54l15/cpuapp/ns + - panb611evb/nrf54l15/cpuflpr + - panb611evb/nrf54l15/cpuflpr/xip - mimxrt700_evk/mimxrt798s/cm33_cpu1 - nrf54l15dk/nrf54l15/cpuapp/ns - nrf54l15dk/nrf54l10/cpuapp/ns diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml index cbe43b7ad893c..1e6ae08b31a18 100644 --- a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml +++ b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml @@ -3,7 +3,10 @@ tests: drivers.watchdog.reset_none: - filter: dt_compat_enabled("nxp,s32-swt") or dt_compat_enabled("renesas,ra-wdt") + filter: | + dt_compat_enabled("nxp,s32-swt") + or dt_compat_enabled("renesas,ra-wdt") + or dt_compat_enabled("silabs,gecko-wdog") integration_platforms: - s32z2xxdc2/s32z270/rtu0 tags: diff --git a/tests/drivers/watchdog/wdt_error_cases/src/main.c b/tests/drivers/watchdog/wdt_error_cases/src/main.c index 935d8dd95a0fb..c1c62f7d41cf2 100644 --- a/tests/drivers/watchdog/wdt_error_cases/src/main.c +++ b/tests/drivers/watchdog/wdt_error_cases/src/main.c @@ -36,6 +36,8 @@ #define WDT_OPT_PAUSE_IN_SLEEP_SUPPORTED BIT(5) #define WDT_OPT_PAUSE_HALTED_BY_DBG_SUPPORTED BIT(6) #define WDT_FEED_CAN_STALL BIT(7) +#define WDT_WINDOW_MIN_SUPPORTED BIT(8) +#define WDT_OPT_PAUSE_IN_SLEEP_REQUIRES_PM BIT(9) /* Common for all targets: */ #define DEFAULT_WINDOW_MAX (500U) @@ -52,6 +54,21 @@ #define MAX_INSTALLABLE_TIMEOUTS (8) #define WDT_WINDOW_MAX_ALLOWED (0x07CFFFFFU) #define DEFAULT_OPTIONS (WDT_OPT_PAUSE_IN_SLEEP | WDT_OPT_PAUSE_HALTED_BY_DBG) +#elif defined(CONFIG_SOC_FAMILY_SILABS_S2) +#if defined(WDOG_CFG_EM1RUN) +#define WDT_TEST_FLAG_SLEEP_REQUIRES_PM 0 +#else +#define WDT_TEST_FLAG_SLEEP_REQUIRES_PM WDT_OPT_PAUSE_IN_SLEEP_REQUIRES_PM +#endif +#define WDT_TEST_FLAGS \ + (WDT_DISABLE_SUPPORTED | WDT_FLAG_RESET_NONE_SUPPORTED | WDT_FLAG_RESET_SOC_SUPPORTED | \ + WDT_FLAG_ONLY_ONE_TIMEOUT_VALUE_SUPPORTED | WDT_OPT_PAUSE_IN_SLEEP_SUPPORTED | \ + WDT_OPT_PAUSE_HALTED_BY_DBG_SUPPORTED | WDT_WINDOW_MIN_SUPPORTED | \ + WDT_TEST_FLAG_SLEEP_REQUIRES_PM) +#define DEFAULT_FLAGS (WDT_FLAG_RESET_NONE) +#define MAX_INSTALLABLE_TIMEOUTS (1) +#define WDT_WINDOW_MAX_ALLOWED (0x40001U) +#define DEFAULT_OPTIONS (WDT_OPT_PAUSE_IN_SLEEP | WDT_OPT_PAUSE_HALTED_BY_DBG) #else /* By default run most of the error checks. * See Readme.txt on how to align test scope for the specific target. @@ -276,12 +293,14 @@ ZTEST(wdt_coverage, test_04w_wdt_install_timeout_with_invalid_window) /* ----------------- window.min * Check that window.min can't be different than 0 */ - m_cfg_wdt0.window.min = 1U; - ret = wdt_install_timeout(wdt, &m_cfg_wdt0); - zassert_true(ret == -EINVAL, - "Calling wdt_install_timeout with window.min = 1 should return -EINVAL (-22), " - "got unexpected value of %d", - ret); + if (!(WDT_TEST_FLAGS & WDT_WINDOW_MIN_SUPPORTED)) { + m_cfg_wdt0.window.min = 1U; + ret = wdt_install_timeout(wdt, &m_cfg_wdt0); + zassert_true(ret == -EINVAL, + "Calling wdt_install_timeout with window.min = 1 should return -EINVAL (-22), " + "got unexpected value of %d", + ret); + } /* Set default window.min */ m_cfg_wdt0.window.min = DEFAULT_WINDOW_MIN; @@ -323,6 +342,11 @@ ZTEST(wdt_coverage, test_04wm_wdt_install_timeout_with_multiple_timeout_values) ztest_test_skip(); } + if (MAX_INSTALLABLE_TIMEOUTS < 2) { + /* Skip this test because two timeouts aren't supported */ + ztest_test_skip(); + } + m_cfg_wdt0.callback = NULL; m_cfg_wdt0.flags = DEFAULT_FLAGS; m_cfg_wdt0.window.max = DEFAULT_WINDOW_MAX; @@ -428,6 +452,11 @@ ZTEST(wdt_coverage, test_06b_wdt_setup_WDT_OPT_PAUSE_IN_SLEEP_functional) ztest_test_skip(); } + if ((WDT_TEST_FLAGS & WDT_OPT_PAUSE_IN_SLEEP_REQUIRES_PM) && !IS_ENABLED(CONFIG_PM)) { + /* Skip this test because WDT_OPT_PAUSE_IN_SLEEP can't be tested without PM. */ + ztest_test_skip(); + } + /* When test fails, watchdog sets m_test_06b_value to TEST_06B_TAG in WDT callback * wdt_test_06b_cb. Then, target is reset. Check value of m_test_06b_value to prevent reset * loop on this test. diff --git a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml index 438b59e927171..5325d73a88ce6 100644 --- a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml +++ b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml @@ -17,7 +17,15 @@ tests: - nrf9280pdk/nrf9280/cpurad - ophelia4ev/nrf54l15/cpuapp - raytac_an54l15q_db/nrf54l15/cpuapp + - xg24_rb4187c + - xg27_dk2602a integration_platforms: - nrf54l15dk/nrf54l15/cpuapp - ophelia4ev/nrf54l15/cpuapp - raytac_an54l15q_db/nrf54l15/cpuapp + drivers.watchdog.wdt_error_cases_pm: + platform_allow: + - xg24_rb4187c + - xg27_dk2602a + extra_configs: + - CONFIG_PM=y diff --git a/tests/drivers/watchdog/wdt_variables/src/main.c b/tests/drivers/watchdog/wdt_variables/src/main.c index e81780ea8d969..538c015c24178 100644 --- a/tests/drivers/watchdog/wdt_variables/src/main.c +++ b/tests/drivers/watchdog/wdt_variables/src/main.c @@ -88,7 +88,7 @@ int main(void) return 1; } - LOG_INF("Watchdog shall fire in ~%u miliseconds", WDT_WINDOW_MAX); + LOG_INF("Watchdog shall fire in ~%u milliseconds", WDT_WINDOW_MAX); k_sleep(K_FOREVER); } else { bool test_passing = true; diff --git a/tests/kernel/common/src/bitarray.c b/tests/kernel/common/src/bitarray.c index acac6efdf51af..668fe952d4158 100644 --- a/tests/kernel/common/src/bitarray.c +++ b/tests/kernel/common/src/bitarray.c @@ -282,6 +282,39 @@ ZTEST(bitarray, test_bitarray_set_clear) "sys_bitarray_test_and_clear_bit() erroneously changed bitarray"); } +static void test_alloc_free_32(uint32_t mask, uint32_t mask_after, size_t num_bits, + size_t exp_offset, int exp_ret) +{ + int ret; + size_t offset; + + SYS_BITARRAY_DEFINE(ba_32, 32); + + ba_32.bundles[0] = mask; + + ret = sys_bitarray_alloc(&ba_32, num_bits, &offset); + zassert_equal(ret, exp_ret, "sys_bitarray_alloc() failed: %d", ret); + if (exp_ret < 0) { + return; + } + zassert_equal(offset, exp_offset, + "sys_bitarray_alloc() offset expected %d, got %d", exp_offset, offset); + zassert_equal(ba_32.bundles[0], mask_after, "sys_bitarray_alloc() failed bits comparison"); + + ret = sys_bitarray_free(&ba_32, num_bits, offset); + zassert_equal(ret, 0, "sys_bitarray_free() failed: %d", ret); + zassert_equal(ba_32.bundles[0], mask, "sys_bitarray_alloc() failed bits comparison"); +} + +static void alloc_and_free_32_predefined(void) +{ + printk("Testing bit array alloc and free with predefined patterns using 32 bit array\n"); + + test_alloc_free_32(0x0F0F070F, 0x0F0FFF0F, 5, 11, 0); + test_alloc_free_32(0x33333333, 0xF3333333, 3, 0, -ENOSPC); + test_alloc_free_32(0x33333333, 0xF3333333, 2, 30, 0); +} + void alloc_and_free_predefined(void) { int ret; @@ -291,7 +324,7 @@ void alloc_and_free_predefined(void) SYS_BITARRAY_DEFINE(ba_128, 128); - printk("Testing bit array alloc and free with predefined patterns\n"); + printk("Testing bit array alloc and free with predefined patterns using 128 bit array\n"); /* Pre-populate the bits */ ba_128.bundles[0] = 0x0F0F070F; @@ -360,29 +393,13 @@ void alloc_and_free_predefined(void) "sys_bitarray_alloc() failed bits comparison"); } -static inline size_t count_bits(uint32_t val) -{ - /* Implements Brian Kernighan’s Algorithm - * to count bits. - */ - - size_t cnt = 0; - - while (val != 0) { - val = val & (val - 1); - cnt++; - } - - return cnt; -} - size_t get_bitarray_popcnt(sys_bitarray_t *ba) { size_t popcnt = 0; unsigned int idx; for (idx = 0; idx < ba->num_bundles; idx++) { - popcnt += count_bits(ba->bundles[idx]); + popcnt += sys_count_bits(&ba->bundles[idx], sizeof(uint32_t)); } return popcnt; @@ -514,6 +531,7 @@ ZTEST(bitarray, test_bitarray_alloc_free) } alloc_and_free_predefined(); + alloc_and_free_32_predefined(); i = 1; while (i < 65) { diff --git a/tests/kernel/device/app.overlay b/tests/kernel/device/app.overlay index 9f0bacd99efce..c2cc551848650 100644 --- a/tests/kernel/device/app.overlay +++ b/tests/kernel/device/app.overlay @@ -66,6 +66,13 @@ zephyr,deferred-init; }; + fakedeferdriver@F9000000 { + compatible = "fakedeferdriver"; + reg = <0xF9000000 0x2000>; + status = "okay"; + zephyr,deferred-init; + }; + fakedomain_0: fakedomain_0 { compatible = "fakedomain"; status = "okay"; diff --git a/tests/kernel/device/src/main.c b/tests/kernel/device/src/main.c index 6948a180862bf..2cdf8cac37e16 100644 --- a/tests/kernel/device/src/main.c +++ b/tests/kernel/device/src/main.c @@ -25,6 +25,7 @@ #define FAKEDEFERDRIVER0 DEVICE_DT_GET(DT_PATH(fakedeferdriver_e7000000)) #define FAKEDEFERDRIVER1 DEVICE_DT_GET(DT_PATH(fakedeferdriver_e8000000)) +#define FAKEDEFERDRIVER2 DEVICE_DT_GET(DT_PATH(fakedeferdriver_f9000000)) #define FAKEDRIVER0_NODEID DT_PATH(fakedriver_e0000000) #define FAKEDRIVER0_NODELABEL "fake_driver_label" @@ -43,6 +44,12 @@ DEVICE_DT_DEFINE(DT_INST(1, fakedeferdriver), NULL, NULL, NULL, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &fakedeferdriverapi); +/* fake devices used to test deferred initialization failure */ +static int fakedeferdriver_init(const struct device *dev); + +DEVICE_DT_DEFINE(DT_INST(2, fakedeferdriver), fakedeferdriver_init, NULL, NULL, NULL, POST_KERNEL, + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL); + /** * @brief Test cases to verify device objects * @@ -430,6 +437,38 @@ ZTEST(device, test_deferred_init) zassert_true(device_is_ready(FAKEDEFERDRIVER0)); } +static int fakedeferdriver_init(const struct device *dev) +{ + return -EIO; +} + +/** + * @brief Test deferred initialization error + * + * @details Verify device_init error cases and expected device states + * + * - case -errno: if the device initialization fails + * - case -EALREADY: if the device is already initialized. + * + * @see device_init + * @ingroup kernel_device_tests + */ +ZTEST(device, test_deferred_init_failure) +{ + int ret; + const struct device *dev = FAKEDEFERDRIVER2; + + zassert_false(device_is_ready(dev)); + ret = device_init(dev); + zassert_equal(ret, -EIO); + zassert_false(device_is_ready(dev)); + zassert_equal(dev->state->init_res, EIO); + + ret = device_init(dev); + zassert_equal(ret, -EALREADY); + zassert_equal(dev->state->init_res, EIO); +} + ZTEST(device, test_device_api) { const struct device *dev; diff --git a/tests/kernel/events/event_api/src/test_event_apis.c b/tests/kernel/events/event_api/src/test_event_apis.c index 818f254f40d24..b25097ddce490 100644 --- a/tests/kernel/events/event_api/src/test_event_apis.c +++ b/tests/kernel/events/event_api/src/test_event_apis.c @@ -434,6 +434,45 @@ ZTEST(events_api, test_event_receive) test_wake_multiple_threads(); } + +ZTEST(events_api, test_k_event_wait_safe) +{ + uint32_t events; + + k_event_set(&test_event, 0x73); + + events = k_event_wait_safe(&test_event, 0x11, false, K_NO_WAIT); + zexpect_equal(events, 0x11, "expected 0x11, got %x", events); + + events = k_event_wait_safe(&test_event, 0x11, false, K_NO_WAIT); + zexpect_equal(events, 0x0, "phantom events %x not removed from event object", events); + + events = k_event_wait_safe(&test_event, 0x62, false, K_NO_WAIT); + zexpect_equal(events, 0x62, "expected 0x62, got %x", events); + + events = k_event_wait_safe(&test_event, -1, false, K_NO_WAIT); + zexpect_equal(events, 0x0, "phantom events %x not removed from event object", events); +} + +ZTEST(events_api, test_k_event_wait_all_safe) +{ + uint32_t events; + + k_event_set(&test_event, 0x73); + + events = k_event_wait_all_safe(&test_event, 0x81, false, K_NO_WAIT); + zexpect_equal(events, 0x0, "expected 0x0, got %x", events); + + events = k_event_wait_all_safe(&test_event, 0x11, false, K_NO_WAIT); + zexpect_equal(events, 0x11, "expected 0x11, got %x", events); + + events = k_event_wait_all_safe(&test_event, 0x63, false, K_NO_WAIT); + zexpect_equal(events, 0x0, "expected 0x0, got %x", events); + + events = k_event_wait_all_safe(&test_event, 0x62, false, K_NO_WAIT); + zexpect_equal(events, 0x62, "expected 0x62, got %x", events); +} + /** * @} */ diff --git a/tests/kernel/fatal/exception/src/main.c b/tests/kernel/fatal/exception/src/main.c index b93aa0a60680f..048aabff103af 100644 --- a/tests/kernel/fatal/exception/src/main.c +++ b/tests/kernel/fatal/exception/src/main.c @@ -385,7 +385,7 @@ ZTEST(fatal_exception, test_fatal) #ifndef CONFIG_ARCH_POSIX -#ifdef CONFIG_STACK_SENTINEL +#if defined(CONFIG_STACK_SENTINEL) && !defined(CONFIG_HW_SHADOW_STACK) TC_PRINT("test stack sentinel overflow - timer irq\n"); check_stack_overflow(stack_sentinel_timer, 0); diff --git a/tests/kernel/fifo/fifo_api/src/test_fifo_cancel.c b/tests/kernel/fifo/fifo_api/src/test_fifo_cancel.c index daa1b46f89a10..950b0084988da 100644 --- a/tests/kernel/fifo/fifo_api/src/test_fifo_cancel.c +++ b/tests/kernel/fifo/fifo_api/src/test_fifo_cancel.c @@ -13,7 +13,7 @@ K_FIFO_DEFINE(kfifo_c); struct k_fifo fifo_c; -static K_THREAD_STACK_DEFINE(tstack, STACK_SIZE); +static K_THREAD_STACK_DEFINE(tstack_cancel, STACK_SIZE); static struct k_thread thread; static void t_cancel_wait_entry(void *p1, void *p2, void *p3) @@ -24,7 +24,7 @@ static void t_cancel_wait_entry(void *p1, void *p2, void *p3) static void tfifo_thread_thread(struct k_fifo *pfifo) { - k_tid_t tid = k_thread_create(&thread, tstack, STACK_SIZE, + k_tid_t tid = k_thread_create(&thread, tstack_cancel, STACK_SIZE, t_cancel_wait_entry, pfifo, NULL, NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT); uint32_t start_t = k_uptime_get_32(); diff --git a/tests/kernel/fifo/fifo_api/src/test_fifo_contexts.c b/tests/kernel/fifo/fifo_api/src/test_fifo_contexts.c index a50f665b25db6..32d81e78750f8 100644 --- a/tests/kernel/fifo/fifo_api/src/test_fifo_contexts.c +++ b/tests/kernel/fifo/fifo_api/src/test_fifo_contexts.c @@ -16,7 +16,7 @@ static fdata_t data[LIST_LEN]; static fdata_t data_l[LIST_LEN]; static fdata_t data_sl[LIST_LEN]; -static K_THREAD_STACK_DEFINE(tstack, STACK_SIZE); +static K_THREAD_STACK_DEFINE(tstack_contexts, STACK_SIZE); static struct k_thread tdata; static struct k_sem end_sema; @@ -88,7 +88,7 @@ static void tfifo_thread_thread(struct k_fifo *pfifo) { k_sem_init(&end_sema, 0, 1); /**TESTPOINT: thread-thread data passing via fifo*/ - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, + k_tid_t tid = k_thread_create(&tdata, tstack_contexts, STACK_SIZE, tThread_entry, pfifo, NULL, NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT); tfifo_put(pfifo); diff --git a/tests/kernel/fifo/fifo_api/src/test_fifo_loop.c b/tests/kernel/fifo/fifo_api/src/test_fifo_loop.c index 9e57dff7fec81..084ffd66e540b 100644 --- a/tests/kernel/fifo/fifo_api/src/test_fifo_loop.c +++ b/tests/kernel/fifo/fifo_api/src/test_fifo_loop.c @@ -12,7 +12,7 @@ static fdata_t data[LIST_LEN]; static struct k_fifo fifo; -static K_THREAD_STACK_DEFINE(tstack, STACK_SIZE); +static K_THREAD_STACK_DEFINE(tstack_loop, STACK_SIZE); static struct k_thread tdata; static struct k_sem end_sema; @@ -60,7 +60,7 @@ static void tfifo_read_write(struct k_fifo *pfifo) { k_sem_init(&end_sema, 0, 1); /**TESTPOINT: thread-isr-thread data passing via fifo*/ - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, + k_tid_t tid = k_thread_create(&tdata, tstack_loop, STACK_SIZE, tThread_entry, pfifo, NULL, NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT); diff --git a/tests/kernel/ipi_work/CMakeLists.txt b/tests/kernel/ipi_work/CMakeLists.txt new file mode 100644 index 0000000000000..f7e737818f4f5 --- /dev/null +++ b/tests/kernel/ipi_work/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(smp) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/kernel/ipi_work/prj.conf b/tests/kernel/ipi_work/prj.conf new file mode 100644 index 0000000000000..8d9afb748cb01 --- /dev/null +++ b/tests/kernel/ipi_work/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_SMP=y +CONFIG_IPI_OPTIMIZE=y diff --git a/tests/kernel/ipi_work/src/main.c b/tests/kernel/ipi_work/src/main.c new file mode 100644 index 0000000000000..9af35843bddc8 --- /dev/null +++ b/tests/kernel/ipi_work/src/main.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2025 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#if (CONFIG_MP_MAX_NUM_CPUS == 1) +#error "This test must have at least CONFIG_MP_MAX_NUM_CPUS=2 CPUs" +#endif + +/* structs */ + +struct test_ipi_work { + struct k_ipi_work work; + + volatile unsigned int cpu_bit; +}; + +/* forward declarations */ + +static void timer_func(struct k_timer *tmr); + +/* locals */ + +static struct test_ipi_work test_item; +static K_SEM_DEFINE(timer_sem, 0, 1); +static K_TIMER_DEFINE(timer, timer_func, NULL); +static uint32_t timer_target_cpu; + +/** + * This function is called when the IPI work item is executed on a CPU. + * It sets the CPU ID in the test_item structure to indicate which CPU + * executed the work item. + * + * @param item Pointer to the IPI work item to be executed + */ +static void test_function(struct k_ipi_work *item) +{ + struct test_ipi_work *my_work; + unsigned int cpu; + + cpu = arch_curr_cpu()->id; + + my_work = CONTAINER_OF(item, struct test_ipi_work, work); + my_work->cpu_bit = BIT(cpu); +} + +/** + * Timer function that is called to initiate the IPI work from + * an ISR and to wait for the work item to complete. + */ +static void timer_func(struct k_timer *tmr) +{ + ARG_UNUSED(tmr); + + timer_target_cpu = _current_cpu->id == 0 ? BIT(1) : BIT(0); + + /* Add the work item to the IPI queue, signal and wait */ + + k_ipi_work_add(&test_item.work, timer_target_cpu, test_function); + k_ipi_work_signal(); + while (k_ipi_work_wait(&test_item.work, K_NO_WAIT) == -EAGAIN) { + } + + /* Wake the thread waiting for the work item to complete */ + k_sem_give(&timer_sem); + +} + +/** + * This test covers the simplest working cases of IPI work + * item execution and waiting. It adds a single IPI work item + * to another CPU's queue, signals it and waits for it to complete. + * Waiting covers two scenarios + * 1. From thread level + * 2. From a k_timer (ISR). + */ +ZTEST(ipi_work, test_ipi_work_simple) +{ + unsigned int key; + unsigned int cpu_id; + unsigned int target_cpu_mask; + int status; + + k_ipi_work_init(&test_item.work); + + /* + * Issue the IPI work item from thread level. The current thread will + * pend while waiting for work completion. Interrupts are locked to + * ensure that the current thread does not change CPUs while setting + * up the IPI work item. + */ + + TC_PRINT("Thread level IPI\n"); + + key = arch_irq_lock(); + cpu_id = arch_curr_cpu()->id; + target_cpu_mask = _current_cpu->id == 0 ? BIT(1) : BIT(0); + + test_item.cpu_bit = 0xFFFFFFFFU; + k_ipi_work_add(&test_item.work, target_cpu_mask, test_function); + k_ipi_work_signal(); + arch_irq_unlock(key); + + /* Wait for the work item to complete */ + + status = k_ipi_work_wait(&test_item.work, K_FOREVER); + zassert_equal(status, 0, "k_ipi_work_wait failed: %d", status); + + zassert_equal(test_item.cpu_bit, target_cpu_mask, + "Work item was not executed on the expected CPU"); + + /* + * Issue the IPI work item from a k_timer (ISR). The k_timer will spin + * while waiting for the IPI work item to complete. + */ + + TC_PRINT("ISR level IPI\n"); + + test_item.cpu_bit = 0xFFFFFFFFU; + k_timer_start(&timer, K_TICKS(2), K_NO_WAIT); + status = k_sem_take(&timer_sem, K_SECONDS(10)); + + zassert_equal(status, 0, "k_sem_take failed: %d", status); + zassert_equal(test_item.cpu_bit, timer_target_cpu, + "Work item was not executed on the expected CPU"); +} + +ZTEST_SUITE(ipi_work, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/kernel/ipi_work/testcase.yaml b/tests/kernel/ipi_work/testcase.yaml new file mode 100644 index 0000000000000..5fd378ff7444c --- /dev/null +++ b/tests/kernel/ipi_work/testcase.yaml @@ -0,0 +1,6 @@ +tests: + kernel.ipi_work: + tags: + - kernel + - smp + filter: (CONFIG_MP_MAX_NUM_CPUS > 1) and CONFIG_SCHED_IPI_SUPPORTED diff --git a/tests/kernel/lifo/lifo_api/src/test_lifo_contexts.c b/tests/kernel/lifo/lifo_api/src/test_lifo_contexts.c index 1f32f151cc6ac..3e4ed72dd45b8 100644 --- a/tests/kernel/lifo/lifo_api/src/test_lifo_contexts.c +++ b/tests/kernel/lifo/lifo_api/src/test_lifo_contexts.c @@ -14,7 +14,7 @@ K_LIFO_DEFINE(klifo); struct k_lifo lifo; static ldata_t data[LIST_LEN]; -static K_THREAD_STACK_DEFINE(tstack, STACK_SIZE); +static K_THREAD_STACK_DEFINE(tstack_contexts, STACK_SIZE); static struct k_thread tdata; static struct k_sem end_sema; @@ -59,7 +59,7 @@ static void tlifo_thread_thread(struct k_lifo *plifo) { k_sem_init(&end_sema, 0, 1); /**TESTPOINT: thread-thread data passing via lifo*/ - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, + k_tid_t tid = k_thread_create(&tdata, tstack_contexts, STACK_SIZE, tThread_entry, plifo, NULL, NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT); tlifo_put(plifo); diff --git a/tests/kernel/lifo/lifo_api/src/test_lifo_loop.c b/tests/kernel/lifo/lifo_api/src/test_lifo_loop.c index c7e7310932c46..0f20fb3e61d89 100644 --- a/tests/kernel/lifo/lifo_api/src/test_lifo_loop.c +++ b/tests/kernel/lifo/lifo_api/src/test_lifo_loop.c @@ -12,7 +12,7 @@ static ldata_t data[LIST_LEN]; static struct k_lifo lifo; -static K_THREAD_STACK_DEFINE(tstack, STACK_SIZE); +static K_THREAD_STACK_DEFINE(tstack_loop, STACK_SIZE); static struct k_thread tdata; static struct k_sem end_sema; @@ -60,7 +60,7 @@ static void tlifo_read_write(struct k_lifo *plifo) { k_sem_init(&end_sema, 0, 1); /**TESTPOINT: thread-isr-thread data passing via lifo*/ - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, + k_tid_t tid = k_thread_create(&tdata, tstack_loop, STACK_SIZE, tThread_entry, plifo, NULL, NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT); diff --git a/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny.overlay b/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny.overlay index 60f3c0c4b71d1..f08d26a1ecc3e 100644 --- a/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny.overlay +++ b/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny.overlay @@ -1,3 +1,3 @@ &dram0 { - reg = < 0x100000 0x50000 >; + reg = <0x100000 0x50000>; }; diff --git a/tests/kernel/pipe/deprecated/pipe/prj.conf b/tests/kernel/pipe/deprecated/pipe/prj.conf deleted file mode 100644 index 97ef605d171f4..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe/prj.conf +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_ZTEST=y -CONFIG_TEST_USERSPACE=y -CONFIG_MP_MAX_NUM_CPUS=1 -CONFIG_TIMESLICE_SIZE=0 -CONFIG_PIPES=y -CONFIG_DEPRECATION_TEST=y diff --git a/tests/kernel/pipe/deprecated/pipe/src/main.c b/tests/kernel/pipe/deprecated/pipe/src/main.c deleted file mode 100644 index b0f495137bc6c..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe/src/main.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -extern struct k_pipe test_pipe; -extern struct k_pipe small_pipe; -extern struct k_sem put_sem, get_sem, sync_sem, multiple_send_sem; -extern struct k_stack stack_1; -extern struct k_thread get_single_tid; - -static void *pipe_setup(void) -{ - k_thread_access_grant(k_current_get(), - &test_pipe, &small_pipe, &put_sem, &get_sem, - &sync_sem, &multiple_send_sem, - &get_single_tid, &stack_1); - - return NULL; -} - -ZTEST_SUITE(pipe, NULL, pipe_setup, NULL, NULL, NULL); diff --git a/tests/kernel/pipe/deprecated/pipe/src/test_pipe.c b/tests/kernel/pipe/deprecated/pipe/src/test_pipe.c deleted file mode 100644 index 4ad9ee230a457..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe/src/test_pipe.c +++ /dev/null @@ -1,1160 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#include - -/** - * @brief Define and initialize test_pipe at compile time - */ -K_PIPE_DEFINE(test_pipe, 256, 4); -#define STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE) -#define PIPE_SIZE (256) - -K_PIPE_DEFINE(small_pipe, 10, 4); - -K_THREAD_STACK_DEFINE(stack_1, STACK_SIZE); - -K_SEM_DEFINE(get_sem, 0, 1); -K_SEM_DEFINE(put_sem, 1, 1); -K_SEM_DEFINE(sync_sem, 0, 1); -K_SEM_DEFINE(multiple_send_sem, 0, 1); - -ZTEST_BMEM uint8_t tx_buffer[PIPE_SIZE + 1]; -ZTEST_BMEM uint8_t rx_buffer[PIPE_SIZE + 1]; - -#define TOTAL_ELEMENTS (sizeof(single_elements) / sizeof(struct pipe_sequence)) -#define TOTAL_WAIT_ELEMENTS (sizeof(wait_elements) / \ - sizeof(struct pipe_sequence)) -#define TOTAL_TIMEOUT_ELEMENTS (sizeof(timeout_elements) / \ - sizeof(struct pipe_sequence)) - -/* Minimum tx/rx size*/ -/* the pipe will always pass */ -#define NO_CONSTRAINT (0U) - -/* Pipe will at least put one byte */ -#define ATLEAST_1 (1U) - -/* Pipe must put all data on the buffer */ -#define ALL_BYTES (sizeof(tx_buffer)) - -#define RETURN_SUCCESS (0) -#define TIMEOUT_VAL (K_MSEC(10)) -#define TIMEOUT_200MSEC (K_MSEC(200)) - -/* encompassing structs */ -struct pipe_sequence { - uint32_t size; - uint32_t min_size; - uint32_t sent_bytes; - int return_value; -}; - -static const struct pipe_sequence single_elements[] = { - { 0, ALL_BYTES, 0, 0 }, - { 1, ALL_BYTES, 1, RETURN_SUCCESS }, - { PIPE_SIZE - 1, ALL_BYTES, PIPE_SIZE - 1, RETURN_SUCCESS }, - { PIPE_SIZE, ALL_BYTES, PIPE_SIZE, RETURN_SUCCESS }, - { PIPE_SIZE + 1, ALL_BYTES, 0, -EIO }, - /* minimum 1 byte */ - /* {0, ATLEAST_1, 0, -EIO}, */ - { 1, ATLEAST_1, 1, RETURN_SUCCESS }, - { PIPE_SIZE - 1, ATLEAST_1, PIPE_SIZE - 1, RETURN_SUCCESS }, - { PIPE_SIZE, ATLEAST_1, PIPE_SIZE, RETURN_SUCCESS }, - { PIPE_SIZE + 1, ATLEAST_1, PIPE_SIZE, RETURN_SUCCESS }, - /* /\* any number of bytes *\/ */ - { 0, NO_CONSTRAINT, 0, 0 }, - { 1, NO_CONSTRAINT, 1, RETURN_SUCCESS }, - { PIPE_SIZE - 1, NO_CONSTRAINT, PIPE_SIZE - 1, RETURN_SUCCESS }, - { PIPE_SIZE, NO_CONSTRAINT, PIPE_SIZE, RETURN_SUCCESS }, - { PIPE_SIZE + 1, NO_CONSTRAINT, PIPE_SIZE, RETURN_SUCCESS } -}; - -static const struct pipe_sequence multiple_elements[] = { - { PIPE_SIZE / 3, ALL_BYTES, PIPE_SIZE / 3, RETURN_SUCCESS, }, - { PIPE_SIZE / 3, ALL_BYTES, PIPE_SIZE / 3, RETURN_SUCCESS, }, - { PIPE_SIZE / 3, ALL_BYTES, PIPE_SIZE / 3, RETURN_SUCCESS, }, - { PIPE_SIZE / 3, ALL_BYTES, 0, -EIO }, - - { PIPE_SIZE / 3, ATLEAST_1, PIPE_SIZE / 3, RETURN_SUCCESS }, - { PIPE_SIZE / 3, ATLEAST_1, PIPE_SIZE / 3, RETURN_SUCCESS }, - { PIPE_SIZE / 3, ATLEAST_1, PIPE_SIZE / 3, RETURN_SUCCESS }, - { PIPE_SIZE / 3, ATLEAST_1, 1, RETURN_SUCCESS }, - { PIPE_SIZE / 3, ATLEAST_1, 0, -EIO }, - - { PIPE_SIZE / 3, NO_CONSTRAINT, PIPE_SIZE / 3, RETURN_SUCCESS }, - { PIPE_SIZE / 3, NO_CONSTRAINT, PIPE_SIZE / 3, RETURN_SUCCESS }, - { PIPE_SIZE / 3, NO_CONSTRAINT, PIPE_SIZE / 3, RETURN_SUCCESS }, - { PIPE_SIZE / 3, NO_CONSTRAINT, 1, RETURN_SUCCESS }, - { PIPE_SIZE / 3, NO_CONSTRAINT, 0, RETURN_SUCCESS } -}; - -static const struct pipe_sequence wait_elements[] = { - { 1, ALL_BYTES, 1, RETURN_SUCCESS }, - { PIPE_SIZE - 1, ALL_BYTES, PIPE_SIZE - 1, RETURN_SUCCESS }, - { PIPE_SIZE, ALL_BYTES, PIPE_SIZE, RETURN_SUCCESS }, - { PIPE_SIZE + 1, ALL_BYTES, PIPE_SIZE + 1, RETURN_SUCCESS }, - - { PIPE_SIZE - 1, ATLEAST_1, PIPE_SIZE - 1, RETURN_SUCCESS }, -}; - -static const struct pipe_sequence timeout_elements[] = { - { 0, ALL_BYTES, 0, 0 }, - { 1, ALL_BYTES, 0, -EAGAIN }, - { PIPE_SIZE - 1, ALL_BYTES, 0, -EAGAIN }, - { PIPE_SIZE, ALL_BYTES, 0, -EAGAIN }, - { PIPE_SIZE + 1, ALL_BYTES, 0, -EAGAIN }, - - { 1, ATLEAST_1, 0, -EAGAIN }, - { PIPE_SIZE - 1, ATLEAST_1, 0, -EAGAIN }, - { PIPE_SIZE, ATLEAST_1, 0, -EAGAIN }, - { PIPE_SIZE + 1, ATLEAST_1, 0, -EAGAIN } -}; - -struct k_thread get_single_tid; - -/* Helper functions */ - -uint32_t rx_buffer_check(char *buffer, uint32_t size) -{ - uint32_t index; - - for (index = 0U; index < size; index++) { - if (buffer[index] != (char) index) { - printk("buffer[index] = %d index = %d\n", - buffer[index], (char) index); - return index; - } - } - - return size; -} - - -/******************************************************************************/ -void pipe_put_single(void) -{ - uint32_t index; - size_t written; - int return_value; - size_t min_xfer; - - for (index = 0U; index < TOTAL_ELEMENTS; index++) { - k_sem_take(&put_sem, K_FOREVER); - - min_xfer = (single_elements[index].min_size == ALL_BYTES ? - single_elements[index].size : - single_elements[index].min_size); - - return_value = k_pipe_put(&test_pipe, &tx_buffer, - single_elements[index].size, &written, - min_xfer, K_NO_WAIT); - - zassert_true((return_value == - single_elements[index].return_value), - " Return value of k_pipe_put mismatch at index = %d expected =%d received = %d\n", - index, - single_elements[index].return_value, return_value); - - zassert_true((written == single_elements[index].sent_bytes), - "Bytes written mismatch written is %d but expected is %d index = %d\n", - written, - single_elements[index].sent_bytes, index); - - k_sem_give(&get_sem); - } - -} - -void pipe_get_single(void *p1, void *p2, void *p3) -{ - uint32_t index; - size_t read; - int return_value; - size_t min_xfer; - - for (index = 0U; index < TOTAL_ELEMENTS; index++) { - k_sem_take(&get_sem, K_FOREVER); - - /* reset the rx buffer for the next interation */ - (void)memset(rx_buffer, 0, sizeof(rx_buffer)); - - min_xfer = (single_elements[index].min_size == ALL_BYTES ? - single_elements[index].size : - single_elements[index].min_size); - - return_value = k_pipe_get(&test_pipe, &rx_buffer, - single_elements[index].size, &read, - min_xfer, K_NO_WAIT); - - - zassert_true((return_value == - single_elements[index].return_value), - "Return value of k_pipe_get mismatch at index = %d expected =%d received = %d\n", - index, single_elements[index].return_value, - return_value); - - zassert_true((read == single_elements[index].sent_bytes), - "Bytes read mismatch read is %d but expected is %d index = %d\n", - read, single_elements[index].sent_bytes, index); - - zassert_true(rx_buffer_check(rx_buffer, read) == read, - "Bytes read are not matching at index= %d\n expected =%d but received= %d", - index, read, rx_buffer_check(rx_buffer, read)); - k_sem_give(&put_sem); - } - k_sem_give(&sync_sem); -} - -/******************************************************************************/ -void pipe_put_multiple(void) -{ - uint32_t index; - size_t written; - int return_value; - size_t min_xfer; - - for (index = 0U; index < TOTAL_ELEMENTS; index++) { - - min_xfer = (multiple_elements[index].min_size == ALL_BYTES ? - multiple_elements[index].size : - multiple_elements[index].min_size); - - return_value = k_pipe_put(&test_pipe, &tx_buffer, - multiple_elements[index].size, - &written, - min_xfer, K_NO_WAIT); - - zassert_true((return_value == - multiple_elements[index].return_value), - "Return value of k_pipe_put mismatch at index = %d expected =%d received = %d\n", - index, - multiple_elements[index].return_value, - return_value); - - zassert_true((written == multiple_elements[index].sent_bytes), - "Bytes written mismatch written is %d but expected is %d index = %d\n", - written, - multiple_elements[index].sent_bytes, index); - if (return_value != RETURN_SUCCESS) { - k_sem_take(&multiple_send_sem, K_FOREVER); - } - - } - -} - -void pipe_get_multiple(void *p1, void *p2, void *p3) -{ - uint32_t index; - size_t read; - int return_value; - size_t min_xfer; - - for (index = 0U; index < TOTAL_ELEMENTS; index++) { - - - /* reset the rx buffer for the next interation */ - (void)memset(rx_buffer, 0, sizeof(rx_buffer)); - - min_xfer = (multiple_elements[index].min_size == ALL_BYTES ? - multiple_elements[index].size : - multiple_elements[index].min_size); - - return_value = k_pipe_get(&test_pipe, &rx_buffer, - multiple_elements[index].size, &read, - min_xfer, K_NO_WAIT); - - - zassert_true((return_value == - multiple_elements[index].return_value), - "Return value of k_pipe_get mismatch at index = %d expected =%d received = %d\n", - index, multiple_elements[index].return_value, - return_value); - - zassert_true((read == multiple_elements[index].sent_bytes), - "Bytes read mismatch read is %d but expected is %d index = %d\n", - read, multiple_elements[index].sent_bytes, index); - - zassert_true(rx_buffer_check(rx_buffer, read) == read, - "Bytes read are not matching at index= %d\n expected =%d but received= %d", - index, read, rx_buffer_check(rx_buffer, read)); - - if (return_value != RETURN_SUCCESS) { - k_sem_give(&multiple_send_sem); - } - - } - k_sem_give(&sync_sem); -} - -/******************************************************************************/ - -void pipe_put_forever_wait(void) -{ - size_t written; - int return_value; - - /* 1. fill the pipe. */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, K_FOREVER); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_put failed expected = 0 received = %d\n", - return_value); - - zassert_true(written == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); - - - /* wake up the get task */ - k_sem_give(&get_sem); - /* 2. k_pipe_put() will force a context switch to the other thread. */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, K_FOREVER); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_put failed expected = 0 received = %d\n", - return_value); - - zassert_true(written == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); - - /* 3. k_pipe_put() will force a context switch to the other thread. */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - ATLEAST_1, K_FOREVER); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_put failed expected = 0 received = %d\n", - return_value); - - zassert_true(written == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); - -} - - -void pipe_get_forever_wait(void *pi, void *p2, void *p3) -{ - size_t read; - int return_value; - - /* get blocked until put forces the execution to come here */ - k_sem_take(&get_sem, K_FOREVER); - - /* k_pipe_get will force a context switch to the put function. */ - return_value = k_pipe_get(&test_pipe, &rx_buffer, - PIPE_SIZE, &read, - PIPE_SIZE, K_FOREVER); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_get failed expected = 0 received = %d\n", - return_value); - - zassert_true(read == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, read); - - /* k_pipe_get will force a context switch to the other thread. */ - return_value = k_pipe_get(&test_pipe, &rx_buffer, - PIPE_SIZE, &read, - ATLEAST_1, K_FOREVER); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_get failed expected = 0 received = %d\n", - return_value); - - zassert_true(read == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, read); - - /*3. last read to clear the pipe */ - return_value = k_pipe_get(&test_pipe, &rx_buffer, - PIPE_SIZE, &read, - ATLEAST_1, K_FOREVER); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_get failed expected = 0 received = %d\n", - return_value); - - zassert_true(read == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, read); - - - k_sem_give(&sync_sem); - -} - - -/******************************************************************************/ -void pipe_put_timeout(void) -{ - size_t written; - int return_value; - - /* 1. fill the pipe. */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, TIMEOUT_VAL); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_put failed expected = 0 received = %d\n", - return_value); - - zassert_true(written == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); - - - /* pipe put cant be satisfied and thus timeout */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, TIMEOUT_VAL); - - zassert_true(return_value == -EAGAIN, - "k_pipe_put failed expected = -EAGAIN received = %d\n", - return_value); - - zassert_true(written == 0, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); - - /* Try once more with 1 byte pipe put cant be satisfied and - * thus timeout. - */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - ATLEAST_1, TIMEOUT_VAL); - - zassert_true(return_value == -EAGAIN, - "k_pipe_put failed expected = -EAGAIN received = %d\n", - return_value); - - zassert_true(written == 0, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); - - k_sem_give(&get_sem); - - /* 2. pipe_get thread will now accept this data */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, TIMEOUT_VAL); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_put failed expected = 0 received = %d\n", - return_value); - - zassert_true(written == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); - - /* 3. pipe_get thread will now accept this data */ - return_value = k_pipe_put(&test_pipe, &tx_buffer, - PIPE_SIZE, &written, - ATLEAST_1, TIMEOUT_VAL); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_put failed expected = 0 received = %d\n", - return_value); - - zassert_true(written == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, written); -} - - -void pipe_get_timeout(void *pi, void *p2, void *p3) -{ - size_t read; - int return_value; - - /* get blocked until put forces the execution to come here */ - k_sem_take(&get_sem, K_FOREVER); - - /* k_pipe_get will do a context switch to the put function. */ - return_value = k_pipe_get(&test_pipe, &rx_buffer, - PIPE_SIZE, &read, - PIPE_SIZE, TIMEOUT_VAL); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_get failed expected = 0 received = %d\n", - return_value); - - zassert_true(read == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, read); - - /* k_pipe_get will do a context switch to the put function. */ - return_value = k_pipe_get(&test_pipe, &rx_buffer, - PIPE_SIZE, &read, - ATLEAST_1, TIMEOUT_VAL); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_get failed expected = 0 received = %d\n", - return_value); - - zassert_true(read == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, read); - - /* cleanup the pipe */ - return_value = k_pipe_get(&test_pipe, &rx_buffer, - PIPE_SIZE, &read, - ATLEAST_1, TIMEOUT_VAL); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_get failed expected = 0 received = %d\n", - return_value); - - zassert_true(read == PIPE_SIZE, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, read); - - k_sem_give(&sync_sem); -} - - -/******************************************************************************/ -void pipe_get_on_empty_pipe(void) -{ - size_t read; - int return_value; - uint32_t read_size; - uint32_t size_array[] = { 1, PIPE_SIZE - 1, PIPE_SIZE, PIPE_SIZE + 1 }; - - for (int i = 0; i < 4; i++) { - read_size = size_array[i]; - return_value = k_pipe_get(&test_pipe, &rx_buffer, - read_size, &read, - read_size, K_NO_WAIT); - - zassert_true(return_value == -EIO, - "k_pipe_get failed expected = -EIO received = %d\n", - return_value); - - return_value = k_pipe_get(&test_pipe, &rx_buffer, - read_size, &read, - ATLEAST_1, K_NO_WAIT); - - zassert_true(return_value == -EIO, - "k_pipe_get failed expected = -EIO received = %d\n", - return_value); - - return_value = k_pipe_get(&test_pipe, &rx_buffer, - read_size, &read, - NO_CONSTRAINT, K_NO_WAIT); - - zassert_true(return_value == RETURN_SUCCESS, - "k_pipe_get failed expected = 0 received = %d\n", - return_value); - - zassert_true(read == 0, - "k_pipe_put written failed expected = %d received = %d\n", - PIPE_SIZE, read); - } - -} - - -/******************************************************************************/ -void pipe_put_forever_timeout(void) -{ - uint32_t index; - size_t written; - int return_value; - size_t min_xfer; - - /* using this to synchronize the 2 threads */ - k_sem_take(&put_sem, K_FOREVER); - - for (index = 0U; index < TOTAL_WAIT_ELEMENTS; index++) { - - min_xfer = (wait_elements[index].min_size == ALL_BYTES ? - wait_elements[index].size : - wait_elements[index].min_size); - - return_value = k_pipe_put(&test_pipe, &tx_buffer, - wait_elements[index].size, &written, - min_xfer, K_FOREVER); - - zassert_true((return_value == - wait_elements[index].return_value), - "Return value of k_pipe_put mismatch at index = %d expected =%d received = %d\n", - index, wait_elements[index].return_value, - return_value); - - zassert_true((written == wait_elements[index].sent_bytes), - "Bytes written mismatch written is %d but expected is %d index = %d\n", - written, wait_elements[index].sent_bytes, index); - - } - -} - -void pipe_get_forever_timeout(void *p1, void *p2, void *p3) -{ - uint32_t index; - size_t read; - int return_value; - size_t min_xfer; - - /* using this to synchronize the 2 threads */ - k_sem_give(&put_sem); - for (index = 0U; index < TOTAL_WAIT_ELEMENTS; index++) { - - min_xfer = (wait_elements[index].min_size == ALL_BYTES ? - wait_elements[index].size : - wait_elements[index].min_size); - - return_value = k_pipe_get(&test_pipe, &rx_buffer, - wait_elements[index].size, &read, - min_xfer, K_FOREVER); - - - zassert_true((return_value == - wait_elements[index].return_value), - "Return value of k_pipe_get mismatch at index = %d expected =%d received = %d\n", - index, wait_elements[index].return_value, - return_value); - - zassert_true((read == wait_elements[index].sent_bytes), - "Bytes read mismatch read is %d but expected is %d index = %d\n", - read, wait_elements[index].sent_bytes, index); - - - } - k_sem_give(&sync_sem); -} - -/******************************************************************************/ -void pipe_put_get_timeout(void) -{ - uint32_t index; - size_t read; - int return_value; - size_t min_xfer; - - for (index = 0U; index < TOTAL_TIMEOUT_ELEMENTS; index++) { - - min_xfer = (timeout_elements[index].min_size == ALL_BYTES ? - timeout_elements[index].size : - timeout_elements[index].min_size); - - return_value = k_pipe_get(&test_pipe, &rx_buffer, - timeout_elements[index].size, &read, - min_xfer, TIMEOUT_200MSEC); - - - zassert_true((return_value == - timeout_elements[index].return_value), - "Return value of k_pipe_get mismatch at index = %d expected =%d received = %d\n", - index, timeout_elements[index].return_value, - return_value); - - zassert_true((read == timeout_elements[index].sent_bytes), - "Bytes read mismatch read is %d but expected is %d index = %d\n", - read, timeout_elements[index].sent_bytes, index); - - - } - -} - -/******************************************************************************/ -ZTEST_BMEM bool valid_fault; -void k_sys_fatal_error_handler(unsigned int reason, const struct arch_esf *pEsf) -{ - printk("Caught system error -- reason %d\n", reason); - if (valid_fault) { - valid_fault = false; /* reset back to normal */ - ztest_test_pass(); - } else { - TC_END_REPORT(TC_FAIL); - k_fatal_halt(reason); - } -} -/******************************************************************************/ -/* Test case entry points */ - -/** - * @brief Verify pipe with 1 element insert. - * - * @ingroup kernel_pipe_tests - * - * @details - * Test Objective: - * - transfer sequences of bytes of data in whole. - * - * Testing techniques: - * - function and block box testing,Interface testing, - * Dynamic analysis and testing. - * - * Prerequisite Conditions: - * - CONFIG_TEST_USERSPACE. - * - * Input Specifications: - * - N/A - * - * Test Procedure: - * -# Define and initialize a pipe at compile time. - * -# Using a sub thread to get pipe data in whole, - * and check if the data is correct with expected. - * -# Using main thread to put data in whole, - * check if the return is correct with expected. - * - * Expected Test Result: - * - The pipe put/get whole data is correct. - * - * Pass/Fail Criteria: - * - Successful if check points in test procedure are all passed, otherwise failure. - * - * Assumptions and Constraints: - * - N/A - * - * @see k_pipe_put(), k_pipe_get() - */ -ZTEST_USER(pipe, test_pipe_on_single_elements) -{ - /* initialize the tx buffer */ - for (int i = 0; i < sizeof(tx_buffer); i++) { - tx_buffer[i] = i; - } - - k_thread_create(&get_single_tid, stack_1, STACK_SIZE, - pipe_get_single, NULL, NULL, NULL, - K_PRIO_PREEMPT(0), K_INHERIT_PERMS | K_USER, - K_NO_WAIT); - - pipe_put_single(); - k_sem_take(&sync_sem, K_FOREVER); - k_thread_abort(&get_single_tid); - ztest_test_pass(); -} - -/** - * @brief Test when multiple items are present in the pipe - * @details transfer sequences of bytes of data in part. - * - Using a sub thread to get data part. - * - Using main thread to put data part by part - * @ingroup kernel_pipe_tests - * @see k_pipe_put() - */ -ZTEST_USER(pipe, test_pipe_on_multiple_elements) -{ - k_thread_create(&get_single_tid, stack_1, STACK_SIZE, - pipe_get_multiple, NULL, NULL, NULL, - K_PRIO_PREEMPT(0), K_INHERIT_PERMS | K_USER, - K_NO_WAIT); - - pipe_put_multiple(); - k_sem_take(&sync_sem, K_FOREVER); - k_thread_abort(&get_single_tid); - ztest_test_pass(); -} - -/** - * @brief Test when multiple items are present with wait - * @ingroup kernel_pipe_tests - * @see k_pipe_put() - */ -ZTEST_USER(pipe, test_pipe_forever_wait) -{ - k_thread_create(&get_single_tid, stack_1, STACK_SIZE, - pipe_get_forever_wait, NULL, NULL, NULL, - K_PRIO_PREEMPT(0), K_INHERIT_PERMS | K_USER, - K_NO_WAIT); - - pipe_put_forever_wait(); - k_sem_take(&sync_sem, K_FOREVER); - k_thread_abort(&get_single_tid); - ztest_test_pass(); -} - -/** - * @brief Test pipes with timeout - * - * @ingroup kernel_pipe_tests - * - * @details - * Test Objective: - * - Check if the kernel support supplying a timeout parameter - * indicating the maximum amount of time a process will wait. - * - * Testing techniques: - * - function and block box testing,Interface testing, - * Dynamic analysis and testing. - * - * Prerequisite Conditions: - * - CONFIG_TEST_USERSPACE. - * - * Input Specifications: - * - N/A - * - * Test Procedure: - * -# Create a sub thread to get data from a pipe. - * -# In the sub thread, Set K_MSEC(10) as timeout for k_pipe_get(). - * and check the data which get from pipe if correct. - * -# In main thread, use k_pipe_put to put data. - * and check the return of k_pipe_put. - * - * Expected Test Result: - * - The pipe can set timeout and works well. - * - * Pass/Fail Criteria: - * - Successful if check points in test procedure are all passed, otherwise failure. - * - * Assumptions and Constraints: - * - N/A - * - * @see k_pipe_put() - */ -ZTEST_USER(pipe, test_pipe_timeout) -{ - k_thread_create(&get_single_tid, stack_1, STACK_SIZE, - pipe_get_timeout, NULL, NULL, NULL, - K_PRIO_PREEMPT(0), K_INHERIT_PERMS | K_USER, - K_NO_WAIT); - - pipe_put_timeout(); - k_sem_take(&sync_sem, K_FOREVER); - k_thread_abort(&get_single_tid); - ztest_test_pass(); -} - -/** - * @brief Test pipe get from a empty pipe - * @ingroup kernel_pipe_tests - * @see k_pipe_get() - */ -ZTEST_USER(pipe, test_pipe_get_on_empty_pipe) -{ - pipe_get_on_empty_pipe(); - ztest_test_pass(); -} - -/** - * @brief Test the pipe_get with K_FOREVER as timeout. - * @details Testcase is similar to test_pipe_on_single_elements() - * but with K_FOREVER as timeout. - * @ingroup kernel_pipe_tests - * @see k_pipe_put() - */ -ZTEST_USER(pipe, test_pipe_forever_timeout) -{ - k_thread_priority_set(k_current_get(), K_PRIO_PREEMPT(0)); - - k_thread_create(&get_single_tid, stack_1, STACK_SIZE, - pipe_get_forever_timeout, NULL, NULL, NULL, - K_PRIO_PREEMPT(0), K_INHERIT_PERMS | K_USER, - K_NO_WAIT); - - pipe_put_forever_timeout(); - k_sem_take(&sync_sem, K_FOREVER); - ztest_test_pass(); -} - -/** - * @brief k_pipe_get timeout test - * @ingroup kernel_pipe_tests - * @see k_pipe_get() - */ -ZTEST_USER(pipe, test_pipe_get_timeout) -{ - pipe_put_get_timeout(); - - ztest_test_pass(); -} - -/** - * @brief Test pipe get of invalid size - * @ingroup kernel_pipe_tests - * @see k_pipe_get() - */ -ZTEST_USER(pipe, test_pipe_get_invalid_size) -{ - size_t read; - int ret; - - valid_fault = true; - ret = k_pipe_get(&test_pipe, &rx_buffer, - 0, &read, - 1, TIMEOUT_200MSEC); - - zassert_equal(ret, -EINVAL, - "fault didn't occur for min_xfer <= bytes_to_read"); -} - -/** - * @brief Test pipe get returns immediately if >= min_xfer is available - * @ingroup kernel_pipe_tests - * @see k_pipe_get() - */ -ZTEST_USER(pipe, test_pipe_get_min_xfer) -{ - int res; - size_t bytes_written = 0; - size_t bytes_read = 0; - char buf[8] = {}; - - res = k_pipe_put(&test_pipe, "Hi!", 3, &bytes_written, - 3 /* min_xfer */, K_FOREVER); - zassert_equal(res, 0, "did not write entire message"); - zassert_equal(bytes_written, 3, "did not write entire message"); - - res = k_pipe_get(&test_pipe, buf, sizeof(buf), &bytes_read, - 1 /* min_xfer */, K_FOREVER); - zassert_equal(res, 0, "did not read at least one byte"); - zassert_equal(bytes_read, 3, "did not read all bytes available"); -} - -/** - * @brief Test pipe put returns immediately if >= min_xfer is available - * @ingroup kernel_pipe_tests - * @see k_pipe_put() - */ -ZTEST_USER(pipe, test_pipe_put_min_xfer) -{ - int res; - size_t bytes_written = 0; - - /* write 6 bytes into the pipe, so that 2 bytes are still free */ - for (size_t i = 0; i < 2; ++i) { - bytes_written = 0; - res = k_pipe_put(&test_pipe, "Hi!", 3, &bytes_written, - 3 /* min_xfer */, K_FOREVER); - zassert_equal(res, 0, "did not write entire message"); - zassert_equal(bytes_written, 3, "did not write entire message"); - } - - /* attempt to write 3 bytes, but allow success if >= 1 byte */ - bytes_written = 0; - res = k_pipe_put(&test_pipe, "Hi!", 3, &bytes_written, - 1 /* min_xfer */, K_FOREVER); - zassert_equal(res, 0, "did not write min_xfer"); - zassert_true(bytes_written >= 1, "did not write min_xfer"); - - /* flush the pipe so other test can write to this pipe */ - k_pipe_flush(&test_pipe); -} - -/** - * @brief Test defining and initializing pipes at run time - * - * @ingroup kernel_pipe_tests - * - * @details - * Test Objective: - * - Check if the kernel provided a mechanism for defining and - * initializing pipes at run time. - * - * Testing techniques: - * - function and block box testing,Interface testing, - * Dynamic analysis and testing. - * - * Prerequisite Conditions: - * - CONFIG_TEST_USERSPACE. - * - * Input Specifications: - * - N/A - * - * Test Procedure: - * -# Define and initialize a pipe at run time - * -# Using this pipe to transfer data. - * -# Check the pipe get/put operation. - * - * Expected Test Result: - * - Pipe can be defined and initialized at run time. - * - * Pass/Fail Criteria: - * - Successful if check points in test procedure are all passed, otherwise failure. - * - * Assumptions and Constraints: - * - N/A - * - * @see k_pipe_init() - */ -ZTEST(pipe, test_pipe_define_at_runtime) -{ - unsigned char ring_buffer[PIPE_SIZE]; - struct k_pipe pipe; - size_t written, read; - - /*Define and initialize pipe at run time*/ - k_pipe_init(&pipe, ring_buffer, sizeof(ring_buffer)); - - /* initialize the tx buffer */ - for (int i = 0; i < sizeof(tx_buffer); i++) { - tx_buffer[i] = i; - } - - /*Using test_pipe which define and initialize at run time*/ - zassert_equal(k_pipe_put(&pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, K_NO_WAIT), RETURN_SUCCESS, NULL); - - /* Returned without waiting; zero data bytes were written. */ - zassert_equal(k_pipe_put(&pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, K_NO_WAIT), -EIO, NULL); - - /* Waiting period timed out. */ - zassert_equal(k_pipe_put(&pipe, &tx_buffer, - PIPE_SIZE, &written, - PIPE_SIZE, TIMEOUT_VAL), -EAGAIN, NULL); - - zassert_equal(k_pipe_get(&pipe, &rx_buffer, - PIPE_SIZE, &read, - PIPE_SIZE, K_NO_WAIT), RETURN_SUCCESS, NULL); - - zassert_true(rx_buffer_check(rx_buffer, read) == read, - "Bytes read are not match."); - - /* Returned without waiting; zero data bytes were read. */ - zassert_equal(k_pipe_get(&pipe, &rx_buffer, - PIPE_SIZE, &read, - PIPE_SIZE, K_NO_WAIT), -EIO, NULL); - /* Waiting period timed out. */ - zassert_equal(k_pipe_get(&pipe, &rx_buffer, - PIPE_SIZE, &read, - PIPE_SIZE, TIMEOUT_VAL), -EAGAIN, NULL); -} - -/** - * @brief Helper thread to test k_pipe_flush() and k_pipe_buffer_flush() - * - * This helper thread attempts to write 50 bytes to the pipe identified by - * [p1], which has an internal buffer size of 10. This helper thread is - * expected to fill the internal buffer, and then block until it can complete - * the write. - */ -void test_pipe_flush_helper(void *p1, void *p2, void *p3) -{ - struct k_pipe *pipe = (struct k_pipe *)p1; - char buffer[50]; - size_t i; - size_t bytes_written; - int rv; - - for (i = 0; i < sizeof(buffer); i++) { - buffer[i] = i; - } - - rv = k_pipe_put(pipe, buffer, sizeof(buffer), &bytes_written, - sizeof(buffer), K_FOREVER); - - zassert_true(rv == 0, "k_pipe_put() failed with %d", rv); - zassert_true(bytes_written == sizeof(buffer), - "Expected %zu bytes written, not %zu", - sizeof(buffer), bytes_written); -} - -/** - * @brief Test flushing a pipe - * - * @ingroup kernel_pipe_tests - * - * @details - * Test Objective: - * - Check if the kernel flushes a pipe properly at runtime. - * - * Testing techniques: - * - function and block box testing,Interface testing, - * Dynamic analysis and testing. - * - * Prerequisite Conditions: - * - CONFIG_TEST_USERSPACE. - * - * Input Specifications: - * - N/A - * - * Test Procedure: - * -# Define and initialize a pipe at run time - * -# Use this pipe to transfer data. - * -# Have a thread fill and block on writing to the pipe - * -# Flush the pipe and check that the pipe is completely empty - * -# Have a thread fill and block on writing to the pipe - * -# Flush only the pipe's buffer and check the results - * - * Expected Test Result: - * - Reading from the pipe after k_pipe_flush() results in no data to read. - * - Reading from the pipe after k_pipe_buffer_flush() results in read data, - * but missing the original data that was in the buffer prior to the flush. - * - * Pass/Fail Criteria: - * - Successful if check points in test procedure are all passed, otherwise - * failure. - * - * Assumptions and Constraints: - * - N/A - */ -ZTEST(pipe, test_pipe_flush) -{ - unsigned char results_buffer[50]; - size_t bytes_read; - size_t i; - int rv; - - memset(results_buffer, 0, sizeof(results_buffer)); - - (void)k_thread_create(&get_single_tid, stack_1, STACK_SIZE, - test_pipe_flush_helper, &small_pipe, NULL, NULL, - K_PRIO_PREEMPT(0), K_INHERIT_PERMS | K_USER, - K_NO_WAIT); - - k_sleep(K_MSEC(50)); /* give helper thread time to execute */ - - /* Completely flush the pipe */ - - k_pipe_flush(&small_pipe); - - rv = k_pipe_get(&small_pipe, results_buffer, sizeof(results_buffer), - &bytes_read, 0, K_MSEC(100)); - - zassert_true(rv == 0, "k_pipe_get() failed with %d\n", rv); - zassert_true(bytes_read == 0, - "k_pipe_get() unexpectedly read %zu bytes\n", bytes_read); - - rv = k_thread_join(&get_single_tid, K_MSEC(50)); - zassert_true(rv == 0, "Wait for helper thread failed (%d)", rv); - - (void)k_thread_create(&get_single_tid, stack_1, STACK_SIZE, - test_pipe_flush_helper, &small_pipe, NULL, NULL, - K_PRIO_PREEMPT(0), K_INHERIT_PERMS | K_USER, - K_NO_WAIT); - - k_sleep(K_MSEC(50)); /* give helper thread time to execute */ - - /* - * Only flush the pipe's buffer. This is expected to leave 40 bytes - * left to receive. - */ - - k_pipe_buffer_flush(&small_pipe); - - rv = k_pipe_get(&small_pipe, results_buffer, sizeof(results_buffer), - &bytes_read, 0, K_MSEC(100)); - - zassert_true(rv == 0, "k_pipe_get() failed with %d\n", rv); - zassert_true(bytes_read == 40, - "k_pipe_get() unexpectedly read %zu bytes\n", bytes_read); - for (i = 0; i < 40; i++) { - zassert_true(results_buffer[i] == (unsigned char)(i + 10), - "At offset %zd, expected byte %02x, not %02x\n", - i, (i + 10), results_buffer[i]); - } - - rv = k_thread_join(&get_single_tid, K_MSEC(50)); - zassert_true(rv == 0, "Wait for helper thread failed (%d)", rv); -} diff --git a/tests/kernel/pipe/deprecated/pipe/testcase.yaml b/tests/kernel/pipe/deprecated/pipe/testcase.yaml deleted file mode 100644 index 76658b6757d42..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe/testcase.yaml +++ /dev/null @@ -1,6 +0,0 @@ -tests: - kernel.deprecated.pipe: - tags: - - kernel - - userspace - ignore_faults: true diff --git a/tests/kernel/pipe/deprecated/pipe_api/CMakeLists.txt b/tests/kernel/pipe/deprecated/pipe_api/CMakeLists.txt deleted file mode 100644 index 44f65534e3f81..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe_api/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -set(CMAKE_C_FLAGS "-D__deprecated=\"/* deprecated */\" -D__DEPRECATED_MACRO=\"/* deprecated_macro*/\"") -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(pipe_api) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/kernel/pipe/deprecated/pipe_api/prj.conf b/tests/kernel/pipe/deprecated/pipe_api/prj.conf deleted file mode 100644 index 02d8fd3dd5655..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe_api/prj.conf +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_ZTEST=y -CONFIG_IRQ_OFFLOAD=y -CONFIG_TEST_USERSPACE=y -CONFIG_DYNAMIC_OBJECTS=y -CONFIG_MP_MAX_NUM_CPUS=1 -CONFIG_ZTEST_FATAL_HOOK=y -CONFIG_PIPES=y -CONFIG_DEPRECATION_TEST=y diff --git a/tests/kernel/pipe/deprecated/pipe_api/src/main.c b/tests/kernel/pipe/deprecated/pipe_api/src/main.c deleted file mode 100644 index c6f057d9176aa..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe_api/src/main.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @defgroup kernel_pipe_tests PIPEs - * @ingroup all_tests - * @{ - * @} - */ - -#include - -/* k objects */ -extern struct k_pipe pipe, kpipe, khalfpipe, put_get_pipe; -extern struct k_sem end_sema; -extern struct k_stack tstack; -extern struct k_thread tdata; -extern struct k_heap test_pool; - -static void *pipe_api_setup(void) -{ - k_thread_access_grant(k_current_get(), &pipe, - &kpipe, &end_sema, &tdata, &tstack, - &khalfpipe, &put_get_pipe); - - k_thread_heap_assign(k_current_get(), &test_pool); - - return NULL; -} - -ZTEST_SUITE(pipe_api, NULL, pipe_api_setup, NULL, NULL, NULL); - -ZTEST_SUITE(pipe_api_1cpu, NULL, pipe_api_setup, - ztest_simple_1cpu_before, ztest_simple_1cpu_after, NULL); diff --git a/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_avail.c b/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_avail.c deleted file mode 100644 index 7c3ff00bd2443..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_avail.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2020 Friedt Professional Engineering Services, Inc - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief Tests for the Pipe read / write availability - * @ingroup kernel_pipe_tests - * @{ - */ - -#include - -static ZTEST_DMEM unsigned char __aligned(4) data[] = "abcdefgh"; -static struct k_pipe pipe = { - .buffer = data, - .size = sizeof(data) - 1 /* '\0' */, -}; - -static struct k_pipe bufferless; - -static struct k_pipe bufferless1 = { - .buffer = data, - .size = 0, -}; - -/** - * @brief Pipes with no buffer or size 0 should return 0 bytes available - * - * Pipes can be created to be bufferless (i.e. @ref k_pipe.buffer is `NULL` - * or @ref k_pipe.size is 0). - * - * If either of those conditions is true, then @ref k_pipe_read_avail and - * @ref k_pipe_write_avail should return 0. - * - * @note - * A distinction can be made between buffered and bufferless pipes in that - * @ref k_pipe_read_avail and @ref k_pipe_write_avail will never - * simultaneously return 0 for a buffered pipe, but they will both return 0 - * for an unbuffered pipe. - */ -ZTEST(pipe_api, test_pipe_avail_no_buffer) -{ - size_t r_avail; - size_t w_avail; - - r_avail = k_pipe_read_avail(&bufferless); - zassert_equal(r_avail, 0, "read: expected: 0 actual: %u", r_avail); - - w_avail = k_pipe_write_avail(&bufferless); - zassert_equal(w_avail, 0, "write: expected: 0 actual: %u", w_avail); - - r_avail = k_pipe_read_avail(&bufferless1); - zassert_equal(r_avail, 0, "read: expected: 0 actual: %u", r_avail); - - w_avail = k_pipe_write_avail(&bufferless1); - zassert_equal(w_avail, 0, "write: expected: 0 actual: %u", w_avail); -} - -/** - * @brief Test available read / write space for r < w - * - * This test case is for buffered @ref k_pipe objects and covers the case - * where @ref k_pipe.read_index is less than @ref k_pipe.write_index. - * - * In this case, @ref k_pipe.bytes_used is not relevant. - * - * r w - * |a|b|c|d|e|f|g|h| - * |0|1|2|3|4|5|6|7| - * - * As shown above, the pipe will be able to read 3 bytes without blocking - * and write 5 bytes without blocking. - * - * Thus - * r_avail = w - r = 3 - * would read: a b c d - * - * w_avail = N - (w - r) = 5 - * would overwrite: e f g h - */ -ZTEST(pipe_api, test_pipe_avail_r_lt_w) -{ - size_t r_avail; - size_t w_avail; - - pipe.read_index = 0; - pipe.write_index = 3; - /* pipe.bytes_used is irrelevant */ - - r_avail = k_pipe_read_avail(&pipe); - zassert_equal(r_avail, 3, "read: expected: 3 actual: %u", r_avail); - - w_avail = k_pipe_write_avail(&pipe); - zassert_equal(w_avail, 5, "write: expected: 5 actual: %u", w_avail); -} - -/** - * @brief Test available read / write space for w < r - * - * This test case is for buffered @ref k_pipe objects and covers the case - * where @ref k_pipe.write_index is less than @ref k_pipe.read_index. - * - * In this case, @ref k_pipe.bytes_used is not relevant. - * - * w r - * |a|b|c|d|e|f|g|h| - * |0|1|2|3|4|5|6|7| - * - * - * As shown above, the pipe will fbe able to read 5 bytes without blocking - * and write 3 bytes without blocking. - * - * Thus - * r_avail = N - (r - w) = 5 - * would read: e f g h - * - * w_avail = r - w = 3 - * would overwrite: a b c d - */ -ZTEST(pipe_api, test_pipe_avail_w_lt_r) -{ - size_t r_avail; - size_t w_avail; - - pipe.read_index = 3; - pipe.write_index = 0; - /* pipe.bytes_used is irrelevant */ - - r_avail = k_pipe_read_avail(&pipe); - zassert_equal(r_avail, 5, "read: expected: 4 actual: %u", r_avail); - - w_avail = k_pipe_write_avail(&pipe); - zassert_equal(w_avail, 3, "write: expected: 4 actual: %u", w_avail); -} - -/** - * @brief Test available read / write space for `r == w` and an empty buffer - * - * This test case is for buffered @ref k_pipe objects and covers the case - * where @ref k_pipe.read_index is equal to @ref k_pipe.write_index and - * @ref k_pipe.bytes_used is zero. - * - * In this case, @ref k_pipe.bytes_used is relevant because the read and - * write indices are equal. - * - * r - * w - * |a|b|c|d|e|f|g|h| - * |0|1|2|3|4|5|6|7| - * - * Regardless of whether the buffer is full or empty, the following holds: - * - * r_avail = bytes_used - * w_avail = N - bytes_used - * - * Thus: - * r_avail = 0 - * would read: - * - * w_avail = N - 0 = 8 - * would overwrite: e f g h a b c d - */ -ZTEST(pipe_api, test_pipe_avail_r_eq_w_empty) -{ - size_t r_avail; - size_t w_avail; - - pipe.read_index = 4; - pipe.write_index = 4; - pipe.bytes_used = 0; - - r_avail = k_pipe_read_avail(&pipe); - zassert_equal(r_avail, 0, "read: expected: 0 actual: %u", r_avail); - - w_avail = k_pipe_write_avail(&pipe); - zassert_equal(w_avail, 8, "write: expected: 8 actual: %u", w_avail); -} - -/** - * @brief Test available read / write space for `r == w` and a full buffer - * - * This test case is for buffered @ref k_pipe objects and covers the case - * where @ref k_pipe.read_index is equal to @ref k_pipe.write_index and - * @ref k_pipe.bytes_used is equal to @ref k_pipe.size. - * - * In this case, @ref k_pipe.bytes_used is relevant because the read and - * write indices are equal. - * - * r - * w - * |a|b|c|d|e|f|g|h| - * |0|1|2|3|4|5|6|7| - * - * Regardless of whether the buffer is full or empty, the following holds: - * - * r_avail = bytes_used - * w_avail = N - bytes_used - * - * Thus - * r_avail = N = 8 - * would read: e f g h a b c d - * - * w_avail = N - 8 = 0 - * would overwrite: - */ -ZTEST(pipe_api, test_pipe_avail_r_eq_w_full) -{ - size_t r_avail; - size_t w_avail; - - pipe.read_index = 4; - pipe.write_index = 4; - pipe.bytes_used = pipe.size; - - r_avail = k_pipe_read_avail(&pipe); - zassert_equal(r_avail, 8, "read: expected: 8 actual: %u", r_avail); - - w_avail = k_pipe_write_avail(&pipe); - zassert_equal(w_avail, 0, "write: expected: 0 actual: %u", w_avail); -} - -/** - * @} - */ diff --git a/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_contexts.c b/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_contexts.c deleted file mode 100644 index 376bf65a97e52..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_contexts.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#define STACK_SIZE (1024 + CONFIG_TEST_EXTRA_STACK_SIZE) -#define PIPE_LEN (4 * 16) -#define BYTES_TO_WRITE 16 -#define BYTES_TO_READ BYTES_TO_WRITE - -K_HEAP_DEFINE(mpool, PIPE_LEN * 1); - -static ZTEST_DMEM unsigned char __aligned(4) data[] = -"abcd1234$%^&PIPEefgh5678!/?*EPIPijkl9012[]<>PEPImnop3456{}()IPEP"; -BUILD_ASSERT(sizeof(data) >= PIPE_LEN); - -/**TESTPOINT: init via K_PIPE_DEFINE*/ -K_PIPE_DEFINE(kpipe, PIPE_LEN, 4); -K_PIPE_DEFINE(khalfpipe, (PIPE_LEN / 2), 4); -K_PIPE_DEFINE(kpipe1, PIPE_LEN, 4); -K_PIPE_DEFINE(pipe_test_alloc, PIPE_LEN, 4); -K_PIPE_DEFINE(ksmallpipe, 10, 2); -struct k_pipe pipe, pipe1; - -K_THREAD_STACK_DEFINE(tstack, STACK_SIZE); -K_THREAD_STACK_DEFINE(tstack1, STACK_SIZE); -K_THREAD_STACK_DEFINE(tstack2, STACK_SIZE); -struct k_thread tdata; -struct k_thread tdata1; -struct k_thread tdata2; -K_SEM_DEFINE(end_sema, 0, 1); - -#ifdef CONFIG_64BIT -#define SZ 256 -#else -#define SZ 128 -#endif -K_HEAP_DEFINE(test_pool, SZ * 4); - -struct mem_block { - void *data; -}; - -static void tpipe_put(struct k_pipe *ppipe, k_timeout_t timeout) -{ - size_t to_wt, wt_byte = 0; - - for (int i = 0; i < PIPE_LEN; i += wt_byte) { - /**TESTPOINT: pipe put*/ - to_wt = (PIPE_LEN - i) >= BYTES_TO_WRITE ? - BYTES_TO_WRITE : (PIPE_LEN - i); - zassert_false(k_pipe_put(ppipe, &data[i], to_wt, - &wt_byte, 1, timeout), NULL); - zassert_true(wt_byte == to_wt || wt_byte == 1); - } -} - -static void tpipe_get(struct k_pipe *ppipe, k_timeout_t timeout) -{ - unsigned char rx_data[PIPE_LEN]; - size_t to_rd, rd_byte = 0; - - /*get pipe data from "pipe_put"*/ - for (int i = 0; i < PIPE_LEN; i += rd_byte) { - /**TESTPOINT: pipe get*/ - to_rd = (PIPE_LEN - i) >= BYTES_TO_READ ? - BYTES_TO_READ : (PIPE_LEN - i); - zassert_false(k_pipe_get(ppipe, &rx_data[i], to_rd, - &rd_byte, 1, timeout), NULL); - zassert_true(rd_byte == to_rd || rd_byte == 1); - } - for (int i = 0; i < PIPE_LEN; i++) { - zassert_equal(rx_data[i], data[i]); - } -} - -static void tThread_entry(void *p1, void *p2, void *p3) -{ - tpipe_get((struct k_pipe *)p1, K_FOREVER); - k_sem_give(&end_sema); - - tpipe_put((struct k_pipe *)p1, K_NO_WAIT); - k_sem_give(&end_sema); -} - -static void tpipe_thread_thread(struct k_pipe *ppipe) -{ - /**TESTPOINT: thread-thread data passing via pipe*/ - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, - tThread_entry, ppipe, NULL, NULL, - K_PRIO_PREEMPT(0), - K_INHERIT_PERMS | K_USER, K_NO_WAIT); - - tpipe_put(ppipe, K_NO_WAIT); - k_sem_take(&end_sema, K_FOREVER); - - k_sem_take(&end_sema, K_FOREVER); - tpipe_get(ppipe, K_FOREVER); - - /* clear the spawned thread avoid side effect */ - k_thread_abort(tid); -} - -static void tpipe_kthread_to_kthread(struct k_pipe *ppipe) -{ - /**TESTPOINT: thread-thread data passing via pipe*/ - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, - tThread_entry, ppipe, NULL, NULL, - K_PRIO_PREEMPT(0), 0, K_NO_WAIT); - - tpipe_put(ppipe, K_NO_WAIT); - k_sem_take(&end_sema, K_FOREVER); - - k_sem_take(&end_sema, K_FOREVER); - tpipe_get(ppipe, K_FOREVER); - - /* clear the spawned thread avoid side effect */ - k_thread_abort(tid); -} - -static void tpipe_put_no_wait(struct k_pipe *ppipe) -{ - size_t to_wt, wt_byte = 0; - - for (int i = 0; i < PIPE_LEN; i += wt_byte) { - /**TESTPOINT: pipe put*/ - to_wt = (PIPE_LEN - i) >= BYTES_TO_WRITE ? - BYTES_TO_WRITE : (PIPE_LEN - i); - zassert_false(k_pipe_put(ppipe, &data[i], to_wt, - &wt_byte, 1, K_NO_WAIT), NULL); - zassert_true(wt_byte == to_wt || wt_byte == 1); - } -} - -static void tpipe_put_small_size(struct k_pipe *ppipe, k_timeout_t timeout) -{ - size_t to_wt, wt_byte = 0; - - for (int i = 0; i < PIPE_LEN; i += wt_byte) { - /**TESTPOINT: pipe put*/ - to_wt = 15; - zassert_false(k_pipe_put(ppipe, &data[i], to_wt, &wt_byte, - 1, timeout) != 0, NULL); - - } -} - -static void tpipe_get_small_size(struct k_pipe *ppipe, k_timeout_t timeout) -{ - unsigned char rx_data[PIPE_LEN]; - size_t to_rd, rd_byte = 0; - - /*get pipe data from "pipe_put"*/ - for (int i = 0; i < PIPE_LEN; i += rd_byte) { - /**TESTPOINT: pipe get*/ - to_rd = 15; - zassert_false(k_pipe_get(ppipe, &rx_data[i], to_rd, - &rd_byte, 1, timeout), NULL); - } -} - - -static void tpipe_get_large_size(struct k_pipe *ppipe, k_timeout_t timeout) -{ - unsigned char rx_data[PIPE_LEN]; - size_t to_rd, rd_byte = 0; - - /*get pipe data from "pipe_put"*/ - for (int i = 0; i < PIPE_LEN; i += rd_byte) { - /**TESTPOINT: pipe get*/ - to_rd = (PIPE_LEN - i) >= 128 ? - 128 : (PIPE_LEN - i); - zassert_false(k_pipe_get(ppipe, &rx_data[i], to_rd, - &rd_byte, 1, timeout), NULL); - } -} - - -/** - * @brief Test Initialization and buffer allocation of pipe, - * with various parameters - * @see k_pipe_alloc_init(), k_pipe_cleanup() - */ -ZTEST(pipe_api_1cpu, test_pipe_alloc) -{ - int ret; - - zassert_false(k_pipe_alloc_init(&pipe_test_alloc, PIPE_LEN)); - - tpipe_kthread_to_kthread(&pipe_test_alloc); - k_pipe_cleanup(&pipe_test_alloc); - - zassert_false(k_pipe_alloc_init(&pipe_test_alloc, 0)); - k_pipe_cleanup(&pipe_test_alloc); - - ret = k_pipe_alloc_init(&pipe_test_alloc, 2048); - zassert_true(ret == -ENOMEM, - "resource pool max block size is not smaller then requested buffer"); -} - -static void thread_for_get_forever(void *p1, void *p2, void *p3) -{ - tpipe_get((struct k_pipe *)p1, K_FOREVER); -} - -ZTEST(pipe_api, test_pipe_cleanup) -{ - int ret; - - zassert_false(k_pipe_alloc_init(&pipe_test_alloc, PIPE_LEN)); - - /**TESTPOINT: test if a dynamically allocated buffer can be freed*/ - ret = k_pipe_cleanup(&pipe_test_alloc); - zassert_true((ret == 0) && (pipe_test_alloc.buffer == NULL), - "Failed to free buffer with k_pipe_cleanup()."); - - /**TESTPOINT: nothing to do with k_pipe_cleanup() for static buffer in pipe*/ - ret = k_pipe_cleanup(&kpipe); - zassert_true((ret == 0) && (kpipe.buffer != NULL), - "Static buffer should not be freed."); - - zassert_false(k_pipe_alloc_init(&pipe_test_alloc, PIPE_LEN)); - - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, - thread_for_get_forever, &pipe_test_alloc, NULL, - NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT); - k_sleep(K_MSEC(100)); - - ret = k_pipe_cleanup(&pipe_test_alloc); - zassert_true(ret == -EAGAIN, "k_pipe_cleanup() should not return with 0."); - k_thread_abort(tid); -} - -static void thread_handler(void *p1, void *p2, void *p3) -{ - tpipe_put_no_wait((struct k_pipe *)p1); - k_sem_give(&end_sema); -} - -/** - * @addtogroup kernel_pipe_tests - * @{ - */ - -/** - * @brief Test pipe data passing between threads - * - * @ingroup kernel_pipe_tests - * - * @details - * Test Objective: - * - Verify data passing with "pipe put/get" APIs between - * threads - * - * Testing techniques: - * - function and block box testing,Interface testing, - * Dynamic analysis and testing. - * - * Prerequisite Conditions: - * - CONFIG_TEST_USERSPACE. - * - * Input Specifications: - * - N/A - * - * Test Procedure: - * -# Initialize a pipe, which is defined at run time. - * -# Create a thread (A). - * -# In A thread, check if it can get data, which is sent - * by main thread via the pipe. - * -# In A thread, send data to main thread via the pipe. - * -# In main thread, send data to A thread via the pipe. - * -# In main thread, check if it can get data, which is sent - * by A thread. - * -# Do the same testing with a pipe, which is defined at compile - * time - * - * Expected Test Result: - * - Data can be sent/received between threads. - * - * Pass/Fail Criteria: - * - Successful if check points in test procedure are all passed, otherwise failure. - * - * Assumptions and Constraints: - * - N/A - * - * @see k_pipe_init(), k_pipe_put(), #K_PIPE_DEFINE(x) - */ - -ZTEST(pipe_api_1cpu, test_pipe_thread2thread) -{ - /**TESTPOINT: test k_pipe_init pipe*/ - k_pipe_init(&pipe, data, PIPE_LEN); - tpipe_thread_thread(&pipe); - - /**TESTPOINT: test K_PIPE_DEFINE pipe*/ - tpipe_thread_thread(&kpipe); -} - -#ifdef CONFIG_USERSPACE -/** - * @brief Test data passing using pipes between user threads - * @see k_pipe_init(), k_pipe_put(), #K_PIPE_DEFINE(x) - */ -ZTEST_USER(pipe_api_1cpu, test_pipe_user_thread2thread) -{ - /**TESTPOINT: test k_object_alloc pipe*/ - struct k_pipe *p = k_object_alloc(K_OBJ_PIPE); - - zassert_true(p != NULL); - - /**TESTPOINT: test k_pipe_alloc_init*/ - zassert_false(k_pipe_alloc_init(p, PIPE_LEN)); - tpipe_thread_thread(p); - -} -#endif - -/** - * @brief Test resource pool free - * @see k_heap_alloc() - */ -#ifdef CONFIG_USERSPACE -ZTEST(pipe_api, test_resource_pool_auto_free) -{ - /* Pool has 2 blocks, both should succeed if kernel object and pipe - * buffer are auto-freed when the allocating threads exit - */ - zassert_true(k_heap_alloc(&test_pool, 64, K_NO_WAIT) != NULL); - zassert_true(k_heap_alloc(&test_pool, 64, K_NO_WAIT) != NULL); -} -#endif - -static void tThread_half_pipe_put(void *p1, void *p2, void *p3) -{ - tpipe_put((struct k_pipe *)p1, K_FOREVER); -} - -static void tThread_half_pipe_get(void *p1, void *p2, void *p3) -{ - tpipe_get((struct k_pipe *)p1, K_FOREVER); -} - -/** - * @brief Test put/get with smaller pipe buffer - * @see k_pipe_put(), k_pipe_get() - */ -ZTEST(pipe_api, test_half_pipe_put_get) -{ - unsigned char rx_data[PIPE_LEN]; - size_t rd_byte = 0; - int ret; - - memset(rx_data, 0, sizeof(rx_data)); - - /* TESTPOINT: min_xfer > bytes_to_read */ - ret = k_pipe_put(&kpipe, &rx_data[0], 1, &rd_byte, 24, K_NO_WAIT); - zassert_true(ret == -EINVAL); - ret = k_pipe_put(&kpipe, &rx_data[0], 24, NULL, 1, K_NO_WAIT); - zassert_true(ret == -EINVAL); - - /**TESTPOINT: thread-thread data passing via pipe*/ - k_tid_t tid1 = k_thread_create(&tdata1, tstack1, STACK_SIZE, - tThread_half_pipe_get, &khalfpipe, - NULL, NULL, K_PRIO_PREEMPT(0), - K_INHERIT_PERMS | K_USER, K_NO_WAIT); - - k_tid_t tid2 = k_thread_create(&tdata2, tstack2, STACK_SIZE, - tThread_half_pipe_get, &khalfpipe, - NULL, NULL, K_PRIO_PREEMPT(0), - K_INHERIT_PERMS | K_USER, K_NO_WAIT); - - k_sleep(K_MSEC(100)); - tpipe_put_small_size(&khalfpipe, K_NO_WAIT); - - /* clear the spawned thread avoid side effect */ - k_thread_abort(tid1); - k_thread_abort(tid2); -} - -ZTEST(pipe_api, test_pipe_get_put) -{ - unsigned char rx_data[PIPE_LEN]; - size_t rd_byte = 0; - int ret; - - /* TESTPOINT: min_xfer > bytes_to_read */ - ret = k_pipe_get(&kpipe, &rx_data[0], 1, &rd_byte, 24, K_NO_WAIT); - zassert_true(ret == -EINVAL); - ret = k_pipe_get(&kpipe, &rx_data[0], 24, NULL, 1, K_NO_WAIT); - zassert_true(ret == -EINVAL); - - /**TESTPOINT: thread-thread data passing via pipe*/ - k_tid_t tid1 = k_thread_create(&tdata1, tstack1, STACK_SIZE, - tThread_half_pipe_put, &khalfpipe, - NULL, NULL, K_PRIO_PREEMPT(0), - K_INHERIT_PERMS | K_USER, K_NO_WAIT); - - k_tid_t tid2 = k_thread_create(&tdata2, tstack2, STACK_SIZE, - tThread_half_pipe_put, &khalfpipe, - NULL, NULL, K_PRIO_PREEMPT(0), - K_INHERIT_PERMS | K_USER, K_NO_WAIT); - - k_sleep(K_MSEC(100)); - tpipe_get_small_size(&khalfpipe, K_NO_WAIT); - - /* clear the spawned thread avoid side effect */ - k_thread_abort(tid1); - k_thread_abort(tid2); -} - -ZTEST(pipe_api, test_pipe_get_large) -{ - /**TESTPOINT: thread-thread data passing via pipe*/ - k_tid_t tid1 = k_thread_create(&tdata1, tstack1, STACK_SIZE, - tThread_half_pipe_put, &khalfpipe, - NULL, NULL, K_PRIO_PREEMPT(0), - K_INHERIT_PERMS | K_USER, K_NO_WAIT); - - k_tid_t tid2 = k_thread_create(&tdata2, tstack2, STACK_SIZE, - tThread_half_pipe_put, &khalfpipe, - NULL, NULL, K_PRIO_PREEMPT(0), - K_INHERIT_PERMS | K_USER, K_NO_WAIT); - - k_sleep(K_MSEC(100)); - tpipe_get_large_size(&khalfpipe, K_NO_WAIT); - - /* clear the spawned thread avoid side effect */ - k_thread_abort(tid1); - k_thread_abort(tid2); -} - - -/** - * @brief Test pending reader in pipe - * @see k_pipe_put(), k_pipe_get() - */ -ZTEST(pipe_api, test_pipe_reader_wait) -{ - k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE, - thread_handler, &kpipe1, NULL, NULL, - K_PRIO_PREEMPT(0), 0, K_NO_WAIT); - - tpipe_get(&kpipe1, K_FOREVER); - k_sem_take(&end_sema, K_FOREVER); - k_thread_abort(tid); -} - -/** - * @} - */ diff --git a/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_fail.c b/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_fail.c deleted file mode 100644 index 60f4771ba2cc7..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_fail.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#include -#include - -#define TIMEOUT K_MSEC(100) -#define PIPE_LEN 8 - -static ZTEST_DMEM unsigned char __aligned(4) data[] = "abcd1234"; -struct k_pipe put_get_pipe; - -static void put_fail(struct k_pipe *p) -{ - size_t wt_byte = 0; - - zassert_false(k_pipe_put(p, data, PIPE_LEN, &wt_byte, - 1, K_FOREVER), NULL); - /**TESTPOINT: pipe put returns -EIO*/ - zassert_equal(k_pipe_put(p, data, PIPE_LEN, &wt_byte, - 1, K_NO_WAIT), -EIO, NULL); - zassert_false(wt_byte); - /**TESTPOINT: pipe put returns -EAGAIN*/ - zassert_equal(k_pipe_put(p, data, PIPE_LEN, &wt_byte, - 1, TIMEOUT), -EAGAIN, NULL); - zassert_true(wt_byte < 1); - zassert_equal(k_pipe_put(p, data, PIPE_LEN, &wt_byte, - PIPE_LEN + 1, TIMEOUT), -EINVAL, NULL); - -} - -/** - * @brief Test pipe put failure scenario - * @ingroup kernel_pipe_tests - * @see k_pipe_init(), k_pipe_put() - */ -ZTEST(pipe_api_1cpu, test_pipe_put_fail) -{ - k_pipe_init(&put_get_pipe, data, PIPE_LEN); - - put_fail(&put_get_pipe); -} -/** - * @brief Test pipe put by a user thread - * @ingroup kernel_pipe_tests - * @see k_pipe_put() - */ -#ifdef CONFIG_USERSPACE -ZTEST_USER(pipe_api_1cpu, test_pipe_user_put_fail) -{ - struct k_pipe *p = k_object_alloc(K_OBJ_PIPE); - - zassert_true(p != NULL); - zassert_false(k_pipe_alloc_init(p, PIPE_LEN)); - /* check the number of bytes that may be read from pipe. */ - zassert_equal(k_pipe_read_avail(p), 0); - /* check the number of bytes that may be written to pipe.*/ - zassert_equal(k_pipe_write_avail(p), PIPE_LEN); - - put_fail(p); -} -#endif - -static void get_fail(struct k_pipe *p) -{ - unsigned char rx_data[PIPE_LEN]; - size_t rd_byte = 0; - - /**TESTPOINT: pipe put returns -EIO*/ - zassert_equal(k_pipe_get(p, rx_data, PIPE_LEN, &rd_byte, 1, - K_NO_WAIT), -EIO, NULL); - zassert_false(rd_byte); - /**TESTPOINT: pipe put returns -EAGAIN*/ - zassert_equal(k_pipe_get(p, rx_data, PIPE_LEN, &rd_byte, 1, - TIMEOUT), -EAGAIN, NULL); - zassert_true(rd_byte < 1); - zassert_equal(k_pipe_get(p, rx_data, PIPE_LEN, &rd_byte, 1, - TIMEOUT), -EAGAIN, NULL); -} - -/** - * @brief Test pipe get failure scenario - * @ingroup kernel_pipe_tests - * @see k_pipe_init(), k_pipe_get() - */ -ZTEST(pipe_api, test_pipe_get_fail) -{ - k_pipe_init(&put_get_pipe, data, PIPE_LEN); - - get_fail(&put_get_pipe); -} - -#ifdef CONFIG_USERSPACE -static unsigned char user_unreach[PIPE_LEN]; -static size_t unreach_byte; - -/** - * @brief Test pipe get by a user thread - * @ingroup kernel_pipe_tests - * @see k_pipe_alloc_init() - */ -ZTEST_USER(pipe_api, test_pipe_user_get_fail) -{ - struct k_pipe *p = k_object_alloc(K_OBJ_PIPE); - - zassert_true(p != NULL); - zassert_false(k_pipe_alloc_init(p, PIPE_LEN)); - - get_fail(p); -} - -/** - * @brief Test k_pipe_alloc_init() failure scenario - * - * @details See what will happen if an uninitialized - * k_pipe is passed to k_pipe_alloc_init(). - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_alloc_init() - */ -ZTEST_USER(pipe_api, test_pipe_alloc_not_init) -{ - struct k_pipe pipe; - - ztest_set_fault_valid(true); - k_pipe_alloc_init(&pipe, PIPE_LEN); -} - -/** - * @brief Test k_pipe_get() failure scenario - * - * @details See what will happen if an uninitialized - * k_pipe is passed to k_pipe_get(). - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_get() - */ -ZTEST_USER(pipe_api, test_pipe_get_null) -{ - unsigned char rx_data[PIPE_LEN]; - size_t rd_byte = 0; - - ztest_set_fault_valid(true); - k_pipe_get(NULL, rx_data, PIPE_LEN, - &rd_byte, 1, TIMEOUT); -} - -/** - * @brief Test k_pipe_get() failure scenario - * - * @details See what will happen if the parameter - * address is accessed deny to test k_pipe_get - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_get() - */ -ZTEST_USER(pipe_api, test_pipe_get_unreach_data) -{ - struct k_pipe *p = k_object_alloc(K_OBJ_PIPE); - size_t rd_byte = 0; - - zassert_true(p != NULL); - zassert_false(k_pipe_alloc_init(p, PIPE_LEN)); - - ztest_set_fault_valid(true); - k_pipe_get(p, user_unreach, PIPE_LEN, - &rd_byte, 1, TIMEOUT); - -} - -/** - * @brief Test k_pipe_get() failure scenario - * - * @details See what will happen if the parameter - * address is accessed deny to test k_pipe_get - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_get() - */ -ZTEST_USER(pipe_api, test_pipe_get_unreach_size) -{ - struct k_pipe *p = k_object_alloc(K_OBJ_PIPE); - unsigned char rx_data[PIPE_LEN]; - - zassert_true(p != NULL); - zassert_false(k_pipe_alloc_init(p, PIPE_LEN)); - - ztest_set_fault_valid(true); - k_pipe_get(p, rx_data, PIPE_LEN, - &unreach_byte, 1, TIMEOUT); - -} - -/** - * @brief Test k_pipe_put() failure scenario - * - * @details See what will happen if a null pointer - * is passed into the k_pipe_put as a parameter - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_put() - */ -ZTEST_USER(pipe_api, test_pipe_put_null) -{ - unsigned char tx_data = 0xa; - size_t to_wt = 0, wt_byte = 0; - - ztest_set_fault_valid(true); - k_pipe_put(NULL, &tx_data, to_wt, - &wt_byte, 1, TIMEOUT); -} - -/** - * @brief Test k_pipe_put() failure scenario - * - * @details See what will happen if the parameter - * address is accessed deny to test k_pipe_put - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_put() - */ -ZTEST_USER(pipe_api, test_pipe_put_unreach_data) -{ - struct k_pipe *p = k_object_alloc(K_OBJ_PIPE); - size_t to_wt = 0, wt_byte = 0; - - zassert_true(p != NULL); - zassert_false(k_pipe_alloc_init(p, PIPE_LEN)); - - ztest_set_fault_valid(true); - k_pipe_put(p, &user_unreach[0], to_wt, - &wt_byte, 1, TIMEOUT); - -} - -/** - * @brief Test k_pipe_put() failure scenario - * - * @details See what will happen if the parameter - * address is accessed deny to test k_pipe_put - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_put() - */ -ZTEST_USER(pipe_api, test_pipe_put_unreach_size) -{ - struct k_pipe *p = k_object_alloc(K_OBJ_PIPE); - unsigned char tx_data = 0xa; - size_t to_wt = 0; - - zassert_true(p != NULL); - zassert_false(k_pipe_alloc_init(p, PIPE_LEN)); - - ztest_set_fault_valid(true); - k_pipe_put(p, &tx_data, to_wt, - &unreach_byte, 1, TIMEOUT); -} - -/** - * @brief Test k_pipe_read_avail() failure scenario - * - * @details See what will happen if a null pointer - * is passed into the k_pipe_read_avail as a parameter - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_read_avail() - */ -ZTEST_USER(pipe_api, test_pipe_read_avail_null) -{ - ztest_set_fault_valid(true); - k_pipe_read_avail(NULL); -} - -/** - * @brief Test k_pipe_write_avail() failure scenario - * - * @details See what will happen if a null pointer - * is passed into the k_pipe_write_avail as a parameter - * - * @ingroup kernel_pipe_tests - * - * @see k_pipe_write_avail() - */ -ZTEST_USER(pipe_api, test_pipe_write_avail_null) -{ - ztest_set_fault_valid(true); - k_pipe_write_avail(NULL); -} -#endif diff --git a/tests/kernel/pipe/deprecated/pipe_api/testcase.yaml b/tests/kernel/pipe/deprecated/pipe_api/testcase.yaml deleted file mode 100644 index 1564321cb7339..0000000000000 --- a/tests/kernel/pipe/deprecated/pipe_api/testcase.yaml +++ /dev/null @@ -1,5 +0,0 @@ -tests: - kernel.deprecated.pipe.api: - tags: - - kernel - - userspace diff --git a/tests/kernel/timer/starve/Kconfig b/tests/kernel/timer/starve/Kconfig index 2fee08f2a094f..7600fd15d90a6 100644 --- a/tests/kernel/timer/starve/Kconfig +++ b/tests/kernel/timer/starve/Kconfig @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2019 Nordic Semicondutor ASA +# Copyright (c) 2019 Nordic Semiconductor ASA mainmenu "Timer Starvation Test" diff --git a/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c b/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c index be5a1fc997449..699534a640ba8 100644 --- a/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c +++ b/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c @@ -33,7 +33,10 @@ static struct k_thread *main_thread; */ void helper1(void *p1, void *p2, void *p3) { - while (1) { + /* Using volatile condition to prevent compilers from optimizing while(true) */ + volatile bool condition = true; + + while (condition) { } } diff --git a/tests/lib/devicetree/api/app.overlay b/tests/lib/devicetree/api/app.overlay index 2bd178dcd1758..950ca9b403555 100644 --- a/tests/lib/devicetree/api/app.overlay +++ b/tests/lib/devicetree/api/app.overlay @@ -25,14 +25,14 @@ }; test { - #address-cells = < 0x1 >; - #size-cells = < 0x1 >; + #address-cells = <0x1>; + #size-cells = <0x1>; interrupt-parent = <&test_intc>; - test_cpu_intc: interrupt-controller { + test_cpu_intc: interrupt-controller { compatible = "vnd,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; @@ -98,7 +98,7 @@ test_enum_int_default_0: enum-4 { compatible = "vnd,enum-int-required-false-holder"; - val = < 5 >; + val = <5>; }; test_enum_int_default_1: enum-5 { @@ -130,31 +130,31 @@ */ disabled-node@0 { compatible = "vnd,disabled-compat"; - reg = < 0x0 0x1000 >; + reg = <0x0 0x1000>; status = "disabled"; }; reserved-node@0 { compatible = "vnd,reserved-node"; - reg = < 0x0 0x1000 >; + reg = <0x0 0x1000>; status = "reserved"; }; disabled_gpio: gpio@0 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0x0 0x1000 >; + reg = <0x0 0x1000>; interrupts = <3 1>; - #gpio-cells = < 0x2 >; + #gpio-cells = <0x2>; status = "disabled"; }; reserved_gpio: gpio@1 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0x1 0x1000 >; + reg = <0x1 0x1000>; interrupts = <3 1>; - #gpio-cells = < 0x2 >; + #gpio-cells = <0x2>; status = "reserved"; }; @@ -168,10 +168,10 @@ test_nodelabel: TEST_NODELABEL_ALLCAPS: test_gpio_1: gpio@deadbeef { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0xdeadbeef 0x1000 >; - #gpio-cells = < 0x2 >; - #foo-cells = < 0x1 >; - #baz-cells = < 0x1 >; + reg = <0xdeadbeef 0x1000>; + #gpio-cells = <0x2>; + #foo-cells = <0x1>; + #baz-cells = <0x1>; interrupts = <4 3>; status = "okay"; ngpios = <100>; @@ -192,11 +192,11 @@ test_gpio_2: gpio@abcd1234 { compatible = "vnd,gpio-device"; gpio-controller; - reg = < 0xabcd1234 0x500 0x98765432 0xff >; + reg = <0xabcd1234 0x500 0x98765432 0xff>; reg-names = "one", "two"; - #gpio-cells = < 0x2 >; - #foo-cells = < 0x1 >; - #baz-cells = < 0x1 >; + #gpio-cells = <0x2>; + #foo-cells = <0x1>; + #baz-cells = <0x1>; interrupts = <5 2>; status = "okay"; ngpios = <200>; @@ -212,8 +212,8 @@ test_gpio_3: gpio@1234 { compatible = "vnd,gpio-one-cell"; gpio-controller; - reg = < 0x1234 0x500 >; - #gpio-cells = < 0x1 >; + reg = <0x1234 0x500>; + #gpio-cells = <0x1>; status = "okay"; }; @@ -228,18 +228,18 @@ }; test_i2c: i2c@11112222 { - #address-cells = < 1 >; - #size-cells = < 0 >; + #address-cells = <1>; + #size-cells = <0>; compatible = "vnd,i2c"; - reg = < 0x11112222 0x1000 >; + reg = <0x11112222 0x1000>; status = "okay"; - clock-frequency = < 100000 >; + clock-frequency = <100000>; interrupts = <6 2 7 1>; interrupt-names = "status", "error"; test-i2c-dev@10 { compatible = "vnd,i2c-device"; - reg = < 0x10 >; + reg = <0x10>; }; gpio@11 { @@ -276,33 +276,33 @@ }; test_i2c_no_reg: i2c { - #address-cells = < 1 >; - #size-cells = < 0 >; + #address-cells = <1>; + #size-cells = <0>; compatible = "vnd,i2c"; status = "okay"; - clock-frequency = < 100000 >; + clock-frequency = <100000>; test-i2c-dev@12 { compatible = "vnd,i2c-device"; - reg = < 0x12 >; + reg = <0x12>; }; }; test_i3c: i3c@88889999 { - #address-cells = < 3 >; - #size-cells = < 0 >; + #address-cells = <3>; + #size-cells = <0>; compatible = "vnd,i3c"; - reg = < 0x88889999 0x1000 >; + reg = <0x88889999 0x1000>; status = "okay"; test-i3c-dev@420000ABCD12345678 { compatible = "vnd,i3c-device"; - reg = < 0x42 0xABCD 0x12345678 >; + reg = <0x42 0xABCD 0x12345678>; }; test-i3c-i2c-dev@380000000000000050 { compatible = "vnd,i3c-i2c-device"; - reg = < 0x38 0x0 0x50 >; + reg = <0x38 0x0 0x50>; }; }; @@ -319,30 +319,30 @@ }; test_spi: spi@33334444 { - #address-cells = < 1 >; - #size-cells = < 0 >; + #address-cells = <1>; + #size-cells = <0>; compatible = "vnd,spi"; - reg = < 0x33334444 0x1000 >; + reg = <0x33334444 0x1000>; interrupts = <8 3 9 0 10 1>; status = "okay"; - clock-frequency = < 2000000 >; + clock-frequency = <2000000>; cs-gpios = <&test_gpio_1 0x10 0x20>, - <&test_gpio_2 0x30 0x40>, - <&test_gpio_2 0x50 0x60>; + <&test_gpio_2 0x30 0x40>, + <&test_gpio_2 0x50 0x60>; /* all vnd,spi-device instances should have CS */ test-spi-dev@0 { compatible = "vnd,spi-device"; reg = <0>; - spi-max-frequency = < 2000000 >; + spi-max-frequency = <2000000>; }; test-spi-dev@1 { compatible = "vnd,spi-device"; reg = <1>; - spi-max-frequency = < 2000000 >; + spi-max-frequency = <2000000>; }; gpio@2 { @@ -355,12 +355,12 @@ }; test_spi_no_cs: spi@55556666 { - #address-cells = < 1 >; - #size-cells = < 0 >; + #address-cells = <1>; + #size-cells = <0>; compatible = "vnd,spi"; - reg = < 0x55556666 0x1000 >; + reg = <0x55556666 0x1000>; status = "okay"; - clock-frequency = < 2000000 >; + clock-frequency = <2000000>; /* * There should only be one spi-device-2 node. @@ -369,17 +369,17 @@ test_spi_dev_no_cs: test-spi-dev@0 { compatible = "vnd,spi-device-2"; reg = <0>; - spi-max-frequency = < 2000000 >; + spi-max-frequency = <2000000>; }; }; test_i2c_1: i2c@77778888 { - #address-cells = < 1 >; - #size-cells = < 0 >; + #address-cells = <1>; + #size-cells = <0>; compatible = "vnd,i2c"; - reg = < 0x77778888 0x1000 >; + reg = <0x77778888 0x1000>; status = "okay"; - clock-frequency = < 100000 >; + clock-frequency = <100000>; interrupts = <11 3 12 2>; interrupt-names = "status", "error"; }; @@ -420,7 +420,7 @@ /* there should only be one of these */ test_reg: reg-holder@9999aaaa { compatible = "vnd,reg-holder"; - reg = < 0x9999aaaa 0x1000 0xbbbbcccc 0x3f >; + reg = <0x9999aaaa 0x1000 0xbbbbcccc 0x3f>; status = "okay"; reg-names = "first", "second"; misc-prop = <1234>; @@ -431,7 +431,7 @@ status = "okay"; }; - test_intc: interrupt-controller@bbbbcccc { + test_intc: interrupt-controller@bbbbcccc { compatible = "vnd,intc"; reg = <0xbbbbcccc 0x1000>; interrupt-controller; @@ -493,7 +493,7 @@ test_dma1: dma@44443333 { compatible = "vnd,dma"; #dma-cells = <2>; - reg = < 0x44443333 0x1000 >; + reg = <0x44443333 0x1000>; interrupts = <11 3>; status = "okay"; }; @@ -501,7 +501,7 @@ test_dma2: dma@44442222 { compatible = "vnd,dma"; #dma-cells = <2>; - reg = < 0x44442222 0x1000 >; + reg = <0x44442222 0x1000>; interrupts = <12 3>; status = "okay"; }; @@ -574,14 +574,14 @@ test_pwm1: pwm@55551111 { compatible = "vnd,pwm"; #pwm-cells = <3>; - reg = < 0x55551111 0x1000 >; + reg = <0x55551111 0x1000>; status = "okay"; }; test_pwm2: pwm@55552222 { compatible = "vnd,pwm"; #pwm-cells = <3>; - reg = < 0x55552222 0x1000 >; + reg = <0x55552222 0x1000>; status = "okay"; }; @@ -602,14 +602,14 @@ test_can0: can@55553333 { compatible = "vnd,can-controller"; - reg = < 0x55553333 0x1000 >; + reg = <0x55553333 0x1000>; status = "okay"; phys = <&test_transceiver0>; }; test_can1: can@55554444 { compatible = "vnd,can-controller"; - reg = < 0x55554444 0x1000 >; + reg = <0x55554444 0x1000>; status = "okay"; can-transceiver { @@ -620,7 +620,7 @@ test_can2: can@55555555 { compatible = "vnd,can-controller"; - reg = < 0x55555555 0x1000 >; + reg = <0x55555555 0x1000>; status = "okay"; can-transceiver { @@ -630,7 +630,7 @@ test_can3: can@55557777 { compatible = "vnd,can-controller"; - reg = < 0x55556666 0x1000 >; + reg = <0x55556666 0x1000>; status = "okay"; phys = <&test_transceiver1>; }; @@ -845,25 +845,25 @@ }; test-mtd@ffeeddcc { - reg = < 0xffeeddcc 0x1000 >; - #address-cells = < 1 >; - #size-cells = < 1 >; + reg = <0xffeeddcc 0x1000>; + #address-cells = <1>; + #size-cells = <1>; flash@20000000 { compatible = "soc-nv-flash"; - reg = < 0x20000000 0x100 >; + reg = <0x20000000 0x100>; partitions { compatible = "fixed-partitions"; - #address-cells = < 1 >; - #size-cells = < 1 >; + #address-cells = <1>; + #size-cells = <1>; partition@0 { - reg = < 0x0 0xc0 >; + reg = <0x0 0xc0>; label = "test-partition-0"; }; partition@c0 { - reg = < 0xc0 0x40 >; + reg = <0xc0 0x40>; label = "test-partition-1"; }; @@ -890,15 +890,15 @@ }; test-mtd@33221100 { - reg = < 0x33221100 0x1000 >; + reg = <0x33221100 0x1000>; partitions { compatible = "fixed-partitions"; - #address-cells = < 1 >; - #size-cells = < 1 >; + #address-cells = <1>; + #size-cells = <1>; partition@6ff80 { - reg = < 0x6ff80 0x80 >; + reg = <0x6ff80 0x80>; label = "test-partition-2"; }; }; @@ -906,12 +906,12 @@ }; test_64 { - #address-cells = < 2 >; - #size-cells = < 0 >; + #address-cells = <2>; + #size-cells = <0>; test_reg_64: reg-holder-64@ffffffff11223344 { compatible = "vnd,reg-holder-64"; - reg = < 0xffffffff 0x11223344>; + reg = <0xffffffff 0x11223344>; status = "okay"; reg-names = "test_name"; }; diff --git a/tests/lib/devicetree/api/src/main.c b/tests/lib/devicetree/api/src/main.c index bb214ec6a7666..98189ebe582cc 100644 --- a/tests/lib/devicetree/api/src/main.c +++ b/tests/lib/devicetree/api/src/main.c @@ -18,7 +18,7 @@ #define TEST_NODELABEL DT_NODELABEL(test_nodelabel) #define TEST_INST DT_INST(0, vnd_gpio_device) #define TEST_ARRAYS DT_NODELABEL(test_arrays) -#define TEST_PH DT_NODELABEL(test_phandles) +#define TEST_PH DT_NODELABEL(test_phandles) #define TEST_INTC DT_NODELABEL(test_intc) #define TEST_IRQ DT_NODELABEL(test_irq) #define TEST_IRQ_EXT DT_NODELABEL(test_irq_extended) @@ -1114,6 +1114,65 @@ ZTEST(devicetree_api, test_phandles) zassert_true(DT_SAME_NODE(DT_PHANDLE_BY_NAME(TEST_PH, foos, a), TEST_GPIO_1), ""); zassert_true(DT_SAME_NODE(DT_PHANDLE_BY_NAME(TEST_PH, foos, b_c), TEST_GPIO_2), ""); + /* DT_PHA_NUM_CELLS_BY_IDX */ + zassert_equal(DT_PHA_NUM_CELLS_BY_IDX(TEST_PH, foos, 0), 1); + zassert_equal(DT_PHA_NUM_CELLS_BY_IDX(TEST_PH, pha_gpios, 2), 1); + zassert_equal(DT_PHA_NUM_CELLS_BY_IDX(TEST_PH, pha_gpios, 3), 2); + + /* DT_PHA_NUM_CELLS_BY_NAME */ + zassert_equal(DT_PHA_NUM_CELLS_BY_NAME(TEST_PH, foos, a), 1); + zassert_equal(DT_PHA_NUM_CELLS_BY_NAME(TEST_PH, pwms, green), 3); + zassert_equal(DT_PHA_NUM_CELLS_BY_NAME(TEST_PH, pwms, red), 3); + + /* DT_PHA_ELEM_NAME_BY_IDX */ + zassert_str_equal(DT_PHA_ELEM_NAME_BY_IDX(TEST_PH, foos, 0), "A"); + zassert_str_equal(DT_PHA_ELEM_NAME_BY_IDX(TEST_PH, foos, 1), "b-c"); + zassert_str_equal(DT_PHA_ELEM_NAME_BY_IDX(TEST_PH, pwms, 0), "red"); + zassert_str_equal(DT_PHA_ELEM_NAME_BY_IDX(TEST_PH, pwms, 1), "green"); + + /* DT_PHA_ELEM_IDX_BY_NAME */ + zassert_equal(DT_PHA_ELEM_IDX_BY_NAME(TEST_PH, foos, a), 0); + zassert_equal(DT_PHA_ELEM_IDX_BY_NAME(TEST_PH, foos, b_c), 1); + zassert_equal(DT_PHA_ELEM_IDX_BY_NAME(TEST_PH, pwms, red), 0); + zassert_equal(DT_PHA_ELEM_IDX_BY_NAME(TEST_PH, pwms, green), 1); + + /* DT_FOREACH_PHA_CELL_BY_IDX */ + int chksum; + +#define ADD_TWO(node_id, pha, idx, x) (DT_PHA_BY_IDX(node_id, pha, idx, x) + 2) + + chksum = DT_FOREACH_PHA_CELL_BY_IDX(TEST_PH, pwms, 0, ADD_TWO) 0; + zassert_equal(chksum, 211 + 6); + chksum = DT_FOREACH_PHA_CELL_BY_IDX(TEST_PH, foos, 1, ADD_TWO) 0; + zassert_equal(chksum, 110 + 2); + + /* DT_FOREACH_PHA_CELL_BY_IDX_SEP */ + int cells_one[2] = { + DT_FOREACH_PHA_CELL_BY_IDX_SEP(TEST_PH, pha_gpios, 0, DT_PHA_BY_IDX, (,)) + }; + int cells_two[1] = { + DT_FOREACH_PHA_CELL_BY_IDX_SEP(TEST_PH, pha_gpios, 2, DT_PHA_BY_IDX, (,)) + }; + + zassert_equal(cells_one[0], 50); + zassert_equal(cells_one[1], 60); + zassert_equal(cells_two[0], 70); + + /* DT_FOREACH_PHA_CELL_BY_NAME */ +#define ADD_THREE(node_id, pha, idx, x) (DT_PHA_BY_NAME(node_id, pha, idx, x) + 3) + + chksum = DT_FOREACH_PHA_CELL_BY_NAME(TEST_PH, pwms, red, ADD_THREE) 0; + zassert_equal(chksum, 211 + 9); + chksum = DT_FOREACH_PHA_CELL_BY_NAME(TEST_PH, pwms, green, ADD_THREE) 0; + zassert_equal(chksum, 106 + 9); + + /* DT_FOREACH_PHA_CELL_BY_NAME_SEP */ + int cells_pwms[3] = { + DT_FOREACH_PHA_CELL_BY_NAME_SEP(TEST_PH, pwms, green, DT_PHA_BY_NAME, (,)) + }; + + zassert_equal(cells_pwms[0], 5); + zassert_equal(cells_pwms[1], 100); + zassert_equal(cells_pwms[2], 1); + /* array initializers */ zassert_equal(gps[0].pin, 10, ""); zassert_equal(gps[0].flags, 20, ""); diff --git a/tests/lib/devicetree/api_ext/app.overlay b/tests/lib/devicetree/api_ext/app.overlay index 5f20b5cbbf95e..8be62885b8825 100644 --- a/tests/lib/devicetree/api_ext/app.overlay +++ b/tests/lib/devicetree/api_ext/app.overlay @@ -13,17 +13,17 @@ / { test { - #address-cells = < 0x1 >; - #size-cells = < 0x1 >; + #address-cells = <0x1>; + #size-cells = <0x1>; test_sram1: sram@20000000 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = < 0x20000000 0x1000 >; + reg = <0x20000000 0x1000>; zephyr,memory-region = "SRAM_REGION"; }; test_sram2: sram@20001000 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = < 0x20001000 0x1000 >; + reg = <0x20001000 0x1000>; zephyr,memory-region = "SRAM@REGION#2"; }; diff --git a/tests/lib/devicetree/memory_region/app.overlay b/tests/lib/devicetree/memory_region/app.overlay index 9f7ae4162191e..27a506811c698 100644 --- a/tests/lib/devicetree/memory_region/app.overlay +++ b/tests/lib/devicetree/memory_region/app.overlay @@ -4,12 +4,12 @@ / { test { - #address-cells = < 0x1 >; - #size-cells = < 0x1 >; + #address-cells = <0x1>; + #size-cells = <0x1>; test_sram: sram@20010000 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = < 0x20010000 0x1000 >; + reg = <0x20010000 0x1000>; zephyr,memory-region = "SRAM_REGION"; }; }; diff --git a/tests/lib/devicetree/memory_region_flags/app.overlay b/tests/lib/devicetree/memory_region_flags/app.overlay index 481ac6ce8aaf4..e54053e7bb3f6 100644 --- a/tests/lib/devicetree/memory_region_flags/app.overlay +++ b/tests/lib/devicetree/memory_region_flags/app.overlay @@ -4,32 +4,32 @@ / { test { - #address-cells = < 0x1 >; - #size-cells = < 0x1 >; + #address-cells = <0x1>; + #size-cells = <0x1>; test_region_r: sram@20010000 { compatible = "zephyr,memory-region"; - reg = < 0x20010000 0x100 >; + reg = <0x20010000 0x100>; zephyr,memory-region = "TEST_REGION_R"; zephyr,memory-region-flags = "r"; }; test_region_nrwxail: sram@20010100 { compatible = "zephyr,memory-region"; - reg = < 0x20010100 0x100 >; + reg = <0x20010100 0x100>; zephyr,memory-region = "TEST_REGION_NRWXAIL"; zephyr,memory-region-flags = "!rwxail"; }; test_region_no_flags: sram@20010200 { compatible = "zephyr,memory-region"; - reg = < 0x20010200 0x100 >; + reg = <0x20010200 0x100>; zephyr,memory-region = "TEST_REGION_NO_FLAGS"; }; test_region_none: sram@20010300 { compatible = "zephyr,memory-region"; - reg = < 0x20010300 0x100 >; + reg = <0x20010300 0x100>; zephyr,memory-region = "TEST_REGION_NONE"; zephyr,memory-region-flags = ""; }; diff --git a/tests/lib/shared_multi_heap/boards/mps2_an521_cpu0.overlay b/tests/lib/shared_multi_heap/boards/mps2_an521_cpu0.overlay index fca88ad07fd58..02af41ff1f132 100644 --- a/tests/lib/shared_multi_heap/boards/mps2_an521_cpu0.overlay +++ b/tests/lib/shared_multi_heap/boards/mps2_an521_cpu0.overlay @@ -20,20 +20,20 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x38100000 0x1000>; zephyr,memory-region = "RES0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = ; }; res1: memory@38200000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x38200000 0x2000>; zephyr,memory-region = "RES1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; res2: memory@38300000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x38300000 0x3000>; zephyr,memory-region = "RES2"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = ; }; }; diff --git a/tests/lib/shared_multi_heap/boards/qemu_cortex_a53.overlay b/tests/lib/shared_multi_heap/boards/qemu_cortex_a53.overlay index e00b217a8eb89..63300a304b16c 100644 --- a/tests/lib/shared_multi_heap/boards/qemu_cortex_a53.overlay +++ b/tests/lib/shared_multi_heap/boards/qemu_cortex_a53.overlay @@ -13,14 +13,14 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 0x42000000 0x0 0x1000>; zephyr,memory-region = "RES0"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = ; }; res1: memory@43000000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 0x43000000 0x0 0x2000>; zephyr,memory-region = "RES1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; res_no_mpu: memory@45000000 { @@ -33,7 +33,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 0x44000000 0x0 0x3000>; zephyr,memory-region = "RES2"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = ; }; }; }; diff --git a/tests/lib/timespec_util/src/main.c b/tests/lib/timespec_util/src/main.c index b85727d226770..b3ab77a5583c8 100644 --- a/tests/lib/timespec_util/src/main.c +++ b/tests/lib/timespec_util/src/main.c @@ -12,19 +12,18 @@ #include #include -BUILD_ASSERT(sizeof(time_t) == sizeof(int64_t), "time_t must be 64-bit"); -BUILD_ASSERT(sizeof(((struct timespec *)0)->tv_sec) == sizeof(int64_t), "tv_sec must be 64-bit"); - -/* need NSEC_PER_SEC to be signed for the purposes of this testsuite */ -#undef NSEC_PER_SEC -#define NSEC_PER_SEC 1000000000L - #undef CORRECTABLE #define CORRECTABLE true #undef UNCORRECTABLE #define UNCORRECTABLE false +/* Initialize a struct timespec object from a tick count with additional nanoseconds */ +#define SYS_TICKS_TO_TIMESPEC_PLUS_NSECS(ticks, ns) \ + SYS_TIMESPEC(SYS_TICKS_TO_SECS(ticks) + \ + (SYS_TICKS_TO_NSECS(ticks) + (uint64_t)(ns)) / NSEC_PER_SEC, \ + (SYS_TICKS_TO_NSECS(ticks) + (uint64_t)(ns)) % NSEC_PER_SEC) + /* * test spec for simple timespec validation * @@ -79,37 +78,39 @@ static const struct ts_test_spec ts_tests[] = { DECL_VALID_TS_TEST(-1, 0), DECL_VALID_TS_TEST(-1, 1), DECL_VALID_TS_TEST(-1, NSEC_PER_SEC - 1), - DECL_VALID_TS_TEST(INT64_MIN, 0), - DECL_VALID_TS_TEST(INT64_MIN, NSEC_PER_SEC - 1), - DECL_VALID_TS_TEST(INT64_MAX, 0), - DECL_VALID_TS_TEST(INT64_MAX, NSEC_PER_SEC - 1), + DECL_VALID_TS_TEST(SYS_TIME_T_MIN, 0), + DECL_VALID_TS_TEST(SYS_TIME_T_MIN, NSEC_PER_SEC - 1), + DECL_VALID_TS_TEST(SYS_TIME_T_MAX, 0), + DECL_VALID_TS_TEST(SYS_TIME_T_MAX, NSEC_PER_SEC - 1), /* Correctable, invalid cases */ - DECL_INVALID_TS_TEST(0, -2 * NSEC_PER_SEC + 1, -2, 1, CORRECTABLE), - DECL_INVALID_TS_TEST(0, -2 * NSEC_PER_SEC - 1, -3, NSEC_PER_SEC - 1, CORRECTABLE), - DECL_INVALID_TS_TEST(0, -NSEC_PER_SEC - 1, -2, NSEC_PER_SEC - 1, CORRECTABLE), + DECL_INVALID_TS_TEST(0, -2LL * NSEC_PER_SEC + 1, -2, 1, CORRECTABLE), + DECL_INVALID_TS_TEST(0, -2LL * NSEC_PER_SEC - 1, -3, NSEC_PER_SEC - 1, CORRECTABLE), + DECL_INVALID_TS_TEST(0, -1LL * NSEC_PER_SEC - 1, -2, NSEC_PER_SEC - 1, CORRECTABLE), DECL_INVALID_TS_TEST(0, -1, -1, NSEC_PER_SEC - 1, CORRECTABLE), DECL_INVALID_TS_TEST(0, NSEC_PER_SEC, 1, 0, CORRECTABLE), - DECL_INVALID_TS_TEST(0, NSEC_PER_SEC + 1, 1, 0, CORRECTABLE), + DECL_INVALID_TS_TEST(0, NSEC_PER_SEC + 1, 1, 1, CORRECTABLE), DECL_INVALID_TS_TEST(1, -1, 0, NSEC_PER_SEC - 1, CORRECTABLE), DECL_INVALID_TS_TEST(1, NSEC_PER_SEC, 2, 0, CORRECTABLE), DECL_INVALID_TS_TEST(-1, -1, -2, NSEC_PER_SEC - 1, CORRECTABLE), DECL_INVALID_TS_TEST(0, NSEC_PER_SEC, 1, 0, CORRECTABLE), DECL_INVALID_TS_TEST(1, -1, 0, NSEC_PER_SEC - 1, CORRECTABLE), DECL_INVALID_TS_TEST(1, NSEC_PER_SEC, 2, 0, CORRECTABLE), - DECL_INVALID_TS_TEST(INT64_MIN, NSEC_PER_SEC, INT64_MIN + 1, 0, CORRECTABLE), - DECL_INVALID_TS_TEST(INT64_MAX, -1, INT64_MAX - 1, NSEC_PER_SEC - 1, CORRECTABLE), - DECL_INVALID_TS_TEST(0, LONG_MIN, LONG_MAX / NSEC_PER_SEC, 145224192, CORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MIN, NSEC_PER_SEC, SYS_TIME_T_MIN + 1, 0, CORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MAX, -1, SYS_TIME_T_MAX - 1, NSEC_PER_SEC - 1, CORRECTABLE), + DECL_INVALID_TS_TEST(0, LONG_MIN, (int64_t)LONG_MIN / NSEC_PER_SEC - 1, + NSEC_PER_SEC + LONG_MIN % (long long)NSEC_PER_SEC, CORRECTABLE), DECL_INVALID_TS_TEST(0, LONG_MAX, LONG_MAX / NSEC_PER_SEC, LONG_MAX % NSEC_PER_SEC, CORRECTABLE), /* Uncorrectable, invalid cases */ - DECL_INVALID_TS_TEST(INT64_MIN + 2, -2 * NSEC_PER_SEC - 1, 0, 0, UNCORRECTABLE), - DECL_INVALID_TS_TEST(INT64_MIN + 1, -NSEC_PER_SEC - 1, 0, 0, UNCORRECTABLE), - DECL_INVALID_TS_TEST(INT64_MIN + 1, -NSEC_PER_SEC - 1, 0, 0, UNCORRECTABLE), - DECL_INVALID_TS_TEST(INT64_MIN, -1, 0, 0, UNCORRECTABLE), - DECL_INVALID_TS_TEST(INT64_MAX, NSEC_PER_SEC, 0, 0, UNCORRECTABLE), - DECL_INVALID_TS_TEST(INT64_MAX - 1, 2 * NSEC_PER_SEC, 0, 0, UNCORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MIN + 2, -2 * (int64_t)NSEC_PER_SEC - 1, 0, 0, + UNCORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MIN + 1, -(int64_t)NSEC_PER_SEC - 1, 0, 0, UNCORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MIN + 1, -(int64_t)NSEC_PER_SEC - 1, 0, 0, UNCORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MIN, -1, 0, 0, UNCORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MAX, (int64_t)NSEC_PER_SEC, 0, 0, UNCORRECTABLE), + DECL_INVALID_TS_TEST(SYS_TIME_T_MAX - 1, 2 * (int64_t)NSEC_PER_SEC, 0, 0, UNCORRECTABLE), }; ZTEST(timeutil_api, test_timespec_is_valid) @@ -128,24 +129,33 @@ ZTEST(timeutil_api, test_timespec_is_valid) ZTEST(timeutil_api, test_timespec_normalize) { ARRAY_FOR_EACH(ts_tests, i) { - bool different; + bool different, corrected; bool overflow; const struct ts_test_spec *const tspec = &ts_tests[i]; struct timespec norm = tspec->invalid_ts; + TC_PRINT("%zu: timespec_normalize({%lld, %lld})\n", i, + (long long)tspec->invalid_ts.tv_sec, (long long)tspec->invalid_ts.tv_nsec); + overflow = !timespec_normalize(&norm); zexpect_not_equal(tspec->expect_valid || tspec->correctable, overflow, - "%d: timespec_normalize({%ld, %ld}) %s, unexpectedly", i, - (long)tspec->invalid_ts.tv_sec, (long)tspec->invalid_ts.tv_nsec, + "%d: timespec_normalize({%lld, %lld}) %s, unexpectedly", i, + (long long)tspec->invalid_ts.tv_sec, + (long long)tspec->invalid_ts.tv_nsec, tspec->correctable ? "failed" : "succeeded"); if (!tspec->expect_valid && tspec->correctable) { different = !timespec_equal(&tspec->invalid_ts, &norm); - zexpect_true(different, "%d: {%ld, %ld} and {%ld, %ld} are unexpectedly %s", - i, tspec->invalid_ts.tv_sec, tspec->invalid_ts.tv_nsec, - norm.tv_sec, tspec->valid_ts.tv_sec, - (tspec->expect_valid || tspec->correctable) ? "different" - : "equal"); + corrected = timespec_equal(&tspec->valid_ts, &norm); + zexpect_true(different && corrected, + "%d: {%lld, %lld} is not properly corrected:" + "{%lld, %lld} != {%lld, %lld}", i, + (long long)tspec->invalid_ts.tv_sec, + (long long)tspec->invalid_ts.tv_nsec, + (long long)tspec->valid_ts.tv_sec, + (long long)tspec->valid_ts.tv_nsec, + (long long)norm.tv_sec, + (long long)norm.tv_nsec); } } } @@ -166,10 +176,12 @@ ZTEST(timeutil_api, test_timespec_add) {.a = {-1, 1}, .b = {-1, 1}, .result = {-2, 2}, .expect = false}, {.a = {-1, NSEC_PER_SEC - 1}, .b = {0, 1}, .result = {0, 0}, .expect = false}, /* overflow cases */ - {.a = {INT64_MAX, 0}, .b = {1, 0}, .result = {0}, .expect = true}, - {.a = {INT64_MIN, 0}, .b = {-1, 0}, .result = {0}, .expect = true}, - {.a = {INT64_MAX, NSEC_PER_SEC - 1}, .b = {1, 1}, .result = {0}, .expect = true}, - {.a = {INT64_MIN, NSEC_PER_SEC - 1}, .b = {-1, 0}, .result = {0}, .expect = true}, + {.a = {SYS_TIME_T_MAX, 0}, .b = {1, 0}, .result = {0}, .expect = true}, + {.a = {SYS_TIME_T_MIN, 0}, .b = {-1, 0}, .result = {0}, .expect = true}, + {.a = {SYS_TIME_T_MAX, NSEC_PER_SEC - 1}, .b = {1, 1}, .result = {0}, + .expect = true}, + {.a = {SYS_TIME_T_MIN, NSEC_PER_SEC - 1}, .b = {-1, 0}, .result = {0}, + .expect = true}, }; ARRAY_FOR_EACH(tspecs, i) { @@ -203,9 +215,10 @@ ZTEST(timeutil_api, test_timespec_negate) {.ts = {0, 0}, .result = {0, 0}, .expect_failure = false}, {.ts = {1, 1}, .result = {-2, NSEC_PER_SEC - 1}, .expect_failure = false}, {.ts = {-1, 1}, .result = {0, NSEC_PER_SEC - 1}, .expect_failure = false}, - {.ts = {INT64_MAX, 0}, .result = {INT64_MIN + 1, 0}, .expect_failure = false}, + {.ts = {SYS_TIME_T_MAX, 0}, .result = {SYS_TIME_T_MIN + 1, 0}, + .expect_failure = false}, /* overflow cases */ - {.ts = {INT64_MIN, 0}, .result = {0}, .expect_failure = true}, + {.ts = {SYS_TIME_T_MIN, 0}, .result = {0}, .expect_failure = true}, }; ARRAY_FOR_EACH(tspecs, i) { @@ -268,57 +281,173 @@ ZTEST(timeutil_api, test_timespec_equal) zexpect_false(timespec_equal(&a, &b)); } -#define K_TICK_MAX ((uint64_t)(CONFIG_TIMEOUT_64BIT ? (INT64_MAX) : (UINT32_MAX))) -#define NS_PER_TICK (NSEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) +ZTEST(timeutil_api, test_SYS_TICKS_TO_SECS) +{ + zexpect_equal(SYS_TICKS_TO_SECS(0), 0); + zexpect_equal(SYS_TICKS_TO_SECS(CONFIG_SYS_CLOCK_TICKS_PER_SEC), 1); + zexpect_equal(SYS_TICKS_TO_SECS(2 * CONFIG_SYS_CLOCK_TICKS_PER_SEC), 2); + zexpect_equal(SYS_TICKS_TO_SECS(K_TICKS_FOREVER), SYS_TIME_T_MAX); + + if (SYS_TIME_T_MAX >= 92233720368547758LL) { + /* These checks should only be done if time_t has enough bits to hold K_TS_MAX */ + zexpect_equal(SYS_TICKS_TO_SECS(K_TICK_MAX), SYS_TIMESPEC_MAX.tv_sec); +#if defined(CONFIG_TIMEOUT_64BIT) && (CONFIG_SYS_CLOCK_TICKS_PER_SEC == 100) + zexpect_equal(SYS_TIMESPEC_MAX.tv_sec, 92233720368547758LL); +#endif + } -/* 0 := lower limit, 2 := upper limit */ -static const struct timespec k_timeout_limits[] = { - /* K_NO_WAIT + 1 tick */ - { - .tv_sec = 0, - .tv_nsec = NS_PER_TICK, - }, - /* K_FOREVER - 1 tick */ - { - .tv_sec = CLAMP((NS_PER_TICK * K_TICK_MAX) / NSEC_PER_SEC, 0, INT64_MAX), - .tv_nsec = CLAMP((NS_PER_TICK * K_TICK_MAX) % NSEC_PER_SEC, 0, NSEC_PER_SEC - 1), - }, -}; +#if (CONFIG_SYS_CLOCK_TICKS_PER_SEC == 32768) +#if defined(CONFIG_TIMEOUT_64BIT) + if (SYS_TIME_T_MAX >= 281474976710655LL) { + zexpect_equal(SYS_TIMESPEC_MAX.tv_sec, 281474976710655LL); + } +#else + zexpect_equal(SYS_TIMESPEC_MAX.tv_sec, 131071); +#endif +#endif +} + +ZTEST(timeutil_api, test_SYS_TICKS_TO_NSECS) +{ + zexpect_equal(SYS_TICKS_TO_NSECS(0), 0); + zexpect_equal(SYS_TICKS_TO_NSECS(1) % NSEC_PER_SEC, + (NSEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) % NSEC_PER_SEC); + zexpect_equal(SYS_TICKS_TO_NSECS(2) % NSEC_PER_SEC, + (2 * NSEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) % NSEC_PER_SEC); + zexpect_equal(SYS_TICKS_TO_NSECS(K_TICK_MAX), SYS_TIMESPEC_MAX.tv_nsec); + zexpect_equal(SYS_TICKS_TO_NSECS(K_TICKS_FOREVER), NSEC_PER_SEC - 1); + +#if defined(CONFIG_TIMEOUT_64BIT) && (CONFIG_SYS_CLOCK_TICKS_PER_SEC == 100) + zexpect_equal(SYS_TIMESPEC_MAX.tv_nsec, 70000000L); +#endif + +#if (CONFIG_SYS_CLOCK_TICKS_PER_SEC == 32768) +#if defined(CONFIG_TIMEOUT_64BIT) + zexpect_equal(SYS_TIMESPEC_MAX.tv_nsec, 999969482L); +#else + zexpect_equal(SYS_TIMESPEC_MAX.tv_nsec, 999938964L); +#endif +#endif +} + +/* non-saturating */ +#define DECL_TOSPEC_TEST(to, ts, sat, neg, round) \ + { \ + .timeout = (to), \ + .tspec = (ts), \ + .saturation = (sat), \ + .negative = (neg), \ + .roundup = (round), \ + } +/* negative timespecs rounded up to K_NO_WAIT */ +#define DECL_TOSPEC_NEGATIVE_TEST(ts) DECL_TOSPEC_TEST(K_NO_WAIT, (ts), 0, true, false) +/* zero-valued timeout */ +#define DECL_TOSPEC_ZERO_TEST(to) DECL_TOSPEC_TEST((to), SYS_TIMESPEC(0, 0), 0, false, false) +/* round up toward K_TICK_MIN */ +#define DECL_NSAT_TOSPEC_TEST(ts) DECL_TOSPEC_TEST(K_TICKS(K_TICK_MIN), (ts), -1, false, false) +/* round up toward next tick boundary */ +#define DECL_ROUND_TOSPEC_TEST(to, ts) DECL_TOSPEC_TEST((to), (ts), 0, false, true) +/* round down toward K_TICK_MAX */ +#define DECL_PSAT_TOSPEC_TEST(ts) DECL_TOSPEC_TEST(K_TICKS(K_TICK_MAX), (ts), 1, false, false) static const struct tospec { k_timeout_t timeout; struct timespec tspec; int saturation; + bool negative; + bool roundup; } tospecs[] = { - {K_NO_WAIT, {INT64_MIN, 0}, -1}, - {K_NO_WAIT, {-1, 0}, -1}, - {K_NO_WAIT, {-1, NSEC_PER_SEC - 1}, -1}, - {K_NO_WAIT, {0, 0}, 0}, - {K_NSEC(0), {0, 0}, 0}, - {K_NSEC(2000000000), {2, 0}, 0}, - {K_USEC(0), {0, 0}, 0}, - {K_USEC(2000000), {2, 0}, 0}, - {K_MSEC(100), {0, 100000000}, 0}, - {K_MSEC(2000), {2, 0}, 0}, - {K_SECONDS(0), {0, 0}, 0}, - {K_SECONDS(1), {1, 0}, 0}, - {K_SECONDS(100), {100, 0}, 0}, - {K_FOREVER, {INT64_MAX, NSEC_PER_SEC - 1}, 0}, + /* negative timespecs should round-up to K_NO_WAIT */ + DECL_TOSPEC_NEGATIVE_TEST(SYS_TIMESPEC(SYS_TIME_T_MIN, 0)), + DECL_TOSPEC_NEGATIVE_TEST(SYS_TIMESPEC(-1, 0)), + DECL_TOSPEC_NEGATIVE_TEST(SYS_TIMESPEC(-1, NSEC_PER_SEC - 1)), + + /* zero-valued timeouts are equivalent to K_NO_WAIT */ + DECL_TOSPEC_ZERO_TEST(K_NSEC(0)), + DECL_TOSPEC_ZERO_TEST(K_USEC(0)), + DECL_TOSPEC_ZERO_TEST(K_MSEC(0)), + DECL_TOSPEC_ZERO_TEST(K_SECONDS(0)), + + /* round up to K_TICK_MIN */ + DECL_NSAT_TOSPEC_TEST(SYS_TIMESPEC(0, 1)), + DECL_NSAT_TOSPEC_TEST(SYS_TIMESPEC(0, 2)), +#if CONFIG_SYS_CLOCK_TICKS_PER_SEC > 1 + DECL_NSAT_TOSPEC_TEST(SYS_TIMESPEC(0, SYS_TICKS_TO_NSECS(K_TICK_MIN))), +#endif + +#if CONFIG_SYS_CLOCK_TICKS_PER_SEC < MHZ(1) + DECL_NSAT_TOSPEC_TEST(SYS_TIMESPEC(0, NSEC_PER_USEC)), +#endif +#if CONFIG_SYS_CLOCK_TICKS_PER_SEC < KHZ(1) + DECL_NSAT_TOSPEC_TEST(SYS_TIMESPEC(0, NSEC_PER_MSEC)), +#endif + +/* round to next tick boundary (low-end) */ +#if CONFIG_SYS_CLOCK_TICKS_PER_SEC > 1 + DECL_ROUND_TOSPEC_TEST(K_TICKS(2), SYS_TICKS_TO_TIMESPEC_PLUS_NSECS(1, 1)), + DECL_ROUND_TOSPEC_TEST(K_TICKS(2), + SYS_TICKS_TO_TIMESPEC_PLUS_NSECS(1, SYS_TICKS_TO_NSECS(1) / 2)), + DECL_ROUND_TOSPEC_TEST(K_TICKS(2), + SYS_TICKS_TO_TIMESPEC_PLUS_NSECS(1, SYS_TICKS_TO_NSECS(1) - 1)), +#endif + +/* exact conversions for large timeouts */ +#ifdef CONFIG_TIMEOUT_64BIT + DECL_TOSPEC_TEST(K_NSEC(2000000000), SYS_TIMESPEC(2, 0), 0, false, false), +#endif + DECL_TOSPEC_TEST(K_USEC(2000000), SYS_TIMESPEC(2, 0), 0, false, false), + DECL_TOSPEC_TEST(K_MSEC(2000), SYS_TIMESPEC(2, 0), 0, false, false), + + DECL_TOSPEC_TEST(K_SECONDS(1), + SYS_TIMESPEC(1, SYS_TICKS_TO_NSECS(CONFIG_SYS_CLOCK_TICKS_PER_SEC)), 0, + false, false), + DECL_TOSPEC_TEST(K_SECONDS(2), + SYS_TIMESPEC(2, SYS_TICKS_TO_NSECS(2 * CONFIG_SYS_CLOCK_TICKS_PER_SEC)), 0, + false, false), + DECL_TOSPEC_TEST(K_SECONDS(100), + SYS_TIMESPEC(100, + SYS_TICKS_TO_NSECS(100 * CONFIG_SYS_CLOCK_TICKS_PER_SEC)), + 0, false, false), + + DECL_TOSPEC_TEST(K_TICKS(1000), SYS_TICKS_TO_TIMESPEC(1000), 0, false, false), + +/* round to next tick boundary (high-end) */ +#if CONFIG_SYS_CLOCK_TICKS_PER_SEC > 1 + DECL_ROUND_TOSPEC_TEST(K_TICKS(1000), SYS_TICKS_TO_TIMESPEC_PLUS_NSECS(999, 1)), + DECL_ROUND_TOSPEC_TEST(K_TICKS(1000), + SYS_TICKS_TO_TIMESPEC_PLUS_NSECS(999, SYS_TICKS_TO_NSECS(1) / 2)), + DECL_ROUND_TOSPEC_TEST(K_TICKS(1000), + SYS_TICKS_TO_TIMESPEC_PLUS_NSECS(999, SYS_TICKS_TO_NSECS(1) - 1)), +#endif + + /* round down toward K_TICK_MAX */ + DECL_PSAT_TOSPEC_TEST(SYS_TICKS_TO_TIMESPEC(K_TICK_MAX)), + + /* K_FOREVER <=> SYS_TIMESPEC_FOREVER */ + DECL_TOSPEC_TEST(K_FOREVER, SYS_TIMESPEC(SYS_TIME_T_MAX, NSEC_PER_SEC - 1), 0, false, + false), }; ZTEST(timeutil_api, test_timespec_from_timeout) { - ztest_test_skip(); /* Provisionally disabled until #92158 is fixed */ - ARRAY_FOR_EACH(tospecs, i) { const struct tospec *const tspec = &tospecs[i]; struct timespec actual; - if (tspec->saturation != 0) { - /* saturation cases are only checked in test_timespec_to_timeout */ + /* + * In this test we only check exact conversions, so skip negative timespecs that + * saturate up to K_NO_WAIT and skip values under SYS_TIMESPEC_MIN and over + * SYS_TIMESPEC_MAX. Also, skip "normal" conversions that just round up to the next + * tick boundary. + */ + if (tspec->negative || (tspec->saturation != 0) || tspec->roundup) { continue; } + TC_PRINT("%zu: ticks: {%lld}, timespec: {%lld, %lld}\n", i, + (long long)tspec->timeout.ticks, (long long)tspec->tspec.tv_sec, + (long long)tspec->tspec.tv_nsec); + timespec_from_timeout(tspec->timeout, &actual); zexpect_true(timespec_equal(&actual, &tspec->tspec), "%d: {%ld, %ld} and {%ld, %ld} are unexpectedly different", i, @@ -329,54 +458,111 @@ ZTEST(timeutil_api, test_timespec_from_timeout) ZTEST(timeutil_api, test_timespec_to_timeout) { - ztest_test_skip(); /* Provisionally disabled until #92158 is fixed */ - ARRAY_FOR_EACH(tospecs, i) { const struct tospec *const tspec = &tospecs[i]; k_timeout_t actual; + struct timespec tick_ts; + struct timespec rem = {}; + TC_PRINT("%zu: ticks: {%lld}, timespec: {%lld, %lld}\n", i, + (long long)tspec->timeout.ticks, (long long)tspec->tspec.tv_sec, + (long long)tspec->tspec.tv_nsec); + + actual = timespec_to_timeout(&tspec->tspec, &rem); if (tspec->saturation == 0) { - /* no saturation / exact match */ - actual = timespec_to_timeout(&tspec->tspec); + /* exact match or rounding up */ + if (!tspec->negative && + (timespec_compare(&tspec->tspec, &SYS_TIMESPEC_NO_WAIT) != 0) && + (timespec_compare(&tspec->tspec, &SYS_TIMESPEC_FOREVER) != 0)) { + __ASSERT(timespec_compare(&tspec->tspec, &SYS_TIMESPEC_MIN) >= 0, + "%zu: timespec: {%lld, %lld} is not greater than " + "SYS_TIMESPEC_MIN", + i, (long long)tspec->tspec.tv_sec, + (long long)tspec->tspec.tv_nsec); + __ASSERT(timespec_compare(&tspec->tspec, &SYS_TIMESPEC_MAX) <= 0, + "%zu: timespec: {%lld, %lld} is not less than " + "SYS_TIMESPEC_MAX", + i, (long long)tspec->tspec.tv_sec, + (long long)tspec->tspec.tv_nsec); + } zexpect_equal(actual.ticks, tspec->timeout.ticks, "%d: {%" PRId64 "} and {%" PRId64 "} are unexpectedly different", i, (int64_t)actual.ticks, (int64_t)tspec->timeout.ticks); - continue; - } - - if ((tspec->saturation < 0) || - (timespec_compare(&tspec->tspec, &k_timeout_limits[0]) < 0)) { - /* K_NO_WAIT saturation */ - actual = timespec_to_timeout(&tspec->tspec); - zexpect_equal(actual.ticks, K_NO_WAIT.ticks, + } else if (tspec->saturation < 0) { + /* K_TICK_MIN saturation */ + __ASSERT(timespec_compare(&tspec->tspec, &SYS_TIMESPEC_MIN) <= 0, + "timespec: {%lld, %lld} is not less than or equal to " + "SYS_TIMESPEC_MIN " + "{%lld, %lld}", + (long long)tspec->tspec.tv_sec, (long long)tspec->tspec.tv_nsec, + (long long)SYS_TIMESPEC_MIN.tv_sec, + (long long)SYS_TIMESPEC_MIN.tv_nsec); + zexpect_equal(actual.ticks, K_TICK_MIN, "%d: {%" PRId64 "} and {%" PRId64 "} are unexpectedly different", - i, (int64_t)actual.ticks, (int64_t)K_NO_WAIT.ticks); - continue; - } - - if ((tspec->saturation > 0) || - (timespec_compare(&tspec->tspec, &k_timeout_limits[1]) > 0)) { - /* K_FOREVER saturation */ - actual = timespec_to_timeout(&tspec->tspec); - zexpect_equal(actual.ticks, K_TICKS_FOREVER, + i, (int64_t)actual.ticks, (int64_t)K_TICK_MIN); + } else if (tspec->saturation > 0) { + /* K_TICK_MAX saturation */ + __ASSERT(timespec_compare(&tspec->tspec, &SYS_TIMESPEC_MAX) >= 0, + "timespec: {%lld, %lld} is not greater than or equal to " + "SYS_TIMESPEC_MAX " + "{%lld, %lld}", + (long long)tspec->tspec.tv_sec, (long long)tspec->tspec.tv_nsec, + (long long)SYS_TIMESPEC_MAX.tv_sec, + (long long)SYS_TIMESPEC_MAX.tv_nsec); + zexpect_equal(actual.ticks, K_TICK_MAX, "%d: {%" PRId64 "} and {%" PRId64 "} are unexpectedly different", - i, (int64_t)actual.ticks, (int64_t)K_TICKS_FOREVER); - continue; + i, (int64_t)actual.ticks, (int64_t)K_TICK_MAX); } + + timespec_from_timeout(tspec->timeout, &tick_ts); + timespec_add(&tick_ts, &rem); + zexpect_true(timespec_equal(&tick_ts, &tspec->tspec), + "%d: {%ld, %ld} and {%ld, %ld} are unexpectedly different", i, + tick_ts.tv_sec, tick_ts.tv_nsec, tspec->tspec.tv_sec, + tspec->tspec.tv_nsec); + } + +#if defined(CONFIG_TIMEOUT_64BIT) && (CONFIG_SYS_CLOCK_TICKS_PER_SEC == 100) + { + struct timespec rem = {}; + k_timeout_t to = K_TICKS(K_TICK_MAX); + /* SYS_TIMESPEC_MAX corresponding K_TICK_MAX with a tick rate of 100 Hz */ + struct timespec ts = SYS_TIMESPEC(92233720368547758LL, 70000000L); + + zexpect_true(K_TIMEOUT_EQ(timespec_to_timeout(&ts, &rem), to), + "timespec_to_timeout(%lld, %lld) != %lld", (long long)ts.tv_sec, + (long long)ts.tv_nsec, (long long)to.ticks); + zexpect_true(timespec_equal(&rem, &SYS_TIMESPEC_NO_WAIT), + "non-zero remainder {%lld, %lld}", (long long)rem.tv_sec, + (long long)rem.tv_nsec); + + TC_PRINT("timespec_to_timeout():\nts: {%lld, %lld} => to: {%lld}, rem: {%lld, " + "%lld}\n", + (long long)ts.tv_sec, (long long)ts.tv_nsec, (long long)to.ticks, + (long long)rem.tv_sec, (long long)rem.tv_nsec); } +#endif } static void *setup(void) { - printk("CONFIG_TIMEOUT_64BIT=%c\n", CONFIG_TIMEOUT_64BIT ? 'y' : 'n'); - printk("K_TICK_MAX: %lld\n", (long long)K_TICK_MAX); - printk("minimum timeout: {%lld, %lld}\n", (long long)k_timeout_limits[0].tv_sec, - (long long)k_timeout_limits[0].tv_nsec); - printk("maximum timeout: {%lld, %lld}\n", (long long)k_timeout_limits[1].tv_sec, - (long long)k_timeout_limits[1].tv_nsec); + TC_PRINT("CONFIG_SYS_CLOCK_TICKS_PER_SEC=%d\n", CONFIG_SYS_CLOCK_TICKS_PER_SEC); + TC_PRINT("CONFIG_TIMEOUT_64BIT=%c\n", IS_ENABLED(CONFIG_TIMEOUT_64BIT) ? 'y' : 'n'); + TC_PRINT("K_TICK_MIN: %lld\n", (long long)K_TICK_MIN); + TC_PRINT("K_TICK_MAX: %lld\n", (long long)K_TICK_MAX); + TC_PRINT("SYS_TIMESPEC_MIN: {%lld, %lld}\n", (long long)SYS_TIMESPEC_MIN.tv_sec, + (long long)SYS_TIMESPEC_MIN.tv_nsec); + TC_PRINT("SYS_TIMESPEC_MAX: {%lld, %lld}\n", (long long)SYS_TIMESPEC_MAX.tv_sec, + (long long)SYS_TIMESPEC_MAX.tv_nsec); + TC_PRINT("INT64_MIN: %lld\n", (long long)INT64_MIN); + TC_PRINT("INT64_MAX: %lld\n", (long long)INT64_MAX); + PRINT_LINE; + + /* check numerical values corresponding to K_TICK_MAX */ + zassert_equal(K_TICK_MAX, IS_ENABLED(CONFIG_TIMEOUT_64BIT) ? INT64_MAX : UINT32_MAX - 1); return NULL; } diff --git a/tests/lib/timespec_util/testcase.yaml b/tests/lib/timespec_util/testcase.yaml index d69c5bb755fb0..13ad4c1b1433b 100644 --- a/tests/lib/timespec_util/testcase.yaml +++ b/tests/lib/timespec_util/testcase.yaml @@ -1,6 +1,5 @@ # FIXME: this should be under tests/unit/timeutil but will not work due to #90029 common: - filter: not CONFIG_NATIVE_LIBC tags: - timeutils # 1 tier0 platform per supported architecture @@ -8,29 +7,85 @@ common: - arch - simulation integration_platforms: + - native_sim - native_sim/native/64 tests: libraries.timespec_utils: {} - libraries.timespec_utils.speed: + libraries.timespec_utils.timeout_32bit: extra_configs: + - CONFIG_TIMEOUT_64BIT=n + + # Using platform_allow below because some platforms such as qemu_cortex_r5/zynqmp_rpu throw + # build errors when the timer tick frequency is not divisible by the system tick frequency. + # + # The test configurations below are mainly for numerical coverage and correctness. + libraries.timespec_utils.speed.timeout_32bit: + platform_allow: + - native_sim + - native_sim/native/64 + extra_configs: + - CONFIG_TIMEOUT_64BIT=n + - CONFIG_SPEED_OPTIMIZATIONS=y + libraries.timespec_utils.speed.timeout_64bit: + platform_allow: + - native_sim + - native_sim/native/64 + extra_configs: + - CONFIG_TIMEOUT_64BIT=y - CONFIG_SPEED_OPTIMIZATIONS=y - libraries.timespec_utils.armclang_std_libc: - toolchain_allow: armclang + libraries.timespec_utils.low_tick_rate.timeout_32bit: + platform_allow: + - native_sim + - native_sim/native/64 + extra_configs: + - CONFIG_TIMEOUT_64BIT=n + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=1 + libraries.timespec_utils.low_tick_rate.timeout_64bit: + platform_allow: + - native_sim + - native_sim/native/64 + extra_configs: + - CONFIG_TIMEOUT_64BIT=y + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=1 + libraries.timespec_utils.high_tick_rate.timeout_32bit: + platform_allow: + - native_sim + - native_sim/native/64 + extra_configs: + - CONFIG_TIMEOUT_64BIT=n + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000000 + libraries.timespec_utils.high_tick_rate.timeout_64bit: + platform_allow: + - native_sim + - native_sim/native/64 extra_configs: - - CONFIG_ARMCLANG_STD_LIBC=y - libraries.timespec_utils.arcmwdtlib: - toolchain_allow: arcmwdt + - CONFIG_TIMEOUT_64BIT=y + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000000 + libraries.timespec_utils.32k_tick_rate.timeout_32bit: + platform_allow: + - native_sim + - native_sim/native/64 extra_configs: - - CONFIG_ARCMWDT_LIBC=y - libraries.timespec_utils.minimal: + - CONFIG_TIMEOUT_64BIT=n + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 + libraries.timespec_utils.32k_tick_rate.timeout_64bit: + platform_allow: + - native_sim + - native_sim/native/64 extra_configs: - - CONFIG_MINIMAL_LIBC=y - libraries.timespec_utils.newlib: - filter: TOOLCHAIN_HAS_NEWLIB == 1 + - CONFIG_TIMEOUT_64BIT=y + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 + libraries.timespec_utils.prime_tick_rate.timeout_32bit: + platform_allow: + - native_sim + - native_sim/native/64 extra_configs: - - CONFIG_NEWLIB_LIBC=y - libraries.timespec_utils.picolibc: - tags: picolibc - filter: CONFIG_PICOLIBC_SUPPORTED + - CONFIG_TIMEOUT_64BIT=n + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=10007 + libraries.timespec_utils.prime_tick_rate.timeout_64bit: + platform_allow: + - native_sim + - native_sim/native/64 extra_configs: - - CONFIG_PICOLIBC=y + - CONFIG_TIMEOUT_64BIT=y + - CONFIG_SYS_CLOCK_TICKS_PER_SEC=10007 diff --git a/tests/misc/kconfigoptions/native_sim.overlay b/tests/misc/kconfigoptions/native_sim.overlay index 1da8f728393f1..f65a9104bd58b 100644 --- a/tests/misc/kconfigoptions/native_sim.overlay +++ b/tests/misc/kconfigoptions/native_sim.overlay @@ -4,6 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - &flashcontroller0 { +&flashcontroller0 { reg = <0x00000001 4194304>; }; diff --git a/tests/net/dhcpv6/src/main.c b/tests/net/dhcpv6/src/main.c index a7c396cc07888..396718c3aee7e 100644 --- a/tests/net/dhcpv6/src/main.c +++ b/tests/net/dhcpv6/src/main.c @@ -636,7 +636,7 @@ ZTEST(dhcpv6_tests, test_input_reject_client_initiated_messages) set_generic_client_options); zassert_not_null(pkt, "Failed to create fake pkt"); - result = net_ipv6_input(pkt, false); + result = net_ipv6_input(pkt); zassert_equal(result, NET_DROP, "Should've drop the message"); net_pkt_unref(pkt); @@ -719,7 +719,7 @@ ZTEST(dhcpv6_tests, test_input_advertise) set_advertise_options); zassert_not_null(pkt, "Failed to create pkt"); - result = net_ipv6_input(pkt, false); + result = net_ipv6_input(pkt); switch (state) { case NET_DHCPV6_SOLICITING: @@ -826,7 +826,7 @@ ZTEST(dhcpv6_tests, test_input_reply) set_reply_options); zassert_not_null(pkt, "Failed to create pkt"); - result = net_ipv6_input(pkt, false); + result = net_ipv6_input(pkt); switch (state) { case NET_DHCPV6_CONFIRMING: @@ -891,7 +891,7 @@ static void test_solicit_expect_request_send_reply(struct net_if *iface, set_reply_options); zassert_not_null(reply, "Failed to create pkt"); - result = net_ipv6_input(reply, false); + result = net_ipv6_input(reply); zassert_equal(result, NET_OK, "Message should've been processed"); /* Verify client state */ @@ -936,7 +936,7 @@ static void test_solicit_expect_solicit_send_advertise(struct net_if *iface, set_advertise_options); zassert_not_null(reply, "Failed to create pkt"); - result = net_ipv6_input(reply, false); + result = net_ipv6_input(reply); zassert_equal(result, NET_OK, "Message should've been processed"); /* Verify client state */ @@ -993,7 +993,7 @@ static void expect_request_send_reply(struct net_if *iface, struct net_pkt *pkt) set_reply_options); zassert_not_null(reply, "Failed to create pkt"); - result = net_ipv6_input(reply, false); + result = net_ipv6_input(reply); zassert_equal(result, NET_OK, "Message should've been processed"); k_sem_give(&test_ctx.exchange_complete_sem); @@ -1013,7 +1013,7 @@ static void expect_solicit_send_advertise(struct net_if *iface, struct net_pkt * set_advertise_options); zassert_not_null(reply, "Failed to create pkt"); - result = net_ipv6_input(reply, false); + result = net_ipv6_input(reply); zassert_equal(result, NET_OK, "Message should've been processed"); } @@ -1058,7 +1058,7 @@ static void test_confirm_expect_confirm_send_reply(struct net_if *iface, set_reply_options); zassert_not_null(reply, "Failed to create pkt"); - result = net_ipv6_input(reply, false); + result = net_ipv6_input(reply); zassert_equal(result, NET_OK, "Message should've been processed"); /* Verify client state */ @@ -1127,7 +1127,7 @@ static void test_rebind_expect_rebind_send_reply(struct net_if *iface, set_reply_options); zassert_not_null(reply, "Failed to create pkt"); - result = net_ipv6_input(reply, false); + result = net_ipv6_input(reply); zassert_equal(result, NET_OK, "Message should've been processed"); /* Verify client state */ @@ -1201,7 +1201,7 @@ static void test_renew_expect_renew_send_reply(struct net_if *iface, set_reply_options); zassert_not_null(reply, "Failed to create pkt"); - result = net_ipv6_input(reply, false); + result = net_ipv6_input(reply); zassert_equal(result, NET_OK, "Message should've been processed"); /* Verify client state */ diff --git a/tests/net/icmpv4/src/main.c b/tests/net/icmpv4/src/main.c index 36e9436065dba..caddef589c4c8 100644 --- a/tests/net/icmpv4/src/main.c +++ b/tests/net/icmpv4/src/main.c @@ -452,7 +452,7 @@ static void icmpv4_send_echo_req(void) zassert_true(false, "EchoRequest packet prep failed"); } - if (net_ipv4_input(pkt, false)) { + if (net_ipv4_input(pkt)) { net_pkt_unref(pkt); zassert_true(false, "Failed to send"); } @@ -474,7 +474,7 @@ static void icmpv4_send_echo_rep(void) zassert_true(false, "EchoReply packet prep failed"); } - if (net_ipv4_input(pkt, false)) { + if (net_ipv4_input(pkt)) { net_pkt_unref(pkt); zassert_true(false, "Failed to send"); } @@ -494,7 +494,7 @@ ZTEST(net_icmpv4, test_icmpv4_send_echo_req_opt) zassert_true(false, "EchoRequest with opts packet prep failed"); } - if (net_ipv4_input(pkt, false)) { + if (net_ipv4_input(pkt)) { net_pkt_unref(pkt); zassert_true(false, "Failed to send"); } @@ -510,7 +510,7 @@ ZTEST(net_icmpv4, test_send_echo_req_bad_opt) "EchoRequest with bad opts packet prep failed"); } - if (net_ipv4_input(pkt, false)) { + if (net_ipv4_input(pkt)) { net_pkt_unref(pkt); } } diff --git a/tests/net/igmp/src/main.c b/tests/net/igmp/src/main.c index e2f201dd4eeef..ad25ff55eeb5d 100644 --- a/tests/net/igmp/src/main.c +++ b/tests/net/igmp/src/main.c @@ -596,7 +596,7 @@ static void igmp_send_query(bool is_imgpv3) pkt = prepare_igmp_query(net_iface, is_imgpv3); zassert_not_null(pkt, "IGMPv2 query packet prep failed"); - zassert_equal(net_ipv4_input(pkt, false), NET_OK, "Failed to send"); + zassert_equal(net_ipv4_input(pkt), NET_OK, "Failed to send"); zassert_ok(k_sem_take(&wait_data, K_MSEC(WAIT_TIME)), "Timeout while waiting query event"); diff --git a/tests/net/ipv6/src/main.c b/tests/net/ipv6/src/main.c index cf22e0652e8b4..2708cd581ef12 100644 --- a/tests/net/ipv6/src/main.c +++ b/tests/net/ipv6/src/main.c @@ -1735,7 +1735,7 @@ static enum net_verdict recv_msg(struct in6_addr *src, struct in6_addr *dst) /* We by-pass the normal packet receiving flow in this case in order * to simplify the testing. */ - return net_ipv6_input(pkt, false); + return net_ipv6_input(pkt); } static int send_msg(struct in6_addr *src, struct in6_addr *dst) diff --git a/tests/net/lib/dns_cache/prj.conf b/tests/net/lib/dns_cache/prj.conf index 023d41a029a49..56444ac5cac4d 100644 --- a/tests/net/lib/dns_cache/prj.conf +++ b/tests/net/lib/dns_cache/prj.conf @@ -10,3 +10,4 @@ CONFIG_DNS_RESOLVER_CACHE=y CONFIG_ENTROPY_GENERATOR=y CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_ZTEST_STACK_SIZE=1280 diff --git a/tests/net/lib/ocpp/src/main.c b/tests/net/lib/ocpp/src/main.c index 179dd824148c7..969a710679dad 100644 --- a/tests/net/lib/ocpp/src/main.c +++ b/tests/net/lib/ocpp/src/main.c @@ -85,7 +85,7 @@ int test_ocpp_init(void) net_dhcpv4_start(net_if_get_default()); - /* wait for device dhcp ip recive */ + /* wait for device dhcp ip receive */ k_sleep(K_SECONDS(3)); ret = ocpp_init(&cpi, diff --git a/tests/net/tcp/src/main.c b/tests/net/tcp/src/main.c index b982ad5fce83f..2c0cfcd9ef2cc 100644 --- a/tests/net/tcp/src/main.c +++ b/tests/net/tcp/src/main.c @@ -1439,8 +1439,8 @@ static void handle_data_fin1_test(sa_family_t af, struct tcphdr *th) "%s:%d unexpected sequence number in original FIN, got %d", __func__, __LINE__, get_rel_seq(th)); zassert_true(ntohl(th->th_ack) == 2, - "%s:%d unexpected acknowlegdement in original FIN, got %d", - __func__, __LINE__, ntohl(th->th_ack)); + "%s:%d unexpected acknowledgment in original FIN, got %d", __func__, + __LINE__, ntohl(th->th_ack)); t_state = T_FIN_1; /* retransmit the data that we already send*/ reply = prepare_data_packet(af, htons(MY_PORT), @@ -1457,7 +1457,7 @@ static void handle_data_fin1_test(sa_family_t af, struct tcphdr *th) "%s:%i unexpected sequence number in retransmitted FIN, got %d", __func__, __LINE__, get_rel_seq(th)); zassert_true(ntohl(th->th_ack) == 2, - "%s:%i unexpected acknowlegdement in retransmitted FIN, got %d", + "%s:%i unexpected acknowledgment in retransmitted FIN, got %d", __func__, __LINE__, ntohl(th->th_ack)); ack = ack + 1U; t_state = T_FIN_2; @@ -1575,8 +1575,8 @@ static void handle_data_during_fin1_test(sa_family_t af, struct tcphdr *th) "%s:%d unexpected sequence number in original FIN, got %d", __func__, __LINE__, get_rel_seq(th)); zassert_true(ntohl(th->th_ack) == 1, - "%s:%d unexpected acknowlegdement in original FIN, got %d", - __func__, __LINE__, ntohl(th->th_ack)); + "%s:%d unexpected acknowledgment in original FIN, got %d", __func__, + __LINE__, ntohl(th->th_ack)); ack = ack + 1U; diff --git a/tests/net/traffic_class/testcase.yaml b/tests/net/traffic_class/testcase.yaml index 21cec521c384b..c90df9080ab5e 100644 --- a/tests/net/traffic_class/testcase.yaml +++ b/tests/net/traffic_class/testcase.yaml @@ -12,30 +12,6 @@ tests: extra_configs: - CONFIG_NET_TC_TX_COUNT=1 - CONFIG_NET_TC_RX_COUNT=1 - net.traffic_class.2: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=2 - - CONFIG_NET_TC_RX_COUNT=2 - net.traffic_class.3: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=3 - - CONFIG_NET_TC_RX_COUNT=3 - net.traffic_class.4: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=4 - - CONFIG_NET_TC_RX_COUNT=4 - net.traffic_class.5: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=5 - - CONFIG_NET_TC_RX_COUNT=5 - net.traffic_class.6: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=6 - - CONFIG_NET_TC_RX_COUNT=6 - net.traffic_class.7: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=7 - - CONFIG_NET_TC_RX_COUNT=7 net.traffic_class.8: extra_configs: - CONFIG_NET_TC_TX_COUNT=8 @@ -45,225 +21,18 @@ tests: extra_configs: - CONFIG_NET_TC_TX_COUNT=2 - CONFIG_NET_TC_RX_COUNT=1 - net.traffic_class.3_no_rx: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=3 - - CONFIG_NET_TC_RX_COUNT=1 - net.traffic_class.4_no_rx: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=4 - - CONFIG_NET_TC_RX_COUNT=1 - net.traffic_class.5_no_rx: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=5 - - CONFIG_NET_TC_RX_COUNT=1 - net.traffic_class.6_no_rx: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=6 - - CONFIG_NET_TC_RX_COUNT=1 - net.traffic_class.7_no_rx: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=7 - - CONFIG_NET_TC_RX_COUNT=1 - net.traffic_class.8_no_rx: - extra_configs: - - CONFIG_NET_TC_TX_COUNT=8 - - CONFIG_NET_TC_RX_COUNT=1 # TX one queue, RX multi queue net.traffic_class.2_no_tx: extra_configs: - CONFIG_NET_TC_RX_COUNT=2 - CONFIG_NET_TC_TX_COUNT=1 - net.traffic_class.3_no_tx: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=3 - - CONFIG_NET_TC_TX_COUNT=1 - net.traffic_class.4_no_tx: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=4 - - CONFIG_NET_TC_TX_COUNT=1 - net.traffic_class.5_no_tx: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=5 - - CONFIG_NET_TC_TX_COUNT=1 - net.traffic_class.6_no_tx: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=6 - - CONFIG_NET_TC_TX_COUNT=1 - net.traffic_class.7_no_tx: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=7 - - CONFIG_NET_TC_TX_COUNT=1 - net.traffic_class.8_no_tx: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=8 - - CONFIG_NET_TC_TX_COUNT=1 - # Then test some hybrid combinations. - net.traffic_class.tx_2_rx_3: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=3 - - CONFIG_NET_TC_TX_COUNT=2 - net.traffic_class.tx_3_rx_8: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=8 - - CONFIG_NET_TC_TX_COUNT=3 - net.traffic_class.rx_4_tx_8: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=4 - - CONFIG_NET_TC_TX_COUNT=8 - net.traffic_class.rx_5_tx_7: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=5 - - CONFIG_NET_TC_TX_COUNT=7 - net.traffic_class.tx_6_rx_2: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=2 - - CONFIG_NET_TC_TX_COUNT=6 - net.traffic_class.tx_7_rx_5: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=5 - - CONFIG_NET_TC_TX_COUNT=7 - net.traffic_class.tx_8_rx_7: - extra_configs: - - CONFIG_NET_TC_RX_COUNT=7 - - CONFIG_NET_TC_TX_COUNT=8 net.traffic_class.2_sr_ab: extra_configs: - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - CONFIG_NET_TC_TX_COUNT=2 - CONFIG_NET_TC_RX_COUNT=2 - net.traffic_class.3_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_TX_COUNT=3 - - CONFIG_NET_TC_RX_COUNT=3 - net.traffic_class.4_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_TX_COUNT=4 - - CONFIG_NET_TC_RX_COUNT=4 - net.traffic_class.5_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_TX_COUNT=5 - - CONFIG_NET_TC_RX_COUNT=5 - net.traffic_class.6_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_TX_COUNT=6 - - CONFIG_NET_TC_RX_COUNT=6 - net.traffic_class.7_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_TX_COUNT=7 - - CONFIG_NET_TC_RX_COUNT=7 - net.traffic_class.8_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_TX_COUNT=8 - - CONFIG_NET_TC_RX_COUNT=8 - net.traffic_class.tx_2_rx_3_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_RX_COUNT=3 - - CONFIG_NET_TC_TX_COUNT=2 - net.traffic_class.tx_3_rx_8_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_RX_COUNT=8 - - CONFIG_NET_TC_TX_COUNT=3 - net.traffic_class.rx_4_tx_8_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_RX_COUNT=4 - - CONFIG_NET_TC_TX_COUNT=8 - net.traffic_class.rx_5_tx_7_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_RX_COUNT=5 - - CONFIG_NET_TC_TX_COUNT=7 - net.traffic_class.tx_6_rx_2_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_RX_COUNT=2 - - CONFIG_NET_TC_TX_COUNT=6 - net.traffic_class.tx_7_rx_5_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_RX_COUNT=5 - - CONFIG_NET_TC_TX_COUNT=7 - net.traffic_class.tx_8_rx_7_sr_ab: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_A_AND_B=y - - CONFIG_NET_TC_RX_COUNT=7 - - CONFIG_NET_TC_TX_COUNT=8 net.traffic_class.2_sr_b: extra_configs: - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - CONFIG_NET_TC_TX_COUNT=2 - CONFIG_NET_TC_RX_COUNT=2 - net.traffic_class.3_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_TX_COUNT=3 - - CONFIG_NET_TC_RX_COUNT=3 - net.traffic_class.4_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_TX_COUNT=4 - - CONFIG_NET_TC_RX_COUNT=4 - net.traffic_class.5_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_TX_COUNT=5 - - CONFIG_NET_TC_RX_COUNT=5 - net.traffic_class.6_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_TX_COUNT=6 - - CONFIG_NET_TC_RX_COUNT=6 - net.traffic_class.7_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_TX_COUNT=7 - - CONFIG_NET_TC_RX_COUNT=7 - net.traffic_class.8_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_TX_COUNT=8 - - CONFIG_NET_TC_RX_COUNT=8 - net.traffic_class.tx_2_rx_3_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_RX_COUNT=3 - - CONFIG_NET_TC_TX_COUNT=2 - net.traffic_class.tx_3_rx_8_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_RX_COUNT=8 - - CONFIG_NET_TC_TX_COUNT=3 - net.traffic_class.rx_4_tx_8_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_RX_COUNT=4 - - CONFIG_NET_TC_TX_COUNT=8 - net.traffic_class.rx_5_tx_7_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_RX_COUNT=5 - - CONFIG_NET_TC_TX_COUNT=7 - net.traffic_class.tx_6_rx_2_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_RX_COUNT=2 - - CONFIG_NET_TC_TX_COUNT=6 - net.traffic_class.tx_7_rx_5_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_RX_COUNT=5 - - CONFIG_NET_TC_TX_COUNT=7 - net.traffic_class.tx_8_rx_7_sr_b: - extra_configs: - - CONFIG_NET_TC_MAPPING_SR_CLASS_B_ONLY=y - - CONFIG_NET_TC_RX_COUNT=7 - - CONFIG_NET_TC_TX_COUNT=8 diff --git a/tests/net/virtual/src/main.c b/tests/net/virtual/src/main.c index 618b80d2c2676..218f805c980af 100644 --- a/tests/net/virtual/src/main.c +++ b/tests/net/virtual/src/main.c @@ -1067,9 +1067,9 @@ static void test_virtual_recv_data_from_tunnel(int remote_ip, net_pkt_cursor_init(outer); if (peer_addr.sa_family == AF_INET) { - verdict = net_ipv4_input(outer, false); + verdict = net_ipv4_input(outer); } else { - verdict = net_ipv6_input(outer, false); + verdict = net_ipv6_input(outer); } if (expected_ok) { diff --git a/tests/net/wifi/configs/testcase.yaml b/tests/net/wifi/configs/testcase.yaml index f57e3da6fedad..80ea0ff4b14d5 100644 --- a/tests/net/wifi/configs/testcase.yaml +++ b/tests/net/wifi/configs/testcase.yaml @@ -65,7 +65,7 @@ tests: - CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP=y wifi.build.disable_advanced_feat: extra_configs: - - CONFIG_WIFI_NM_WPA_SUPPLICANT_ADVANCED_FEATURES=y + - CONFIG_WIFI_NM_WPA_SUPPLICANT_ADVANCED_FEATURES=n wifi.build.enterprise_runtime: extra_configs: - CONFIG_WIFI_SHELL_RUNTIME_CERTIFICATES=y diff --git a/tests/net/wifi/wifi_nm/Kconfig b/tests/net/wifi/wifi_nm/Kconfig index 57e1217d10a0a..b59d45fc0b793 100644 --- a/tests/net/wifi/wifi_nm/Kconfig +++ b/tests/net/wifi/wifi_nm/Kconfig @@ -1,4 +1,4 @@ -# Configuration opions for Wi-Fi test +# Configuration options for Wi-Fi test # Copyright (c) 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 diff --git a/tests/posix/common/src/mutex.c b/tests/posix/common/src/mutex.c index 40987d50297a0..20b992620eb8a 100644 --- a/tests/posix/common/src/mutex.c +++ b/tests/posix/common/src/mutex.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -182,7 +183,7 @@ static void *test_mutex_timedlock_fn(void *arg) struct timespec time_point; pthread_mutex_t *mtx = (pthread_mutex_t *)arg; - zassume_ok(clock_gettime(CLOCK_MONOTONIC, &time_point)); + zassume_ok(clock_gettime(CLOCK_REALTIME, &time_point)); timespec_add_ms(&time_point, TIMEDLOCK_TIMEOUT_MS); return INT_TO_POINTER(pthread_mutex_timedlock(mtx, &time_point)); diff --git a/tests/posix/common/src/pthread.c b/tests/posix/common/src/pthread.c index 035730ee4dc73..96a16f7ddb33b 100644 --- a/tests/posix/common/src/pthread.c +++ b/tests/posix/common/src/pthread.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -409,8 +410,8 @@ ZTEST(pthread, test_pthread_timedjoin) }; /* setup timespecs when the thread is still running and when it is done */ - clock_gettime(CLOCK_MONOTONIC, ¬_done); - clock_gettime(CLOCK_MONOTONIC, &done); + clock_gettime(CLOCK_REALTIME, ¬_done); + clock_gettime(CLOCK_REALTIME, &done); not_done.tv_nsec += sleep_duration_ms / 2 * NSEC_PER_MSEC; done.tv_nsec += sleep_duration_ms * 1.5 * NSEC_PER_MSEC; while (not_done.tv_nsec >= NSEC_PER_SEC) { diff --git a/tests/posix/fs/src/test_fs_stat.c b/tests/posix/fs/src/test_fs_stat.c index 9aa7db128917e..2850368de4af4 100644 --- a/tests/posix/fs/src/test_fs_stat.c +++ b/tests/posix/fs/src/test_fs_stat.c @@ -105,3 +105,60 @@ ZTEST(posix_fs_stat_test, test_fs_stat_dir) /* note: for posix compatibility should should actually work */ zassert_not_equal(0, stat(TEST_ROOT, &buf)); } + +/** + * @brief Test fstat command on file + * + * @details Tests file in root, file in directroy, and empty file + */ +ZTEST(posix_fs_stat_test, test_fs_fstat_file) +{ + struct stat buf; + + int test_file_fd = open(TEST_FILE, O_RDONLY); + int dir_file_fd = open(TEST_DIR_FILE, O_RDONLY); + int empty_file_fd = open(TEST_EMPTY_FILE, O_RDONLY); + + zassert_not_equal(-1, test_file_fd); + zassert_equal(0, fstat(test_file_fd, &buf)); + zassert_equal(TEST_FILE_SIZE, buf.st_size); + zassert_equal(S_IFREG, buf.st_mode); + close(test_file_fd); + + zassert_not_equal(-1, dir_file_fd); + zassert_equal(0, fstat(dir_file_fd, &buf)); + zassert_equal(TEST_DIR_FILE_SIZE, buf.st_size); + zassert_equal(S_IFREG, buf.st_mode); + close(dir_file_fd); + + zassert_not_equal(-1, empty_file_fd); + zassert_equal(0, fstat(empty_file_fd, &buf)); + zassert_equal(0, buf.st_size); + zassert_equal(S_IFREG, buf.st_mode); + close(empty_file_fd); +} + +/** + * @brief Test fstat command on dir + * + * @details Tests if we can retrieve stastics for a directory. + */ +ZTEST(posix_fs_stat_test, test_fs_fstat_dir) +{ + struct stat buf; + + int fd = open(TEST_DIR, O_RDONLY); + + /* + * if this failed it means open doesn't support directories + * so skip the rest of the test + */ + if (fd == -1) { + ztest_test_skip(); + } + + zassert_equal(0, fstat(fd, &buf)); + zassert_equal(0, buf.st_size); + zassert_equal(S_IFDIR, buf.st_mode); + close(fd); +} diff --git a/tests/posix/headers/src/types_h.c b/tests/posix/headers/src/types_h.c new file mode 100644 index 0000000000000..09ba5eab85aec --- /dev/null +++ b/tests/posix/headers/src/types_h.c @@ -0,0 +1,12 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* _GNU_SOURCE causes extra headers to be included and can cause dependency + * loops + */ +#define _GNU_SOURCE + +#include diff --git a/tests/subsys/cpu_freq/cpu_freq_soc/CMakeLists.txt b/tests/subsys/cpu_freq/cpu_freq_soc/CMakeLists.txt new file mode 100644 index 0000000000000..10115a1c9ff16 --- /dev/null +++ b/tests/subsys/cpu_freq/cpu_freq_soc/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(cpu_freq_soc_test) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/subsys/cpu_freq/cpu_freq_soc/prj.conf b/tests/subsys/cpu_freq/cpu_freq_soc/prj.conf new file mode 100644 index 0000000000000..526815f4ad574 --- /dev/null +++ b/tests/subsys/cpu_freq/cpu_freq_soc/prj.conf @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_LOG=y +CONFIG_ZTEST=y + +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_LOG_LEVEL_DBG=y +CONFIG_CPU_FREQ_POLICY_ON_DEMAND=y +# Long interval so test can run without automatic frequency changes +CONFIG_CPU_FREQ_INTERVAL_MS=1000000 diff --git a/tests/subsys/cpu_freq/cpu_freq_soc/src/main.c b/tests/subsys/cpu_freq/cpu_freq_soc/src/main.c new file mode 100644 index 0000000000000..a57d6c81dc45b --- /dev/null +++ b/tests/subsys/cpu_freq/cpu_freq_soc/src/main.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(cpu_freq_soc_test, LOG_LEVEL_INF); + +const struct pstate *soc_pstates_dt[] = { + DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(performance_states), PSTATE_DT_GET, (,))}; + +/* + * Test SoC integration of CPU Freq + */ +ZTEST(cpu_freq_soc, test_soc_pstates) +{ + int ret; + + zassert_true(ARRAY_SIZE(soc_pstates_dt) > 0, "No p-states defined in devicetree"); + + LOG_INF("%d p-states defined for %s", ARRAY_SIZE(soc_pstates_dt), CONFIG_BOARD_TARGET); + + zassert_equal(cpu_freq_pstate_set(NULL), -EINVAL, "Expected -EINVAL for NULL pstate"); + + for (int i = 0; i < ARRAY_SIZE(soc_pstates_dt); i++) { + const struct pstate *state = soc_pstates_dt[i]; + + /* Set performance state using pstate driver */ + ret = cpu_freq_pstate_set(state); + zassert_equal(ret, 0, "Failed to set p-state %d", i); + } +} + +ZTEST_SUITE(cpu_freq_soc, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/subsys/cpu_freq/cpu_freq_soc/testcase.yaml b/tests/subsys/cpu_freq/cpu_freq_soc/testcase.yaml new file mode 100644 index 0000000000000..dc740e4ac3732 --- /dev/null +++ b/tests/subsys/cpu_freq/cpu_freq_soc/testcase.yaml @@ -0,0 +1,9 @@ +tests: + subsys.cpu_freq.soc: + platform_allow: + - native_sim + - native_sim/native/64 + tags: cpu_freq + integration_platforms: + - native_sim + - native_sim/native/64 diff --git a/tests/subsys/cpu_freq/policies/on_demand/CMakeLists.txt b/tests/subsys/cpu_freq/policies/on_demand/CMakeLists.txt new file mode 100644 index 0000000000000..dbe544567b88c --- /dev/null +++ b/tests/subsys/cpu_freq/policies/on_demand/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(cpu_freq_on_demand_test) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/subsys/cpu_freq/policies/on_demand/prj.conf b/tests/subsys/cpu_freq/policies/on_demand/prj.conf new file mode 100644 index 0000000000000..c1ffad127ded5 --- /dev/null +++ b/tests/subsys/cpu_freq/policies/on_demand/prj.conf @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_LOG=y +CONFIG_ZTEST=y + +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_LOG_LEVEL_DBG=y +CONFIG_CPU_LOAD_LOG_LEVEL_DBG=y +CONFIG_CPU_FREQ_POLICY_ON_DEMAND=y +# Long interval so test can run without automatic frequency changes +CONFIG_CPU_FREQ_INTERVAL_MS=1000000 diff --git a/tests/subsys/cpu_freq/policies/on_demand/src/main.c b/tests/subsys/cpu_freq/policies/on_demand/src/main.c new file mode 100644 index 0000000000000..afdc25221513e --- /dev/null +++ b/tests/subsys/cpu_freq/policies/on_demand/src/main.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(cpu_freq_on_demand_test, LOG_LEVEL_INF); + +#define WAIT_US 1000 + +/* + * Test APIs of on_demand CPU frequency policy. + */ +ZTEST(cpu_freq_on_demand, test_pstates) +{ + int ret; + const struct pstate *test_pstate; + + /* Test invalid arg */ + zassert_equal(cpu_freq_policy_select_pstate(NULL), -EINVAL, + "Expected -EINVAL for NULL pstate_out"); + + /* Simulate high-load and get pstate */ + k_busy_wait(WAIT_US); + + /* Get pstate after a moment of high-load */ + ret = cpu_freq_policy_select_pstate(&test_pstate); + zassert_equal(ret, 0, "Expected success from cpu_freq_policy_select_pstate"); + + int prev_threshold = test_pstate->load_threshold; + + /* Simulate low-load by sleeping, then getting pstate*/ + k_sleep(K_USEC(WAIT_US)); + + /* Get pstate after a moment of low-load between calls to policy */ + ret = cpu_freq_policy_select_pstate(&test_pstate); + zassert_equal(ret, 0, "Expected success from cpu_freq_policy_select_pstate"); + + zassert_not_equal(test_pstate->load_threshold, prev_threshold, + "Expected different p-state after sleep"); +} + +ZTEST_SUITE(cpu_freq_on_demand, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/subsys/cpu_freq/policies/on_demand/testcase.yaml b/tests/subsys/cpu_freq/policies/on_demand/testcase.yaml new file mode 100644 index 0000000000000..46692d472fd10 --- /dev/null +++ b/tests/subsys/cpu_freq/policies/on_demand/testcase.yaml @@ -0,0 +1,9 @@ +tests: + subsys.cpu_freq.policies.on_demand: + platform_allow: + - native_sim + - native_sim/native/64 + tags: cpu_freq + integration_platforms: + - native_sim + - native_sim/native/64 diff --git a/tests/subsys/crc/CMakeLists.txt b/tests/subsys/crc/CMakeLists.txt new file mode 100644 index 0000000000000..4046fc42d0c25 --- /dev/null +++ b/tests/subsys/crc/CMakeLists.txt @@ -0,0 +1,6 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) + +project(subsys_crc_test) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/subsys/crc/prj.conf b/tests/subsys/crc/prj.conf new file mode 100644 index 0000000000000..d187aba6a129d --- /dev/null +++ b/tests/subsys/crc/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_CRC=y +CONFIG_LOG=y diff --git a/tests/subsys/crc/src/main.c b/tests/subsys/crc/src/main.c new file mode 100644 index 0000000000000..b01693599bfe8 --- /dev/null +++ b/tests/subsys/crc/src/main.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +/* Define result of CRC computation */ +#define RESULT_CRC8 0xB2 + +/** + * @brief Test crc8 works + */ +ZTEST(crc_subsys, test_crc_8) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc8(data, sizeof(data), CRC8_REFLECT_POLY, 0x00, true), RESULT_CRC8); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_CCITT 0x4D + +/** + * @brief Test crc8_ccitt works + */ +ZTEST(crc_subsys, test_crc_8_ccitt) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc8_ccitt(0x00, data, sizeof(data)), RESULT_CRC8_CCITT); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_ROHC 0xB2 + +/** + * @brief Test that crc_8_rohc works + */ +ZTEST(crc_subsys, test_crc_8_rohc) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc8_rohc(0x00, data, sizeof(data)), RESULT_CRC8_ROHC); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16 0xE58F + +/** + * @brief Test that crc_16 works + */ +ZTEST(crc_subsys, test_crc_16) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16(CRC16_POLY, CRC16_INIT_VAL, data, sizeof(data)), RESULT_CRC16); +} +/* Define result of CRC computation */ +#define RESULT_CRC16_REFLECT 0xD543 + +/** + * @brief Test that crc_16_reflect works + */ +ZTEST(crc_subsys, test_crc_16_reflect) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_reflect(CRC16_REFLECT_POLY, CRC16_INIT_VAL, data, sizeof(data)), + RESULT_CRC16_REFLECT); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16_ANSI 0xDE03 + +/** + * @brief Test that crc_16_ansi works + */ +ZTEST(crc_subsys, test_crc_16_ansi) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_ansi(data, sizeof(data)), RESULT_CRC16_ANSI); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT 0x445C + +/** + * @brief Test that crc_16_ccitt works + */ +ZTEST(crc_subsys, test_crc_16_ccitt) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_ccitt(0x0000, data, sizeof(data)), RESULT_CRC_CCITT); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16_ITU_T 0x8866 + +/** + * @brief Test that crc_16_itu_t works + */ +ZTEST(crc_subsys, test_crc_16_itu_t) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_itu_t(0x0000, data, sizeof(data)), RESULT_CRC16_ITU_T); +} + +/* Define result of CRC computation */ +#define RESULT_CRC32_C 0xBB19ECB2 + +/** + * @brief Test that crc32_c works + */ +ZTEST(crc_subsys, test_crc_32_c) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc32_c(0x000, data, sizeof(data), true, false), RESULT_CRC32_C); +} +/* Define result of CRC computation */ +#define RESULT_CRC32_IEEE 0xCEA4A6C2 + +/** + * @brief Test that crc_32_ieee works + */ +ZTEST(crc_subsys, test_crc_32_ieee) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc32_ieee(data, sizeof(data)), RESULT_CRC32_IEEE); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_CCITT_REMAIN_1 0x57 + +/** + * @brief Test crc8_ccitt_remain_1 work + */ +ZTEST(crc_subsys, test_crc_8_ccitt_remain_1) +{ + uint8_t data[9] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D}; + + zassert_equal(crc8_ccitt(0x00, data, sizeof(data)), RESULT_CRC8_CCITT_REMAIN_1); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_ROHC_REMAIN_2 0x4F + +/** + * @brief Test that crc_8_rohc_remain_2 works + */ +ZTEST(crc_subsys, test_crc_8_rohc_remain_2) +{ + uint8_t data[10] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0xFF}; + + zassert_equal(crc8_rohc(0x00, data, sizeof(data)), RESULT_CRC8_ROHC_REMAIN_2); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT_REMAIN_3 0x454B + +/** + * @brief Test that crc_16_ccitt_remain_3 works + */ +ZTEST(crc_subsys, test_crc_16_ccitt_remain_3) +{ + uint8_t data[11] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0xFF, 0xE2}; + + zassert_equal(crc16_ccitt(0x0000, data, sizeof(data)), RESULT_CRC_CCITT_REMAIN_3); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16_ITU_T_REMAIN_1 0x917E + +/** + * @brief Test that crc_16_itu_t_remain_1 works + */ +ZTEST(crc_subsys, test_crc_16_itu_t_remain_1) +{ + uint8_t data[9] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D}; + + zassert_equal(crc16_itu_t(0x0000, data, sizeof(data)), RESULT_CRC16_ITU_T_REMAIN_1); +} + +ZTEST_SUITE(crc_subsys, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/subsys/crc/testcase.yaml b/tests/subsys/crc/testcase.yaml new file mode 100644 index 0000000000000..6e8f87cc10fbd --- /dev/null +++ b/tests/subsys/crc/testcase.yaml @@ -0,0 +1,7 @@ +tests: + subsys.crc: + depends_on: crc + tags: + - subsys + - crc + harness: ztest diff --git a/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay b/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay index 6ceffda8610a0..703a9f1e9a825 100644 --- a/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay +++ b/tests/subsys/debug/coredump_backends/boards/qemu_x86.overlay @@ -18,6 +18,5 @@ reg = <0x31000 DT_SIZE_K(8)>; }; - }; }; diff --git a/tests/subsys/dfu/mcuboot_multi/native_sim.overlay b/tests/subsys/dfu/mcuboot_multi/native_sim.overlay index fe7b0da6714e7..5166674f432c7 100644 --- a/tests/subsys/dfu/mcuboot_multi/native_sim.overlay +++ b/tests/subsys/dfu/mcuboot_multi/native_sim.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - /delete-node/ &scratch_partition; /delete-node/ &storage_partition; diff --git a/tests/subsys/dfu/mcuboot_multi/nrf52840dk_nrf52840.overlay b/tests/subsys/dfu/mcuboot_multi/nrf52840dk_nrf52840.overlay index 924ba1a6a0c68..9b71571fd1a96 100644 --- a/tests/subsys/dfu/mcuboot_multi/nrf52840dk_nrf52840.overlay +++ b/tests/subsys/dfu/mcuboot_multi/nrf52840dk_nrf52840.overlay @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - /delete-node/ &storage_partition; /delete-node/ &slot0_partition; /delete-node/ &slot1_partition; diff --git a/tests/subsys/fs/fat_fs_api/src/test_fat_file_reentrant.c b/tests/subsys/fs/fat_fs_api/src/test_fat_file_reentrant.c index af91f017042e4..ec025c2099613 100644 --- a/tests/subsys/fs/fat_fs_api/src/test_fat_file_reentrant.c +++ b/tests/subsys/fs/fat_fs_api/src/test_fat_file_reentrant.c @@ -74,7 +74,7 @@ static int test_reentrant_parallel_file_access(void) zassert_ok(res, "Err: File 1 could not be opened [%d]\n", res); TC_PRINT("File 1 opened 1\n"); - /* Start 2nd file acces thread */ + /* Start 2nd file access thread */ k_tid_t tid = k_thread_create(&tfile2_access_data, tfile2_access_stack_area, K_THREAD_STACK_SIZEOF(tfile2_access_stack_area), tfile2_access, diff --git a/tests/subsys/fs/fcb/boards/native_sim_ev_0x00.overlay b/tests/subsys/fs/fcb/boards/native_sim_ev_0x00.overlay index 3f82b6d2d71e0..55d0ee94e9d20 100644 --- a/tests/subsys/fs/fcb/boards/native_sim_ev_0x00.overlay +++ b/tests/subsys/fs/fcb/boards/native_sim_ev_0x00.overlay @@ -5,7 +5,7 @@ */ &flashcontroller0 { - erase-value = < 0x00 >; + erase-value = <0x00>; }; &flash0 { diff --git a/tests/subsys/fs/fcb/boards/qemu_x86_ev_0x00.overlay b/tests/subsys/fs/fcb/boards/qemu_x86_ev_0x00.overlay index af662f2918770..0ae7ddca0b7e0 100644 --- a/tests/subsys/fs/fcb/boards/qemu_x86_ev_0x00.overlay +++ b/tests/subsys/fs/fcb/boards/qemu_x86_ev_0x00.overlay @@ -5,7 +5,7 @@ */ &sim_flash { - erase-value = < 0x00 >; + erase-value = <0x00>; }; &flash_sim0 { diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.overlay index 000a49903c5c7..7c7b3ca21f8a3 100644 --- a/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.overlay +++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.overlay @@ -7,10 +7,10 @@ /delete-node/ &storage_partition; &flash0 { - partitions { - small_partition: partition@1D000 { - label = "small"; - reg = <0x0001D000 DT_SIZE_K(128)>; - }; - }; + partitions { + small_partition: partition@1D000 { + label = "small"; + reg = <0x0001D000 DT_SIZE_K(128)>; + }; + }; }; diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.overlay index 000a49903c5c7..7c7b3ca21f8a3 100644 --- a/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.overlay +++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.overlay @@ -7,10 +7,10 @@ /delete-node/ &storage_partition; &flash0 { - partitions { - small_partition: partition@1D000 { - label = "small"; - reg = <0x0001D000 DT_SIZE_K(128)>; - }; - }; + partitions { + small_partition: partition@1D000 { + label = "small"; + reg = <0x0001D000 DT_SIZE_K(128)>; + }; + }; }; diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.overlay index d78949bf3ddc2..e67dc535faf4c 100644 --- a/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.overlay +++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.overlay @@ -7,10 +7,10 @@ /delete-node/ &storage_partition; &flash0 { - partitions { - small_partition: partition@1D800 { - label = "small"; - reg = <0x0001D800 DT_SIZE_K(128)>; - }; - }; + partitions { + small_partition: partition@1D800 { + label = "small"; + reg = <0x0001D800 DT_SIZE_K(128)>; + }; + }; }; diff --git a/tests/subsys/fs/nvs/boards/native_sim_64kb_erase_block.overlay b/tests/subsys/fs/nvs/boards/native_sim_64kb_erase_block.overlay new file mode 100644 index 0000000000000..2079b50ceab20 --- /dev/null +++ b/tests/subsys/fs/nvs/boards/native_sim_64kb_erase_block.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&flash0 { + erase-block-size = <0x10000>; + + /* + * Delete old partitions that were not aligned on 64kb addresses and + * create new ones that are aligned. + */ + /delete-node/ partitions; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00070000>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00070000>; + }; + scratch_partition: partition@f0000 { + label = "image-scratch"; + reg = <0x000f0000 0x00020000>; + }; + storage_partition: partition@110000 { + label = "storage"; + reg = <0x00110000 0x00050000>; + }; + }; +}; diff --git a/tests/subsys/fs/nvs/boards/qemu_x86_ev_0x00.overlay b/tests/subsys/fs/nvs/boards/qemu_x86_ev_0x00.overlay index 0f122e3400752..5dc5f348824c5 100644 --- a/tests/subsys/fs/nvs/boards/qemu_x86_ev_0x00.overlay +++ b/tests/subsys/fs/nvs/boards/qemu_x86_ev_0x00.overlay @@ -5,5 +5,5 @@ */ &sim_flash { - erase-value = < 0x00 >; + erase-value = <0x00>; }; diff --git a/tests/subsys/fs/nvs/src/main.c b/tests/subsys/fs/nvs/src/main.c index a3d35ca823edf..3d2254ada9294 100644 --- a/tests/subsys/fs/nvs/src/main.c +++ b/tests/subsys/fs/nvs/src/main.c @@ -96,7 +96,14 @@ ZTEST_SUITE(nvs, NULL, setup, before, after, NULL); ZTEST_F(nvs, test_nvs_mount) { int err; + size_t orig_sector_size = fixture->fs.sector_size; + fixture->fs.sector_size = KB(128); + err = nvs_mount(&fixture->fs); + zassert_true(err == -EINVAL, + "nvs_mount did not return expected err for invalid sector_size"); + + fixture->fs.sector_size = orig_sector_size; err = nvs_mount(&fixture->fs); zassert_true(err == 0, "nvs_mount call failure: %d", err); } @@ -307,7 +314,7 @@ static void write_content(uint16_t max_id, uint16_t begin, uint16_t end, for (uint16_t i = begin; i < end; i++) { uint8_t id = (i % max_id); - uint8_t id_data = id + max_id * (i / max_id); + uint8_t id_data = id + max_id * ((i % 256) / max_id); memset(buf, id_data, sizeof(buf)); @@ -346,13 +353,25 @@ ZTEST_F(nvs, test_nvs_gc_3sectors) const uint16_t max_id = 10; /* 50th write will trigger 1st GC. */ - const uint16_t max_writes = 51; + uint16_t max_writes = 51; /* 75th write will trigger 2st GC. */ - const uint16_t max_writes_2 = 51 + 25; + uint16_t max_writes_2 = 51 + 25; /* 100th write will trigger 3st GC. */ - const uint16_t max_writes_3 = 51 + 25 + 25; + uint16_t max_writes_3 = 51 + 25 + 25; /* 125th write will trigger 4st GC. */ - const uint16_t max_writes_4 = 51 + 25 + 25 + 25; + uint16_t max_writes_4 = 51 + 25 + 25 + 25; + + if (fixture->fs.sector_size == KB(64)) { + /* write 1637 will trigger 1st GC. */ + /* write 3274 will trigger 2nd GC. */ + max_writes = 3275; + /* write 4911 will trigger 3rd GC. */ + max_writes_2 = 3275 + 1637; + /* write 6548 will trigger 4th GC. */ + max_writes_3 = 3275 + 1637 + 1637; + /* write 8185 will trigger 5th GC. */ + max_writes_4 = 3275 + 1637 + 1637 + 1637; + } fixture->fs.sector_count = 3; @@ -361,7 +380,7 @@ ZTEST_F(nvs, test_nvs_gc_3sectors) zassert_equal(fixture->fs.ate_wra >> ADDR_SECT_SHIFT, 0, "unexpected write sector"); - /* Trigger 1st GC */ + /* Trigger 1st and 2nd GC */ write_content(max_id, 0, max_writes, &fixture->fs); /* sector sequence: empty,closed, write */ @@ -376,7 +395,7 @@ ZTEST_F(nvs, test_nvs_gc_3sectors) "unexpected write sector"); check_content(max_id, &fixture->fs); - /* Trigger 2nd GC */ + /* Trigger 3rd GC */ write_content(max_id, max_writes, max_writes_2, &fixture->fs); /* sector sequence: write, empty, closed */ @@ -391,7 +410,7 @@ ZTEST_F(nvs, test_nvs_gc_3sectors) "unexpected write sector"); check_content(max_id, &fixture->fs); - /* Trigger 3rd GC */ + /* Trigger 4th GC */ write_content(max_id, max_writes_2, max_writes_3, &fixture->fs); /* sector sequence: closed, write, empty */ @@ -406,7 +425,7 @@ ZTEST_F(nvs, test_nvs_gc_3sectors) "unexpected write sector"); check_content(max_id, &fixture->fs); - /* Trigger 4th GC */ + /* Trigger 5th GC */ write_content(max_id, max_writes_3, max_writes_4, &fixture->fs); /* sector sequence: empty,closed, write */ diff --git a/tests/subsys/fs/nvs/testcase.yaml b/tests/subsys/fs/nvs/testcase.yaml index c796cda1307b0..34b28ab30e623 100644 --- a/tests/subsys/fs/nvs/testcase.yaml +++ b/tests/subsys/fs/nvs/testcase.yaml @@ -28,3 +28,6 @@ tests: - CONFIG_NVS_LOOKUP_CACHE=y - CONFIG_NVS_LOOKUP_CACHE_SIZE=64 platform_allow: native_sim + filesystem.nvs.64kb_erase_block: + extra_args: DTC_OVERLAY_FILE=boards/native_sim_64kb_erase_block.overlay + platform_allow: native_sim diff --git a/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay b/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay index 0f122e3400752..5dc5f348824c5 100644 --- a/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay +++ b/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay @@ -5,5 +5,5 @@ */ &sim_flash { - erase-value = < 0x00 >; + erase-value = <0x00>; }; diff --git a/tests/subsys/fs/zms/src/main.c b/tests/subsys/fs/zms/src/main.c index 563782044a2b5..a69a2b009537b 100644 --- a/tests/subsys/fs/zms/src/main.c +++ b/tests/subsys/fs/zms/src/main.c @@ -889,3 +889,62 @@ ZTEST_F(zms, test_zms_cache_hash_quality) #endif } + +ZTEST_F(zms, test_zms_input_validation) +{ + int err; + + err = zms_mount(NULL); + zassert_true(err == -EINVAL, "zms_mount call with NULL fs failure: %d", err); + + err = zms_clear(NULL); + zassert_true(err == -EINVAL, "zms_clear call with NULL fs failure: %d", err); + err = zms_clear(&fixture->fs); + zassert_true(err == -EACCES, "zms_clear call before mount fs failure: %d", err); + + err = zms_calc_free_space(NULL); + zassert_true(err == -EINVAL, "zms_calc_free_space call with NULL fs failure: %d", err); + err = zms_calc_free_space(&fixture->fs); + zassert_true(err == -EACCES, "zms_calc_free_space call before mount fs failure: %d", err); + + err = zms_active_sector_free_space(NULL); + zassert_true(err == -EINVAL, "zms_active_sector_free_space call with NULL fs failure: %d", + err); + err = zms_active_sector_free_space(&fixture->fs); + zassert_true(err == -EACCES, "zms_calc_free_space call before mount fs failure: %d", err); + + err = zms_sector_use_next(NULL); + zassert_true(err == -EINVAL, "zms_sector_use_next call with NULL fs failure: %d", err); + err = zms_sector_use_next(&fixture->fs); + zassert_true(err == -EACCES, "zms_sector_use_next call before mount fs failure: %d", err); + + /* Read */ + err = zms_read(NULL, 0, NULL, 0); + zassert_true(err == -EINVAL, "zms_read call with NULL fs failure: %d", err); + err = zms_read(&fixture->fs, 0, NULL, 0); + zassert_true(err == -EACCES, "zms_read call before mount fs failure: %d", err); + + /* zms_read() and zms_get_data_length() are currently wrappers around zms_read_hist() but + * add test here in case that is ever changed. Same is true for zms_delete() and zms_write() + */ + err = zms_read_hist(NULL, 0, NULL, 0, 0); + zassert_true(err == -EINVAL, "zms_read_hist call with NULL fs failure: %d", err); + err = zms_read_hist(&fixture->fs, 0, NULL, 0, 0); + zassert_true(err == -EACCES, "zms_read_hist call before mount fs failure: %d", err); + err = zms_get_data_length(NULL, 0); + zassert_true(err == -EINVAL, "zms_get_data_length call with NULL fs failure: %d", err); + err = zms_get_data_length(&fixture->fs, 0); + zassert_true(err == -EACCES, "zms_get_data_length call before mount fs failure: %d", err); + + /* Write */ + err = zms_write(NULL, 0, NULL, 0); + zassert_true(err == -EINVAL, "zms_write call with NULL fs failure: %d", err); + err = zms_write(&fixture->fs, 0, NULL, 0); + zassert_true(err == -EACCES, "zms_write call before mount fs failure: %d", err); + + /* Delete */ + err = zms_delete(NULL, 0); + zassert_true(err == -EINVAL, "zms_delete call with NULL fs failure: %d", err); + err = zms_delete(&fixture->fs, 0); + zassert_true(err == -EACCES, "zms_delete call before mount fs failure: %d", err); +} diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig.icmsg_v1 b/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig.icmsg_v1 index 463a1a0ad3cea..97666b23f973c 100644 --- a/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig.icmsg_v1 +++ b/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig.icmsg_v1 @@ -22,7 +22,7 @@ config IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS_V1 backends basing on icmsg library. This time should be relatively low. config IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS_V1 - int "Bond notification timeout in miliseconds" + int "Bond notification timeout in milliseconds" range 1 100 default 1 help diff --git a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay index 95dffe367e4d5..1ea1c1a27712c 100644 --- a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay +++ b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay @@ -7,30 +7,30 @@ /delete-node/ &ipc0; / { - chosen { - /delete-property/ zephyr,ipc_shm; - }; + chosen { + /delete-property/ zephyr,ipc_shm; + }; - reserved-memory { - /delete-node/ memory@20070000; + reserved-memory { + /delete-node/ memory@20070000; - sram_rx: memory@20070000 { - reg = <0x20070000 0x8000>; - }; + sram_rx: memory@20070000 { + reg = <0x20070000 0x8000>; + }; - sram_tx: memory@20078000 { - reg = <0x20078000 0x8000>; - }; - }; + sram_tx: memory@20078000 { + reg = <0x20078000 0x8000>; + }; + }; - ipc0: ipc0 { - compatible = "zephyr,ipc-icmsg"; - tx-region = <&sram_tx>; - rx-region = <&sram_rx>; - mboxes = <&mbox 0>, <&mbox 1>; - mbox-names = "rx", "tx"; - dcache-alignment = <8>; - unbound = "detect"; - status = "okay"; - }; + ipc0: ipc0 { + compatible = "zephyr,ipc-icmsg"; + tx-region = <&sram_tx>; + rx-region = <&sram_rx>; + mboxes = <&mbox 0>, <&mbox 1>; + mbox-names = "rx", "tx"; + dcache-alignment = <8>; + unbound = "detect"; + status = "okay"; + }; }; diff --git a/tests/subsys/llext/src/test_llext.c b/tests/subsys/llext/src/test_llext.c index b88af808849ec..77e44ec1c885c 100644 --- a/tests/subsys/llext/src/test_llext.c +++ b/tests/subsys/llext/src/test_llext.c @@ -237,7 +237,7 @@ void load_call_unload(const struct llext_test *test_case) /* * Attempt to load, list, list symbols, call a fn, and unload each - * extension in the test table. This excercises loading, calling into, and + * extension in the test table. This exercises loading, calling into, and * unloading each extension which may itself excercise various APIs provided by * Zephyr. */ diff --git a/tests/subsys/mem_mgmt/mem_attr/app.overlay b/tests/subsys/mem_mgmt/mem_attr/app.overlay index 26773fe2345c7..c0c9a86bd13a5 100644 --- a/tests/subsys/mem_mgmt/mem_attr/app.overlay +++ b/tests/subsys/mem_mgmt/mem_attr/app.overlay @@ -10,19 +10,19 @@ mem_ram: memory@10000000 { compatible = "vnd,memory-attr"; reg = <0x10000000 0x1000>; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) | DT_MEM_NON_VOLATILE )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_FLASH) | DT_MEM_NON_VOLATILE)>; }; mem_ram_nocache: memory@20000000 { compatible = "vnd,memory-attr"; reg = <0x20000000 0x2000>; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = ; }; mem_ram_disabled: memory@30000000 { compatible = "vnd,memory-attr"; reg = <0x30000000 0x3000>; - zephyr,memory-attr = <( DT_MEM_CACHEABLE | DT_MEM_OOO )>; + zephyr,memory-attr = <(DT_MEM_CACHEABLE | DT_MEM_OOO)>; status = "disabled"; }; }; diff --git a/tests/subsys/mem_mgmt/mem_attr_heap/boards/qemu_cortex_m3.overlay b/tests/subsys/mem_mgmt/mem_attr_heap/boards/qemu_cortex_m3.overlay index dc2e25a4e0d99..d75f0423a4ead 100644 --- a/tests/subsys/mem_mgmt/mem_attr_heap/boards/qemu_cortex_m3.overlay +++ b/tests/subsys/mem_mgmt/mem_attr_heap/boards/qemu_cortex_m3.overlay @@ -7,43 +7,43 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20008000 0x1000>; zephyr,memory-region = "MEM_CACHEABLE"; - zephyr,memory-attr = <( DT_MEM_CACHEABLE )>; + zephyr,memory-attr = ; }; mem_cache_sw: memory@20009000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20009000 0x1000>; zephyr,memory-region = "MEM_CACHEABLE_SW"; - zephyr,memory-attr = <( DT_MEM_CACHEABLE | DT_MEM_SW_ALLOC_CACHE )>; + zephyr,memory-attr = <(DT_MEM_CACHEABLE | DT_MEM_SW_ALLOC_CACHE)>; }; mem_noncache_sw: memory@2000A000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x2000A000 0x1000>; zephyr,memory-region = "MEM_NON_CACHEABLE_SW"; - zephyr,memory-attr = <( DT_MEM_SW_ALLOC_NON_CACHE )>; + zephyr,memory-attr = ; }; mem_dma_sw: memory@2000B000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x2000B000 0x1000>; zephyr,memory-region = "MEM_DMA_SW"; - zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_SW_ALLOC_DMA )>; + zephyr,memory-attr = <(DT_MEM_DMA | DT_MEM_SW_ALLOC_DMA)>; }; mem_cache_sw_big: memory@2000C000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x2000C000 0x2000>; zephyr,memory-region = "MEM_CACHEABLE_SW_BIG"; - zephyr,memory-attr = <( DT_MEM_CACHEABLE | DT_MEM_SW_ALLOC_CACHE )>; + zephyr,memory-attr = <(DT_MEM_CACHEABLE | DT_MEM_SW_ALLOC_CACHE)>; }; mem_cache_cache_dma_multi: memory@2000E000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x2000E000 0x1000>; zephyr,memory-region = "MEM_CACHEABLE_SW_MULTI_ATTR"; - zephyr,memory-attr = <( DT_MEM_CACHEABLE | DT_MEM_DMA | - DT_MEM_SW_ALLOC_CACHE | DT_MEM_SW_ALLOC_DMA)>; + zephyr,memory-attr = <(DT_MEM_CACHEABLE | DT_MEM_DMA | + DT_MEM_SW_ALLOC_CACHE | DT_MEM_SW_ALLOC_DMA)>; }; }; diff --git a/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/boards/nrf5340dk_nrf5340_cpuapp_dual_slot.overlay b/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/boards/nrf5340dk_nrf5340_cpuapp_dual_slot.overlay index dbb67ed76f854..4d5de021baa42 100644 --- a/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/boards/nrf5340dk_nrf5340_cpuapp_dual_slot.overlay +++ b/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/boards/nrf5340dk_nrf5340_cpuapp_dual_slot.overlay @@ -5,8 +5,6 @@ */ /delete-node/ &boot_partition; -/delete-node/ &slot0_ns_partition; -/delete-node/ &slot1_ns_partition; /delete-node/ &slot0_partition; /delete-node/ &slot1_partition; @@ -20,18 +18,22 @@ label = "mcuboot"; reg = <0x00000000 0x10000>; }; + slot0_partition: partition@10000 { label = "image-0"; reg = <0x00010000 0x40000>; }; + slot1_partition: partition@50000 { label = "image-1"; reg = <0x00050000 0x40000>; }; + slot2_partition: partition@90000 { label = "image-2"; reg = <0x00090000 0x30000>; }; + slot3_partition: partition@c0000 { label = "image-3"; reg = <0x000c0000 0x30000>; diff --git a/tests/subsys/modem/modem_pipelink/app.overlay b/tests/subsys/modem/modem_pipelink/app.overlay index 5c8de45740466..fa2522d77cdc4 100644 --- a/tests/subsys/modem/modem_pipelink/app.overlay +++ b/tests/subsys/modem/modem_pipelink/app.overlay @@ -1,4 +1,3 @@ / { - test_node: test_node { - }; + test_node: test_node {}; }; diff --git a/tests/subsys/pm/device_runtime_api/src/main.c b/tests/subsys/pm/device_runtime_api/src/main.c index 20a4686592f3f..96672582f5a1a 100644 --- a/tests/subsys/pm/device_runtime_api/src/main.c +++ b/tests/subsys/pm/device_runtime_api/src/main.c @@ -42,6 +42,8 @@ void test_api_setup(void *data) int ret; enum pm_device_state state; + test_driver_pm_retval(test_dev, 0); + /* check API always returns 0 when runtime PM is disabled */ ret = pm_device_runtime_get(test_dev); zassert_equal(ret, 0); @@ -107,6 +109,12 @@ ZTEST(device_runtime_api, test_api) /*** get + put ***/ + /* usage: 0, 0, resume: no */ + test_driver_pm_retval(test_dev, -EIO); + ret = pm_device_runtime_get(test_dev); + zassert_equal(ret, -EIO); + test_driver_pm_retval(test_dev, 0); + /* usage: 0, +1, resume: yes */ ret = pm_device_runtime_get(test_dev); zassert_equal(ret, 0); @@ -126,6 +134,12 @@ ZTEST(device_runtime_api, test_api) (void)pm_device_state_get(test_dev, &state); zassert_equal(state, PM_DEVICE_STATE_ACTIVE); + /* usage: 1, 0, suspend: no */ + test_driver_pm_retval(test_dev, -EIO); + ret = pm_device_runtime_put(test_dev); + zassert_equal(ret, -EIO); + test_driver_pm_retval(test_dev, 0); + /* usage: 1, -1, suspend: yes */ ret = pm_device_runtime_put(test_dev); zassert_equal(ret, 0); diff --git a/tests/subsys/pm/device_runtime_api/src/test_driver.c b/tests/subsys/pm/device_runtime_api/src/test_driver.c index 48dd4385cbc03..7cf412027ab6b 100644 --- a/tests/subsys/pm/device_runtime_api/src/test_driver.c +++ b/tests/subsys/pm/device_runtime_api/src/test_driver.c @@ -14,6 +14,7 @@ struct test_driver_data { bool ongoing; bool async; struct k_sem sync; + int ret; }; static int test_driver_action(const struct device *dev, @@ -34,7 +35,7 @@ static int test_driver_action(const struct device *dev, data->count++; - return 0; + return data->ret; } void test_driver_pm_async(const struct device *dev) @@ -65,6 +66,13 @@ size_t test_driver_pm_count(const struct device *dev) return data->count; } +void test_driver_pm_retval(const struct device *dev, int ret) +{ + struct test_driver_data *data = dev->data; + + data->ret = ret; +} + int test_driver_init(const struct device *dev) { struct test_driver_data *data = dev->data; diff --git a/tests/subsys/pm/device_runtime_api/src/test_driver.h b/tests/subsys/pm/device_runtime_api/src/test_driver.h index 4979c7d2cb1bb..390994caa2d59 100644 --- a/tests/subsys/pm/device_runtime_api/src/test_driver.h +++ b/tests/subsys/pm/device_runtime_api/src/test_driver.h @@ -45,4 +45,13 @@ bool test_driver_pm_ongoing(const struct device *dev); */ size_t test_driver_pm_count(const struct device *dev); +/** + * @brief Configure the return value of pm actions. + * + * @param dev Device instance. + * + * @return The number of state changes the device made. + */ +void test_driver_pm_retval(const struct device *dev, int ret); + #endif /* TESTS_SUBSYS_PM_DEVICE_RUNTIME_TEST_DRIVER_H_ */ diff --git a/tests/subsys/pm/power_mgmt_soc/testcase.yaml b/tests/subsys/pm/power_mgmt_soc/testcase.yaml index 9d5b2b6ceb062..57d65ec5215f2 100644 --- a/tests/subsys/pm/power_mgmt_soc/testcase.yaml +++ b/tests/subsys/pm/power_mgmt_soc/testcase.yaml @@ -14,6 +14,7 @@ tests: - frdm_ke17z - frdm_ke17z512 - xg29_rb4412a + - bg29_rb4420a - max32690evkit/max32690/m4 - max32655evkit/max32655/m4 - max32655fthr/max32655/m4 diff --git a/tests/subsys/pm/power_residency_time/boards/stm32l562e_dk.overlay b/tests/subsys/pm/power_residency_time/boards/stm32l562e_dk.overlay index ee4d80f9e903d..113473fefcb68 100644 --- a/tests/subsys/pm/power_residency_time/boards/stm32l562e_dk.overlay +++ b/tests/subsys/pm/power_residency_time/boards/stm32l562e_dk.overlay @@ -4,19 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ -&stop0{ +&stop0 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; substate-id = <1>; min-residency-us = <500000>; }; -&stop1{ +&stop1 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; substate-id = <2>; min-residency-us = <1000000>; }; -&stop2{ +&stop2 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; substate-id = <3>; diff --git a/tests/subsys/pm/power_states/boards/stm32l562e_dk.overlay b/tests/subsys/pm/power_states/boards/stm32l562e_dk.overlay index d128ff520ca50..a6772e536133d 100644 --- a/tests/subsys/pm/power_states/boards/stm32l562e_dk.overlay +++ b/tests/subsys/pm/power_states/boards/stm32l562e_dk.overlay @@ -9,19 +9,19 @@ }; }; -&stop0{ +&stop0 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; substate-id = <1>; min-residency-us = <500000>; }; -&stop1{ +&stop1 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; substate-id = <2>; min-residency-us = <1000000>; }; -&stop2{ +&stop2 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; substate-id = <3>; diff --git a/tests/subsys/pm/power_wakeup_timer/boards/stm32l562e_dk.overlay b/tests/subsys/pm/power_wakeup_timer/boards/stm32l562e_dk.overlay index b13e8a9552b17..faa73575e9ae3 100644 --- a/tests/subsys/pm/power_wakeup_timer/boards/stm32l562e_dk.overlay +++ b/tests/subsys/pm/power_wakeup_timer/boards/stm32l562e_dk.overlay @@ -6,10 +6,10 @@ &rtc { compatible = "st,stm32-rtc"; - reg = < 0x40002800 0xc00 >; - interrupts = < 0x2 0x0 >; - clocks = < &rcc STM32_CLOCK_BUS_APB1 0x400 >, < &rcc STM32_SRC_LSE RTC_SEL(1)>; - prescaler = < 0x8000 >; + reg = <0x40002800 0xc00>; + interrupts = <0x2 0x0>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x400>, <&rcc STM32_SRC_LSE RTC_SEL(1)>; + prescaler = <0x8000>; status = "okay"; wakeup-source; }; diff --git a/tests/subsys/rtio/rtio_api/CMakeLists.txt b/tests/subsys/rtio/rtio_api/CMakeLists.txt index 88d15b5f0da54..c77376373284a 100644 --- a/tests/subsys/rtio/rtio_api/CMakeLists.txt +++ b/tests/subsys/rtio/rtio_api/CMakeLists.txt @@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(rtio_api_test) -target_sources(app PRIVATE src/test_rtio_api.c) +target_sources(app PRIVATE src/test_rtio_api.c src/test_rtio_pool.c) target_include_directories(app PRIVATE ${ZEPHYR_BASE}/include diff --git a/tests/subsys/rtio/rtio_api/src/test_rtio_api.c b/tests/subsys/rtio/rtio_api/src/test_rtio_api.c index d288abca881ae..4fcefc9a0589e 100644 --- a/tests/subsys/rtio/rtio_api/src/test_rtio_api.c +++ b/tests/subsys/rtio/rtio_api/src/test_rtio_api.c @@ -949,9 +949,97 @@ void test_rtio_await_(struct rtio *rtio0, struct rtio *rtio1) rtio_cqe_release(rtio1, cqe); } +/** + * @brief Test await operations handled purely by the executor + * + * Ensures we can pause just one SQE chain using the AWAIT operation, letting the rtio_iodev serve + * other sequences during the wait, and finally resume the executor by calling rtio_sqe_signal(). + */ +void test_rtio_await_executor_(struct rtio *rtio0, struct rtio *rtio1) +{ + int res; + int32_t userdata[4] = {0, 1, 2, 3}; + struct rtio_sqe *await_sqe; + struct rtio_sqe *sqe; + struct rtio_cqe *cqe; + + rtio_iodev_test_init(&iodev_test_await0); + + /* Prepare a NOP->AWAIT chain on rtio0 to verify the blocking behavior of AWAIT */ + sqe = rtio_sqe_acquire(rtio0); + zassert_not_null(sqe, "Expected a valid sqe"); + rtio_sqe_prep_nop(sqe, &iodev_test_await0, &userdata[0]); + sqe->flags = RTIO_SQE_CHAINED; + + await_sqe = rtio_sqe_acquire(rtio0); + zassert_not_null(await_sqe, "Expected a valid sqe"); + rtio_sqe_prep_await_executor(await_sqe, RTIO_PRIO_LOW, &userdata[1]); + await_sqe->flags = 0; + + /* + * Prepare another NOP on rtio0, to verify that while the await is busy, the executor + * can process an unconnected operation + */ + sqe = rtio_sqe_acquire(rtio0); + zassert_not_null(sqe, "Expected a valid sqe"); + rtio_sqe_prep_nop(sqe, &iodev_test_await0, &userdata[3]); + sqe->flags = 0; + + /* Prepare a NOP sqe on rtio1 */ + sqe = rtio_sqe_acquire(rtio1); + zassert_not_null(sqe, "Expected a valid sqe"); + rtio_sqe_prep_nop(sqe, &iodev_test_await0, &userdata[2]); + sqe->prio = RTIO_PRIO_HIGH; + sqe->flags = 0; + + /* Submit the rtio0 sequence and make sure it reaches the AWAIT sqe */ + TC_PRINT("Submitting await sqe from rtio0\n"); + res = rtio_submit(rtio0, 0); + zassert_ok(res, "Submission failed"); + + TC_PRINT("Wait for nop sqe from rtio0 completed\n"); + cqe = rtio_cqe_consume_block(rtio0); + zassert_not_null(sqe, "Expected a valid sqe"); + zassert_equal(cqe->userdata, &userdata[0]); + rtio_cqe_release(rtio0, cqe); + + /* Submit rtio1 sequence and ensure it completes while rtio0 is paused at the AWAIT */ + TC_PRINT("Submitting sqe from rtio1\n"); + res = rtio_submit(rtio1, 0); + zassert_ok(res, "Submission failed"); + + TC_PRINT("Ensure sqe from rtio1 completes\n"); + cqe = rtio_cqe_consume_block(rtio1); + zassert_not_null(cqe, "Expected a valid cqe"); + zassert_equal(cqe->userdata, &userdata[2]); + rtio_cqe_release(rtio1, cqe); + + /* Verify that rtio0 processes the freestanding NOP during the await */ + TC_PRINT("Ensure freestanding NOP completes while await is busy\n"); + cqe = rtio_cqe_consume_block(rtio0); + zassert_not_null(cqe, "Expected a valid cqe"); + zassert_equal(cqe->userdata, &userdata[3]); + rtio_cqe_release(rtio1, cqe); + + /* Make sure rtio0 is still paused at the AWAIT and finally complete it */ + TC_PRINT("Ensure await_sqe is not completed unintentionally\n"); + cqe = rtio_cqe_consume(rtio0); + zassert_equal(cqe, NULL, "Expected no valid cqe"); + + TC_PRINT("Signal await sqe from rtio0\n"); + rtio_sqe_signal(await_sqe); + + TC_PRINT("Ensure sqe from rtio0 completed\n"); + cqe = rtio_cqe_consume_block(rtio0); + zassert_not_null(cqe, "Expected a valid cqe"); + zassert_equal(cqe->userdata, &userdata[1]); + rtio_cqe_release(rtio0, cqe); +} + ZTEST(rtio_api, test_rtio_await) { test_rtio_await_(&r_await0, &r_await1); + test_rtio_await_executor_(&r_await0, &r_await1); } static void *rtio_api_setup(void) diff --git a/tests/subsys/rtio/rtio_api/src/test_rtio_pool.c b/tests/subsys/rtio/rtio_api/src/test_rtio_pool.c new file mode 100644 index 0000000000000..6904a18a4f51f --- /dev/null +++ b/tests/subsys/rtio/rtio_api/src/test_rtio_pool.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2025 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +RTIO_POOL_DEFINE(rpool, 2, 8, 8); + +#ifdef CONFIG_USERSPACE +struct k_mem_domain pool_domain; +#endif + + +ZTEST_USER(rtio_pool, test_rtio_pool_acquire_release) +{ + struct rtio *r = rtio_pool_acquire(&rpool); + + zassert_not_null(r, "expected valid rtio context"); + + struct rtio_sqe nop_sqe; + struct rtio_cqe nop_cqe; + + rtio_sqe_prep_nop(&nop_sqe, NULL, NULL); + rtio_sqe_copy_in(r, &nop_sqe, 1); + rtio_submit(r, 1); + rtio_cqe_copy_out(r, &nop_cqe, 1, K_FOREVER); + + rtio_pool_release(&rpool, r); +} + +static void *rtio_pool_setup(void) +{ +#ifdef CONFIG_USERSPACE + k_mem_domain_init(&pool_domain, 0, NULL); + k_mem_domain_add_partition(&pool_domain, &rtio_partition); +#if Z_LIBC_PARTITION_EXISTS + k_mem_domain_add_partition(&pool_domain, &z_libc_partition); +#endif /* Z_LIBC_PARTITION_EXISTS */ +#endif /* CONFIG_USERSPACE */ + + return NULL; +} + +static void rtio_pool_before(void *a) +{ + ARG_UNUSED(a); + +#ifdef CONFIG_USERSPACE + k_object_access_grant(&rpool, k_current_get()); +#endif /* CONFIG_USERSPACE */ +} + +ZTEST_SUITE(rtio_pool, NULL, rtio_pool_setup, rtio_pool_before, NULL, NULL); diff --git a/tests/subsys/sd/sdio/boards/arduino_portenta_h7_stm32h747xx_m7.overlay b/tests/subsys/sd/sdio/boards/arduino_portenta_h7_stm32h747xx_m7.overlay index 957e315ef6c71..20b2ef76777dc 100644 --- a/tests/subsys/sd/sdio/boards/arduino_portenta_h7_stm32h747xx_m7.overlay +++ b/tests/subsys/sd/sdio/boards/arduino_portenta_h7_stm32h747xx_m7.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -&boot_partition{ +&boot_partition { reg = <0x00000000 0x00020000>; }; &scratch_partition { @@ -14,7 +14,7 @@ reg = <0x00040000 0x001C0000>; }; &slot1_partition { - reg = <0x00200000 0x001C0000>; + reg = <0x00200000 0x001C0000>; }; &wifi { diff --git a/tests/subsys/secure_storage/psa/crypto/testcase.yaml b/tests/subsys/secure_storage/psa/crypto/testcase.yaml index 8755a5a193523..1482d23cb6c7e 100644 --- a/tests/subsys/secure_storage/psa/crypto/testcase.yaml +++ b/tests/subsys/secure_storage/psa/crypto/testcase.yaml @@ -8,7 +8,6 @@ tests: integration_platforms: - native_sim - nrf54l15dk/nrf54l15/cpuapp - - ophelia4ev/nrf54l15/cpuapp secure_storage.psa.crypto.tfm: filter: CONFIG_BUILD_WITH_TFM extra_args: EXTRA_CONF_FILE=overlay-tfm.conf diff --git a/tests/subsys/secure_storage/psa/its/overlay-store_zms.conf b/tests/subsys/secure_storage/psa/its/overlay-store_zms.conf index 7efe611bc0a4b..6c36dd4029728 100644 --- a/tests/subsys/secure_storage/psa/its/overlay-store_zms.conf +++ b/tests/subsys/secure_storage/psa/its/overlay-store_zms.conf @@ -1,3 +1,4 @@ CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS=y CONFIG_ZMS=y CONFIG_FLASH=y +CONFIG_FLASH_MAP=y diff --git a/tests/subsys/secure_storage/psa/its/testcase.yaml b/tests/subsys/secure_storage/psa/its/testcase.yaml index 05f1c1b9a6acf..75950a798143a 100644 --- a/tests/subsys/secure_storage/psa/its/testcase.yaml +++ b/tests/subsys/secure_storage/psa/its/testcase.yaml @@ -2,7 +2,6 @@ common: integration_platforms: - native_sim - nrf54l15dk/nrf54l15/cpuapp - - ophelia4ev/nrf54l15/cpuapp platform_exclude: - qemu_cortex_m0 # settings subsystem initialization fails timeout: 600 @@ -10,10 +9,9 @@ common: - psa.secure_storage tests: secure_storage.psa.its.secure_storage.store.zms: - filter: CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS # DT-based filtering is not possible for this test scenario. # Platforms with a storage_partition must be manually added here. - platform_allow: + platform_allow: &zms_platform_allow - native_sim - mps2/an385 - qemu_x86/atom @@ -25,14 +23,29 @@ tests: - nrf9160dk/nrf9160 - nrf9161dk/nrf9161 - ophelia4ev/nrf54l15/cpuapp - extra_args: + extra_args: &zms_extra_args - EXTRA_DTC_OVERLAY_FILE=zms.overlay - - EXTRA_CONF_FILE=overlay-secure_storage.conf;overlay-store_zms.conf;overlay-transform_default.conf + - EXTRA_CONF_FILE=\ + overlay-secure_storage.conf;overlay-store_zms.conf;overlay-transform_default.conf + + secure_storage.psa.its.secure_storage.store.zms.64-bit_uids: + platform_allow: *zms_platform_allow + extra_args: *zms_extra_args + extra_configs: + - CONFIG_SECURE_STORAGE_64_BIT_UID=y secure_storage.psa.its.secure_storage.store.settings: - filter: CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS - extra_args: "EXTRA_CONF_FILE=\ - overlay-secure_storage.conf;overlay-transform_default.conf;overlay-store_settings.conf" + filter: &settings_filter + CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS + extra_args: &settings_extra_args + "EXTRA_CONF_FILE=\ + overlay-secure_storage.conf;overlay-transform_default.conf;overlay-store_settings.conf" + + secure_storage.psa.its.secure_storage.store.settings.64-bit_uids: + filter: *settings_filter + extra_args: *settings_extra_args + extra_configs: + - CONFIG_SECURE_STORAGE_64_BIT_UID=y secure_storage.psa.its.secure_storage.custom.transform: filter: CONFIG_SECURE_STORAGE and not CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_NONE diff --git a/tests/subsys/settings/its/prj.conf b/tests/subsys/settings/its/prj.conf index 7d9f4339bb6cd..e03e76747ba34 100644 --- a/tests/subsys/settings/its/prj.conf +++ b/tests/subsys/settings/its/prj.conf @@ -9,4 +9,5 @@ CONFIG_TFM_PARTITION_INTERNAL_TRUSTED_STORAGE=y CONFIG_TFM_ITS_MAX_ASSET_SIZE_OVERRIDE=y CONFIG_TFM_ITS_MAX_ASSET_SIZE=1024 CONFIG_SETTINGS=y +CONFIG_SETTINGS_TFM_ITS=y CONFIG_SETTINGS_RUNTIME=y diff --git a/tests/subsys/settings/its/testcase.yaml b/tests/subsys/settings/its/testcase.yaml index 9c0f913375353..de11f1ef72643 100644 --- a/tests/subsys/settings/its/testcase.yaml +++ b/tests/subsys/settings/its/testcase.yaml @@ -10,3 +10,5 @@ tests: - max32657evkit/max32657/ns - nrf5340dk/nrf5340/cpuapp/ns - nrf54l15dk/nrf54l15/cpuapp/ns + platform_exclude: + - lpcxpresso55s69/lpc55s69/cpu0/ns diff --git a/tests/subsys/storage/flash_map/app.overlay b/tests/subsys/storage/flash_map/app.overlay index 879b9500e8557..1465a9fb1cef2 100644 --- a/tests/subsys/storage/flash_map/app.overlay +++ b/tests/subsys/storage/flash_map/app.overlay @@ -7,7 +7,7 @@ * Test compilation with disabled flash nodes. */ -/{ +/ { disabled_flash@0 { compatible = "vnd,flash"; reg = <0x00 0x1000>; diff --git a/tests/subsys/storage/stream/stream_flash/src/main.c b/tests/subsys/storage/stream/stream_flash/src/main.c index b691a7e07926d..944892e256f39 100644 --- a/tests/subsys/storage/stream/stream_flash/src/main.c +++ b/tests/subsys/storage/stream/stream_flash/src/main.c @@ -276,6 +276,42 @@ ZTEST(lib_stream_flash, test_stream_flash_bytes_written) VERIFY_WRITTEN(BUF_LEN, BUF_LEN); } +ZTEST(lib_stream_flash, test_stream_flash_bytes_buffered) +{ + int rc; + size_t buffered; + + init_target(); + + /* Initially no bytes should be buffered */ + buffered = stream_flash_bytes_buffered(&ctx); + zassert_equal(buffered, 0, "expected no buffered bytes"); + + /* Write partial buffer */ + rc = stream_flash_buffered_write(&ctx, write_buf, BUF_LEN - 128, false); + zassert_equal(rc, 0, "expected success"); + + /* Verify buffered bytes */ + buffered = stream_flash_bytes_buffered(&ctx); + zassert_equal(buffered, BUF_LEN - 128, "expected buffered bytes"); + + /* Write remaining buffer */ + rc = stream_flash_buffered_write(&ctx, write_buf, 128, false); + zassert_equal(rc, 0, "expected success"); + + /* After auto-flush, no bytes should be buffered */ + buffered = stream_flash_bytes_buffered(&ctx); + zassert_equal(buffered, 0, "expected no buffered bytes"); + + /* Write more than buffer size to trigger auto-flush */ + rc = stream_flash_buffered_write(&ctx, write_buf, BUF_LEN + 128, false); + zassert_equal(rc, 0, "expected success"); + + /* Verify buffered bytes */ + buffered = stream_flash_bytes_buffered(&ctx); + zassert_equal(buffered, 128, "expected remaining buffered bytes after auto-flush"); +} + ZTEST(lib_stream_flash, test_stream_flash_buf_size_greater_than_page_size) { int rc; diff --git a/tests/subsys/storage/stream/stream_flash/unaligned_flush.overlay b/tests/subsys/storage/stream/stream_flash/unaligned_flush.overlay index 1809506c2d104..97e4acd1febc8 100644 --- a/tests/subsys/storage/stream/stream_flash/unaligned_flush.overlay +++ b/tests/subsys/storage/stream/stream_flash/unaligned_flush.overlay @@ -5,5 +5,5 @@ */ &flash0 { - write-block-size = < 0x8 >; + write-block-size = <0x8>; }; diff --git a/tests/subsys/usb/device_next/build_all.overlay b/tests/subsys/usb/device_next/build_all.overlay index bafd8f94aaa7d..e571e4b4bd7e0 100644 --- a/tests/subsys/usb/device_next/build_all.overlay +++ b/tests/subsys/usb/device_next/build_all.overlay @@ -66,7 +66,6 @@ maximum-speed = "high-speed"; }; }; - }; &zephyr_udc0 { diff --git a/tests/subsys/usb/uac2/app.overlay b/tests/subsys/usb/uac2/app.overlay index 52db720a29ca5..a6d5faf99aa12 100644 --- a/tests/subsys/usb/uac2/app.overlay +++ b/tests/subsys/usb/uac2/app.overlay @@ -33,10 +33,9 @@ compatible = "zephyr,uac2-feature-unit"; data-source = <&out_terminal>; mute-control = "host-programmable"; - automatic-gain-control = - "host-programmable" /* Primary */, - "host-programmable" /* Channel 1 */, - "host-programmable" /* Channel 2 */; + automatic-gain-control = "host-programmable", /* Primary */ + "host-programmable", /* Channel 1 */ + "host-programmable"; /* Channel 2 */ }; headphones_output: headphones { @@ -64,9 +63,8 @@ compatible = "zephyr,uac2-feature-unit"; data-source = <&mic_input>; mute-control = "host-programmable"; - automatic-gain-control = - "not-present" /* Primary */, - "host-programmable" /* Channel 1 */; + automatic-gain-control = "not-present", /* Primary */ + "host-programmable"; /* Channel 1 */ }; in_terminal: in_terminal { diff --git a/tests/unit/crc/main.c b/tests/unit/crc/main.c index dab84c0021103..b8cef7df1b861 100644 --- a/tests/unit/crc/main.c +++ b/tests/unit/crc/main.c @@ -6,14 +6,14 @@ #include #include -#include "../../../lib/crc/crc8_sw.c" -#include "../../../lib/crc/crc16_sw.c" -#include "../../../lib/crc/crc32_sw.c" -#include "../../../lib/crc/crc32c_sw.c" -#include "../../../lib/crc/crc7_sw.c" -#include "../../../lib/crc/crc24_sw.c" -#include "../../../lib/crc/crc4_sw.c" -#include "../../../lib/crc/crc32k_4_2_sw.c" +#include "../../../subsys/crc/crc8_sw.c" +#include "../../../subsys/crc/crc16_sw.c" +#include "../../../subsys/crc/crc32_sw.c" +#include "../../../subsys/crc/crc32c_sw.c" +#include "../../../subsys/crc/crc7_sw.c" +#include "../../../subsys/crc/crc24_sw.c" +#include "../../../subsys/crc/crc4_sw.c" +#include "../../../subsys/crc/crc32k_4_2_sw.c" ZTEST(crc, test_crc32_k_4_2) { diff --git a/tests/unit/util/CMakeLists.txt b/tests/unit/util/CMakeLists.txt index ecdc5f67979fe..e2eeb9989aa77 100644 --- a/tests/unit/util/CMakeLists.txt +++ b/tests/unit/util/CMakeLists.txt @@ -11,6 +11,7 @@ target_sources(testbinary main.c ${ZEPHYR_BASE}/lib/utils/dec.c ${ZEPHYR_BASE}/lib/utils/utf8.c + ${ZEPHYR_BASE}/lib/utils/bitmask.c ) if(CONFIG_CPP) diff --git a/tests/unit/util/main.c b/tests/unit/util/main.c index 2ea8724019908..369a0e88d41c3 100644 --- a/tests/unit/util/main.c +++ b/tests/unit/util/main.c @@ -1,14 +1,21 @@ /* * Copyright (c) 2019 Oticon A/S + * Copyright (c) 2025 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ -#include -#include +#include #include #include +#include +#include +#include +#include +#include +#include + ZTEST(util, test_u8_to_dec) { char text[4]; uint8_t len; @@ -845,6 +852,26 @@ ZTEST(util, test_mem_xor_128) zassert_mem_equal(expected_result, dst, 16); } +ZTEST(util, test_sys_count_bits) +{ + uint8_t zero = 0U; + uint8_t u8 = 29U; + uint16_t u16 = 29999U; + uint32_t u32 = 2999999999U; + uint64_t u64 = 123456789012345ULL; + uint8_t u8_arr[] = {u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, + u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8}; + + zassert_equal(sys_count_bits(&zero, sizeof(zero)), 0); + zassert_equal(sys_count_bits(&u8, sizeof(u8)), 4); + zassert_equal(sys_count_bits(&u16, sizeof(u16)), 10); + zassert_equal(sys_count_bits(&u32, sizeof(u32)), 20); + zassert_equal(sys_count_bits(&u64, sizeof(u64)), 23); + + zassert_equal(sys_count_bits(u8_arr, sizeof(u8_arr)), 128); + zassert_equal(sys_count_bits(&u8_arr[1], sizeof(u8_arr) - sizeof(u8_arr[0])), 124); +} + ZTEST(util, test_CONCAT) { #define _CAT_PART1 1 @@ -1005,6 +1032,31 @@ ZTEST(util, test_utf8_lcpy_null_termination) zassert_str_equal(dest_str, expected_result, "Failed to truncate"); } +ZTEST(util, test_utf8_count_chars_ASCII) +{ + const char *test_str = "I have 15 char."; + int count = utf8_count_chars(test_str); + + zassert_equal(count, 15, "Failed to count ASCII"); +} + +ZTEST(util, test_utf8_count_chars_non_ASCII) +{ + const char *test_str = "Hello دنیا!🌍"; + int count = utf8_count_chars(test_str); + + zassert_equal(count, 12, "Failed to count non-ASCII"); +} + +ZTEST(util, test_utf8_count_chars_invalid_utf) +{ + const char test_str[] = { (char)0x80, 0x00 }; + int count = utf8_count_chars(test_str); + int expected_result = -EINVAL; + + zassert_equal(count, expected_result, "Failed to detect invalid UTF"); +} + ZTEST(util, test_util_eq) { uint8_t src1[16]; @@ -1056,4 +1108,27 @@ ZTEST(util, test_util_memeq) zassert_false(mem_area_matching_2); } +static void test_single_bitmask_find_gap(uint32_t mask, size_t num_bits, size_t total_bits, + bool first_match, int exp_rv, int line) +{ + int rv; + + rv = bitmask_find_gap(mask, num_bits, total_bits, first_match); + zassert_equal(rv, exp_rv, "%d Unexpected rv:%d (exp:%d)", line, rv, exp_rv); +} + +ZTEST(util, test_bitmask_find_gap) +{ + test_single_bitmask_find_gap(0x0F0F070F, 6, 32, true, -1, __LINE__); + test_single_bitmask_find_gap(0x0F0F070F, 5, 32, true, 11, __LINE__); + test_single_bitmask_find_gap(0x030F070F, 5, 32, true, 26, __LINE__); + test_single_bitmask_find_gap(0x030F070F, 5, 32, false, 11, __LINE__); + test_single_bitmask_find_gap(0x0F0F070F, 5, 32, true, 11, __LINE__); + test_single_bitmask_find_gap(0x030F070F, 5, 32, true, 26, __LINE__); + test_single_bitmask_find_gap(0x030F070F, 5, 32, false, 11, __LINE__); + test_single_bitmask_find_gap(0x0, 1, 32, true, 0, __LINE__); + test_single_bitmask_find_gap(0x1F1F071F, 4, 32, true, 11, __LINE__); + test_single_bitmask_find_gap(0x0000000F, 2, 6, false, 4, __LINE__); +} + ZTEST_SUITE(util, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/ztest/fail/README.rst b/tests/ztest/fail/README.rst index a87cccf4a0f33..6a38086c3b0c2 100644 --- a/tests/ztest/fail/README.rst +++ b/tests/ztest/fail/README.rst @@ -8,7 +8,7 @@ Overview In order to test the actual framework's failure cases, this test suite has to do something unique. There's a subdirectory to this test called 'core'. This project builds a sample as a -:ref:`native_sim ` or :ref:`unit_testing ` +:zephyr:board:`native_sim ` or :ref:`unit_testing ` binary which is expected to fail by calling one of the following: - ``ztest_test_fail()`` during either the ``after`` or ``teardown`` phase of the test suite - ``ztest_test_skip()`` during either the ``after`` or ``teardown`` phase of the test suite diff --git a/west.yml b/west.yml index a564256794447..ead1b90e0831d 100644 --- a/west.yml +++ b/west.yml @@ -169,7 +169,7 @@ manifest: groups: - hal - name: hal_espressif - revision: aa5443a4eea6a49d58f808f41bceb5de19678fa6 + revision: 465e13cf9e95d2b3baf211ee31ff4bcb12ae5f4e path: modules/hal/espressif west-commands: west/west-commands.yml groups: @@ -200,7 +200,7 @@ manifest: groups: - hal - name: hal_nordic - revision: a6579483deb33112cc763d05a4a3f8085883c1ac + revision: 54f33f10a0b826174fb145f155afa61ce5a44b93 path: modules/hal/nordic groups: - hal @@ -210,7 +210,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 54ebe9bfd5ecc96ee68ad54f710d92732bcc401d + revision: 809b1c1806e7e311543866758d6c2d06407f6387 path: modules/hal/nxp groups: - hal @@ -231,11 +231,11 @@ manifest: - hal - name: hal_rpi_pico path: modules/hal/rpi_pico - revision: 5a981c7c29e3846646549a1902183684f0147e1d + revision: b547a36a722af7787e5f55b551fd6ce72dcba5a4 groups: - hal - name: hal_silabs - revision: 13343bccf850eb7b6541f6e71a8d2a880209850b + revision: 14dff7b65169055e347d3ddb49ee872ecb864de1 path: modules/hal/silabs groups: - hal @@ -245,7 +245,7 @@ manifest: groups: - hal - name: hal_stm32 - revision: d46f8453c5ce28fb6aba7613de7ebc75bd8572c3 + revision: 3a4b521441607646ec43bece2c53f333ce7f9b69 path: modules/hal/stm32 groups: - hal @@ -281,7 +281,7 @@ manifest: - hal - name: hostap path: modules/lib/hostap - revision: c55683ce514953277be5566fceb38c4c2485f1e1 + revision: 5abcff1c0ecff65f0f81e0cc086b7f766e5101bf - name: liblc3 revision: 48bbd3eacd36e99a57317a0a4867002e0b09e183 path: modules/lib/liblc3 @@ -301,6 +301,9 @@ manifest: groups: - fs revision: 8f5ca347843363882619d8f96c00d8dbd88a8e79 + - name: lora-basics-modem + revision: 9a14f6772c1d6e303bacb2d594c8063bb804b6ee + path: modules/lib/lora-basics-modem - name: loramac-node revision: fb00b383072518c918e2258b0916c996f2d4eebe path: modules/lib/loramac-node @@ -313,7 +316,7 @@ manifest: groups: - crypto - name: mcuboot - revision: bf5321bb6906e9e75b4c85b7c98b71c06ae52e90 + revision: aa4fa2b6e17361dd3ce16a60883059778fd147a9 path: bootloader/mcuboot groups: - bootloader @@ -334,7 +337,7 @@ manifest: revision: 40403f5f2805cca210d2a47c8717d89c4e816cda path: modules/bsim_hw_models/nrf_hw_models - name: nrf_wifi - revision: 787eea1a3c8dd13c86214e204a919e6f9bcebf91 + revision: 5fffeab6496932abb10f9dae53ed3686967aa050 path: modules/lib/nrf_wifi - name: open-amp revision: c30a6d8b92fcebdb797fc1a7698e8729e250f637 @@ -361,7 +364,7 @@ manifest: groups: - tee - name: trusted-firmware-m - revision: 021e2bbd50c215e41710a72e05abce3224f074a7 + revision: 3e12b0cc27d828d7ec04c4ac62ad45a9a905573e path: modules/tee/tf-m/trusted-firmware-m groups: - tee