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Merge pull request #22 from Ansuel/add-ipq8064
Add support for IPQ8064 SoC
2 parents aff941f + a601807 commit d15bea7

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4 files changed

+245
-4
lines changed

4 files changed

+245
-4
lines changed

‎debugcc.c‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -116,13 +116,20 @@ void mux_disable(struct debug_mux *mux)
116116
unsigned long measure_gcc(const struct measure_clk *clk,
117117
const struct debug_mux *mux)
118118
{
119-
unsigned long raw_count_short;
120-
unsigned long raw_count_full;
119+
unsigned int xo_rate = 4800000;
120+
uint64_t raw_count_short;
121+
uint64_t raw_count_full;
121122
struct gcc_mux *gcc = container_of(mux, struct gcc_mux, mux);
122123
unsigned long xo_div4;
123124

125+
if (gcc->xo_rate)
126+
xo_rate = gcc->xo_rate;
127+
124128
xo_div4 = readl(mux->base + gcc->xo_div4_reg);
125-
writel(xo_div4 | 1, mux->base + gcc->xo_div4_reg);
129+
if (gcc->xo_div4_val)
130+
writel(xo_div4 | gcc->xo_div4_val, mux->base + gcc->xo_div4_reg);
131+
else
132+
writel(xo_div4 | 1, mux->base + gcc->xo_div4_reg);
126133

127134
raw_count_short = measure_ticks(gcc, 0x1000);
128135
raw_count_full = measure_ticks(gcc, 0x10000);
@@ -133,7 +140,7 @@ unsigned long measure_gcc(const struct measure_clk *clk,
133140
return 0;
134141
}
135142

136-
raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
143+
raw_count_full = ((raw_count_full * 10) + 15) * xo_rate;
137144
raw_count_full = raw_count_full / ((0x10000 * 10) + 35);
138145

139146
if (mux->div_val)

‎debugcc.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
#define __DEBUGCC_H__
3333

3434
#define BIT(x) (1 << (x))
35+
#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (sizeof(long) * 8 - 1 - (h))))
3536

3637
#define CORE_CC_BLOCK "core"
3738

@@ -65,7 +66,11 @@ struct debug_mux {
6566
struct gcc_mux {
6667
struct debug_mux mux;
6768

69+
unsigned int xo_rate;
70+
6871
unsigned int xo_div4_reg;
72+
unsigned int xo_div4_val;
73+
6974
unsigned int debug_ctl_reg;
7075
unsigned int debug_status_reg;
7176
};

‎ipq8064.c‎

Lines changed: 228 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,228 @@
1+
// SPDX-License-Identifier: BSD-3-Clause
2+
3+
#include <sys/mman.h>
4+
#include <err.h>
5+
#include <fcntl.h>
6+
#include <stdio.h>
7+
#include <stdint.h>
8+
#include <stdlib.h>
9+
#include <string.h>
10+
#include <unistd.h>
11+
12+
#include "debugcc.h"
13+
14+
#define GCC_PHYS 0x900000
15+
16+
#define PDM_CLK_NS_REG 0x2cc0
17+
#define XO4_CLK_DIV_4 BIT(3) | BIT(4)
18+
#define XO4_CLK_BRANCH_ENA BIT(7)
19+
#define CLK_ROOT_ENA BIT(11)
20+
#define CXO_SRC_BRANCH_ENA BIT(13)
21+
22+
#define RINGOSC_NS_REG 0x2dc0
23+
#define RO_CLK_BRANCH_ENA BIT(9)
24+
#define RO_ROOT_ENA BIT(11)
25+
26+
#define RINGOSC_TCXO_CTL_REG 0x2dc4
27+
#define RINGOSC_STATUS_REG 0x2dcc
28+
29+
#define CLK_TEST_REG 0x2fa0
30+
#define RING_OSC_DBG_SEL BIT(26) // Select cc_dbg_hs_clk instead of default value cc_ringosc_clk
31+
#define TEST_BUS_ENA BIT(23)
32+
#define TEST_BUS_SEL_MASK GENMASK(22, 19)
33+
#define HS_DBG_CLK_BRANCH_ENA BIT(17)
34+
#define DBG_CLK_HS_SEL_MASK GENMASK(16, 10)
35+
#define DBG_CLK_HS_SEL_SHIFT 10
36+
#define LS_DBG_CLK_BRANCH_ENA BIT(8)
37+
#define DBG_CLK_LS_SEL_MASK GENMASK(7, 0)
38+
39+
#define APCS_GCC_PHYS 0x2011000
40+
41+
#define APCS_CLK_DIAG_REG 0x1c
42+
#define FAST_CLK_EN BIT(7)
43+
#define FAST_CLK_SEL_MASK GENMASK(5, 3)
44+
#define FAST_CLK_SEL_SHIFT 3
45+
#define SLOW_CLK_SEL_MASK GENMASK(2, 0)
46+
47+
static struct debug_mux ringosc_mux;
48+
49+
static struct gcc_mux gcc = {
50+
.mux = {
51+
.phys = GCC_PHYS,
52+
.size = 0x4000,
53+
54+
.measure = measure_gcc,
55+
56+
.enable_reg = CLK_TEST_REG,
57+
.enable_mask = RING_OSC_DBG_SEL,
58+
59+
.parent = &ringosc_mux,
60+
},
61+
62+
// PXO == CXO == 25MHz
63+
.xo_rate = (25 * 1000 * 1000) / 4,
64+
65+
.xo_div4_reg = PDM_CLK_NS_REG,
66+
.xo_div4_val = XO4_CLK_DIV_4 | XO4_CLK_BRANCH_ENA | \
67+
CLK_ROOT_ENA | CXO_SRC_BRANCH_ENA,
68+
69+
.debug_ctl_reg = RINGOSC_TCXO_CTL_REG,
70+
.debug_status_reg = RINGOSC_STATUS_REG,
71+
};
72+
73+
static struct debug_mux ringosc_mux = {
74+
.phys = GCC_PHYS,
75+
.size = 0x4000,
76+
77+
.enable_reg = RINGOSC_NS_REG,
78+
.enable_mask = RO_CLK_BRANCH_ENA | RO_ROOT_ENA,
79+
};
80+
81+
static struct debug_mux hs_mux = {
82+
.phys = GCC_PHYS,
83+
.size = 0x4000,
84+
.block_name = "hs",
85+
86+
.measure = measure_leaf,
87+
.parent = &gcc.mux,
88+
89+
.enable_reg = CLK_TEST_REG,
90+
.enable_mask = HS_DBG_CLK_BRANCH_ENA,
91+
92+
.mux_reg = CLK_TEST_REG,
93+
.mux_mask = DBG_CLK_HS_SEL_MASK,
94+
.mux_shift = DBG_CLK_HS_SEL_SHIFT,
95+
};
96+
97+
static struct debug_mux ls_mux = {
98+
.phys = GCC_PHYS,
99+
.size = 0x4000,
100+
.block_name = "ls",
101+
102+
.measure = measure_leaf,
103+
.parent = &hs_mux,
104+
// cc_dbg_ls_out_clk
105+
.parent_mux_val = 0x43,
106+
107+
.enable_reg = CLK_TEST_REG,
108+
.enable_mask = LS_DBG_CLK_BRANCH_ENA,
109+
110+
.mux_reg = CLK_TEST_REG,
111+
.mux_mask = DBG_CLK_LS_SEL_MASK,
112+
};
113+
114+
static struct debug_mux cpul2_mux = {
115+
.phys = APCS_GCC_PHYS,
116+
.size = 0x1000,
117+
.block_name = "cpul2",
118+
119+
.measure = measure_leaf,
120+
.parent = &hs_mux,
121+
// sc_dbg_hs1_clk
122+
.parent_mux_val = 0x41,
123+
124+
.enable_reg = APCS_CLK_DIAG_REG,
125+
.enable_mask = FAST_CLK_EN,
126+
127+
.mux_reg = APCS_CLK_DIAG_REG,
128+
.mux_mask = FAST_CLK_SEL_MASK,
129+
.mux_shift = FAST_CLK_SEL_SHIFT,
130+
};
131+
132+
static struct measure_clk ipq8064_clocks[] = {
133+
{ "sdc1_p_clk", &ls_mux, 0x12 },
134+
{ "sdc1_clk", &ls_mux, 0x13 },
135+
{ "sdc3_p_clk", &ls_mux, 0x16 },
136+
{ "sdc3_clk", &ls_mux, 0x17 },
137+
{ "gp0_clk", &ls_mux, 0x1F },
138+
{ "gp1_clk", &ls_mux, 0x20 },
139+
{ "gp2_clk", &ls_mux, 0x21 },
140+
{ "dfab_clk", &ls_mux, 0x25 },
141+
{ "dfab_a_clk", &ls_mux, 0x25 },
142+
{ "pmem_clk", &ls_mux, 0x26 },
143+
{ "dma_bam_p_clk", &ls_mux, 0x32 },
144+
{ "cfpb_clk", &ls_mux, 0x33 },
145+
{ "cfpb_a_clk", &ls_mux, 0x33 },
146+
{ "gsbi1_p_clk", &ls_mux, 0x3D },
147+
{ "gsbi1_uart_clk", &ls_mux, 0x3E },
148+
{ "gsbi1_qup_clk", &ls_mux, 0x3F },
149+
{ "gsbi2_p_clk", &ls_mux, 0x41 },
150+
{ "gsbi2_uart_clk", &ls_mux, 0x42 },
151+
{ "gsbi2_qup_clk", &ls_mux, 0x44 },
152+
{ "gsbi4_p_clk", &ls_mux, 0x49 },
153+
{ "gsbi4_uart_clk", &ls_mux, 0x4A },
154+
{ "gsbi5_p_clk", &ls_mux, 0x4D },
155+
{ "gsbi5_uart_clk", &ls_mux, 0x4E },
156+
{ "gsbi5_qup_clk", &ls_mux, 0x50 },
157+
{ "gsbi6_p_clk", &ls_mux, 0x51 },
158+
{ "gsbi6_uart_clk", &ls_mux, 0x52 },
159+
{ "gsbi6_qup_clk", &ls_mux, 0x54 },
160+
{ "gsbi7_p_clk", &ls_mux, 0x55 },
161+
{ "gsbi7_uart_clk", &ls_mux, 0x56 },
162+
{ "gsbi7_qup_clk", &ls_mux, 0x58 },
163+
{ "sfab_sata_s_p_clk", &ls_mux, 0x59 },
164+
{ "sata_p_clk", &ls_mux, 0x5A },
165+
{ "sata_rxoob_clk", &ls_mux, 0x5B },
166+
{ "sata_pmalive_clk", &ls_mux, 0x5C },
167+
{ "pcie_src_clk", &ls_mux, 0x5D },
168+
{ "pcie_p_clk", &ls_mux, 0x5E },
169+
{ "ce5_p_clk", &ls_mux, 0x5F },
170+
{ "ce5_core_clk", &ls_mux, 0x60 },
171+
{ "sata_phy_ref_clk", &ls_mux, 0x6B },
172+
{ "sata_phy_cfg_clk", &ls_mux, 0x6C },
173+
{ "sfpb_clk", &ls_mux, 0x78 },
174+
{ "sfpb_a_clk", &ls_mux, 0x78 },
175+
{ "pmic_ssbi2_clk", &ls_mux, 0x7A },
176+
{ "pmic_arb0_p_clk", &ls_mux, 0x7B },
177+
{ "pmic_arb1_p_clk", &ls_mux, 0x7C },
178+
{ "prng_clk", &ls_mux, 0x7D },
179+
{ "rpm_msg_ram_p_clk", &ls_mux, 0x7F },
180+
{ "adm0_p_clk", &ls_mux, 0x80 },
181+
{ "usb_hs1_p_clk", &ls_mux, 0x84 },
182+
{ "usb_hs1_xcvr_clk", &ls_mux, 0x85 },
183+
{ "usb_hsic_p_clk", &ls_mux, 0x86 },
184+
{ "usb_hsic_system_clk", &ls_mux, 0x87 },
185+
{ "usb_hsic_xcvr_fs_clk", &ls_mux, 0x88 },
186+
{ "usb_fs1_p_clk", &ls_mux, 0x89 },
187+
{ "usb_fs1_sys_clk", &ls_mux, 0x8A },
188+
{ "usb_fs1_xcvr_clk", &ls_mux, 0x8B },
189+
{ "tsif_p_clk", &ls_mux, 0x8F },
190+
{ "tsif_ref_clk", &ls_mux, 0x91 },
191+
{ "ce1_p_clk", &ls_mux, 0x92 },
192+
{ "tssc_clk", &ls_mux, 0x94 },
193+
{ "usb_hsic_hsio_cal_clk", &ls_mux, 0x9D },
194+
{ "ce1_core_clk", &ls_mux, 0xA4 },
195+
{ "pcie1_p_clk", &ls_mux, 0xB0 },
196+
{ "pcie1_src_clk", &ls_mux, 0xB1 },
197+
{ "pcie2_p_clk", &ls_mux, 0xB2 },
198+
{ "pcie2_src_clk", &ls_mux, 0xB3 },
199+
200+
{ "afab_clk", &hs_mux, 0x07 },
201+
{ "afab_a_clk", &hs_mux, 0x07 },
202+
{ "sfab_clk", &hs_mux, 0x18 },
203+
{ "sfab_a_clk", &hs_mux, 0x18 },
204+
{ "adm0_clk", &hs_mux, 0x2A },
205+
{ "sata_a_clk", &hs_mux, 0x31 },
206+
{ "pcie_aux_clk", &hs_mux, 0x2B },
207+
{ "pcie_phy_ref_clk", &hs_mux, 0x2D },
208+
{ "pcie_a_clk", &hs_mux, 0x32 },
209+
{ "ebi1_clk", &hs_mux, 0x34 },
210+
{ "ebi1_a_clk", &hs_mux, 0x34 },
211+
{ "usb_hsic_hsic_clk", &hs_mux, 0x50 },
212+
{ "pcie1_aux_clk", &hs_mux, 0x55 },
213+
{ "pcie1_phy_ref_clk", &hs_mux, 0x56 },
214+
{ "pcie2_aux_clk", &hs_mux, 0x57 },
215+
{ "pcie2_phy_ref_clk", &hs_mux, 0x58 },
216+
{ "pcie1_a_clk", &hs_mux, 0x66 },
217+
{ "pcie2_a_clk", &hs_mux, 0x67 },
218+
219+
{ "l2_m_clk", &cpul2_mux, 0x2, 8 },
220+
{ "krait0_m_clk", &cpul2_mux, 0x0, 8 },
221+
{ "krait1_m_clk", &cpul2_mux, 0x1, 8 },
222+
{}
223+
};
224+
225+
struct debugcc_platform ipq8064_debugcc = {
226+
"ipq8064",
227+
ipq8064_clocks,
228+
};

‎meson.build‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ project('debugcc',
1010
)
1111

1212
platforms = [
13+
'ipq8064',
1314
'msm8936',
1415
'msm8994',
1516
'msm8996',

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