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kuba-mookuba-moo
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sync to upstream v6.16+ - 010510128873 ("netlink: specs: ethtool: fix module EEPROM input/output arguments")
Signed-off-by: Jakub Kicinski <[email protected]>
1 parent de557a1 commit 698c416

35 files changed

+6966
-1020
lines changed

‎generated/devlink-user.c‎

Lines changed: 50 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -79,11 +79,11 @@ static const char * const devlink_port_flavour_strmap[] = {
7979
[0] = "physical",
8080
[1] = "cpu",
8181
[2] = "dsa",
82-
[3] = "pci_pf",
83-
[4] = "pci_vf",
82+
[3] = "pci-pf",
83+
[4] = "pci-vf",
8484
[5] = "virtual",
8585
[6] = "unused",
86-
[7] = "pci_sf",
86+
[7] = "pci-sf",
8787
};
8888

8989
const char *devlink_port_flavour_str(enum devlink_port_flavour value)
@@ -324,7 +324,7 @@ static const char * const devlink_var_attr_type_strmap[] = {
324324
[4] = "u64",
325325
[5] = "string",
326326
[6] = "flag",
327-
[10] = "nul_string",
327+
[10] = "nul-string",
328328
[11] = "binary",
329329
};
330330

@@ -556,6 +556,16 @@ const struct ynl_policy_nest devlink_dl_selftest_id_nest = {
556556
.table = devlink_dl_selftest_id_policy,
557557
};
558558

559+
const struct ynl_policy_attr devlink_dl_rate_tc_bws_policy[DEVLINK_RATE_TC_ATTR_MAX + 1] = {
560+
[DEVLINK_RATE_TC_ATTR_INDEX] = { .name = "index", .type = YNL_PT_U8, },
561+
[DEVLINK_RATE_TC_ATTR_BW] = { .name = "bw", .type = YNL_PT_U32, },
562+
};
563+
564+
const struct ynl_policy_nest devlink_dl_rate_tc_bws_nest = {
565+
.max_attr = DEVLINK_RATE_TC_ATTR_MAX,
566+
.table = devlink_dl_rate_tc_bws_policy,
567+
};
568+
559569
const struct ynl_policy_attr devlink_dl_dpipe_table_matches_policy[DEVLINK_ATTR_MAX + 1] = {
560570
[DEVLINK_ATTR_DPIPE_MATCH] = { .name = "dpipe-match", .type = YNL_PT_NEST, .nest = &devlink_dl_dpipe_match_nest, },
561571
};
@@ -898,6 +908,7 @@ const struct ynl_policy_attr devlink_policy[DEVLINK_ATTR_MAX + 1] = {
898908
[DEVLINK_ATTR_RATE_TX_PRIORITY] = { .name = "rate-tx-priority", .type = YNL_PT_U32, },
899909
[DEVLINK_ATTR_RATE_TX_WEIGHT] = { .name = "rate-tx-weight", .type = YNL_PT_U32, },
900910
[DEVLINK_ATTR_REGION_DIRECT] = { .name = "region-direct", .type = YNL_PT_FLAG, },
911+
[DEVLINK_ATTR_RATE_TC_BWS] = { .name = "rate-tc-bws", .type = YNL_PT_NEST, .nest = &devlink_dl_rate_tc_bws_nest, },
901912
};
902913

903914
const struct ynl_policy_nest devlink_nest = {
@@ -1513,6 +1524,25 @@ int devlink_dl_selftest_id_put(struct nlmsghdr *nlh, unsigned int attr_type,
15131524
return 0;
15141525
}
15151526

1527+
void devlink_dl_rate_tc_bws_free(struct devlink_dl_rate_tc_bws *obj)
1528+
{
1529+
}
1530+
1531+
int devlink_dl_rate_tc_bws_put(struct nlmsghdr *nlh, unsigned int attr_type,
1532+
struct devlink_dl_rate_tc_bws *obj)
1533+
{
1534+
struct nlattr *nest;
1535+
1536+
nest = ynl_attr_nest_start(nlh, attr_type);
1537+
if (obj->_present.index)
1538+
ynl_attr_put_u8(nlh, DEVLINK_RATE_TC_ATTR_INDEX, obj->index);
1539+
if (obj->_present.bw)
1540+
ynl_attr_put_u32(nlh, DEVLINK_RATE_TC_ATTR_BW, obj->bw);
1541+
ynl_attr_nest_end(nlh, nest);
1542+
1543+
return 0;
1544+
}
1545+
15161546
void
15171547
devlink_dl_dpipe_table_matches_free(struct devlink_dl_dpipe_table_matches *obj)
15181548
{
@@ -6833,17 +6863,23 @@ devlink_rate_get_dump(struct ynl_sock *ys,
68336863
/* DEVLINK_CMD_RATE_SET - do */
68346864
void devlink_rate_set_req_free(struct devlink_rate_set_req *req)
68356865
{
6866+
unsigned int i;
6867+
68366868
free(req->bus_name);
68376869
free(req->dev_name);
68386870
free(req->rate_node_name);
68396871
free(req->rate_parent_node_name);
6872+
for (i = 0; i < req->_count.rate_tc_bws; i++)
6873+
devlink_dl_rate_tc_bws_free(&req->rate_tc_bws[i]);
6874+
free(req->rate_tc_bws);
68406875
free(req);
68416876
}
68426877

68436878
int devlink_rate_set(struct ynl_sock *ys, struct devlink_rate_set_req *req)
68446879
{
68456880
struct ynl_req_state yrs = { .yarg = { .ys = ys, }, };
68466881
struct nlmsghdr *nlh;
6882+
unsigned int i;
68476883
int err;
68486884

68496885
nlh = ynl_gemsg_start_req(ys, ys->family_id, DEVLINK_CMD_RATE_SET, 1);
@@ -6866,6 +6902,8 @@ int devlink_rate_set(struct ynl_sock *ys, struct devlink_rate_set_req *req)
68666902
ynl_attr_put_u32(nlh, DEVLINK_ATTR_RATE_TX_WEIGHT, req->rate_tx_weight);
68676903
if (req->_len.rate_parent_node_name)
68686904
ynl_attr_put_str(nlh, DEVLINK_ATTR_RATE_PARENT_NODE_NAME, req->rate_parent_node_name);
6905+
for (i = 0; i < req->_count.rate_tc_bws; i++)
6906+
devlink_dl_rate_tc_bws_put(nlh, DEVLINK_ATTR_RATE_TC_BWS, &req->rate_tc_bws[i]);
68696907

68706908
err = ynl_exec(ys, nlh, &yrs);
68716909
if (err < 0)
@@ -6878,17 +6916,23 @@ int devlink_rate_set(struct ynl_sock *ys, struct devlink_rate_set_req *req)
68786916
/* DEVLINK_CMD_RATE_NEW - do */
68796917
void devlink_rate_new_req_free(struct devlink_rate_new_req *req)
68806918
{
6919+
unsigned int i;
6920+
68816921
free(req->bus_name);
68826922
free(req->dev_name);
68836923
free(req->rate_node_name);
68846924
free(req->rate_parent_node_name);
6925+
for (i = 0; i < req->_count.rate_tc_bws; i++)
6926+
devlink_dl_rate_tc_bws_free(&req->rate_tc_bws[i]);
6927+
free(req->rate_tc_bws);
68856928
free(req);
68866929
}
68876930

68886931
int devlink_rate_new(struct ynl_sock *ys, struct devlink_rate_new_req *req)
68896932
{
68906933
struct ynl_req_state yrs = { .yarg = { .ys = ys, }, };
68916934
struct nlmsghdr *nlh;
6935+
unsigned int i;
68926936
int err;
68936937

68946938
nlh = ynl_gemsg_start_req(ys, ys->family_id, DEVLINK_CMD_RATE_NEW, 1);
@@ -6911,6 +6955,8 @@ int devlink_rate_new(struct ynl_sock *ys, struct devlink_rate_new_req *req)
69116955
ynl_attr_put_u32(nlh, DEVLINK_ATTR_RATE_TX_WEIGHT, req->rate_tx_weight);
69126956
if (req->_len.rate_parent_node_name)
69136957
ynl_attr_put_str(nlh, DEVLINK_ATTR_RATE_PARENT_NODE_NAME, req->rate_parent_node_name);
6958+
for (i = 0; i < req->_count.rate_tc_bws; i++)
6959+
devlink_dl_rate_tc_bws_put(nlh, DEVLINK_ATTR_RATE_TC_BWS, &req->rate_tc_bws[i]);
69146960

69156961
err = ynl_exec(ys, nlh, &yrs);
69166962
if (err < 0)

‎generated/dpll-user.c‎

Lines changed: 108 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -158,6 +158,18 @@ const char *dpll_pin_capabilities_str(enum dpll_pin_capabilities value)
158158
return dpll_pin_capabilities_strmap[value];
159159
}
160160

161+
static const char * const dpll_feature_state_strmap[] = {
162+
[0] = "disable",
163+
[1] = "enable",
164+
};
165+
166+
const char *dpll_feature_state_str(enum dpll_feature_state value)
167+
{
168+
if (value < 0 || value >= (int)YNL_ARRAY_SIZE(dpll_feature_state_strmap))
169+
return NULL;
170+
return dpll_feature_state_strmap[value];
171+
}
172+
161173
/* Policies */
162174
const struct ynl_policy_attr dpll_frequency_range_policy[DPLL_A_PIN_MAX + 1] = {
163175
[DPLL_A_PIN_FREQUENCY_MIN] = { .name = "frequency-min", .type = YNL_PT_U64, },
@@ -192,6 +204,16 @@ const struct ynl_policy_nest dpll_pin_parent_pin_nest = {
192204
.table = dpll_pin_parent_pin_policy,
193205
};
194206

207+
const struct ynl_policy_attr dpll_reference_sync_policy[DPLL_A_PIN_MAX + 1] = {
208+
[DPLL_A_PIN_ID] = { .name = "id", .type = YNL_PT_U32, },
209+
[DPLL_A_PIN_STATE] = { .name = "state", .type = YNL_PT_U32, },
210+
};
211+
212+
const struct ynl_policy_nest dpll_reference_sync_nest = {
213+
.max_attr = DPLL_A_PIN_MAX,
214+
.table = dpll_reference_sync_policy,
215+
};
216+
195217
const struct ynl_policy_attr dpll_policy[DPLL_A_MAX + 1] = {
196218
[DPLL_A_ID] = { .name = "id", .type = YNL_PT_U32, },
197219
[DPLL_A_MODULE_NAME] = { .name = "module-name", .type = YNL_PT_NUL_STR, },
@@ -204,6 +226,7 @@ const struct ynl_policy_attr dpll_policy[DPLL_A_MAX + 1] = {
204226
[DPLL_A_TYPE] = { .name = "type", .type = YNL_PT_U32, },
205227
[DPLL_A_LOCK_STATUS_ERROR] = { .name = "lock-status-error", .type = YNL_PT_U32, },
206228
[DPLL_A_CLOCK_QUALITY_LEVEL] = { .name = "clock-quality-level", .type = YNL_PT_U32, },
229+
[DPLL_A_PHASE_OFFSET_MONITOR] = { .name = "phase-offset-monitor", .type = YNL_PT_U32, },
207230
};
208231

209232
const struct ynl_policy_nest dpll_nest = {
@@ -239,6 +262,7 @@ const struct ynl_policy_attr dpll_pin_policy[DPLL_A_PIN_MAX + 1] = {
239262
[DPLL_A_PIN_ESYNC_FREQUENCY] = { .name = "esync-frequency", .type = YNL_PT_U64, },
240263
[DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED] = { .name = "esync-frequency-supported", .type = YNL_PT_NEST, .nest = &dpll_frequency_range_nest, },
241264
[DPLL_A_PIN_ESYNC_PULSE] = { .name = "esync-pulse", .type = YNL_PT_U32, },
265+
[DPLL_A_PIN_REFERENCE_SYNC] = { .name = "reference-sync", .type = YNL_PT_NEST, .nest = &dpll_reference_sync_nest, },
242266
};
243267

244268
const struct ynl_policy_nest dpll_pin_nest = {
@@ -385,6 +409,50 @@ int dpll_pin_parent_pin_parse(struct ynl_parse_arg *yarg,
385409
return 0;
386410
}
387411

412+
void dpll_reference_sync_free(struct dpll_reference_sync *obj)
413+
{
414+
}
415+
416+
int dpll_reference_sync_put(struct nlmsghdr *nlh, unsigned int attr_type,
417+
struct dpll_reference_sync *obj)
418+
{
419+
struct nlattr *nest;
420+
421+
nest = ynl_attr_nest_start(nlh, attr_type);
422+
if (obj->_present.id)
423+
ynl_attr_put_u32(nlh, DPLL_A_PIN_ID, obj->id);
424+
if (obj->_present.state)
425+
ynl_attr_put_u32(nlh, DPLL_A_PIN_STATE, obj->state);
426+
ynl_attr_nest_end(nlh, nest);
427+
428+
return 0;
429+
}
430+
431+
int dpll_reference_sync_parse(struct ynl_parse_arg *yarg,
432+
const struct nlattr *nested)
433+
{
434+
struct dpll_reference_sync *dst = yarg->data;
435+
const struct nlattr *attr;
436+
437+
ynl_attr_for_each_nested(attr, nested) {
438+
unsigned int type = ynl_attr_type(attr);
439+
440+
if (type == DPLL_A_PIN_ID) {
441+
if (ynl_attr_validate(yarg, attr))
442+
return YNL_PARSE_CB_ERROR;
443+
dst->_present.id = 1;
444+
dst->id = ynl_attr_get_u32(attr);
445+
} else if (type == DPLL_A_PIN_STATE) {
446+
if (ynl_attr_validate(yarg, attr))
447+
return YNL_PARSE_CB_ERROR;
448+
dst->_present.state = 1;
449+
dst->state = ynl_attr_get_u32(attr);
450+
}
451+
}
452+
453+
return 0;
454+
}
455+
388456
/* ============== DPLL_CMD_DEVICE_ID_GET ============== */
389457
/* DPLL_CMD_DEVICE_ID_GET - do */
390458
void dpll_device_id_get_req_free(struct dpll_device_id_get_req *req)
@@ -534,6 +602,11 @@ int dpll_device_get_rsp_parse(const struct nlmsghdr *nlh,
534602
return YNL_PARSE_CB_ERROR;
535603
dst->_present.type = 1;
536604
dst->type = ynl_attr_get_u32(attr);
605+
} else if (type == DPLL_A_PHASE_OFFSET_MONITOR) {
606+
if (ynl_attr_validate(yarg, attr))
607+
return YNL_PARSE_CB_ERROR;
608+
dst->_present.phase_offset_monitor = 1;
609+
dst->phase_offset_monitor = ynl_attr_get_u32(attr);
537610
}
538611
}
539612

@@ -652,6 +725,8 @@ int dpll_device_set(struct ynl_sock *ys, struct dpll_device_set_req *req)
652725

653726
if (req->_present.id)
654727
ynl_attr_put_u32(nlh, DPLL_A_ID, req->id);
728+
if (req->_present.phase_offset_monitor)
729+
ynl_attr_put_u32(nlh, DPLL_A_PHASE_OFFSET_MONITOR, req->phase_offset_monitor);
655730

656731
err = ynl_exec(ys, nlh, &yrs);
657732
if (err < 0)
@@ -766,6 +841,9 @@ void dpll_pin_get_rsp_free(struct dpll_pin_get_rsp *rsp)
766841
for (i = 0; i < rsp->_count.esync_frequency_supported; i++)
767842
dpll_frequency_range_free(&rsp->esync_frequency_supported[i]);
768843
free(rsp->esync_frequency_supported);
844+
for (i = 0; i < rsp->_count.reference_sync; i++)
845+
dpll_reference_sync_free(&rsp->reference_sync[i]);
846+
free(rsp->reference_sync);
769847
free(rsp);
770848
}
771849

@@ -774,6 +852,7 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
774852
{
775853
unsigned int n_esync_frequency_supported = 0;
776854
unsigned int n_frequency_supported = 0;
855+
unsigned int n_reference_sync = 0;
777856
unsigned int n_parent_device = 0;
778857
unsigned int n_parent_pin = 0;
779858
struct dpll_pin_get_rsp *dst;
@@ -792,6 +871,8 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
792871
return ynl_error_parse(yarg, "attribute already present (pin.parent-device)");
793872
if (dst->parent_pin)
794873
return ynl_error_parse(yarg, "attribute already present (pin.parent-pin)");
874+
if (dst->reference_sync)
875+
return ynl_error_parse(yarg, "attribute already present (pin.reference-sync)");
795876

796877
ynl_attr_for_each(attr, nlh, yarg->ys->family->hdr_len) {
797878
unsigned int type = ynl_attr_type(attr);
@@ -887,6 +968,8 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
887968
return YNL_PARSE_CB_ERROR;
888969
dst->_present.esync_pulse = 1;
889970
dst->esync_pulse = ynl_attr_get_u32(attr);
971+
} else if (type == DPLL_A_PIN_REFERENCE_SYNC) {
972+
n_reference_sync++;
890973
}
891974
}
892975

@@ -946,6 +1029,20 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
9461029
}
9471030
}
9481031
}
1032+
if (n_reference_sync) {
1033+
dst->reference_sync = calloc(n_reference_sync, sizeof(*dst->reference_sync));
1034+
dst->_count.reference_sync = n_reference_sync;
1035+
i = 0;
1036+
parg.rsp_policy = &dpll_reference_sync_nest;
1037+
ynl_attr_for_each(attr, nlh, yarg->ys->family->hdr_len) {
1038+
if (ynl_attr_type(attr) == DPLL_A_PIN_REFERENCE_SYNC) {
1039+
parg.data = &dst->reference_sync[i];
1040+
if (dpll_reference_sync_parse(&parg, attr))
1041+
return YNL_PARSE_CB_ERROR;
1042+
i++;
1043+
}
1044+
}
1045+
}
9491046

9501047
return YNL_PARSE_CB_OK;
9511048
}
@@ -1013,6 +1110,9 @@ void dpll_pin_get_list_free(struct dpll_pin_get_list *rsp)
10131110
for (i = 0; i < rsp->obj._count.esync_frequency_supported; i++)
10141111
dpll_frequency_range_free(&rsp->obj.esync_frequency_supported[i]);
10151112
free(rsp->obj.esync_frequency_supported);
1113+
for (i = 0; i < rsp->obj._count.reference_sync; i++)
1114+
dpll_reference_sync_free(&rsp->obj.reference_sync[i]);
1115+
free(rsp->obj.reference_sync);
10161116
free(rsp);
10171117
}
10181118
}
@@ -1069,6 +1169,9 @@ void dpll_pin_get_ntf_free(struct dpll_pin_get_ntf *rsp)
10691169
for (i = 0; i < rsp->obj._count.esync_frequency_supported; i++)
10701170
dpll_frequency_range_free(&rsp->obj.esync_frequency_supported[i]);
10711171
free(rsp->obj.esync_frequency_supported);
1172+
for (i = 0; i < rsp->obj._count.reference_sync; i++)
1173+
dpll_reference_sync_free(&rsp->obj.reference_sync[i]);
1174+
free(rsp->obj.reference_sync);
10721175
free(rsp);
10731176
}
10741177

@@ -1084,6 +1187,9 @@ void dpll_pin_set_req_free(struct dpll_pin_set_req *req)
10841187
for (i = 0; i < req->_count.parent_pin; i++)
10851188
dpll_pin_parent_pin_free(&req->parent_pin[i]);
10861189
free(req->parent_pin);
1190+
for (i = 0; i < req->_count.reference_sync; i++)
1191+
dpll_reference_sync_free(&req->reference_sync[i]);
1192+
free(req->reference_sync);
10871193
free(req);
10881194
}
10891195

@@ -1116,6 +1222,8 @@ int dpll_pin_set(struct ynl_sock *ys, struct dpll_pin_set_req *req)
11161222
ynl_attr_put_s32(nlh, DPLL_A_PIN_PHASE_ADJUST, req->phase_adjust);
11171223
if (req->_present.esync_frequency)
11181224
ynl_attr_put_u64(nlh, DPLL_A_PIN_ESYNC_FREQUENCY, req->esync_frequency);
1225+
for (i = 0; i < req->_count.reference_sync; i++)
1226+
dpll_reference_sync_put(nlh, DPLL_A_PIN_REFERENCE_SYNC, &req->reference_sync[i]);
11191227

11201228
err = ynl_exec(ys, nlh, &yrs);
11211229
if (err < 0)

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