driver: fix DDR2 W9751G6NB timing for sam9x7 sip

The number of tRC cycles is between 0 and 15. When tRC is greater than
or equal to 60 ns, the maximum supported frequency is 250 MHz. When
the frequency is higher than 200 MHz, an offset of one is added
automatically. In such case, tRC must be set to 15 to match the value.
If the frequency is higher than 200MHz, the CAS latency must be set
higher than 3. For sam9x7, the frequency is 266MHz, the CAS should be 5.
Adjust the DDR2 timings(tRCD, tRP, tRC and tRAS) with DDR2-800D @cl=5.

Signed-off-by: Xing Chen <[email protected]>

Author: LiBinSHA

device/sam9x7/sam9x7.c

@@ -331,7 +331,7 @@ void hw_init(void)
 
 	reg = readl(AT91C_BASE_SFR + SFR_DDRCFG);
 
-#ifdef CONFIG_DDR3
+#if defined(CONFIG_DDR2) || defined(CONFIG_DDR3)
 	reg |= (AT91C_EBI_CS1A | AT91C_EBI_DDR_MP_EN);
 	writel(reg, (AT91C_BASE_SFR + SFR_DDRCFG));
 	/* Initialize DDRAM Controller */

driver/ddramc.c

@@ -130,12 +130,13 @@ static void ddram_reg_config(struct ddramc_register *ddramc_config)
 	dbw = AT91C_DDRC2_DBW_16_BITS;
 	col = AT91C_DDRC2_NC_DDR10_SDR9;
 	row = AT91C_DDRC2_NR_13;
-	cas = AT91C_DDRC2_CAS_3;
 	bank = AT91C_DDRC2_NB_BANKS_4;
 #if defined(CONFIG_BUS_SPEED_200MHZ)
+	cas = AT91C_DDRC2_CAS_3;
 	/* Refresh Timer is (64ms / 8k) * 116MHz = 1562(0x61a) */
 	ddramc_config->rtr = 0x61a;
 #elif defined(CONFIG_BUS_SPEED_266MHZ)
+	cas = AT91C_DDRC2_CAS_5;
 	/* Refresh Timer is (64ms / 8k) * 116MHz = 2078(0x81e) */
 	ddramc_config->rtr = 0x81e;
 #else

include/ddr_device.h

@@ -202,22 +202,22 @@ static const struct ddram_timings ddr_ddram_timings = {
 	.tfaw = 8,
 #elif defined(CONFIG_BUS_SPEED_266MHZ)
 	.tras = 12,
-	.trcd = 3,
+	.trcd = 4,
 	.twr = 4,
 	.trc = 15,
-	.trp = 3,
+	.trp = 4,
 	.trrd = 3,
 	.twtr = 2,
 	.tmrd = 2,
 	.trfc = 28,
-	.txsnr = 38,
+	.txsnr = 31,
 	.txsrd = 200,
 	.txp = 2,
 	.txard = 2,
-	.txards = 6,
-	.trpa = 3,
+	.txards = 8,
+	.trpa = 5,
 	.trtp = 2,
-	.tfaw = 10,
+	.tfaw = 12,
 #endif
 #elif defined(CONFIG_DDR_W632GU6MB)
 /* Two DDR3L(W632GU6MB-12 = 16 Mbit x 16 x 8 banks), total 4 Gbit on SAMA5D2 ICP*/