Revert "driver:dram: align the device name of the 2g dram sip"

This reverts commit 5776d65.

Author: gehariprasath

configs/sam9x75_som2g_nf_uboot_defconfig

@@ -5,7 +5,7 @@
 CONFIG_SAM9X7=y
 CONFIG_DEBUG=y
 CONFIG_DDR_SET_BY_DEVICE=y
-CONFIG_DDR_W632GU6NB12I=y
+CONFIG_DDR_W632GU6NG=y
 CONFIG_NANDFLASH=y
 CONFIG_NAND_TIMING_MODE=y
 CONFIG_NAND_DMA_SUPPORT=y

configs/sam9x75_som2g_sd_uboot_defconfig

@@ -5,5 +5,5 @@
 CONFIG_SAM9X7=y
 CONFIG_DEBUG=y
 CONFIG_DDR_SET_BY_DEVICE=y
-CONFIG_DDR_W632GU6NB12I=y
+CONFIG_DDR_W632GU6NG=y
 CONFIG_SDCARD=y

driver/Config.in.dram

@@ -82,6 +82,11 @@ config DDR_W971GG6SB
 	depends on DDRC
 	help
 		DDR2 W971GG6SB 1 Gbit
+config DDR_W632GU6NG
+	bool "DDR3L W632GU6NG (SAM9X75-2G SiP)"
+	depends on DDRC
+	help
+		DDR3L W632GU6NG 2 Gbit
 config DDR_W9751G6NB
 	bool "DDR3L W9751G6NB (SAM9X75-512M SiP)"
 	depends on DDRC
@@ -147,7 +152,8 @@ config DDR_W631GU6NB12I
   help
     DDR3L W631GU6NB12I 8 Meg x 16 x 8 DDR3-1600
 config DDR_W632GU6NB12I
-	bool "DDR3L W632GU6NB12I(SAM9X75|SAMA7G54|SAMA7D65 2G-SIP)"
+	bool "DDR3L W632GU6NB12I(SAMA7G54|SAMA7D65 2G-SIP)"
+	depends on UMCTL2
 	help
 		DDR3L W632GU6N12I 16 Meg x 16 x 8 DDR3L-1600
 config DDR_W634GU6NB12I

driver/ddramc.c

@@ -77,8 +77,8 @@ static void ddram_reg_config(struct ddramc_register *ddramc_config)
 #else
 	#error "No CLK setting defined"
 #endif
-#elif defined(CONFIG_DDR_W632GU6NB12I)
-/* DDR3L(W632GU6NB12I = 16 Mbit x 16 x 8 banks), total 2Gbit on SAM9X75D2G */
+#elif defined(CONFIG_DDR_W632GU6NG)
+/* DDR3L(W632GU6NG = 16 Mbit x 16 x 8 banks), total 2Gbit on SAM9X75D2G */
 	type = AT91C_DDRC2_MD_DDR3_SDRAM;
 	dbw = AT91C_DDRC2_DBW_16_BITS;
 	col = AT91C_DDRC2_NC_DDR10_SDR9;

driver/driver_cpp.mk

@@ -27,6 +27,9 @@ endif
 ifeq ($(CONFIG_DDR_MT41K128M16),y)
 CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR_2_GBIT
 endif
+ifeq ($(CONFIG_DDR_W632GU6NG),y)
+CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR_2_GBIT
+endif
 ifeq ($(CONFIG_DDR_W9751G6NB),y)
 CPPFLAGS += -DCONFIG_DDR2 -DCONFIG_DDR_512_MBIT
 endif

include/ddr_device.h

@@ -97,8 +97,8 @@ static const struct ddram_timings ddr_ddram_timings = {
 	#error "No CLK setting defined"
 #endif /* Endif of CONFIG_BUS_SPEED_200MHZ */
 
-#elif defined(CONFIG_DDR_W632GU6NB12I)
-/* DDR3L (W632GU6NB12I = 16 Mbit x 16 x 8 banks), total 2Gbit on SAM9X75D2G */
+#elif defined(CONFIG_DDR_W632GU6NG)
+/* DDR3L (W632GU6NG = 16 Mbit x 16 x 8 banks), total 2Gbit on SAM9X75D2G */
 #if defined(CONFIG_BUS_SPEED_200MHZ)
 	.tras = 7,
 	.trcd = 3,