|
10 | 10 | import re |
11 | 11 | import sys |
12 | 12 | import argparse |
| 13 | +import shutil |
13 | 14 |
|
14 | 15 | from litex.soc.integration.builder import Builder |
15 | 16 | from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP |
@@ -59,6 +60,9 @@ def main(): |
59 | 60 | parser.add_argument("--spi-data-width", default=8, type=int, help="SPI data width (max bits per xfer).") |
60 | 61 | parser.add_argument("--spi-clk-freq", default=1e6, type=int, help="SPI clock frequency.") |
61 | 62 | parser.add_argument("--fdtoverlays", default="", help="Device Tree Overlays to apply.") |
| 63 | + parser.add_argument("--rootfs", default="ram0", help="Location of the RootFS.", |
| 64 | + choices=["ram0", "mmcblk0p2"] |
| 65 | + ) |
62 | 66 | VexRiscvSMP.args_fill(parser) |
63 | 67 | args = parser.parse_args() |
64 | 68 |
|
@@ -174,12 +178,15 @@ def main(): |
174 | 178 | builder.build(run=args.build, build_name=board_name) |
175 | 179 |
|
176 | 180 | # DTS -------------------------------------------------------------------------------------- |
177 | | - soc.generate_dts(board_name) |
| 181 | + soc.generate_dts(board_name, args.rootfs) |
178 | 182 | soc.compile_dts(board_name, args.fdtoverlays) |
179 | 183 |
|
180 | 184 | # DTB -------------------------------------------------------------------------------------- |
181 | 185 | soc.combine_dtb(board_name, args.fdtoverlays) |
182 | 186 |
|
| 187 | + # boot.json -------------------------------------------------------------------------------- |
| 188 | + shutil.copyfile(f"images/boot_{args.rootfs}.json", "images/boot.json") |
| 189 | + |
183 | 190 | # PCIe Driver ------------------------------------------------------------------------------ |
184 | 191 | if "pcie" in board.soc_capabilities: |
185 | 192 | from litepcie.software import generate_litepcie_software |
|
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