SoC bus: AXI instead of Wishbone. Is it possible?

[pcotret]

#138

There is this old issue where a user wanted to use AXI instead of Wishbone. I'd like to know what is the situation nowadays: is it possible to use AXI there? (the bus-standard flag isn't implemented in the make Python script).

I'd glad to help to make it working with an AXI/AXI-lite bus. Not exactly sure of which parts need to be modified.