ZCU104: Unable to Boot or Connect to Linux on the LiteX VexRiscv SoC

[manili]

Hi all,

I'm trying to bring up a the LiteX VexRiscv SoC on a ZCU104 board and running Linux on it, following the instructions from this repo. I’ve managed to build everything (Linux and SoC) from scratch. I'm not sure yet, but I believe most steps completed successfully—however, it seems like I’m still unable to connect to the running Linux system on the board (or maybe download the Linux image on the SoC).

What I’ve Done So Far

• Followed the instructions from this repo.
• Successfully built both the LiteX VexRiscv SoC and the Linux system.
• Simulated the design on my laptop using ./sim.py — Linux boots up fine in simulation.
• Programmed the ZCU104’s PL using Vivado Hardware Manager — after JTAG programming, I see the expected LED pattern blinking (some sort of circular blinking).

Where I’m Stuck

I’m trying to connect to the Linux console via litex_term, but I get no output at all. So right now I can't tell:

1. Whether the LiteX VexRiscv SoC is actually running in the PL.
2. Whether Linux has booted at all.

My Assumption (but not 100% sure)

As far as I understand, all the main peripherals on the ZCU104 board—RAM, USB, SD card, Ethernet, UART-to-USB—are connected to the PS side. The LiteX VexRiscv SoC and its Linux system, however, run on the PL side.

So I’m guessing the PL design is not able to access memory or communicate through UART unless the PS is set up to act as a bridge or provide access. But I don’t know how to configure this correctly.

Specifically:

• How can I configure the PS side (e.g. boot mode, FSBL, interconnect) to let the PL-hosted Linux use memory or peripherals?
• How can I route the LiteX UART input/output (liteuart) to a UART/USB port on the board that I can connect to via litex_term?

Thanks in advance!

[manili]

I just noticed that the simulation process takes more than usual, and it is stuck at [ 6.425654] Run /init as init process for several hours now.

manili@ubuntu:~/LiteX/linux-on-litex-vexriscv$ ./sim.py
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2025-08-01 07:21:32)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv_smp added.
INFO:SoC:CPU vexriscv_smp adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv_smp overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv_smp setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv_smp adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU vexriscv_smp adding SoC components.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCBusHandler:opensbi Region added at Origin: 0x40f00000, Size: 0x00080000, Mode:  RW, Cached:  True, Linker:  True.
INFO:SoCBusHandler:plic Region added at Origin: 0xf0c00000, Size: 0x00400000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:plic added as Bus Slave.
INFO:SoCBusHandler:clint Region added at Origin: 0xf0010000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:clint added as Bus Slave.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00010000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00010000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 1.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 2.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x04000000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (1 <-> 6).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:sdram CSR allocated at Location 1.
INFO:SoCCSRHandler:supervisor CSR allocated at Location 4.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False
Bus Regions: (7)
rom                 : Origin: 0x00000000, Size: 0x00010000, Mode:  RX, Cached:  True, Linker: False
sram                : Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False
main_ram            : Origin: 0x40000000, Size: 0x04000000, Mode: RWX, Cached:  True, Linker: False
opensbi             : Origin: 0x40f00000, Size: 0x00080000, Mode:  RW, Cached:  True, Linker:  True
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False
clint               : Origin: 0xf0010000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False
plic                : Origin: 0xf0c00000, Size: 0x00400000, Mode:  RW, Cached: False, Linker: False
Bus Masters: (1)
- cpu_bus0
Bus Slaves: (6)
- plic
- clint
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (5)
- ctrl       : 0
- sdram      : 1
- uart       : 2
- timer0     : 3
- supervisor : 4
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (3)
- noirq  : 0
- uart   : 1
- timer0 : 2
INFO:SoC:--------------------------------------------------------------------------------
VexRiscv cluster : VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
SoCLinux
└─── crg (CRG)
└─── bus (SoCBusHandler)
│    └─── _interconnect (InterconnectShared)
│    │    └─── arbiter (Arbiter)
│    │    │    └─── rr (RoundRobin)
│    │    └─── decoder (Decoder)
│    │    └─── timeout (Timeout)
│    │    │    └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (VexRiscvSMP)
│    └─── [VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1]
└─── rom (SRAM)
└─── sram (SRAM)
└─── uart_phy (RS232PHYModel)
└─── uart (UART)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
│    │    └─── eventsourceprocess_1* (EventSourceProcess)
│    └─── tx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
│    └─── rx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
└─── supervisor (Supervisor)
└─── sdrphy (SDRAMPHYModel)
│    └─── dfiphasemodel_0* (DFIPhaseModel)
│    └─── bankmodel_0* (BankModel)
│    └─── bankmodel_1* (BankModel)
│    └─── bankmodel_2* (BankModel)
│    └─── bankmodel_3* (BankModel)
└─── sdram (LiteDRAMCore)
│    └─── dfii (DFIInjector)
│    │    └─── pi0 (PhaseInjector)
│    └─── controller (LiteDRAMController)
│    │    └─── refresher (Refresher)
│    │    │    └─── timer (RefreshTimer)
│    │    │    └─── postponer (RefreshPostponer)
│    │    │    └─── sequencer (RefreshSequencer)
│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_0* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_1* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_2* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_3* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── multiplexer (Multiplexer)
│    │    │    └─── choose_cmd (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── choose_req (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── _steerer_0* (_Steerer)
│    │    │    └─── trrdcon (tXXDController)
│    │    │    └─── tfawcon (tFAWController)
│    │    │    └─── tccdcon (tXXDController)
│    │    │    └─── twtrcon (tXXDController)
│    │    │    └─── fsm (FSM)
│    └─── crossbar (LiteDRAMCrossbar)
│    │    └─── roundrobin_0* (RoundRobin)
│    │    └─── roundrobin_1* (RoundRobin)
│    │    └─── roundrobin_2* (RoundRobin)
│    │    └─── roundrobin_3* (RoundRobin)
└─── converter_0* (Converter)
└─── wishbone_bridge (LiteDRAMWishbone2Native)
│    └─── fsm (FSM)
└─── csr_bridge (Wishbone2CSR)
│    └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│    └─── csrbank_0* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── csrbank_1* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstorage_4* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── csrbank_2* (CSRBank)
│    └─── csrbank_3* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_4* (CSRStorage)
│    └─── csrbank_4* (CSRBank)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstatus_3* (CSRStatus)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstatus_4* (CSRStatus)
│    │    └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.

INFO:SoC:--------------------------------------------------------------------------------
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libc'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libc'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libcompiler_rt'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libbase'
 CC       console.o
 CC       system.o
 CC       memtest.o
 CC       uart.o
 CC       spiflash.o
 CC       i2c.o
 CC       isr.o
 CC       hyperram.o
/home/manili/LiteX/litex/litex/soc/software/libbase/isr.c:54:6: warning: no previous prototype for 'plic_init' [-Wmissing-prototypes]
   54 | void plic_init(void)
      |      ^~~~~~~~~
 AR       libbase.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libbase'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libfatfs'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libfatfs'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitespi'
 CC       spiflash.o
 CC       spiram.o
 AR       liblitespi.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitespi'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitedram'
 CC       sdram.o
 CC       bist.o
 CC       sdram_dbg.o
 CC       sdram_spd.o
 CC       utils.o
 CC       accessors.o
 AR       liblitedram.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitedram'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libliteeth'
 CC       udp.o
 CC       tftp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libliteeth'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesdcard'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesata'
 CC       sata.o
 AR       liblitesata.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesata'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/bios'
 CC       boot.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       sim_debug.o
 CC       main.o
 CC       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.crcfbigen bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 25.39KiB 	(39.67%)
RAM usage: 1.64KiB 	(20.51%)

make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x65a0).
INFO:SoC:Auto-Resizing ROM rom from 0x10000 to 0x65a0.
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2025-08-01 07:21:43)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv_smp added.
INFO:SoC:CPU vexriscv_smp adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv_smp setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv_smp adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU vexriscv_smp adding SoC components.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCBusHandler:opensbi Region added at Origin: 0x40f00000, Size: 0x00080000, Mode:  RW, Cached:  True, Linker:  True.
INFO:SoCBusHandler:plic Region added at Origin: 0xf0c00000, Size: 0x00400000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:plic added as Bus Slave.
INFO:SoCBusHandler:clint Region added at Origin: 0xf0010000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:clint added as Bus Slave.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00010000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00010000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 1.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 2.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x04000000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (1 <-> 6).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:sdram CSR allocated at Location 1.
INFO:SoCCSRHandler:supervisor CSR allocated at Location 4.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False
Bus Regions: (7)
rom                 : Origin: 0x00000000, Size: 0x00010000, Mode:  RX, Cached:  True, Linker: False
sram                : Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False
main_ram            : Origin: 0x40000000, Size: 0x04000000, Mode: RWX, Cached:  True, Linker: False
opensbi             : Origin: 0x40f00000, Size: 0x00080000, Mode:  RW, Cached:  True, Linker:  True
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False
clint               : Origin: 0xf0010000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False
plic                : Origin: 0xf0c00000, Size: 0x00400000, Mode:  RW, Cached: False, Linker: False
Bus Masters: (1)
- cpu_bus0
Bus Slaves: (6)
- plic
- clint
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (5)
- ctrl       : 0
- sdram      : 1
- uart       : 2
- timer0     : 3
- supervisor : 4
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (3)
- noirq  : 0
- uart   : 1
- timer0 : 2
INFO:SoC:--------------------------------------------------------------------------------
VexRiscv cluster : VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
SoCLinux
└─── crg (CRG)
└─── bus (SoCBusHandler)
│    └─── _interconnect (InterconnectShared)
│    │    └─── arbiter (Arbiter)
│    │    │    └─── rr (RoundRobin)
│    │    └─── decoder (Decoder)
│    │    └─── timeout (Timeout)
│    │    │    └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (VexRiscvSMP)
│    └─── [VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1]
└─── rom (SRAM)
└─── sram (SRAM)
└─── uart_phy (RS232PHYModel)
└─── uart (UART)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
│    │    └─── eventsourceprocess_1* (EventSourceProcess)
│    └─── tx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
│    └─── rx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
└─── supervisor (Supervisor)
└─── sdrphy (SDRAMPHYModel)
│    └─── dfiphasemodel_0* (DFIPhaseModel)
│    └─── bankmodel_0* (BankModel)
│    └─── bankmodel_1* (BankModel)
│    └─── bankmodel_2* (BankModel)
│    └─── bankmodel_3* (BankModel)
└─── sdram (LiteDRAMCore)
│    └─── dfii (DFIInjector)
│    │    └─── pi0 (PhaseInjector)
│    └─── controller (LiteDRAMController)
│    │    └─── refresher (Refresher)
│    │    │    └─── timer (RefreshTimer)
│    │    │    └─── postponer (RefreshPostponer)
│    │    │    └─── sequencer (RefreshSequencer)
│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_0* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_1* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_2* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_3* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── multiplexer (Multiplexer)
│    │    │    └─── choose_cmd (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── choose_req (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── _steerer_0* (_Steerer)
│    │    │    └─── trrdcon (tXXDController)
│    │    │    └─── tfawcon (tFAWController)
│    │    │    └─── tccdcon (tXXDController)
│    │    │    └─── twtrcon (tXXDController)
│    │    │    └─── fsm (FSM)
│    └─── crossbar (LiteDRAMCrossbar)
│    │    └─── roundrobin_0* (RoundRobin)
│    │    └─── roundrobin_1* (RoundRobin)
│    │    └─── roundrobin_2* (RoundRobin)
│    │    └─── roundrobin_3* (RoundRobin)
└─── converter_0* (Converter)
└─── wishbone_bridge (LiteDRAMWishbone2Native)
│    └─── fsm (FSM)
└─── csr_bridge (Wishbone2CSR)
│    └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│    └─── csrbank_0* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── csrbank_1* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstorage_4* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── csrbank_2* (CSRBank)
│    └─── csrbank_3* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_4* (CSRStorage)
│    └─── csrbank_4* (CSRBank)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstatus_3* (CSRStatus)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstatus_4* (CSRStatus)
│    │    └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.

INFO:SoC:--------------------------------------------------------------------------------
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libc'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libc'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libcompiler_rt'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libbase'
 CC       console.o
 CC       system.o
 CC       memtest.o
 CC       uart.o
 CC       spiflash.o
 CC       i2c.o
 CC       isr.o
 CC       hyperram.o
/home/manili/LiteX/litex/litex/soc/software/libbase/isr.c:54:6: warning: no previous prototype for 'plic_init' [-Wmissing-prototypes]
   54 | void plic_init(void)
      |      ^~~~~~~~~
 AR       libbase.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libbase'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libfatfs'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libfatfs'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitespi'
 CC       spiflash.o
 CC       spiram.o
 AR       liblitespi.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitespi'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitedram'
 CC       sdram.o
 CC       bist.o
 CC       sdram_spd.o
 CC       sdram_dbg.o
 CC       utils.o
 CC       accessors.o
 AR       liblitedram.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitedram'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libliteeth'
 CC       udp.o
 CC       tftp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/libliteeth'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesdcard'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesata'
 CC       sata.o
 AR       liblitesata.a
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/liblitesata'
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/bios'
 CC       boot.o
 CC       cmd_bios.o
 CC       cmd_boot.o
 CC       cmd_mem.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       sim_debug.o
 CC       main.o
 CC       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.crcfbigen bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 25.39KiB 	(39.67%)
RAM usage: 1.64KiB 	(20.51%)

make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x65a0).
INFO:SoC:Auto-Resizing ROM rom from 0x10000 to 0x65a0.
make: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware'
mkdir -p modules
make -C modules -f /home/manili/LiteX/litex/litex/build/sim/core/modules/Makefile
make[1]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules'
mkdir -p xgmii_ethernet
make MOD=xgmii_ethernet -C xgmii_ethernet -f /home/manili/LiteX/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/xgmii_ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/xgmii_ethernet'
cp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so
mkdir -p ethernet
make MOD=ethernet -C ethernet -f /home/manili/LiteX/litex/litex/build/sim/core/modules/ethernet/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/ethernet'
cp ethernet/ethernet.so ethernet.so
mkdir -p serial2console
make MOD=serial2console -C serial2console -f /home/manili/LiteX/litex/litex/build/sim/core/modules/serial2console/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/serial2console'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/serial2console'
cp serial2console/serial2console.so serial2console.so
mkdir -p serial2tcp
make MOD=serial2tcp -C serial2tcp -f /home/manili/LiteX/litex/litex/build/sim/core/modules/serial2tcp/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/serial2tcp'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/serial2tcp'
cp serial2tcp/serial2tcp.so serial2tcp.so
mkdir -p clocker
make MOD=clocker -C clocker -f /home/manili/LiteX/litex/litex/build/sim/core/modules/clocker/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/clocker'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/clocker'
cp clocker/clocker.so clocker.so
mkdir -p spdeeprom
make MOD=spdeeprom -C spdeeprom -f /home/manili/LiteX/litex/litex/build/sim/core/modules/spdeeprom/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/spdeeprom'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/spdeeprom'
cp spdeeprom/spdeeprom.so spdeeprom.so
mkdir -p gmii_ethernet
make MOD=gmii_ethernet -C gmii_ethernet -f /home/manili/LiteX/litex/litex/build/sim/core/modules/gmii_ethernet/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/gmii_ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/gmii_ethernet'
cp gmii_ethernet/gmii_ethernet.so gmii_ethernet.so
mkdir -p jtagremote
make MOD=jtagremote -C jtagremote -f /home/manili/LiteX/litex/litex/build/sim/core/modules/jtagremote/Makefile
make[2]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/jtagremote'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules/jtagremote'
cp jtagremote/jtagremote.so jtagremote.so
make[1]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/modules'
mkdir -p /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir
cc -c -ggdb -Wall -O3    -o /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir/modules.o /home/manili/LiteX/litex/litex/build/sim/core/modules.c
In file included from /usr/include/string.h:495,
                 from /home/manili/LiteX/litex/litex/build/sim/core/modules.c:5:
In function ‘strcat’,
    inlined from ‘tinydir_readfile’ at /home/manili/LiteX/litex/litex/build/sim/core/tinydir.h:532:2,
    inlined from ‘litex_sim_load_ext_modules’ at /home/manili/LiteX/litex/litex/build/sim/core/modules.c:68:14:
/usr/include/x86_64-linux-gnu/bits/string_fortified.h:128:10: warning: ‘__builtin___strcat_chk’ accessing 4097 or more bytes at offsets 0 and 4096 may overlap 1 byte at offset 4096 [-Wrestrict]
  128 |   return __builtin___strcat_chk (__dest, __src, __bos (__dest));
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc -c -ggdb -Wall -O3    -o /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir/pads.o /home/manili/LiteX/litex/litex/build/sim/core/pads.c
cc -c -ggdb -Wall -O3    -o /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir/sim.o /home/manili/LiteX/litex/litex/build/sim/core/sim.c
cc -c -ggdb -Wall -O3    -o /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir/libdylib.o /home/manili/LiteX/litex/litex/build/sim/core/libdylib.c
cc -c -ggdb -Wall -O3    -o /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir/parse.o /home/manili/LiteX/litex/litex/build/sim/core/parse.c
verilator -Wno-fatal -O3 --cc /home/manili/LiteX/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/Ram_1w_1rs_Generic.v --cc /home/manili/LiteX/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1.v --cc /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/sim.v  --top-module sim --exe \
	-DPRINTF_COND=0 \
	sim_init.cpp /home/manili/LiteX/litex/litex/build/sim/core/veril.cpp modules.o pads.o sim.o libdylib.o parse.o \
	--top-module sim \
	 \
	-CFLAGS "-ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core" \
	-LDFLAGS "-lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent " \
	--trace \
	 \
	 \
	 \
	--unroll-count 256 \
	--output-split 5000 \
	--output-split-cfuncs 500 \
	--output-split-ctrace 500 \
	 \
	-Wno-BLKANDNBLK \
	-Wno-WIDTH \
	-Wno-COMBDLY \
	-Wno-CASEINCOMPLETE \
	 \
	--relative-includes 
%Warning-TIMESCALEMOD: /home/manili/LiteX/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/Ram_1w_1rs_Generic.v:2:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
    2 | module Ram_1w_1rs #(
      |        ^~~~~~~~~~
                       /home/manili/LiteX/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1.v:8:8: ... Location of module with timescale
    8 | module VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1 (
      |        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                       ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.039
                       ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message.
- V e r i l a t i o n   R e p o r t: Verilator 5.039 devel rev v5.038-111-gd0f091983
- Verilator: Built from 2.483 MB sources in 33 modules, into 4.897 MB in 42 C++ files needing 0.001 MB
- Verilator: Walltime 1.622 s (elab=0.149, cvt=1.036, bld=0.000); cpu 1.540 s on 1 threads; alloced 83.379 MB
make -j -C /home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir -f Vsim.mk Vsim
make[1]: Entering directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir'
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ccache g++ -Os  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -c -o verilated_dpi.o /usr/local/share/verilator/include/verilated_dpi.cpp
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ccache g++ -Os  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -x c++-header Vsim__pch.h -o Vsim__pch.h.fast.gch
ccache g++   -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -x c++-header Vsim__pch.h -o Vsim__pch.h.slow.gch
echo "" > Vsim__ALL.verilator_deplist.tmp
/home/manili/LiteX/litex/litex/build/sim/core/veril.cpp: In function ‘int litex_sim_got_finish()’:
/home/manili/LiteX/litex/litex/build/sim/core/veril.cpp:129:15: warning: suggest parentheses around assignment used as truth value [-Wparentheses]
  129 |   if(finished = Verilated::gotFinish()) {
      |      ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
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ccache g++   -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1__DepSet_he3a756d5__0__Slow.o Vsim_VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_ITs4DTs4_Ldw32_Ood_Hb1__DepSet_he3a756d5__0__Slow.cpp
ccache g++   -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__Slow.cpp
ccache g++   -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.cpp
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ccache g++ -Os  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_VexRiscv__DepSet_h9f7c89a9__1.o Vsim_VexRiscv__DepSet_h9f7c89a9__1.cpp
ccache g++ -Os  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Dpi.o Vsim__Dpi.cpp
ccache g++ -Os  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Trace__0.o Vsim__Trace__0.cpp
ccache g++ -Os  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Trace__1.o Vsim__Trace__1.cpp
ccache g++ -Os  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3    -I/home/manili/LiteX/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Trace__2.o Vsim__Trace__2.cpp
g++    veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o verilated_threads.o Vsim__ALL.a   modules.o pads.o sim.o libdylib.o parse.o -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent  -pthread -lpthread -latomic   -o Vsim
rm Vsim__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware/obj_dir'
make: Leaving directory '/home/manili/LiteX/linux-on-litex-vexriscv/build/sim/gateware'

[serial2tcp] loaded (0x5557944b8ef0)
[serial2console] loaded (0x5557944b8ef0)
[clocker] loaded
[jtagremote] loaded (0x5557944b8ef0)
[ethernet] loaded (0x5557944b8ef0)
[xgmii_ethernet] loaded (0x5557944b8ef0)
[spdeeprom] loaded (addr = 0x0)
[gmii_ethernet] loaded (0x5557944b8ef0)
MDEBUG: Save time: -1, load_time: 0
[clocker] sys_clk: freq_hz=1000000, phase_deg=0

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2025 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Aug  1 2025 07:21:45
 BIOS CRC passed (3a4f7cae)

 LiteX git sha1: 6153651d5

--=============== SoC ==================--
CPU:		VexRiscv SMP-LINUX @ 100MHz
BUS:		wishbone 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64.0KiB
SRAM:		8.0KiB
SDRAM:		64.0MiB 32-bit @ 100MT/s (CL-2 CWL-2)
MAIN-RAM:	64.0MiB

--========== Initialization ============--

Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Executing booted program at 0x40f00000

--============= Liftoff! ===============--

OpenSBI v1.3
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name             : LiteX / VexRiscv-SMP
Platform Features         : medeleg
Platform HART Count       : 8
Platform IPI Device       : aclint-mswi
Platform Timer Device     : aclint-mtimer @ 100000000Hz
Platform Console Device   : litex_uart
Platform HSM Device       : ---
Platform PMU Device       : ---
Platform Reboot Device    : ---
Platform Shutdown Device  : ---
Platform Suspend Device   : ---
Platform CPPC Device      : ---
Firmware Base             : 0x40f00000
Firmware Size             : 376 KB
Firmware RW Offset        : 0x40000
Firmware RW Size          : 120 KB
Firmware Heap Offset      : 0x52000
Firmware Heap Size        : 48 KB (total), 3 KB (reserved), 8 KB (used), 36 KB (free)
Firmware Scratch Size     : 4096 B (total), 452 B (used), 3644 B (free)
Runtime SBI Version       : 1.0

Domain0 Name              : root
Domain0 Boot HART         : 0
Domain0 HARTs             : 0*,1*,2*,3*,4*,5*,6*,7*
Domain0 Region00          : 0xf0018000-0xf001bfff M: (I,R,W) S/U: ()
Domain0 Region01          : 0xf0010000-0xf0017fff M: (I,R,W) S/U: ()
Domain0 Region02          : 0x40f40000-0x40f5ffff M: (R,W) S/U: ()
Domain0 Region03          : 0x40f00000-0x40f3ffff M: (R,X) S/U: ()
Domain0 Region04          : 0x00000000-0xffffffff M: (R,W,X) S/U: (R,W,X)
Domain0 Next Address      : 0x40000000
Domain0 Next Arg1         : 0x40ef0000
Domain0 Next Mode         : S-mode
Domain0 SysReset          : yes
Domain0 SysSuspend        : yes

Boot HART ID              : 0
Boot HART Domain          : root
Boot HART Priv Version    : unknown
Boot HART Base ISA        : rv32ima
Boot HART ISA Extensions  : zicntr
Boot HART PMP Count       : 0
Boot HART PMP Granularity : 0
Boot HART PMP Address Bits: 0
Boot HART MHPM Count      : 0
Boot HART MIDELEG         : 0x00000222
Boot HART MEDELEG         : 0x0000b109
[    0.000000] Linux version 6.9.0 (manili@ubuntu) (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.05-626-gf5101638b9) 13.4.0, GNU ld (GNU Binutils) 2.43.1) #1 SMP Thu Jul 31 23:39:21 EDT 2025
[    0.000000] Machine model: sim
[    0.000000] SBI specification v1.0 detected
[    0.000000] SBI implementation ID=0x1 Version=0x10003
[    0.000000] SBI TIME extension detected
[    0.000000] SBI IPI extension detected
[    0.000000] SBI RFENCE extension detected
[    0.000000] earlycon: liteuart0 at I/O port 0x0 (options '')
[    0.000000] Malformed early option 'console'
[    0.000000] earlycon: liteuart0 at MMIO 0xf0001000 (options '')
[    0.000000] printk: legacy bootconsole [liteuart0] enabled
[    0.000000] OF: reserved mem: OVERLAP DETECTED!
[    0.000000] mmode_resv1@40f00000 (0x40f00000--0x40f40000) overlaps with opensbi@40f00000 (0x40f00000--0x40f80000)
[    0.000000] OF: reserved mem: OVERLAP DETECTED!
[    0.000000] opensbi@40f00000 (0x40f00000--0x40f80000) overlaps with mmode_resv0@40f40000 (0x40f40000--0x40f60000)
[    0.000000] OF: reserved mem: 0x40f00000..0x40f3ffff (256 KiB) nomap non-reusable mmode_resv1@40f00000
[    0.000000] OF: reserved mem: 0x40f00000..0x40f7ffff (512 KiB) map non-reusable opensbi@40f00000
[    0.000000] OF: reserved mem: 0x40f40000..0x40f5ffff (128 KiB) nomap non-reusable mmode_resv0@40f40000
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000040000000-0x0000000043ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000040000000-0x0000000040efffff]
[    0.000000]   node   0: [mem 0x0000000040f00000-0x0000000040f5ffff]
[    0.000000]   node   0: [mem 0x0000000040f60000-0x0000000043ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x0000000043ffffff]
[    0.000000] SBI HSM extension detected
[    0.000000] riscv: base ISA extensions aim
[    0.000000] riscv: ELF capabilities aim
[    0.000000] percpu: Embedded 11 pages/cpu s22932 r0 d22124 u45056
[    0.000000] Kernel command line: console=liteuart earlycon=liteuart,0xf0001000 rootwait root=/dev/ram0
[    0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
[    0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes, linear)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 16256
[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[    0.000000] Memory: 47336K/65536K available (6676K kernel code, 579K rwdata, 1040K rodata, 258K init, 249K bss, 18200K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=32 to nr_cpu_ids=1.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] riscv-intc: 32 local interrupts mapped
[    0.000000] riscv: providing IPIs using SBI IPI extension
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
[    0.000023] sched_clock: 64 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns
[    0.003141] Console: colour dummy device 80x25
[    0.004194] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=1000000)
[    0.005144] pid_max: default: 32768 minimum: 301
[    0.009349] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.010144] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.051301] ASID allocator using 9 bits (512 entries)
[    0.056200] rcu: Hierarchical SRCU implementation.
[    0.056711] rcu: 	Max phase no-delay instances is 1000.
[    0.073995] smp: Bringing up secondary CPUs ...
[    0.074719] smp: Brought up 1 node, 1 CPU
[    0.085264] devtmpfs: initialized
[    0.128671] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.129584] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
[    0.166351] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.178151] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
[    0.311454] cpu0: Ratio of byte access time to unaligned word access is 0.00, unaligned accesses are slow
[    0.325618] platform soc: Fixed dependency cycle(s) with /soc/interrupt-controller@f0c00000
[    0.335189] platform soc: Fixed dependency cycle(s) with /soc/interrupt-controller@f0c00000
[    0.373521] pps_core: LinuxPPS API ver. 1 registered
[    0.374087] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.375173] PTP clock support registered
[    0.380736] FPGA manager framework
[    0.400950] clocksource: Switched to clocksource riscv_clocksource
[    0.726609] NET: Registered PF_INET protocol family
[    0.731938] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
[    0.744362] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
[    0.745294] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.746173] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.747170] TCP bind hash table entries: 1024 (order: 2, 16384 bytes, linear)
[    0.748213] TCP: Hash tables configured (established 1024 bind 1024)
[    0.749768] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
[    0.751311] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
[    0.778676] Unpacking initramfs...
[    0.802172] workingset: timestamp_bits=30 max_order=14 bucket_order=0
[    0.811622] io scheduler mq-deadline registered
[    0.812196] io scheduler kyber registered
[    0.813140] io scheduler bfq registered
[    0.841844] riscv-plic f0c00000.interrupt-controller: mapped 32 interrupts with 1 handlers for 2 contexts.
[    0.858129] LiteX SoC Controller driver initialized
[    4.677092] Freeing initrd memory: 8192K
[    5.896556] f0001000.serial: ttyLXU0 at MMIO 0x0 (irq = 12, base_baud = 0) is a liteuart
[    5.897833] printk: legacy console [liteuart0] enabled
[    5.897833] printk: legacy console [liteuart0] enabled
[    5.898794] printk: legacy bootconsole [liteuart0] disabled
[    5.898794] printk: legacy bootconsole [liteuart0] disabled
[    5.932180] i2c_dev: i2c /dev entries driver
[    5.963077] NET: Registered PF_INET6 protocol family
[    5.987925] Segment Routing with IPv6
[    5.990311] In-situ OAM (IOAM) with IPv6
[    5.992908] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    6.011104] NET: Registered PF_PACKET protocol family
[    6.411744] clk: Disabling unused clocks
[    6.424297] Freeing unused kernel image (initmem) memory: 252K
[    6.424924] Kernel memory protection not selected by kernel config.
[    6.425654] Run /init as init process

[n1kl0s]

I have the same problem with Linux getting stuck in the init process

[Dolu1990]

Continuation on #432