Vivado build error: combinational loop in 7-Series bitstreams

[fischermoseley]

Thank you for this fantastic project! Despite the issue described below I was able to get Linux booted on a different FPGA board I had (an Arty S7) and that's been super fun to play with. Much appreciated!

With a fresh checkout of LiteX and Vivado 2025.1 on Ubuntu 24.04, I'm unable to build designs for 7-Series boards as Vivado finds a combinatorial loop in what appears to be the DRAM controller. If I run ./make.py --board=nexys4ddr --cpu-count=1 --build then the RTL will successfully generate, but bitstream generation fails with:

INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 5 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is ODDR_22_i_2_n_0. Please evaluate your design. The cells in the loop are: ODDR_22_i_2, ODDR_22_i_3, ODDR_22_i_7, soclinux_dataw_crc16_crc10[12]_i_1, and soclinux_dataw_crc16_crc10[12]_i_2.

There's a few more similar errors after this, full build log at this gist. I've also tried this with the nexys_video and arty_a7 targets and obtained the same error.

I've filed this under the linux-on-litex-vexriscv project for now, forgive me if I should have filed under the LiteDRAM project!