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pcbarts_klusterlab: add target and platform file
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‎litex_boards/platforms/pcbarts_klusterlab.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk66", 0, Pins("B26"), IOStandard("LVCMOS18")),
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("clk200", 0,
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Subsignal("p", Pins("AC9"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("AD9"), IOStandard("DIFF_SSTL15"))
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),
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("clk_si", 0,
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Subsignal("p", Pins("K6"), IOStandard("DIFF_HSTL_I_10")),
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Subsignal("n", Pins("K5"), IOStandard("DIFF_HSTL_I_10"))
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),
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("clk_sata_150", 0,
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Subsignal("p", Pins("F6"), IOStandard("DIFF_HSTL_I_10")),
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Subsignal("n", Pins("F5"), IOStandard("DIFF_HSTL_I_10"))
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),
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("clk_net_156", 0,
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Subsignal("p", Pins("H6"), IOStandard("DIFF_HSTL_I_10")),
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Subsignal("n", Pins("H5"), IOStandard("DIFF_HSTL_I_10"))
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),
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("cpu_reset_n", 0, Pins("A20"), IOStandard("LVCMOS18")),
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("pi_reset_n", 0, Pins("A18"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("F23"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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("user_led", 1, Pins("J26"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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("user_led", 2, Pins("G26"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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("user_led", 3, Pins("H26"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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("user_led", 4, Pins("G25"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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("user_led", 5, Pins("F24"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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("user_led", 6, Pins("F25"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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("user_led", 7, Pins("G24"), IOStandard("LVCMOS18"), Misc("SLEW=SLOW")),
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# Buttons
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("user_btn", 0, Pins("J24"), IOStandard("LVCMOS18")),
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("user_btn", 1, Pins("H22"), IOStandard("LVCMOS18")),
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("user_btn", 2, Pins("H23"), IOStandard("LVCMOS18")),
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("user_btn", 3, Pins("H24"), IOStandard("LVCMOS18")),
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("user_btn", 4, Pins("G22"), IOStandard("LVCMOS18")),
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# Switches
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("user_sw", 0, Pins("E25"), IOStandard("LVCMOS18")),
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("user_sw", 1, Pins("E26"), IOStandard("LVCMOS18")),
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("user_sw", 2, Pins("D25"), IOStandard("LVCMOS18")),
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("user_sw", 3, Pins("F22"), IOStandard("LVCMOS18")),
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("user_sw", 4, Pins("D24"), IOStandard("LVCMOS18")),
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("user_sw", 5, Pins("D23"), IOStandard("LVCMOS18")),
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("user_sw", 6, Pins("E23"), IOStandard("LVCMOS18")),
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("user_sw", 7, Pins("E22"), IOStandard("LVCMOS18")),
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("user_sw", 8, Pins("J25"), IOStandard("LVCMOS18")),
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# Testpoints
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("tp", 0, Pins("M17"), IOStandard("LVCMOS33")),
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("tp", 1, Pins("L18"), IOStandard("LVCMOS33")),
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("tp", 2, Pins("L17"), IOStandard("LVCMOS33")),
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("tp", 3, Pins("K18"), IOStandard("LVCMOS33")),
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# Fan control
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("fan", 0,
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Subsignal("tach", Pins("B19")),
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Subsignal("pwm", Pins("C17")),
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Subsignal("sys", Pins("C19")),
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IOStandard("LVCMOS33")),
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# The Serial which connects to the second UART
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# of the FTDI on the base board (first FTDI port is JTAG)
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("serial", 0,
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Subsignal("tx", Pins("A17")),
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Subsignal("rx", Pins("K15")),
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Subsignal("rts", Pins("B17")),
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Subsignal("cts", Pins("F18")),
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IOStandard("LVCMOS15")
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),
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# I2C
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("i2c_mxrst_n", Pins("W21"), IOStandard("LVCMOS18")),
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# IO
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("i2c", 0,
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Subsignal("scl", Pins("V21")),
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Subsignal("sda", Pins("AE22")),
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IOStandard("LVCMOS18"),
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),
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# temperature
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("i2c", 1,
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Subsignal("scl", Pins("AE26")),
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Subsignal("sda", Pins("AD26")),
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IOStandard("LVCMOS18"),
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),
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("si5324", 0,
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Subsignal("int", Pins("V22")),
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Subsignal("rst", Pins("V24")),
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IOStandard("LVCMOS18"),
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),
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("smi", 0,
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Subsignal("sa", Pins("AB26 V26 U24 U26 AB25 V23"), IOStandard("LVCMOS33")),
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Subsignal("sd", Pins("W24 Y26 Y25 AA25 U22 AC26 U25 AB24"
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"Y22 W25 Y23 AC23 Y21 W20 W26 AA23"
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"AA24 AA22"), IOStandard("LVCMOS33")),
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Subsignal("soe_n", Pins("AC24"), IOStandard("LVCMOS33")),
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Subsignal("swe_n", Pins("W23"), IOStandard("LVCMOS33")),
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),
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# SD Card
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("sdcard", 0,
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Subsignal("data", Pins("AD24 AC21 AD23 AB21"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("AB22"), Misc("PULLUP True")),
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Subsignal("clk", Pins("AD21")),
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Subsignal("cd", Pins("AC22")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS18"),
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),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("B16"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("D6")),
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Subsignal("clk_n", Pins("D5")),
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Subsignal("rx_p", Pins("B6")),
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Subsignal("rx_n", Pins("B5")),
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Subsignal("tx_p", Pins("A4")),
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Subsignal("tx_n", Pins("A3"))
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),
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("sata", 0,
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Subsignal("rx_p", Pins("C4")),
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Subsignal("rx_n", Pins("C3")),
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Subsignal("tx_p", Pins("B2")),
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Subsignal("tx_n", Pins("B1")),
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AF7 AD8 AB10 AC8 W11 AA12 AC12 AD13",
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"AB12 AD11 AE7 Y11 AA13 AB7 Y13 Y12"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AC7 V8 AC13"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AA10"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AA7"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("Y8 V7"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"AC19 V17 AF17 AA14 AC4 AF2 U7 Y1"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AB17 AC18 AC17 AD19 AA19 AA20 AD18 AC16",
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"V16 V18 AB20 AB19 W15 V19 W16 Y17",
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"AF19 AE17 AE15 AF15 AF20 AD16 AD15 AF14",
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"AA15 AB16 AD14 AB14 AA18 AA17 AB15 AC14",
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"AD6 AC6 AC3 AB4 AB6 Y6 Y5 AA4",
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"AF3 AE3 AE2 AE1 AE6 AE5 AD4 AD1",
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"W3 V4 U2 U5 V6 V3 U1 U6",
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"AB2 AA3 W1 V2 AC2 Y3 Y2 V1 "),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AD20 W18 AE18 Y15 AA5 AF5 W6 AB1"),
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IOStandard("DIFF_SSTL15_T_DCI")),
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Subsignal("dqs_n", Pins("AE20 W19 AF18 Y16 AB5 AF4 W5 AC1"),
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IOStandard("DIFF_SSTL15_T_DCI")),
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Subsignal("clk_p", Pins("AB11 AA9"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AC11 AB9"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("Y10 W9"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AA8 V9"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("V11"), IOStandard("SSTL15"), Misc("SLEW=SLOW")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH"),
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),
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# HDMI In
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("hdmi_in", 0,
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Subsignal("clk_p", Pins("M24"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("L24"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("P24"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("N24"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("R26"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("P26"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("R25"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("P25"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("P23"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("M21"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("M22"), IOStandard("LVCMOS25")),
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Subsignal("cec", Pins("N23"), IOStandard("LVCMOS33")),
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# Subsignal("txen", Pins(""), IOStandard("LVCMOS33")),
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),
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# HDMI Out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("N19"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("M20"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("P19"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("P20"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("K25"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("K26"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("M25"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("L25"), IOStandard("TMDS_33")),
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# Subsignal("scl", Pins(""), IOStandard("LVCMOS33")),
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# Subsignal("sda", Pins(""), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("N26"), IOStandard("LVCMOS33")),
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Subsignal("hdp", Pins("M26"), IOStandard("LVCMOS25")),
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),
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# SFP0
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("sfp_tx", 0,
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Subsignal("p", Pins("P2")),
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Subsignal("n", Pins("P1"))
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),
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("sfp_rx", 0,
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Subsignal("p", Pins("R4")),
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Subsignal("n", Pins("R3"))
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),
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("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 0, Pins("T19"), IOStandard("LVCMOS33")),
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("sfp_link", 0, Pins("T24"), IOStandard("LVCMOS33")),
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("sfp_act", 0, Pins("T25"), IOStandard("LVCMOS33")),
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# SFP1
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("sfp_tx", 1,
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Subsignal("p", Pins("M2")),
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Subsignal("n", Pins("M1")),
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),
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("sfp_rx", 1,
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Subsignal("p", Pins("N4")),
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Subsignal("n", Pins("N3")),
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),
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("sfp_tx_disable_n", 1, Pins("N18"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 1, Pins("M19"), IOStandard("LVCMOS33")),
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("sfp_link", 1, Pins("T22"), IOStandard("LVCMOS33")),
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("sfp_act", 1, Pins("R23"), IOStandard("LVCMOS33")),
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# SFP2
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("sfp_tx", 2,
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Subsignal("p", Pins("K2")),
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Subsignal("n", Pins("K1")),
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),
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("sfp_rx", 2,
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Subsignal("p", Pins("L4")),
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Subsignal("n", Pins("L3")),
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),
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("sfp_tx_disable_n", 2, Pins("N17"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 2, Pins("R17"), IOStandard("LVCMOS33")),
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("sfp_link", 2, Pins("N22"), IOStandard("LVCMOS33")),
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("sfp_act", 2, Pins("N21"), IOStandard("LVCMOS33")),
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# SFP3
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("sfp_tx", 3,
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Subsignal("p", Pins("H2")),
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Subsignal("n", Pins("H1")),
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),
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("sfp_rx", 3,
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Subsignal("p", Pins("J4")),
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Subsignal("n", Pins("J3")),
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),
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("sfp_tx_disable_n", 3, Pins("P16"), IOStandard("LVCMOS33")),
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("sfp_rx_los", 3, Pins("R16"), IOStandard("LVCMOS33")),
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("sfp_link", 3, Pins("R20"), IOStandard("LVCMOS33")),
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("sfp_act", 3, Pins("R22"), IOStandard("LVCMOS33")),
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]
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_connectors = [
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("cruvi_a", {
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"0_p" : "F14",
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"0_n" : "F13",
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"1_p" : "A13",
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"1_n" : "A12",
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"2_p" : "D9",
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"2_n" : "D8",
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"3_p" : "C9",
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"3_n" : "B9",
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"4_p" : "B10",
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"4_n" : "A10",
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"5_p" : "B12",
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"5_n" : "B11",
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"6_p" : "C12",
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"6_n" : "C11",
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"7_p" : "B14",
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"7_n" : "A14",
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"8_p" : "B15",
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"8_n" : "A15",
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"9_p" : "C14",
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"9_n" : "C13",
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"10_p" : "H14",
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"10_n" : "G14",
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"11_p" : "D14",
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"11_n" : "D13",
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"di" : "G19",
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"do" : "D20",
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"hsi" : "F17",
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"hso" : "H17",
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"hsio" : "H18",
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"mode" : "F20",
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"refclk" : "E17",
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"reset" : "H16",
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"sck" : "G20",
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"sel" : "E20",
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"smb_alert" : "H19",
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"smb_scl" : "G17",
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"smb_sda" : "F19",
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}),
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("cruvi_b", {
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"0_p" : "J10",
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"0_n" : "J11",
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"1_p" : "H8",
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"1_n" : "H9",
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"2_p" : "G9",
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"2_n" : "G10",
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"3_p" : "F8",
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"3_n" : "F9",
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"4_p" : "F10",
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"4_n" : "G11",
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"5_p" : "D10",
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"5_n" : "E10",
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"6_p" : "A8",
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"6_n" : "A9",
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"7_p" : "D11",
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"7_n" : "E11",
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"8_p" : "F12",
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"8_n" : "G12",
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"9_p" : "E12",
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"9_n" : "E13",
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"10_p" : "H11",
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"10_n" : "H12",
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"11_p" : "H13",
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"11_n" : "J13",
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"di" : "J15",
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"do" : "C18",
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"hsi" : "G16",
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"hso" : "D16",
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"hsio" : "F15",
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"mode" : "E18",
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"refclk" : "E16",
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"reset" : "D15",
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"sck" : "D19",
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"sel" : "D18",
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"smb_alert" : "G15",
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"smb_scl" : "E15",
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"smb_sda" : "J16",
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}),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7k160tffg676-2", _io, _connectors, toolchain=toolchain)
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self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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self.add_platform_command("set_property CFGBVS GND [current_design]")
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# DDR3 is connected to banks 32, 33 and 34
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 32]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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# The VRP/VRN resistors are connected to bank 34.
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# Banks 32 and 33 have LEDs in the places, so we have to use the reference from bank 34
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# Bank 33 has no _T_DCI signals connected
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self.add_platform_command("set_property DCI_CASCADE {{32}} [get_iobanks 34]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]")
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# Important! Do not remove this constraint!
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# This property ensures that all unused pins are set to high impedance.
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# If the constraint is removed, all unused pins have to be set to HiZ in the top level file
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# This causes DDR3 to use 1.5V by default
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]")
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def add_baseboard(self, bb):
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self.add_connector(bb.connectors)
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self.add_extension(bb.io)
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)

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