diff --git a/litex_boards/platforms/ypcb_00338_1p1.py b/litex_boards/platforms/ypcb_00338_1p1.py
index c0ac7e182..5646fb545 100644
--- a/litex_boards/platforms/ypcb_00338_1p1.py
+++ b/litex_boards/platforms/ypcb_00338_1p1.py
@@ -27,6 +27,14 @@
     # Clk / Rst.
     ("clk50", 0, Pins("AA28"), IOStandard("LVCMOS18")),
     ("rst_n", 0, Pins("R28"),  IOStandard("LVCMOS18")),
+    ("clk200", 0,
+        Subsignal("p", Pins("AH27"), IOStandard("LVDS_25")),
+        Subsignal("n", Pins("AH28"), IOStandard("LVDS_25")),
+    ),
+    ("clk200_1", 0,
+        Subsignal("p", Pins("G25"), IOStandard("LVDS_25")),
+        Subsignal("n", Pins("G26"), IOStandard("LVDS_25")),
+    ),
 
     # Leds.
     ("user_led", 0, Pins("P30"), IOStandard("LVCMOS18")), # Red.
@@ -182,8 +190,8 @@
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(Xilinx7SeriesPlatform):
-    default_clk_name   = "clk50"
-    default_clk_period = 1e9/50e6
+    default_clk_name   = "clk200"
+    default_clk_period = 1e9/200e6
 
     def __init__(self, toolchain="vivado"):
         device = "xc7k480t-ffg1156-2"
diff --git a/litex_boards/targets/ypcb_00338_1p1.py b/litex_boards/targets/ypcb_00338_1p1.py
index 9b51ab892..479bd2c1c 100755
--- a/litex_boards/targets/ypcb_00338_1p1.py
+++ b/litex_boards/targets/ypcb_00338_1p1.py
@@ -39,13 +39,13 @@ def __init__(self, platform, sys_clk_freq):
         self.cd_idelay = ClockDomain()
 
         # Clk/Rst.
-        clk50 = platform.request("clk50")
+        clk200 = platform.request("clk200")
         rst_n = platform.request("rst_n")
 
         # PLL.
         self.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(~rst_n | self.rst)
-        pll.register_clkin(clk50, 50e6)
+        pll.register_clkin(clk200, 200e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=135)
@@ -107,6 +107,7 @@ def __init__(self, sys_clk_freq=125e6,
             platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y17 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[6].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
             platform.toolchain.pre_placement_commands.append("set_property LOC GTXE2_CHANNEL_X0Y16 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*pipe_lane[7].gt_wrapper_i/gtx_channel.gtxe2_channel_i}}]")
 
+
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(platform.request_all("user_led"), sys_clk_freq)
@@ -122,8 +123,8 @@ def main():
     args = parser.parse_args()
 
     soc = BaseSoC(
-        sys_clk_freq = args.sys_clk_freq,
-        with_pcie    = args.with_pcie,
+        sys_clk_freq   = args.sys_clk_freq,
+        with_pcie      = args.with_pcie,
         **parser.soc_argdict
     )
     builder = Builder(soc, **parser.builder_argdict)