Merge from x86-smp: implement SMP for both 32 and 64bit x86

A large pile of changes to the PC platform and x86 architecture that
facilitate SMP support. Tested in both 64 and 32bit on qemu and real
hardware all the way back through i486.

Author: travisg

.clang-tidy

@@ -3,6 +3,7 @@ Checks: >
   -*,
   bugprone-*,
   -bugprone-easily-swappable-parameters,
+  -bugprone-reserved-identifier,
 
   clang-diagnostic-*,
   -clang-diagnostic-unused-command-line-argument,
@@ -38,6 +39,7 @@ Checks: >
   -readability-implicit-bool-conversion,
   -readability-isolate-declaration,
   -readability-magic-numbers,
+  -readability-math-missing-parentheses,
   -readability-named-parameter,
   -readability-qualified-auto,
   -readability-uppercase-literal-suffix,

arch/arm64/mmu.c

@@ -34,7 +34,7 @@ __SECTION(".bss.prebss.translation_table");
 /* the base TCR flags, computed from early init code in start.S */
 uint64_t arm64_mmu_tcr_flags __SECTION(".bss.prebss.tcr_flags");
 
-static inline bool is_valid_vaddr(arch_aspace_t *aspace, vaddr_t vaddr) {
+static inline bool is_valid_vaddr(const arch_aspace_t *aspace, vaddr_t vaddr) {
     return (vaddr >= aspace->base && vaddr <= aspace->base + aspace->size - 1);
 }
 

arch/test/mmu.cpp

@@ -15,7 +15,9 @@
 #include <lib/unittest.h>
 #include <kernel/vm.h>
 
-static bool create_user_aspace(void) {
+namespace {
+
+bool create_user_aspace() {
     BEGIN_TEST;
 
     if (arch_mmu_supports_user_aspaces()) {
@@ -34,7 +36,7 @@ static bool create_user_aspace(void) {
     END_TEST;
 }
 
-static bool map_user_pages(void) {
+bool map_user_pages() {
     BEGIN_TEST;
 
     if (arch_mmu_supports_user_aspaces()) {
@@ -89,7 +91,7 @@ static bool map_user_pages(void) {
     END_TEST;
 }
 
-static bool map_region_query_result(vmm_aspace_t *aspace, uint arch_flags) {
+bool map_region_query_result(vmm_aspace_t *aspace, uint arch_flags) {
     BEGIN_TEST;
     void *ptr = NULL;
 
@@ -109,10 +111,17 @@ static bool map_region_query_result(vmm_aspace_t *aspace, uint arch_flags) {
     // free this region we made
     EXPECT_EQ(NO_ERROR, vmm_free_region(aspace, (vaddr_t)ptr), "free region");
 
+    // query that the page is not there anymore
+    {
+        paddr_t pa = 0;
+        uint flags = ~arch_flags;
+        EXPECT_EQ(ERR_NOT_FOUND, arch_mmu_query(&aspace->arch_aspace, (vaddr_t)ptr, &pa, &flags), "arch_query");
+    }
+
     END_TEST;
 }
 
-static bool map_region_expect_failure(vmm_aspace_t *aspace, uint arch_flags, int expected_error) {
+bool map_region_expect_failure(vmm_aspace_t *aspace, uint arch_flags, int expected_error) {
     BEGIN_TEST;
     void *ptr = NULL;
 
@@ -123,7 +132,7 @@ static bool map_region_expect_failure(vmm_aspace_t *aspace, uint arch_flags, int
     END_TEST;
 }
 
-static bool map_query_pages(void) {
+bool map_query_pages() {
     BEGIN_TEST;
 
     vmm_aspace_t *kaspace = vmm_get_kernel_aspace();
@@ -153,9 +162,12 @@ static bool map_query_pages(void) {
     END_TEST;
 }
 
-static bool context_switch(void) {
+bool context_switch() {
     BEGIN_TEST;
 
+    // create a user space, map a page or two and access it
+    // NOTE: this assumes that kernel code can directly access user space, which isn't necessarily true
+    // on all architectures. See SMAP on x86, PAN on ARM, and SUM on RISC-V.
     if (arch_mmu_supports_user_aspaces()) {
         arch_aspace_t as;
         status_t err = arch_mmu_init_aspace(&as, USER_ASPACE_BASE, USER_ASPACE_SIZE, 0);
@@ -218,4 +230,6 @@ RUN_TEST(map_query_pages);
 RUN_TEST(context_switch);
 END_TEST_CASE(arch_mmu_tests)
 
+} // namespace
+
 #endif // ARCH_HAS_MMU

arch/x86/32/exceptions.S

@@ -45,7 +45,8 @@ LOCAL_FUNCTION(interrupt_common)
     pushl %ds
     pusha                   /* save general purpose registers */
     movl $DATA_SELECTOR, %eax /* put known good value in segment registers */
-    movl %eax, %gs
+    // do not reset %gs, as it is used by the kernel
+    // TODO: when dealing with user space, we need to reset %gs here
     movl %eax, %fs
     movl %eax, %es
     movl %eax, %ds
@@ -61,8 +62,7 @@ LOCAL_FUNCTION(interrupt_common)
     popl %ds                /* restore segment registers */
     popl %es
     popl %fs
-    popl %gs
-    addl $8, %esp           /* drop exception number and error code */
+    addl $12, %esp          /* drop gs, exception number, and error code */
     iret
 END_FUNCTION(interrupt_common)
 
@@ -83,8 +83,6 @@ FUNCTION(setup_idt)
 
     loop .Lloop
 
-    lidt _idtr
-
     ret
 END_FUNCTION(setup_idt)
 

arch/x86/32/gdt.S

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2009 Corey Tabaka
+ * Copyright (c) 2015 Intel Corporation
+ * Copyright (c) 2016 Travis Geiselbrecht
+ *
+ * Use of this source code is governed by a MIT-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/MIT
+ */
+#include <lk/asm.h>
+#include <arch/x86/descriptor.h>
+
+#define PHYS_LOAD_ADDRESS (MEMBASE + KERNEL_LOAD_OFFSET)
+#define PHYS_ADDR_DELTA (KERNEL_BASE + KERNEL_LOAD_OFFSET - PHYS_LOAD_ADDRESS)
+#define PHYS(x) ((x) - PHYS_ADDR_DELTA)
+
+.section .rodata
+
+.balign 8
+DATA(_gdtr_phys)
+    .short _gdt_end - _gdt - 1
+    .int PHYS(_gdt)
+END_DATA(_gdtr_phys)
+
+.balign 8
+DATA(_gdtr)
+    .short _gdt_end - _gdt - 1
+    .int _gdt
+END_DATA(_gdtr)
+
+
+// 32bit GDT, laid out in a specific way due to requirements by the SYSENTER/SYSEXIT and
+// SYSCALL/SYSRET instructions:
+//
+// CODE32   <- IA32_SYSENTER_CS, IA32_STAR.SYSCALL_CS
+// DATA
+// UCODE32  <- IA32_STAR.SYSRET_CS
+// UDATA
+.data
+.balign 8
+DATA(_gdt)
+    .int 0
+    .int 0
+
+/* ring 0 code 32bit (for bootstrapping into 64bit) */
+    .short 0xffff           /* limit 15:00 */
+    .short 0x0000           /* base 15:00 */
+    .byte  0x00             /* base 23:16 */
+    .byte  0b10011010       /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
+    .byte  0b11001111       /* G(1) D(1) 0 0 limit 19:16 */
+    .byte  0x0              /* base 31:24 */
+
+/* ring 0 data 32bit */
+    .short 0xffff           /* limit 15:00 */
+    .short 0x0000           /* base 15:00 */
+    .byte  0x00             /* base 23:16 */
+    .byte  0b10010010       /* P(1) DPL(00) S(1) 0 E(0) W(1) A(0) */
+    .byte  0b11001111       /* G(1) B(1) 0 0 limit 19:16 */
+    .byte  0x0              /* base 31:24 */
+
+/* ring 3 code 32bit */
+    .short 0xffff           /* limit 15:00 */
+    .short 0x0000           /* base 15:00 */
+    .byte  0x00             /* base 23:16 */
+    .byte  0b11111010       /* P(1) DPL(11) S(1) 1 C(0) R(1) A(0) */
+    .byte  0b11001111       /* G(1) D(1) 0 0 limit 19:16 */
+    .byte  0x0              /* base 31:24 */
+
+/* ring 3 data 32bit */
+    .short 0xffff           /* limit 15:00 */
+    .short 0x0000           /* base 15:00 */
+    .byte  0x00             /* base 23:16 */
+    .byte  0b11110010       /* P(1) DPL(11) S(1) 0 E(0) W(1) A(0) */
+    .byte  0b11001111       /* G(1) B(1) 0 0 limit 19:16 */
+    .byte  0x0              /* base 31:24 */
+
+/* per-cpu TSS descriptor */
+.set i, 1
+.rept SMP_MAX_CPUS
+    .short 0                /* limit 15:00 */
+    .short 0                /* base 15:00 */
+    .byte  0                /* base 23:16 */
+    .byte  0x89             /* P(1) DPL(00) S(0) TYPE(9) */
+    .byte  0x80             /* G(1) D/B(0) L(0) AVL(0) limit 19:16 */
+    .byte  0                /* base 31:24 */
+.set i, i+1
+.endr
+
+/* per-cpu GS descriptor for x86-32 */
+.set i, 1
+.rept SMP_MAX_CPUS
+    .int   0               /* filled in by C code later */
+    .int   0
+.set i, i+1
+.endr
+
+END_DATA(_gdt)
+
+DATA(_gdt_end)
+