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[Hexagon] Use MCRegister. NFC
1 parent af629ec commit 6b81357

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9 files changed

+85
-81
lines changed

9 files changed

+85
-81
lines changed

‎llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Lines changed: 24 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
124124

125125
bool parseDirectiveAttribute(SMLoc L);
126126

127-
bool RegisterMatchesArch(unsigned MatchNum) const;
127+
bool RegisterMatchesArch(MCRegister MatchNum) const;
128128

129129
bool matchBundleOptions();
130130
bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
@@ -145,10 +145,10 @@ class HexagonAsmParser : public MCTargetAsmParser {
145145
int processInstruction(MCInst &Inst, OperandVector const &Operands,
146146
SMLoc IDLoc);
147147

148-
unsigned matchRegister(StringRef Name);
148+
MCRegister matchRegister(StringRef Name);
149149

150-
/// @name Auto-generated Match Functions
151-
/// {
150+
/// @name Auto-generated Match Functions
151+
/// {
152152

153153
#define GET_ASSEMBLER_HEADER
154154
#include "HexagonGenAsmMatcher.inc"
@@ -205,7 +205,7 @@ struct HexagonOperand : public MCParsedAsmOperand {
205205
};
206206

207207
struct RegTy {
208-
unsigned RegNum;
208+
MCRegister RegNum;
209209
};
210210

211211
struct ImmTy {
@@ -434,9 +434,9 @@ struct HexagonOperand : public MCParsedAsmOperand {
434434
}
435435

436436
static std::unique_ptr<HexagonOperand>
437-
CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
437+
CreateReg(MCContext &Context, MCRegister Reg, SMLoc S, SMLoc E) {
438438
HexagonOperand *Op = new HexagonOperand(Register, Context);
439-
Op->Reg.RegNum = RegNum;
439+
Op->Reg.RegNum = Reg;
440440
Op->StartLoc = S;
441441
Op->EndLoc = E;
442442
return std::unique_ptr<HexagonOperand>(Op);
@@ -867,7 +867,7 @@ bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
867867
}
868868

869869
// validate register against architecture
870-
bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
870+
bool HexagonAsmParser::RegisterMatchesArch(MCRegister MatchNum) const {
871871
if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum))
872872
if (!getSTI().hasFeature(Hexagon::ArchV62))
873873
return false;
@@ -929,7 +929,7 @@ bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
929929
MCAsmLexer &Lexer = getLexer();
930930
if (!parseRegister(Register, Begin, End)) {
931931
if (!ErrorMissingParenthesis)
932-
switch (Register) {
932+
switch (Register.id()) {
933933
default:
934934
break;
935935
case Hexagon::P0:
@@ -1054,8 +1054,8 @@ ParseStatus HexagonAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
10541054
llvm::erase_if(Collapsed, isSpace);
10551055
StringRef FullString = Collapsed;
10561056
std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
1057-
unsigned DotReg = matchRegister(DotSplit.first.lower());
1058-
if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1057+
MCRegister DotReg = matchRegister(DotSplit.first.lower());
1058+
if (DotReg && RegisterMatchesArch(DotReg)) {
10591059
if (DotSplit.second.empty()) {
10601060
Reg = DotReg;
10611061
EndLoc = Lexer.getLoc();
@@ -1074,8 +1074,8 @@ ParseStatus HexagonAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
10741074
}
10751075
}
10761076
std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1077-
unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1078-
if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1077+
MCRegister ColonReg = matchRegister(ColonSplit.first.lower());
1078+
if (ColonReg && RegisterMatchesArch(DotReg)) {
10791079
do {
10801080
Lexer.UnLex(Lookahead.pop_back_val());
10811081
} while (!Lookahead.empty() && !Lexer.is(AsmToken::Colon));
@@ -1358,13 +1358,13 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
13581358

13591359
return std::make_pair(matchRegister(R1), matchRegister(R2));
13601360
};
1361-
auto GetScalarRegs = [RI, GetRegPair](unsigned RegPair) {
1361+
auto GetScalarRegs = [RI, GetRegPair](MCRegister RegPair) {
13621362
const unsigned Lower = RI->getEncodingValue(RegPair);
13631363
const RegPairVals RegPair_ = std::make_pair(Lower + 1, Lower);
13641364

13651365
return GetRegPair(RegPair_);
13661366
};
1367-
auto GetVecRegs = [GetRegPair](unsigned VecRegPair) {
1367+
auto GetVecRegs = [GetRegPair](MCRegister VecRegPair) {
13681368
const RegPairVals RegPair =
13691369
HexagonMCInstrInfo::GetVecRegPairIndices(VecRegPair);
13701370

@@ -1461,7 +1461,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
14611461
// Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
14621462
case Hexagon::A2_tfrp: {
14631463
MCOperand &MO = Inst.getOperand(1);
1464-
const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
1464+
const std::pair<MCRegister, MCRegister> RegPair =
1465+
GetScalarRegs(MO.getReg());
14651466
MO.setReg(RegPair.first);
14661467
Inst.addOperand(MCOperand::createReg(RegPair.second));
14671468
Inst.setOpcode(Hexagon::A2_combinew);
@@ -1471,7 +1472,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
14711472
case Hexagon::A2_tfrpt:
14721473
case Hexagon::A2_tfrpf: {
14731474
MCOperand &MO = Inst.getOperand(2);
1474-
const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
1475+
const std::pair<MCRegister, MCRegister> RegPair =
1476+
GetScalarRegs(MO.getReg());
14751477
MO.setReg(RegPair.first);
14761478
Inst.addOperand(MCOperand::createReg(RegPair.second));
14771479
Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
@@ -1482,7 +1484,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
14821484
case Hexagon::A2_tfrptnew:
14831485
case Hexagon::A2_tfrpfnew: {
14841486
MCOperand &MO = Inst.getOperand(2);
1485-
const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
1487+
const std::pair<MCRegister, MCRegister> RegPair =
1488+
GetScalarRegs(MO.getReg());
14861489
MO.setReg(RegPair.first);
14871490
Inst.addOperand(MCOperand::createReg(RegPair.second));
14881491
Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
@@ -1494,7 +1497,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
14941497
// Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
14951498
case Hexagon::V6_vassignp: {
14961499
MCOperand &MO = Inst.getOperand(1);
1497-
const std::pair<unsigned, unsigned> RegPair = GetVecRegs(MO.getReg());
1500+
const std::pair<MCRegister, MCRegister> RegPair = GetVecRegs(MO.getReg());
14981501
MO.setReg(RegPair.first);
14991502
Inst.addOperand(MCOperand::createReg(RegPair.second));
15001503
Inst.setOpcode(Hexagon::V6_vcombine);
@@ -2051,8 +2054,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
20512054
return Match_Success;
20522055
}
20532056

2054-
unsigned HexagonAsmParser::matchRegister(StringRef Name) {
2055-
if (unsigned Reg = MatchRegisterName(Name))
2057+
MCRegister HexagonAsmParser::matchRegister(StringRef Name) {
2058+
if (MCRegister Reg = MatchRegisterName(Name))
20562059
return Reg;
20572060
return MatchRegisterAltName(Name);
20582061
}

‎llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -499,13 +499,14 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
499499
bool SubregBit = (Register & 0x1) != 0;
500500
if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
501501
// If subreg bit is set we're selecting the second produced newvalue
502-
unsigned Producer = SubregBit ?
503-
HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() :
504-
HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
502+
MCRegister Producer =
503+
SubregBit
504+
? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
505+
: HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
505506
assert(Producer != Hexagon::NoRegister);
506507
MCO.setReg(Producer);
507508
} else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
508-
unsigned Producer =
509+
MCRegister Producer =
509510
HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
510511

511512
if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -65,8 +65,8 @@ void HexagonMCChecker::init() {
6565
init(MCB);
6666
}
6767

68-
void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
69-
bool &isTrue) {
68+
void HexagonMCChecker::initReg(MCInst const &MCI, MCRegister R,
69+
MCRegister &PredReg, bool &isTrue) {
7070
if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
7171
HexagonMCInstrInfo::isPredReg(RI, R)) {
7272
// Note an used predicate register.
@@ -91,7 +91,7 @@ void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
9191

9292
void HexagonMCChecker::init(MCInst const &MCI) {
9393
const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
94-
unsigned PredReg = Hexagon::NoRegister;
94+
MCRegister PredReg;
9595
bool isTrue = false;
9696

9797
// Get used registers.
@@ -133,7 +133,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
133133

134134
// Figure out explicit register definitions.
135135
for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
136-
unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
136+
MCRegister R = MCI.getOperand(i).getReg(), S = MCRegister();
137137
// USR has subregisters (while C8 does not for technical reasons), so
138138
// reset R to USR, since we know how to handle multiple defs of USR,
139139
// taking into account its subregisters.
@@ -187,7 +187,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
187187
if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
188188
for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
189189
if (MCI.getOperand(i).isReg()) {
190-
unsigned P = MCI.getOperand(i).getReg();
190+
MCRegister P = MCI.getOperand(i).getReg();
191191

192192
if (HexagonMCInstrInfo::isPredReg(RI, P))
193193
NewPreds.insert(P);
@@ -531,7 +531,7 @@ bool HexagonMCChecker::checkRegistersReadOnly() {
531531
for (unsigned j = 0; j < Defs; ++j) {
532532
MCOperand const &Operand = Inst.getOperand(j);
533533
assert(Operand.isReg() && "Def is not a register");
534-
unsigned Register = Operand.getReg();
534+
MCRegister Register = Operand.getReg();
535535
if (ReadOnly.find(Register) != ReadOnly.end()) {
536536
reportError(Inst.getLoc(), "Cannot write to read-only register `" +
537537
Twine(RI.getName(Register)) + "'");
@@ -542,7 +542,7 @@ bool HexagonMCChecker::checkRegistersReadOnly() {
542542
return true;
543543
}
544544

545-
bool HexagonMCChecker::registerUsed(unsigned Register) {
545+
bool HexagonMCChecker::registerUsed(MCRegister Register) {
546546
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
547547
for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
548548
n = I.getNumOperands();
@@ -556,7 +556,7 @@ bool HexagonMCChecker::registerUsed(unsigned Register) {
556556

557557
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
558558
HexagonMCChecker::registerProducer(
559-
unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
559+
MCRegister Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
560560
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
561561
WrongSense;
562562

@@ -588,7 +588,7 @@ void HexagonMCChecker::checkRegisterCurDefs() {
588588
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
589589
if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
590590
HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) {
591-
const unsigned RegDef = I.getOperand(0).getReg();
591+
const MCRegister RegDef = I.getOperand(0).getReg();
592592

593593
bool HasRegDefUse = false;
594594
for (MCRegAliasIterator Alias(RegDef, &RI, true); Alias.isValid();
@@ -819,7 +819,7 @@ bool HexagonMCChecker::checkHVXAccum()
819819
HexagonMCInstrInfo::isAccumulator(MCII, I) && I.getOperand(0).isReg();
820820
if (!IsTarget)
821821
continue;
822-
unsigned int R = I.getOperand(0).getReg();
822+
MCRegister R = I.getOperand(0).getReg();
823823
TmpDefsIterator It = TmpDefs.find(R);
824824
if (It != TmpDefs.end()) {
825825
reportError("register `" + Twine(RI.getName(R)) + ".tmp" +

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -77,15 +77,15 @@ class HexagonMCChecker {
7777

7878
void init();
7979
void init(MCInst const &);
80-
void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
80+
void initReg(MCInst const &, MCRegister, MCRegister &PredReg, bool &isTrue);
8181

82-
bool registerUsed(unsigned Register);
82+
bool registerUsed(MCRegister Register);
8383

8484
/// \return a tuple of: pointer to the producer instruction or nullptr if
8585
/// none was found, the operand index, and the PredicateInfo for the
8686
/// producer.
8787
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
88-
registerProducer(unsigned Register,
88+
registerProducer(MCRegister Register,
8989
HexagonMCInstrInfo::PredicateInfo Predicated);
9090

9191
// Checks performed.

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -388,8 +388,8 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI,
388388
}
389389
}
390390

391-
static bool RegisterMatches(unsigned Consumer, unsigned Producer,
392-
unsigned Producer2) {
391+
static bool RegisterMatches(MCRegister Consumer, MCRegister Producer,
392+
MCRegister Producer2) {
393393
return (Consumer == Producer) || (Consumer == Producer2) ||
394394
HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(Producer,
395395
Consumer);
@@ -721,9 +721,9 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
721721
// Calculate the new value distance to the associated producer
722722
unsigned SOffset = 0;
723723
unsigned VOffset = 0;
724-
unsigned UseReg = MO.getReg();
725-
unsigned DefReg1 = Hexagon::NoRegister;
726-
unsigned DefReg2 = Hexagon::NoRegister;
724+
MCRegister UseReg = MO.getReg();
725+
MCRegister DefReg1;
726+
MCRegister DefReg2;
727727

728728
auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
729729
const MCOperand *I = Instrs.begin() + State.Index - 1;
@@ -734,8 +734,8 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
734734
if (HexagonMCInstrInfo::isImmext(Inst))
735735
continue;
736736

737-
DefReg1 = Hexagon::NoRegister;
738-
DefReg2 = Hexagon::NoRegister;
737+
DefReg1 = MCRegister();
738+
DefReg2 = MCRegister();
739739
++SOffset;
740740
if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
741741
// Vector instructions don't count scalars.
@@ -770,7 +770,7 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
770770

771771
assert(!MO.isImm());
772772
if (MO.isReg()) {
773-
unsigned Reg = MO.getReg();
773+
MCRegister Reg = MO.getReg();
774774
switch (HexagonMCInstrInfo::getDesc(MCII, MI)
775775
.operands()[OperandNumber]
776776
.RegClass) {

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ static const unsigned cmpgtn1BitOpcode[8] = {
7878

7979
// enum HexagonII::CompoundGroup
8080
static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended) {
81-
unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
81+
MCRegister DstReg, SrcReg, Src1Reg, Src2Reg;
8282

8383
switch (MI.getOpcode()) {
8484
default:
@@ -174,7 +174,7 @@ static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended) {
174174
/// getCompoundOp - Return the index from 0-7 into the above opcode lists.
175175
static unsigned getCompoundOp(MCInst const &HMCI) {
176176
const MCOperand &Predicate = HMCI.getOperand(0);
177-
unsigned PredReg = Predicate.getReg();
177+
MCRegister PredReg = Predicate.getReg();
178178

179179
assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
180180
(PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ unsigned HexagonMCInstrInfo::iClassOfDuplexPair(unsigned Ga, unsigned Gb) {
187187
}
188188

189189
unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
190-
unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
190+
MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
191191

192192
switch (MCI.getOpcode()) {
193193
default:
@@ -533,7 +533,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
533533
}
534534

535535
bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) {
536-
unsigned DstReg, SrcReg;
536+
MCRegister DstReg, SrcReg;
537537
switch (potentialDuplex.getOpcode()) {
538538
case Hexagon::A2_addi:
539539
// testing for case of: Rx = add(Rx,#s7)
@@ -657,7 +657,7 @@ bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
657657
inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
658658
unsigned opNum) {
659659
if (Inst.getOperand(opNum).isReg()) {
660-
switch (Inst.getOperand(opNum).getReg()) {
660+
switch (Inst.getOperand(opNum).getReg().id()) {
661661
default:
662662
llvm_unreachable("Not Duplexable Register");
663663
break;

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