Skip to content

Commit fd50cdf

Browse files
topperctopperc
committed
[AMDGPU] Use MCRegister. NFC
1 parent fcde4f6 commit fd50cdf

File tree

9 files changed

+113
-110
lines changed

9 files changed

+113
-110
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 87 additions & 82 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1038,18 +1038,18 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
10381038
return;
10391039

10401040
// Widen the register to the correct number of enabled channels.
1041-
unsigned NewVdata = AMDGPU::NoRegister;
1041+
MCRegister NewVdata;
10421042
if (DstSize != Info->VDataDwords) {
10431043
auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
10441044

10451045
// Get first subregister of VData
1046-
unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
1047-
unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
1046+
MCRegister Vdata0 = MI.getOperand(VDataIdx).getReg();
1047+
MCRegister VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
10481048
Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
10491049

10501050
NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
10511051
&MRI.getRegClass(DataRCID));
1052-
if (NewVdata == AMDGPU::NoRegister) {
1052+
if (!NewVdata) {
10531053
// It's possible to encode this such that the low register + enabled
10541054
// components exceeds the register count.
10551055
return;
@@ -1059,11 +1059,11 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
10591059
// If not using NSA on GFX10+, widen vaddr0 address register to correct size.
10601060
// If using partial NSA on GFX11+ widen last address register.
10611061
int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx;
1062-
unsigned NewVAddrSA = AMDGPU::NoRegister;
1062+
MCRegister NewVAddrSA;
10631063
if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) &&
10641064
AddrSize != Info->VAddrDwords) {
1065-
unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg();
1066-
unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
1065+
MCRegister VAddrSA = MI.getOperand(VAddrSAIdx).getReg();
1066+
MCRegister VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
10671067
VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
10681068

10691069
auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -315,10 +315,10 @@ void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
315315
}
316316
}
317317

318-
void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
318+
void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O,
319319
const MCRegisterInfo &MRI) {
320320
#if !defined(NDEBUG)
321-
switch (RegNo) {
321+
switch (Reg.id()) {
322322
case AMDGPU::FP_REG:
323323
case AMDGPU::SP_REG:
324324
case AMDGPU::PRIVATE_RSRC_REG:
@@ -328,7 +328,7 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
328328
}
329329
#endif
330330

331-
O << getRegisterName(RegNo);
331+
O << getRegisterName(Reg);
332332
}
333333

334334
void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ class AMDGPUInstPrinter : public MCInstPrinter {
3232
void printRegName(raw_ostream &OS, MCRegister Reg) const override;
3333
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
3434
const MCSubtargetInfo &STI, raw_ostream &O) override;
35-
static void printRegOperand(unsigned RegNo, raw_ostream &O,
35+
static void printRegOperand(MCRegister Reg, raw_ostream &O,
3636
const MCRegisterInfo &MRI);
3737

3838
private:

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -489,7 +489,7 @@ void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
489489
const MCOperand &MO = MI.getOperand(OpNo);
490490

491491
if (MO.isReg()) {
492-
unsigned Reg = MO.getReg();
492+
MCRegister Reg = MO.getReg();
493493
RegEnc |= MRI.getEncodingValue(Reg);
494494
RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
495495
if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
@@ -518,7 +518,7 @@ void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
518518

519519
const MCOperand &MO = MI.getOperand(OpNo);
520520

521-
unsigned Reg = MO.getReg();
521+
MCRegister Reg = MO.getReg();
522522
if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
523523
RegEnc |= MRI.getEncodingValue(Reg);
524524
RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
@@ -530,7 +530,7 @@ void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
530530
void AMDGPUMCCodeEmitter::getAVOperandEncoding(
531531
const MCInst &MI, unsigned OpNo, APInt &Op,
532532
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
533-
unsigned Reg = MI.getOperand(OpNo).getReg();
533+
MCRegister Reg = MI.getOperand(OpNo).getReg();
534534
unsigned Enc = MRI.getEncodingValue(Reg);
535535
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
536536
bool IsVGPROrAGPR =

‎llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
141141

142142
const MCOperand &Op = MI->getOperand(OpNo);
143143
if (Op.isReg()) {
144-
switch (Op.getReg()) {
144+
switch (Op.getReg().id()) {
145145
// This is the default predicate state, so we don't need to print it.
146146
case R600::PRED_SEL_OFF:
147147
break;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ class R600MCCodeEmitter : public MCCodeEmitter {
5252
void emit(uint32_t value, SmallVectorImpl<char> &CB) const;
5353
void emit(uint64_t value, SmallVectorImpl<char> &CB) const;
5454

55-
unsigned getHWReg(unsigned regNo) const;
55+
unsigned getHWReg(MCRegister Reg) const;
5656

5757
uint64_t getBinaryCodeForInstr(const MCInst &MI,
5858
SmallVectorImpl<MCFixup> &Fixups,
@@ -145,8 +145,8 @@ void R600MCCodeEmitter::emit(uint64_t Value, SmallVectorImpl<char> &CB) const {
145145
support::endian::write(CB, Value, llvm::endianness::little);
146146
}
147147

148-
unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
149-
return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
148+
unsigned R600MCCodeEmitter::getHWReg(MCRegister Reg) const {
149+
return MRI.getEncodingValue(Reg) & HW_REG_MASK;
150150
}
151151

152152
uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2219,9 +2219,9 @@ int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
22192219
return std::max(ArgNumVGPR, ArgNumAGPR);
22202220
}
22212221

2222-
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
2222+
bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI) {
22232223
const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
2224-
const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
2224+
const MCRegister FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
22252225
return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
22262226
Reg == AMDGPU::SCC;
22272227
}
@@ -2232,7 +2232,7 @@ bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI) {
22322232

22332233
#define MAP_REG2REG \
22342234
using namespace AMDGPU; \
2235-
switch(Reg) { \
2235+
switch(Reg.id()) { \
22362236
default: return Reg; \
22372237
CASE_CI_VI(FLAT_SCR) \
22382238
CASE_CI_VI(FLAT_SCR_LO) \
@@ -2287,7 +2287,7 @@ bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI) {
22872287
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
22882288
case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
22892289

2290-
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
2290+
MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI) {
22912291
if (STI.getTargetTriple().getArch() == Triple::r600)
22922292
return Reg;
22932293
MAP_REG2REG
@@ -2303,9 +2303,7 @@ unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
23032303
#define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
23042304
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
23052305

2306-
unsigned mc2PseudoReg(unsigned Reg) {
2307-
MAP_REG2REG
2308-
}
2306+
MCRegister mc2PseudoReg(MCRegister Reg) { MAP_REG2REG }
23092307

23102308
bool isInlineValue(unsigned Reg) {
23112309
switch (Reg) {

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1316,18 +1316,18 @@ unsigned hasKernargPreload(const MCSubtargetInfo &STI);
13161316
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST);
13171317

13181318
/// Is Reg - scalar register
1319-
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1319+
bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI);
13201320

13211321
/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.
13221322
bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI);
13231323

13241324
/// If \p Reg is a pseudo reg, return the correct hardware register given
13251325
/// \p STI otherwise return \p Reg.
1326-
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1326+
MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI);
13271327

13281328
/// Convert hardware register \p Reg to a pseudo register
13291329
LLVM_READNONE
1330-
unsigned mc2PseudoReg(unsigned Reg);
1330+
MCRegister mc2PseudoReg(MCRegister Reg);
13311331

13321332
LLVM_READNONE
13331333
bool isInlineValue(unsigned Reg);

0 commit comments

Comments
 (0)