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[llvm-mca][X86] Add missing CLWB/CLZERO/FSGSBASE/LWP/MWAITX/RDPID/SHA tests
We're getting pretty close to matching/exceeding test coverage of the test\CodeGen\X86\*-schedule.ll files, which should allow us to get rid of -print-schedule and fix PR37160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351836 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 1175177 commit f26bb9e

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -instruction-tables < %s | FileCheck %s
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llwpcb %edi
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llwpcb %rdi
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lwpins $-1985229329, %esi, %edi
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lwpins $-1985229329, (%rsi), %edi
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lwpins $-1985229329, %esi, %rdi
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lwpins $-1985229329, (%rsi), %rdi
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lwpval $-1985229329, %esi, %edi
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lwpval $-1985229329, (%rsi), %edi
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lwpval $-1985229329, %esi, %rdi
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lwpval $-1985229329, (%rsi), %rdi
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slwpcb %edi
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slwpcb %rdi
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 100 0.50 * * U llwpcb %edi
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# CHECK-NEXT: 1 100 0.50 * * U llwpcb %rdi
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# CHECK-NEXT: 1 100 0.50 * * U lwpins $-1985229329, %esi, %edi
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# CHECK-NEXT: 1 100 0.50 * * U lwpins $-1985229329, (%rsi), %edi
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# CHECK-NEXT: 1 100 0.50 * * U lwpins $-1985229329, %esi, %rdi
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# CHECK-NEXT: 1 100 0.50 * * U lwpins $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: 1 100 0.50 * * U lwpval $-1985229329, %esi, %edi
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# CHECK-NEXT: 1 100 0.50 * * U lwpval $-1985229329, (%rsi), %edi
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# CHECK-NEXT: 1 100 0.50 * * U lwpval $-1985229329, %esi, %rdi
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# CHECK-NEXT: 1 100 0.50 * * U lwpval $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: 1 100 0.50 * * U slwpcb %edi
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# CHECK-NEXT: 1 100 0.50 * * U slwpcb %rdi
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - PdAGLU01
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# CHECK-NEXT: [0.1] - PdAGLU01
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# CHECK-NEXT: [1] - PdBranch
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# CHECK-NEXT: [2] - PdCount
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# CHECK-NEXT: [3] - PdDiv
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# CHECK-NEXT: [4] - PdEX0
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# CHECK-NEXT: [5] - PdEX1
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# CHECK-NEXT: [6] - PdFPCVT
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# CHECK-NEXT: [7.0] - PdFPFMA
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# CHECK-NEXT: [7.1] - PdFPFMA
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# CHECK-NEXT: [8.0] - PdFPMAL
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# CHECK-NEXT: [8.1] - PdFPMAL
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# CHECK-NEXT: [9] - PdFPMMA
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# CHECK-NEXT: [10] - PdFPSTO
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# CHECK-NEXT: [11] - PdFPU0
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# CHECK-NEXT: [12] - PdFPU1
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# CHECK-NEXT: [13] - PdFPU2
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# CHECK-NEXT: [14] - PdFPU3
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# CHECK-NEXT: [15] - PdFPXBR
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# CHECK-NEXT: [16.0] - PdLoad
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# CHECK-NEXT: [16.1] - PdLoad
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# CHECK-NEXT: [17] - PdMul
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# CHECK-NEXT: [18] - PdStore
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7.0] [7.1] [8.0] [8.1] [9] [10] [11] [12] [13] [14] [15] [16.0] [16.1] [17] [18]
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# CHECK-NEXT: - - - - - 6.00 6.00 - - - - - - - - - - - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7.0] [7.1] [8.0] [8.1] [9] [10] [11] [12] [13] [14] [15] [16.0] [16.1] [17] [18] Instructions:
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - llwpcb %edi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - llwpcb %rdi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpins $-1985229329, %esi, %edi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpins $-1985229329, (%rsi), %edi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpins $-1985229329, %esi, %rdi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpins $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpval $-1985229329, %esi, %edi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpval $-1985229329, (%rsi), %edi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpval $-1985229329, %esi, %rdi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lwpval $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - slwpcb %edi
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# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - slwpcb %rdi
Lines changed: 59 additions & 0 deletions
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -instruction-tables < %s | FileCheck %s
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rdfsbase %eax
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rdfsbase %rax
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rdgsbase %eax
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rdgsbase %rax
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wrfsbase %edi
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wrfsbase %rdi
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wrgsbase %edi
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wrgsbase %rdi
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 100 0.25 * * U rdfsbasel %eax
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# CHECK-NEXT: 1 100 0.25 * * U rdfsbaseq %rax
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# CHECK-NEXT: 1 100 0.25 * * U rdgsbasel %eax
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# CHECK-NEXT: 1 100 0.25 * * U rdgsbaseq %rax
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# CHECK-NEXT: 1 100 0.25 * * U wrfsbasel %edi
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# CHECK-NEXT: 1 100 0.25 * * U wrfsbaseq %rdi
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# CHECK-NEXT: 1 100 0.25 * * U wrgsbasel %edi
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# CHECK-NEXT: 1 100 0.25 * * U wrgsbaseq %rdi
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# CHECK: Resources:
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# CHECK-NEXT: [0] - BWDivider
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# CHECK-NEXT: [1] - BWFPDivider
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# CHECK-NEXT: [2] - BWPort0
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# CHECK-NEXT: [3] - BWPort1
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# CHECK-NEXT: [4] - BWPort2
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# CHECK-NEXT: [5] - BWPort3
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# CHECK-NEXT: [6] - BWPort4
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# CHECK-NEXT: [7] - BWPort5
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# CHECK-NEXT: [8] - BWPort6
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# CHECK-NEXT: [9] - BWPort7
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
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# CHECK-NEXT: - - 2.00 2.00 - - - 2.00 2.00 -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - rdfsbasel %eax
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - rdfsbaseq %rax
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - rdgsbasel %eax
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - rdgsbaseq %rax
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - wrfsbasel %edi
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - wrfsbaseq %rdi
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - wrgsbasel %edi
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# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - wrgsbaseq %rdi
Lines changed: 33 additions & 0 deletions
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
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clwb (%rax)
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 5 0.50 * * U clwb (%rax)
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SBDivider
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# CHECK-NEXT: [1] - SBFPDivider
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# CHECK-NEXT: [2] - SBPort0
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# CHECK-NEXT: [3] - SBPort1
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# CHECK-NEXT: [4] - SBPort4
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# CHECK-NEXT: [5] - SBPort5
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# CHECK-NEXT: [6.0] - SBPort23
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# CHECK-NEXT: [6.1] - SBPort23
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
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# CHECK-NEXT: - - - - - - 0.50 0.50
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
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# CHECK-NEXT: - - - - - - 0.50 0.50 clwb (%rax)
Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
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clzero
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 100 0.33 U clzero
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SBDivider
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# CHECK-NEXT: [1] - SBFPDivider
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# CHECK-NEXT: [2] - SBPort0
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# CHECK-NEXT: [3] - SBPort1
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# CHECK-NEXT: [4] - SBPort4
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# CHECK-NEXT: [5] - SBPort5
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# CHECK-NEXT: [6.0] - SBPort23
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# CHECK-NEXT: [6.1] - SBPort23
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - clzero
Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
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rdfsbase %eax
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rdfsbase %rax
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rdgsbase %eax
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rdgsbase %rax
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wrfsbase %edi
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wrfsbase %rdi
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wrgsbase %edi
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wrgsbase %rdi
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 100 0.33 * * U rdfsbasel %eax
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# CHECK-NEXT: 1 100 0.33 * * U rdfsbaseq %rax
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# CHECK-NEXT: 1 100 0.33 * * U rdgsbasel %eax
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# CHECK-NEXT: 1 100 0.33 * * U rdgsbaseq %rax
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# CHECK-NEXT: 1 100 0.33 * * U wrfsbasel %edi
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# CHECK-NEXT: 1 100 0.33 * * U wrfsbaseq %rdi
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# CHECK-NEXT: 1 100 0.33 * * U wrgsbasel %edi
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# CHECK-NEXT: 1 100 0.33 * * U wrgsbaseq %rdi
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SBDivider
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# CHECK-NEXT: [1] - SBFPDivider
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# CHECK-NEXT: [2] - SBPort0
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# CHECK-NEXT: [3] - SBPort1
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# CHECK-NEXT: [4] - SBPort4
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# CHECK-NEXT: [5] - SBPort5
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# CHECK-NEXT: [6.0] - SBPort23
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# CHECK-NEXT: [6.1] - SBPort23
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
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# CHECK-NEXT: - - 2.67 2.67 - 2.67 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdfsbasel %eax
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdfsbaseq %rax
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdgsbasel %eax
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdgsbaseq %rax
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wrfsbasel %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wrfsbaseq %rdi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wrgsbasel %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wrgsbaseq %rdi
Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
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llwpcb %edi
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llwpcb %rdi
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lwpins $-1985229329, %esi, %edi
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lwpins $-1985229329, (%rsi), %edi
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lwpins $-1985229329, %esi, %rdi
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lwpins $-1985229329, (%rsi), %rdi
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lwpval $-1985229329, %esi, %edi
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lwpval $-1985229329, (%rsi), %edi
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lwpval $-1985229329, %esi, %rdi
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lwpval $-1985229329, (%rsi), %rdi
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slwpcb %edi
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slwpcb %rdi
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 100 0.33 * * U llwpcb %edi
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# CHECK-NEXT: 1 100 0.33 * * U llwpcb %rdi
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# CHECK-NEXT: 1 100 0.33 * * U lwpins $-1985229329, %esi, %edi
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# CHECK-NEXT: 1 100 0.33 * * U lwpins $-1985229329, (%rsi), %edi
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# CHECK-NEXT: 1 100 0.33 * * U lwpins $-1985229329, %esi, %rdi
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# CHECK-NEXT: 1 100 0.33 * * U lwpins $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: 1 100 0.33 * * U lwpval $-1985229329, %esi, %edi
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# CHECK-NEXT: 1 100 0.33 * * U lwpval $-1985229329, (%rsi), %edi
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# CHECK-NEXT: 1 100 0.33 * * U lwpval $-1985229329, %esi, %rdi
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# CHECK-NEXT: 1 100 0.33 * * U lwpval $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: 1 100 0.33 * * U slwpcb %edi
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# CHECK-NEXT: 1 100 0.33 * * U slwpcb %rdi
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SBDivider
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# CHECK-NEXT: [1] - SBFPDivider
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# CHECK-NEXT: [2] - SBPort0
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# CHECK-NEXT: [3] - SBPort1
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# CHECK-NEXT: [4] - SBPort4
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# CHECK-NEXT: [5] - SBPort5
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# CHECK-NEXT: [6.0] - SBPort23
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# CHECK-NEXT: [6.1] - SBPort23
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
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# CHECK-NEXT: - - 4.00 4.00 - 4.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - llwpcb %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - llwpcb %rdi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpins $-1985229329, %esi, %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpins $-1985229329, (%rsi), %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpins $-1985229329, %esi, %rdi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpins $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpval $-1985229329, %esi, %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpval $-1985229329, (%rsi), %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpval $-1985229329, %esi, %rdi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - lwpval $-1985229329, (%rsi), %rdi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - slwpcb %edi
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - slwpcb %rdi
Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
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monitorx
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mwaitx
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 100 0.33 U monitorx
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# CHECK-NEXT: 1 100 0.33 * * U mwaitx
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19+
# CHECK: Resources:
20+
# CHECK-NEXT: [0] - SBDivider
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# CHECK-NEXT: [1] - SBFPDivider
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# CHECK-NEXT: [2] - SBPort0
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# CHECK-NEXT: [3] - SBPort1
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# CHECK-NEXT: [4] - SBPort4
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# CHECK-NEXT: [5] - SBPort5
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# CHECK-NEXT: [6.0] - SBPort23
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# CHECK-NEXT: [6.1] - SBPort23
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29+
# CHECK: Resource pressure per iteration:
30+
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
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# CHECK-NEXT: - - 0.67 0.67 - 0.67 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - monitorx
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# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - mwaitx

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