AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D38439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316815 91177308-0d34-0410-b5e6-96231b3b80d8

Author: tstellar

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

@@ -49,6 +49,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
 
   setAction({G_FCONSTANT, S32}, Legal);
 
+  setAction({G_FADD, S32}, Legal);
+
   setAction({G_FMUL, S32}, Legal);
 
   setAction({G_GEP, P1}, Legal);

test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir

@@ -0,0 +1,26 @@
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @test_fadd() {
+  entry:
+    ret void
+  }
+
+...
+
+---
+name:            test_fadd
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %vgpr0, %vgpr1
+    ; CHECK-LABEL: name: test_fadd
+    ; CHECK: %2:_(s32) = G_FADD %0, %1
+
+    %0(s32) = COPY %vgpr0
+    %1(s32) = COPY %vgpr1
+    %2(s32) = G_FADD %0, %1
+...