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[Hexagon] Avoid implicit truncation in getConstant()
Use getSignedConstant() or change variable type as appropriate. This will avoid assertion failures when implicit truncation is disabled.
1 parent 8895932 commit 22fdc57

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5 files changed

+30
-28
lines changed

5 files changed

+30
-28
lines changed

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
135135
llvm_unreachable("Unexpected memory type in indexed load");
136136
}
137137

138-
SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
138+
SDValue IncV = CurDAG->getSignedTargetConstant(Inc, dl, MVT::i32);
139139
MachineMemOperand *MemOp = LD->getMemOperand();
140140

141141
auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl)
@@ -213,7 +213,8 @@ MachineSDNode *HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(SDNode *IntN) {
213213
EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
214214
// Operands: { Base, Increment, Modifier, Chain }
215215
auto Inc = cast<ConstantSDNode>(IntN->getOperand(5));
216-
SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), dl, MVT::i32);
216+
SDValue I =
217+
CurDAG->getSignedTargetConstant(Inc->getSExtValue(), dl, MVT::i32);
217218
MachineSDNode *Res = CurDAG->getMachineNode(FLC->second, dl, RTys,
218219
{ IntN->getOperand(2), I, IntN->getOperand(4),
219220
IntN->getOperand(0) });
@@ -531,7 +532,7 @@ void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) {
531532
dl, MVT::i32, Value);
532533
}
533534

534-
SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
535+
SDValue IncV = CurDAG->getSignedTargetConstant(Inc, dl, MVT::i32);
535536
MachineMemOperand *MemOp = ST->getMemOperand();
536537

537538
// Next address Chain
@@ -889,7 +890,7 @@ void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
889890
MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
890891
assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits());
891892

892-
SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
893+
SDValue C = CurDAG->getSignedTargetConstant(-1, dl, MVT::i32);
893894
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
894895
SDNode *T = CurDAG->getMachineNode(Hexagon::V6_vandvrt, dl, ResTy,
895896
N->getOperand(0), SDValue(R,0));
@@ -902,7 +903,7 @@ void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) {
902903
// The result of V2Q should be a single vector.
903904
assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits());
904905

905-
SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
906+
SDValue C = CurDAG->getSignedTargetConstant(-1, dl, MVT::i32);
906907
SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
907908
SDNode *T = CurDAG->getMachineNode(Hexagon::V6_vandqrt, dl, ResTy,
908909
N->getOperand(0), SDValue(R,0));
@@ -1491,7 +1492,7 @@ inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) {
14911492
EVT T = N.getValueType();
14921493
if (!T.isInteger() || T.getSizeInBits() != 32 || !isa<ConstantSDNode>(N))
14931494
return false;
1494-
int32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
1495+
uint32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
14951496
R = CurDAG->getTargetConstant(V, SDLoc(N), N.getValueType());
14961497
return true;
14971498
}
@@ -1502,7 +1503,7 @@ bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R,
15021503
case ISD::Constant: {
15031504
if (N.getValueType() != MVT::i32)
15041505
return false;
1505-
int32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
1506+
uint32_t V = cast<const ConstantSDNode>(N)->getZExtValue();
15061507
if (!isAligned(Alignment, V))
15071508
return false;
15081509
R = CurDAG->getTargetConstant(V, SDLoc(N), N.getValueType());

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2557,10 +2557,10 @@ HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
25572557
if (ElemTy == MVT::i8) {
25582558
// First try generating a constant.
25592559
if (AllConst) {
2560-
int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2561-
(Consts[1]->getZExtValue() & 0xFF) << 8 |
2562-
(Consts[2]->getZExtValue() & 0xFF) << 16 |
2563-
Consts[3]->getZExtValue() << 24;
2560+
uint32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2561+
(Consts[1]->getZExtValue() & 0xFF) << 8 |
2562+
(Consts[2]->getZExtValue() & 0xFF) << 16 |
2563+
Consts[3]->getZExtValue() << 24;
25642564
return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
25652565
}
25662566

‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1203,8 +1203,9 @@ HexagonTargetLowering::insertHvxElementReg(SDValue VecV, SDValue IdxV,
12031203
SDValue ByteIdxV) {
12041204
MVT VecTy = ty(VecV);
12051205
unsigned HwLen = Subtarget.getVectorLength();
1206-
SDValue MaskV = DAG.getNode(ISD::AND, dl, MVT::i32,
1207-
{ByteIdxV, DAG.getConstant(-4, dl, MVT::i32)});
1206+
SDValue MaskV =
1207+
DAG.getNode(ISD::AND, dl, MVT::i32,
1208+
{ByteIdxV, DAG.getSignedConstant(-4, dl, MVT::i32)});
12081209
SDValue RotV = DAG.getNode(HexagonISD::VROR, dl, VecTy, {VecV, MaskV});
12091210
SDValue InsV = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy, {RotV, ValV});
12101211
SDValue SubV = DAG.getNode(ISD::SUB, dl, MVT::i32,
@@ -1882,7 +1883,7 @@ HexagonTargetLowering::LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const {
18821883
SDValue VecW = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy,
18831884
DAG.getConstant(ElemWidth, dl, MVT::i32));
18841885
SDValue VecN1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy,
1885-
DAG.getConstant(-1, dl, MVT::i32));
1886+
DAG.getAllOnesConstant(dl, MVT::i32));
18861887

18871888
// Do not use DAG.getNOT, because that would create BUILD_VECTOR with
18881889
// a BITCAST. Here we can skip the BITCAST (so we don't have to handle
@@ -2264,7 +2265,7 @@ SDValue HexagonTargetLowering::LowerHvxFpExtend(SDValue Op,
22642265

22652266
SDValue ShuffVec =
22662267
getInstr(Hexagon::V6_vshuffvdd, dl, VecTy,
2267-
{HiVec, LoVec, DAG.getConstant(-4, dl, MVT::i32)}, DAG);
2268+
{HiVec, LoVec, DAG.getSignedConstant(-4, dl, MVT::i32)}, DAG);
22682269

22692270
return ShuffVec;
22702271
}
@@ -2416,7 +2417,7 @@ HexagonTargetLowering::emitHvxAddWithOverflow(SDValue A, SDValue B,
24162417
// i.e. (~A xor B) & ((A+B) xor B), then check the sign bit
24172418
SDValue Add = DAG.getNode(ISD::ADD, dl, ResTy, {A, B});
24182419
SDValue NotA =
2419-
DAG.getNode(ISD::XOR, dl, ResTy, {A, DAG.getConstant(-1, dl, ResTy)});
2420+
DAG.getNode(ISD::XOR, dl, ResTy, {A, DAG.getAllOnesConstant(dl, ResTy)});
24202421
SDValue Xor0 = DAG.getNode(ISD::XOR, dl, ResTy, {NotA, B});
24212422
SDValue Xor1 = DAG.getNode(ISD::XOR, dl, ResTy, {Add, B});
24222423
SDValue And = DAG.getNode(ISD::AND, dl, ResTy, {Xor0, Xor1});
@@ -3620,7 +3621,7 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
36203621
case HexagonISD::Q2V:
36213622
if (Ops[0].getOpcode() == HexagonISD::QTRUE)
36223623
return DAG.getNode(ISD::SPLAT_VECTOR, dl, ty(Op),
3623-
DAG.getConstant(-1, dl, MVT::i32));
3624+
DAG.getAllOnesConstant(dl, MVT::i32));
36243625
if (Ops[0].getOpcode() == HexagonISD::QFALSE)
36253626
return getZero(dl, ty(Op), DAG);
36263627
break;

‎llvm/lib/Target/Hexagon/HexagonIntrinsics.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,12 +148,12 @@ class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
148148

149149
def SDEC2 : SDNodeXForm<imm, [{
150150
int32_t V = N->getSExtValue();
151-
return CurDAG->getTargetConstant(V-2, SDLoc(N), MVT::i32);
151+
return CurDAG->getSignedTargetConstant(V-2, SDLoc(N), MVT::i32);
152152
}]>;
153153

154154
def SDEC3 : SDNodeXForm<imm, [{
155155
int32_t V = N->getSExtValue();
156-
return CurDAG->getTargetConstant(V-3, SDLoc(N), MVT::i32);
156+
return CurDAG->getSignedTargetConstant(V-3, SDLoc(N), MVT::i32);
157157
}]>;
158158

159159
// Table Index : Extract and insert bits.

‎llvm/lib/Target/Hexagon/HexagonPatterns.td‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -171,7 +171,7 @@ class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm),
171171

172172
def SDEC1: SDNodeXForm<imm, [{
173173
int32_t V = N->getSExtValue();
174-
return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
174+
return CurDAG->getSignedTargetConstant(V-1, SDLoc(N), MVT::i32);
175175
}]>;
176176

177177
def UDEC1: SDNodeXForm<imm, [{
@@ -388,12 +388,12 @@ def Uitofp: pf1<uint_to_fp>;
388388
//
389389

390390
def Imm64Lo: SDNodeXForm<imm, [{
391-
return CurDAG->getTargetConstant(int32_t (N->getSExtValue()),
392-
SDLoc(N), MVT::i32);
391+
return CurDAG->getSignedTargetConstant(int32_t(N->getSExtValue()),
392+
SDLoc(N), MVT::i32);
393393
}]>;
394394
def Imm64Hi: SDNodeXForm<imm, [{
395-
return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32),
396-
SDLoc(N), MVT::i32);
395+
return CurDAG->getSignedTargetConstant(int32_t(N->getSExtValue()>>32),
396+
SDLoc(N), MVT::i32);
397397
}]>;
398398

399399

@@ -406,7 +406,7 @@ def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
406406
def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
407407

408408
def TruncI64ToI32: SDNodeXForm<imm, [{
409-
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
409+
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
410410
}]>;
411411

412412
def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
@@ -2597,14 +2597,14 @@ def IMM_BYTE : SDNodeXForm<imm, [{
25972597
// -1 can be represented as 255, etc.
25982598
// assigning to a byte restores our desired signed value.
25992599
int8_t imm = N->getSExtValue();
2600-
return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2600+
return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32);
26012601
}]>;
26022602

26032603
def IMM_HALF : SDNodeXForm<imm, [{
26042604
// -1 can be represented as 65535, etc.
26052605
// assigning to a short restores our desired signed value.
26062606
int16_t imm = N->getSExtValue();
2607-
return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2607+
return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32);
26082608
}]>;
26092609

26102610
def IMM_WORD : SDNodeXForm<imm, [{
@@ -2613,7 +2613,7 @@ def IMM_WORD : SDNodeXForm<imm, [{
26132613
// might convert -1 to a large +ve number.
26142614
// assigning to a word restores our desired signed value.
26152615
int32_t imm = N->getSExtValue();
2616-
return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2616+
return CurDAG->getSignedTargetConstant(imm, SDLoc(N), MVT::i32);
26172617
}]>;
26182618

26192619
def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;

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