[ARM] Fix -mno-omit-leaf-frame-pointer flag doesn't works on 32-bit ARM (llvm#109628)

The -mno-omit-leaf-frame-pointer flag works on 32-bit ARM architectures
and addresses the bug reported in llvm#108019

Author: guoxin049

clang/docs/ReleaseNotes.rst

@@ -612,6 +612,11 @@ X86 Support
 Arm and AArch64 Support
 ^^^^^^^^^^^^^^^^^^^^^^^
 
+- In the ARM Target, the frame pointer (FP) of a leaf function can be retained
+  by using the ``-fno-omit-frame-pointer`` option. If you want to eliminate the FP
+  in leaf functions after enabling ``-fno-omit-frame-pointer``, you can do so by adding
+  the ``-momit-leaf-frame-pointer`` option.
+
 Android Support
 ^^^^^^^^^^^^^^^
 

llvm/docs/ReleaseNotes.md

@@ -125,6 +125,12 @@ Changes to the ARM Backend
   the required alignment space with a sequence of `0x0` bytes (the requested
   fill value) rather than NOPs.
 
+* The default behavior for frame pointers in leaf functions has been updated.
+  When the `-fno-omit-frame-pointer` option is specified, `FPKeepKindStr` is
+  set to `-mframe-pointer=all`, meaning the frame pointer (FP) is now retained
+  in leaf functions by default. To eliminate the frame pointer in leaf functions,
+  you must explicitly use the `-momit-leaf-frame-pointer` option.
+
 Changes to the AVR Backend
 --------------------------
 

llvm/include/llvm/CodeGen/TargetFrameLowering.h

@@ -277,12 +277,6 @@ class TargetFrameLowering {
     return false;
   }
 
-  /// Return true if the target wants to keep the frame pointer regardless of
-  /// the function attribute "frame-pointer".
-  virtual bool keepFramePointer(const MachineFunction &MF) const {
-    return false;
-  }
-
   /// hasFP - Return true if the specified function should have a dedicated
   /// frame pointer register. For most targets this is true only if the function
   /// has variable sized allocas or if frame pointer elimination is disabled.

llvm/lib/CodeGen/TargetOptionsImpl.cpp

@@ -22,10 +22,6 @@ using namespace llvm;
 /// DisableFramePointerElim - This returns true if frame pointer elimination
 /// optimization should be disabled for the given machine function.
 bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
-  // Check to see if the target want to forcibly keep frame pointer.
-  if (MF.getSubtarget().getFrameLowering()->keepFramePointer(MF))
-    return true;
-
   const Function &F = MF.getFunction();
 
   if (!F.hasFnAttribute("frame-pointer"))
@@ -41,10 +37,6 @@ bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
 }
 
 bool TargetOptions::FramePointerIsReserved(const MachineFunction &MF) const {
-  // Check to see if the target want to forcibly keep frame pointer.
-  if (MF.getSubtarget().getFrameLowering()->keepFramePointer(MF))
-    return true;
-
   const Function &F = MF.getFunction();
 
   if (!F.hasFnAttribute("frame-pointer"))

llvm/lib/Target/ARM/ARMFrameLowering.cpp

@@ -330,6 +330,10 @@ bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
 
+  // Check to see if the target want to forcibly keep frame pointer.
+  if (keepFramePointer(MF))
+    return true;
+
   // ABI-required frame pointer.
   if (MF.getTarget().Options.DisableFramePointerElim(MF))
     return true;
@@ -2403,7 +2407,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
   // to take advantage the eliminateFrameIndex machinery. This also ensures it
   // is spilled in the order specified by getCalleeSavedRegs() to make it easier
   // to combine multiple loads / stores.
-  bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF));
+  bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF)) &&
+                           !MF.getTarget().Options.DisableFramePointerElim(MF);
   bool CS1Spilled = false;
   bool LRSpilled = false;
   unsigned NumGPRSpills = 0;

llvm/lib/Target/ARM/ARMFrameLowering.h

@@ -41,7 +41,7 @@ class ARMFrameLowering : public TargetFrameLowering {
                               MutableArrayRef<CalleeSavedInfo> CSI,
                               const TargetRegisterInfo *TRI) const override;
 
-  bool keepFramePointer(const MachineFunction &MF) const override;
+  bool keepFramePointer(const MachineFunction &MF) const;
 
   bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
 

llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll

@@ -9,7 +9,7 @@
 
 @oStruct = external global %struct.Outer, align 4
 
-define void @main(i8 %val8) nounwind {
+define void @main(i8 %val8) nounwind "frame-pointer"="none" {
 ; CHECK-LABEL: main:
 ; CHECK:       @ %bb.0: @ %for.body.lr.ph
 ; CHECK-NEXT:    movw r0, :lower16:(L_oStruct$non_lazy_ptr-(LPC0_0+4))

llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll

@@ -3,7 +3,7 @@
 ; Radar 10567930: Make sure that all the caller-saved registers are saved and
 ; restored in a function with setjmp/longjmp EH.  In particular, r6 was not
 ; being saved here.
-; CHECK: push {r4, r5, r6, r7, lr}
+; CHECK: push.w {r4, r5, r6, r7, r8, r10, r11, lr}
 
 %0 = type opaque
 %struct.NSConstantString = type { ptr, i32, ptr, i32 }

llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll

@@ -1732,7 +1732,7 @@ if.end:
 ; Another infinite loop test this time with two nested infinite loop.
 ; infiniteloop3
 ; bx lr
-define void @infiniteloop3() "frame-pointer"="all" {
+define void @infiniteloop3() "frame-pointer"="none" {
 ; ARM-LABEL: infiniteloop3:
 ; ARM:       @ %bb.0: @ %entry
 ; ARM-NEXT:    mov r0, #0

llvm/test/CodeGen/ARM/atomic-load-store.ll

@@ -324,18 +324,17 @@ define void @test_old_store_64bit(ptr %p, i64 %v) {
 ;
 ; ARMOPTNONE-LABEL: test_old_store_64bit:
 ; ARMOPTNONE:       @ %bb.0:
-; ARMOPTNONE-NEXT:    push {r4, r5, r7, lr}
-; ARMOPTNONE-NEXT:    add r7, sp, #8
-; ARMOPTNONE-NEXT:    push {r8, r10, r11}
-; ARMOPTNONE-NEXT:    sub sp, sp, #24
-; ARMOPTNONE-NEXT:    str r0, [sp, #4] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r2, [sp, #8] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r1, [sp, #12] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    dmb ish
-; ARMOPTNONE-NEXT:    ldr r1, [r0]
-; ARMOPTNONE-NEXT:    ldr r0, [r0, #4]
-; ARMOPTNONE-NEXT:    str r1, [sp, #16] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    push	{r4, r5, r7, r8, r10, r11, lr}
+; ARMOPTNONE-NEXT:    add	r7, sp, #20
+; ARMOPTNONE-NEXT:    sub	sp, sp, #24
+; ARMOPTNONE-NEXT:    str	r0, [sp, #4] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r2, [sp, #8] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r1, [sp, #12] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    dmb	ish
+; ARMOPTNONE-NEXT:    ldr	r1, [r0]
+; ARMOPTNONE-NEXT:    ldr	r0, [r0, #4]
+; ARMOPTNONE-NEXT:    str	r1, [sp, #16] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r0, [sp, #20] @ 4-byte Spill
 ; ARMOPTNONE-NEXT:    b LBB5_1
 ; ARMOPTNONE-NEXT:  LBB5_1: @ %atomicrmw.start
 ; ARMOPTNONE-NEXT:    @ =>This Loop Header: Depth=1
@@ -382,8 +381,7 @@ define void @test_old_store_64bit(ptr %p, i64 %v) {
 ; ARMOPTNONE-NEXT:  LBB5_5: @ %atomicrmw.end
 ; ARMOPTNONE-NEXT:    dmb ish
 ; ARMOPTNONE-NEXT:    sub sp, r7, #20
-; ARMOPTNONE-NEXT:    pop {r8, r10, r11}
-; ARMOPTNONE-NEXT:    pop {r4, r5, r7, pc}
+; ARMOPTNONE-NEXT:    pop	{r4, r5, r7, r8, r10, r11, pc}
 ;
 ; THUMBTWO-LABEL: test_old_store_64bit:
 ; THUMBTWO:       @ %bb.0:
@@ -864,20 +862,19 @@ define void @store_atomic_f64__seq_cst(ptr %ptr, double %val1) {
 ;
 ; ARMOPTNONE-LABEL: store_atomic_f64__seq_cst:
 ; ARMOPTNONE:       @ %bb.0:
-; ARMOPTNONE-NEXT:    push {r4, r5, r7, lr}
-; ARMOPTNONE-NEXT:    add r7, sp, #8
-; ARMOPTNONE-NEXT:    push {r8, r10, r11}
-; ARMOPTNONE-NEXT:    sub sp, sp, #24
-; ARMOPTNONE-NEXT:    str r0, [sp, #4] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    vmov d16, r1, r2
-; ARMOPTNONE-NEXT:    vmov r1, r2, d16
-; ARMOPTNONE-NEXT:    str r2, [sp, #8] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r1, [sp, #12] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    dmb ish
-; ARMOPTNONE-NEXT:    ldr r1, [r0]
-; ARMOPTNONE-NEXT:    ldr r0, [r0, #4]
-; ARMOPTNONE-NEXT:    str r1, [sp, #16] @ 4-byte Spill
-; ARMOPTNONE-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    push	{r4, r5, r7, r8, r10, r11, lr}
+; ARMOPTNONE-NEXT:    add	r7, sp, #20
+; ARMOPTNONE-NEXT:    sub	sp, sp, #24
+; ARMOPTNONE-NEXT:    str	r0, [sp, #4] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    vmov	d16, r1, r2
+; ARMOPTNONE-NEXT:    vmov	r1, r2, d16
+; ARMOPTNONE-NEXT:    str	r2, [sp, #8] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r1, [sp, #12] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    dmb	ish
+; ARMOPTNONE-NEXT:    ldr	r1, [r0]
+; ARMOPTNONE-NEXT:    ldr	r0, [r0, #4]
+; ARMOPTNONE-NEXT:    str	r1, [sp, #16] @ 4-byte Spill
+; ARMOPTNONE-NEXT:    str	r0, [sp, #20] @ 4-byte Spill
 ; ARMOPTNONE-NEXT:    b LBB13_1
 ; ARMOPTNONE-NEXT:  LBB13_1: @ %atomicrmw.start
 ; ARMOPTNONE-NEXT:    @ =>This Loop Header: Depth=1
@@ -924,8 +921,7 @@ define void @store_atomic_f64__seq_cst(ptr %ptr, double %val1) {
 ; ARMOPTNONE-NEXT:  LBB13_5: @ %atomicrmw.end
 ; ARMOPTNONE-NEXT:    dmb ish
 ; ARMOPTNONE-NEXT:    sub sp, r7, #20
-; ARMOPTNONE-NEXT:    pop {r8, r10, r11}
-; ARMOPTNONE-NEXT:    pop {r4, r5, r7, pc}
+; ARMOPTNONE-NEXT:    pop	{r4, r5, r7, r8, r10, r11, pc}
 ;
 ; THUMBTWO-LABEL: store_atomic_f64__seq_cst:
 ; THUMBTWO:       @ %bb.0: