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[RISCV]Add svvptc extension (llvm#113882)
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -147,6 +147,7 @@
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// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
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// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
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// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
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// CHECK-NEXT: svvptc 1.0 'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
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// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
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// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)
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// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation)

‎clang/test/Preprocessor/riscv-target-features.c‎

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@@ -52,6 +52,7 @@
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// CHECK-NOT: __riscv_svinval {{.*$}}
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// CHECK-NOT: __riscv_svnapot {{.*$}}
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// CHECK-NOT: __riscv_svpbmt {{.*$}}
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// CHECK-NOT: __riscv_svvptc {{.*$}}
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// CHECK-NOT: __riscv_v {{.*$}}
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// CHECK-NOT: __riscv_v_elen {{.*$}}
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// CHECK-NOT: __riscv_v_elen_fp {{.*$}}
@@ -516,6 +517,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
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// CHECK-SVPBMT-EXT: __riscv_svpbmt 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32isvvptc -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64isvvptc -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s
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// CHECK-SVVPTC-EXT: __riscv_svvptc 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32iv1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s

‎llvm/docs/RISCVUsage.rst‎

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@@ -156,6 +156,7 @@ on support follow.
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``Svinval`` Assembly Support
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``Svnapot`` Assembly Support
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``Svpbmt`` Supported
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``Svvptc`` Supported
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``V`` Supported
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``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)

‎llvm/docs/ReleaseNotes.md‎

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@@ -178,7 +178,7 @@ Changes to the RISC-V Backend
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means Zve32x and Zve32f will also require Zvl64b. The prior support was
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largely untested.
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* The `Zvbc32e` and `Zvkgs` extensions are now supported experimentally.
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* Added `Smctr` and `Ssctr` extensions.
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* Added `Smctr`, `Ssctr` and `Svvptc` extensions.
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* `-mcpu=syntacore-scr7` was added.
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* The `Zacas` extension is no longer marked as experimental.
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* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1029,6 +1029,10 @@ def FeatureStdExtSvpbmt
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: RISCVExtension<"svpbmt", 1, 0,
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"'Svpbmt' (Page-Based Memory Types)">;
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def FeatureStdExtSvvptc
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: RISCVExtension<"svvptc", 1, 0,
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"'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)">;
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def FeatureStdExtSha
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: RISCVExtension<"sha", 1, 0,
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"'Sha' (Augmented Hypervisor)",

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -62,6 +62,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s
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; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
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; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
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; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV32SVVPTC %s
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; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
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; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
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; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
@@ -202,6 +203,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s
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; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s
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; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s
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; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s
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; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s
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; RUN: llc -mtriple=riscv64 -mattr=+xsfvfwmaccqqq %s -o - | FileCheck --check-prefix=RV64XSFVFWMACCQQQ %s
@@ -358,6 +360,7 @@
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; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0"
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; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
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; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
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; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0"
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; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
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; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
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; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
@@ -500,6 +503,7 @@
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; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0"
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; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0"
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; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
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; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0"
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; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
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; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
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; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"

‎llvm/test/MC/RISCV/attribute-arch.s‎

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.attribute arch, "rv32i_svbare1p0"
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# CHECK: attribute 5, "rv32i2p1_svbare1p0"
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.attribute arch, "rv32i_svvptc1p0"
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# CHECK: attribute 5, "rv32i2p1_svvptc1p0"
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.attribute arch, "rv32i_zfbfmin1p0"
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# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
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‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp‎

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@@ -1092,6 +1092,7 @@ R"(All available -march extensions for RISC-V
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svinval 1.0
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svnapot 1.0
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svpbmt 1.0
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svvptc 1.0
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xcvalu 1.0
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xcvbi 1.0
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xcvbitmanip 1.0

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