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Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (llvm#110714)" v2 (llvm#111708)"
This reverts commit 4b4a0d4. New test fails on buildbots https://lab.llvm.org/buildbot/#/builders/63/builds/2039 https://lab.llvm.org/buildbot/#/builders/127/builds/1055
1 parent a1c9dd7 commit 8a849a2

12 files changed

+275
-4015
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 19 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -494,8 +494,6 @@ static bool loadStoreBitcastWorkaround(const LLT Ty) {
494494
return false;
495495

496496
const unsigned Size = Ty.getSizeInBits();
497-
if (Ty.isPointerVector())
498-
return true;
499497
if (Size <= 64)
500498
return false;
501499
// Address space 8 pointers get their own workaround.
@@ -504,6 +502,9 @@ static bool loadStoreBitcastWorkaround(const LLT Ty) {
504502
if (!Ty.isVector())
505503
return true;
506504

505+
if (Ty.isPointerVector())
506+
return true;
507+
507508
unsigned EltSize = Ty.getScalarSizeInBits();
508509
return EltSize != 32 && EltSize != 64;
509510
}
@@ -5817,9 +5818,8 @@ Register AMDGPULegalizerInfo::handleD16VData(MachineIRBuilder &B,
58175818
return Reg;
58185819
}
58195820

5820-
Register AMDGPULegalizerInfo::fixStoreSourceType(MachineIRBuilder &B,
5821-
Register VData, LLT MemTy,
5822-
bool IsFormat) const {
5821+
Register AMDGPULegalizerInfo::fixStoreSourceType(
5822+
MachineIRBuilder &B, Register VData, bool IsFormat) const {
58235823
MachineRegisterInfo *MRI = B.getMRI();
58245824
LLT Ty = MRI->getType(VData);
58255825

@@ -5829,10 +5829,6 @@ Register AMDGPULegalizerInfo::fixStoreSourceType(MachineIRBuilder &B,
58295829
if (hasBufferRsrcWorkaround(Ty))
58305830
return castBufferRsrcToV4I32(VData, B);
58315831

5832-
if (shouldBitcastLoadStoreType(ST, Ty, MemTy)) {
5833-
Ty = getBitcastRegisterType(Ty);
5834-
VData = B.buildBitcast(Ty, VData).getReg(0);
5835-
}
58365832
// Fixup illegal register types for i8 stores.
58375833
if (Ty == LLT::scalar(8) || Ty == S16) {
58385834
Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0);
@@ -5850,27 +5846,23 @@ Register AMDGPULegalizerInfo::fixStoreSourceType(MachineIRBuilder &B,
58505846
}
58515847

58525848
bool AMDGPULegalizerInfo::legalizeBufferStore(MachineInstr &MI,
5853-
LegalizerHelper &Helper,
5849+
MachineRegisterInfo &MRI,
5850+
MachineIRBuilder &B,
58545851
bool IsTyped,
58555852
bool IsFormat) const {
5856-
MachineIRBuilder &B = Helper.MIRBuilder;
5857-
MachineRegisterInfo &MRI = *B.getMRI();
5858-
58595853
Register VData = MI.getOperand(1).getReg();
58605854
LLT Ty = MRI.getType(VData);
58615855
LLT EltTy = Ty.getScalarType();
58625856
const bool IsD16 = IsFormat && (EltTy.getSizeInBits() == 16);
58635857
const LLT S32 = LLT::scalar(32);
58645858

5865-
MachineMemOperand *MMO = *MI.memoperands_begin();
5866-
const int MemSize = MMO->getSize().getValue();
5867-
LLT MemTy = MMO->getMemoryType();
5868-
5869-
VData = fixStoreSourceType(B, VData, MemTy, IsFormat);
5870-
5859+
VData = fixStoreSourceType(B, VData, IsFormat);
58715860
castBufferRsrcArgToV4I32(MI, B, 2);
58725861
Register RSrc = MI.getOperand(2).getReg();
58735862

5863+
MachineMemOperand *MMO = *MI.memoperands_begin();
5864+
const int MemSize = MMO->getSize().getValue();
5865+
58745866
unsigned ImmOffset;
58755867

58765868
// The typed intrinsics add an immediate after the registers.
@@ -5962,13 +5954,10 @@ static void buildBufferLoad(unsigned Opc, Register LoadDstReg, Register RSrc,
59625954
}
59635955

59645956
bool AMDGPULegalizerInfo::legalizeBufferLoad(MachineInstr &MI,
5965-
LegalizerHelper &Helper,
5957+
MachineRegisterInfo &MRI,
5958+
MachineIRBuilder &B,
59665959
bool IsFormat,
59675960
bool IsTyped) const {
5968-
MachineIRBuilder &B = Helper.MIRBuilder;
5969-
MachineRegisterInfo &MRI = *B.getMRI();
5970-
GISelChangeObserver &Observer = Helper.Observer;
5971-
59725961
// FIXME: Verifier should enforce 1 MMO for these intrinsics.
59735962
MachineMemOperand *MMO = *MI.memoperands_begin();
59745963
const LLT MemTy = MMO->getMemoryType();
@@ -6017,21 +6006,9 @@ bool AMDGPULegalizerInfo::legalizeBufferLoad(MachineInstr &MI,
60176006
// Make addrspace 8 pointers loads into 4xs32 loads here, so the rest of the
60186007
// logic doesn't have to handle that case.
60196008
if (hasBufferRsrcWorkaround(Ty)) {
6020-
Observer.changingInstr(MI);
60216009
Ty = castBufferRsrcFromV4I32(MI, B, MRI, 0);
6022-
Observer.changedInstr(MI);
60236010
Dst = MI.getOperand(0).getReg();
6024-
B.setInsertPt(B.getMBB(), MI);
60256011
}
6026-
if (shouldBitcastLoadStoreType(ST, Ty, MemTy)) {
6027-
Ty = getBitcastRegisterType(Ty);
6028-
Observer.changingInstr(MI);
6029-
Helper.bitcastDst(MI, Ty, 0);
6030-
Observer.changedInstr(MI);
6031-
Dst = MI.getOperand(0).getReg();
6032-
B.setInsertPt(B.getMBB(), MI);
6033-
}
6034-
60356012
LLT EltTy = Ty.getScalarType();
60366013
const bool IsD16 = IsFormat && (EltTy.getSizeInBits() == 16);
60376014
const bool Unpacked = ST.hasUnpackedD16VMem();
@@ -7411,17 +7388,17 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
74117388
case Intrinsic::amdgcn_raw_ptr_buffer_store:
74127389
case Intrinsic::amdgcn_struct_buffer_store:
74137390
case Intrinsic::amdgcn_struct_ptr_buffer_store:
7414-
return legalizeBufferStore(MI, Helper, false, false);
7391+
return legalizeBufferStore(MI, MRI, B, false, false);
74157392
case Intrinsic::amdgcn_raw_buffer_store_format:
74167393
case Intrinsic::amdgcn_raw_ptr_buffer_store_format:
74177394
case Intrinsic::amdgcn_struct_buffer_store_format:
74187395
case Intrinsic::amdgcn_struct_ptr_buffer_store_format:
7419-
return legalizeBufferStore(MI, Helper, false, true);
7396+
return legalizeBufferStore(MI, MRI, B, false, true);
74207397
case Intrinsic::amdgcn_raw_tbuffer_store:
74217398
case Intrinsic::amdgcn_raw_ptr_tbuffer_store:
74227399
case Intrinsic::amdgcn_struct_tbuffer_store:
74237400
case Intrinsic::amdgcn_struct_ptr_tbuffer_store:
7424-
return legalizeBufferStore(MI, Helper, true, true);
7401+
return legalizeBufferStore(MI, MRI, B, true, true);
74257402
case Intrinsic::amdgcn_raw_buffer_load:
74267403
case Intrinsic::amdgcn_raw_ptr_buffer_load:
74277404
case Intrinsic::amdgcn_raw_atomic_buffer_load:
@@ -7430,17 +7407,17 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
74307407
case Intrinsic::amdgcn_struct_ptr_buffer_load:
74317408
case Intrinsic::amdgcn_struct_atomic_buffer_load:
74327409
case Intrinsic::amdgcn_struct_ptr_atomic_buffer_load:
7433-
return legalizeBufferLoad(MI, Helper, false, false);
7410+
return legalizeBufferLoad(MI, MRI, B, false, false);
74347411
case Intrinsic::amdgcn_raw_buffer_load_format:
74357412
case Intrinsic::amdgcn_raw_ptr_buffer_load_format:
74367413
case Intrinsic::amdgcn_struct_buffer_load_format:
74377414
case Intrinsic::amdgcn_struct_ptr_buffer_load_format:
7438-
return legalizeBufferLoad(MI, Helper, true, false);
7415+
return legalizeBufferLoad(MI, MRI, B, true, false);
74397416
case Intrinsic::amdgcn_raw_tbuffer_load:
74407417
case Intrinsic::amdgcn_raw_ptr_tbuffer_load:
74417418
case Intrinsic::amdgcn_struct_tbuffer_load:
74427419
case Intrinsic::amdgcn_struct_ptr_tbuffer_load:
7443-
return legalizeBufferLoad(MI, Helper, true, true);
7420+
return legalizeBufferLoad(MI, MRI, B, true, true);
74447421
case Intrinsic::amdgcn_raw_buffer_atomic_swap:
74457422
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_swap:
74467423
case Intrinsic::amdgcn_struct_buffer_atomic_swap:

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -195,13 +195,15 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
195195

196196
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
197197
Register Reg, bool ImageStore = false) const;
198-
Register fixStoreSourceType(MachineIRBuilder &B, Register VData, LLT MemTy,
198+
Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
199199
bool IsFormat) const;
200200

201-
bool legalizeBufferStore(MachineInstr &MI, LegalizerHelper &Helper,
202-
bool IsTyped, bool IsFormat) const;
203-
bool legalizeBufferLoad(MachineInstr &MI, LegalizerHelper &Helper,
204-
bool IsFormat, bool IsTyped) const;
201+
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
202+
MachineIRBuilder &B, bool IsTyped,
203+
bool IsFormat) const;
204+
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
205+
MachineIRBuilder &B, bool IsFormat,
206+
bool IsTyped) const;
205207
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
206208
Intrinsic::ID IID) const;
207209

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -590,7 +590,7 @@ class RegisterTypes<list<ValueType> reg_types> {
590590

591591
def Reg16Types : RegisterTypes<[i16, f16, bf16]>;
592592
def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, v2bf16, p2, p3, p5, p6]>;
593-
def Reg64Types : RegisterTypes<[i64, f64, v2i32, v2f32, p0, p1, p4, v4i16, v4f16, v4bf16]>;
593+
def Reg64Types : RegisterTypes<[i64, f64, v2i32, v2f32, p0, v4i16, v4f16, v4bf16]>;
594594
def Reg96Types : RegisterTypes<[v3i32, v3f32]>;
595595
def Reg128Types : RegisterTypes<[v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16]>;
596596

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