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[VPlan] Set debug location for recipes in VPBB::executeRecipes.
Set the debug location for each recipe before executing the recipe, instead of ad-hoc setting the debug location during individual recipe execution. This simplifies the code and ensures that all recipe repsect the recipe's debug location. There are some minor changes, where previously we would re-use a previously set debug location.
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5 files changed

+52
-72
lines changed

5 files changed

+52
-72
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -552,8 +552,10 @@ void VPBasicBlock::executeRecipes(VPTransformState *State, BasicBlock *BB) {
552552

553553
State->CFG.PrevVPBB = this;
554554

555-
for (VPRecipeBase &Recipe : Recipes)
555+
for (VPRecipeBase &Recipe : Recipes) {
556+
State->setDebugLocFrom(Recipe.getDebugLoc());
556557
Recipe.execute(*State);
558+
}
557559

558560
LLVM_DEBUG(dbgs() << "LV: filled BB:" << *BB);
559561
}

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,6 @@ VPPartialReductionRecipe::computeCost(ElementCount VF,
327327
}
328328

329329
void VPPartialReductionRecipe::execute(VPTransformState &State) {
330-
State.setDebugLocFrom(getDebugLoc());
331330
auto &Builder = State.Builder;
332331

333332
assert(getOpcode() == Instruction::Add &&
@@ -882,7 +881,6 @@ void VPInstruction::execute(VPTransformState &State) {
882881
"Recipe not a FPMathOp but has fast-math flags?");
883882
if (hasFastMathFlags())
884883
State.Builder.setFastMathFlags(getFastMathFlags());
885-
State.setDebugLocFrom(getDebugLoc());
886884
bool GeneratesPerFirstLaneOnly = canGenerateScalarForFirstLane() &&
887885
(vputils::onlyFirstLaneUsed(this) ||
888886
isVectorToScalar() || isSingleScalar());
@@ -1163,7 +1161,6 @@ void VPIRPhi::print(raw_ostream &O, const Twine &Indent,
11631161

11641162
void VPWidenCallRecipe::execute(VPTransformState &State) {
11651163
assert(State.VF.isVector() && "not widening");
1166-
State.setDebugLocFrom(getDebugLoc());
11671164

11681165
FunctionType *VFTy = Variant->getFunctionType();
11691166
// Add return type if intrinsic is overloaded on it.
@@ -1232,7 +1229,6 @@ void VPWidenCallRecipe::print(raw_ostream &O, const Twine &Indent,
12321229

12331230
void VPWidenIntrinsicRecipe::execute(VPTransformState &State) {
12341231
assert(State.VF.isVector() && "not widening");
1235-
State.setDebugLocFrom(getDebugLoc());
12361232

12371233
SmallVector<Type *, 2> TysForDecl;
12381234
// Add return type if intrinsic is overloaded on it.
@@ -1355,7 +1351,6 @@ void VPWidenIntrinsicRecipe::print(raw_ostream &O, const Twine &Indent,
13551351
#endif
13561352

13571353
void VPHistogramRecipe::execute(VPTransformState &State) {
1358-
State.setDebugLocFrom(getDebugLoc());
13591354
IRBuilderBase &Builder = State.Builder;
13601355

13611356
Value *Address = State.get(getOperand(0));
@@ -1456,8 +1451,6 @@ void VPWidenSelectRecipe::print(raw_ostream &O, const Twine &Indent,
14561451
#endif
14571452

14581453
void VPWidenSelectRecipe::execute(VPTransformState &State) {
1459-
State.setDebugLocFrom(getDebugLoc());
1460-
14611454
// The condition can be loop invariant but still defined inside the
14621455
// loop. This means that we can't just use the original 'cond' value.
14631456
// We have to take the 'vectorized' value and pick the first lane.
@@ -1569,7 +1562,6 @@ void VPRecipeWithIRFlags::printFlags(raw_ostream &O) const {
15691562
#endif
15701563

15711564
void VPWidenRecipe::execute(VPTransformState &State) {
1572-
State.setDebugLocFrom(getDebugLoc());
15731565
auto &Builder = State.Builder;
15741566
switch (Opcode) {
15751567
case Instruction::Call:
@@ -1750,7 +1742,6 @@ void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent,
17501742
#endif
17511743

17521744
void VPWidenCastRecipe::execute(VPTransformState &State) {
1753-
State.setDebugLocFrom(getDebugLoc());
17541745
auto &Builder = State.Builder;
17551746
/// Vectorize casts.
17561747
assert(State.VF.isVector() && "Not vectorizing?");
@@ -2029,7 +2020,6 @@ void VPDerivedIVRecipe::print(raw_ostream &O, const Twine &Indent,
20292020
#endif
20302021

20312022
void VPScalarIVStepsRecipe::execute(VPTransformState &State) {
2032-
State.setDebugLocFrom(getDebugLoc());
20332023
// Fast-math-flags propagate from the original induction instruction.
20342024
IRBuilder<>::FastMathFlagGuard FMFG(State.Builder);
20352025
if (hasFastMathFlags())
@@ -2223,7 +2213,6 @@ static Type *getGEPIndexTy(bool IsScalable, bool IsReverse,
22232213

22242214
void VPVectorEndPointerRecipe::execute(VPTransformState &State) {
22252215
auto &Builder = State.Builder;
2226-
State.setDebugLocFrom(getDebugLoc());
22272216
unsigned CurrentPart = getUnrollPart(*this);
22282217
Type *IndexTy = getGEPIndexTy(State.VF.isScalable(), /*IsReverse*/ true,
22292218
CurrentPart, Builder);
@@ -2259,7 +2248,6 @@ void VPVectorEndPointerRecipe::print(raw_ostream &O, const Twine &Indent,
22592248

22602249
void VPVectorPointerRecipe::execute(VPTransformState &State) {
22612250
auto &Builder = State.Builder;
2262-
State.setDebugLocFrom(getDebugLoc());
22632251
unsigned CurrentPart = getUnrollPart(*this);
22642252
Type *IndexTy = getGEPIndexTy(State.VF.isScalable(), /*IsReverse*/ false,
22652253
CurrentPart, Builder);
@@ -2285,7 +2273,6 @@ void VPVectorPointerRecipe::print(raw_ostream &O, const Twine &Indent,
22852273

22862274
void VPBlendRecipe::execute(VPTransformState &State) {
22872275
assert(isNormalized() && "Expected blend to be normalized!");
2288-
State.setDebugLocFrom(getDebugLoc());
22892276
// We know that all PHIs in non-header blocks are converted into
22902277
// selects, so we don't have to worry about the insertion order and we
22912278
// can just use the builder.
@@ -2367,7 +2354,6 @@ void VPReductionRecipe::execute(VPTransformState &State) {
23672354
// Propagate the fast-math flags carried by the underlying instruction.
23682355
IRBuilderBase::FastMathFlagGuard FMFGuard(State.Builder);
23692356
State.Builder.setFastMathFlags(getFastMathFlags());
2370-
State.setDebugLocFrom(getDebugLoc());
23712357
Value *NewVecOp = State.get(getVecOp());
23722358
if (VPValue *Cond = getCondOp()) {
23732359
Value *NewCond = State.get(Cond, State.VF.isScalar());
@@ -2570,7 +2556,6 @@ void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent,
25702556
#endif
25712557

25722558
Value *VPScalarCastRecipe ::generate(VPTransformState &State) {
2573-
State.setDebugLocFrom(getDebugLoc());
25742559
assert(vputils::onlyFirstLaneUsed(this) &&
25752560
"Codegen only implemented for first lane.");
25762561
switch (Opcode) {
@@ -2602,7 +2587,6 @@ void VPScalarCastRecipe ::print(raw_ostream &O, const Twine &Indent,
26022587
#endif
26032588

26042589
void VPBranchOnMaskRecipe::execute(VPTransformState &State) {
2605-
State.setDebugLocFrom(getDebugLoc());
26062590
assert(State.Lane && "Branch on Mask works only on single instance.");
26072591

26082592
VPValue *BlockInMask = getOperand(0);
@@ -2628,7 +2612,6 @@ InstructionCost VPBranchOnMaskRecipe::computeCost(ElementCount VF,
26282612
}
26292613

26302614
void VPPredInstPHIRecipe::execute(VPTransformState &State) {
2631-
State.setDebugLocFrom(getDebugLoc());
26322615
assert(State.Lane && "Predicated instruction PHI works per instance.");
26332616
Instruction *ScalarPredInst =
26342617
cast<Instruction>(State.get(getOperand(0), *State.Lane));
@@ -2734,7 +2717,6 @@ void VPWidenLoadRecipe::execute(VPTransformState &State) {
27342717
bool CreateGather = !isConsecutive();
27352718

27362719
auto &Builder = State.Builder;
2737-
State.setDebugLocFrom(getDebugLoc());
27382720
Value *Mask = nullptr;
27392721
if (auto *VPMask = getMask()) {
27402722
// Mask reversal is only needed for non-all-one (null) masks, as reverse
@@ -2793,7 +2775,6 @@ void VPWidenLoadEVLRecipe::execute(VPTransformState &State) {
27932775
bool CreateGather = !isConsecutive();
27942776

27952777
auto &Builder = State.Builder;
2796-
State.setDebugLocFrom(getDebugLoc());
27972778
CallInst *NewLI;
27982779
Value *EVL = State.get(getEVL(), VPLane(0));
27992780
Value *Addr = State.get(getAddr(), !CreateGather);
@@ -2868,7 +2849,6 @@ void VPWidenStoreRecipe::execute(VPTransformState &State) {
28682849
const Align Alignment = getLoadStoreAlignment(&Ingredient);
28692850

28702851
auto &Builder = State.Builder;
2871-
State.setDebugLocFrom(getDebugLoc());
28722852

28732853
Value *Mask = nullptr;
28742854
if (auto *VPMask = getMask()) {
@@ -2914,7 +2894,6 @@ void VPWidenStoreEVLRecipe::execute(VPTransformState &State) {
29142894
const Align Alignment = getLoadStoreAlignment(&Ingredient);
29152895

29162896
auto &Builder = State.Builder;
2917-
State.setDebugLocFrom(getDebugLoc());
29182897

29192898
CallInst *NewSI = nullptr;
29202899
Value *StoredVal = State.get(StoredValue);
@@ -3717,7 +3696,6 @@ void VPWidenPHIRecipe::execute(VPTransformState &State) {
37173696
assert(EnableVPlanNativePath &&
37183697
"Non-native vplans are not expected to have VPWidenPHIRecipes.");
37193698

3720-
State.setDebugLocFrom(getDebugLoc());
37213699
Value *Op0 = State.get(getOperand(0));
37223700
Type *VecTy = Op0->getType();
37233701
Value *VecPhi = State.Builder.CreatePHI(VecTy, 2, Name);
@@ -3743,7 +3721,6 @@ void VPActiveLaneMaskPHIRecipe::execute(VPTransformState &State) {
37433721
PHINode *Phi =
37443722
State.Builder.CreatePHI(StartMask->getType(), 2, "active.lane.mask");
37453723
Phi->addIncoming(StartMask, VectorPH);
3746-
Phi->setDebugLoc(getDebugLoc());
37473724
State.set(this, Phi);
37483725
}
37493726

‎llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll‎

Lines changed: 44 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -15,23 +15,23 @@ define void @foo(ptr %h) !dbg !4 {
1515
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[FOR_COND_CLEANUP32:%.*]] ]
1616
; CHECK-NEXT: br label [[FOR_COND5_PREHEADER1:%.*]], !dbg [[DBG21]]
1717
; CHECK: for.cond5.preheader1:
18-
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, [[VECTOR_BODY]] ], [ [[TMP4:%.*]], [[FOR_COND5_PREHEADER1]] ], !dbg [[DBG34:![0-9]+]]
18+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, [[VECTOR_BODY]] ], [ [[TMP4:%.*]], [[FOR_COND5_PREHEADER1]] ], !dbg [[DBG22:![0-9]+]]
1919
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[H]], <4 x i64> [[VEC_PHI]]
20-
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> zeroinitializer, <4 x ptr> [[TMP0]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG22:![0-9]+]]
21-
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, <4 x ptr> [[TMP0]], i64 1, !dbg [[DBG22]]
22-
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> splat (i32 1), <4 x ptr> [[TMP1]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG22]]
23-
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, <4 x ptr> [[TMP0]], i64 2, !dbg [[DBG22]]
24-
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> splat (i32 2), <4 x ptr> [[TMP2]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG22]]
25-
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, <4 x ptr> [[TMP0]], i64 3, !dbg [[DBG22]]
26-
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> splat (i32 3), <4 x ptr> [[TMP3]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG22]]
27-
; CHECK-NEXT: [[TMP4]] = add nuw nsw <4 x i64> [[VEC_PHI]], splat (i64 1), !dbg [[DBG24:![0-9]+]]
28-
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <4 x i64> [[TMP4]], splat (i64 5), !dbg [[DBG25:![0-9]+]]
29-
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP5]], i32 0, !dbg [[DBG26:![0-9]+]]
30-
; CHECK-NEXT: br i1 [[TMP6]], label [[FOR_COND_CLEANUP32]], label [[FOR_COND5_PREHEADER1]], !dbg [[DBG26]]
20+
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> zeroinitializer, <4 x ptr> [[TMP0]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG23:![0-9]+]]
21+
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, <4 x ptr> [[TMP0]], i64 1, !dbg [[DBG25:![0-9]+]]
22+
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> splat (i32 1), <4 x ptr> [[TMP1]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG23]]
23+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, <4 x ptr> [[TMP0]], i64 2, !dbg [[DBG25]]
24+
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> splat (i32 2), <4 x ptr> [[TMP2]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG23]]
25+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, <4 x ptr> [[TMP0]], i64 3, !dbg [[DBG25]]
26+
; CHECK-NEXT: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> splat (i32 3), <4 x ptr> [[TMP3]], i32 4, <4 x i1> splat (i1 true)), !dbg [[DBG23]]
27+
; CHECK-NEXT: [[TMP4]] = add nuw nsw <4 x i64> [[VEC_PHI]], splat (i64 1), !dbg [[DBG26:![0-9]+]]
28+
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <4 x i64> [[TMP4]], splat (i64 5), !dbg [[DBG27:![0-9]+]]
29+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP5]], i32 0, !dbg [[DBG28:![0-9]+]]
30+
; CHECK-NEXT: br i1 [[TMP6]], label [[FOR_COND_CLEANUP32]], label [[FOR_COND5_PREHEADER1]], !dbg [[DBG28]]
3131
; CHECK: vector.latch:
3232
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
3333
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 20
34-
; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP27:![0-9]+]]
34+
; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP29:![0-9]+]]
3535
; CHECK: middle.block:
3636
; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]], !dbg [[DBG21]]
3737
; CHECK: scalar.ph:
@@ -40,27 +40,27 @@ define void @foo(ptr %h) !dbg !4 {
4040
; CHECK: for.cond1.preheader:
4141
; CHECK-NEXT: [[I_023:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC13:%.*]], [[FOR_COND_CLEANUP3:%.*]] ]
4242
; CHECK-NEXT: #dbg_value(i64 [[I_023]], [[META11]], !DIExpression(), [[META20]])
43-
; CHECK-NEXT: br label [[FOR_COND5_PREHEADER:%.*]], !dbg [[DBG26]]
43+
; CHECK-NEXT: br label [[FOR_COND5_PREHEADER:%.*]], !dbg [[DBG28]]
4444
; CHECK: for.cond5.preheader:
45-
; CHECK-NEXT: [[L_022:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER]] ], [ [[INC10:%.*]], [[FOR_COND5_PREHEADER]] ], !dbg [[DBG34]]
45+
; CHECK-NEXT: [[L_022:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER]] ], [ [[INC10:%.*]], [[FOR_COND5_PREHEADER]] ], !dbg [[DBG22]]
4646
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[H]], i64 [[L_022]]
47-
; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 4, !dbg [[DBG22]]
48-
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, ptr [[TMP10]], i64 1, !dbg [[DBG31:![0-9]+]]
49-
; CHECK-NEXT: store i32 1, ptr [[ARRAYIDX_1]], align 4, !dbg [[DBG22]]
50-
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, ptr [[TMP10]], i64 2, !dbg [[DBG31]]
51-
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX_2]], align 4, !dbg [[DBG22]]
52-
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr i32, ptr [[TMP10]], i64 3, !dbg [[DBG31]]
53-
; CHECK-NEXT: store i32 3, ptr [[ARRAYIDX_3]], align 4, !dbg [[DBG22]]
54-
; CHECK-NEXT: [[INC10]] = add nuw nsw i64 [[L_022]], 1, !dbg [[DBG24]]
55-
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC10]], 5, !dbg [[DBG25]]
56-
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_COND5_PREHEADER]], !dbg [[DBG26]]
47+
; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 4, !dbg [[DBG23]]
48+
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, ptr [[TMP10]], i64 1, !dbg [[DBG25]]
49+
; CHECK-NEXT: store i32 1, ptr [[ARRAYIDX_1]], align 4, !dbg [[DBG23]]
50+
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, ptr [[TMP10]], i64 2, !dbg [[DBG25]]
51+
; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX_2]], align 4, !dbg [[DBG23]]
52+
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr i32, ptr [[TMP10]], i64 3, !dbg [[DBG25]]
53+
; CHECK-NEXT: store i32 3, ptr [[ARRAYIDX_3]], align 4, !dbg [[DBG23]]
54+
; CHECK-NEXT: [[INC10]] = add nuw nsw i64 [[L_022]], 1, !dbg [[DBG26]]
55+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC10]], 5, !dbg [[DBG27]]
56+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_COND5_PREHEADER]], !dbg [[DBG28]]
5757
; CHECK: for.cond.cleanup3:
58-
; CHECK-NEXT: [[INC13]] = add nuw nsw i64 [[I_023]], 1, !dbg [[DBG32:![0-9]+]]
58+
; CHECK-NEXT: [[INC13]] = add nuw nsw i64 [[I_023]], 1, !dbg [[DBG33:![0-9]+]]
5959
; CHECK-NEXT: #dbg_value(i64 [[INC13]], [[META11]], !DIExpression(), [[META20]])
60-
; CHECK-NEXT: [[EXITCOND24_NOT:%.*]] = icmp eq i64 [[INC13]], 23, !dbg [[DBG33:![0-9]+]]
61-
; CHECK-NEXT: br i1 [[EXITCOND24_NOT]], label [[EXIT]], label [[FOR_COND1_PREHEADER]], !dbg [[DBG21]], !llvm.loop [[LOOP34:![0-9]+]]
60+
; CHECK-NEXT: [[EXITCOND24_NOT:%.*]] = icmp eq i64 [[INC13]], 23, !dbg [[DBG34:![0-9]+]]
61+
; CHECK-NEXT: br i1 [[EXITCOND24_NOT]], label [[EXIT]], label [[FOR_COND1_PREHEADER]], !dbg [[DBG21]], !llvm.loop [[LOOP35:![0-9]+]]
6262
; CHECK: exit:
63-
; CHECK-NEXT: ret void, !dbg [[DBG35:![0-9]+]]
63+
; CHECK-NEXT: ret void, !dbg [[DBG36:![0-9]+]]
6464
;
6565
entry:
6666
call void @llvm.dbg.value(metadata i64 0, metadata !11, metadata !DIExpression()), !dbg !20
@@ -156,18 +156,19 @@ declare void @llvm.dbg.value(metadata, metadata, metadata)
156156
; CHECK: [[META19]] = distinct !DILexicalBlock(scope: [[META15]], file: [[META1]], line: 11, column: 5)
157157
; CHECK: [[META20]] = !DILocation(line: 0, scope: [[META12]])
158158
; CHECK: [[DBG21]] = !DILocation(line: 10, column: 3, scope: [[META12]])
159-
; CHECK: [[DBG22]] = !DILocation(line: 13, column: 11, scope: [[META23:![0-9]+]])
160-
; CHECK: [[META23]] = distinct !DILexicalBlock(scope: [[META18]], file: [[META1]], line: 12, column: 7)
161-
; CHECK: [[DBG24]] = !DILocation(line: 11, column: 32, scope: [[META19]])
162-
; CHECK: [[DBG25]] = !DILocation(line: 11, column: 26, scope: [[META19]])
163-
; CHECK: [[DBG26]] = !DILocation(line: 11, column: 5, scope: [[META15]])
164-
; CHECK: [[LOOP27]] = distinct !{[[LOOP27]], [[DBG21]], [[META28:![0-9]+]], [[META29:![0-9]+]], [[META30:![0-9]+]]}
165-
; CHECK: [[META28]] = !DILocation(line: 13, column: 13, scope: [[META12]])
166-
; CHECK: [[META29]] = !{!"llvm.loop.isvectorized", i32 1}
167-
; CHECK: [[META30]] = !{!"llvm.loop.unroll.runtime.disable"}
168-
; CHECK: [[DBG31]] = !DILocation(line: 13, column: 2, scope: [[META23]])
169-
; CHECK: [[DBG32]] = !DILocation(line: 10, column: 30, scope: [[META16]])
170-
; CHECK: [[DBG33]] = !DILocation(line: 10, column: 24, scope: [[META16]])
171-
; CHECK: [[LOOP34]] = distinct !{[[LOOP34]], [[DBG21]], [[META28]], [[META29]]}
172-
; CHECK: [[DBG35]] = !DILocation(line: 14, column: 1, scope: [[DBG4]])
159+
; CHECK: [[DBG22]] = !DILocation(line: 10, column: 5, scope: [[META12]])
160+
; CHECK: [[DBG23]] = !DILocation(line: 13, column: 11, scope: [[META24:![0-9]+]])
161+
; CHECK: [[META24]] = distinct !DILexicalBlock(scope: [[META18]], file: [[META1]], line: 12, column: 7)
162+
; CHECK: [[DBG25]] = !DILocation(line: 13, column: 2, scope: [[META24]])
163+
; CHECK: [[DBG26]] = !DILocation(line: 11, column: 32, scope: [[META19]])
164+
; CHECK: [[DBG27]] = !DILocation(line: 11, column: 26, scope: [[META19]])
165+
; CHECK: [[DBG28]] = !DILocation(line: 11, column: 5, scope: [[META15]])
166+
; CHECK: [[LOOP29]] = distinct !{[[LOOP29]], [[DBG21]], [[META30:![0-9]+]], [[META31:![0-9]+]], [[META32:![0-9]+]]}
167+
; CHECK: [[META30]] = !DILocation(line: 13, column: 13, scope: [[META12]])
168+
; CHECK: [[META31]] = !{!"llvm.loop.isvectorized", i32 1}
169+
; CHECK: [[META32]] = !{!"llvm.loop.unroll.runtime.disable"}
170+
; CHECK: [[DBG33]] = !DILocation(line: 10, column: 30, scope: [[META16]])
171+
; CHECK: [[DBG34]] = !DILocation(line: 10, column: 24, scope: [[META16]])
172+
; CHECK: [[LOOP35]] = distinct !{[[LOOP35]], [[DBG21]], [[META30]], [[META31]]}
173+
; CHECK: [[DBG36]] = !DILocation(line: 14, column: 1, scope: [[DBG4]])
173174
;.

‎llvm/test/Transforms/LoopVectorize/debugloc.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,8 +67,8 @@ define i32 @test_debug_loc_on_branch_in_loop(ptr noalias %src, ptr noalias %dst)
6767
; CHECK-NEXT: br i1 [[EXT]], label %pred.store.if, label %pred.store.continue, !dbg [[LOC3]]
6868
; CHECK-EMPTY:
6969
; CHECK-NEXT: pred.store.if:
70-
; CHECK-NEXT: [[GEP:%.+]] = getelementptr inbounds i32, ptr %dst, i64 {{.+}}, !dbg [[LOC3]]
71-
; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4, !dbg [[LOC3]]
70+
; CHECK-NEXT: [[GEP:%.+]] = getelementptr inbounds i32, ptr %dst, i64 {{.+}}
71+
; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
7272
; CHECK-NEXT: br label %pred.store.continue, !dbg [[LOC3]]
7373
; CHECK-EMPTY:
7474
;
@@ -107,7 +107,7 @@ define i32 @test_different_debug_loc_on_replicate_recipe(ptr noalias %src, ptr n
107107
; CHECK-EMPTY:
108108
; CHECK-NEXT: pred.store.if:
109109
; CHECK-NEXT: [[GEP:%.+]] = getelementptr inbounds i32, ptr %dst, i64 {{.+}}, !dbg [[LOC5:!.+]]
110-
; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4, !dbg [[LOC5]]
110+
; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
111111
; CHECK-NEXT: br label %pred.store.continue, !dbg [[LOC4]]
112112
; CHECK-EMPTY:
113113
;

‎llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -636,8 +636,8 @@ define void @pr30172(ptr nocapture %asd, ptr nocapture %bsd) !dbg !5 {;
636636
; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = icmp slt i32 [[TMP5]], 100
637637
; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = xor i1 [[TMP12]], true, !dbg [[DBG34:![0-9]+]]
638638
; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = xor i1 [[TMP13]], true, !dbg [[DBG34]]
639-
; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP4]], 200, !dbg [[DBG34]]
640-
; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP5]], 200, !dbg [[DBG34]]
639+
; UNROLL-NO-VF-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP4]], 200
640+
; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP5]], 200
641641
; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], i1 [[TMP15]], i1 false, !dbg [[DBG35:![0-9]+]]
642642
; UNROLL-NO-VF-NEXT: [[TMP19:%.*]] = select i1 [[TMP14]], i1 [[TMP16]], i1 false, !dbg [[DBG35]]
643643
; UNROLL-NO-VF-NEXT: [[TMP20:%.*]] = or i1 [[TMP18]], [[TMP12]]

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