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[CIR] Added support for __builtin_ia32_pshufd (#1861)
## Summary This PR implements support for the `__builtin_ia32_pshufd` SIMD intrinsic in ClangIR, which was previously unimplemented and causing compilation failures. ## Problem The `__builtin_ia32_pshufd` intrinsic (used by `_mm_shuffle_epi32`) was hitting an `NYI` error, preventing compilation of code that uses common SIMD operations.
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‎clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp‎

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@@ -25,6 +25,7 @@
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#include "clang/Basic/TargetBuiltins.h"
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#include "clang/CIR/Dialect/IR/CIRDialect.h"
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#include "clang/CIR/Dialect/IR/CIRTypes.h"
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#include "llvm/ADT/TypeSwitch.h"
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#include "llvm/IR/IntrinsicsX86.h"
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#include "llvm/Support/ErrorHandling.h"
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@@ -1046,8 +1047,38 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
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case X86::BI__builtin_ia32_vpermilpd256:
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case X86::BI__builtin_ia32_vpermilps256:
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case X86::BI__builtin_ia32_vpermilpd512:
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case X86::BI__builtin_ia32_vpermilps512:
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llvm_unreachable("pshufd NYI");
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case X86::BI__builtin_ia32_vpermilps512: {
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uint32_t imm = getIntValueFromConstOp(Ops[1]);
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auto vecTy = cast<cir::VectorType>(Ops[0].getType());
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unsigned numElts = vecTy.getSize();
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auto eltTy = vecTy.getElementType();
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assert(isSized(eltTy) && "Element type must be a sized type");
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unsigned eltBitWidth =
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llvm::TypeSwitch<mlir::Type, unsigned>(eltTy)
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.Case<cir::IntType>([](auto intTy) { return intTy.getWidth(); })
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.Case<cir::SingleType>([](auto) { return 32; })
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.Case<cir::DoubleType>([](auto) { return 64; })
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.Default([](auto) {
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llvm_unreachable("NYI: Unsupported type");
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return 0;
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});
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unsigned vecBitWidth = numElts * eltBitWidth;
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unsigned numLanes = vecBitWidth / 128;
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unsigned numLaneElts = numElts / numLanes;
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imm = (imm & 0xff) * 0x01010101;
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llvm::SmallVector<int64_t, 16> indices;
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for (unsigned l = 0; l != numElts; l += numLaneElts) {
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for (unsigned i = 0; i != numLaneElts; ++i) {
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indices.push_back((imm % numLaneElts) + l);
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imm /= numLaneElts;
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}
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}
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return builder.createVecShuffle(getLoc(E->getExprLoc()), Ops[0], indices);
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}
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case X86::BI__builtin_ia32_shufpd:
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case X86::BI__builtin_ia32_shufpd256:
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case X86::BI__builtin_ia32_shufpd512:

‎clang/test/CIR/CodeGen/builtin-x86-pshufd.cpp‎

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// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir
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// RUN: FileCheck --input-file=%t.cir %s
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// Test that __builtin_ia32_pshufd and __builtin_ia32_vpermilp generates correct CIR vec.shuffle operations
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// This verifies the fix for SIMD intrinsic support that was previously NYI
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typedef int __v4si __attribute__((__vector_size__(16)));
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typedef float __v4sf __attribute__((__vector_size__(16)));
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typedef double __v2df __attribute__((__vector_size__(16)));
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typedef float __v8sf __attribute__((__vector_size__(32)));
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typedef double __v4df __attribute__((__vector_size__(32)));
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typedef float __v16sf __attribute__((__vector_size__(64)));
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typedef double __v8df __attribute__((__vector_size__(64)));
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typedef __v4si __m128i;
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typedef __v4sf __m128;
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typedef __v2df __m128d;
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typedef __v8sf __m256;
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typedef __v4df __m256d;
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typedef __v16sf __m512;
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typedef __v8df __m512d;
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// CHECK-LABEL: @_Z11test_pshufdv
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void test_pshufd() {
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__m128i vec = {1, 2, 3, 4};
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s32i x 4>) [#cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<!s32i x 4>
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__m128i result = __builtin_ia32_pshufd(vec, 0x4E);
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}
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// CHECK-LABEL: @_Z19test_different_maskv
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void test_different_mask() {
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__m128i vec = {10, 20, 30, 40};
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// Test different immediate value: 0x1B = 00011011 = [3,2,1,0] reversed
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s32i x 4>) [#cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<1> : !s32i, #cir.int<0> : !s32i] : !cir.vector<!s32i x 4>
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__m128i result = __builtin_ia32_pshufd(vec, 0x1B);
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}
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// CHECK-LABEL: @_Z9test_casev
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void test_case() {
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__m128i p0 = {1, 2, 3, 4};
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// This reproduces the exact pattern from stb_image.h:2685 that was failing:
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// _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p0, 0x4e));
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// Which expands to: __builtin_ia32_pshufd(p0, 0x4e)
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s32i x 4>) [#cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<!s32i x 4>
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__m128i out_vec = __builtin_ia32_pshufd(p0, 0x4e);
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}
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// CHECK-LABEL: @_Z15test_vpermilps4v
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void test_vpermilps4() {
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__m128 vec = {1.0f, 2.0f, 3.0f, 4.0f};
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// vpermilps with immediate 0x4E = 01001110 = [1,3,2,0] for 4 elements
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.float x 4>) [#cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<!cir.float x 4>
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__m128 result = __builtin_ia32_vpermilps(vec, 0x4E);
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}
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// CHECK-LABEL: @_Z15test_vpermilpd2v
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void test_vpermilpd2() {
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__m128d vec = {1.0, 2.0};
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// vpermilpd with immediate 0x1 = 01 = [1,0] for 2 elements
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.double x 2>) [#cir.int<1> : !s32i, #cir.int<0> : !s32i] : !cir.vector<!cir.double x 2>
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__m128d result = __builtin_ia32_vpermilpd(vec, 0x1);
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}
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// CHECK-LABEL: @_Z17test_vpermilps256v
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void test_vpermilps256() {
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__m256 vec = {1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f};
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// vpermilps256 with immediate 0x1B = 00011011 = [3,2,1,0] for each 128-bit lane
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.float x 8>) [#cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<1> : !s32i, #cir.int<0> : !s32i, #cir.int<7> : !s32i, #cir.int<6> : !s32i, #cir.int<5> : !s32i, #cir.int<4> : !s32i] : !cir.vector<!cir.float x 8>
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__m256 result = __builtin_ia32_vpermilps256(vec, 0x1B);
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}
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// CHECK-LABEL: @_Z17test_vpermilpd256v
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void test_vpermilpd256() {
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__m256d vec = {1.0, 2.0, 3.0, 4.0};
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// vpermilpd256 with immediate 0x5 = 0101 = [1,0,1,0] for 4 elements
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.double x 4>) [#cir.int<1> : !s32i, #cir.int<0> : !s32i, #cir.int<3> : !s32i, #cir.int<2> : !s32i] : !cir.vector<!cir.double x 4>
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__m256d result = __builtin_ia32_vpermilpd256(vec, 0x5);
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}
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// CHECK-LABEL: @_Z17test_vpermilps512v
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void test_vpermilps512() {
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__m512 vec = {1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f,
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9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f};
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// vpermilps512 with immediate 0x4E = 01001110 = [1,3,2,0] for each 128-bit lane
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.float x 16>) [#cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i] : !cir.vector<!cir.float x 16>
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__m512 result = __builtin_ia32_vpermilps512(vec, 0x4E);
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}
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// CHECK-LABEL: @_Z17test_vpermilpd512v
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void test_vpermilpd512() {
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__m512d vec = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0};
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// vpermilpd512 with immediate 0x55 = 01010101 = [1,0,1,0,1,0,1,0] for 8 elements
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.double x 8>) [#cir.int<1> : !s32i, #cir.int<0> : !s32i, #cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<5> : !s32i, #cir.int<4> : !s32i, #cir.int<7> : !s32i, #cir.int<6> : !s32i] : !cir.vector<!cir.double x 8>
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__m512d result = __builtin_ia32_vpermilpd512(vec, 0x55);
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}
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// Test different immediate values
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// CHECK-LABEL: @_Z24test_vpermilps_differentv
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void test_vpermilps_different() {
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__m128 vec = {10.0f, 20.0f, 30.0f, 40.0f};
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// Test different immediate value: 0x1B = 00011011 = [3,2,1,0] reversed
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.float x 4>) [#cir.int<3> : !s32i, #cir.int<2> : !s32i, #cir.int<1> : !s32i, #cir.int<0> : !s32i] : !cir.vector<!cir.float x 4>
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__m128 result = __builtin_ia32_vpermilps(vec, 0x1B);
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}
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// CHECK-LABEL: @_Z24test_vpermilpd_differentv
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void test_vpermilpd_different() {
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__m128d vec = {100.0, 200.0};
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// Test immediate 0x0 = 00 = [0,0] - duplicate first element
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// CHECK: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!cir.double x 2>) [#cir.int<0> : !s32i, #cir.int<0> : !s32i] : !cir.vector<!cir.double x 2>
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__m128d result = __builtin_ia32_vpermilpd(vec, 0x0);
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}

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