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[CIR] Added support for __builtin_ia32_pslldqi_byteshift (#1883)
**Related Issue**: #1880
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‎clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp‎

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -158,6 +158,49 @@ static mlir::Value emitX86SExtMask(CIRGenFunction &cgf, mlir::Value op,
158158
return cgf.getBuilder().createCast(loc, cir::CastKind::integral, mask, dstTy);
159159
}
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161+
static mlir::Value emitX86PSLLDQIByteShift(CIRGenFunction &cgf,
162+
const CallExpr *E,
163+
ArrayRef<mlir::Value> Ops) {
164+
auto &builder = cgf.getBuilder();
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unsigned shiftVal = getIntValueFromConstOp(Ops[1]) & 0xff;
166+
auto loc = cgf.getLoc(E->getExprLoc());
167+
auto resultType = cast<cir::VectorType>(Ops[0].getType());
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// If pslldq is shifting the vector more than 15 bytes, emit zero.
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// This matches the hardware behavior where shifting by 16+ bytes
171+
// clears the entire 128-bit lane.
172+
if (shiftVal >= 16)
173+
return builder.getZero(loc, resultType);
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// Builtin type is vXi64 so multiply by 8 to get bytes.
176+
unsigned numElts = resultType.getSize() * 8;
177+
assert(numElts % 16 == 0 && "Vector size must be multiple of 16 bytes");
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llvm::SmallVector<int64_t, 64> indices;
180+
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// 256/512-bit pslldq operates on 128-bit lanes so we need to handle that
182+
for (unsigned l = 0; l < numElts; l += 16) {
183+
for (unsigned i = 0; i != 16; ++i) {
184+
unsigned idx = numElts + i - shiftVal;
185+
if (idx < numElts)
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idx -= numElts - 16; // end of lane, switch operand.
187+
indices.push_back(idx + l);
188+
}
189+
}
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// Cast to byte vector for shuffle operation
192+
auto byteVecTy = cir::VectorType::get(builder.getSInt8Ty(), numElts);
193+
mlir::Value byteCast = builder.createBitcast(Ops[0], byteVecTy);
194+
mlir::Value zero = builder.getZero(loc, byteVecTy);
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// Perform the shuffle (left shift by inserting zeros)
197+
mlir::Value shuffleResult =
198+
builder.createVecShuffle(loc, zero, byteCast, indices);
199+
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// Cast back to original type
201+
return builder.createBitcast(shuffleResult, resultType);
202+
}
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161204
mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
162205
const CallExpr *E) {
163206
if (BuiltinID == Builtin::BI__builtin_cpu_is)
@@ -1108,7 +1151,7 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
11081151
case X86::BI__builtin_ia32_pslldqi128_byteshift:
11091152
case X86::BI__builtin_ia32_pslldqi256_byteshift:
11101153
case X86::BI__builtin_ia32_pslldqi512_byteshift:
1111-
llvm_unreachable("pslldqi NYI");
1154+
return emitX86PSLLDQIByteShift(*this, E, Ops);
11121155
case X86::BI__builtin_ia32_psrldqi128_byteshift:
11131156
case X86::BI__builtin_ia32_psrldqi256_byteshift:
11141157
case X86::BI__builtin_ia32_psrldqi512_byteshift:

‎clang/test/CIR/CodeGen/builtin-x86-pslldqi.cpp‎

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,177 @@
1+
// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir -target-feature +avx512f -target-feature +avx512bw
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// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR
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// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll -target-feature +avx512f -target-feature +avx512bw
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// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM
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// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.og.ll -target-feature +avx512f -target-feature +avx512bw
6+
// RUN: FileCheck --input-file=%t.og.ll %s -check-prefix=OGCG
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// Tests PSLLDQI byte shift intrinsics implementation in ClangIR
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// Compares CIR emission, LLVM lowering, and original CodeGen output
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typedef long long __m128i __attribute__((__vector_size__(16)));
12+
typedef long long __m256i __attribute__((__vector_size__(32)));
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typedef long long __m512i __attribute__((__vector_size__(64)));
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// Declare the builtins directly
16+
extern __m128i __builtin_ia32_pslldqi128_byteshift(__m128i, int);
17+
extern __m256i __builtin_ia32_pslldqi256_byteshift(__m256i, int);
18+
extern __m512i __builtin_ia32_pslldqi512_byteshift(__m512i, int);
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// ============================================================================
21+
// Core Functionality Tests
22+
// ============================================================================
23+
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// CIR-LABEL: @_Z22test_pslldqi128_shift4Dv2_x
25+
// LLVM-LABEL: @_Z22test_pslldqi128_shift4Dv2_x
26+
// OGCG-LABEL: @_Z22test_pslldqi128_shift4Dv2_x
27+
__m128i test_pslldqi128_shift4(__m128i a) {
28+
// Should shift left by 4 bytes, filling with zeros
29+
// CIR: %{{.*}} = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<16> : !s32i, #cir.int<17> : !s32i, #cir.int<18> : !s32i, #cir.int<19> : !s32i, #cir.int<20> : !s32i, #cir.int<21> : !s32i, #cir.int<22> : !s32i, #cir.int<23> : !s32i, #cir.int<24> : !s32i, #cir.int<25> : !s32i, #cir.int<26> : !s32i, #cir.int<27> : !s32i] : !cir.vector<!s8i x 16>
30+
// LLVM: %{{.*}} = shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
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// OGCG: %{{.*}} = shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
32+
return __builtin_ia32_pslldqi128_byteshift(a, 4);
33+
}
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// CIR-LABEL: @_Z22test_pslldqi128_shift0Dv2_x
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// LLVM-LABEL: @_Z22test_pslldqi128_shift0Dv2_x
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// OGCG-LABEL: @_Z22test_pslldqi128_shift0Dv2_x
38+
__m128i test_pslldqi128_shift0(__m128i a) {
39+
// Should return input unchanged (shift by 0)
40+
// CIR: %{{.*}} = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<16> : !s32i, #cir.int<17> : !s32i, #cir.int<18> : !s32i, #cir.int<19> : !s32i, #cir.int<20> : !s32i, #cir.int<21> : !s32i, #cir.int<22> : !s32i, #cir.int<23> : !s32i, #cir.int<24> : !s32i, #cir.int<25> : !s32i, #cir.int<26> : !s32i, #cir.int<27> : !s32i, #cir.int<28> : !s32i, #cir.int<29> : !s32i, #cir.int<30> : !s32i, #cir.int<31> : !s32i] : !cir.vector<!s8i x 16>
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// LLVM: %{{.*}} = shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
42+
// OGCG: %{{.*}} = shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
43+
return __builtin_ia32_pslldqi128_byteshift(a, 0);
44+
}
45+
46+
// CIR-LABEL: @_Z23test_pslldqi128_shift16Dv2_x
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// LLVM-LABEL: @_Z23test_pslldqi128_shift16Dv2_x
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// OGCG-LABEL: @_Z23test_pslldqi128_shift16Dv2_x
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__m128i test_pslldqi128_shift16(__m128i a) {
50+
// Entire vector shifted out, should return zero
51+
// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 2>
52+
// LLVM: store <2 x i64> zeroinitializer, ptr %{{.*}}, align 16
53+
// OGCG: ret <2 x i64> zeroinitializer
54+
return __builtin_ia32_pslldqi128_byteshift(a, 16);
55+
}
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// ============================================================================
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// 256-bit Tests (Two Independent 128-bit Lanes)
59+
// ============================================================================
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// CIR-LABEL: @_Z22test_pslldqi256_shift4Dv4_x
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// LLVM-LABEL: @_Z22test_pslldqi256_shift4Dv4_x
63+
// OGCG-LABEL: @_Z22test_pslldqi256_shift4Dv4_x
64+
__m256i test_pslldqi256_shift4(__m256i a) {
65+
// Each 128-bit lane shifts independently by 4 bytes
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// CIR: %{{.*}} = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 32>) [#cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<32> : !s32i, #cir.int<33> : !s32i, #cir.int<34> : !s32i, #cir.int<35> : !s32i, #cir.int<36> : !s32i, #cir.int<37> : !s32i, #cir.int<38> : !s32i, #cir.int<39> : !s32i, #cir.int<40> : !s32i, #cir.int<41> : !s32i, #cir.int<42> : !s32i, #cir.int<43> : !s32i, #cir.int<28> : !s32i, #cir.int<29> : !s32i, #cir.int<30> : !s32i, #cir.int<31> : !s32i, #cir.int<48> : !s32i, #cir.int<49> : !s32i, #cir.int<50> : !s32i, #cir.int<51> : !s32i, #cir.int<52> : !s32i, #cir.int<53> : !s32i, #cir.int<54> : !s32i, #cir.int<55> : !s32i, #cir.int<56> : !s32i, #cir.int<57> : !s32i, #cir.int<58> : !s32i, #cir.int<59> : !s32i] : !cir.vector<!s8i x 32>
67+
// LLVM: %{{.*}} = shufflevector <32 x i8> zeroinitializer, <32 x i8> %{{.*}}, <32 x i32> <i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59>
68+
// OGCG: %{{.*}} = shufflevector <32 x i8> zeroinitializer, <32 x i8> %{{.*}}, <32 x i32> <i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59>
69+
return __builtin_ia32_pslldqi256_byteshift(a, 4);
70+
}
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// CIR-LABEL: @_Z23test_pslldqi256_shift16Dv4_x
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// LLVM-LABEL: @_Z23test_pslldqi256_shift16Dv4_x
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// OGCG-LABEL: @_Z23test_pslldqi256_shift16Dv4_x
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__m256i test_pslldqi256_shift16(__m256i a) {
76+
// Both lanes completely shifted out, returns zero
77+
// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 4>
78+
// LLVM: store <4 x i64> zeroinitializer, ptr %{{.*}}, align 32
79+
// OGCG: ret <4 x i64> zeroinitializer
80+
return __builtin_ia32_pslldqi256_byteshift(a, 16);
81+
}
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// ============================================================================
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// 512-bit Tests (Four Independent 128-bit Lanes)
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// ============================================================================
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// CIR-LABEL: @_Z22test_pslldqi512_shift4Dv8_x
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// LLVM-LABEL: @_Z22test_pslldqi512_shift4Dv8_x
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// OGCG-LABEL: @_Z22test_pslldqi512_shift4Dv8_x
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__m512i test_pslldqi512_shift4(__m512i a) {
91+
// All 4 lanes shift independently by 4 bytes
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// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 64>)
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// LLVM: shufflevector <64 x i8> zeroinitializer, <64 x i8> %{{.*}}, <64 x i32> <i32 12, i32 13, i32 14, i32 15, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 28, i32 29, i32 30, i32 31, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 44, i32 45, i32 46, i32 47, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 60, i32 61, i32 62, i32 63, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123>
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// OGCG: shufflevector <64 x i8> zeroinitializer, <64 x i8> %{{.*}}, <64 x i32> <i32 12, i32 13, i32 14, i32 15, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 28, i32 29, i32 30, i32 31, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 44, i32 45, i32 46, i32 47, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 60, i32 61, i32 62, i32 63, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123>
95+
return __builtin_ia32_pslldqi512_byteshift(a, 4);
96+
}
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// CIR-LABEL: @_Z23test_pslldqi512_shift16Dv8_x
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// LLVM-LABEL: @_Z23test_pslldqi512_shift16Dv8_x
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// OGCG-LABEL: @_Z23test_pslldqi512_shift16Dv8_x
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__m512i test_pslldqi512_shift16(__m512i a) {
102+
// All 4 lanes completely cleared
103+
// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 8>
104+
// LLVM: store <8 x i64> zeroinitializer, ptr %{{.*}}, align 64
105+
// OGCG: ret <8 x i64> zeroinitializer
106+
return __builtin_ia32_pslldqi512_byteshift(a, 16);
107+
}
108+
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// ============================================================================
110+
// Input-Output Verification Tests
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// ============================================================================
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// Test with specific input values to verify correct data transformation
114+
// CIR-LABEL: @_Z26test_input_output_shift4_1Dv2_x
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// LLVM-LABEL: @_Z26test_input_output_shift4_1Dv2_x
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// OGCG-LABEL: @_Z26test_input_output_shift4_1Dv2_x
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__m128i test_input_output_shift4_1(__m128i a) {
118+
// Input: [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] (bytes)
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// Shift left by 4 bytes (insert 4 zeros at start)
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// Output: [0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4] (bytes)
121+
// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<16> : !s32i, #cir.int<17> : !s32i, #cir.int<18> : !s32i, #cir.int<19> : !s32i, #cir.int<20> : !s32i, #cir.int<21> : !s32i, #cir.int<22> : !s32i, #cir.int<23> : !s32i, #cir.int<24> : !s32i, #cir.int<25> : !s32i, #cir.int<26> : !s32i, #cir.int<27> : !s32i] : !cir.vector<!s8i x 16>
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// LLVM: shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
123+
// OGCG: shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
124+
return __builtin_ia32_pslldqi128_byteshift(a, 4);
125+
}
126+
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// Test 256-bit lane independence with specific input pattern
128+
// CIR-LABEL: @_Z34test_input_output_256_independenceDv4_x
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// LLVM-LABEL: @_Z34test_input_output_256_independenceDv4_x
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// OGCG-LABEL: @_Z34test_input_output_256_independenceDv4_x
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__m256i test_input_output_256_independence(__m256i a) {
132+
// Input: Two 128-bit lanes, each with pattern [15,14,13,...,2,1,0]
133+
// Lane 0: [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
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// Lane 1: [31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16]
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// After shift by 4 bytes:
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// Lane 0: [0, 0, 0, 0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4]
137+
// Lane 1: [0, 0, 0, 0, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20]
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// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 32>)
139+
// LLVM: shufflevector <32 x i8> zeroinitializer, <32 x i8> %{{.*}}, <32 x i32> <i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59>
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// OGCG: shufflevector <32 x i8> zeroinitializer, <32 x i8> %{{.*}}, <32 x i32> <i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59>
141+
return __builtin_ia32_pslldqi256_byteshift(a, 4);
142+
}
143+
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// ============================================================================
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// Edge Cases
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// ============================================================================
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// Test with concrete constant values to verify exact transformation
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// CIR-LABEL: @_Z28test_concrete_input_constantv
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// LLVM-LABEL: @_Z28test_concrete_input_constantv
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// OGCG-LABEL: @_Z28test_concrete_input_constantv
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__m128i test_concrete_input_constant() {
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// Create a known input pattern: 0x0F0E0D0C0B0A09080706050403020100
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// This represents bytes [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
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__m128i input = (__m128i){0x0706050403020100LL, 0x0F0E0D0C0B0A0908LL};
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// Shift left by 4 bytes - should produce: 0x0B0A090807060504030201000000000
158+
// This represents bytes [0,0,0,0,15,14,13,12,11,10,9,8,7,6,5,4]
159+
__m128i result = __builtin_ia32_pslldqi128_byteshift(input, 4);
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// CIR: cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<!s8i x 16>) [#cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i, #cir.int<16> : !s32i, #cir.int<17> : !s32i, #cir.int<18> : !s32i, #cir.int<19> : !s32i, #cir.int<20> : !s32i, #cir.int<21> : !s32i, #cir.int<22> : !s32i, #cir.int<23> : !s32i, #cir.int<24> : !s32i, #cir.int<25> : !s32i, #cir.int<26> : !s32i, #cir.int<27> : !s32i] : !cir.vector<!s8i x 16>
162+
// LLVM: shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
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// OGCG: shufflevector <16 x i8> zeroinitializer, <16 x i8> %{{.*}}, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
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return result;
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}
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// CIR-LABEL: @_Z22test_large_shift_valueDv2_x
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// LLVM-LABEL: @_Z22test_large_shift_valueDv2_x
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// OGCG-LABEL: @_Z22test_large_shift_valueDv2_x
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__m128i test_large_shift_value(__m128i a) {
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// 240 & 0xFF = 240, so this should return zero (240 > 16)
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// CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<!s64i x 2>
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// LLVM: store <2 x i64> zeroinitializer, ptr %{{.*}}, align 16
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// OGCG: ret <2 x i64> zeroinitializer
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return __builtin_ia32_pslldqi128_byteshift(a, 240);
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}

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