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lines changed Original file line number Diff line number Diff line change @@ -4365,8 +4365,11 @@ class CIRSignBitOpLowering : public mlir::OpConversionPattern<cir::SignBitOp> {
43654365 if (auto longDoubleType =
43664366 mlir::dyn_cast<cir::LongDoubleType>(op.getInput ().getType ())) {
43674367 if (mlir::isa<cir::FP80Type>(longDoubleType.getUnderlying ())) {
4368- // see https://github.com/llvm/clangir/issues/1057
4369- llvm_unreachable (" NYI" );
4368+ // If the underlying type of LongDouble is FP80Type,
4369+ // DataLayout::getTypeSizeInBits returns 128.
4370+ // See https://github.com/llvm/clangir/issues/1057.
4371+ // Set the width to 80 manually.
4372+ width = 80 ;
43704373 }
43714374 }
43724375 auto intTy = mlir::IntegerType::get (rewriter.getContext (), width);
Original file line number Diff line number Diff line change @@ -23,3 +23,13 @@ void test_signbit_double(double val) {
2323 // LLVM: %{{.+}} = zext i1 [[TMP2]] to i32
2424 __builtin_signbitf (val );
2525}
26+
27+ void test_signbit_long_double (long double val ) {
28+ // CIR: test_signbit_long_double
29+ // LLVM: test_signbit_long_double
30+ __builtin_signbitl (val );
31+ // CIR: %{{.+}} = cir.signbit %{{.+}} : !cir.long_double<!cir.f80> -> !s32i
32+ // LLVM: [[TMP1:%.*]] = bitcast x86_fp80 %{{.+}} to i80
33+ // LLVM: [[TMP2:%.*]] = icmp slt i80 [[TMP1]], 0
34+ // LLVM: %{{.+}} = zext i1 [[TMP2]] to i32
35+ }
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