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RegisterCoalescer: Set undef on full register uses when coalescing implicit_def Issue Release Workflow #315529: Issue comment #118321 (comment) edited by arsenm
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AMDGPU: Add codegen support for gfx950 v_ashr_pk_i8/u8_i32 Check code formatting #116589: Pull request #118304 synchronize by arsenm
3m 15s users/arsenm/gfx950/v_ashr_pk_i8-patterns
users/arsenm/gfx950/v_ashr_pk_i8-patterns
3m 15s
AMDGPU: Add codegen support for gfx950 v_ashr_pk_i8/u8_i32 Labelling new pull requests #151626: Pull request #118304 synchronize by arsenm
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Comment on an issue Comment on an issue #102080: completed by clayborg
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Comment on an issue Comment on an issue #102079: completed by arsenm
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Comment on an issue Comment on an issue #102078: completed by preames
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[LLD] [COFF] Print a warning when using /dependentloadflag without load config Issue Release Workflow #315528: Issue comment #117400 (comment) created by nurmukhametov
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AMDGPU: Add support for V_CVT_PK_F16_F32 instruction for gfx950 Check code formatting #116588: Pull request #118300 synchronize by arsenm
3m 13s users/arsenm/gfx950/v_cvt_pk_f16_f32
users/arsenm/gfx950/v_cvt_pk_f16_f32
3m 13s
AMDGPU: Add support for V_CVT_PK_F16_F32 instruction for gfx950 Labelling new pull requests #151625: Pull request #118300 synchronize by arsenm
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Comment on an issue Comment on an issue #102077: completed by preames
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RegisterCoalescer: Set undef on full register uses when coalescing implicit_def Issue Release Workflow #315527: Issue comment #118321 (comment) created by arsenm
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[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match Check code formatting #116587: Pull request #118391 synchronize by preames
2m 58s preames:pr-riscv-deinterleave-via-shift-and-trunc
preames:pr-riscv-deinterleave-via-shift-and-trunc
2m 58s
[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match Labelling new pull requests #151624: Pull request #118391 synchronize by preames
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[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match Issue Release Workflow #315526: Issue comment #118391 (comment) created by llvmbot
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[lldb] Fix the DWARF index cache when index is partial. Issue Release Workflow #315525: Issue comment #118390 (comment) created by llvmbot
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[lldb] Fix the DWARF index cache when index is partial. PR Subscriber #75018: Pull request #118390 labeled by llvmbot
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[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match PR Subscriber #75019: Pull request #118391 labeled by llvmbot
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[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match Check code formatting #116586: Pull request #118391 opened by preames
55s preames:pr-riscv-deinterleave-via-shift-and-trunc
preames:pr-riscv-deinterleave-via-shift-and-trunc
55s
[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match Check for private emails used in PRs #26719: Pull request #118391 opened by preames
1m 23s preames:pr-riscv-deinterleave-via-shift-and-trunc
preames:pr-riscv-deinterleave-via-shift-and-trunc
1m 23s
[lldb] Fix the DWARF index cache when index is partial. Labelling new pull requests #151622: Pull request #118390 opened by clayborg
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[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match Labelling new pull requests #151623: Pull request #118391 opened by preames
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[lldb] Fix the DWARF index cache when index is partial. Check code formatting #116585: Pull request #118390 opened by clayborg
3m 24s clayborg:manual-index-partial
clayborg:manual-index-partial
3m 24s
[lldb] Fix the DWARF index cache when index is partial. Check for private emails used in PRs #26718: Pull request #118390 opened by clayborg
1m 34s clayborg:manual-index-partial
clayborg:manual-index-partial
1m 34s
AMDGPU: Add codegen support for gfx950 v_ashr_pk_i8/u8_i32 Labelling new pull requests #151621: Pull request #118304 synchronize by arsenm
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AMDGPU: Add support for V_CVT_PK_F16_F32 instruction for gfx950 Issue Release Workflow #315524: Issue comment #118300 (comment) edited by arsenm
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