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LU-JOHNLU-JOHN
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Update rebased test results
Signed-off-by: John Lu <[email protected]>
1 parent 9c62f92 commit 00011d0

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7 files changed

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-28
lines changed

7 files changed

+0
-28
lines changed

‎llvm/test/CodeGen/AMDGPU/carryout-selection.ll‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -704,7 +704,6 @@ define amdgpu_kernel void @suaddo64(ptr addrspace(1) %out, ptr addrspace(1) %car
704704
; CISI-NEXT: s_add_u32 s4, s4, s6
705705
; CISI-NEXT: s_cselect_b64 s[12:13], -1, 0
706706
; CISI-NEXT: s_or_b32 s6, s12, s13
707-
; CISI-NEXT: s_cmp_lg_u32 s6, 0
708707
; CISI-NEXT: s_addc_u32 s5, s5, s7
709708
; CISI-NEXT: s_mov_b32 s8, s0
710709
; CISI-NEXT: s_mov_b32 s9, s1
@@ -1691,7 +1690,6 @@ define amdgpu_kernel void @susubo64(ptr addrspace(1) %out, ptr addrspace(1) %car
16911690
; CISI-NEXT: s_sub_u32 s4, s4, s6
16921691
; CISI-NEXT: s_cselect_b64 s[12:13], -1, 0
16931692
; CISI-NEXT: s_or_b32 s6, s12, s13
1694-
; CISI-NEXT: s_cmp_lg_u32 s6, 0
16951693
; CISI-NEXT: s_subb_u32 s5, s5, s7
16961694
; CISI-NEXT: s_mov_b32 s8, s0
16971695
; CISI-NEXT: s_mov_b32 s9, s1

‎llvm/test/CodeGen/AMDGPU/sdiv64.ll‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,6 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) {
204204
; GCN-IR-NEXT: s_add_u32 s18, s16, 1
205205
; GCN-IR-NEXT: s_cselect_b64 s[10:11], -1, 0
206206
; GCN-IR-NEXT: s_or_b32 s10, s10, s11
207-
; GCN-IR-NEXT: s_cmp_lg_u32 s10, 0
208207
; GCN-IR-NEXT: s_addc_u32 s10, s17, 0
209208
; GCN-IR-NEXT: s_cselect_b64 s[10:11], -1, 0
210209
; GCN-IR-NEXT: s_sub_i32 s16, 63, s16
@@ -238,7 +237,6 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) {
238237
; GCN-IR-NEXT: s_add_u32 s14, s14, 1
239238
; GCN-IR-NEXT: s_cselect_b64 s[20:21], -1, 0
240239
; GCN-IR-NEXT: s_or_b32 s20, s20, s21
241-
; GCN-IR-NEXT: s_cmp_lg_u32 s20, 0
242240
; GCN-IR-NEXT: s_addc_u32 s15, s15, 0
243241
; GCN-IR-NEXT: s_cselect_b64 s[20:21], -1, 0
244242
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[8:9]
@@ -1307,7 +1305,6 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
13071305
; GCN-IR-NEXT: s_add_u32 s12, s10, 1
13081306
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
13091307
; GCN-IR-NEXT: s_or_b32 s8, s8, s9
1310-
; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0
13111308
; GCN-IR-NEXT: s_addc_u32 s8, s11, 0
13121309
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
13131310
; GCN-IR-NEXT: s_sub_i32 s10, 63, s10
@@ -1340,7 +1337,6 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
13401337
; GCN-IR-NEXT: s_add_u32 s16, s16, 1
13411338
; GCN-IR-NEXT: s_cselect_b64 s[18:19], -1, 0
13421339
; GCN-IR-NEXT: s_or_b32 s18, s18, s19
1343-
; GCN-IR-NEXT: s_cmp_lg_u32 s18, 0
13441340
; GCN-IR-NEXT: s_addc_u32 s17, s17, 0
13451341
; GCN-IR-NEXT: s_cselect_b64 s[18:19], -1, 0
13461342
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]

‎llvm/test/CodeGen/AMDGPU/srem64.ll‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,6 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) {
182182
; GCN-IR-NEXT: s_add_u32 s14, s12, 1
183183
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
184184
; GCN-IR-NEXT: s_or_b32 s8, s8, s9
185-
; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0
186185
; GCN-IR-NEXT: s_addc_u32 s8, s13, 0
187186
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
188187
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
@@ -216,7 +215,6 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) {
216215
; GCN-IR-NEXT: s_add_u32 s16, s16, 1
217216
; GCN-IR-NEXT: s_cselect_b64 s[18:19], -1, 0
218217
; GCN-IR-NEXT: s_or_b32 s18, s18, s19
219-
; GCN-IR-NEXT: s_cmp_lg_u32 s18, 0
220218
; GCN-IR-NEXT: s_addc_u32 s17, s17, 0
221219
; GCN-IR-NEXT: s_cselect_b64 s[18:19], -1, 0
222220
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
@@ -1160,7 +1158,6 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
11601158
; GCN-IR-NEXT: s_add_u32 s16, s14, 1
11611159
; GCN-IR-NEXT: s_cselect_b64 s[10:11], -1, 0
11621160
; GCN-IR-NEXT: s_or_b32 s10, s10, s11
1163-
; GCN-IR-NEXT: s_cmp_lg_u32 s10, 0
11641161
; GCN-IR-NEXT: s_addc_u32 s10, s15, 0
11651162
; GCN-IR-NEXT: s_cselect_b64 s[10:11], -1, 0
11661163
; GCN-IR-NEXT: s_sub_i32 s14, 63, s14
@@ -1194,7 +1191,6 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
11941191
; GCN-IR-NEXT: s_add_u32 s18, s18, 1
11951192
; GCN-IR-NEXT: s_cselect_b64 s[20:21], -1, 0
11961193
; GCN-IR-NEXT: s_or_b32 s20, s20, s21
1197-
; GCN-IR-NEXT: s_cmp_lg_u32 s20, 0
11981194
; GCN-IR-NEXT: s_addc_u32 s19, s19, 0
11991195
; GCN-IR-NEXT: s_cselect_b64 s[20:21], -1, 0
12001196
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[2:3]
@@ -1474,7 +1470,6 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x)
14741470
; GCN-IR-NEXT: s_add_u32 s8, s2, 1
14751471
; GCN-IR-NEXT: s_cselect_b64 s[10:11], -1, 0
14761472
; GCN-IR-NEXT: s_or_b32 s9, s10, s11
1477-
; GCN-IR-NEXT: s_cmp_lg_u32 s9, 0
14781473
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
14791474
; GCN-IR-NEXT: s_cselect_b64 s[10:11], -1, 0
14801475
; GCN-IR-NEXT: s_sub_i32 s2, 63, s2
@@ -1507,7 +1502,6 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x)
15071502
; GCN-IR-NEXT: s_add_u32 s14, s14, 1
15081503
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
15091504
; GCN-IR-NEXT: s_or_b32 s16, s16, s17
1510-
; GCN-IR-NEXT: s_cmp_lg_u32 s16, 0
15111505
; GCN-IR-NEXT: s_addc_u32 s15, s15, 0
15121506
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
15131507
; GCN-IR-NEXT: s_mov_b64 s[8:9], s[6:7]

‎llvm/test/CodeGen/AMDGPU/uaddo.ll‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@ define amdgpu_kernel void @s_uaddo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %
1818
; SI-NEXT: s_mov_b32 s5, s1
1919
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
2020
; SI-NEXT: s_or_b32 s0, s0, s1
21-
; SI-NEXT: s_cmp_lg_u32 s0, 0
2221
; SI-NEXT: s_addc_u32 s3, s3, s9
2322
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
2423
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
@@ -444,7 +443,6 @@ define amdgpu_kernel void @s_uaddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
444443
; SI-NEXT: s_add_u32 s4, s4, s6
445444
; SI-NEXT: s_cselect_b64 s[12:13], -1, 0
446445
; SI-NEXT: s_or_b32 s6, s12, s13
447-
; SI-NEXT: s_cmp_lg_u32 s6, 0
448446
; SI-NEXT: s_addc_u32 s5, s5, s7
449447
; SI-NEXT: s_mov_b32 s8, s0
450448
; SI-NEXT: s_mov_b32 s9, s1

‎llvm/test/CodeGen/AMDGPU/udiv64.ll‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,6 @@ define amdgpu_kernel void @s_test_udiv_i64(ptr addrspace(1) %out, i64 %x, i64 %y
148148
; GCN-IR-NEXT: s_add_u32 s14, s12, 1
149149
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
150150
; GCN-IR-NEXT: s_or_b32 s8, s8, s9
151-
; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0
152151
; GCN-IR-NEXT: s_addc_u32 s8, s13, 0
153152
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
154153
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
@@ -182,7 +181,6 @@ define amdgpu_kernel void @s_test_udiv_i64(ptr addrspace(1) %out, i64 %x, i64 %y
182181
; GCN-IR-NEXT: s_add_u32 s10, s10, 1
183182
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
184183
; GCN-IR-NEXT: s_or_b32 s16, s16, s17
185-
; GCN-IR-NEXT: s_cmp_lg_u32 s16, 0
186184
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
187185
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
188186
; GCN-IR-NEXT: s_mov_b64 s[2:3], s[4:5]
@@ -941,7 +939,6 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
941939
; GCN-IR-NEXT: s_add_u32 s10, s8, 1
942940
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
943941
; GCN-IR-NEXT: s_or_b32 s6, s6, s7
944-
; GCN-IR-NEXT: s_cmp_lg_u32 s6, 0
945942
; GCN-IR-NEXT: s_addc_u32 s6, s9, 0
946943
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
947944
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
@@ -974,7 +971,6 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
974971
; GCN-IR-NEXT: s_add_u32 s14, s14, 1
975972
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
976973
; GCN-IR-NEXT: s_or_b32 s16, s16, s17
977-
; GCN-IR-NEXT: s_cmp_lg_u32 s16, 0
978974
; GCN-IR-NEXT: s_addc_u32 s15, s15, 0
979975
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
980976
; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]
@@ -1313,7 +1309,6 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x)
13131309
; GCN-IR-NEXT: s_add_u32 s11, s8, 1
13141310
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
13151311
; GCN-IR-NEXT: s_or_b32 s6, s6, s7
1316-
; GCN-IR-NEXT: s_cmp_lg_u32 s6, 0
13171312
; GCN-IR-NEXT: s_addc_u32 s6, s9, 0
13181313
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
13191314
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
@@ -1343,7 +1338,6 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x)
13431338
; GCN-IR-NEXT: s_add_u32 s10, s10, 1
13441339
; GCN-IR-NEXT: s_cselect_b64 s[12:13], -1, 0
13451340
; GCN-IR-NEXT: s_or_b32 s12, s12, s13
1346-
; GCN-IR-NEXT: s_cmp_lg_u32 s12, 0
13471341
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
13481342
; GCN-IR-NEXT: s_cselect_b64 s[12:13], -1, 0
13491343
; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]

‎llvm/test/CodeGen/AMDGPU/urem64.ll‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,6 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y
182182
; GCN-IR-NEXT: s_add_u32 s14, s12, 1
183183
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
184184
; GCN-IR-NEXT: s_or_b32 s8, s8, s9
185-
; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0
186185
; GCN-IR-NEXT: s_addc_u32 s8, s13, 0
187186
; GCN-IR-NEXT: s_cselect_b64 s[8:9], -1, 0
188187
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
@@ -216,7 +215,6 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y
216215
; GCN-IR-NEXT: s_add_u32 s16, s16, 1
217216
; GCN-IR-NEXT: s_cselect_b64 s[18:19], -1, 0
218217
; GCN-IR-NEXT: s_or_b32 s18, s18, s19
219-
; GCN-IR-NEXT: s_cmp_lg_u32 s18, 0
220218
; GCN-IR-NEXT: s_addc_u32 s17, s17, 0
221219
; GCN-IR-NEXT: s_cselect_b64 s[18:19], -1, 0
222220
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
@@ -960,7 +958,6 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x)
960958
; GCN-IR-NEXT: s_add_u32 s10, s8, 1
961959
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
962960
; GCN-IR-NEXT: s_or_b32 s6, s6, s7
963-
; GCN-IR-NEXT: s_cmp_lg_u32 s6, 0
964961
; GCN-IR-NEXT: s_addc_u32 s6, s9, 0
965962
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
966963
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
@@ -993,7 +990,6 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x)
993990
; GCN-IR-NEXT: s_add_u32 s14, s14, 1
994991
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
995992
; GCN-IR-NEXT: s_or_b32 s16, s16, s17
996-
; GCN-IR-NEXT: s_cmp_lg_u32 s16, 0
997993
; GCN-IR-NEXT: s_addc_u32 s15, s15, 0
998994
; GCN-IR-NEXT: s_cselect_b64 s[16:17], -1, 0
999995
; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]
@@ -1083,7 +1079,6 @@ define amdgpu_kernel void @s_test_urem_k_den_i64(ptr addrspace(1) %out, i64 %x)
10831079
; GCN-IR-NEXT: s_add_u32 s11, s8, 1
10841080
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
10851081
; GCN-IR-NEXT: s_or_b32 s6, s6, s7
1086-
; GCN-IR-NEXT: s_cmp_lg_u32 s6, 0
10871082
; GCN-IR-NEXT: s_addc_u32 s6, s9, 0
10881083
; GCN-IR-NEXT: s_cselect_b64 s[6:7], -1, 0
10891084
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
@@ -1113,7 +1108,6 @@ define amdgpu_kernel void @s_test_urem_k_den_i64(ptr addrspace(1) %out, i64 %x)
11131108
; GCN-IR-NEXT: s_add_u32 s12, s12, 1
11141109
; GCN-IR-NEXT: s_cselect_b64 s[14:15], -1, 0
11151110
; GCN-IR-NEXT: s_or_b32 s14, s14, s15
1116-
; GCN-IR-NEXT: s_cmp_lg_u32 s14, 0
11171111
; GCN-IR-NEXT: s_addc_u32 s13, s13, 0
11181112
; GCN-IR-NEXT: s_cselect_b64 s[14:15], -1, 0
11191113
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]

‎llvm/test/CodeGen/AMDGPU/usubo.ll‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@ define amdgpu_kernel void @s_usubo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %
1818
; SI-NEXT: s_mov_b32 s5, s1
1919
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
2020
; SI-NEXT: s_or_b32 s0, s0, s1
21-
; SI-NEXT: s_cmp_lg_u32 s0, 0
2221
; SI-NEXT: s_subb_u32 s3, s3, s9
2322
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
2423
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
@@ -443,7 +442,6 @@ define amdgpu_kernel void @s_usubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
443442
; SI-NEXT: s_sub_u32 s4, s4, s6
444443
; SI-NEXT: s_cselect_b64 s[12:13], -1, 0
445444
; SI-NEXT: s_or_b32 s6, s12, s13
446-
; SI-NEXT: s_cmp_lg_u32 s6, 0
447445
; SI-NEXT: s_subb_u32 s5, s5, s7
448446
; SI-NEXT: s_mov_b32 s8, s0
449447
; SI-NEXT: s_mov_b32 s9, s1

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