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arsenmarsenm
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AMDGPU: Fix broken frame index expansion for v_add_co_u32_e64 (#114634)
With an explicit carry out operand, one too many operands were deleted resulting in a malformed v_mov_b32.
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2 files changed

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lines changed

2 files changed

+168
-1
lines changed

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2607,7 +2607,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
26072607
MI->removeOperand(FIOperandNum);
26082608

26092609
unsigned NumOps = MI->getNumOperands();
2610-
for (unsigned I = NumOps - 2; I >= 2; --I)
2610+
for (unsigned I = NumOps - 2; I >= NumDefs + 1; --I)
26112611
MI->removeOperand(I);
26122612

26132613
if (NumDefs == 2)

‎llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir‎

Lines changed: 167 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1661,3 +1661,170 @@ body: |
16611661
SI_RETURN implicit $vgpr0
16621662
16631663
...
1664+
1665+
---
1666+
name: v_add_co_u32_e64__fi_sgpr_kernel
1667+
tracksRegLiveness: true
1668+
stack:
1669+
- { id: 0, size: 20, alignment: 4 }
1670+
machineFunctionInfo:
1671+
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
1672+
frameOffsetReg: '$sgpr33'
1673+
stackPtrOffsetReg: '$sgpr32'
1674+
isEntryFunction: true
1675+
body: |
1676+
bb.0:
1677+
liveins: $sgpr4
1678+
1679+
; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel
1680+
; MUBUFW64: liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3
1681+
; MUBUFW64-NEXT: {{ $}}
1682+
; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
1683+
; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
1684+
; MUBUFW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec
1685+
; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0
1686+
;
1687+
; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel
1688+
; FLATSCRW64: liveins: $sgpr4
1689+
; FLATSCRW64-NEXT: {{ $}}
1690+
; FLATSCRW64-NEXT: renamable $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec
1691+
; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0
1692+
renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $sgpr4, 0, implicit $exec
1693+
SI_RETURN implicit $vgpr0
1694+
1695+
...
1696+
1697+
---
1698+
name: v_add_co_u32_e64__fi_sgpr_func
1699+
tracksRegLiveness: true
1700+
stack:
1701+
- { id: 0, size: 20, alignment: 4 }
1702+
machineFunctionInfo:
1703+
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
1704+
frameOffsetReg: '$sgpr33'
1705+
stackPtrOffsetReg: '$sgpr32'
1706+
body: |
1707+
bb.0:
1708+
liveins: $sgpr4
1709+
1710+
; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_func
1711+
; MUBUFW64: liveins: $sgpr4
1712+
; MUBUFW64-NEXT: {{ $}}
1713+
; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec
1714+
; MUBUFW64-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 killed $sgpr4, killed $vgpr1, 0, implicit $exec
1715+
; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0
1716+
;
1717+
; GFX940-LABEL: name: v_add_co_u32_e64__fi_sgpr_func
1718+
; GFX940: liveins: $sgpr4
1719+
; GFX940-NEXT: {{ $}}
1720+
; GFX940-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec
1721+
; GFX940-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 killed $sgpr4, killed $vgpr1, 0, implicit $exec
1722+
; GFX940-NEXT: SI_RETURN implicit $vgpr0
1723+
;
1724+
; GFX11-LABEL: name: v_add_co_u32_e64__fi_sgpr_func
1725+
; GFX11: liveins: $sgpr4
1726+
; GFX11-NEXT: {{ $}}
1727+
; GFX11-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 $sgpr32, killed $sgpr4, 0, implicit $exec
1728+
; GFX11-NEXT: SI_RETURN implicit $vgpr0
1729+
;
1730+
; GFX12-LABEL: name: v_add_co_u32_e64__fi_sgpr_func
1731+
; GFX12: liveins: $sgpr4
1732+
; GFX12-NEXT: {{ $}}
1733+
; GFX12-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 $sgpr32, killed $sgpr4, 0, implicit $exec
1734+
; GFX12-NEXT: SI_RETURN implicit $vgpr0
1735+
renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $sgpr4, 0, implicit $exec
1736+
SI_RETURN implicit $vgpr0
1737+
1738+
...
1739+
1740+
---
1741+
name: v_add_co_u32_e64__fi_inc_same_vgpr_kernel
1742+
tracksRegLiveness: true
1743+
stack:
1744+
- { id: 0, size: 20, alignment: 4 }
1745+
machineFunctionInfo:
1746+
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
1747+
frameOffsetReg: '$sgpr33'
1748+
stackPtrOffsetReg: '$sgpr32'
1749+
isEntryFunction: true
1750+
body: |
1751+
bb.0:
1752+
liveins: $vgpr0
1753+
1754+
; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_kernel
1755+
; MUBUFW64: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3
1756+
; MUBUFW64-NEXT: {{ $}}
1757+
; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
1758+
; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
1759+
; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0
1760+
;
1761+
; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_kernel
1762+
; FLATSCRW64: liveins: $vgpr0
1763+
; FLATSCRW64-NEXT: {{ $}}
1764+
; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0
1765+
renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $vgpr0, 0, implicit $exec
1766+
SI_RETURN implicit $vgpr0
1767+
1768+
...
1769+
1770+
---
1771+
name: v_add_co_u32_e64__fi_inc_same_vgpr_func
1772+
tracksRegLiveness: true
1773+
stack:
1774+
- { id: 0, size: 20, alignment: 4 }
1775+
machineFunctionInfo:
1776+
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
1777+
frameOffsetReg: '$sgpr33'
1778+
stackPtrOffsetReg: '$sgpr32'
1779+
body: |
1780+
bb.0:
1781+
liveins: $vgpr0
1782+
1783+
; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_func
1784+
; MUBUFW64: liveins: $vgpr0
1785+
; MUBUFW64-NEXT: {{ $}}
1786+
; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec
1787+
; MUBUFW64-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 killed $vgpr0, killed $vgpr1, 0, implicit $exec
1788+
; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0
1789+
;
1790+
; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_inc_same_vgpr_func
1791+
; FLATSCRW64: liveins: $vgpr0
1792+
; FLATSCRW64-NEXT: {{ $}}
1793+
; FLATSCRW64-NEXT: renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 $sgpr32, killed $vgpr0, 0, implicit $exec
1794+
; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0
1795+
renamable $vgpr0, dead renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $vgpr0, 0, implicit $exec
1796+
SI_RETURN implicit $vgpr0
1797+
1798+
...
1799+
1800+
---
1801+
name: v_add_co_u32_e64__fi_sgpr_kernel_live_co
1802+
tracksRegLiveness: true
1803+
stack:
1804+
- { id: 0, size: 20, alignment: 4 }
1805+
machineFunctionInfo:
1806+
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
1807+
frameOffsetReg: '$sgpr33'
1808+
stackPtrOffsetReg: '$sgpr32'
1809+
isEntryFunction: true
1810+
body: |
1811+
bb.0:
1812+
liveins: $sgpr4
1813+
1814+
; MUBUFW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel_live_co
1815+
; MUBUFW64: liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3
1816+
; MUBUFW64-NEXT: {{ $}}
1817+
; MUBUFW64-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $noreg, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
1818+
; MUBUFW64-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
1819+
; MUBUFW64-NEXT: renamable $vgpr0, renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 0, killed $sgpr4, 0, implicit $exec
1820+
; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr4_sgpr5
1821+
;
1822+
; FLATSCRW64-LABEL: name: v_add_co_u32_e64__fi_sgpr_kernel_live_co
1823+
; FLATSCRW64: liveins: $sgpr4
1824+
; FLATSCRW64-NEXT: {{ $}}
1825+
; FLATSCRW64-NEXT: renamable $vgpr0, renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 0, killed $sgpr4, 0, implicit $exec
1826+
; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr4_sgpr5
1827+
renamable $vgpr0, renamable $sgpr4_sgpr5 = V_ADD_CO_U32_e64 %stack.0, killed $sgpr4, 0, implicit $exec
1828+
SI_RETURN implicit $vgpr0, implicit $sgpr4_sgpr5
1829+
1830+
...

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