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fixup! Add check for UndefinedBooleanContents. Add missing compare.
1 parent f7b9e3f commit 002dabc

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5 files changed

+46
-44
lines changed

5 files changed

+46
-44
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7938,15 +7938,17 @@ LegalizerHelper::lowerThreewayCompare(MachineInstr &MI) {
79387938

79397939
auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
79407940
const DataLayout &DL = MIRBuilder.getDataLayout();
7941+
auto BC = TLI.getBooleanContents(DstTy.isVector(), /*isFP=*/false);
79417942
if (TLI.shouldExpandCmpUsingSelects(
7942-
getApproximateEVTForLLT(SrcTy, DL, Ctx))) {
7943+
getApproximateEVTForLLT(SrcTy, DL, Ctx)) ||
7944+
BC == TargetLowering::UndefinedBooleanContent) {
79437945
auto One = MIRBuilder.buildConstant(DstTy, 1);
79447946
auto SelectZeroOrOne = MIRBuilder.buildSelect(DstTy, IsGT, One, Zero);
79457947

79467948
auto MinusOne = MIRBuilder.buildConstant(DstTy, -1);
79477949
MIRBuilder.buildSelect(Dst, IsLT, MinusOne, SelectZeroOrOne);
79487950
} else {
7949-
if (TLI.getBooleanContents(DstTy.isVector(), /*isFP=*/false))
7951+
if (BC == TargetLowering::ZeroOrNegativeOneBooleanContent)
79507952
std::swap(IsGT, IsLT);
79517953
unsigned BoolExtOp =
79527954
MIRBuilder.getBoolExtOp(DstTy.isVector(), /*isFP=*/false);

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ body: |
1414
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
1515
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
1616
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
17-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ICMP1]], [[ICMP]]
17+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ICMP]], [[ICMP1]]
1818
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
1919
; CHECK-NEXT: PseudoRET implicit $x10
2020
%0:_(s32) = COPY $x10
@@ -38,7 +38,7 @@ body: |
3838
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
3939
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
4040
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
41-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ICMP1]], [[ICMP]]
41+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ICMP]], [[ICMP1]]
4242
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
4343
; CHECK-NEXT: PseudoRET implicit $x10
4444
%0:_(s32) = COPY $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ body: |
1616
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
1717
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
1818
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
19-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ICMP1]], [[ICMP]]
19+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ICMP]], [[ICMP1]]
2020
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32
2121
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
2222
; CHECK-NEXT: PseudoRET implicit $x10
@@ -45,7 +45,7 @@ body: |
4545
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
4646
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
4747
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
48-
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ICMP1]], [[ICMP]]
48+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ICMP]], [[ICMP1]]
4949
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32
5050
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
5151
; CHECK-NEXT: PseudoRET implicit $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@ define i8 @scmp.8.8(i8 signext %x, i8 signext %y) nounwind {
77
; RV32I: # %bb.0:
88
; RV32I-NEXT: slt a2, a1, a0
99
; RV32I-NEXT: slt a0, a0, a1
10-
; RV32I-NEXT: sub a0, a0, a2
10+
; RV32I-NEXT: sub a0, a2, a0
1111
; RV32I-NEXT: ret
1212
;
1313
; RV64I-LABEL: scmp.8.8:
1414
; RV64I: # %bb.0:
1515
; RV64I-NEXT: slt a2, a1, a0
1616
; RV64I-NEXT: slt a0, a0, a1
17-
; RV64I-NEXT: sub a0, a0, a2
17+
; RV64I-NEXT: sub a0, a2, a0
1818
; RV64I-NEXT: ret
1919
%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
2020
ret i8 %1
@@ -25,14 +25,14 @@ define i8 @scmp.8.16(i16 signext %x, i16 signext %y) nounwind {
2525
; RV32I: # %bb.0:
2626
; RV32I-NEXT: slt a2, a1, a0
2727
; RV32I-NEXT: slt a0, a0, a1
28-
; RV32I-NEXT: sub a0, a0, a2
28+
; RV32I-NEXT: sub a0, a2, a0
2929
; RV32I-NEXT: ret
3030
;
3131
; RV64I-LABEL: scmp.8.16:
3232
; RV64I: # %bb.0:
3333
; RV64I-NEXT: slt a2, a1, a0
3434
; RV64I-NEXT: slt a0, a0, a1
35-
; RV64I-NEXT: sub a0, a0, a2
35+
; RV64I-NEXT: sub a0, a2, a0
3636
; RV64I-NEXT: ret
3737
%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
3838
ret i8 %1
@@ -43,7 +43,7 @@ define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {
4343
; RV32I: # %bb.0:
4444
; RV32I-NEXT: slt a2, a1, a0
4545
; RV32I-NEXT: slt a0, a0, a1
46-
; RV32I-NEXT: sub a0, a0, a2
46+
; RV32I-NEXT: sub a0, a2, a0
4747
; RV32I-NEXT: ret
4848
;
4949
; RV64I-LABEL: scmp.8.32:
@@ -52,7 +52,7 @@ define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {
5252
; RV64I-NEXT: sext.w a1, a1
5353
; RV64I-NEXT: slt a2, a1, a0
5454
; RV64I-NEXT: slt a0, a0, a1
55-
; RV64I-NEXT: sub a0, a0, a2
55+
; RV64I-NEXT: sub a0, a2, a0
5656
; RV64I-NEXT: ret
5757
%1 = call i8 @llvm.scmp(i32 %x, i32 %y)
5858
ret i8 %1
@@ -65,19 +65,19 @@ define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {
6565
; RV32I-NEXT: # %bb.1:
6666
; RV32I-NEXT: slt a4, a3, a1
6767
; RV32I-NEXT: slt a0, a1, a3
68-
; RV32I-NEXT: sub a0, a0, a4
68+
; RV32I-NEXT: sub a0, a4, a0
6969
; RV32I-NEXT: ret
7070
; RV32I-NEXT: .LBB3_2:
7171
; RV32I-NEXT: sltu a4, a2, a0
7272
; RV32I-NEXT: sltu a0, a0, a2
73-
; RV32I-NEXT: sub a0, a0, a4
73+
; RV32I-NEXT: sub a0, a4, a0
7474
; RV32I-NEXT: ret
7575
;
7676
; RV64I-LABEL: scmp.8.64:
7777
; RV64I: # %bb.0:
7878
; RV64I-NEXT: slt a2, a1, a0
7979
; RV64I-NEXT: slt a0, a0, a1
80-
; RV64I-NEXT: sub a0, a0, a2
80+
; RV64I-NEXT: sub a0, a2, a0
8181
; RV64I-NEXT: ret
8282
%1 = call i8 @llvm.scmp(i64 %x, i64 %y)
8383
ret i8 %1
@@ -88,7 +88,7 @@ define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {
8888
; RV32I: # %bb.0:
8989
; RV32I-NEXT: slt a2, a1, a0
9090
; RV32I-NEXT: slt a0, a0, a1
91-
; RV32I-NEXT: sub a0, a0, a2
91+
; RV32I-NEXT: sub a0, a2, a0
9292
; RV32I-NEXT: ret
9393
;
9494
; RV64I-LABEL: scmp.32.32:
@@ -97,7 +97,7 @@ define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {
9797
; RV64I-NEXT: sext.w a1, a1
9898
; RV64I-NEXT: slt a2, a1, a0
9999
; RV64I-NEXT: slt a0, a0, a1
100-
; RV64I-NEXT: sub a0, a0, a2
100+
; RV64I-NEXT: sub a0, a2, a0
101101
; RV64I-NEXT: ret
102102
%1 = call i32 @llvm.scmp(i32 %x, i32 %y)
103103
ret i32 %1
@@ -110,19 +110,19 @@ define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {
110110
; RV32I-NEXT: # %bb.1:
111111
; RV32I-NEXT: slt a4, a3, a1
112112
; RV32I-NEXT: slt a0, a1, a3
113-
; RV32I-NEXT: sub a0, a0, a4
113+
; RV32I-NEXT: sub a0, a4, a0
114114
; RV32I-NEXT: ret
115115
; RV32I-NEXT: .LBB5_2:
116116
; RV32I-NEXT: sltu a4, a2, a0
117117
; RV32I-NEXT: sltu a0, a0, a2
118-
; RV32I-NEXT: sub a0, a0, a4
118+
; RV32I-NEXT: sub a0, a4, a0
119119
; RV32I-NEXT: ret
120120
;
121121
; RV64I-LABEL: scmp.32.64:
122122
; RV64I: # %bb.0:
123123
; RV64I-NEXT: slt a2, a1, a0
124124
; RV64I-NEXT: slt a0, a0, a1
125-
; RV64I-NEXT: sub a0, a0, a2
125+
; RV64I-NEXT: sub a0, a2, a0
126126
; RV64I-NEXT: ret
127127
%1 = call i32 @llvm.scmp(i64 %x, i64 %y)
128128
ret i32 %1
@@ -140,16 +140,16 @@ define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {
140140
; RV32I-NEXT: sltu a4, a2, a0
141141
; RV32I-NEXT: sltu a1, a0, a2
142142
; RV32I-NEXT: .LBB6_3:
143-
; RV32I-NEXT: sub a0, a1, a4
144-
; RV32I-NEXT: sltu a1, a1, a4
143+
; RV32I-NEXT: sub a0, a4, a1
144+
; RV32I-NEXT: sltu a1, a4, a1
145145
; RV32I-NEXT: neg a1, a1
146146
; RV32I-NEXT: ret
147147
;
148148
; RV64I-LABEL: scmp.64.64:
149149
; RV64I: # %bb.0:
150150
; RV64I-NEXT: slt a2, a1, a0
151151
; RV64I-NEXT: slt a0, a0, a1
152-
; RV64I-NEXT: sub a0, a0, a2
152+
; RV64I-NEXT: sub a0, a2, a0
153153
; RV64I-NEXT: ret
154154
%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
155155
ret i64 %1

‎llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@ define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {
77
; RV32I: # %bb.0:
88
; RV32I-NEXT: sltu a2, a1, a0
99
; RV32I-NEXT: sltu a0, a0, a1
10-
; RV32I-NEXT: sub a0, a0, a2
10+
; RV32I-NEXT: sub a0, a2, a0
1111
; RV32I-NEXT: ret
1212
;
1313
; RV64I-LABEL: ucmp.8.8:
1414
; RV64I: # %bb.0:
1515
; RV64I-NEXT: sltu a2, a1, a0
1616
; RV64I-NEXT: sltu a0, a0, a1
17-
; RV64I-NEXT: sub a0, a0, a2
17+
; RV64I-NEXT: sub a0, a2, a0
1818
; RV64I-NEXT: ret
1919
%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
2020
ret i8 %1
@@ -25,14 +25,14 @@ define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {
2525
; RV32I: # %bb.0:
2626
; RV32I-NEXT: sltu a2, a1, a0
2727
; RV32I-NEXT: sltu a0, a0, a1
28-
; RV32I-NEXT: sub a0, a0, a2
28+
; RV32I-NEXT: sub a0, a2, a0
2929
; RV32I-NEXT: ret
3030
;
3131
; RV64I-LABEL: ucmp.8.16:
3232
; RV64I: # %bb.0:
3333
; RV64I-NEXT: sltu a2, a1, a0
3434
; RV64I-NEXT: sltu a0, a0, a1
35-
; RV64I-NEXT: sub a0, a0, a2
35+
; RV64I-NEXT: sub a0, a2, a0
3636
; RV64I-NEXT: ret
3737
%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
3838
ret i8 %1
@@ -43,7 +43,7 @@ define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
4343
; RV32I: # %bb.0:
4444
; RV32I-NEXT: sltu a2, a1, a0
4545
; RV32I-NEXT: sltu a0, a0, a1
46-
; RV32I-NEXT: sub a0, a0, a2
46+
; RV32I-NEXT: sub a0, a2, a0
4747
; RV32I-NEXT: ret
4848
;
4949
; RV64I-LABEL: ucmp.8.32:
@@ -54,7 +54,7 @@ define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
5454
; RV64I-NEXT: srli a1, a1, 32
5555
; RV64I-NEXT: sltu a2, a1, a0
5656
; RV64I-NEXT: sltu a0, a0, a1
57-
; RV64I-NEXT: sub a0, a0, a2
57+
; RV64I-NEXT: sub a0, a2, a0
5858
; RV64I-NEXT: ret
5959
%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
6060
ret i8 %1
@@ -67,19 +67,19 @@ define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
6767
; RV32I-NEXT: # %bb.1:
6868
; RV32I-NEXT: sltu a4, a3, a1
6969
; RV32I-NEXT: sltu a0, a1, a3
70-
; RV32I-NEXT: sub a0, a0, a4
70+
; RV32I-NEXT: sub a0, a4, a0
7171
; RV32I-NEXT: ret
7272
; RV32I-NEXT: .LBB3_2:
7373
; RV32I-NEXT: sltu a4, a2, a0
7474
; RV32I-NEXT: sltu a0, a0, a2
75-
; RV32I-NEXT: sub a0, a0, a4
75+
; RV32I-NEXT: sub a0, a4, a0
7676
; RV32I-NEXT: ret
7777
;
7878
; RV64I-LABEL: ucmp.8.64:
7979
; RV64I: # %bb.0:
8080
; RV64I-NEXT: sltu a2, a1, a0
8181
; RV64I-NEXT: sltu a0, a0, a1
82-
; RV64I-NEXT: sub a0, a0, a2
82+
; RV64I-NEXT: sub a0, a2, a0
8383
; RV64I-NEXT: ret
8484
%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
8585
ret i8 %1
@@ -90,7 +90,7 @@ define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
9090
; RV32I: # %bb.0:
9191
; RV32I-NEXT: sltu a2, a1, a0
9292
; RV32I-NEXT: sltu a0, a0, a1
93-
; RV32I-NEXT: sub a0, a0, a2
93+
; RV32I-NEXT: sub a0, a2, a0
9494
; RV32I-NEXT: ret
9595
;
9696
; RV64I-LABEL: ucmp.32.32:
@@ -101,7 +101,7 @@ define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
101101
; RV64I-NEXT: srli a1, a1, 32
102102
; RV64I-NEXT: sltu a2, a1, a0
103103
; RV64I-NEXT: sltu a0, a0, a1
104-
; RV64I-NEXT: sub a0, a0, a2
104+
; RV64I-NEXT: sub a0, a2, a0
105105
; RV64I-NEXT: ret
106106
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
107107
ret i32 %1
@@ -112,7 +112,7 @@ define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {
112112
; RV32I: # %bb.0:
113113
; RV32I-NEXT: sltu a2, a1, a0
114114
; RV32I-NEXT: sltu a0, a0, a1
115-
; RV32I-NEXT: sub a0, a0, a2
115+
; RV32I-NEXT: sub a0, a2, a0
116116
; RV32I-NEXT: ret
117117
;
118118
; RV64I-LABEL: ucmp.32.32_sext:
@@ -123,7 +123,7 @@ define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {
123123
; RV64I-NEXT: srli a1, a1, 32
124124
; RV64I-NEXT: sltu a2, a1, a0
125125
; RV64I-NEXT: sltu a0, a0, a1
126-
; RV64I-NEXT: sub a0, a0, a2
126+
; RV64I-NEXT: sub a0, a2, a0
127127
; RV64I-NEXT: ret
128128
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
129129
ret i32 %1
@@ -134,14 +134,14 @@ define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind {
134134
; RV32I: # %bb.0:
135135
; RV32I-NEXT: sltu a2, a1, a0
136136
; RV32I-NEXT: sltu a0, a0, a1
137-
; RV32I-NEXT: sub a0, a0, a2
137+
; RV32I-NEXT: sub a0, a2, a0
138138
; RV32I-NEXT: ret
139139
;
140140
; RV64I-LABEL: ucmp.32.32_zext:
141141
; RV64I: # %bb.0:
142142
; RV64I-NEXT: sltu a2, a1, a0
143143
; RV64I-NEXT: sltu a0, a0, a1
144-
; RV64I-NEXT: sub a0, a0, a2
144+
; RV64I-NEXT: sub a0, a2, a0
145145
; RV64I-NEXT: ret
146146
%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
147147
ret i32 %1
@@ -154,19 +154,19 @@ define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
154154
; RV32I-NEXT: # %bb.1:
155155
; RV32I-NEXT: sltu a4, a3, a1
156156
; RV32I-NEXT: sltu a0, a1, a3
157-
; RV32I-NEXT: sub a0, a0, a4
157+
; RV32I-NEXT: sub a0, a4, a0
158158
; RV32I-NEXT: ret
159159
; RV32I-NEXT: .LBB7_2:
160160
; RV32I-NEXT: sltu a4, a2, a0
161161
; RV32I-NEXT: sltu a0, a0, a2
162-
; RV32I-NEXT: sub a0, a0, a4
162+
; RV32I-NEXT: sub a0, a4, a0
163163
; RV32I-NEXT: ret
164164
;
165165
; RV64I-LABEL: ucmp.32.64:
166166
; RV64I: # %bb.0:
167167
; RV64I-NEXT: sltu a2, a1, a0
168168
; RV64I-NEXT: sltu a0, a0, a1
169-
; RV64I-NEXT: sub a0, a0, a2
169+
; RV64I-NEXT: sub a0, a2, a0
170170
; RV64I-NEXT: ret
171171
%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
172172
ret i32 %1
@@ -184,16 +184,16 @@ define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
184184
; RV32I-NEXT: sltu a4, a2, a0
185185
; RV32I-NEXT: sltu a1, a0, a2
186186
; RV32I-NEXT: .LBB8_3:
187-
; RV32I-NEXT: sub a0, a1, a4
188-
; RV32I-NEXT: sltu a1, a1, a4
187+
; RV32I-NEXT: sub a0, a4, a1
188+
; RV32I-NEXT: sltu a1, a4, a1
189189
; RV32I-NEXT: neg a1, a1
190190
; RV32I-NEXT: ret
191191
;
192192
; RV64I-LABEL: ucmp.64.64:
193193
; RV64I: # %bb.0:
194194
; RV64I-NEXT: sltu a2, a1, a0
195195
; RV64I-NEXT: sltu a0, a0, a1
196-
; RV64I-NEXT: sub a0, a0, a2
196+
; RV64I-NEXT: sub a0, a2, a0
197197
; RV64I-NEXT: ret
198198
%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
199199
ret i64 %1

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