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Inline bitcast node creation.
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+6
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llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4853,22 +4853,24 @@ static SDValue getBitwiseToSrcModifierOp(SDValue N,
48534853
EVT VT = RHS.getValueType();
48544854
EVT FVT = getFloatVT(VT);
48554855
SDLoc SL = SDLoc(N);
4856-
SDValue BC = DAG.getNode(ISD::BITCAST, SL, FVT, LHS);
48574856

48584857
switch (Opc) {
48594858
case ISD::XOR:
48604859
if (CRHS->getAPIntValue().isSignMask())
4861-
return DAG.getNode(ISD::FNEG, SL, FVT, BC);
4860+
return DAG.getNode(ISD::FNEG, SL, FVT,
4861+
DAG.getNode(ISD::BITCAST, SL, FVT, LHS));
48624862
break;
48634863
case ISD::OR:
48644864
if (CRHS->getAPIntValue().isSignMask()) {
4865-
SDValue Abs = DAG.getNode(ISD::FABS, SL, FVT, BC);
4865+
SDValue Abs = DAG.getNode(ISD::FABS, SL, FVT,
4866+
DAG.getNode(ISD::BITCAST, SL, FVT, LHS));
48664867
return DAG.getNode(ISD::FNEG, SL, FVT, Abs);
48674868
}
48684869
break;
48694870
case ISD::AND:
48704871
if (CRHS->getAPIntValue().isMaxSignedValue())
4871-
return DAG.getNode(ISD::FABS, SL, FVT, BC);
4872+
return DAG.getNode(ISD::FABS, SL, FVT,
4873+
DAG.getNode(ISD::BITCAST, SL, FVT, LHS));
48724874
break;
48734875
default:
48744876
return SDValue();

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