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davemgreendavemgreen
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[AArch64] Add costs for ROTR and ROTL. (#169335)
A funnel shift with the first two operands is a rotate. AArch64 has scalar instructions for ror so can handle a ROTR by a constant or variant amount cheaply. A ROTL is a ROTR by the opposite amount, which for constants is cheap and for variable shifts requires an extra neg.
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-55
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3 files changed

+67
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‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -926,8 +926,20 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
926926
if (ICA.getArgs().empty())
927927
break;
928928

929-
// TODO: Add handling for fshl where third argument is not a constant.
930929
const TTI::OperandValueInfo OpInfoZ = TTI::getOperandInfo(ICA.getArgs()[2]);
930+
931+
// ROTR / ROTL is a funnel shift with equal first and second operand. For
932+
// ROTR on integer registers (i32/i64) this can be done in a single ror
933+
// instruction. A fshl with a non-constant shift uses a neg + ror.
934+
if (RetTy->isIntegerTy() && ICA.getArgs()[0] == ICA.getArgs()[1] &&
935+
(RetTy->getPrimitiveSizeInBits() == 32 ||
936+
RetTy->getPrimitiveSizeInBits() == 64)) {
937+
InstructionCost NegCost =
938+
(ICA.getID() == Intrinsic::fshl && !OpInfoZ.isConstant()) ? 1 : 0;
939+
return 1 + NegCost;
940+
}
941+
942+
// TODO: Add handling for fshl where third argument is not a constant.
931943
if (!OpInfoZ.isConstant())
932944
break;
933945

‎llvm/test/Analysis/CostModel/AArch64/fshl.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -349,7 +349,7 @@ entry:
349349

350350
define i32 @rotl_i32_3rd_arg_var(i32 %a, i32 %c) {
351351
; CHECK-LABEL: 'rotl_i32_3rd_arg_var'
352-
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
352+
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
353353
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
354354
;
355355
entry:
@@ -369,7 +369,7 @@ entry:
369369

370370
define i64 @rotl_i64_3rd_arg_var(i64 %a, i64 %c) {
371371
; CHECK-LABEL: 'rotl_i64_3rd_arg_var'
372-
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
372+
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
373373
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
374374
;
375375
entry:

‎llvm/test/Analysis/CostModel/AArch64/fshr.ll‎

Lines changed: 52 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -297,8 +297,8 @@ entry:
297297

298298
; Rotate tests
299299

300-
define i8 @rotl_i8_3rd_arg_const(i8 %a) {
301-
; CHECK-LABEL: 'rotl_i8_3rd_arg_const'
300+
define i8 @rotr_i8_3rd_arg_const(i8 %a) {
301+
; CHECK-LABEL: 'rotr_i8_3rd_arg_const'
302302
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 9)
303303
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i8 %r
304304
;
@@ -307,8 +307,8 @@ entry:
307307
ret i8 %r
308308
}
309309

310-
define i8 @rotl_i8_3rd_arg_var(i8 %a, i8 %c) {
311-
; CHECK-LABEL: 'rotl_i8_3rd_arg_var'
310+
define i8 @rotr_i8_3rd_arg_var(i8 %a, i8 %c) {
311+
; CHECK-LABEL: 'rotr_i8_3rd_arg_var'
312312
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 %c)
313313
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i8 %r
314314
;
@@ -317,8 +317,8 @@ entry:
317317
ret i8 %r
318318
}
319319

320-
define i16 @rotl_i16_3rd_arg_const(i16 %a) {
321-
; CHECK-LABEL: 'rotl_i16_3rd_arg_const'
320+
define i16 @rotr_i16_3rd_arg_const(i16 %a) {
321+
; CHECK-LABEL: 'rotr_i16_3rd_arg_const'
322322
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 9)
323323
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i16 %r
324324
;
@@ -327,8 +327,8 @@ entry:
327327
ret i16 %r
328328
}
329329

330-
define i16 @rotl_i16_3rd_arg_var(i16 %a, i16 %c) {
331-
; CHECK-LABEL: 'rotl_i16_3rd_arg_var'
330+
define i16 @rotr_i16_3rd_arg_var(i16 %a, i16 %c) {
331+
; CHECK-LABEL: 'rotr_i16_3rd_arg_var'
332332
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %c)
333333
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i16 %r
334334
;
@@ -337,8 +337,8 @@ entry:
337337
ret i16 %r
338338
}
339339

340-
define i32 @rotl_i32_3rd_arg_const(i32 %a) {
341-
; CHECK-LABEL: 'rotl_i32_3rd_arg_const'
340+
define i32 @rotr_i32_3rd_arg_const(i32 %a) {
341+
; CHECK-LABEL: 'rotr_i32_3rd_arg_const'
342342
; CHECK-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
343343
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
344344
;
@@ -347,18 +347,18 @@ entry:
347347
ret i32 %r
348348
}
349349

350-
define i32 @rotl_i32_3rd_arg_var(i32 %a, i32 %c) {
351-
; CHECK-LABEL: 'rotl_i32_3rd_arg_var'
352-
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
350+
define i32 @rotr_i32_3rd_arg_var(i32 %a, i32 %c) {
351+
; CHECK-LABEL: 'rotr_i32_3rd_arg_var'
352+
; CHECK-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
353353
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
354354
;
355355
entry:
356356
%r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
357357
ret i32 %r
358358
}
359359

360-
define i64 @rotl_i64_3rd_arg_const(i64 %a) {
361-
; CHECK-LABEL: 'rotl_i64_3rd_arg_const'
360+
define i64 @rotr_i64_3rd_arg_const(i64 %a) {
361+
; CHECK-LABEL: 'rotr_i64_3rd_arg_const'
362362
; CHECK-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
363363
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
364364
;
@@ -367,18 +367,18 @@ entry:
367367
ret i64 %r
368368
}
369369

370-
define i64 @rotl_i64_3rd_arg_var(i64 %a, i64 %c) {
371-
; CHECK-LABEL: 'rotl_i64_3rd_arg_var'
372-
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
370+
define i64 @rotr_i64_3rd_arg_var(i64 %a, i64 %c) {
371+
; CHECK-LABEL: 'rotr_i64_3rd_arg_var'
372+
; CHECK-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
373373
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
374374
;
375375
entry:
376376
%r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
377377
ret i64 %r
378378
}
379379

380-
define i128 @rotl_i128_3rd_arg_const(i128 %a) {
381-
; CHECK-LABEL: 'rotl_i128_3rd_arg_const'
380+
define i128 @rotr_i128_3rd_arg_const(i128 %a) {
381+
; CHECK-LABEL: 'rotr_i128_3rd_arg_const'
382382
; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 9)
383383
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i128 %r
384384
;
@@ -387,8 +387,8 @@ entry:
387387
ret i128 %r
388388
}
389389

390-
define i128 @rotl_i128_3rd_arg_var(i128 %a, i128 %c) {
391-
; CHECK-LABEL: 'rotl_i128_3rd_arg_var'
390+
define i128 @rotr_i128_3rd_arg_var(i128 %a, i128 %c) {
391+
; CHECK-LABEL: 'rotr_i128_3rd_arg_var'
392392
; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %c)
393393
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i128 %r
394394
;
@@ -397,8 +397,8 @@ entry:
397397
ret i128 %r
398398
}
399399

400-
define <16 x i8> @rotl_v16i8_3rd_arg_vec_const_all_lanes_same(<16 x i8> %a) {
401-
; CHECK-LABEL: 'rotl_v16i8_3rd_arg_vec_const_all_lanes_same'
400+
define <16 x i8> @rotr_v16i8_3rd_arg_vec_const_all_lanes_same(<16 x i8> %a) {
401+
; CHECK-LABEL: 'rotr_v16i8_3rd_arg_vec_const_all_lanes_same'
402402
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> splat (i8 3))
403403
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <16 x i8> %r
404404
;
@@ -407,8 +407,8 @@ entry:
407407
ret <16 x i8> %r
408408
}
409409

410-
define <16 x i8> @rotl_v16i8_3rd_arg_vec_const_lanes_different(<16 x i8> %a) {
411-
; CHECK-LABEL: 'rotl_v16i8_3rd_arg_vec_const_lanes_different'
410+
define <16 x i8> @rotr_v16i8_3rd_arg_vec_const_lanes_different(<16 x i8> %a) {
411+
; CHECK-LABEL: 'rotr_v16i8_3rd_arg_vec_const_lanes_different'
412412
; CHECK-NEXT: Cost Model: Found costs of 4 for: %r = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 9, i8 1, i8 13, i8 7, i8 31, i8 23, i8 43, i8 51, i8 3, i8 3, i8 17, i8 3, i8 11, i8 15, i8 3, i8 3>)
413413
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <16 x i8> %r
414414
;
@@ -417,8 +417,8 @@ entry:
417417
ret <16 x i8> %r
418418
}
419419

420-
define <16 x i8> @rotl_v16i8_3rd_arg_var(<16 x i8> %a, <16 x i8> %c) {
421-
; CHECK-LABEL: 'rotl_v16i8_3rd_arg_var'
420+
define <16 x i8> @rotr_v16i8_3rd_arg_var(<16 x i8> %a, <16 x i8> %c) {
421+
; CHECK-LABEL: 'rotr_v16i8_3rd_arg_var'
422422
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %c)
423423
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <16 x i8> %r
424424
;
@@ -427,8 +427,8 @@ entry:
427427
ret <16 x i8> %r
428428
}
429429

430-
define <8 x i16> @rotl_v8i16_3rd_arg_vec_const_all_lanes_same(<8 x i16> %a) {
431-
; CHECK-LABEL: 'rotl_v8i16_3rd_arg_vec_const_all_lanes_same'
430+
define <8 x i16> @rotr_v8i16_3rd_arg_vec_const_all_lanes_same(<8 x i16> %a) {
431+
; CHECK-LABEL: 'rotr_v8i16_3rd_arg_vec_const_all_lanes_same'
432432
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> splat (i16 3))
433433
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <8 x i16> %r
434434
;
@@ -437,8 +437,8 @@ entry:
437437
ret <8 x i16> %r
438438
}
439439

440-
define <8 x i16> @rotl_v8i16_3rd_arg_vec_const_lanes_different(<8 x i16> %a) {
441-
; CHECK-LABEL: 'rotl_v8i16_3rd_arg_vec_const_lanes_different'
440+
define <8 x i16> @rotr_v8i16_3rd_arg_vec_const_lanes_different(<8 x i16> %a) {
441+
; CHECK-LABEL: 'rotr_v8i16_3rd_arg_vec_const_lanes_different'
442442
; CHECK-NEXT: Cost Model: Found costs of 4 for: %r = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> <i16 3, i16 1, i16 13, i16 8, i16 7, i16 31, i16 43, i16 51>)
443443
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <8 x i16> %r
444444
;
@@ -447,8 +447,8 @@ entry:
447447
ret <8 x i16> %r
448448
}
449449

450-
define <8 x i16> @rotl_v8i16_3rd_arg_var(<8 x i16> %a, <8 x i16> %c) {
451-
; CHECK-LABEL: 'rotl_v8i16_3rd_arg_var'
450+
define <8 x i16> @rotr_v8i16_3rd_arg_var(<8 x i16> %a, <8 x i16> %c) {
451+
; CHECK-LABEL: 'rotr_v8i16_3rd_arg_var'
452452
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %c)
453453
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <8 x i16> %r
454454
;
@@ -457,8 +457,8 @@ entry:
457457
ret <8 x i16> %r
458458
}
459459

460-
define <4 x i32> @rotl_v4i32_3rd_arg_vec_const_all_lanes_same(<4 x i32> %a) {
461-
; CHECK-LABEL: 'rotl_v4i32_3rd_arg_vec_const_all_lanes_same'
460+
define <4 x i32> @rotr_v4i32_3rd_arg_vec_const_all_lanes_same(<4 x i32> %a) {
461+
; CHECK-LABEL: 'rotr_v4i32_3rd_arg_vec_const_all_lanes_same'
462462
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> splat (i32 3))
463463
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <4 x i32> %r
464464
;
@@ -467,8 +467,8 @@ entry:
467467
ret <4 x i32> %r
468468
}
469469

470-
define <4 x i32> @rotl_v4i32_3rd_arg_vec_const_lanes_different(<4 x i32> %a) {
471-
; CHECK-LABEL: 'rotl_v4i32_3rd_arg_vec_const_lanes_different'
470+
define <4 x i32> @rotr_v4i32_3rd_arg_vec_const_lanes_different(<4 x i32> %a) {
471+
; CHECK-LABEL: 'rotr_v4i32_3rd_arg_vec_const_lanes_different'
472472
; CHECK-NEXT: Cost Model: Found costs of 4 for: %r = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 1, i32 3, i32 11, i32 2>)
473473
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <4 x i32> %r
474474
;
@@ -477,8 +477,8 @@ entry:
477477
ret <4 x i32> %r
478478
}
479479

480-
define <4 x i32> @rotl_v4i32_3rd_arg_var(<4 x i32> %a, <4 x i32> %c) {
481-
; CHECK-LABEL: 'rotl_v4i32_3rd_arg_var'
480+
define <4 x i32> @rotr_v4i32_3rd_arg_var(<4 x i32> %a, <4 x i32> %c) {
481+
; CHECK-LABEL: 'rotr_v4i32_3rd_arg_var'
482482
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %c)
483483
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <4 x i32> %r
484484
;
@@ -487,8 +487,8 @@ entry:
487487
ret <4 x i32> %r
488488
}
489489

490-
define <2 x i64> @rotl_v2i64_3rd_arg_vec_const_all_lanes_same(<2 x i64> %a) {
491-
; CHECK-LABEL: 'rotl_v2i64_3rd_arg_vec_const_all_lanes_same'
490+
define <2 x i64> @rotr_v2i64_3rd_arg_vec_const_all_lanes_same(<2 x i64> %a) {
491+
; CHECK-LABEL: 'rotr_v2i64_3rd_arg_vec_const_all_lanes_same'
492492
; CHECK-NEXT: Cost Model: Found costs of 2 for: %r = tail call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> splat (i64 1))
493493
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <2 x i64> %r
494494
;
@@ -497,8 +497,8 @@ entry:
497497
ret <2 x i64> %r
498498
}
499499

500-
define <2 x i64> @rotl_v2i64_3rd_arg_vec_const_lanes_different(<2 x i64> %a) {
501-
; CHECK-LABEL: 'rotl_v2i64_3rd_arg_vec_const_lanes_different'
500+
define <2 x i64> @rotr_v2i64_3rd_arg_vec_const_lanes_different(<2 x i64> %a) {
501+
; CHECK-LABEL: 'rotr_v2i64_3rd_arg_vec_const_lanes_different'
502502
; CHECK-NEXT: Cost Model: Found costs of 4 for: %r = tail call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 1, i64 2>)
503503
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <2 x i64> %r
504504
;
@@ -507,8 +507,8 @@ entry:
507507
ret <2 x i64> %r
508508
}
509509

510-
define <2 x i64> @rotl_v2i64_3rd_arg_var(<2 x i64> %a, <2 x i64> %c) {
511-
; CHECK-LABEL: 'rotl_v2i64_3rd_arg_var'
510+
define <2 x i64> @rotr_v2i64_3rd_arg_var(<2 x i64> %a, <2 x i64> %c) {
511+
; CHECK-LABEL: 'rotr_v2i64_3rd_arg_var'
512512
; CHECK-NEXT: Cost Model: Found costs of 5 for: %r = tail call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %c)
513513
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <2 x i64> %r
514514
;
@@ -517,8 +517,8 @@ entry:
517517
ret <2 x i64> %r
518518
}
519519

520-
define <2 x i128> @rotl_v2i128_3rd_arg_vec_const_all_lanes_same(<2 x i128> %a) {
521-
; CHECK-LABEL: 'rotl_v2i128_3rd_arg_vec_const_all_lanes_same'
520+
define <2 x i128> @rotr_v2i128_3rd_arg_vec_const_all_lanes_same(<2 x i128> %a) {
521+
; CHECK-LABEL: 'rotr_v2i128_3rd_arg_vec_const_all_lanes_same'
522522
; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %a, <2 x i128> %a, <2 x i128> splat (i128 1))
523523
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <2 x i128> %r
524524
;
@@ -527,8 +527,8 @@ entry:
527527
ret <2 x i128> %r
528528
}
529529

530-
define <2 x i128> @rotl_v2i128_3rd_arg_vec_const_lanes_different(<2 x i128> %a) {
531-
; CHECK-LABEL: 'rotl_v2i128_3rd_arg_vec_const_lanes_different'
530+
define <2 x i128> @rotr_v2i128_3rd_arg_vec_const_lanes_different(<2 x i128> %a) {
531+
; CHECK-LABEL: 'rotr_v2i128_3rd_arg_vec_const_lanes_different'
532532
; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %a, <2 x i128> %a, <2 x i128> <i128 1, i128 2>)
533533
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <2 x i128> %r
534534
;
@@ -537,8 +537,8 @@ entry:
537537
ret <2 x i128> %r
538538
}
539539

540-
define <2 x i128> @rotl_v2i128_3rd_arg_var(<2 x i128> %a, <2 x i128> %c) {
541-
; CHECK-LABEL: 'rotl_v2i128_3rd_arg_var'
540+
define <2 x i128> @rotr_v2i128_3rd_arg_var(<2 x i128> %a, <2 x i128> %c) {
541+
; CHECK-LABEL: 'rotr_v2i128_3rd_arg_var'
542542
; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %a, <2 x i128> %a, <2 x i128> %c)
543543
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <2 x i128> %r
544544
;

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