More format fixing

Author: chrisjbris

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -4116,7 +4116,7 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SDLoc SL(N);
   SelectionDAG &DAG = DCI.DAG;
 
-  if(SDValue SS = getShiftForReduction(ISD::SHL, LHS, RHS, DAG))
+  if (SDValue SS = getShiftForReduction(ISD::SHL, LHS, RHS, DAG))
     return SS;
 
   unsigned RHSVal;
@@ -4219,7 +4219,7 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
   SelectionDAG &DAG = DCI.DAG;
   SDLoc SL(N);
 
-  if(SDValue SS = getShiftForReduction(ISD::SRA, LHS, RHS, DAG))
+  if (SDValue SS = getShiftForReduction(ISD::SRA, LHS, RHS, DAG))
     return SS;
 
   if (VT.getScalarType() != MVT::i64)
@@ -4325,7 +4325,7 @@ SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
   SDLoc SL(N);
   unsigned RHSVal;
 
-  if(SDValue SS = getShiftForReduction(ISD::SRL, LHS, RHS, DAG))
+  if (SDValue SS = getShiftForReduction(ISD::SRL, LHS, RHS, DAG))
     return SS;
 
   if (CRHS) {