[X86][CodeGen] - Use shift operators instead of built-ins for SSE emulation of MMX intrinsics

When performing constant value shifts, the generated code using
SSE emulation via intrinsics is less efficient than using standard
left/right shift operators. allow for better performance by using operators
instead of built-ins.

Author: pawan-nirpal-031

clang/lib/Headers/mmintrin.h

@@ -880,11 +880,11 @@ _mm_sll_si64(__m64 __m, __m64 __count)
 ///    A 32-bit integer value.
 /// \returns A 64-bit integer vector containing the left-shifted value. If
 ///     \a __count is greater or equal to 64, the result is set to 0.
-static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2
-_mm_slli_si64(__m64 __m, int __count)
-{
-    return __trunc64(__builtin_ia32_psllqi128((__v2di)__anyext128(__m),
-                                              __count));
+static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 _mm_slli_si64(__m64 __m,
+                                                              int __count) {
+  if (__builtin_constant_p(__count))
+    return (__m64)((__count > 63) ? 0 : ((long long)__m << __count));
+  return __trunc64(__builtin_ia32_psllqi128((__v2di)__anyext128(__m), __count));
 }
 
 /// Right-shifts each 16-bit integer element of the first parameter,
@@ -1115,11 +1115,11 @@ _mm_srl_si64(__m64 __m, __m64 __count)
 /// \param __count
 ///    A 32-bit integer value.
 /// \returns A 64-bit integer vector containing the right-shifted value.
-static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2
-_mm_srli_si64(__m64 __m, int __count)
-{
-    return __trunc64(__builtin_ia32_psrlqi128((__v2di)__anyext128(__m),
-                                              __count));
+static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 _mm_srli_si64(__m64 __m,
+                                                              int __count) {
+  if (__builtin_constant_p(__count))
+    return (__m64)((__count > 63) ? 0 : ((long long)__m >> __count));
+  return __trunc64(__builtin_ia32_psrlqi128((__v2di)__anyext128(__m), __count));
 }
 
 /// Performs a bitwise AND of two 64-bit integer vectors.

clang/test/CodeGen/X86/mmx-builtins.c

@@ -563,7 +563,13 @@ __m64 test_mm_slli_pi32(__m64 a) {
 
 __m64 test_mm_slli_si64(__m64 a) {
   // CHECK-LABEL: test_mm_slli_si64
-  // CHECK: call <2 x i64> @llvm.x86.sse2.pslli.q(
+  // CHECK:  %__m.addr.i = alloca <1 x i64>, align 8
+  // CHECK:  %__count.addr.i = alloca i32, align 4
+  // CHECK:  %5 = load <1 x i64>, ptr %__m.addr.i, align 8
+  // CHECK:  %6 = bitcast <1 x i64> %5 to i64
+  // CHECK:  %7 = load i32, ptr %__count.addr.i, align 4
+  // CHECK:  %sh_prom.i = zext i32 %7 to i64
+  // CHECK:  %shl.i = shl i64 %6, %sh_prom.i
   return _mm_slli_si64(a, 3);
 }
 
@@ -623,7 +629,13 @@ __m64 test_mm_srli_pi32(__m64 a) {
 
 __m64 test_mm_srli_si64(__m64 a) {
   // CHECK-LABEL: test_mm_srli_si64
-  // CHECK: call <2 x i64> @llvm.x86.sse2.psrli.q(
+  // CHECK:  %__m.addr.i = alloca <1 x i64>, align 8
+  // CHECK:  %__count.addr.i = alloca i32, align 4
+  // CHECK:  %5 = load <1 x i64>, ptr %__m.addr.i, align 8
+  // CHECK:  %6 = bitcast <1 x i64> %5 to i64
+  // CHECK:  %7 = load i32, ptr %__count.addr.i, align 4
+  // CHECK:  %sh_prom.i = zext i32 %7 to i64
+  // CHECK:  %shr.i = ashr i64 %6, %sh_prom.i
   return _mm_srli_si64(a, 3);
 }