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alexey-bataevalexey-bataev
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[SLP]Fix a crash on an subvector size calculation for non-power-of-2 vector
Patch fixes cost estimation for the extractelements from non-power-of-2 vectors, defined as subvector extracts. In this case the subvector size might be not adjusted to a whole register size, need to get the minimum between whole vector size and the actual difference to prevent compiler crash. Fixes #143513
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4 files changed

+119
-34
lines changed

4 files changed

+119
-34
lines changed

‎llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -12085,7 +12085,8 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis {
1208512085
// FIXME: this must be moved to TTI for better estimation.
1208612086
unsigned EltsPerVector = getPartNumElems(VL.size(), NumParts);
1208712087
auto CheckPerRegistersShuffle = [&](MutableArrayRef<int> Mask,
12088-
SmallVectorImpl<unsigned> &Indices)
12088+
SmallVectorImpl<unsigned> &Indices,
12089+
SmallVectorImpl<unsigned> &SubVecSizes)
1208912090
-> std::optional<TTI::ShuffleKind> {
1209012091
if (NumElts <= EltsPerVector)
1209112092
return std::nullopt;
@@ -12130,7 +12131,9 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis {
1213012131
return std::min(S, I);
1213112132
}),
1213212133
EltsPerVector);
12133-
Indices.push_back(OffsetReg1 % NumElts);
12134+
unsigned Index = OffsetReg1 % NumElts;
12135+
Indices.push_back(Index);
12136+
SubVecSizes.push_back(std::min(NumElts - Index, EltsPerVector));
1213412137
}
1213512138
Idx = I - OffsetReg1;
1213612139
}
@@ -12152,8 +12155,9 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis {
1215212155
SmallVector<int> SubMask(EltsPerVector, PoisonMaskElem);
1215312156
copy(MaskSlice, SubMask.begin());
1215412157
SmallVector<unsigned, 2> Indices;
12158+
SmallVector<unsigned, 2> SubVecSizes;
1215512159
std::optional<TTI::ShuffleKind> RegShuffleKind =
12156-
CheckPerRegistersShuffle(SubMask, Indices);
12160+
CheckPerRegistersShuffle(SubMask, Indices, SubVecSizes);
1215712161
if (!RegShuffleKind) {
1215812162
if (*ShuffleKinds[Part] != TTI::SK_PermuteSingleSrc ||
1215912163
!ShuffleVectorInst::isIdentityMask(
@@ -12171,12 +12175,12 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis {
1217112175
}
1217212176
const unsigned BaseVF = getFullVectorNumberOfElements(
1217312177
*R.TTI, VL.front()->getType(), alignTo(NumElts, EltsPerVector));
12174-
for (unsigned Idx : Indices) {
12175-
assert((Idx + EltsPerVector) <= BaseVF &&
12178+
for (const auto [Idx, SubVecSize] : zip(Indices, SubVecSizes)) {
12179+
assert((Idx + SubVecSize) <= BaseVF &&
1217612180
"SK_ExtractSubvector index out of range");
1217712181
Cost += ::getShuffleCost(TTI, TTI::SK_ExtractSubvector,
1217812182
getWidenedType(ScalarTy, BaseVF), {}, CostKind,
12179-
Idx, getWidenedType(ScalarTy, EltsPerVector));
12183+
Idx, getWidenedType(ScalarTy, SubVecSize));
1218012184
}
1218112185
// Second attempt to check, if just a permute is better estimated than
1218212186
// subvector extract.

‎llvm/test/Transforms/PhaseOrdering/X86/hadd.ll‎

Lines changed: 11 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -272,24 +272,21 @@ define <16 x i16> @add_v16i16_0123456789ABCDEF(<16 x i16> %a, <16 x i16> %b) {
272272

273273
define <16 x i16> @add_v16i16_0123u56789uBCDEF(<16 x i16> %a, <16 x i16> %b) {
274274
; SSE2-LABEL: @add_v16i16_0123u56789uBCDEF(
275-
; SSE2-NEXT: [[BC:%.*]] = extractelement <16 x i16> [[B:%.*]], i64 12
276-
; SSE2-NEXT: [[BD:%.*]] = extractelement <16 x i16> [[B]], i64 13
277-
; SSE2-NEXT: [[BE:%.*]] = extractelement <16 x i16> [[B]], i64 14
275+
; SSE2-NEXT: [[BE:%.*]] = extractelement <16 x i16> [[B:%.*]], i64 14
278276
; SSE2-NEXT: [[BF:%.*]] = extractelement <16 x i16> [[B]], i64 15
279-
; SSE2-NEXT: [[BCD:%.*]] = add i16 [[BC]], [[BD]]
280277
; SSE2-NEXT: [[BEF:%.*]] = add i16 [[BE]], [[BF]]
281-
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 18, i32 20, i32 22, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
282-
; SSE2-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 19, i32 21, i32 23, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
283-
; SSE2-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[A]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 24, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
284-
; SSE2-NEXT: [[TMP7:%.*]] = shufflevector <16 x i16> [[TMP2]], <16 x i16> [[A]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 25, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
278+
; SSE2-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> [[B1:%.*]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 18, i32 20, i32 22, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
279+
; SSE2-NEXT: [[TMP7:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> [[B1]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 19, i32 21, i32 23, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
285280
; SSE2-NEXT: [[HADD8:%.*]] = add <16 x i16> [[TMP3]], [[TMP7]]
286-
; SSE2-NEXT: [[TMP4:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 10, i32 poison, i32 14, i32 24, i32 26, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
287-
; SSE2-NEXT: [[TMP5:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 11, i32 poison, i32 15, i32 25, i32 27, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
281+
; SSE2-NEXT: [[TMP4:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> poison, <16 x i32> <i32 9, i32 10, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
282+
; SSE2-NEXT: [[TMP5:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> poison, <16 x i32> <i32 8, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
288283
; SSE2-NEXT: [[TMP6:%.*]] = add <16 x i16> [[TMP4]], [[TMP5]]
289-
; SSE2-NEXT: [[HADDD1:%.*]] = shufflevector <16 x i16> [[HADD8]], <16 x i16> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 8, i32 16, i32 poison, i32 18, i32 19, i32 20, i32 poison, i32 poison>
290-
; SSE2-NEXT: [[HADDE:%.*]] = insertelement <16 x i16> [[HADDD1]], i16 [[BCD]], i64 14
291-
; SSE2-NEXT: [[HADDF:%.*]] = insertelement <16 x i16> [[HADDE]], i16 [[BEF]], i64 15
292-
; SSE2-NEXT: [[RESULT:%.*]] = shufflevector <16 x i16> [[HADDF]], <16 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 8, i32 9, i32 poison, i32 11, i32 12, i32 13, i32 14, i32 15>
284+
; SSE2-NEXT: [[HADD92:%.*]] = shufflevector <16 x i16> [[HADD8]], <16 x i16> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
285+
; SSE2-NEXT: [[HADDB:%.*]] = insertelement <16 x i16> [[HADD92]], i16 [[BEF]], i64 11
286+
; SSE2-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[B1]], <16 x i16> poison, <16 x i32> <i32 8, i32 10, i32 12, i32 14, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
287+
; SSE2-NEXT: [[TMP8:%.*]] = shufflevector <16 x i16> [[B1]], <16 x i16> poison, <16 x i32> <i32 9, i32 11, i32 13, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
288+
; SSE2-NEXT: [[TMP9:%.*]] = add <16 x i16> [[TMP10]], [[TMP8]]
289+
; SSE2-NEXT: [[RESULT:%.*]] = shufflevector <16 x i16> [[HADDB]], <16 x i16> [[TMP9]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 8, i32 9, i32 poison, i32 11, i32 16, i32 17, i32 18, i32 19>
293290
; SSE2-NEXT: ret <16 x i16> [[RESULT]]
294291
;
295292
; SSE4-LABEL: @add_v16i16_0123u56789uBCDEF(

‎llvm/test/Transforms/PhaseOrdering/X86/hsub.ll‎

Lines changed: 11 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -272,24 +272,21 @@ define <16 x i16> @sub_v16i16_0123456789ABCDEF(<16 x i16> %a, <16 x i16> %b) {
272272

273273
define <16 x i16> @sub_v16i16_0123u56789uBCDEF(<16 x i16> %a, <16 x i16> %b) {
274274
; SSE2-LABEL: @sub_v16i16_0123u56789uBCDEF(
275-
; SSE2-NEXT: [[BC:%.*]] = extractelement <16 x i16> [[B:%.*]], i64 12
276-
; SSE2-NEXT: [[BD:%.*]] = extractelement <16 x i16> [[B]], i64 13
277-
; SSE2-NEXT: [[BE:%.*]] = extractelement <16 x i16> [[B]], i64 14
275+
; SSE2-NEXT: [[BE:%.*]] = extractelement <16 x i16> [[B:%.*]], i64 14
278276
; SSE2-NEXT: [[BF:%.*]] = extractelement <16 x i16> [[B]], i64 15
279-
; SSE2-NEXT: [[BCD:%.*]] = sub i16 [[BC]], [[BD]]
280277
; SSE2-NEXT: [[BEF:%.*]] = sub i16 [[BE]], [[BF]]
281-
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 18, i32 20, i32 22, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
282-
; SSE2-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 19, i32 21, i32 23, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
283-
; SSE2-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[A]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 24, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
284-
; SSE2-NEXT: [[TMP7:%.*]] = shufflevector <16 x i16> [[TMP2]], <16 x i16> [[A]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 25, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
278+
; SSE2-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> [[B1:%.*]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 18, i32 20, i32 22, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
279+
; SSE2-NEXT: [[TMP7:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> [[B1]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 19, i32 21, i32 23, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
285280
; SSE2-NEXT: [[HSUB8:%.*]] = sub <16 x i16> [[TMP3]], [[TMP7]]
286-
; SSE2-NEXT: [[TMP4:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 10, i32 poison, i32 14, i32 24, i32 26, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
287-
; SSE2-NEXT: [[TMP5:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 11, i32 poison, i32 15, i32 25, i32 27, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
281+
; SSE2-NEXT: [[TMP4:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> poison, <16 x i32> <i32 8, i32 10, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
282+
; SSE2-NEXT: [[TMP5:%.*]] = shufflevector <16 x i16> [[B]], <16 x i16> poison, <16 x i32> <i32 9, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
288283
; SSE2-NEXT: [[TMP6:%.*]] = sub <16 x i16> [[TMP4]], [[TMP5]]
289-
; SSE2-NEXT: [[HSUBD1:%.*]] = shufflevector <16 x i16> [[HSUB8]], <16 x i16> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 8, i32 16, i32 poison, i32 18, i32 19, i32 20, i32 poison, i32 poison>
290-
; SSE2-NEXT: [[HSUBE:%.*]] = insertelement <16 x i16> [[HSUBD1]], i16 [[BCD]], i64 14
291-
; SSE2-NEXT: [[HSUBF:%.*]] = insertelement <16 x i16> [[HSUBE]], i16 [[BEF]], i64 15
292-
; SSE2-NEXT: [[RESULT:%.*]] = shufflevector <16 x i16> [[HSUBF]], <16 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 8, i32 9, i32 poison, i32 11, i32 12, i32 13, i32 14, i32 15>
284+
; SSE2-NEXT: [[HSUB92:%.*]] = shufflevector <16 x i16> [[HSUB8]], <16 x i16> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
285+
; SSE2-NEXT: [[HSUBB:%.*]] = insertelement <16 x i16> [[HSUB92]], i16 [[BEF]], i64 11
286+
; SSE2-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[B1]], <16 x i16> poison, <16 x i32> <i32 8, i32 10, i32 12, i32 14, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
287+
; SSE2-NEXT: [[TMP8:%.*]] = shufflevector <16 x i16> [[B1]], <16 x i16> poison, <16 x i32> <i32 9, i32 11, i32 13, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
288+
; SSE2-NEXT: [[TMP9:%.*]] = sub <16 x i16> [[TMP10]], [[TMP8]]
289+
; SSE2-NEXT: [[RESULT:%.*]] = shufflevector <16 x i16> [[HSUBB]], <16 x i16> [[TMP9]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 6, i32 7, i32 8, i32 9, i32 poison, i32 11, i32 16, i32 17, i32 18, i32 19>
293290
; SSE2-NEXT: ret <16 x i16> [[RESULT]]
294291
;
295292
; SSE4-LABEL: @sub_v16i16_0123u56789uBCDEF(

‎llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll‎

Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,87 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S --passes=slp-vectorizer -mtriple=s390x-ibm-linux -mcpu=z13 -slp-max-reg-size=256 -slp-vectorize-hor-store -slp-vectorize-non-power-of-2 < %s | FileCheck %s
3+
4+
@c = external global [1 x [10 x i32]]
5+
@j.0 = external global i32
6+
7+
define void @p() {
8+
; CHECK-LABEL: define void @p(
9+
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
10+
; CHECK-NEXT: [[ENTRY:.*:]]
11+
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @c, i64 52), align 4
12+
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0
13+
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2
14+
; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> [[TMP0]], splat (i32 1)
15+
; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr getelementptr inbounds nuw (i8, ptr @c, i64 52), align 4
16+
; CHECK-NEXT: [[TMP4:%.*]] = load <7 x i32>, ptr getelementptr inbounds nuw (i8, ptr @c, i64 200), align 4
17+
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <7 x i32> [[TMP4]], i32 3
18+
; CHECK-NEXT: [[OR_1_5_I_3:%.*]] = or i32 [[TMP1]], [[TMP5]]
19+
; CHECK-NEXT: store i32 [[OR_1_5_I_3]], ptr @j.0, align 4
20+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <7 x i32> [[TMP4]], i32 5
21+
; CHECK-NEXT: [[TMP7:%.*]] = xor <7 x i32> [[TMP4]], splat (i32 1)
22+
; CHECK-NEXT: store <7 x i32> [[TMP7]], ptr getelementptr inbounds nuw (i8, ptr @c, i64 200), align 4
23+
; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @c, i64 252), align 4
24+
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP8]], i32 1
25+
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP2]]
26+
; CHECK-NEXT: [[OR_1_5_I_5:%.*]] = or i32 [[TMP10]], [[TMP6]]
27+
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP8]], i32 2
28+
; CHECK-NEXT: [[OR_1_6_I_5:%.*]] = or i32 [[OR_1_5_I_5]], [[TMP11]]
29+
; CHECK-NEXT: store i32 [[OR_1_6_I_5]], ptr @j.0, align 4
30+
; CHECK-NEXT: [[TMP12:%.*]] = xor <4 x i32> [[TMP8]], splat (i32 1)
31+
; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr getelementptr inbounds nuw (i8, ptr @c, i64 252), align 4
32+
; CHECK-NEXT: ret void
33+
;
34+
entry:
35+
%arrayidx12.promoted.5.i = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 200), align 4
36+
%conv14.5.i = xor i32 %arrayidx12.promoted.5.i, 1
37+
store i32 %conv14.5.i, ptr getelementptr inbounds nuw (i8, ptr @c, i64 200), align 4
38+
%arrayidx12.promoted.5.i.1 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 204), align 4
39+
%conv14.5.i.1 = xor i32 %arrayidx12.promoted.5.i.1, 1
40+
store i32 %conv14.5.i.1, ptr getelementptr inbounds nuw (i8, ptr @c, i64 204), align 4
41+
%arrayidx12.promoted.5.i.2 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 208), align 4
42+
%conv14.5.i.2 = xor i32 %arrayidx12.promoted.5.i.2, 1
43+
store i32 %conv14.5.i.2, ptr getelementptr inbounds nuw (i8, ptr @c, i64 208), align 4
44+
%arrayidx12.promoted.1.i.3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 52), align 4
45+
%conv14.1.i.3 = xor i32 %arrayidx12.promoted.1.i.3, 1
46+
store i32 %conv14.1.i.3, ptr getelementptr inbounds nuw (i8, ptr @c, i64 52), align 4
47+
%arrayidx12.promoted.5.i.3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 212), align 4
48+
%conv14.5.i.3 = xor i32 %arrayidx12.promoted.5.i.3, 1
49+
store i32 %conv14.5.i.3, ptr getelementptr inbounds nuw (i8, ptr @c, i64 212), align 4
50+
%arrayidx12.promoted.6.i.3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 252), align 4
51+
%conv14.6.i.3 = xor i32 %arrayidx12.promoted.6.i.3, 1
52+
%or.1.5.i.3 = or i32 %arrayidx12.promoted.1.i.3, %arrayidx12.promoted.5.i.3
53+
store i32 %conv14.6.i.3, ptr getelementptr inbounds nuw (i8, ptr @c, i64 252), align 4
54+
store i32 %or.1.5.i.3, ptr @j.0, align 4
55+
%arrayidx12.promoted.1.i.4 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 56), align 4
56+
%conv14.1.i.4 = xor i32 %arrayidx12.promoted.1.i.4, 1
57+
store i32 %conv14.1.i.4, ptr getelementptr inbounds nuw (i8, ptr @c, i64 56), align 4
58+
%arrayidx12.promoted.5.i.4 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 216), align 4
59+
%conv14.5.i.4 = xor i32 %arrayidx12.promoted.5.i.4, 1
60+
store i32 %conv14.5.i.4, ptr getelementptr inbounds nuw (i8, ptr @c, i64 216), align 4
61+
%arrayidx12.promoted.6.i.4 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 256), align 4
62+
%conv14.6.i.4 = xor i32 %arrayidx12.promoted.6.i.4, 1
63+
store i32 %conv14.6.i.4, ptr getelementptr inbounds nuw (i8, ptr @c, i64 256), align 4
64+
%arrayidx12.promoted.1.i.5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 60), align 4
65+
%conv14.1.i.5 = xor i32 %arrayidx12.promoted.1.i.5, 1
66+
store i32 %conv14.1.i.5, ptr getelementptr inbounds nuw (i8, ptr @c, i64 60), align 4
67+
%arrayidx12.promoted.5.i.5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 220), align 4
68+
%conv14.5.i.5 = xor i32 %arrayidx12.promoted.5.i.5, 1
69+
store i32 %conv14.5.i.5, ptr getelementptr inbounds nuw (i8, ptr @c, i64 220), align 4
70+
%arrayidx12.promoted.6.i.5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 260), align 4
71+
%conv14.6.i.5 = xor i32 %arrayidx12.promoted.6.i.5, 1
72+
%0 = or i32 %arrayidx12.promoted.6.i.4, %arrayidx12.promoted.1.i.5
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%or.1.5.i.5 = or i32 %0, %arrayidx12.promoted.5.i.5
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%or.1.6.i.5 = or i32 %or.1.5.i.5, %arrayidx12.promoted.6.i.5
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store i32 %conv14.6.i.5, ptr getelementptr inbounds nuw (i8, ptr @c, i64 260), align 4
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store i32 %or.1.6.i.5, ptr @j.0, align 4
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%arrayidx12.promoted.1.i.6 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 64), align 4
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%conv14.1.i.6 = xor i32 %arrayidx12.promoted.1.i.6, 1
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store i32 %conv14.1.i.6, ptr getelementptr inbounds nuw (i8, ptr @c, i64 64), align 4
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%arrayidx12.promoted.5.i.6 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 224), align 4
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%conv14.5.i.6 = xor i32 %arrayidx12.promoted.5.i.6, 1
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store i32 %conv14.5.i.6, ptr getelementptr inbounds nuw (i8, ptr @c, i64 224), align 4
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%arrayidx12.promoted.6.i.6 = load i32, ptr getelementptr inbounds nuw (i8, ptr @c, i64 264), align 4
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%conv14.6.i.6 = xor i32 %arrayidx12.promoted.6.i.6, 1
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store i32 %conv14.6.i.6, ptr getelementptr inbounds nuw (i8, ptr @c, i64 264), align 4
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ret void
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}

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