[MIPS]Optimize (signext (xor (trunc X, i32), -1), i64) to (xor (X, -1))

The constant operand of the XOR is an i32, which makes the two operands
being truncated to i32, and sign extended to i64 afterwards. Since both
of the i32 operands are sign extended to i64 before performing the
TRUNCATE operation, we just remove the unnecessary TRUNCATE and
SIGN_EXTEND.

Fix #99783

Author: anbbna

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -517,7 +517,8 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
   setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND,
-                       ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL});
+                       ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL,
+                       ISD::SIGN_EXTEND});
 
   if (Subtarget.isGP64bit())
     setMaxAtomicSizeInBitsSupported(64);
@@ -1210,6 +1211,41 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
                      DAG.getConstant(SMSize, DL, MVT::i32));
 }
 
+static SDValue performSignExtendCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI,const MipsSubtarget &Subtarget) {
+  if (DCI.Level != AfterLegalizeDAG) {
+    return SDValue();
+  }
+
+  if (!Subtarget.isGP64bit()) {
+    return SDValue();
+  }
+
+  SDValue N0 = N->getOperand(0);
+  EVT VT = N->getValueType(0);
+
+  if (N0->getNumOperands() != 2) {
+    return SDValue();
+  }
+
+  // Pattern match XOR.
+  //  $dst = (sign_extend (xor (trunc $src, i32), -1), i64)
+  //  => $dst = (xor ($src, -1), i64)
+  if (N0.getOpcode() == ISD::XOR &&
+      N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
+      N0.getOperand(1).getOpcode() == ISD::Constant) {
+    SDValue TruncateOperand = N0.getOperand(0).getOperand(0);
+    if (VT == MVT::i64 && VT == TruncateOperand->getValueType(0)) {
+      APInt MinusOne(32, -1, true);
+      if (N0.getConstantOperandAPInt(1) == MinusOne) {
+        return DAG.getNode(ISD::XOR, SDLoc(N0), VT, TruncateOperand,
+                           DAG.getTargetConstant(-1, SDLoc(N0), VT));
+      }
+    }
+  }
+
+  return SDValue();
+}
+
 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
   const {
   SelectionDAG &DAG = DCI.DAG;
@@ -1235,6 +1271,8 @@ SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
     return performSHLCombine(N, DAG, DCI, Subtarget);
   case ISD::SUB:
     return performSUBCombine(N, DAG, DCI, Subtarget);
+  case ISD::SIGN_EXTEND:
+    return performSignExtendCombine(N, DAG, DCI, Subtarget);
   }
 
   return SDValue();