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michaelmaitlandmichaelmaitland
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[RISCV][GISEL] instruction-select vmclr
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4 files changed

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4 files changed

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‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,8 @@ class RISCVInstructionSelector : public InstructionSelector {
100100
return selectSHXADD_UWOp(Root, ShAmt);
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}
102102

103+
ComplexRendererFns selectVLOp(MachineOperand &Root) const;
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103105
// Custom renderers for tablegen
104106
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
105107
int OpIdx) const;
@@ -376,6 +378,26 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
376378
return std::nullopt;
377379
}
378380

381+
InstructionSelector::ComplexRendererFns
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RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
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MachineRegisterInfo &MRI =
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Root.getParent()->getParent()->getParent()->getRegInfo();
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assert(Root.isReg() && "Expected operand to be a Register");
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MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
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if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
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RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
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// If the operand is a G_CONSTANT with value VLMaxSentinel, convert it
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// to an immediate with value VLMaxSentinel. This is recognized specially by
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// the vsetvli insertion pass.
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return {
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{[=](MachineInstrBuilder &MIB) { MIB.addImm(RISCV::VLMaxSentinel); }}};
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// FIXME: Implement non-VLMAX case. ISEL will fail gracefully by returning
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// like this for now.
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return std::nullopt;
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}
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379401
InstructionSelector::ComplexRendererFns
380402
RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
381403
if (!Root.isReg())

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,11 @@ def GIAddrRegImm :
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GIComplexOperandMatcher<s32, "selectAddrRegImm">,
5151
GIComplexPatternEquiv<AddrRegImm>;
5252

53+
def GIVLOpS32 : GIComplexOperandMatcher<s32, "selectVLOp">,
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GIComplexPatternEquiv<VLOp>;
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def GIVLOpS64 : GIComplexOperandMatcher<s64, "selectVLOp">,
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GIComplexPatternEquiv<VLOp>;
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5358
// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
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// checking happy so we can use ADDIW which expects an XLen immediate.
5560
def as_i64imm : SDNodeXForm<imm, [{

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,124 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: splat_zero_nxv1i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv1i1
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; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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21+
...
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---
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name: splat_zero_nxv2i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv2i1
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; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
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%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 2 x s1>)
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PseudoRET implicit $v0
37+
38+
...
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---
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name: splat_zero_nxv4i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
45+
bb.1:
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; CHECK-LABEL: name: splat_zero_nxv4i1
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; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
51+
%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 4 x s1>)
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PseudoRET implicit $v0
54+
55+
...
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---
57+
name: splat_zero_nxv8i1
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legalized: true
59+
regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv8i1
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; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
68+
%1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 8 x s1>)
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PseudoRET implicit $v0
71+
72+
...
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---
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name: splat_zero_nxv16i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv16i1
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; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
85+
%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 16 x s1>)
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PseudoRET implicit $v0
88+
89+
...
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---
91+
name: splat_zero_nxv32i1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
97+
; CHECK-LABEL: name: splat_zero_nxv32i1
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; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
100+
; CHECK-NEXT: PseudoRET implicit $v0
101+
%0:gprb(s32) = G_CONSTANT i32 -1
102+
%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
103+
$v0 = COPY %1(<vscale x 32 x s1>)
104+
PseudoRET implicit $v0
105+
106+
...
107+
---
108+
name: splat_zero_nxv64i1
109+
legalized: true
110+
regBankSelected: true
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tracksRegLiveness: true
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body: |
113+
bb.1:
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; CHECK-LABEL: name: splat_zero_nxv64i1
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; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:gprb(s32) = G_CONSTANT i32 -1
119+
%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 64 x s1>)
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PseudoRET implicit $v0
122+
123+
...
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‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,124 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
5+
---
6+
name: splat_zero_nxv1i1
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.1:
12+
; CHECK-LABEL: name: splat_zero_nxv1i1
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; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
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; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
15+
; CHECK-NEXT: PseudoRET implicit $v0
16+
%0:gprb(s64) = G_CONSTANT i64 -1
17+
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
18+
$v0 = COPY %1(<vscale x 1 x s1>)
19+
PseudoRET implicit $v0
20+
21+
...
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---
23+
name: splat_zero_nxv2i1
24+
legalized: true
25+
regBankSelected: true
26+
tracksRegLiveness: true
27+
body: |
28+
bb.1:
29+
; CHECK-LABEL: name: splat_zero_nxv2i1
30+
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
31+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
32+
; CHECK-NEXT: PseudoRET implicit $v0
33+
%0:gprb(s64) = G_CONSTANT i64 -1
34+
%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
35+
$v0 = COPY %1(<vscale x 2 x s1>)
36+
PseudoRET implicit $v0
37+
38+
...
39+
---
40+
name: splat_zero_nxv4i1
41+
legalized: true
42+
regBankSelected: true
43+
tracksRegLiveness: true
44+
body: |
45+
bb.1:
46+
; CHECK-LABEL: name: splat_zero_nxv4i1
47+
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
48+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
49+
; CHECK-NEXT: PseudoRET implicit $v0
50+
%0:gprb(s64) = G_CONSTANT i64 -1
51+
%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
52+
$v0 = COPY %1(<vscale x 4 x s1>)
53+
PseudoRET implicit $v0
54+
55+
...
56+
---
57+
name: splat_zero_nxv8i1
58+
legalized: true
59+
regBankSelected: true
60+
tracksRegLiveness: true
61+
body: |
62+
bb.1:
63+
; CHECK-LABEL: name: splat_zero_nxv8i1
64+
; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
65+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
66+
; CHECK-NEXT: PseudoRET implicit $v0
67+
%0:gprb(s64) = G_CONSTANT i64 -1
68+
%1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)
69+
$v0 = COPY %1(<vscale x 8 x s1>)
70+
PseudoRET implicit $v0
71+
72+
...
73+
---
74+
name: splat_zero_nxv16i1
75+
legalized: true
76+
regBankSelected: true
77+
tracksRegLiveness: true
78+
body: |
79+
bb.1:
80+
; CHECK-LABEL: name: splat_zero_nxv16i1
81+
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
82+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
83+
; CHECK-NEXT: PseudoRET implicit $v0
84+
%0:gprb(s64) = G_CONSTANT i64 -1
85+
%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
86+
$v0 = COPY %1(<vscale x 16 x s1>)
87+
PseudoRET implicit $v0
88+
89+
...
90+
---
91+
name: splat_zero_nxv32i1
92+
legalized: true
93+
regBankSelected: true
94+
tracksRegLiveness: true
95+
body: |
96+
bb.1:
97+
; CHECK-LABEL: name: splat_zero_nxv32i1
98+
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
99+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
100+
; CHECK-NEXT: PseudoRET implicit $v0
101+
%0:gprb(s64) = G_CONSTANT i64 -1
102+
%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
103+
$v0 = COPY %1(<vscale x 32 x s1>)
104+
PseudoRET implicit $v0
105+
106+
...
107+
---
108+
name: splat_zero_nxv64i1
109+
legalized: true
110+
regBankSelected: true
111+
tracksRegLiveness: true
112+
body: |
113+
bb.1:
114+
; CHECK-LABEL: name: splat_zero_nxv64i1
115+
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
116+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
117+
; CHECK-NEXT: PseudoRET implicit $v0
118+
%0:gprb(s64) = G_CONSTANT i64 -1
119+
%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
120+
$v0 = COPY %1(<vscale x 64 x s1>)
121+
PseudoRET implicit $v0
122+
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...
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