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Revert "[InlineSpiller] Check rematerialization before folding operand (#134015)"
This reverts commit b25b51e. The InlineSpiller should conceptually not be aware of the allocation order.
1 parent b0f2bfc commit 0257a0c

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10 files changed

+98
-185
lines changed

10 files changed

+98
-185
lines changed

‎llvm/include/llvm/CodeGen/Spiller.h‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@ class LiveIntervals;
2323
class LiveStacks;
2424
class MachineDominatorTree;
2525
class MachineBlockFrequencyInfo;
26-
class AllocationOrder;
2726

2827
/// Spiller interface.
2928
///
@@ -36,7 +35,7 @@ class Spiller {
3635
virtual ~Spiller() = 0;
3736

3837
/// spill - Spill the LRE.getParent() live interval.
39-
virtual void spill(LiveRangeEdit &LRE, AllocationOrder *Order = nullptr) = 0;
38+
virtual void spill(LiveRangeEdit &LRE) = 0;
4039

4140
/// Return the registers that were spilled.
4241
virtual ArrayRef<Register> getSpilledRegs() = 0;
@@ -59,8 +58,7 @@ class Spiller {
5958
/// of deferring though VirtRegMap.
6059
Spiller *createInlineSpiller(const Spiller::RequiredAnalyses &Analyses,
6160
MachineFunction &MF, VirtRegMap &VRM,
62-
VirtRegAuxInfo &VRAI,
63-
LiveRegMatrix *Matrix = nullptr);
61+
VirtRegAuxInfo &VRAI);
6462

6563
} // end namespace llvm
6664

‎llvm/lib/CodeGen/InlineSpiller.cpp‎

Lines changed: 7 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,6 @@
1111
//
1212
//===----------------------------------------------------------------------===//
1313

14-
#include "AllocationOrder.h"
1514
#include "SplitKit.h"
1615
#include "llvm/ADT/ArrayRef.h"
1716
#include "llvm/ADT/DenseMap.h"
@@ -24,7 +23,6 @@
2423
#include "llvm/CodeGen/LiveInterval.h"
2524
#include "llvm/CodeGen/LiveIntervals.h"
2625
#include "llvm/CodeGen/LiveRangeEdit.h"
27-
#include "llvm/CodeGen/LiveRegMatrix.h"
2826
#include "llvm/CodeGen/LiveStacks.h"
2927
#include "llvm/CodeGen/MachineBasicBlock.h"
3028
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
@@ -151,14 +149,12 @@ class InlineSpiller : public Spiller {
151149
MachineRegisterInfo &MRI;
152150
const TargetInstrInfo &TII;
153151
const TargetRegisterInfo &TRI;
154-
LiveRegMatrix *Matrix = nullptr;
155152

156153
// Variables that are valid during spill(), but used by multiple methods.
157154
LiveRangeEdit *Edit = nullptr;
158155
LiveInterval *StackInt = nullptr;
159156
int StackSlot;
160157
Register Original;
161-
AllocationOrder *Order = nullptr;
162158

163159
// All registers to spill to StackSlot, including the main register.
164160
SmallVector<Register, 8> RegsToSpill;
@@ -188,13 +184,13 @@ class InlineSpiller : public Spiller {
188184

189185
public:
190186
InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF,
191-
VirtRegMap &VRM, VirtRegAuxInfo &VRAI, LiveRegMatrix *Matrix)
187+
VirtRegMap &VRM, VirtRegAuxInfo &VRAI)
192188
: MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), VRM(VRM),
193189
MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
194-
TRI(*MF.getSubtarget().getRegisterInfo()), Matrix(Matrix),
195-
HSpiller(Analyses, MF, VRM), VRAI(VRAI) {}
190+
TRI(*MF.getSubtarget().getRegisterInfo()), HSpiller(Analyses, MF, VRM),
191+
VRAI(VRAI) {}
196192

197-
void spill(LiveRangeEdit &, AllocationOrder *Order = nullptr) override;
193+
void spill(LiveRangeEdit &) override;
198194
ArrayRef<Register> getSpilledRegs() override { return RegsToSpill; }
199195
ArrayRef<Register> getReplacedRegs() override { return RegsReplaced; }
200196
void postOptimization() override;
@@ -211,7 +207,6 @@ class InlineSpiller : public Spiller {
211207

212208
void markValueUsed(LiveInterval*, VNInfo*);
213209
bool canGuaranteeAssignmentAfterRemat(Register VReg, MachineInstr &MI);
214-
bool hasPhysRegAvailable(const MachineInstr &MI);
215210
bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
216211
void reMaterializeAll();
217212

@@ -234,8 +229,8 @@ void Spiller::anchor() {}
234229
Spiller *
235230
llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses,
236231
MachineFunction &MF, VirtRegMap &VRM,
237-
VirtRegAuxInfo &VRAI, LiveRegMatrix *Matrix) {
238-
return new InlineSpiller(Analyses, MF, VRM, VRAI, Matrix);
232+
VirtRegAuxInfo &VRAI) {
233+
return new InlineSpiller(Analyses, MF, VRM, VRAI);
239234
}
240235

241236
//===----------------------------------------------------------------------===//
@@ -620,23 +615,6 @@ bool InlineSpiller::canGuaranteeAssignmentAfterRemat(Register VReg,
620615
return true;
621616
}
622617

623-
/// hasPhysRegAvailable - Check if there is an available physical register for
624-
/// rematerialization.
625-
bool InlineSpiller::hasPhysRegAvailable(const MachineInstr &MI) {
626-
if (!Order || !Matrix)
627-
return false;
628-
629-
SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
630-
SlotIndex PrevIdx = UseIdx.getPrevSlot();
631-
632-
for (MCPhysReg PhysReg : *Order) {
633-
if (!Matrix->checkInterference(PrevIdx, UseIdx, PhysReg))
634-
return true;
635-
}
636-
637-
return false;
638-
}
639-
640618
/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
641619
bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
642620
// Analyze instruction
@@ -683,7 +661,6 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
683661
// Before rematerializing into a register for a single instruction, try to
684662
// fold a load into the instruction. That avoids allocating a new register.
685663
if (RM.OrigMI->canFoldAsLoad() &&
686-
(RM.OrigMI->mayLoad() || !hasPhysRegAvailable(MI)) &&
687664
foldMemoryOperand(Ops, RM.OrigMI)) {
688665
Edit->markRematerialized(RM.ParentVNI);
689666
++NumFoldedLoads;
@@ -1305,10 +1282,9 @@ void InlineSpiller::spillAll() {
13051282
Edit->eraseVirtReg(Reg);
13061283
}
13071284

1308-
void InlineSpiller::spill(LiveRangeEdit &edit, AllocationOrder *order) {
1285+
void InlineSpiller::spill(LiveRangeEdit &edit) {
13091286
++NumSpilledRanges;
13101287
Edit = &edit;
1311-
Order = order;
13121288
assert(!edit.getReg().isStack() && "Trying to spill a stack slot.");
13131289
// Share a stack slot among all descendants of Original.
13141290
Original = VRM.getOriginal(edit.getReg());

‎llvm/lib/CodeGen/RegAllocGreedy.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2664,7 +2664,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
26642664
NamedRegionTimer T("spill", "Spiller", TimerGroupName,
26652665
TimerGroupDescription, TimePassesIsEnabled);
26662666
LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2667-
spiller().spill(LRE, &Order);
2667+
spiller().spill(LRE);
26682668
ExtraInfo->setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
26692669

26702670
// Tell LiveDebugVariables about the new ranges. Ranges not being covered by
@@ -2908,8 +2908,8 @@ bool RAGreedy::run(MachineFunction &mf) {
29082908
PriorityAdvisor = PriorityProvider->getAdvisor(*MF, *this, *Indexes);
29092909

29102910
VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI);
2911-
SpillerInstance.reset(createInlineSpiller({*LIS, *LSS, *DomTree, *MBFI}, *MF,
2912-
*VRM, *VRAI, Matrix));
2911+
SpillerInstance.reset(
2912+
createInlineSpiller({*LIS, *LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
29132913

29142914
VRAI->calculateSpillWeightsAndHints();
29152915

‎llvm/test/CodeGen/X86/avx-cmp.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,7 @@ define void @render(double %a0) nounwind {
4343
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
4444
; CHECK-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
4545
; CHECK-NEXT: # xmm0 = mem[0],zero
46-
; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
47-
; CHECK-NEXT: vucomisd %xmm1, %xmm0
46+
; CHECK-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
4847
; CHECK-NEXT: jne .LBB2_4
4948
; CHECK-NEXT: jnp .LBB2_2
5049
; CHECK-NEXT: .LBB2_4: # %if.then

‎llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,8 +111,7 @@ define <4 x i32> @eq_or_eq_ult_2_fail_multiuse(<4 x i32> %x) {
111111
; AVX512-NEXT: callq use.v4.i32@PLT
112112
; AVX512-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
113113
; AVX512-NEXT: vpcmpltud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
114-
; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
115-
; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
114+
; AVX512-NEXT: vmovdqa32 {{.*#+}} xmm0 {%k1} {z} = [4294967295,4294967295,4294967295,4294967295]
116115
; AVX512-NEXT: addq $24, %rsp
117116
; AVX512-NEXT: .cfi_def_cfa_offset 8
118117
; AVX512-NEXT: retq

‎llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -195,8 +195,7 @@ define <8 x half> @fmul_pow2_8xhalf(<8 x i16> %i) {
195195
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
196196
; CHECK-SSE-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
197197
; CHECK-SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
198-
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
199-
; CHECK-SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
198+
; CHECK-SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7]
200199
; CHECK-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
201200
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
202201
; CHECK-SSE-NEXT: callq __extendhfsf2@PLT

‎llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll‎

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -567,8 +567,7 @@ define <8 x i1> @test_signed_v8i1_v8f16(<8 x half> %f) nounwind {
567567
; CHECK-NEXT: cvttss2si %xmm0, %eax
568568
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
569569
; CHECK-NEXT: cmovbl %ebp, %eax
570-
; CHECK-NEXT: xorps %xmm1, %xmm1
571-
; CHECK-NEXT: ucomiss %xmm1, %xmm0
570+
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
572571
; CHECK-NEXT: cmoval %ebx, %eax
573572
; CHECK-NEXT: ucomiss %xmm0, %xmm0
574573
; CHECK-NEXT: cmovpl %ebx, %eax
@@ -582,8 +581,7 @@ define <8 x i1> @test_signed_v8i1_v8f16(<8 x half> %f) nounwind {
582581
; CHECK-NEXT: cvttss2si %xmm0, %eax
583582
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
584583
; CHECK-NEXT: cmovbl %ebp, %eax
585-
; CHECK-NEXT: xorps %xmm1, %xmm1
586-
; CHECK-NEXT: ucomiss %xmm1, %xmm0
584+
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
587585
; CHECK-NEXT: cmoval %ebx, %eax
588586
; CHECK-NEXT: ucomiss %xmm0, %xmm0
589587
; CHECK-NEXT: cmovpl %ebx, %eax
@@ -595,8 +593,7 @@ define <8 x i1> @test_signed_v8i1_v8f16(<8 x half> %f) nounwind {
595593
; CHECK-NEXT: cvttss2si %xmm0, %eax
596594
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
597595
; CHECK-NEXT: cmovbl %ebp, %eax
598-
; CHECK-NEXT: xorps %xmm1, %xmm1
599-
; CHECK-NEXT: ucomiss %xmm1, %xmm0
596+
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
600597
; CHECK-NEXT: cmoval %ebx, %eax
601598
; CHECK-NEXT: ucomiss %xmm0, %xmm0
602599
; CHECK-NEXT: cmovpl %ebx, %eax
@@ -612,8 +609,7 @@ define <8 x i1> @test_signed_v8i1_v8f16(<8 x half> %f) nounwind {
612609
; CHECK-NEXT: cvttss2si %xmm0, %eax
613610
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
614611
; CHECK-NEXT: cmovbl %ebp, %eax
615-
; CHECK-NEXT: xorps %xmm1, %xmm1
616-
; CHECK-NEXT: ucomiss %xmm1, %xmm0
612+
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
617613
; CHECK-NEXT: cmoval %ebx, %eax
618614
; CHECK-NEXT: ucomiss %xmm0, %xmm0
619615
; CHECK-NEXT: cmovpl %ebx, %eax
@@ -625,8 +621,7 @@ define <8 x i1> @test_signed_v8i1_v8f16(<8 x half> %f) nounwind {
625621
; CHECK-NEXT: cvttss2si %xmm0, %eax
626622
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
627623
; CHECK-NEXT: cmovbl %ebp, %eax
628-
; CHECK-NEXT: xorps %xmm1, %xmm1
629-
; CHECK-NEXT: ucomiss %xmm1, %xmm0
624+
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
630625
; CHECK-NEXT: cmoval %ebx, %eax
631626
; CHECK-NEXT: ucomiss %xmm0, %xmm0
632627
; CHECK-NEXT: cmovpl %ebx, %eax
@@ -639,8 +634,7 @@ define <8 x i1> @test_signed_v8i1_v8f16(<8 x half> %f) nounwind {
639634
; CHECK-NEXT: cvttss2si %xmm0, %eax
640635
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
641636
; CHECK-NEXT: cmovbl %ebp, %eax
642-
; CHECK-NEXT: xorps %xmm1, %xmm1
643-
; CHECK-NEXT: ucomiss %xmm1, %xmm0
637+
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
644638
; CHECK-NEXT: cmoval %ebx, %eax
645639
; CHECK-NEXT: ucomiss %xmm0, %xmm0
646640
; CHECK-NEXT: cmovpl %ebx, %eax
@@ -652,8 +646,7 @@ define <8 x i1> @test_signed_v8i1_v8f16(<8 x half> %f) nounwind {
652646
; CHECK-NEXT: cvttss2si %xmm0, %eax
653647
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
654648
; CHECK-NEXT: cmovbl %ebp, %eax
655-
; CHECK-NEXT: xorps %xmm1, %xmm1
656-
; CHECK-NEXT: ucomiss %xmm1, %xmm0
649+
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
657650
; CHECK-NEXT: cmoval %ebx, %eax
658651
; CHECK-NEXT: ucomiss %xmm0, %xmm0
659652
; CHECK-NEXT: cmovpl %ebx, %eax

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