use SignExtend64<6> instead of APInt

realqhc · realqhc · commit 025a4f9eeceb · 2025-02-14T17:35:55.000+11:00
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20329,7 +20329,7 @@ emitCV_SHUFFLE_SCI_B(MachineInstr &MI, MachineBasicBlock *MBB,
   const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
   BuildMI(*MBB, MI, DL, TII.get(Opcodes[Imm >> 6]), DstReg)
       .addReg(SrcReg)
-      .addImm(APInt(6, Imm, true).getSExtValue());
+      .addImm(SignExtend64<6>(Imm));
   MI.eraseFromParent();
   return MBB;
 }

Original file line number	Diff line number	Diff line change
`@@ -20329,7 +20329,7 @@ emitCV_SHUFFLE_SCI_B(MachineInstr &MI, MachineBasicBlock *MBB,`
`20329`	`20329`	`const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();`
`20330`	`20330`	`BuildMI(*MBB, MI, DL, TII.get(Opcodes[Imm >> 6]), DstReg)`
`20331`	`20331`	`.addReg(SrcReg)`
`20332`		`- .addImm(APInt(6, Imm, true).getSExtValue());`
	`20332`	`+ .addImm(SignExtend64<6>(Imm));`
`20333`	`20333`	`MI.eraseFromParent();`
`20334`	`20334`	`return MBB;`
`20335`	`20335`	`}`