reorder the lower shuffle opertation

Author: tangaac

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

@@ -1383,11 +1383,6 @@ static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
     /* V2 = V1; */
   }
 
-  if (VT.SimpleTy == MVT::v2i64 || VT.SimpleTy == MVT::v2f64) {
-    if ((Result = lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG)))
-      return Result;
-  }
-
   // It is recommended not to change the pattern comparison order for better
   // performance.
   if ((Result = lowerVECTOR_SHUFFLE_VPACKEV(DL, Mask, VT, V1, V2, DAG)))
@@ -1402,6 +1397,9 @@ static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
     return Result;
   if ((Result = lowerVECTOR_SHUFFLE_VPICKOD(DL, Mask, VT, V1, V2, DAG)))
     return Result;
+  if ((VT.SimpleTy == MVT::v2i64 || VT.SimpleTy == MVT::v2f64) &&
+      (Result = lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG)))
+    return Result;
   if ((Result = lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(DL, Mask, VT, V1, V2, DAG,
                                                      Zeroable)))
     return Result;
@@ -1827,11 +1825,6 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
     /* V2 = V1; */
   }
 
-  if (VT.SimpleTy == MVT::v4i64 || VT.SimpleTy == MVT::v4f64) {
-    if ((Result = lowerVECTOR_SHUFFLE_XVSHUF4I(DL, NewMask, VT, V1, V2, DAG)))
-      return Result;
-  }
-
   // It is recommended not to change the pattern comparison order for better
   // performance.
   if ((Result = lowerVECTOR_SHUFFLE_XVPACKEV(DL, NewMask, VT, V1, V2, DAG)))
@@ -1846,6 +1839,9 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
     return Result;
   if ((Result = lowerVECTOR_SHUFFLE_XVPICKOD(DL, NewMask, VT, V1, V2, DAG)))
     return Result;
+  if ((VT.SimpleTy == MVT::v4i64 || VT.SimpleTy == MVT::v4f64) &&
+      (Result = lowerVECTOR_SHUFFLE_XVSHUF4I(DL, NewMask, VT, V1, V2, DAG)))
+    return Result;
   if ((Result =
            lowerVECTOR_SHUFFLEAsShift(DL, NewMask, VT, V1, V2, DAG, Zeroable)))
     return Result;

llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll

@@ -35,7 +35,7 @@ define <4 x i32> @shufflevector_pack_ev_v4i32(<4 x i32> %a, <4 x i32> %b) {
 define <2 x i64> @shufflevector_pack_ev_v2i64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: shufflevector_pack_ev_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vshuf4i.d $vr0, $vr1, 8
+; CHECK-NEXT:    vpackev.d $vr0, $vr1, $vr0
 ; CHECK-NEXT:    ret
     %c = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
     ret <2 x i64> %c
@@ -55,7 +55,7 @@ define <4 x float> @shufflevector_pack_ev_v4f32(<4 x float> %a, <4 x float> %b)
 define <2 x double> @shufflevector_pack_ev_v2f64(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: shufflevector_pack_ev_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vshuf4i.d $vr0, $vr1, 8
+; CHECK-NEXT:    vpackev.d $vr0, $vr1, $vr0
 ; CHECK-NEXT:    ret
     %c = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
     ret <2 x double> %c
@@ -95,7 +95,7 @@ define <4 x i32> @shufflevector_pack_od_v4i32(<4 x i32> %a, <4 x i32> %b) {
 define <2 x i64> @shufflodector_pack_od_v2i64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: shufflodector_pack_od_v2i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vshuf4i.d $vr0, $vr1, 13
+; CHECK-NEXT:    vpackod.d $vr0, $vr1, $vr0
 ; CHECK-NEXT:    ret
     %c = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
     ret <2 x i64> %c
@@ -115,7 +115,7 @@ define <4 x float> @shufflodector_pack_od_v4f32(<4 x float> %a, <4 x float> %b)
 define <2 x double> @shufflodector_pack_od_v2f64(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: shufflodector_pack_od_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vshuf4i.d $vr0, $vr1, 13
+; CHECK-NEXT:    vpackod.d $vr0, $vr1, $vr0
 ; CHECK-NEXT:    ret
     %c = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
     ret <2 x double> %c

llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll

@@ -230,7 +230,7 @@ define <2 x i64> @shuffle_2i64_vbsll_v_8(<2 x i64> %a) nounwind {
 ; CHECK-LABEL: shuffle_2i64_vbsll_v_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vrepli.b $vr1, 0
-; CHECK-NEXT:    vshuf4i.d $vr0, $vr1, 2
+; CHECK-NEXT:    vpackev.d $vr0, $vr0, $vr1
 ; CHECK-NEXT:    ret
   %shuffle = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> <i32 2, i32 0>
   ret <2 x i64> %shuffle