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[RISCV] Add tests for legalization of <N x i128> and <N x i256> shuffles
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Lines changed: 234 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1141,3 +1141,237 @@ define <16 x i32> @shuffle_disjoint_lanes_one_splat(i32 %v, <16 x i32> %w) {
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%out = shufflevector <16 x i32> %splat, <16 x i32> %w, <16 x i32> <i32 11, i32 15, i32 7, i32 3, i32 26, i32 30, i32 22, i32 18, i32 9, i32 13, i32 5, i32 1, i32 24, i32 28, i32 20, i32 16>
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ret <16 x i32> %out
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}
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define <4 x i128> @shuffle_i128(<4 x i128> %a) {
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; RV32-LABEL: shuffle_i128:
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; RV32: # %bb.0:
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; RV32-NEXT: lw a2, 0(a1)
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; RV32-NEXT: lw a3, 4(a1)
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; RV32-NEXT: lw a4, 8(a1)
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; RV32-NEXT: lw a5, 12(a1)
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; RV32-NEXT: lw a6, 48(a1)
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; RV32-NEXT: lw a7, 52(a1)
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; RV32-NEXT: lw t0, 56(a1)
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; RV32-NEXT: lw t1, 60(a1)
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; RV32-NEXT: lw t2, 32(a1)
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; RV32-NEXT: lw t3, 36(a1)
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; RV32-NEXT: lw t4, 40(a1)
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; RV32-NEXT: lw a1, 44(a1)
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; RV32-NEXT: sw t2, 48(a0)
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; RV32-NEXT: sw t3, 52(a0)
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; RV32-NEXT: sw t4, 56(a0)
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; RV32-NEXT: sw a1, 60(a0)
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; RV32-NEXT: sw a6, 32(a0)
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; RV32-NEXT: sw a7, 36(a0)
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; RV32-NEXT: sw t0, 40(a0)
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; RV32-NEXT: sw t1, 44(a0)
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; RV32-NEXT: sw a2, 16(a0)
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; RV32-NEXT: sw a3, 20(a0)
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; RV32-NEXT: sw a4, 24(a0)
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; RV32-NEXT: sw a5, 28(a0)
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; RV32-NEXT: sw a2, 0(a0)
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; RV32-NEXT: sw a3, 4(a0)
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; RV32-NEXT: sw a4, 8(a0)
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; RV32-NEXT: sw a5, 12(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: shuffle_i128:
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; RV64: # %bb.0:
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; RV64-NEXT: ld a2, 48(a1)
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; RV64-NEXT: ld a3, 56(a1)
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; RV64-NEXT: ld a4, 0(a1)
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; RV64-NEXT: ld a5, 8(a1)
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; RV64-NEXT: ld a6, 32(a1)
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; RV64-NEXT: ld a1, 40(a1)
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; RV64-NEXT: sd a2, 32(a0)
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; RV64-NEXT: sd a3, 40(a0)
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; RV64-NEXT: sd a6, 48(a0)
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; RV64-NEXT: sd a1, 56(a0)
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; RV64-NEXT: sd a4, 0(a0)
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; RV64-NEXT: sd a5, 8(a0)
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; RV64-NEXT: sd a4, 16(a0)
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; RV64-NEXT: sd a5, 24(a0)
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; RV64-NEXT: ret
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%res = shufflevector <4 x i128> %a, <4 x i128> poison, <4 x i32> <i32 0, i32 0, i32 3, i32 2>
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ret <4 x i128> %res
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}
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define void @shuffle_i128_ldst(ptr %p) {
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; RV32-LABEL: shuffle_i128_ldst:
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; RV32: # %bb.0:
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; RV32-NEXT: lw a1, 48(a0)
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; RV32-NEXT: lw a2, 52(a0)
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; RV32-NEXT: lw a3, 56(a0)
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; RV32-NEXT: lw a4, 60(a0)
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; RV32-NEXT: lw a5, 0(a0)
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; RV32-NEXT: lw a6, 4(a0)
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; RV32-NEXT: lw a7, 8(a0)
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; RV32-NEXT: lw t0, 12(a0)
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; RV32-NEXT: lw t1, 32(a0)
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; RV32-NEXT: lw t2, 36(a0)
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; RV32-NEXT: lw t3, 40(a0)
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; RV32-NEXT: lw t4, 44(a0)
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; RV32-NEXT: sw t1, 48(a0)
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; RV32-NEXT: sw t2, 52(a0)
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; RV32-NEXT: sw t3, 56(a0)
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; RV32-NEXT: sw t4, 60(a0)
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; RV32-NEXT: sw a5, 16(a0)
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; RV32-NEXT: sw a6, 20(a0)
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; RV32-NEXT: sw a7, 24(a0)
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; RV32-NEXT: sw t0, 28(a0)
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; RV32-NEXT: sw a1, 32(a0)
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; RV32-NEXT: sw a2, 36(a0)
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; RV32-NEXT: sw a3, 40(a0)
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; RV32-NEXT: sw a4, 44(a0)
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; RV32-NEXT: ret
1227+
;
1228+
; RV64-LABEL: shuffle_i128_ldst:
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; RV64: # %bb.0:
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; RV64-NEXT: ld a1, 0(a0)
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; RV64-NEXT: ld a2, 8(a0)
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; RV64-NEXT: ld a3, 32(a0)
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; RV64-NEXT: ld a4, 40(a0)
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; RV64-NEXT: ld a5, 48(a0)
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; RV64-NEXT: ld a6, 56(a0)
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; RV64-NEXT: sd a3, 48(a0)
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; RV64-NEXT: sd a4, 56(a0)
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; RV64-NEXT: sd a1, 16(a0)
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; RV64-NEXT: sd a2, 24(a0)
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; RV64-NEXT: sd a5, 32(a0)
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; RV64-NEXT: sd a6, 40(a0)
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; RV64-NEXT: ret
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%a = load <4 x i128>, ptr %p
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%res = shufflevector <4 x i128> %a, <4 x i128> poison, <4 x i32> <i32 0, i32 0, i32 3, i32 2>
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store <4 x i128> %res, ptr %p
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ret void
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}
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define void @shuffle_i256_ldst(ptr %p) {
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; RV32-LABEL: shuffle_i256_ldst:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -48
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; RV32-NEXT: .cfi_def_cfa_offset 48
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; RV32-NEXT: sw s0, 44(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s1, 40(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s2, 36(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s3, 32(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s4, 28(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s5, 24(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s6, 20(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s7, 16(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s8, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s9, 8(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset s0, -4
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; RV32-NEXT: .cfi_offset s1, -8
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; RV32-NEXT: .cfi_offset s2, -12
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; RV32-NEXT: .cfi_offset s3, -16
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; RV32-NEXT: .cfi_offset s4, -20
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; RV32-NEXT: .cfi_offset s5, -24
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; RV32-NEXT: .cfi_offset s6, -28
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; RV32-NEXT: .cfi_offset s7, -32
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; RV32-NEXT: .cfi_offset s8, -36
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; RV32-NEXT: .cfi_offset s9, -40
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; RV32-NEXT: lw a1, 0(a0)
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; RV32-NEXT: lw a2, 4(a0)
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; RV32-NEXT: lw a3, 8(a0)
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; RV32-NEXT: lw a4, 12(a0)
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; RV32-NEXT: lw a5, 16(a0)
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; RV32-NEXT: lw a6, 20(a0)
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; RV32-NEXT: lw a7, 24(a0)
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; RV32-NEXT: lw t0, 28(a0)
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; RV32-NEXT: lw t1, 96(a0)
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; RV32-NEXT: lw t2, 100(a0)
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; RV32-NEXT: lw t3, 104(a0)
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; RV32-NEXT: lw t4, 108(a0)
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; RV32-NEXT: lw t5, 112(a0)
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; RV32-NEXT: lw t6, 116(a0)
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; RV32-NEXT: lw s0, 120(a0)
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; RV32-NEXT: lw s1, 124(a0)
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; RV32-NEXT: lw s2, 64(a0)
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; RV32-NEXT: lw s3, 68(a0)
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; RV32-NEXT: lw s4, 72(a0)
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; RV32-NEXT: lw s5, 76(a0)
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; RV32-NEXT: lw s6, 80(a0)
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; RV32-NEXT: lw s7, 84(a0)
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; RV32-NEXT: lw s8, 88(a0)
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; RV32-NEXT: lw s9, 92(a0)
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; RV32-NEXT: sw s6, 112(a0)
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; RV32-NEXT: sw s7, 116(a0)
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; RV32-NEXT: sw s8, 120(a0)
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; RV32-NEXT: sw s9, 124(a0)
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; RV32-NEXT: sw s2, 96(a0)
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; RV32-NEXT: sw s3, 100(a0)
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; RV32-NEXT: sw s4, 104(a0)
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; RV32-NEXT: sw s5, 108(a0)
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; RV32-NEXT: sw t5, 80(a0)
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; RV32-NEXT: sw t6, 84(a0)
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; RV32-NEXT: sw s0, 88(a0)
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; RV32-NEXT: sw s1, 92(a0)
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; RV32-NEXT: sw t1, 64(a0)
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; RV32-NEXT: sw t2, 68(a0)
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; RV32-NEXT: sw t3, 72(a0)
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; RV32-NEXT: sw t4, 76(a0)
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; RV32-NEXT: sw a5, 48(a0)
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; RV32-NEXT: sw a6, 52(a0)
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; RV32-NEXT: sw a7, 56(a0)
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; RV32-NEXT: sw t0, 60(a0)
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; RV32-NEXT: sw a1, 32(a0)
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; RV32-NEXT: sw a2, 36(a0)
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; RV32-NEXT: sw a3, 40(a0)
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; RV32-NEXT: sw a4, 44(a0)
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; RV32-NEXT: lw s0, 44(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s2, 36(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s3, 32(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s4, 28(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s5, 24(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s6, 20(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s7, 16(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s8, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s9, 8(sp) # 4-byte Folded Reload
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; RV32-NEXT: .cfi_restore s0
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; RV32-NEXT: .cfi_restore s1
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; RV32-NEXT: .cfi_restore s2
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; RV32-NEXT: .cfi_restore s3
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; RV32-NEXT: .cfi_restore s4
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; RV32-NEXT: .cfi_restore s5
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; RV32-NEXT: .cfi_restore s6
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; RV32-NEXT: .cfi_restore s7
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; RV32-NEXT: .cfi_restore s8
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; RV32-NEXT: .cfi_restore s9
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; RV32-NEXT: addi sp, sp, 48
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; RV32-NEXT: .cfi_def_cfa_offset 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: shuffle_i256_ldst:
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; RV64: # %bb.0:
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; RV64-NEXT: ld a1, 96(a0)
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; RV64-NEXT: ld a2, 104(a0)
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; RV64-NEXT: ld a3, 112(a0)
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; RV64-NEXT: ld a4, 120(a0)
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; RV64-NEXT: ld a5, 0(a0)
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; RV64-NEXT: ld a6, 8(a0)
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; RV64-NEXT: ld a7, 16(a0)
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; RV64-NEXT: ld t0, 24(a0)
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; RV64-NEXT: ld t1, 64(a0)
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; RV64-NEXT: ld t2, 72(a0)
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; RV64-NEXT: ld t3, 80(a0)
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; RV64-NEXT: ld t4, 88(a0)
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; RV64-NEXT: sd t1, 96(a0)
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; RV64-NEXT: sd t2, 104(a0)
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; RV64-NEXT: sd t3, 112(a0)
1363+
; RV64-NEXT: sd t4, 120(a0)
1364+
; RV64-NEXT: sd a5, 32(a0)
1365+
; RV64-NEXT: sd a6, 40(a0)
1366+
; RV64-NEXT: sd a7, 48(a0)
1367+
; RV64-NEXT: sd t0, 56(a0)
1368+
; RV64-NEXT: sd a1, 64(a0)
1369+
; RV64-NEXT: sd a2, 72(a0)
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; RV64-NEXT: sd a3, 80(a0)
1371+
; RV64-NEXT: sd a4, 88(a0)
1372+
; RV64-NEXT: ret
1373+
%a = load <4 x i256>, ptr %p
1374+
%res = shufflevector <4 x i256> %a, <4 x i256> poison, <4 x i32> <i32 0, i32 0, i32 3, i32 2>
1375+
store <4 x i256> %res, ptr %p
1376+
ret void
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}

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