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el-evel-ev
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address review comments
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2 files changed

+15
-55
lines changed

2 files changed

+15
-55
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1300,17 +1300,16 @@ Instruction *InstCombinerImpl::foldICmpWithZero(ICmpInst &Cmp) {
13001300
// will fold to a constant elsewhere.
13011301
}
13021302

1303-
// (X >> C) + ((X & ((1 << C) - 1)) != 0) == 0 -> X == 0
1304-
if (Pred == ICmpInst::ICMP_EQ) {
1303+
// (X >> C) | ((X & ((1 << C) - 1)) != 0) == 0 -> X == 0
1304+
if (ICmpInst::isEquality(Pred)) {
13051305
Value *X;
13061306
const APInt *C1, *C2;
1307-
CmpPredicate PredNE;
13081307
if (match(Cmp.getOperand(0),
1309-
m_OneUse(
1310-
m_Add(m_LShr(m_Value(X), m_APInt(C1)),
1311-
m_ZExt(m_ICmp(PredNE, m_And(m_Deferred(X), m_APInt(C2)),
1312-
m_Zero()))))) &&
1313-
PredNE == CmpInst::ICMP_NE &&
1308+
m_OneUse(m_c_Or(
1309+
m_LShr(m_Value(X), m_APInt(C1)),
1310+
m_ZExt(m_SpecificICmp(ICmpInst::ICMP_NE,
1311+
m_And(m_Deferred(X), m_APInt(C2)),
1312+
m_Zero()))))) &&
13141313
*C2 == APInt::getLowBitsSet(C2->getBitWidth(), C1->getZExtValue()))
13151314
return new ICmpInst(ICmpInst::ICMP_EQ, X,
13161315
ConstantInt::getNullValue(X->getType()));

‎llvm/test/Transforms/InstCombine/ceil-shift.ll‎

Lines changed: 8 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,7 @@
44
define i1 @ceil_shift4(i32 %arg0) {
55
; CHECK-LABEL: define i1 @ceil_shift4(
66
; CHECK-SAME: i32 [[ARG0:%.*]]) {
7-
; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 4
8-
; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
9-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
10-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
11-
; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
12-
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
7+
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
138
; CHECK-NEXT: ret i1 [[TMP1]]
149
;
1510
%quot = lshr i32 %arg0, 4
@@ -24,12 +19,7 @@ define i1 @ceil_shift4(i32 %arg0) {
2419
define i1 @ceil_shift4_add(i32 %arg0) {
2520
; CHECK-LABEL: define i1 @ceil_shift4_add(
2621
; CHECK-SAME: i32 [[ARG0:%.*]]) {
27-
; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 4
28-
; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
29-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
30-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
31-
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
32-
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP1]], 0
22+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[ARG0]], 0
3323
; CHECK-NEXT: ret i1 [[TMP6]]
3424
;
3525
%quot = lshr i32 %arg0, 4
@@ -44,12 +34,7 @@ define i1 @ceil_shift4_add(i32 %arg0) {
4434
define i1 @ceil_shift6(i32 %arg0) {
4535
; CHECK-LABEL: define i1 @ceil_shift6(
4636
; CHECK-SAME: i32 [[ARG0:%.*]]) {
47-
; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 6
48-
; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 63
49-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
50-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
51-
; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
52-
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
37+
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
5338
; CHECK-NEXT: ret i1 [[TMP1]]
5439
;
5540
%quot = lshr i32 %arg0, 6
@@ -64,12 +49,7 @@ define i1 @ceil_shift6(i32 %arg0) {
6449
define i1 @ceil_shift11(i32 %arg0) {
6550
; CHECK-LABEL: define i1 @ceil_shift11(
6651
; CHECK-SAME: i32 [[ARG0:%.*]]) {
67-
; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 11
68-
; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 2047
69-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
70-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
71-
; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
72-
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
52+
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
7353
; CHECK-NEXT: ret i1 [[TMP1]]
7454
;
7555
%quot = lshr i32 %arg0, 11
@@ -99,12 +79,7 @@ define i1 @ceil_shift0(i32 %arg0) {
9979
define i1 @ceil_shift4_comm(i32 %arg0) {
10080
; CHECK-LABEL: define i1 @ceil_shift4_comm(
10181
; CHECK-SAME: i32 [[ARG0:%.*]]) {
102-
; CHECK-NEXT: [[QUOT:%.*]] = lshr i32 [[ARG0]], 4
103-
; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
104-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
105-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
106-
; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[QUOT]], [[ZEXT_HAS_REM]]
107-
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
82+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[ARG0]], 0
10883
; CHECK-NEXT: ret i1 [[TMP6]]
10984
;
11085
%quot = lshr i32 %arg0, 4
@@ -123,11 +98,7 @@ define i1 @ceil_shift4_used_1(i32 %arg0) {
12398
; CHECK-SAME: i32 [[ARG0:%.*]]) {
12499
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
125100
; CHECK-NEXT: call void @use(i32 [[TMP1]])
126-
; CHECK-NEXT: [[REM:%.*]] = and i32 [[ARG0]], 15
127-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne i32 [[REM]], 0
128-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext i1 [[HAS_REM]] to i32
129-
; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or i32 [[TMP1]], [[ZEXT_HAS_REM]]
130-
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[QUOT_OR_REM]], 0
101+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[ARG0]], 0
131102
; CHECK-NEXT: ret i1 [[TMP6]]
132103
;
133104
%quot = lshr i32 %arg0, 4
@@ -165,12 +136,7 @@ define i1 @ceil_shift4_used_5(i32 %arg0) {
165136
define <4 x i1> @ceil_shift4_v4i32(<4 x i32> %arg0) {
166137
; CHECK-LABEL: define <4 x i1> @ceil_shift4_v4i32(
167138
; CHECK-SAME: <4 x i32> [[ARG0:%.*]]) {
168-
; CHECK-NEXT: [[QUOT:%.*]] = lshr <4 x i32> [[ARG0]], splat (i32 16)
169-
; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[ARG0]], splat (i32 65535)
170-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne <4 x i32> [[REM]], zeroinitializer
171-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext <4 x i1> [[HAS_REM]] to <4 x i32>
172-
; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or <4 x i32> [[QUOT]], [[ZEXT_HAS_REM]]
173-
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[QUOT_OR_REM]], zeroinitializer
139+
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[ARG0]], zeroinitializer
174140
; CHECK-NEXT: ret <4 x i1> [[TMP1]]
175141
;
176142
%quot = lshr <4 x i32> %arg0, splat (i32 16)
@@ -185,12 +151,7 @@ define <4 x i1> @ceil_shift4_v4i32(<4 x i32> %arg0) {
185151
define <8 x i1> @ceil_shift4_v8i16(<8 x i16> %arg0) {
186152
; CHECK-LABEL: define <8 x i1> @ceil_shift4_v8i16(
187153
; CHECK-SAME: <8 x i16> [[ARG0:%.*]]) {
188-
; CHECK-NEXT: [[QUOT:%.*]] = lshr <8 x i16> [[ARG0]], splat (i16 4)
189-
; CHECK-NEXT: [[REM:%.*]] = and <8 x i16> [[ARG0]], splat (i16 15)
190-
; CHECK-NEXT: [[HAS_REM:%.*]] = icmp ne <8 x i16> [[REM]], zeroinitializer
191-
; CHECK-NEXT: [[ZEXT_HAS_REM:%.*]] = zext <8 x i1> [[HAS_REM]] to <8 x i16>
192-
; CHECK-NEXT: [[QUOT_OR_REM:%.*]] = or <8 x i16> [[QUOT]], [[ZEXT_HAS_REM]]
193-
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <8 x i16> [[QUOT_OR_REM]], zeroinitializer
154+
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <8 x i16> [[ARG0]], zeroinitializer
194155
; CHECK-NEXT: ret <8 x i1> [[TMP1]]
195156
;
196157
%quot = lshr <8 x i16> %arg0, splat (i16 4)

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