Skip to content

Commit 037a9a7

Browse files
jroelofsjroelofs
authored
[llvm][AArch64] SVE2 is an optional feature in ARMv9.0a (#96007)
... so move it out of the `implied_features` list, and into the `DefaultExts` list.
1 parent 898b8a4 commit 037a9a7

File tree

4 files changed

+33
-14
lines changed

4 files changed

+33
-14
lines changed

‎llvm/docs/ReleaseNotes.rst‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,13 @@ Changes to the AArch64 Backend
118118
in ``standard`` being equal to ``bti+pac-ret+pc`` when ``+pauth-lr``
119119
is passed as part of ``-mcpu=`` options.
120120

121+
* SVE and SVE2 have been moved to the default extensions list for ARMv9.0,
122+
making them optional per the Arm ARM. Existing v9.0+ CPUs in the backend that
123+
support these extensions continue to have these features enabled by default
124+
when specified via ``-march=`` or an ``-mcpu=`` that supports them. The
125+
attribute ``"target-features"="+v9a"`` no longer implies ``"+sve"`` and
126+
``"+sve2"`` respectively.
127+
121128
Changes to the AMDGPU Backend
122129
-----------------------------
123130

‎llvm/lib/Target/AArch64/AArch64Features.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -799,7 +799,7 @@ def HasV8_9aOps : Architecture64<8, 9, "a", "v8.9a",
799799
!listconcat(HasV8_8aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
800800
FeatureRASv2])>;
801801
def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
802-
[HasV8_5aOps, FeatureMEC, FeatureSVE2],
802+
[HasV8_5aOps, FeatureMEC],
803803
!listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,
804804
FeatureSVE2])>;
805805
def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",

‎llvm/lib/Target/AArch64/AArch64Processors.td‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -690,11 +690,13 @@ def ProcessorFeatures {
690690
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
691691
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
692692
FeatureFP16FML,
693-
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
693+
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
694+
FeatureSVE, FeatureSVE2];
694695
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
695696
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
696697
FeatureFP16FML,
697-
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
698+
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
699+
FeatureSVE, FeatureSVE2];
698700
list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
699701
FeatureNEON, FeatureFullFP16, FeatureDotProd,
700702
FeatureRCPC, FeatureSSBS, FeatureRAS,
@@ -726,19 +728,23 @@ def ProcessorFeatures {
726728
FeatureFP16FML, FeatureSVE, FeatureTRBE,
727729
FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
728730
FeaturePerfMon, FeatureMatMulInt8, FeatureSPE,
729-
FeatureSB, FeatureSSBS, FeatureFullFP16, FeaturePAuth, FeaturePredRes, FeatureFlagM];
731+
FeatureSB, FeatureSSBS, FeatureFullFP16, FeaturePAuth, FeaturePredRes, FeatureFlagM,
732+
FeatureSVE2];
730733
list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
731734
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
732735
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
733-
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
736+
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
737+
FeatureSVE, FeatureSVE2];
734738
list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
735739
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
736740
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
737-
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
741+
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
742+
FeatureSVE, FeatureSVE2];
738743
list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
739744
FeatureETE, FeaturePerfMon, FeatureSPE,
740745
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
741-
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS];
746+
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
747+
FeatureSVE, FeatureSVE2];
742748
list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
743749
FeatureFP16FML, FeatureSSBS, FeaturePredRes,
744750
FeatureSB, FeatureRDM, FeatureDotProd,
@@ -771,16 +777,19 @@ def ProcessorFeatures {
771777
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
772778
FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16,
773779
FeatureFP16FML,
774-
FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS];
780+
FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS,
781+
FeatureSVE2];
775782
list<SubtargetFeature> X4 = [HasV9_2aOps,
776783
FeaturePerfMon, FeatureETE, FeatureTRBE,
777784
FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
778785
FeatureFP16FML, FeatureSPE_EEF,
779-
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
786+
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
787+
FeatureSVE, FeatureSVE2];
780788
list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
781789
FeatureETE, FeaturePerfMon, FeatureSPE,
782790
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
783-
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS];
791+
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
792+
FeatureSVE, FeatureSVE2];
784793
list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
785794
FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
786795
FeatureSVE, FeatureComplxNum,
@@ -849,7 +858,8 @@ def ProcessorFeatures {
849858
FeatureFullFP16, FeatureMTE, FeaturePerfMon,
850859
FeatureRandGen, FeatureSPE, FeatureSPE_EEF,
851860
FeatureSVE2BitPerm,
852-
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
861+
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
862+
FeatureSVE, FeatureSVE2];
853863
list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
854864
FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML,
855865
FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
@@ -871,12 +881,14 @@ def ProcessorFeatures {
871881
FeatureFullFP16, FeatureLS64, FeatureMTE,
872882
FeaturePerfMon, FeatureRandGen, FeatureSPE,
873883
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
874-
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
884+
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
885+
FeatureSVE, FeatureSVE2];
875886
list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
876887
FeatureFullFP16, FeatureLS64, FeatureMTE,
877888
FeaturePerfMon, FeatureRandGen, FeatureSPE,
878889
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
879-
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
890+
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
891+
FeatureSVE, FeatureSVE2];
880892
list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
881893
FeatureNEON, FeatureSPE, FeaturePerfMon];
882894
list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,

‎llvm/unittests/TargetParser/TargetParserTest.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2473,7 +2473,7 @@ AArch64ExtensionDependenciesBaseArchTestParams
24732473
{},
24742474
{"v8.1a", "crc", "fp-armv8", "lse", "rdm", "neon"},
24752475
{}},
2476-
{AArch64::ARMV9_5A, {}, {"v9.5a", "sve", "sve2", "mops", "cpa"}, {}},
2476+
{AArch64::ARMV9_5A, {}, {"v9.5a", "mops", "cpa"}, {}},
24772477

24782478
// Positive modifiers
24792479
{AArch64::ARMV8A, {"fp16"}, {"fullfp16"}, {}},

0 commit comments

Comments
 (0)