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[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction (#75582)
R16-R31 was added into GPRs in #70958, This patch supports the encoding/decoding for promoted SHA instruction in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
1 parent c4457e1 commit 037c220

26 files changed

+290
-32
lines changed

‎llvm/lib/Target/X86/X86InstrAsmAlias.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -686,3 +686,11 @@ def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
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def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;
687687
def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
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689+
// Aliases with explicit %xmm0
690+
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
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(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
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def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
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(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
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def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
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(SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>;

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 65 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -6706,31 +6706,31 @@ let Constraints = "$src1 = $dst" in {
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67076707
// FIXME: Is there a better scheduler class for SHA than WriteVecIMul?
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multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
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X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
6710-
def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
6712-
!if(UsesXMM0,
6713-
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
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[!if(UsesXMM0,
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
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T8PS, Sched<[sched]>;
6719-
6720-
def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!if(UsesXMM0,
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!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
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[!if(UsesXMM0,
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(set VR128:$dst, (IntId VR128:$src1,
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(memop addr:$src2), XMM0)),
6728-
(set VR128:$dst, (IntId VR128:$src1,
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(memop addr:$src2))))]>, T8PS,
6730-
Sched<[sched.Folded, sched.ReadAfterFold]>;
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X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> {
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def rr#Suffix : I<Opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!if(UsesXMM0,
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!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
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[!if(UsesXMM0,
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
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T8PS, Sched<[sched]>;
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def rm#Suffix : I<Opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!if(UsesXMM0,
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!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
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[!if(UsesXMM0,
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(set VR128:$dst, (IntId VR128:$src1,
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(memop addr:$src2), XMM0)),
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(set VR128:$dst, (IntId VR128:$src1,
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(memop addr:$src2))))]>, T8PS,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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6733-
let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
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let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
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def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, u8imm:$src3),
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"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -6757,19 +6757,55 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
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67586758
let Uses=[XMM0] in
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defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
6760-
SchedWriteVecIMul.XMM, 1>;
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SchedWriteVecIMul.XMM, "", 1>;
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67626762
defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
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SchedWriteVecIMul.XMM>;
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defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2,
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SchedWriteVecIMul.XMM>;
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}
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6768-
// Aliases with explicit %xmm0
6769-
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
6770-
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
6771-
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
6772-
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
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let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in {
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def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, u8imm:$src3),
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"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst,
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(int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
6774+
(i8 timm:$src3)))]>,
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EVEX_NoCD8, T_MAP4PS, Sched<[SchedWriteVecIMul.XMM]>;
6776+
def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
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"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst,
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(int_x86_sha1rnds4 VR128:$src1,
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(memop addr:$src2),
6782+
(i8 timm:$src3)))]>,
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EVEX_NoCD8, T_MAP4PS,
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Sched<[SchedWriteVecIMul.XMM.Folded,
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SchedWriteVecIMul.XMM.ReadAfterFold]>;
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defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte,
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SchedWriteVecIMul.XMM, "_EVEX">,
6789+
EVEX_NoCD8, T_MAP4PS;
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defm SHA1MSG1 : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1,
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SchedWriteVecIMul.XMM, "_EVEX">,
6792+
EVEX_NoCD8, T_MAP4PS;
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defm SHA1MSG2 : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2,
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SchedWriteVecIMul.XMM, "_EVEX">,
6795+
EVEX_NoCD8, T_MAP4PS;
6796+
6797+
let Uses=[XMM0] in
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defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2,
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SchedWriteVecIMul.XMM, "_EVEX", 1>,
6800+
EVEX_NoCD8, T_MAP4PS;
6801+
6802+
defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1,
6803+
SchedWriteVecIMul.XMM, "_EVEX">,
6804+
EVEX_NoCD8, T_MAP4PS;
6805+
defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2,
6806+
SchedWriteVecIMul.XMM, "_EVEX">,
6807+
EVEX_NoCD8, T_MAP4PS;
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}
67736809

67746810
//===----------------------------------------------------------------------===//
67756811
// AES-NI Instructions

‎llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt

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@@ -0,0 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
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# ATT: sha1msg1 %xmm13, %xmm12
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# INTEL: sha1msg1 xmm12, xmm13
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0x45,0x0f,0x38,0xc9,0xe5
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# ATT: sha1msg1 291(%r28,%r29,4), %xmm12
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# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
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0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt

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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
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# ATT: sha1msg2 %xmm13, %xmm12
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# INTEL: sha1msg2 xmm12, xmm13
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0x45,0x0f,0x38,0xca,0xe5
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# ATT: sha1msg2 291(%r28,%r29,4), %xmm12
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# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
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0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt

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@@ -0,0 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
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# ATT: sha1nexte %xmm13, %xmm12
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# INTEL: sha1nexte xmm12, xmm13
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0x45,0x0f,0x38,0xc8,0xe5
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8+
# ATT: sha1nexte 291(%r28,%r29,4), %xmm12
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# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
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0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt

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@@ -0,0 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
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# ATT: sha1rnds4 $123, %xmm13, %xmm12
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# INTEL: sha1rnds4 xmm12, xmm13, 123
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0x45,0x0f,0x3a,0xcc,0xe5,0x7b
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8+
# ATT: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
10+
0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b

‎llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt

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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
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4+
# ATT: sha256msg1 %xmm13, %xmm12
5+
# INTEL: sha256msg1 xmm12, xmm13
6+
0x45,0x0f,0x38,0xcc,0xe5
7+
8+
# ATT: sha256msg1 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt

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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
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4+
# ATT: sha256msg2 %xmm13, %xmm12
5+
# INTEL: sha256msg2 xmm12, xmm13
6+
0x45,0x0f,0x38,0xcd,0xe5
7+
8+
# ATT: sha256msg2 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
10+
0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt

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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sha256rnds2 %xmm0, %xmm13, %xmm12
5+
# INTEL: sha256rnds2 xmm12, xmm13, xmm0
6+
0x45,0x0f,0x38,0xcb,0xe5
7+
8+
# ATT: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
9+
# INTEL: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
10+
0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/X86/apx/sha1msg1-att.s

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@@ -0,0 +1,9 @@
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sha1msg1 %xmm13, %xmm12
4+
# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
5+
sha1msg1 %xmm13, %xmm12
6+
7+
# CHECK: sha1msg1 291(%r28,%r29,4), %xmm12
8+
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
9+
sha1msg1 291(%r28,%r29,4), %xmm12

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