@@ -68,7 +68,7 @@ AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
6868}
6969
7070unsigned AggressiveAntiDepState::GetGroup (MCRegister Reg) {
71- unsigned Node = GroupNodeIndices[Reg];
71+ unsigned Node = GroupNodeIndices[Reg. id () ];
7272 while (GroupNodes[Node] != Node)
7373 Node = GroupNodes[Node];
7474
@@ -106,14 +106,14 @@ unsigned AggressiveAntiDepState::LeaveGroup(MCRegister Reg) {
106106 // it.
107107 unsigned idx = GroupNodes.size ();
108108 GroupNodes.push_back (idx);
109- GroupNodeIndices[Reg] = idx;
109+ GroupNodeIndices[Reg. id () ] = idx;
110110 return idx;
111111}
112112
113113bool AggressiveAntiDepState::IsLive (MCRegister Reg) {
114114 // KillIndex must be defined and DefIndex not defined for a register
115115 // to be live.
116- return ((KillIndices[Reg] != ~0u ) && (DefIndices[Reg] == ~0u ));
116+ return ((KillIndices[Reg. id () ] != ~0u ) && (DefIndices[Reg. id () ] == ~0u ));
117117}
118118
119119AggressiveAntiDepBreaker::AggressiveAntiDepBreaker (
@@ -154,10 +154,10 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
154154 for (MachineBasicBlock *Succ : BB->successors ())
155155 for (const auto &LI : Succ->liveins ()) {
156156 for (MCRegAliasIterator AI (LI.PhysReg , TRI, true ); AI.isValid (); ++AI) {
157- unsigned Reg = *AI;
157+ MCRegister Reg = *AI;
158158 State->UnionGroups (Reg, 0 );
159- KillIndices[Reg] = BB->size ();
160- DefIndices[Reg] = ~0u ;
159+ KillIndices[Reg. id () ] = BB->size ();
160+ DefIndices[Reg. id () ] = ~0u ;
161161 }
162162 }
163163
@@ -174,8 +174,8 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
174174 for (MCRegAliasIterator AI (Reg, TRI, true ); AI.isValid (); ++AI) {
175175 MCRegister AliasReg = *AI;
176176 State->UnionGroups (AliasReg, 0 );
177- KillIndices[AliasReg] = BB->size ();
178- DefIndices[AliasReg] = ~0u ;
177+ KillIndices[AliasReg. id () ] = BB->size ();
178+ DefIndices[AliasReg. id () ] = ~0u ;
179179 }
180180 }
181181}
@@ -307,8 +307,8 @@ void AggressiveAntiDepBreaker::HandleLastUse(MCRegister Reg, unsigned KillIdx,
307307 }
308308
309309 if (!State->IsLive (Reg)) {
310- KillIndices[Reg] = KillIdx;
311- DefIndices[Reg] = ~0u ;
310+ KillIndices[Reg. id () ] = KillIdx;
311+ DefIndices[Reg. id () ] = ~0u ;
312312 RegRefs.erase (Reg);
313313 State->LeaveGroup (Reg);
314314 LLVM_DEBUG (if (header) {
@@ -651,7 +651,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
651651 LLVM_DEBUG (dbgs () << " " << printReg (NewReg, TRI));
652652
653653 // Check if Reg can be renamed to NewReg.
654- if (!RenameRegisterMap[Reg].test (NewReg)) {
654+ if (!RenameRegisterMap[Reg].test (NewReg. id () )) {
655655 LLVM_DEBUG (dbgs () << " (no rename)" );
656656 goto next_super_reg;
657657 }
@@ -660,15 +660,16 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
660660 // Regs's kill, it's safe to replace Reg with NewReg. We
661661 // must also check all aliases of NewReg, because we can't define a
662662 // register when any sub or super is already live.
663- if (State->IsLive (NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
663+ if (State->IsLive (NewReg) ||
664+ (KillIndices[Reg.id ()] > DefIndices[NewReg.id ()])) {
664665 LLVM_DEBUG (dbgs () << " (live)" );
665666 goto next_super_reg;
666667 } else {
667668 bool found = false ;
668669 for (MCRegAliasIterator AI (NewReg, TRI, false ); AI.isValid (); ++AI) {
669670 MCRegister AliasReg = *AI;
670671 if (State->IsLive (AliasReg) ||
671- (KillIndices[Reg] > DefIndices[AliasReg])) {
672+ (KillIndices[Reg. id () ] > DefIndices[AliasReg. id () ])) {
672673 LLVM_DEBUG (dbgs ()
673674 << " (alias " << printReg (AliasReg, TRI) << " live)" );
674675 found = true ;
@@ -940,15 +941,15 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
940941 // the state as if it were dead.
941942 State->UnionGroups (NewReg, 0 );
942943 RegRefs.erase (NewReg);
943- DefIndices[NewReg] = DefIndices[CurrReg];
944- KillIndices[NewReg] = KillIndices[CurrReg];
944+ DefIndices[NewReg. id () ] = DefIndices[CurrReg. id () ];
945+ KillIndices[NewReg. id () ] = KillIndices[CurrReg. id () ];
945946
946947 State->UnionGroups (CurrReg, 0 );
947948 RegRefs.erase (CurrReg);
948- DefIndices[CurrReg] = KillIndices[CurrReg];
949- KillIndices[CurrReg] = ~0u ;
950- assert (((KillIndices[CurrReg] == ~0u ) !=
951- (DefIndices[CurrReg] == ~0u )) &&
949+ DefIndices[CurrReg. id () ] = KillIndices[CurrReg. id () ];
950+ KillIndices[CurrReg. id () ] = ~0u ;
951+ assert (((KillIndices[CurrReg. id () ] == ~0u ) !=
952+ (DefIndices[CurrReg. id () ] == ~0u )) &&
952953 " Kill and Def maps aren't consistent for AntiDepReg!" );
953954 }
954955
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