release note

Author: el-ev

llvm/docs/ReleaseNotes.md

@@ -186,6 +186,8 @@ Changes to the RISC-V Backend
 * Adds assembler support for the Andes `XAndesperf` (Andes Performance extension).
 * `-mcpu=sifive-p870` was added.
 * Adds assembler support for the Andes `XAndesvpackfph` (Andes Vector Packed FP16 extension).
+* Adds assembler support for the standard `Q` (Quad-Precision Floating Point) 
+  extension.
 
 Changes to the WebAssembly Backend
 ----------------------------------

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -681,9 +681,6 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FSD;
     IsScalableVector = false;
-  } else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) {
-    Opcode = RISCV::FSQ;
-    IsScalableVector = false;
   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VS1R_V;
   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
@@ -776,9 +773,6 @@ void RISCVInstrInfo::loadRegFromStackSlot(
   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FLD;
     IsScalableVector = false;
-  } else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) {
-    Opcode = RISCV::FLQ;
-    IsScalableVector = false;
   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VL1RE8_V;
   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {

llvm/lib/Target/RISCV/RISCVInstrInfoQ.td

@@ -27,15 +27,15 @@ defvar QExtsRV64 = [QExt];
 let Predicates = [HasStdExtQ] in {
   let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
   def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-              (ins GPRMem:$rs1, simm12:$imm12),
-              "flq", "$rd, ${imm12}(${rs1})">;
+                    (ins GPRMem:$rs1, simm12:$imm12), "flq",
+                    "$rd, ${imm12}(${rs1})">;
   // Operands for stores are in the order srcreg, base, offset rather than
   // reflecting the order these fields are specified in the instruction
   // encoding.
   let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
   def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-              (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
-              "fsq", "$rs2, ${imm12}(${rs1})">;
+                    (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
+                    "$rs2, ${imm12}(${rs1})">;
 } // Predicates = [HasStdExtQ]
 
 foreach Ext = QExts in {
@@ -93,11 +93,11 @@ foreach Ext = QExts in {
 
   let mayRaiseFPException = 0 in 
   defm FCVT_Q_W  : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00000, Ext,
-                                     Ext.PrimaryTy, GPR, "fcvt.q.w">;
+                                           Ext.PrimaryTy, GPR, "fcvt.q.w">;
 
   let mayRaiseFPException = 0 in 
   defm FCVT_Q_WU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00001, Ext,
-                                     Ext.PrimaryTy, GPR, "fcvt.q.wu">;
+                                           Ext.PrimaryTy, GPR, "fcvt.q.wu">;
 } // foreach Ext = QExts
 
 foreach Ext = QExtsRV64 in {
@@ -108,12 +108,14 @@ foreach Ext = QExtsRV64 in {
                                      Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>;
 
   let mayRaiseFPException = 0 in 
-  defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext, Ext.PrimaryTy, 
-                                    GPR, "fcvt.q.l", [IsRV64]>;
+  defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext,
+                                          Ext.PrimaryTy, GPR, "fcvt.q.l",
+                                          [IsRV64]>;
 
   let mayRaiseFPException = 0 in 
-  defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext, Ext.PrimaryTy, 
-                                     GPR, "fcvt.q.lu", [IsRV64]>;
+  defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext,
+                                           Ext.PrimaryTy, GPR, "fcvt.q.lu",
+                                           [IsRV64]>;
 } // foreach Ext = QExtsRV64
 
 //===----------------------------------------------------------------------===//
@@ -141,11 +143,3 @@ let Predicates = [HasStdExtQ] in {
   def PseudoFLQ : PseudoFloatLoad<"flq", FPR128>;
   def PseudoFSQ : PseudoStore<"fsq", FPR128>;
 } // Predicates = [HasStdExtQ]
-
-let Predicates = [HasStdExtQ] in {
-/// Loads
-def : LdPat<load, FLQ, f128>;
-
-/// Stores
-def : StPat<store, FSQ, FPR128, f128>;
-} // Predicates = [HasStdExtQ]

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -198,9 +198,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool useLoadStorePairs() const;
   bool useCCMovInsn() const;
   unsigned getFLen() const {
-    if (HasStdExtQ)
-      return 128;
-
     if (HasStdExtD)
       return 64;